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  "@id": "http://lexmachina.com/data/case/88", 
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      "filed_on": "2002-04-26T00:00:00", 
      "id": 13970, 
      "nice_text": "Answer to Amended Complaint by Sandisk Corporation (fnt) (Entered: 04/26/2002)", 
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          "text": "Case 9:02-cv-00058-jH Document 61 F~ed 05/1 5~002 Page 1 of 2\n\n\nUNTTEDSTATESDISTRICTCOURT\nDISTRICT OF TEXAS\nLUFKIN DIVISION 02 ~ `115 P~1 3: ~5\n\nSAMS~G ELECTRONICS CO LTD, \ufffd - ~\n\nPlaintiff, \ufffd\n\ufffd\nV. \ufffd\n\ufffd\nSANDISK CORPORATION, \ufffd\n\ufffd\nDefendant \ufffd CIVIL ACTION NO. 9:02-C V-58\n\ufffd JUDGE HANNAH\n\ufffd JURY\nSANDISK CORPORATION, \ufffd\n\ufffd\nCounterclaimant, \ufffd\n\ufffd\nv. \ufffd\n\ufffd\nSAMSUNG ELECTRONICS CO., LTD., \ufffd\n\ufffd\nCounterdefendant. \ufffd\n\nDEFENDANT SANDISK CORPORATION'S NOTICE OF DISCLOSURE\n\n\nPlease take notice that Defendant SanDisk Corporation has provided all parties of\n\nrecord with its Initial Disclosure as required by this Court's April 24, 2002 Scheduling Order.\n\nRespectfully submitted,\n\n\n~y-In-~harge for Defe dant\nTracy Cra\n\nEric H. Findlay\nState Bar No. 00789886\nRAMEY & FLOCK, P.C.\nE. Ferguson St.\nTyler, TX 75702\n/597-3301 telephone\n/597-2413 facsimile\n\nCase 9:02~cv-00O.58-JH Document 61 F~ed 05/15/2002 Page 2 of 2\n\n\nOF COUNSEL:\n\nMichael A. Ladra\nJames C. Otteson\nJames C. Yoon\nWILSON SONSINT GOODRICH & ROSATI\nProfessional Corporation\nPage Miii Road\nPalo Alto, CA 94304\n/493-9300 telephone\n/565-5100 facsimile\n\n\nCERTIFICATE OF SERVICE\n\n\nI hereby certify that on this the 15th day of May, 2002, a true and correct copy of the\n\nforegoing instrument was delivered to all counsel of record via facsimile and regular mail in\n\naccordance with the applicable rules of civil procedure.\n\n\nSamsung v. SanDisk Page 2\nNotice of Disclosure\n\n"
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      "filed_on": "2002-05-15T00:00:00", 
      "id": 13991, 
      "nice_text": "Notice of disclosure by Sandisk Corporation (djh) (Entered: 05/16/2002)", 
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          "text": "* Case 9:02~cv-00058JH Document 1 FUed 03/05/2002 Page 1 of 101\n\n\nFRED\nT C9LJRT\n\nVJfl -5 t~i 8: ILl\nIN THE UNITED STATES DISTRICT COUl~T::\nFOR THE EASTERN DISTRICT OFTEXA~' `~`~ 7'S~ ~` Lr~'IN\nLUFKJN DIVISION BY'J 3\n\n\nSAMSUNG ELECTRONICS CO., LTD., \ufffd\n\ufffd\nPlaintiff, \ufffd\n\ufffd CIVIL ACTION NO. g2 d~c C' sr\n\n\nSANDISK CORPORATION, \ufffd JUdge Hannah\n\nDefendant. \ufffd\n\nCOMPLAINT\n\nSamsung Electronics Co., Ltd., complains of SanDisk Corporation for violations\n\nof the United States patent laws. In support of its complaint, Samsung alleges as follows:\n\nPARTIES\n. Samsung Electronics Co., Ltd., (\"Samsung\") is a company organized under the\n\nlaws of South Korea with its principal place of business located at 416 Maetan-3 Dong,\n\nPaldal-Gu, Suwon City, Kyungki-Do, Korea.\n. On information and belief, SanDisk Corporation (\"SanDisk\") is a company\n\norganized under the laws of Delaware with its principal place of business in Sunnyvale,\n\nCalifornia. SanDisk may be served with process by serving Mr. Sanjay Mehrotra, Chief\n\nOperating Officer & Executive Vice President, SanDisk Corporation, 140 Caspian Court,\n\nSunnyvale, California 94089.\n\n\nSAMSUNG ELECTRONICS Co., LTD.'S\nCOMPLAINT FOR PATENT INFRINGEMENT PAGE-i\n\nCase 9:02~cv-00058~JH Document 1 F~ed 03/05/2002 Page 2 of 101\n\n\nJURISDICTION\n. This is an action arising under the United States patent laws, 35 U.S.C. \ufffd 101 et\n\nseq. This Court has subject matter jurisdiction under 35 U.S.C. \ufffd~ 271, 281, and 28\n\nU.S.C. \ufffd \ufffd 1331 and 1338 (a).\n\nVENUE\n. Venue over Samsung's claims is proper in this district pursuant to 28 U.S.C. \ufffd~\n(b)-(c), and 1400(b) because SanDisk resides in this judicial district and part of\n\nSamsung's causes of action arose in this judicial district.\n\nBACKGROUND FACTS COMMON TO ALL CLAIMS\n. Samsung is the world's leading manufacturer of semiconductor memory products.\n\nSamsung currently manufactures, distributes and sells dozens of memory products\n\nthroughout the world, including the United States. One of these memory products is the\n\nNAND Flash card, which is commonly referred to in the industry as a flash memory\n\nproduct.\n. Flash memory products are typically removable memory cards that are often\n\nfound in digital cameras, digital music players, digital camcorders, handheld PCs, e-\n\nBooks, and newer cellular phone tecimology, as well as other emerging products.\n. SanDisk manufactures and supplies flash memory products in consumer, OEM,\n\nand industrial markets. More specifically, SanDisk supplies, at least, the\n\nCompactFlashTM commercial flash memory product line that infringes upon one or more\n\nUnited States patents that are owned by Samsung. SanDisk also distributes other\n\nproducts that infringe at least some of Samsung's patents.\n\nSAMSUNG ELECTRONICS Co., LTD.'S\nCOMPLAINT FOR PATENT INFRINGEMENT PAGE- 2\n\n- Case 9:02~cv-0005&JH Document 1 FUed 03/05/2002 Page 3 of 101\n. SanDisk directly sells its memory products around the world and through\n\nintermediaries, including wholesalers, distributors, value-added resellers, and retailers\n\nlocated throughout the United States and specifically in this judicial district. Retailers of\n\nSanDisk products include Circuit City, K-Mart, Office Depot, Target, Sears, Office Max,\n\nStaples, Eckerd drug stores and Walgreens drug stores, among others.\n. SanDisk also sells its flash memory products to and through original equipment\n\nmanufacturers (\"OEMs\"), including Cannon, Hewlett-Packard, Fujitsu, Motorola, Kodak,\n\nPanasonic, and Polaroid, among others. SanDisk also sells flash memory products to\n\nprivate label partners that re-brand the SanDisk products under a different trade name,\n\nwhich are then sold directly to consumers or installed into consumer products.\n. As part of its sales of memory products in the United States, SanDisk markets,\n\npromotes, sells and offers for sale a full range of its flash memory products in Texas.\n\nSanDisk markets its flash memory products in Texas by using a direct sales organization\n\nand numerous distributors and manufacturers' representatives. In fact, SanDisk even has\n\na direct sales office in Texas to support its OEM customers and its distribution and\n\nmanufacturer representatives.\n. On information and belief, SanDisk flash memory products, including the\n\nCompactFlashTM product line, have been sold and are currently being sold on\n\nAmazon.com's internet website, which is available to consumers residing in the Lulkin\n\nDivision. On information and belief and according to information provided by\n\nAmazon.com, based on purchases made via the Amazon.com internet website, the\n\nSanDisk 128MB CompactFlashTM card ranks among the top selling electronic products\n\npurchased by consumers in Texas. SanDisk and Amazon.com do not restrict or otherwise\n\nSAMSUNG ELECTRONICS Co., LTD.'S\nCOMPLAINT FOR PATENT INFRINGEMENT PAGE- 3\n\nCase 9:02~cv-00058~JH Document 1 F~ed 03/05/2002 Page 4 of 101\n\n\nprevent consumers residing in the Lufkin Division from purchasing SanDisk flash\n\nmemory products on the Amazon.com internet website.\n. On information and belief, SanDisk directly markets, promotes, sells, offers for\n\nsale, or leases its flash memory products, including the CompactFlashTM product line, in\n\nnumerous locations throughout the Lufkin Division of the Eastern District of Texas\n\n(\"Lufkin Division\"). On information and belief, SanDisk also markets, promotes, sells,\n\noffers for sale, or leases its flash memory products, including the CompactFlash~\n\nproduct line, in numerous locations throughout the Lufkin Division by way of\n\nintermediaries, such as wholesalers, distributors, value-added resellers and retailers.\n. SanDisk has sold and is currently selling a full range of its flash memory products\n\nin the Lufkin Division. The SanDisk flash memory products being sold in the Lufkin\n\nDivision include the CompactFlashTM product line. SanDisk is selling these products\n\neither directly or indirectly through wholesalers, distributors, or value-added resellers, to\n\nvarious retail outlets located in Angelina and Nacogdoches Counties. These flash\n\nmemory products are in turn sold to consumers and end-users of the flash memory\n\nproducts who reside in the Lufkin Division.\n. On information and belief, SanDisk flash memory products, including the\n\nCompactFlashTM product line, have been sold and are currently being sold in Lufkin,\n\nAngelina County, Texas at the following retail outlets: Sears, which is located at the\n\nLufkin Mall, 4600 S. Medford Dr., Lufkin, Texas 75901; Waigreens drugstore, which is\n\nlocated at 102 N. Timberland Dr., Lufkin, Texas 75901; two Eckerd drugstores, which\n\nare located at 1204 E. Luflcin Avenue, and at 923 Frank Street, Lufkin, Texas 75901;\n\nTarget, which is located at 4200 S. Medford Drive, Lulkin, Texas 75901; Circuit City,\n\nSAMSUNG ELECTRONICS Co., LTD.'S\nCOMPLAINT FOR PATENT INFRINGEMENT PAGE- 4\n\nCase 9:02~cv-0005~JH Document 1 F~ed 03/05/2002 Page 5 of 101\n\n\nwhich is located at 4600 5. Medford Drive, Lufkin, Texas 75901; Office Depot, which is\n\nlocated at 4210 S. Medford Drive, Lufkin, Texas 75901; and OfficeMax, which is located\n\nat 2429 South John Reddit Drive, Lufkin, Texas 75901. Dozens, if not hundreds, of\n\nSanDisk products are offered for sale to consumers at these locations within the Lufkin\n\nDivision. On information and belief, each of these retail outlets receive flash memory\n\nproducts either directly from SanDisk or indirectly through intermediaries, such as\n\nwholesalers, distributors or value-added resellers. On information and belief, under\n\ncertain conditions, these retail outlets have the right to return any unsold SanDisk flash\n\nmemory inventory directly to SanDisk, including any unsold products in the\n\nCompactFlashTM product line.\n. On information and belief, SanDisk products, including the CompactFlashTM\n\nproduct line, have been sold and are currently being sold in Nacogdoches, Nacogdoches\n\nCounty, Texas at the following retail outlets: Staples, which is located at 4608 North\n\nStreet, Nacogdoches, Texas 75961; and Eckerd drugstore located at 1424 North Street,\n\nNacogdoches, Texas 75961. Dozens of SanDisk products are offered for sale to\n\nconsumers at these locations within the Lufkin Division. On information and belief, each\n\nof these retail outlets receive flash memory products either directly from SanDisk or\n\nindirectly through intermediaries, such as wholesalers, distributors or value-added\n\nresellers. On information and belief, under certain conditions these retail outlets have the\n\nright to return any unsold SanDisk flash memory inventory directly to SanDisk, including\n\nany unsold products in the CompactFlashTM product line.\n. On information and belief, SanDisk products, including products within the\n\nCompactFlashTM product line, have been incorporated into the following OEM products\n\nSAMSUNG ELECTRONICS Co., LTD.'S\nCOMPLAINT FOR PATENT INFRINGEMENT PAGE- 5\n\nCase 9:02~cv-00058-JH Document 1 F~ed 03/05/2002 Page 6 of 101\n\n\nthat have been and are currently being sold in the Lufkin Division: Kodak digital\n\ncameras; Polaroid digital cameras; Nikon digital cameras; and Hewlett-Packard digital\n\ncameras.\n. On information and belief, SanDisk products, including the CompactFlashTM\n\nproduct line, are being promoted, advertised and offered for sale in the Lufkin Division.\n\nMore specifically, SanDisk products have been promoted, advertised, and offered for sale\n\nin Waigreens circular advertisements that were included in Lufkin's newspaper, the\n\nLufkin Daily News, on February 17, 2001. SanDisk also promotes, advertises and offers\n\nfor sale its flash memory products on its internet website, which is described more fully\n\nin the following paragraphs.\n. On information and belief, SanDisk has knowingly and intentionally formed a\n\nchannel of distribution for its flash memory products, including the CompactFlashTM\n\nproduct line, into the Lufkin Division. SanDisk knows or should have known that the\n\nLufkin Division was a termination point of its distribution channel for flash memory\n\nproducts, including the CompactFlashTM product line.\n. On information and belief, SanDisk has offered cash rebates on sales of flash\n\nmemory products sold to consumers in the United States. Cash rebates have been offered\n\nfor SanDisk's flash memory products, including the CompactFlashTM product line, that\n\nwere and are sold to consumers in the Luficin Division. On information and belief,\n\nduring SanDisk promotional events, consumers can ordinarily obtain rebate information\n\nand rebate certificates for SanDisk's products directly from the retail outlets located in\n\nthe Lufkin Division that sell SanDisk flash memory products, including the\n\n\nSAMSUNG ELECTRONICS Co., LTD.'S\nCOMPLAINT FOR PATENT INFRINGEMENT PAGE- 6\n\nCase 9:02~cv-00056~JH Document 1 F~ed 03/05/2002 Page 7 of 101\n\n\nCompactFlashTM product line. This information can also be obtained on SanDisk's\n\ninternet website, which is described more fully in the following paragraphs.\n. On information and belief, SanDisk has offered and continues to offer warranties\n\non its flash memory products sold to consumers in the United States. Warranties have\n\nbeen offered and continue to be offered on SanDisk's flash memory products, including\n\nthe CompactFlashTM product line, to consumers residing in the Lufkin Division. On\n\ninformation and belief, consumers can obtain warranty information and warranty\n\nregistration materials for SanDisk's products from the retail outlets located in the Lufkin\n\nDivision that sell SanDisk flash memory products, including the CompactFlashTM\n\nproduct line. On information and belief, SanDisk warranty information and warranty\n\nregistration materials for SanDisk's flash memory products are included within the\n\npackage of each retail SanDisk product sold. This information can also be obtained on\n\nSanDisk's internet website, which is described more fully in the following paragraphs.\n. On information and belief, SanDisk offers a five-year warranty on all of its flash\n\nmemory products, including products in the CompactFlashTM product line. The SanDisk\n\nwarranty provides that SanDisk \"will repair or replace this Flash Memory Card free of\n\ncharge if it ever fails within 5 years from the date of purchase. . . SanDisk will inspect the\n\nproduct and at its option, repair or replace the product. SanDisk will ship out a product\n\nwith equal or greater capacity.\"\n. The SanDisk warranty registration material on its flash memory products,\n\nincluding the CompactFlashm product line, which is enclosed within the package of each\n\nretail product, require the consumer to complete a mail-in card enclosed with the product\n\nand mail the registration materials to SanDisk's Warranty Registration division. This\n\nSAMSUNG ELECTRONICS Co., LTD.'S\nCOMPLAINT FOR PATENT INFRINGEMENT PAGE- 7\n\nCase 9:02~cv-00058-JH Document 1 F~ed 03/05/2002 Page 8 of 101\n\n\nwarranty registration material refers consumers to SanDisk's internet website, which is\n\ndescribed more fully in the following paragraphs.\n. On information and belief, SanDisk engages in substantial e-comn-ierce by way of\n\nthe internet and does business in the Lufkin Division through its interactive website,\n\nwhich is located at http://www.sandisk.com/main.htm.\n. SanDisk's website is highly interactive in its promotion, advertising and\n\nmarketing of SanDisk's flash memory products. The SanDisk website allows consumers\n\nto shop for, order and purchase a full range of SanDisk's flash memory products.\n\nConsumers in Texas, including consumers residing in the Lufkin Division, have\n\npurchased SanDisk's flash memory products, including products from the\n\nCompactFlashTM product line, through SanDisk's internet website. SanDisk does not\n\nrestrict or otherwise prevent consumers residing in the Lulkin Division from purchasing\n\nSanDisk's flash memory products on its website.\n. SanDisk has shipped flash memory products, including products from the\n\nCompactFlashTM product line, purchased through SanDisk's website to consumers\n\nresiding in the Lufkin Division.\n. SanDisk's website provides consumers with warranty information related to its\n\nflash memory products, including its CompactFlashTM product line. See\n\nhttp://www.sandisk.com/techlrw_cf. asp. SanDisk does not restrict or otherwise prevent\n\nconsumers residing in the Lufkin Division from initiating warranty claims or obtaining\n\nwarranty information about SanDisk's flash memory products from its website.\n. SanDisk allows consumers to register warranty information for its flash memory\n\nproducts, including products from the CompactFlashTM product line, through its website.\n\nSAMSUNG ELECTRONICS Co., LTD.'S\nCOMPLAINT FOR PATENT INFRINGEMENT PAGE- 8\n\nCase 9:02~cv-00058~JH Document 1 F~ed 03/05/2002 Page 9 of 101\n\n\nSee http://www.sandisk.comltech/prod-reg.asp. To register a flash memory product for\n\nwarranty purposes, the consumer must complete several fields of inquiry and provide\n\nrequested information to SanDisk, including the consumer's residence and where the\n\nSanDisk product was purchased. See Id. SanDisk does not restrict or otherwise prevent\n\nconsumers residing in the Lufkin Division from registering SanDisk's flash memory\n\nproducts on its website.\n. SanDisk's website provides consumers residing in the Lufkin Division with cash\n\nrebates and cash rebate information on its flash memory products. See\n\nhttp://www.sandisk.comltechlrebates.asp. As can be seen from the SanDisk website,\n\nrebates are offered on various SanDisk products, including CompactFlash~ cards, and\n\nfrom various retail merchants. See and click on the Circuit City hyperlink at\n\nhttp://www.sandisk.comltechlrebates.asp. SanDisk' s website also instructs consumers on\n\nthe proper procedure for obtaining a delayed rebate payment on any applicable SanDisk\n\nproduct. See and click on hyperlink \"Why haven't I received by rebate yet?\" at\n\nhttp://www.sandisk.comItechIfac~search.asp. SanDisk does not restrict or otherwise\n\nprevent consumers residing in the Lufkin Division from obtaining rebates and rebate\n\ninformation on SanDisk's flash memory products from its website.\n. SanDisk invites consumers to interact with its technical support staff via e-mail or\n\ntelephone with respect to customer service issues or technical support that consumers\n\nneed for the proper operation and use of SanDisk's flash memory products, including the\n\nCompactFlashTM product line. See http://www. sandisk.comltechlcontact.asp. SanDisk\n\ndoes not restrict or otherwise prevent consumers residing in the Lufkin Division from\n\n\nSAMSUNG ELECTRONICS Co., LTD.'S\nCOMPLAINT FOR PATENT INFRINGEMENT PAGE- 9\n\nCase 9:02-cv-00058~JH Document I F~ed 03/05/2002 Page lOaf 101\n\n\nobtaining customer service information or technical support for SanDisk's flash memory\n\nproducts from its website.\n. SanDisk invites consumers to interact with its website by allowing consumers to\n\n\"design products which use SanDisk cards, flash memory chips [including\n\nCompactFlashTM products] and other SanDisk technology.\" See\n\nhttp://www.sandisk.conVtech/oem_designls_oem. asp. SanDisk does not restrict or\n\notherwise prevent consumers residing in the Lufkin Division from interacting with the\n\nSanDisk website to design products that incorporate SanDisk's flash memory products.\n. SanDisk invites consumers to interact with its website by allowing consumers to\n\ndownload software upgrades for various consumer devices so that SanDisk's flash\n\nmemory products, including products from the CompactFlashTM product line, are\n\ncompatible with the consumer devices with which they are installed. See\n\nhttp://www.sandisk.com/techls_downloads.asp. On information and belief, certain\n\nconsumer products will not function unless the consumer downloads the appropriate\n\nsoftware (e.g., drivers) from SanDisk's website. SanDisk does not restrict or otherwise\n\nprevent consumers residing in the Lufkin Division from interacting with the SanDisk\n\nwebsite to download software so that SanDisk's flash memory products can be installed\n\nin consumer devices.\n. SanDisk invites consumers to interact with SanDisk by allowing consumers the\n\noption to enroll in SanDisk's quarterly product e-mail list that is distributed to consumers\n\nby SanDisk. See http://www.sandisk.comltechIprod-reg.asp. SanDisk does not restrict or\n\notherwise prevent consumers residing in the Lufkin Division from receiving SanDisk's\n\nquarterly product e-mail list.\n\nSAMSUNG ELECTRONICS Co., LTD.'S\nCOMPLAINT FOR PATENT INFRINGEMENT PAGE- 10\n\nCase 9:02-cv-00058-JH Document I FHed 03/05/2002 Page 11 of 101\n. As the preceding paragraphs show, SanDisk clearly does business in the Lufkin\n\nDivision by virtue of its established channels of distribution and interactive website.\n\nCOUNT ONE\nInfringement of United States Patent No. 5,473,563\n. Samsung incorporates by reference paragraphs 1 through 33 as though fully set\n\nforth herein.\n. Samsung is the sole owner of the entire right, title, and interest in United States\n\nPatent No. 5,473,563 (\"the `563 patent\"), which was duly and legally issued to Samsung\n\non December 5, 1995, and entitled \"Nonvolatile Semiconductor Memory.\" A copy of the\n\n`563 patent is attached hereto as Exhibit A.\n. Samsung has never licensed or permitted SanDisk to practice any of the claims\n\ngranted in the `563 patent.\n. On information and belief, SanDisk has infringed the `563 patent, literally or by\n\nequivalents, by making, using, selling, offering for sale, leasing, or importing nonvolatile\n\nsemiconductor memory products into the United States, including the Lufkin Division,\n\nthat read on one or more of the inventions covered by the claims of the `563 patent. On\n\ninformation and belief, SanDisk continues to engage in such acts of infringement.\n. On information and belief, SanDisk, with full knowledge of Samsung's ownership\n\ninterests in the `563 patent, has intentionally induced and is currently inducing others to\n\ninfringe the `563 patent, or has contributed to the infringement of the `563 patent by\n\nactively and knowingly aiding and abetting others to make, use, sell, offer for sale, lease,\n\nor import nonvolatile semiconductor memory products into the United States, including\n\n\nSAMSUNG ELECTRONICS Co., LTD.'S\nCOMPLAINT FOR PATENT INFRINGEMENT PAGE-il\n\nCase 9:02-cv-00058~JH Document I F~ed 03/05/2Q02 Page 12 of 101\n\n\nthe Lufkin Division, that infringe one or more of the inventions covered by the claims of\n\nthe `563 patent, either literally or by equivalents.\n. SanDisk's infringement of the `563 patent has been willful, and any further\n\ninfringement of the `563 patent by SanDisk would be with full knowledge of Samsung's\n\nlegal interest in the `563 patent and would be deliberate and willful.\n\nCOUNT TWO\nInfringement of United States Patent No. 5,514,889\n. Samsung incorporates by reference paragraphs 1 through 39 as though fully set\n\nforth herein.\n. Samsung is the sole owner of the entire right, title, and interest in United States\n\nPatent No. 5,514,889 (\"the `889 patent\"), which was duly and legally issued to Samsung\n\non May 7, 1996, and entitled \"Non-Volatile Semiconductor Memory Device and Method\n\nfor Manufacturing the Same.\" A copy of the `889 patent is attached hereto as Exhibit B.\n. Samsung has never licensed or permitted SanDisk to practice any of the claims\n\ngranted in the `889 patent.\n. On information and belief, SanDisk has infringed the `889 patent, literally or by\n\nequivalents, by making, using, selling, offering for sale, leasing, or importing nonvolatile\n\nsemiconductor memory products into the United States, including the Lufkin Division,\n\nthat read on one or more of the inventions covered by the claims of the `889 patent. On\n\ninformation and belief, SanDisk continues to engage in such acts of infringement.\n. On information and belief, SanDisk, with full knowledge of Samsung's ownership\n\ninterests in the `889 patent, has intentionally induced and is currently inducing others to\n\ninfringe the `889 patent, or has contributed to the infringement of the `889 patent by\n\n\nSAMSUNG ELECTRONICS Co., LTD.'S\nCOMPLAINT FOR PATENT INFRINGEMENT PAGE- 12\n\nCase 9:02-cv-00058~JH Document I FHed 03/05/2002 Page 13 of 101\n\n\nactively and knowingly aiding and abetting others to make, use, sell, offer for sale, lease\n\nor import nonvolatile semiconductor memory products into the United States, including\n\nthe Lufkin Division, that infringe one or more of the inventions covered by the claims of\n\nthe `889 patent, either literally or by equivalents.\n. SanDisk's infringement of the `889 patent has been willful, and any further\n\ninfringement of the `889 patent by SanDisk would be with full knowledge of Samsung's\n\nlegal interest in the `889 patent and would be deliberate and willful.\n\nCOUNT THREE\nInfringement of United States Patent No. 5,546,341\n. Samsung incorporates by reference paragraphs 1 through 45 as though fully set\n\nforth herein.\n. Samsung is the sole owner of the entire right, title, and interest in United States\n\nPatent No. 5,546,341 (\"the `341 patent\"), which was duly and legally issued to Samsung\n\non August 13, 1996, and entitled \"Nonvolatile Semiconductor Memory.\" A copy of the\n\n`341 patent is attached hereto as Exhibit C.\n. Samsung has never licensed or permitted SanDisk to practice any of the claims\n\ngranted in the `341 patent.\n. On information and belief, SanDisk has infringed the `341 patent, literally or by\n\nequivalents, by making, using, selling, offering for sale, leasing, or importing nonvolatile\n\nsemiconductor memory products into the United States, including the Lufkin Division,\n\nthat read on one or more of the inventions covered by the claims of the `341 patent. On\n\ninformation and belief, SanDisk continues to engage in such acts of infringement.\n\n\nSAMSUNG ELECTRONICS Co., LTD.'S\nCOMPLAINT FOR PATENT INFRINGEMENT PAGE- 13\n\nCase 9:02-cv-00058~JH Document I F~ed 03/05/2002 Page 14 of 101\n. On information and belief, SanDisk, with full knowledge of Samsung's ownership\n\ninterests in the `341 patent, has intentionally induced and is currently inducing others to\n\ninfringe the `341 patent, or has contributed to the infringement of the `341 patent by\n\nactively and knowingly aiding and abetting others to make, use, sell, offer for sale, lease,\n\nor import nonvolatile semiconductor memory products into the United States, including\n\nthe Lufkin Division, that infringe one or more of the inventions covered by the claims of\n\nthe `341 patent, either literally or by equivalents.\n. SanDisk's infringement of the `341 patent has been willful, and any further\n\ninfringement of the `341 patent by SanDisk would be with full knowledge of Samsung's\n\nlegal interest in the `341 patent and would be deliberate and willful.\n\nCOUNT FOUR\nInfringement of United States Patent No. 5,642,309\n. Samsung incorporates by reference paragraphs 1 through SI as though fully set\n\nforth herein.\n. Samsung is the sole owner of the entire right, title, and interest in United States\n\nPatent No. 5,642,309 (\"the `309 patent\"), which was duly and legally issued to Samsung\n\non June 24, 1997, and entitled \"Auto-Program Circuit in a Nonvolatile Semiconductor\n\nMemory Device.\" A copy of the `309 patent is attached hereto as Exhibit D.\n. Samsung has never licensed or permitted SanDisk to practice any of the claims\n\ngranted in the `309 patent.\n. On information and belief, SanDisk has infringed the `309 patent, literally or by\n\nequivalents, by making, using, selling, offering for sale, leasing, or importing nonvolatile\n\nsemiconductor memory products into the United States, including the Lulkin Division,\n\n\nSAMSUNG ELECTRONICS Co., LTD.'S\nCOMPLAINT FOR PATENT INFRINGEMENT PAGE- 14\n\nCase 9:02-cv-00058~JH Document I FHed 03/05/2002 Page 15 of 101\n\n\nthat read on one or more of the inventions covered by the claims of the `309 patent. On\n\ninformation and belief, SanDisk continues to engage in such acts of infringement.\n. On information and belief, SanDisk, with full knowledge of Samsung's ownership\n\ninterests in the `309 patent, has intentionally induced and is currently inducing others to\n\ninfringe the `309 patent, or has contributed to the infringement of the `309 patent by\n\nactively and knowingly aiding and abetting others to make, use, sell, offer for sale, lease\n\nor import nonvolatile semiconductor memory products into the United States, including\n\nthe Lufkin Division, that infringe one or more of the inventions covered by the claims of\n\nthe `309 patent, either literally or by equivalents.\n. SanDisk's infringement of the `309 patent has been willful, and any further\n\ninfringement of the `309 patent by SanDisk would be with full knowledge of Samsung's\n\nlegal interest in the `309 patent and would be deliberate and willful.\n\nCOUNT FIVE\nPreliminary and Permanent Injunction\n. Samsung incorporates by reference paragraphs 1 through 57 as though fully set\n\nforth herein.\n. As a consequence of SanDisk's activities described herein, Samsung has been\n\nirreparably harmed to an extent yet ascertained, and will continue to be irreparably\n\nharmed by such activities in the future unless SanDisk is enjoined by this Court from\n\nengaging in said activities. Samsung has no adequate remedy at law.\n\nPRAYER FOR RELIEF\n\nWHEREFORE, Samsung requests that this Court enter judgment against SanDisk\n\nand grant Samsung the following relief:\n\n\nSAMSUNG ELECTRONICS Co., LTD.'S\nCOMPLAINT FOR PATENT INFRINGEMENT PAGE- 15\n\nCase 9:02-cv-00058~JH Document I FHed 03/05/2002 Page 16 of 101\n. Issue a preliminary injunction enjoining SanDisk from any further activity\nthat infringes on one or more claims of the following Samsung's patents:\n\n(a) United States Patent No. 5,473,563;\n(b) United States Patent No. 5,514,889;\n(c) United States Patent No. 5,546,341; and\n(d) United States Patent No. 5,642,309;\n. Upon final hearing, permanently enjoin SanDisk from any activity that\ninfringes on one or more claims of the Samsung's patents;\n. Find that SanDisk's infringement of Samsung's patents was and is willful;\n. Find that this an exceptional case and award Samsung reasonable\nattorneys fees in accordance with 35 U.S.C. 285; and\n. Award Samsung the costs it has incurred to prosecute this action.\n\nDated: March _____,2002. Respectfully submitted,\n\n\nGe~ge */\ufffdndler\nAttorney-!h-Charge for Plaintiff\nSamsung Electronics Co., Ltd.\nState Bar No. 04094000\nThe Law Offices of George Chandler\nE. Frank Poland Professional Building\nP.O. Box 340\nLufkin, Texas 75902\nTelephone: (936) 632-7778\nFacsimile: (936) 632-1304\nE-mail: gchandler~chandler1awoffices.com\n\nOF COUNSEL:\n\nTHE LAW OFFICES OF CLAYTON E. DARK, JR.\nClayton E. Dark, Jr.\nState Bar No. 05384500\nP.O. Box 2207\nLulkin, Texas 75902\nTelephone: (936) 637-1733\nFacsimile: (936) 637-2897\n\n\nSAMSUNG ELECTRONICS Co., LTD.'S\nCOMPLAINT FOR PATENT INFRINGEMENT PAGE- 16\n\nCase 9:02-cv-00058~JH Document I FHed 03/05/2002 Page 17 of 101\n\n\nTHE RICHARDS LAW FIRM\nR.W. (\"Ricky\") Richards\nState Bar No. 16854100\nP.O. Box 1309\nJacksonville, Texas 75766\nTelephone: (903) 586-2544\nFacsimile: (903) 586-6529\n\nTHE LAW OFFICES OF CLAUDE E. WELCH\nClaude E. Welch\nState Bar No. 21120500\nP.O. Box 1574\nLufkin, Texas 75902\nTelephone: (936) 639-3311\nFacsimile: (936) 639-3049\n\nWElL, GOTSHAL & MANGES LLP\nDavid J. Healey\nState Bar No. 09327980\nAnita E. Kadala\nState Bar No. 00786007\nLouisiana, Suite 1600\nHouston, Texas 77002\nTelephone: (713) 546-5000\nFacsimile: (713) 224-9511\nE-mail: david.healey~weil.com\nE-mail: anita.kadala@weil.com\n\n\nSAMSUNG ELECTRONICS Co., LTD.'S\nCOMPLAINT FOR PATENT INFRINGEMENT PAGE- 17\n\nDocument I\n\nCase 9:02-cv-00058~JH\n\nFHed 03/05/2002\n\nPage 18 of 101\n\n[54] NONVOLATILE SEMICONDUCTOR\nMEMORY\n\n[75] Inventors: Kang D. Suh, Ahnyang; Jin KL Kim,\nSeoul; Jeong H. Choi, Kwacheieon, all\nof Rep. of Korea\n\n[73] Assignee: Sanisung Electronics Co., LtdL,\nSuwon, Rep. of Korea\n\n[21] AppL No.: 171,300\n[22] Filed: Dec. 22,1993\n[301 Foreign Application Priority Data\nJan. 13. 1993 [KR] Rep, of Korea ........... ...... 1993-390\n\n\n[51] list. 0.6 ....,,,.,,.,.......,.. GIIC 7/00; G1:11C 11/40\n\n[52] U.S. Cl. .........~.. .. 365/1KS,I3; 36~5/1 89.01;\n/189.05; 3665/230.06\n[58] FIeld of Search ............................_ 365/1/185, 218,\n/900, 189.01, l89.0~)5, 230.06\n\n[561\n\nReferences Cited\nU.S. PATENT DOCUMENTS\n,053,990 10/1991 Kreifels ct aL.\n.3 13,432 5/1994 Liii et at - .,.,.. 3 3651'230.06\n,345,418 911994 Challa ...... ..... .... 365/185\n\nFOREIGN PATENT DOCUMENTS\n/1991 Rep.of Korea.\nOTHER PTJBUCATIONS\n`New Device Technologies For 5V-Only4Mb E BEPROM\nWith NAND Structure Cell\" by M. Momodoithi, R. Kir-\nisawa, R. Nakayansa, S. Aritome, T. Endoh, Y. Itoh,,, Y. Iwata,\nR Oodaira, T. Tanaka, M. Chiba, R. Shirotata, and F.\nMasuoka. ULSI Research Center, Toshiba Cor)rporation.\n-IEDM 88.\n\"A Nand Structured Cell With A New Programnthing Tech-\nnology For Highly Reliable 5V-OnIy Flash EEPRROM\", it\n\nKirisawa, S. Aritome, R. Nakayama, T. Endoh, it Shirota,\nand F. Masuoka, 1990 Symposium on VLSI Technology.\n\"A High-Density NAN) EEPROM With Block-Page Pro-\ngramming For Microcomputer Applications\", Y. Iwata, M.\nMomodomi, T. Tanaka, H. Oodaira, Y. Itoh, R. Nakayama,\nit Kirisawa, S. Aritome, T. Endoh, R. Shirota, K. Ohuchi,\nand F Masuoka 1990 IEEE.\nA 4-Mb NAN) EEPROM with light Programmed Vt\nDistribution, M. Momodomu, T. Tanaka, Y. Iwata, Y.\nTanaka, H. Oodaira, Y. Itoh, it Shfrota, K. Ohuchi and F.\nMasuoka 1990 IEEE.\n\nPrimary Examiner-Tan T. Nguyen\nAttorney, Agen4 or Finn-RobertA. Westerhmd; Stephen R.\nWhitt; Charles R. Donohoe\n\n[57]\n\nABSTRACT\nA nonvolatile semiconductor memory device comprising an\narray of cell units, each cell unit including at least one\nmemory transistor which has a floating gate and a control\ngate, the array being divided into a plurality of memory\nblocks each having a certain number of cell units. A selected\nmemory block is erased by an erase voltage applied to a\nsemiconductor substrate while unselected memory blocks\nare prevented from erasing by capacitive coupling of the\nerase voltage to floated word lines connected to control gates\nof memory transistors of the unselected memory blocks. In\na program mode where a program voltage is applied to a\nselected word line of a selected memory block and a pass\nvoltage is applied to unselected word lines of the selected\nmemory block, channel regions and source and drain junc-\ntions of memory transistors of cell units in the selected\nmemory block are charged to a program inhibition voltage.\nChannel regions and source and drain junctions of cell units\nassociated with memory transistors programmed to the other\nbinary data are discharged to be programmed while those of\ncell units associated with nonprogrammed memory transis-\ntors are maintained to the program inhibition voltage to\nprevent programming.\n\nUnited States Patent [1919]\nSub et iii.\nIII~ 11111110 liii ~ 1111111111110111111111111\nUS005473563A\n\n[iii Patent Number: 5,473,563\n[45] Date of Patent: Dec. 5, 1995\nClaims, 19 Drawing Sheets\n\nEXHIBIT\n\nPage 19 of 101\n\nCase 9:02-cv-00058JH Document I\n\nFUed 03/05/200k\n\nU.S. Patent\n\nDec. 5, 11995\n\nSheet 1 of 19\n,473,563\n\nCGL8\nCGL1H I\nI NCGL2\n-\n\nBL1---\n-\n\nBLOCK\nSELECTION\nCONTROL\nCIRCUIT\n\n\nOK1\n\n\nBK2\n\n\nBK1 024\n\n\nLHBL3 . . *\n\nBL2048\n\nL~B~\n\n\n-10\n\n\nF12\n\nCONTROL\nGATE DRIVING\nCIRCU1~\nCSL-\n\nDATA REGISTER AND SENSE AMP\n\nSOURCE\nLINEDRMNG\nCIRCUIT\n-\n-\n\n.\n\n\n-\n\n\nCOLUMN DECODER AND\nSELECTION CIRCUIT\n\n.\n\n* **\n\n\nINPUT/OUTPUT BUFFER\n\n\nPROGRAMMING\nDETERMINA11ON\nCIRCU IT\n\nH\n\n\nH6\n\n\nc~\n\nc~\n\nc1\n\nk\n\n\nI~/O 1\n/0 2 I/O 3\n\nI/O 7 I/O 8\n\nFIG. I\n\nCase 9:02-cv-00058~JH Document I\n\nFHed 03105/2002 Page 20 of 101\n\nCGL5~-.-ii---~[~-~ -----~--\n~\nCGL7~-~-- ----Lip7~I\nCGL8~-~- ~TM~7~\nSGL1 -2~.--~-----r1- --- ____\nBT1 0~ ST2~/\nSGL2-2-.~-.---~_\nCGL8~-~----J~_\nCGL7~~-~_---~[-_ ___J_\nCGL6~-J~- ------HI\nCGL5~-_-J_ ----HIl\nCGL4~-I------HII\nCGL3~-_I_----_---~\nCGL2~-----~\nCGLl~...-~.-_~[-\nSGL2- ~\n\n\nBSC2342 BLL-1I BLL-21 BLA.-256\n\n\nFIG. 2a\n\nU.S. Patent Dec. 5, 11995\n\nSheet 2 of 19\n\nSGL1 -1'\n,473,563\n\nBT1\n\n/ CB&.(L=1,2, ,... ,8)\n\nST\n\nCase 9:02-cv-00058JH Document I\n\nFHed 03/05/2002\n\nPage 21 of 101\n\nU.S. Patent\n\nDec. 5, 11995\n\nSheet 3 of 19\n,473,563\n\nI/O ~\n\nI?IC. 2b\n\nCase 9:02-cv-00058~JH Document I\n\nF~ed 03/05/2002\n\nPage 22 of 101\n\nU.S. Patent\n\nDec. 5, 11995\n\nSheet 4 of 19\n,473,563\n\nBL\n~__4['~j 96\ntL\n(/1\n\n\n:82~i:J\n\n\n\n\n\n.841.~I\n\n: rM2.\n\n\n\n\n.t-\nI\nI\n~\n-'\n~rM8~\n\n\n\n\n.----.\n\n\n\n\n\nC)\n\n\nCSL~\n -~\n\n\nI.\n\na-\n\n\nL.\n\nL \n\n---~~IV\nI \n\nFIG. 3\n\nS\n\nWL1\n\n.-\n\n__~-WL2\n\n()\n\nWL7\nWL8\n\nCase 9:02-cv-00058~JH Document I\n\nFHed 03/05/2002\n\nPage 23 of 101\n\nU.S. Patent\n\nDec. 5, 11995\n\nSheet 5 of 19\n,473,563\n\nCo ~-\nN\n\ncco\ntN-\n\nCase 9:02-cv-00058~JH Document I\n\nFHed 03/05/2002\n\nPage 24 of 101\n\nU.S. Patent\n\nDec. 5,11995\n\nSheet 6 of 19\n,473,563\n\nc'1\n\n-J\n(I)\n\nE\na)\n~\n>\nF')\nc..1\n\n..~s\n-a-\n~\n>\n\nc-I\n,4-J\n\nC'4\n\n\n/\n\n\nfl_\n~\nS.'-\n\n(0\n~t.\n\nCo\nc-i\n\nC Q_ 0 Q~\n\nCase 9:02-cv-00058~JH Document I\n\nFHed 03/05/20Q2\n\nPage 25 of 101\n\nU.S. Patent\n~\n\nII\n\nDec. 5, 11995\n\nSheet 7 of 19\n,473,563\nC.D\n< 1< 1<\n.. L.. i..\n*0 0 0\n)0\n\nCase 9:02-cv-00053~JH Document I FHed 03/05/2002 Page 26 of 101\n\n\nU.S. Patent Dec. 5, 11995 Sheet 8 of 19 5,473,563\n\n\ufffd\n~j2O8\n\nPGM L I\nJI L __ Vpi\n\nPGM I -~CSL\nJFIG. 7\n~\nVcc\n\n\n~4H\n\n\nPIG. 8a\n}I~'IG. 8\n\nCase 9:02-cv-00053~JH Document I\n\nFHed 03/05/2002\n\nPage 27 of 101\n\nU.S. Patent\n\nDec. 5, 11995\n\nSheet 9 of 19\n,473,563\n\nw\n\n\n\n\n\nTO 162\n\nPGM\n\n\nFIG. 8b\nSLE __c~'-~ IfEEE~i07\nPGM\n\n\nFIG. 8c\n\nCase 9:02-cv-00058~JH Document I\n\nFHed 03/05/2002\n\nPage 28 of 101\n\nU.S. Patent\n\nDec. 5, 11995\n\nSheet 10 of 19\n,473,563\nFP1\nFP2\nFP3\nFP4\n\nFP5\nFP6\nFP7\nFP8\n-hG.\na\nb\n~ FP~\nSFP\n\n\nPDS\n\nFIG. 9\n)\n\nVcc\n\nSUP -218\nI 1 -220\n-\nHd72Hd\n,1j\n\nI S ~\n\n\n/\n\n\n.)FJG.\n\nCase 9:02-cv-00058~JH Document I\n\nFHed 03/05/20Q2 Page 29 of 101\n\nU.S. Patent\n\n\nWE\n\nERA\n\nPGM\n\nSLE\n\nVpgm\n\nVpas\n\n\n\ufffd\n\nXd\n\nBLK\n\nDS\n\nVera\n\nDCB\n\nSBL\n\nDec. 5, 11995\n\nSheet 11 of 19\n,473,563\n\n~1 ~2 ~3 ~4~5\n\nFIG. 10\n\nPage 30 of 101\n\nCase 9:02-cv-00058~H Document I\n\n\nUnited States Patent [1g91\nCho et al.\n\n[54] NON-VOLATILE SEMICONDUCTOR\nMEMORY DEVICE AND METHOD F(1OR\nMANUFACTURING TEE SAME\n\n[75] Inventors: Myoung-kwan Cho; Jeoug-hyiyuk Choi,\nboth of Kyungki, Rep. of Korana\n\n[731 Assignee: Sanisung Electronics Co., LIdSL,\nSuwon, Rep. of Korea\n\n[21] Appi. No.: 107,901\n[22] Filed: Aug. 18, 1993\n\n[301 Foreign Application Priority Data\nAug. 18. 1993 [KR] Rep. of Korea 14810/92\n[51] mt. Cl.6 .. H01)1L 29/788\n[52] U.S. Cl .. 257/316; 257/371;.; 257/548;\n/324\n[58] Field of Search 257/7/316, 371,\n/548, 324\n\n[56]\n\nReferences Cited\nU.S. PATENT DOCUMENTS\n\nPrimary Examiner-Edward Wojciechowicz\nAttorney, Agent, or Firnz-Cushman Derby & Cushman\n\n\n[57]\n\nABSTRACT\n\nAn EEPROM device in which a high voltage is applied to\nthe chip during the memory cell operation and a method for\nthe manufacturing the same are disclosed. On a P-type\nsemiconductor substrate, a first N-well is formed in a surface\nportion of the substrate in the cell army region and a second\nN-well is formed in a first surface of the substrate in the\nperipheral circuit region. An EEPROM memory cell is\nformed on the first P-well and a first NMOS transistor is\nformed on the second P-well. Also, a second NMOS tran-\nsistor is formed on a second surface portion of the semi-\nconductor substrate in the peripheral cireuit 10 region and a\nPMOS transistor is formed on the second N-well. The\nimpurity concentrations of the first and second P-wells are\ncontrolled in accordance with the characteristic of the MOS\ntransistors to be formed. Further, a second NMOS transistor\nhaving a resistance against a high voltage is directly formed\non the P-type substrate. Thus, the electric characteristic of\nthe EEPROM device is enhanced.\n,907,058 3/1990 Sakai .. 257/371\n,063,431 11/1991 Ohshima .. . 257/316\n,341,342 8/1994 Brahmbhatt .. .. 257/316\n\n\nCELL\nARRAY REGION\nClaims, 11 Drawing Sheets\n\nF~ed 03/05/200~\n\nliii 11111111 III 11111 11111 11111 ~ liii 11111 11111 11111 111111 Iii III)! liii\nUS005514889A\n\n[11] Patent Number: 5,514,889\n[45] Date of Patent: May 7,_1996\n\nLJ\n\n~PER1 PHERAL CIRC~T REGION\n\nEXHIBIT\n\nCase 9:02-cv-00058~JH Document I\n\nFHed 03.105/2002 Page 31 of 101\n\nU.S. Patent\n\nMay 7, 11996\n\n\nFIG. I\n\nSheet 1 of 11\n,514,889\n\nPERIPHERAL\nCIRCUIT REGION\n\nCELL ARRAY REGION\n\nCODNTROL GATE N\n\nSEELECT GATE 2\n\nERASE WRITE\nBL(I) BL(2) BL(I) BL(2)\nOPEN OPEN O.3V 7V\n\nI 20V\n\nI ov 7V\n\nOv\n\n.OV 7V\n\nJ-\n\nLL\n\nFIG.2\n\nSELECTED\nBIT LINE\n\nUNSELECTED\nBIT LINE\n\nBL(I) BL(2)\n\nSEIIECT GATE\n\nGATE\nV\n\nCODNTROL GATE\nCOf)NTROL GATE 3\nV\n\nOV 7V\nV OV\n\nOPEN\nV\n\nOv\nOv\nOv\n\nN--SUBSTRATE 20V\n\nPage 32 of 101\n\nCase 9:02-cv-00058~H Document I\n\nF~Ied 03./o5/200a\n\nU.S. Patent\n\nMay 7, : 1996\n\n\nFIG. 3\n\nSheet 2 of 11\n,514,889\n\nCELL\nARRAY REGION\n-1--i-\n\nPERIPHERAL CIRCUIT REGION\n\nCase 9:02-cv-00058-JH Document I\n\nFHed 03./05/200a\n\nPage 33 of 101\n\nU.S. Patent\n\n\nro\n\n\nN\nN\n\nMay 7, 1996\n\n\nN\n\nSheet 3 of 11\n,514,889\n\nI\n\nU-\n\n\n\nC\n\n(`U\n-d\n\nCase 9:02-cv-00058~JH Document I\n\nFHed 03/05/2002\n\nPage 34 of 101\n\nU.S. Patent\n\n\n(D\nC\nU-\n\nMay 7, 11996\n\nSheet 4 of 11\n,514,889\n\nN-\n(9\nI:\n\nCase 9:02-cv-00058~H Document I\n\nFHed 03/05/2002\n\nPage 35 of 101\n\nU.S. Patent\n\n\n(9\nU-\n\nMay 7, 11996\n\nSheetS of 11\n,514,889\n\nCase 9:02-cv-00058~JH Document I\n\nFHed 03/05/2002\n\nPage 36 of 101\n\nU.S. Patent\n(9\nU-\n\nMay 7, 11996\n\nSheet 6 of 11\n,514,889\n\nCase 9:02-cv-00058~JH Document I\n\nFHed 03/05/2002\n\nPage 37 of 101\n\nU.S. Patent\n\nC~J\nc-Is\n\nU-\n\nMay 7, : 1996\n\nSheet 7 of 11\n,514,889\n\nCase 9:02-cv-00058~JH Document I\n\nFHed 03/05/2002\n\nPage 38 of 101\n\nU.S. Patent\n\n\nK)\n(9\nU-\n\nMay 7, 1 1996\n\nSheet 8 of II\n,514,889\n\nCase 9:02-cv-00058~JH Document I\n\nFHed 03/05/2002\n\nPage 39 of 101\n\nU.S. Patent\n\n\n(9\nIL\n\nMay 7, 11996\n\nSheet 10 of 11\n,514,889\n\nCase 9:02-cv-00058~JH Document I FHed 03/05/2002 Page 40 of 101\n\n\nU.S. Patent May 7, 11996 Sheet 11 of 11 5,514,889\n-\n/\n/\n\n/\n(0 (`U\n(`U /\n\n\n/\n/\n/\n/\n/\nL\n(9\nU-\n-\n\n\nin\n\nCase 9:02-cv-00058:~H Document I FUed 03/05/2002\n\nPage4l of 101\nNON-VOLATILE SEMICONDUCTODR\nMEMORY DEVICE AND METHOD FFOR\nMANUFACTURING THE SAME\n\nBACKGROUND OF THE INVENTIONN\nThe present invention relates to an electricall)ly erasable\nand programmable read only memory (EEPROM)[) device as\na non-volatile semiconductor memory device andd a method\nfor manufacturing the same, and, more particulalarly, to an\nLEPROM device in which a high voltage is appblied to the\nchip during memory cell operation and a methciod for the\nmanufacturing the same.\nAlong with the progress of computer systems, tithe need for\nlarge-capacity non-volatile memories adaptable e to high-\nspeed operation, such as memory cards, has i increased.\nAmong these non-volatile memories, there hasis been an\nincreased need for EEPROMs comprised of a floaating gate\nand a control gate and which can electrically erase and\nprogram data. Therefore, a variety of cell stniolctures for\nEEPROMs have been suggested for providing hi~iigher inte-\ngration density, larger capacity and faster perfonrmance.\nA NAND-structured memory cell has been de~veloped in\norder to achieve cell area reduction without streressing the\nfabrication technology. An advanced NAND structtured flash\nEEPROM has been suggested (see \"A 2.3 urn2 Meiemory Cell\nStructure For NAND EEPROMs\" by R. Shirota eta al. IEDM,\n, pp 103-106).\nFIG.1 is a sectional view illustrating the abovve NAND-\nstructured EEPROM which is manufactured asis follows.\nFirst, a first P-well 2 (in a cell array region) and d a second\nP-well 3 (in a peripheral circuit region) are forzriined in the\nupper portion of an N-type semiconductor substratate 1. Then,\na cell array comprised of an EEPROM is formeted on first\nP-well 2, an NMOS transistor of the peripheral d circuit is\nformed on a portion of second P-well 3, and an N-'J-well 4 on\nwhich a PMOS transistor of the peripheral circuiiit is to be\nformed, is formed in a portion of second P-well 33. It' order\nto manufacture the above EEPROM, ions are i implanted\nthree times for forming three impurity-doped reregions (or\nbulks): one for forming first P-well 2 on which thee cell array\nis to be formed, one for forming second P-well 33 on which\nthe NMOS transistor of the peripheral circuit is fourmed, and\none for forming N-well 4 on which PMOS transisistor of the\nperipheral circuit is formed.\nFIG. 2 shows a portion of an equivalent circuit ddiagram of\nan EEPROM device using the aforementioned comnventionai\nEEPROM cell and an erase and write (or progrararn) opera-\ntion. The program operation of a selected cell, is ocanied out 50\nby charging electrons into the floating gate and riraising the\ncell's threshold voltage. This is accomplished byy applying\n.3 V to a selected bit line BL(1) of the cell arra~ay and 7 V\nto an unselected bit line BL(2) of the cell array as 8 a program\npreventing voltage, and applying 10 V to the u unselected ~\ncontrol gate and 18 V to the selected control gatite, respec-\ntively. The 18V applied to the selected cell's contriLrol gates is\ncoupled so that about 10 V is induced at the floatingig gate and\n.3 V is transferred to the selected cell's channelel. Then, a\nnearly 10 MeV field applied between the oppositcte sides of\na nearly 100 A-thick tunnel oxide layer whisich exists\nbetween the channel and floating gate, causes thdie floating\ngate electrode to be charged with electrons by ththe Fowler-\nNordheim (F-N) tunnelling effect. Thus, a datum i is written\ninto the selected memory cell. 65\nConversely, the erase operation, which is carricied out by\ndischarging the electrons within the floating gate electrode\nto thereby lower the threshold voltage of the cell, is accom-\nplished by applying 20 V to the P-well 2 on which the cell\narray is formed, opening the bit-line and source-line, and\ngrounding the control gate. Thereby, the electrons Within the\nS floating gate are discharged by the field between the ends of\nthe tunnel oxide layer. Here, in order to protect the transistor\nof the peripheral circuit which operates at +5 V (Vcc) from\nthe approximately 20 V applied to the P-well 2 of the cell\narray during the erase operation, transistors are formed on\nanother P-well 3 which is electrically isolated and indepen-\ndent of the P-well 2 of the cell array.\nA read operation is performed according to the data\ndetermination. The data is determined by the bit-line current\npath fluctuating between \"on\" and \"oft\" states according to\nthe positive or negative value of the threshold voltage of the\n* selected cells.\nFor manufacturing the above conventional NAND\nEEPROM device, a photolithography process for forming\nthe well structures is performed twice: First, that is, for\nforming a first P-well 2 on which a cell array is to be formed\nand a second P-well 3 on which the NMOS transistor of the\nperipheral circuit is to be formed; Second for forming an\nN-well 4 which is located within the second P-well 3, on\nwhich the PMOS transistor of the peripheral circuit is to be\n~ formed on the N-type semiconductor substrate 1.\nHowever, the conventional NAND EEPROM device as\ndescribed above exhibits certain drawbacks. First, since the\nN-type substrate 1 is applied with a high voltage concur-\n~ rently with the erase operation which applies 20 V to the\nP-well 2 on which the cell array exists, transistors cannot be\nformed directly on the N-type substrate 1. Also, since the\ntransistors of the peripheral circuit are formed on a P-well 3\nand an N-well 4 within this P-well 3, the bulk resistance is\nincreased. Accordingly, latchup and other deitorious elec-\ntrical characteristics occur.\n\nSU1~1MARY OF TIlE INVENTION\nFor solving the above-mentioned problems, an object of\nthe present invention is to provide a non-volatile memory\ndevice which can be manufactured by independently con-\ntrolling the bulk regions used in the cell array and peripheral\ncircuit regions thereof.\nAnother object of the present invention is to provide a\nsuitable method for manufacturing a non-volatile memory\ndevice.\nTo accomplish the aforementioned objects, the present\ninvention provides a semiconductor memory device com-\nprising: a semiconductor substrate of a first conductivity\ntype which is divided into a cell array region and a periph-\neral circuit region; a first impurity-doped region of the first\nconductivity type formed in the surface portion of the\nsemiconductor substrate in the cell array region, a second\nimpurity-doped region of a second conductivity type formed\nin the surface portion of the semiconductor substrate in the\ncell array region, the second impurity-doped region enclos-\ning the first impurity-doped region; and a memory cell\ncomprised of a fourth source region and a fourth drain region\nso formed on the surface portion of the first impurity-doped\nregion and of a floating etectrode formed on the first\nimpurity-doped region and a control electrode formed on the\nfloating electrode. It' the peripheral circuit region, the semi-\nconductor memory device may further comprise a third\nimpurity-doped region of the first conductivity type formed\nin a first surface portion of the semiconductor substrate in\nthe peripheral circuit region; a first MOS transistor com-\n,514,889\n\n* Case 9:02-cv-00058~JH\n\nDocument I\n\nFHed 03/05/200~\n,514,889\n\nPage 42 of 101\nprised of a first gate electrode formed on the thirird impurity-\ndoped region and first source and drain regionsis formed in\nsurface portions of the third impurity-doped regicion; a second\nMOS transistor comprised of second source e and drain\nregions formed in a second surface portion of thhe semicon- 5\nductor substrate in the peripheral circuit region aiand a second\ngate electrode formed on the semiconductor a substrate; a\nfourth impurity-doped region of the second ciconductivity\ntype formed in a third surface portion of the seitmiconductor\nsubstrate in the peripheral circuit region; a I third MOS\ntransistor comprised of third source and dritain regions\nformed in surface portions of the fourth impipurity-doped\nregion and a third gate electrode formed on 3 the fourth\nimpurity-doped region.\nIn order to achieve another object, the presersnt invention 15\nprovides a method for manufacturing a seirmiconductor\nmemory device comprising the steps of: providiling a semi-\nconductor substrate of a first conductivity type d defined into\na cell array region and a peripheral circuit regicion; forming\na second impurity-doped region of a second ciconductivity 20\ntype in a surface portion of the semiconductor r substrate in\nthe cell array region; forming a first impurity-ddoped region\nof the first conductivity type enclosed by the flrsrst impurity-\ndoped region, and forming a memory device on the first\nimpurity-doped region. The memory device is a formed by 25\nforming a first conductive layer pattern on the firsrst impurity-\ndoped region, forming an insulating layer pattelern covering\nthe first conductive layer pattern, forming a seco:ond conduc-\ntive layer pattern on the insulating pattern, patatterning the\nsecond conductive layer pattern, the insulating lalayer pattern 30\nand the first conductive layer pattern sequentiallyty, to thereby\nform a control gate electrode and a floating gatete electrode,\nand implanting an impurity into the first impipurity-doped\nregion to thereby form a source region and a draiain region of\nthe memory device.\nIn accordance with one embodiment of the preresent inven-\ntion, in the peripheral circuit region, a third implpuiity-doped\nregion of the first conductivity type in a first surfrface portion\nof the semiconductor substrate in the periphdieral circuit\nregion may be formed, and a fourth impurity-ddoped region\nof the second conductivity type in a third surfacme portion of\nthe semiconductor substrate in the peripheral cirrrcuit may be\nformed.\nThe second and fourth impurity-doped regioons are pref- ~\nerably formed by forming a first oxide layer o~n the semi-\nconductor substrate, forming an antioxidative Irlayer on the\nfirst oxide layer, forming a photoresist pattern c on the anti-\noxidative layer which exposes portions of the anmti-oxidative\nlayer where the second and fourth impurity-dopped regions 50\nare to be formed etching the exposed portions . of the anti-\noxidative layer, arid implanting a second conduuctivity type\nimpurity into surface portions of the semicon\ufffdtor sub-\nstrate via the etched portion of the anti-oxidativive layer.\nThe first and third impurity-doped regions ma~ay be formed ~\nby forming a first oxide layer and an anti-oxidatitive layer on\nthe semiconductor substrate excluding a portioran where the\nsecond impurity-doped region is formed, formiring a second\noxide layer on the second impurity-doped regionin, forming a\nphotoresist pattern exposing a portion of the se4econd oxide ~\nlayer where the first impurity-doped region is tao be formed\nand a portion of the anti-oxidative layer wher~re the third\nimpurity-doped region is to be formed, and then n implanting\na first conductivity type impurity into the seinniconductor\nsubstrate.\nAccording to one embodiment of the presenint invention,\nthe first conductivity type impurity is firstly impplanted at a\nfirst acceleration energy such that the first conductivity type\nimpurity penetrates the second oxide layer and the anti-\noxidative layer, and secondly implanted at a second accel-\neration energy such that the first conductivity type impurity\npenetrates the anti-oxidative layer but not the second oxide\nlayer.\nAccording to another embodiment of the present inven-\ntion, the second oxide layer is etched using the photoresist\npattern as an etching mask to thereby expose a surface\nportion of the semiconductor substrate where the first impu-\nrity-doped region is to be formed. The first conductivity type\nimpurity is firstly implanted at a first acceleration energy\nsuch that the first conductivity type impurity does not\npenetrate the anti-oxidative layer, and secondly implanted at\na second acceleration energy such that the first conductivity\ntype impurity penetrates the anti-oxidative layer.\nAccording to still another embodiment of the present\ninvention, the first conductivity type impurity is firstly\nimplanted at a first acceleration energy such that the first\nconductivity type impurity penetrates the anti-oxidative\nlayer but not the second oxide layer, the second oxide layer\nis etched using the photoresist pattern as an etching mask to\nthereby expose a surface portion of the semiconductor\nsubstrate where the first impurity-doped region is to be\nformed, and then the first conductivity type impurity is\nsecondly implanted at a second acceleration energy such that\nthe first conductivity type impurity penetrates the anti-\noxidalive layer.\nThe NAND-structured EEPROM according to the present\ninvention comprises EEPROM cells formed on the pocket\nP-well. The impurity concentration of the pocket P-well may\nbe controlled independently from the P-well which is\nformed in the peripheral circuit region. Therefore, an\nEEPROM device having two P-wells in the cell array region\nand the peripheral circuit region, respectively, of which the\nconcentrations may controlled according to the device char-\nacteristic and independently from each other, may be\nobtained.\nAlso, an NMOS transistor of the peripheral circuit region\nwhich is operated at a high voltage may be formed directly\non the P-type semiconductor substrate, thus enhancing the\nresistance thereof against the high voltage. In the meantime,\nthe characteristics of the NMOS transistor of the peripheral\ncircuit region which is operated at Vcc, are controlled by\nforming the NMOS transistor on the P-well of the peripheral\ncircuit region to thereby enhance the punch-through char-\nacteristics thereof.\n\nBRIEF DESCRIPTION OF THE DRAWINGS\nThe above object and other advantages of the present\ninvention will become more apparent by describing in detail\na preferred embodiment thereof with reference to the\nattached drawings in which:\nFIG. 1 is a sectional view showing the conventional\nNAND-structured EEPROM;\nFIG. 2 shows a portion of an equivalent circuit diagram of\nan EEPROM device using a conventional NAND-structured\nEEPROM cell and an erase and write (or program) operation\nthereof.\nFIG. 3 is a sectional view showing a structure of a\nNAND-structured EEPROM according to one embodiment\nof the present invention;\nFIGS. 4 through 12 are sectional views illustrating a\nmethod for manufacturing a NAND-structured EEPROM\n\nCase 9:02-cv-00058~jH Document I\n\nFHed 03/05/2002\n,514,889\n\nPage 43 of 101\ndevice according to a first embodiment of ththe present\ninvention;\nFIGS. 13 and 14 are sectional views illustrating g a method\nfor manufacturing a NAND-structured EEPRODM device\naccording to a second embodiment of the present i invention; 5\nFIG. 15 is a sectional view illustrating a metethod for\nmanufacturing a NAND-structured EEPROM~( device\naccording to a third embodiment of the present irinvention;\nFIGS. 16 and 17 are sectional views illustrating g a method\nfor manufacturing a NAND-structured EEPRODM device\naccording to a fourth embodiment of the present i: invention;\nand\nFIG. 18 is a sectional view illustrating a maiethod for\nmanufacturing a NAND-structured EEPRO?s'M device 15\naccording to a ftfth embodiment of the present innvention.\n\nDESCRIPTION OF THE PREFERREDO\nEMBODIMENT\nHereinafter, the present invention is to be denscribed in\nmore detail in reference with the attached drawiangs.\nFIG. 3 is a sectional view of a NAND-s-structured\nEEPROM device according to one embodimetent of the\npresent invention.\nInto a semiconductor substrate of a first conducttivity type\n(having a low concentration), e.g., P-type semisiconductor\nsubstrate 10, a second conductivity type impurity ((anion) is\nimplanted to thereby form a plurality of second coonductivity\ntype impurity-doped regions, i.e., N-wells. Thes~e N-wells 30\ninclude a first N-well 11 as a second impurity-dop.ped region\n(of a second conductivity type) formed in the cell array\nregion and a second N-well 12 as a fourth impuririty-doped\nregion (of a second conductivity type) in a thirird surface\nportion of the semiconductor substrate in the r peripheral 35\ncircuit region.\nA first conductivity type impurity is implanted i into a first\nN-well 11 of the cell array region, to thereby foiorm a first\nP-well 13 as a first impurity-doped region of a firsrst conduc-\ntivity type in the cell array region. On first P-wtvell 13, an\nEEPROM device having source and drain regionars (formed\nin the surface portions of first P-well 13) and a flooating gate\nformed on the first P-well 13 and a control gate fiformed on\nthe floating electrode, is formed. Since first ?`N-well 11\nencloses first P-well 13, the first P-well 13 is generally ~\nreferred to as a pocket P-well.\nIn the peripheral circuit region (having no cell arand includ-\ning second N-well 12) of P-type semiconductor suhibstrate 10,\nfor operating the cell array, a second P-well 14 as a third\nimpurity-doped region of a first conductivity type a is formed\nin a first surface portion of semiconductor substrtrate 10 by\nimplanting an impurity having a first conductivity.y type (the\nsame conductivity type as that of semiconductorir substrate\n) into a first portion of the peripheral circuit I region of\nsemiconductor substrate 10, while excluding ththe portion\nwhere second N-well 12 is formed.\nOn second P-well 14, a first MOS transistor (thhat is, first\nNMOS transistor) is formed which comprises fi\ufffd source\nand drain regions formed in surface portions a of second 60\nP-well 14, and a first gate electrode formed on seco;ond P-well\n.\nIn a second portion of the peripheral circuit: region of\nP-type semiconductor substrate 10 (excluding theie portions\nwhere second N-well 12 and second P-well 14 ar~e formed), 65\na second MOS transistor (second NMOS transistator) which\nhas a resistance against high voltage is formedd between\nsecond P-well 14 and second N-well 12. The second MOS\ntransistor includes second source and drain regions formed\nin second surface portions of semiconductor substrate 10\nand a second gate electrode formed on semiconductor sub-\nstrate 10.\nOn second N-well 12, a third MOS transistor (PMOS\ntransistor) having third source and drain regions in surface\nportions of second N-well 12 and a third gate electrode on\nsecond N-well 12, are formed.\nSince the second NMOS transistor is formed directly on\nthe P-type semiconductor substrate 10, the reverse bias\ncharacteristic between the N\ufffdped region of the NMOS\ntransistor and the P-type semiconductor substrate 10 having\na low impurity concentration is improved. The second\nNMOS transistor has a gate insulating layer whose thickness\nis thicker than that of first NMOS transistor. Also, using a\nP-type semiconductor \ufffdstrate 10 having a low impurity\nconcentration improves the body effect. An NMOS transis-\ntor of the peripheral circuit, which does not have a resistance\nessentially against a high voltage, is formed on second\nP-well 14, thus improving the punch-through characteristic\nof the short channel.\nThe characteristic of second N-well 12 on which a PMOS\ntransistor of the peripheral circuit is formed should be\ncontrolled according to the PMOS characteristic and the\nisolation characteristics thereof. Since second N-well 12 is\nformed simultaneously with the first N-well U wherein first\nP-well 13 (the pocket P-well) is to be formed, the change in\nthe characteristics of second N-well 12 should accompany\nthe characteristic change in first N-well U. This in turn\ncauses the characteristic of first P-well 13 to change. When\nsimultaneously forming first P-well 13 and second P-well 14\nby using the same photomask and the same ion-implantation\nprocesses, in order to optimize first ?-well 13 according to\nthe change in the characteristic of first N-well 11, the\ncharacteristic of second P-well 14 is undesirably changed.\nTo solve this problem, a photolithography process should be\nadded for forming first P-well 13 and second P-well 14\nseparately, which is undesirable.\nIn the present invention, a method for manufacturing the\nabove EEPROM device without an additional photolithog-\nraphy process is provided. Hereinafter, the method will be\ndescribed in detail with reference to the following embodi-\nments.\n\nEmbodiment 1\nFIGS. 4 through 12 are sectional views Illustrating a\nmethod for manufacturing a NAND-structured BEPROM\ndevice according to a first embodiment of the present\ninvention.\nFIG. 4 is a sectional view illustrating a step of fanning a\nfirst N-well 24 as a second impurity-doped region and a\nsecond N-well 24A as a fourth impurity-doped region in an\nupper surface portion of P-type semiconductor substrate 20.\nMore particularly, on a first conductivity type semiconductor\nsubstrate, for example, <100>-oriented P-type semiconduc-\ntor substrate 20 having a resistance of l8Licm, a first oxide\nlayer 21 is firstly formed to a thickness of 380 A, as in the\nconventional N-well formation. Thereafter, on first oxide\nlayer 21, a silicon nitride layer 22 as an anti-oxidative layer\nis formed by depositing silicon nitride to a thickness of about\nA via a conventional chemical vapor deposition (CVD)\nmethod. Thereafter, a photoresist is coated on the silicon\nnitride layer 22 to thereby form a photoresist film (not\nshown). Then, the photoresist film is exposed using a\n\n\nCase 9:02-cv-0005B~JH Document I F~ed 02./05/2002\n\nPage 44 of 101\nphotomask for forming first and second N-well ~ 24 and 24A\nand developed to form a first photoresist pattern (: (not shown)\nwhich exposes a portion of silicon nitride layer 222. Using the\nfirst photoresist pattern as an etching mask, a pre~edetermined\nportion of silicon nitride layer 22 is etched,, to thereby ~\nexpose surtice portions of semiconductor staubstrate 20\nwhere first N-well 24 of the cell array region and second\nN-well 24A of the peripheral circuit region are too be formed.\nThen, a second conductivity type impurity (N-ty~pe impurity)\nsuch as phosphor (P) is ion-implanted at ar dosage of\n.7x10'3 atoms/cm2 and at an acceleration voltitage of 150\nKeV, and then the first photoresist pattern is rematoved. Next,\nthe substrate is heat-treated at a temperature of a about 1150\ufffd\nC. for seventeen hours, to thereby not only a activate the\ndoped N-type impurity, but also diffuse the dopned impurity\ninto semiconductor substrate 20. As a result, firstat N-well 24\nof the cell array region and second N-well 2 24A of the\nperipheral circuit region arc formed.\nHere, during the heat-treatment, second oxideie layers 23\nand 23A of the respective cell array region and~d peripheral\ncircuit region are grown to a thickness of 4,500 ~A where the\nportions of silicon nitride layer 22 have been etctched.\nFIG. 5 is a sectional view for illustrating a step p of forming\na second photoresist pattern 26 for forming a flrsrst P-well as\na first impurity-doped region and a second P-weld as a third\nimpurity-doped region, and then firstly irnplannting a first\nconductivity type impurity. After the step of FIG. t. 4, a second\nphotoresist is coated on the resultant, thereby y forming a\nsecond photoresist film. The second photoresrsist film is\nexposed using a photomask for forming the first t and second\nP-wells and then developed to thereby formu a second\nphotoresist pattern for forming the first and seconnd P-wells\nwhich expose a portion (excluding the edge I portion) of\nsecond oxide layer 23 of the cell array region anind a portion\nof silicon nitride layer 22 where second P-weiell is to be\nformed. Then, a portion (excluding the surroutinding edge\nportions) of second oxide layer 23 of the cell aiarray region\nwhich is formed on first N-well 24 is wet-etchewd using an\noxide etchant, to thereby expose the surface, portion of\nsemiconductor substrate 20 where first N-well 224 has been\nformed. At this time, since silicon nitride layer 222 has a low\netching selectivity with respect to the oxide etcbiiant used in\nthe above wet-etching when compared to the se~econd oxide\nlayer 23, the exposed portion of silicon nitride layryer 25 is not\netched away. Thereafter, a first conductivity type ~ impurity (a\nP-type impurity such as boron) is firstly ion-imprplanted at a\ndosage of O.9~xi013 atoms/cm2 and at a low a acceleration\nvoltage of 50 KeV for forming the pocket P-wellill of the cell\narray region. Under the above conditions, tithe exposed\nportion of silicon nitride layer 22 prevents the im~purity from\ndoping into the substrate. Thus, only a portion of I first N-well\nis doped with P-type impurities via the exporsed surface\nportion of semiconductor substrate 20.\nFIG. 6 is a sectional view illustrating a step a of secondly\nimplanting a first conductivity type impurity to ththereby form 55\na first P-well 27 and a second P-well 27A. AAfter firstly\nimplanting the first conductivity type impurit)Iy at a low\nenergy, in order to form second P-well 27A of theie peripheral\ncircuit region, the same impurity as that firstly irimplanted is\nimplanted at a dose of I .5x10'3 atoms/cm2 at an a acceleration 60\nvoltage of 130 KeV (by which boron can penetstratc silicon\nnitride layer 22 having a thickness of about t 2,000 A),\nwithout removing second photoresist pattern a 26. After\nremoving second photoresist pattern 26, a drive,e-in step is\nperformed at a temperature of 1,150\ufffd C. for eiglght hours, to 65\ncomplete first (pocket) P-well 27 (as a first impwurity-doped\nregion) of the cell array area and second P-weltll 27A (as a\nthird impurity-doped region) of the peripheral circuit region.\nSecond P-well 27A is formed in a first surface portion of\nsemiconductor substrate 20 in the peripheral circuit region.\nFIG. 7 is a sectional view illustrating a step of forming a\nplurality of field oxide layers 28, a first gate oxide layer 29\nof the peripheral circuit region, aninnel oxide layer 30 of the\ncell array region, and first polysiicon layer pattern 31 for\nforming floating electrode of a NAND-structured EEPROM\ncell of the cell array. More particularly, after the drive-in step\nof FIG. 6, silicon nitride layer 22, the 20 remaining second\noxide layers 23 and 23A, and first oxide layer 21 are\nremoved. Then, via a conventional LOCOS process, a\nplurality of field oxide layer 28 for electrically isolating\ndevices are formed on semiconductor substrate 20, and then\na first gate oxide layer 29 is formed to a thickness of 200 A\non the whole surface portion of semiconductor substrate 20\nexcluding the portions where field oxide layers 28 have been\nformed. Next, in order to selectively form tunnel oxide layer\nin the cell array region which is thinner than first gate\noxide layer 29, a portion of first gate oxide layer 29 in the\ncell array region is removed via a conventional photolithog-\nraphy process. After removing the photoresist pattern used\nin the photolithography process, a tunnel oxide layer 30 is\nformed to a thickness of 100 A on first P-well of cell array\nregion. Thereafter, for forming a first conductive layer for\nforming a floating gate of an EEPROM device, a first\npolysilicon is deposited to a thickness of 1,500 A,to thereby\nform a first polysificon layer. The first polysilicon layer is\ndoped with phosphorous ions so as to have a sheet resistance\nof 1 OOGfl], thereby forming a first conductive layer for\nforming the floating gate. Then, the first conductive layer is\npatterned by a conventional photolithography process, to\nthereby form a first conductive layer pattern 31 on the cell\narray region.\nFIG. 8 is a sectional view illustrating an insulating layer\n~ pattern 32 covering first conductive layer pattern 31 and\nimplanting an impurity for controlling the threshold voltage\nof the peripheral circuit region. After the step of FIG. 7, an\noxide/nitride/oxide (ONO) layer is formed to a thickness of\nA/200 A130 A as an insulating layer on the whole\nsurface of the resultant. Thereafter, a third photoresist pal-\ntern 33 is formed which covers the cell array region and\nexposes the peripheral circuit region. Using third photoresist\npattern as an etching mask, the ONO film is etched to\nthereby form insulating layer pattern 32 covering first con-\nductive layer pattern 31. At this time, first gate oxide layer\n~ 29 which is formed on the peripheral circuit region, is\nsimultaneously removed, to thereby expose the surface of\nsemiconductor substrate 20 of the peripheral circuit region.\nThereafter, in order to control the threshold voltage of\n~ peripheral circuit region, while leaving third photoresist\npattern 33, a first conductivity type (P-type) impurity, such\nas boron, is ion-implanted through the exposed surface of\nsemi-conductor substrate 20 at a dosage of 2OxlOhm atoms!\ncm2 and at an acceleration voltage of 50 KeY, and then third\nphotoresist pattern 33 is removed.\nThereafter, an ion-implantation process is performed for\ndifferentiating the threshold of the NMOS transistors of the\nperipheral circuit. More particularly, a region where an\nNMOS transistor of the peripheral circuit is to be formed,\ni.e., second P-well VA, is exposed by forming a fourth\nphotoresist pattern (not shown) and then, a first conductivity\ntype (P-type) impurity, such as boron, is ion-implanted\nthrough the exposed region at a dosage of 6.OxlO\" ~ms!\ncni2 and at an acceleration voltage of 50 KeV. Thereafter, the\nfourth photoresist pattern is removed.\nThen, in order to form a normally on (operable) NMOS\ntransistor of the peripheral circuit directly on semiconductor\n,514,889\n\n\nCase 9:02-cv-00058-JH Document I\n,514,889\n\nFHed 03./05/20Q2\n\nPage 45 of 101\nsubstrate 20 (but not on second N-well 24A nctor second\nP-well 27A), a fifth photoresist pattern (not s shown) is\nformed to expose a portion of semiconductor sut.ibstrate 20\nbetween second P-well 27A and second N-well 2~24A in the\nperipheral circuit section. Through the exposed i portion, a ~\nsecond conductivity type (N-type) impurit~r such a as arsenic\n(As) is ion-implanted at a dosage of 2.2xlO 2atomsis/cm2 and\nat an acceleration voltage of 30 KeY. Next, the flflfth photo-\nresist pattern is removed.\nFIG. 9 is a sectional view illustrating a step off forming a\nsecond gate oxide layer 34 and partially removirlng second\ngate oxide layer 34 on second N-well 24A and secoond P-well\nA. After removing the fifth photoresist patterrrn, second\ngate oxide layer 34 is grown to a thickness of 2000 A via a\nthermal oxidation, on the whole surface of the e resultant\nexcluding the cell array region where insulating laytyer pattern\ncovers. Thereafter, a photoresist is coated on thete resultant\nto form a photoresist film, which is exposed usin~g a photo-\nmask and then developed to form a sixth photoresisist pattern\nexposing a portion of second gate oxide layer 334 formed 20\non both second N-well 24A and second P-well 2717A. Using\nsixth photoresist pattern 35 as an etching mask, theie exposed\nportion (which is formed in the peripheral circcuit region\nexcluding the region where a PMOS transistonr and an\nNMOS transistor having a resistance against a hig.gh voltage ~\nare to be formed) of second gate oxide layer 34 o on second\nP-well 27A and second N-well 24A, is partially rei~moved via\na conventional etching method.\nFIG. 10 is a sectional view illustrating a step otf forming\na third gate oxide layer 36 and forming gate electrcrodes 39a, ~\nb and 39c of the transistors of the peripheral cirrcuit and a\ncomposite conductive pattern 39b for forming coontrol gate\nelectrodes of the cell array EEPROMs. After remooving sixth\nphotoresist pattern 35, on the surface region o of second\nP-well 27A and second N-well 24A (where seccond gate ~\noxide layer 34 has been etched), third gate oxide Islayer 36 is\ngrown to have a thickness of about 180 A, via a conbnventional\nthermal oxidation process. During the thermal oxicidation for\nforming third gate oxide layer 36, second gate oxidrle layer 34\n(which is formed between second P-well 27A anind second ~\nN-well 24A and has not 5 been etched in the abo~ve step of\nFIG. 9) grows to a greater thickness than itsts original\nthickness of 200 A. Reference numeral 34' reprensents the\nadditionally grown second gate oxide layer.\nThereafter, on whole surface of the resultant, asia a second 45\nconductive layer for forming the control gate elecctrodes of\nthe cell array and the gate electrodes of the transisistor of the\nperipheral circuit, a second polysilicon is depositeLed to form\na second polysilicon layer having a thickness of abbout 1,500\nA, and then phosphorous is doped so that ththe second 50\npolysilicon layer has a sheet resistance of l00~)/D.]. Then, on\nthe second polysilicon layer, a refractory metal silicicide layer\nis formed by depositing a refractory metal siicidele (such as\nWSi) to a thickness of 1,500 A. Thereafter, the c composite\nconductive layer consisting of the second polysiliaicon layer 55\nand the refractory metal silicide layer is patterrrned via a\nphotolithography process using a seventh photoresisist pattern\n. Thus, first, second and third gate electrodes 39cia, 39b and\nc of first, second and third MOS transistors of tithe periph-\neral circuit consisting of first, second and third palttterns 37a, 60\nb and 37c of second polysilicon layer pattern i and first,\nsecond and third refractory metal siicide layer palattem 38a,\nb and 38c are formed. Also, a composite pattersrn 39d for\nforming control gate electrode of the cell arra~ay (which\ncovers insulating layer pattern 32) consisting of f a fourth 65\nsecond polysilicon layer pattern 37d and fourth r refractory\nmetal silicide layer pattern 38d, is formed.\nAccording to the above method, since the NMOS tran-\nsistor's gate fonned directly on P-type semiconductor sub-\nstrate 20 which operates at a high voltage of about 20 V\nduring the cell program/erase operation, has the thickly\ngrown second gate oxide layer 34 as a gate oxide layer, its\nresistance against high voltage is improved. In the mean-\ntime, the NMOS transistor formed on second P-well VA\nwhich operates at Vcc (which is a low voltage) uses third\ngate oxide layer 36 as a gate insulating layer (which is\nrelatively thin when compared to that of the NMOS tran-\nsistor formed directly on semiconductor substrate 20).\nTherefore, the punch-through characteristic the NMOS tran-\nsistor is improved.\nFIG. 11 is a sectional view illustrating a step of forming\na control gate electrode 42 and a floating gate electrode 31A\nof the cell array. After removing sixth photoresist pattern 40\nin FIG. 10, a seventh photoresist pattern 43 for forming the\ncontrol and floating electrode of an EEPROM which covers\nthe peripheral circuit region is formed on the resultant.\nUsing seventh photoresist pattern 43 as an etching mask,\nfourth refractory metal silicide layer pattern 38d, second\npolysilicon layer pattern 37d, insulating layer pattern 32 and\nfirst polysilicon layer pattern 31 are sequentially etched to\nthereby form the floating gate electrode 31A and control gate\nelectrode 42 (consisting of a fifth second polysilicon layer\npattern 37e and a fifth refractory metal silicide layer pattern\nk) of the cell array.\nFIG. 12 is a sectional view illustrating a step of complet-\ning the EEPROM cells and first, second and third MOS\ntransistors of the peripheral circuit. After removing seventh\nphotoresist pattern 43, N-type and P-type impurities are\nion-implanted to the resultant, and heat-treatment is per-\nformed for activating and diffusing the implanted ions via a\nconventional MOS transistor-forming process. Therefore, an\nEEPROM cell consisting of floating gate electrode 31A\nformed on first P-well 27, a control gate electrode 42 formed\non floating gate electrode 31A, and a fourth source and drain\nregions 44d is formed. In the peripheral circuit region, a first\nMOS transistor (an first NMOS transistor) consisting of first\ngate electrode 39a formed on second P-well VA, and first\nsource and drain regions formed in the surface portions of\nsecond P-well VA is formed. Also, on a second portion of\nsemiconductor substrate 20 in the peripheral circuit region,\na second MOS transistor (a second NMOS transistor) con-\nsisting of second gate electrode 39b and second source and\ndrain regions 44a formed in the second surface portions of\nsemiconductor substrate 20 in the peripheral circuit region,\nis formed. On second l5N-well 24A, a third MOS transistor\n(a PMOS transistor of the peripheral circuit) consisting of a\nthird gate electrode 39c formed on second N-well 24A and\na third source and drain regions 44c formed in the surface\nportions of second N-well, is formed. Thus, two NMOS\ntransistors and one PMOS transistor of the peripheral circuit\nare formed in the peripheral circuit region.\nSubsequent steps (not shown) such as a metallizalion\nprocess, a process for forming insulation interlayer, and a\nplanarization process, are performed to thereby complete the\nEEPROM device of the present invention, in the same\nmanner as in the case of a conventional memory device.\nTherefore, detailed descriptions thereof will be omitted.\n\n\nEmbodiment 2\nFIGS. 13 and 14 are sectional views illustrating a method\nfor manufacturing a NAND-structured EEPROM device\naccording to a second embodiment of the present invention.\n\nCase 9:02-cv-00058~JH Document I\n\nFHed 03./05/2002\n,514,889\n\nPage 46 of 101\nFIG. 13 is a sectional view illustrating a stctep of firstly\nimplanting a first conductivity type impurity.\nThe same procedure as shown in FIG. 4 of EEmbodiment\nI is performed. After forming second photoresisist pattern 26\nin the same manner as in Embodiment 1, booron is ion- ~\nimplanted at a dosage of l.5x1013 atoms/c1rn12 and at an\nacceleration energy such that the boron penetra-ates first and\nsecond oxide layers 21 and 23 and silicon nitritide layer 22,\nfor example, at an acceleration voltage of 240 ) KeY.\nFIG. 14 is a sectional view illustrating a step p of secondly ~\nimplanting a first conductivity type impurity. Aftfter the step\nof FIG. 13, boron is ion-implanted at a dose of 0 0.5xlO'3 and\nat an acceleration energy such that the boror3n penetrates\nsilicon nitride layer 22 but not second oxide layqer 23, i.e., at\nan acceleration voltage of 130 KeV. Thereafter, r, in the same 15\nmanner as in Embodiment 1, after removing setecond photo-\nresist pattern 26, a drive-in step is performined, to thus\ncomplete first (pocket) P-well 27 of the cell arrrray area and\nsecond P-well 27A of the peripheral circuit reg~gion.\nThereafter, subsequent steps are performed i in the same\nmanner as described with respect to FIGS. 7 thihrough 12 of\nEmbodiment 1, so the detailed descriptions therereof omitted.\n\nEmbodiment 3\nFIG. 15 is a sectional view illustrating a t method for\nmanufacturing a NAND-structured EEPRCOM device\naccording to a third embodiment of the presenht invention.\nFIG. 15 is a sectional view illustrating a step p of implant-\ning a first conductivity type impurity. In Embodiliments I and\n, the first conductivity type impurity is implaninted via two\nimplantation steps. However, in the present emboodiment, the\nfirst conductivity type impurity is implanted juslst once.\nAfter forming second photoresist pattern 26 wind removing\nthe exposed second oxide layer 23 by the wet-etetching in the\nsame manner as in Embodiment 1, for forming g first P-well\nand second P-well VA, boron is implanted ~ at a dose of\nI .5xl 013 atoms/cm2 and at an acceleration energgy such that\nthe boron penetrates silicon nitride layer 22, for r example, at\nan acceleration voltage of 240 KeV. With cbhanging the\nthickness of silicon nitride layer 22, the doped animount of the\nimpurity (that is, boron) which forms second 1 P-well 27A\nmay be controlled.\nThereafter, the subsequent steps are perforirmed in the\nsame manner as in Embodiment 1 (i.e., thosise shown in\nFIGS. 7 through 12).\n\nEmbodiment 4\nFIGS. 16 and 17 are sectional views illustratidng a method\nfor manufacturing a NAND-structured EEPR(~OM device\naccording to a fourth embodiment of the presersnt invention.\nFIG. 16 is a sectional view illustrating a stetep of firstly\nimplanting a first conductivity type impurity. Aftfter perform-\ning the step of FIG. 4 of Embodiment 1, second.d photoresist\npattern 26 is formed in the same manner as in EEmbodiment\n. Thereafter, boron is ion-implanted at a dosage e of l.5x1013\natoms/cm2 and at an acceleration energy suchh that boron\npenetrates silicon nitride layer 22 but not secondd oxide layer\n, for example, at an acceleration voltage of 2240 KeV.\nFIG. 17 is a sectional view illustrating a step a of secondly\nimplanting a first conductivity type impurity. Aftfter the step\nof FIG. 16, the exposed portion of second oxidele layer 23 is\nremoved by the wet-etching, and then boron n is ion-im-\nplanted at a dosage of 1.Oxl 013 and at an acceleraation energy\nsuch that boron penetrates silicon nitride la~ayer 22, for\nexample, at an acceleration energy of 240 KeV. Thereafter,\na drive-in step is performed in the same manner as in\nEmbodiment 1, to thereby form first P-well 27 and second\nP-well 27A.\nThe subsequent steps are performed in the same manner\nas those of FIGS. 7 through 12. Accordingly, the detailed\ndescriptions thereof are omitted.\nEmbodiment 5\n\nFIG. 18 is a sectional view illustrating- a method for\nmanufacturing a NAND-structured EEPROM device\naccording to a fifth embodiment of the present invention.\nIn the present embodiment, controlling the concentration\nof the impurity for forming first P-well 27 and second P-well\nA separately and independently, is 5 unnecessary.\nFIG. 18 is a sectional view illustrating a step of implant-\ning a first conductivity type impurity. After performing the\nstep of FIG. 4 of Embodiment 1, nitride layer 22 (which is\nused as an anti-oxidative layer) and first oxide layer 21 are\nremoved by wet etching, thereby exposing the whole surface\nof semiconductor substrate 20. Thereafter, an oxide layer\nB is grown to a thickness of about 500 A via a conven-\ntional thermal oxidation. Then, second photoresist pattern 26\nis formed in the same manner as in Embodiment 1, to\nthereby expose the portions of oxide layer 23B where first\nP-well and second P-well are to be formed.\nNext, boron is ion-implanted at a dosage of l.5x10'3 and\nat an acceleration energy such that boron penetrates oxide\nB.\nThe subsequent steps are performed in the same manner\nas those of FIGS. 7 through 12. Accordingly, the detailed\ndescriptions thereof are omitted.\nThe NAND-stnictured EEPROM device according to the\npresent invention comprises EEPROM cells formed on a\npocket P-well. The impurity concentration of the pocket\nP-well is controlled independently form the P-well formed\nin the peripheral circuit region. Therefore, an EEPROM\ndevice having two P-wells in the cell array region and the\nperipheral circuit peripheral circuit region of which the\nconcentrations may controlled according to device charac-\nteristics and independently from each other, can be obtained.\nAccording to one embodiment of the present invention, an\nNMOS transistor of the peripheral circuit region which is\n~ operated at a high voltage is formed directly on the P-type\nsemiconductor substrate. Therefore, the resistance thereof\nagainst the high voltage is enhanced. Further, an NMOS\ntransistor of the peripheral circuit region which is operated\nat Vcc, is formed on the P-well of the peripheral circuit\nregion the characteristics of which are controlled indepen-\ndently from the PlO well of the cell array region. This\nenhances the punch-through characteristic.\nAlso, according to a method for manufacturing a NAND\nstructured EEPROM memory device, using only a twice-\nperformed photolithography process may separately and\nindependently control the characteristics of the P-wells of\nthe cell array region and the peripheral circuit region.\nTherefore, the characteristics of the P-wells are differunti-\nated so that the transistor characteristic of the peripheral\ncircuits can be differentiated.\nConsequently, the present invention can provide a non-\nvolatile semiconductor memory device having an excellent\ncharacteristic in spite of the shortened steps of the whole\nprocess.\nWhile the present invention has been particularly shown\nand described with reference to particular embodiments\n\nCase 9:02-cv-00058-J~H Document I F~ed 03./05/2002\n,514,889\n\nPage 47 of 101\nthereof, it will be understood by those skilled in tithe art that\nvarious changes in form and details may be effecteted therein\nwithout departing from the spirit and scope of thete invention\nas defined by the appended claims.\nWhat is claimed is:\n. An EEPROM semiconductor memory devicere compris-\ning:\na semiconductor substrate having a first conductltivity type,\nsaid semiconductor substrate being divided I into a cell\narray region and a peripheral circuit region; i;\na first impurity-doped region having said first c conductiv-\nity type formed in a first surface portioun of said\nsemiconductor substrate in said cell array rengion;\na second impurity-doped region having a secon.nd conduc-\ntivity type formed in said first surface porticion of said\nsemiconductor substrate in said cell array reugion, said\nsecond impurity-doped region enclosing said first\nimpurity-doped region;\na memory cell comprising: 20\na memory source region and a memory drrrain region\nformed on a surface portion of said first t impurity-\ndoped region, and\na floating electrode formed on said first impuiurity-doped\nregion and a control electrode formed on said float- ~\ning electrode;\na third impurity-doped region having said flrsrst conduc-\ntivity type formed in a first surface portioton in said\nperipheral circuit region of said semiconduluctor sub-\nstrate; 30\na first MOS transistor comprising:\nfirst source and drain regions formed in i respective\nsurface portions of said third impurity-doptped region,\nand\na first gate electrode formed on said third I impurity- 35\ndoped region; a second MOS transistor cotomprising:\nsecond source and drain regions formed c directly in\nrespective second surface portions in saraid periph-\neral circuitregion of said semiconductorir substrate,\nand\na second gate electrode formed on said serrmiconduc-\ntor substrate;\na fourth impurity-doped region having said se~cond con-\nductivity type and being formed in a thirird surface\nportion in said peripheral circuit region of s said semi- ~\nconductor substrate; and\na third MOS transistor comprising:\nthird source and drain regions formed in i respective\nsurface portions of said fourth impuririty-doped ~\nregion, and\na third gate electrode formed on said fourth ti impurity-\ndoped region.\n. The EEPROM semiconductor memory devicice accord-\ning to claim 1, wberein said first and second MOS tI transistors\nare NMOS transistors, and said third MOS transisistor is a\nPMOS transistor.\n. The EEPROM semiconductor memory devicice accord-\ning to claim 1, wherein a first gale insulating fitilm of said\nsecond MOS transistor is thicker than a second ~ gate insu-\nlating film of said first MOS transistor.\n. The EEPROM semiconductor memory device accord-\ning to claim 1, wherein said second MOS transistor is\nformed between said first MOS transistor and said third\nMOS transistor.\n. The EEPROM semiconductor memory device accord-\ning to claim 1, wherein a first impurity concentration of said\nfirst impurity-doped region is controlled independently from\na second impurity concentration of said third impurity-\ndoped region.\n. The EEPROM semiconductor memory device accord-\ning to claim!, wherein said first conductivity type is P-type\nand said second conductivity type is N-type.\n. An EEPROM semiconductor memory device compris-\ning:\na P-type semiconductor substrate which is divided into a\ncell array region and a peripheral circuit region;\na first P-well formed in a surface portion in said cell array\nregion of said semiconductor substrate;\na first N-well formed in said surface portion in said cell\narray region of said semiconductor substrate, said first\nN-well enclosing said first P-well;\na memory cell comprising:\na memory source region and a memory drain region\nformed on a surface portion of said first P-well,\na floating electrode formed on said first P-well, and\na control electrode formed over said floating electrode;\na second P-well formed in a first surface portion of said\nperipheral circuit region of said semiconductor sub-\nstrate;\na first NMOS transistor comprising:\nfirst source and drain regions formed in respective\nsurface portions of said second P-well, and\na first gate electrode formed on said second P-well;\na second NMOS transistor comprising~.\nsecond source and drain regions formed directly in a\nsecond surface portion of said peripheral circuit\nregion of said semiconductor substrate, and\na second gate electrode formed on said second surface\nportion of said peripheral circuit region of said\nsemiconductor substrate;\na second N-well formed in a third surface portion of said\nperipheral circuit region of said semiconductor sub-\nstrate; and\na PMOS transistor comprising:\nthird source and drain regions formed in a surface\nportion of said second N-well, and\na third gate electrode formed on said second N-welL\n. The EEPROM semiconductor memory device accord-\ning to claim 7, wherein said first N-well and said second\nN-well are formed substantially simultaneously, and said\nfirst P-well and said second P-well are formed substantially\nindependently.\n. The EEPROM semiconductor memory device accord-\n~ ing to claim 1, wherein said first impurity-doped region and\nsaid third impurity-doped region are formed substantially\nsimultaneously, and said second impurity-doped region and\nsaid fourth impurity~doped region are formed substantially\nindependently.\n\n* * * * *\n\n[54] NONVOLATILE SEMICONDUCTOR\nMEMORY\n\n[751 Inventors: Kang D. Suh, Ahnyang; Jin K. Kim,\nSeoul; Jeong H. Chot, Kwacheon, all\nof Rep. of Korea\n\n[73] Assignee: Samsung Electronics Co., Ltd.,\nSuwon, Rep. of Korea\n\n[21] Appl. No.: 441,477\n\n[22] Filed: May 15, 1995\n\nRelated U.S. Application Data\n[62] Division of Ser. No. 171,300, Dec. 22, 1993. Pat. No.\n,473,563.\n[30] Foreign Application Priority Data\nJan. 13, 1993 [KR] Rep. of Korea 390/1993\n[51] mt. Cl.6 G11C 16/00\n[52] U.S. Cl .. 3651185.33; 365/185.29;\n/218\n[58] Field of Search .. 365/185, 218,\n/900, 185.29, 185.33\n\n[56] References Cited\n\nU.S. PATENT DOCUMENTS\n,811,294 3/1989 Kobayashi ..... ..... 365/185.22\n,949,309 8/1990 Rao .......... 365/185.33\n,047,981 9/1991 Gill et al 365/185.33\n,053,990 10/1991 Kreifcls -. ..... 364/900\n,126,808 6/1992 Monlalvo at al .. 365/185.33\n,185,718 2/1993 Rinerson et Si 3651185.33\n,191,556 3/1993 Radjy .. 365/185.33\n,245,570 9/1993 Fazio et Si ..... 365/185.33\n,270,980 12/1993 Pathak at at ~ 365/185.33\n,297,081 3/1994 ChaUa .._...~... ....... ... 365/185\n,408,429 4/1995 Sawada ....... 365/185.33\n\nFOREIGN PATENT DOCUMENTS\n/1993 European Pat. Off..\n/1992 Germany.\n-17445 11/1991 Rep. of Korea.\n/1993 United Kingdom.\n\nOT}IER PUBLICATIONS\nMonodomi et Si, \"New Device Technologies for 5V.-Only\nMb EEPROM With NAND Structure Cell\", CH2528-8/\n/0000-0412 IEEE (1988) pp. IEDM 88-412-IEDM\n-415.\nKinsawa et a], \"A NAND Structured Cell with a new\nProgramming Technology for Highly Reliable 5V-Only\nFlash EEPROM\". 1990 Symposium on VLSI Technology, 4\nJun. 1990, CH 2874-6, 90/0000-0129 1990 IEEE, Hono-\nlulu, US pp. 129-130.\n(List continued on next page.)\nPnmary Examiner-Tan T. Nguyen\nAttorney, Agent, or Finn-Cushman, Darby & Cushman,\nLLP.\n[57] ABSTRACT\nA nonvolatile semiconductor memory device comprising an\narray of cell units, each cell unit including at least one\nmemory transistor which has a floating gate and a control\ngate, the array being divided into a plurality of memory\nblocks each having a certain number of cell units. A selected\nmemory block is erased by an erase voltage applied to a\nsemiconductor substrate while unselected memory blocks\nare prevented from erasing by capacitive coupling of the\nerase voltage to floated word lines connected to control gates\nof memory transistors of the unselected memory blocks. In\na program mode where a program voltage is applied to a\nselected word line of a selected memory block and a pass\nvoltage is applied to unselected word lines of the selected\nmemory block, channel regions and source and drain junc-\ntions of memory transistors of cell units in the selected\nmemory block are charged to a program inhibition voltage.\nChannel regions and source and drain junctions of cell units\nassociated with memory transistors programmed to the other\nbinary data are discharged to be programmed while those of\ncell units associated with nonprogrammed memory transis-\ntors are maintained to the program inhibition voltage to\nprevent programming.\nClaims, 18 Drawing Sheets\n\nSKI\n\nBK2 -10\nBLOCK\n~ sO.ECfloN\nCON1ROI.\nCIRCIJI1\n<1024\nCCI.\nCCI.\nI1~BL2 . Oi.2O48_-~\nCCL2 ____________________________\n~anERMINA~QN~~ DATA REGI~R AND SENSE AMP Hi 2\nCONTROl.\nGATE ORIWIC\nORCurT\nCSL\nSOURCE\nCOUJUN DECODER AND 14\nUNEDRTA1NC\nSELECTiON CIRCUIT r~\nCRICUIT ________________________\nPROCRAMUING\nINPIJT/OLITPUT BUFFER His\nI CIRCUIT __________________________\nii, Li\n/0 I 1/0 2 1/0 3 . . . I/O 7 1/0 B\n\nCase 9:02-cv-00058-~JH Document I\n\n\nUnited States Patent [19J\nSub et al.\n\nFHed 03105/200a Page 48 of 101\n.1111111111111111111111111111111!\nUSO0554~34lA\n\n[11] Patent Number: 5,546,341\n[45] Date of Patent: Aug. 13, 1996\n\nEXHiBIT\n\nCase 9:02-cv-00058~JH\n\nDocument I\n,546,341\nPage 2\n\nFHed 03/05/20il2\n\nPage 49 of 101\n\nOTHER PUBLICATIONS\n\nIwata et a]., \"A High-Density NAND EEPROM with\nBlock-Page Programming for Microcomputer Applica-\ntions\", IEEE Journal of Solid-State Circuits, vol. 25,2, Apr.\n, pp. 417-423.\n\nMomodomi et a], \"A 4-Mb NAND EEPROM with `light\nProgrammed V1 Distribution\", IEEE Journal of Solid State\nCircuits, vol. 26, No. 4, Apr. 1991, pp. 492-495.\nEndoh eta] \"A study of high performance NAND structural\nEEPROMs\", IEICE Transactions on Electronics, vol. E75C,\nNo. II, Nov. 1992, Tokyo, JP pp. 1351-1356.\n\nPage 50 of 101\n\nCase 9:02-cv-00058-J-H Document I\n\nF~ed 03./05/200~\n\nU.S. Patent\n\nAug. 13, 1996\n\nSheet 1 of 18\n\n\nBK1\n,546,341\n-\n\nBLOCK\nSELECTION\nCONTROL\nCI RCU IT\n\nBK2\n\nH CGL8\nCCL1-1 I\nI h-CGL2\n\nBL1-\n\n\nCONTROL\nGATE DRMNG\nCIRCUIT\n\nCSL-\nK1024\n\n\n\nLHBL3 . .. . BL2048-\nThBL2\n\n\nDATA REGISTER AND SENSE AMP\n~--\n\n\n\n\nCOLUMN DECODER AND\nSELECTION CIRCUIT\n\n\n)\n\nINPUT/OUTPUT BUFFER\n-\n-\n-\n\n.-1O\n\n\n-12\n\n\n-14\n\n\nH6\n\nSOURCE\nLINE DR IVING\nCIRCUIT\n\nPROGRAMMING\nDETERMINA11ON\nCIRCUIT\n\n\nci,\n\ntL\n\nci,\n\n~L\n\nci,\n\nI/O 1\n\nI/O 2 I/O 3 *\n\nI/O 7 I/O 8\n\nFIG. I\n\nCase 9:02-cv-00058-JH Document I\n\nFHed 03105/200Z Page 51 of 101\n\nCGL1~-~[-- T~I\n\nCGL2..-~._~[_ -~7II~\n~\nCGL4'~-~-_-~- ~7!I\n\nCGL5~-~- ~~~7II\n\nCC\nCG ~\nCG ~\nSGL1 -2~~--~----J1_.\n\nBT1O~'\nSGL2-2~.-..--~.--_-1~_\n\nCGL8~\nM8\nCGL7~-~_J~~ HI\n\n~\n\n~\n~\n~\nCGL2~-J~- HI\n\nCCL1~-~-__J~_. \n\nSCL2-1'_--~___J~_ \n\n(T\\ ST1\n___ - BSC2 34-2 - BLL-21 BLk-256\n\nU.S. Patent Aug. 13, 1996 Sheet 2 of 18\n,546,341\n/ CBL(t5.=1,2 ,8)\n\nFIG. 2a\n\nCase 9:02-cv-00058~H Document I\n\nFHed 03/05/2002 Page 52 of 101\n\nU.S. Patent\n\nAug. 13, 1996\n\nSheet 3 of 18\n,546,341\nI/oL\n\nFIG. 2b\n\nCase 9:02-cv-00058-JH Document I\n\nFHed 03/05/2002 Page 53 of 101\n\nU.S. Patent\n\nCSL\n\nAug. 13, 1996\n\nSheet 4 of 18\n\n\nWL1\n\n\nWL2\n\n\nWL7\n\n\nWL8\n\n\nSL2\n,546,341\n\n\nBL\n\nSL1\n\nFIG. 3\n\nCase 9:02-cv-00058~H Document I\n\nFHed 03/05/2002\n\nPage 54 of 101\n\nU.S. Patent\n\n\nN\n-J\nDI ~\nzN~~\n\nAug. 13, 1996\n\nSheet S of 18\n,546,341\n\nN N\n\nN\n\nCase 9:02-cv-00058-iH Document I\n\nFHed 03/05/2002\n\nPage 55 of 101\n\nU.S. Patent\n\nAug. 13, 1996\n\nSheet 6 of 18\n\n\nN\n,546,341\n\nC)\nC!)\n\nE\n~\n>\n\n-J\nC)\nC',\n\nN\nr..)\nN\n\n\n,-~\n~\n>\n\nN\n\nN\n\n\n/\n\nN\n\n\nfl ~\nLr~-~\nuJ\n\n~0.'-\n\n(0\n\nCo\n\n`N\n\n.J.\nOD\n\nr~~j\nN\n~\n\n- -\n\n* . Case 9:02-cv-00058-JH Document I\n\nFHed 03/05/2002\n\nPage 56 of 101\n\nU.S. Patent\n\n\nN\n\nII\n.4,..\n\nAug. 13, 1996\n\nSheet 7 of 18\n,546,341\n\n-J\n\n\nN\naD\n\naD\nN\n\ncoo~\n<1<1<\nL. L\nCoO)O\n\nCase 9:02-cv-00058-JH Document I\n\nFHed 03/05/2002\n\nPage 57 of 101\n\nU.S. Patent\n\n\nPGM\n\nAug. 13, 1996\n\nSheet 8 of 18\n\n\nI\n,546,341\n\nFIG.\n\n\n~4H\nVcc\n\n\nFIG.\nFIG.\nct\n\n/\n\nVpi\nCase 9:02-cv-00058~H Document I\n\nFHed 03/05/2002\n\nPage 58 of 101\n\nU.S. Patent\nAug. 13, 1996\n\nSheet 9 of 18\n\n\nVcc\n\n,546,341\n\nFIG. 86\n\n\nERA\n\nSLE 06\n\nPGM\n\n\nFIG. 8c\n\nOv 4\n\nTO 162\nCase 9:02-cv-00058-JH Document I\n\nFHed 03/05/2002 Page 59 of 101\n\nU.S. Patent\n\nAug. 13, 1996\n\nSheet 10 of 18\n,546,341\n\nFP1\nFP2\nFF3\nFP4\n\nFP5\nFP6\nFP7\nFP8\n\nFIG. 9a\n\nPDS\n\nVcc\n\n(k=1,2 ,8)\n\n-220\nHd72Hd\n,1$\n\n\n/\n 224\n\n\n~\nSFP\n\n\nFIG. 9b\n\nFIG. 9\n\nCase 9:02-cv-00058-JH Document I\n\nFHed 03/05/2002 Page 60 of 101\n\nU.S. Patent\nV\nWE\n____ 5V\n\n\nERA\n\nPGM 5V\n\nSLEE 5V\n\nVpgrn\n\nVpas\n\nOR\n\nXd\n\nBLJK\n\nDS\n\nVera\n\n\nDCB\n\nAug. 13, 1996 Sheet 11 of 18 5,546,341\n\nSBL\n\nFIG. 10\n\nCase 9:02-cv-00058-JH Document I\n\nFHed 03/05/2002 Page 61 of 101\n\nU.S. Patent\n- 5V\n~W~Eov\n____ 5V\n\n\nPGM\n____ 5V\nSLE\n- 5V\nXdOV\n____ 5V\nBLK\n- 5V\nDS\n____ 5V\nERA\nV\nORov\n\nVpgm\n\nVpas\n\nVpi\n\nOi\n\nSBL\n\nDCB\n\nAug. 13, 1996 Sheet 12 of 18 5,546,341\n\nFIG. 11\n\nCase 9:02-cv-00058~H Document I FHed 03/05/2002 Page 62 of 101\n\n\nU.S. Patent Aug. 13, 1996 Sheet 13 of 18 5,546,341\n\n\nSBL~J\n\n\nDCB~J 1\n\n\n_5V-'\n\n\nDSov\ni~ I _________________I\n\n\ufffd1\n\n\nj2\nFIG. 12\n\nCase 9:02-cv-00058-JH Document I\n\nFHed 03/05/2002 Page 63 of 101\n\nU.S. Patent\n\n\nCGL1\n\nCGL2\n\nCC U\n\nCG L4\n\nCGL5\n\nCGL6\nCGL7\n\nCGL8\n\nUSGL(~\n\nAug. 13, 1996\n\nSheet 14 of 18\n,546,341\n\nFIG. iSa\n-i. BSC1\n(i.=1,2,3 ,512.)\nCSL\n\nBLk-1I BLk-2~ BL~-256I\n___ SBK~ I I I\n- - I - - I\n\nCase 9:02-cv-00058-JH Document I\n\nFHed 03/05/2002\n\nPage 64 of 101\n\nU.S. Patent\n\nAug. 13, 1996\n\nSheet 15 of 18\n,546,341\n\n..~\nC!)\nC/)\n\nN\nLI)\n\n\nN\n\nII\n..~\n\n-J\nCr)\n-J\n\n~f)\n~- r4.)\nI~4:J\n\nE\n~\n>\nD\n)\nre)\nD\n\n`4-)\n~~\n\n~-\n\n<p0\nto\np0\n\n-`a\n<\n\nLx-\np-'-\n<\n\n\nIC)\np0\n\nh~\ufffd\n>\nD\nN,\n\nN\n~4)\n\nCase 9:02-cv-00058~.tH Document I\n\nFHed 03./05/200a\n\nPage 65 of 101\n\nU.S. Patent\n\n\nC\nN\nND\n\nAug. 13, 1996\n\nSheet 16 of 18\n\n\n-J\n(j)\n,546,341\n\n-J\nO~)\nN\nND\nN\nND\n(0\nND\n\n\n(0\n\nN\nN\nND\nN\n(0*\nND\nU.S. Patent\n- 5v\nWE Cv\n- 5V\nWEm\n____ 5V\nERA Cv\n\nPGM 5V\n\nVpgm 5V-\n\nVpas\nV-\nOR\n\n- 5V-\nXd CV\n\n____ 5V\nBLIC\n\n- 5V\nDS\nV\nVera ___\n\nDCB 5V\nOv\n\nCase 9:02-cv-00058-JH Document I\n\nFHed 03/05/2002 Page 66 of 101\n\nAug. 13, 1996 Sheet 17 of 18\n,546,341\n\n\n\n\n\nU-\n\n\n-P\n\n~3 ~4 t5\n\n\n\n~1 ~2\n\nFIG. 16\n\nCase 9:02-cv-00058-JH Document I FHed 03/05/2002 Page 67 of 101\n\n\nU.S. Patent Aug. 13, 1996 Sheet 18 of 18 5,546,341\n\n\nWEm\n\n____ 5V\nPGM ov\n\n\nI\nERA5V __--\n\nOR 111111k 1JI.I -\nV I I\nVpgm _____\n\n\nVpas~ j__\nV -\nOi ov I\nV ________________________I\nSBL ____ __I--\n\n\nDCB~ Ti\n\n~2 ?~3\n\n\nFIG. 17\n\nCase 9:02-cv-00058-JH\n\nDocument I\n,546,341\n\nFHed 03/05/2002\n\nPage 68 of 101\nNONVOLATILE SEMICONDUCTOR\nMEMORY\n\nThis is a division of application Ser. No. 07/171,300,\nfiled Dec. 22, 1993, now U.S. Pat. No. 5,473,563. 5\n\nFIELD OF THE INVENTION\nThe present invention relates to electrically erasable and\nprogrammable nonvolatile semiconductor memories and.\nmore particularly, but not exclusively, to electrically eras-\nable and programmable nonvolatile semiconductor memo-\nries with NAND structured cells.\n\nBACKGROUND OF THE INVENTION\nVarious systems controlled by recent computers or micro-\nprocessors require the development of an electrically eras-\nable and programmable read-only memory (hereinafter\nreferred to as a EEPROM) of a high density. Particularly,\nsince the use of a hard disk with a rotary magnetic disk as\na secondary storage occupies a relatively large area in a\nportable computer system such as a battery-powered com-\nputer system of notebook size, system designers take much\ninterest in the development of EEPROMs of high density\nand high performance occupying a smaller area. To achieve\na high density EEPROM, it is a major problem to reduce the\narea occupied by memory cells. To solve such a problem, an\nEEPROM has been developed which contains NAN!) stnlc-\nwred cells being capable of decreasing the number of\nselection transistors per cell and contact holes coupled with\na bit line. Such a NAND structured cell is disclosed in the\nIEDM, pp 412 to 415, 1988 under the title of \"NEW\nDEVICE TECHNOLOGIES FOR 5V-ONLY 4 Mb\nEEPROM WITH NAND STRUCTURE CELL\". This\nNAN!) structured cell (hereinafter referred to as a NAND\ncell unit or a NAND cell) is comprised of a first selection\ntransistor whose drain is connected to the corresponding bit\nline via a contact hole; a second selection transistor whose\nsource is connected to a common source line; and eight\nmemory transistors whose channels are connected in series\nbetween the source of the first selection transistor and the\ndrain of the second selection transistor. The NAN!) cell is\nformed on a p-type semiconductor substrate, and each\nmemory transistor includes a floating gale layer formed on\na gate oxide layer over a channel region between its source\nand drain regions and a control gate layer separated from the\nfloating gate layer by an intermediate insulating layer. To\nprogram of write a selected memory transistor in the NAND\ncell, an operation of simultaneously erasing all memory\ntransistors therein must be followed by the programming\noperation. The simultaneous erasure is performed by apply-\ning 0 volts to the bit line and raising the gate of the first\nselection transistor and control gates of all memory transis-\ntors to 17 volts. This causes all memory transistors to be\nchanged into enhancement mode transistors which are\nassumed as binary logic \"1\" programmed transistors. To\nprogram a selected memory transistor to a binary logic \"0\"\nvolts are applied to the bit line, the gate of the first\nselection transistor and control gates of memory transistors\nbetween the first selection transistor and the selected\nmemory transistor, while 0 volts are applied to the control\ngate of the selected memory transistor, control gates of\nmemory transistor between the selected memory transistor\nand the common source line, and the gate of the second\nselection transistor. Thus, the selected memory transistor is\nchanged into a depletion mode transistor by the Fowler-\nNordheim tunneling (F-N tunneling) of holes from its drain\nto its floating gate. However, the problem of programming\nin this manner is that a portion of the gate oxide of the\nselected memory transistor is subjected to a stress induced\nby application of the high voltage to its drain, and the\npartially stressed gate oxide causes leakage current to flow.\nThis results in degrading more and more the data retention\ncapability of the memory cell according to an increase of the\nnumber of cycles of erasing and/or programming, thereby\nreducing the reliability of the EEPROM. To solve this\nproblem, an improved device structure, in which the NAND\ncells are formed on a p-type well region imbedded in an\nn-type semiconductor substrate, and further improved eras-\ning and programming technologies utilizing the improved\ndevice structure are disclosed in the symposium on VLSI\nTechnology, pp 129 to 130, 1990 under the title of \"A NAN!)\nSTRUCTURED CELL WITH A NEW PROGRAMMING\nTECHNOLOGY FOR HIGHLY RELIABLE 5V-ONLY\nFLASH EEPROM\".\nErasure of all memory transistors in this NAND cell is\nperformed by applying 0 volts to all control gates and a high\npotential of 20 volts to the p-type well region and the n-type\nsubstrate, thereby uniformly extracting electrons from their\nfloating gates to the well region. As a result, each memory\n~ transistor has a threshold voltage of about -4 volts which\nrepresents a state of depletion mode, i.e. a logic \"0\". To\nprogram a selected memory transistor in the NAND cell, a\nhigh voltage of 20 volts is applied to the gate of the first\nselection transistor and the control gate of the selected\n~ memory transistor, while 0 volts are applied to the gate of\nthe second selection transistor, and an intermediate voltage\nof 7 volts is applied to control gates of unselected memory\ntransistors. If the selected memory transistor is to be written\nor programmed into a logic\"]\", 0 volts are applied to the bit\n~ line connected with the NAND cell, thereby injecting elec-\ntrons into the floating gate of the selected memory transistor.\nThis results in causing the selected memory transistor to\nbecome enhancement mode. On the contrary, if the selected\nmemory transistor is to be programmed to a logic \"0\", a\n~ program inhibition voltage of 7 volts instead of 0 volts is\napplied to the bit line to inhibit the programming of the\nselected memory transistot Since such a programming\noperation uniformly injects electrons from the p-type well to\nits floating gate via its gate oxide layer, the partial stress on\n~ the thin gate oxide layer does not occur to a significant\ndegree, and the gate oxide leakage current may thus be\nprevented.\nHowever, when the memory capacity becomes high, such\nways of uniform erasing and programming cause problems\nin the case that system designers want to erase a portion or\na block of previously written or programmed memory cells\nin order to reprogram. In this case, a conventional approach\nis to simultaneously erase all memory transistors in a\nmemory cell array, i.e. to carry out a flash erasure, and then\nas to newly reprogram the content of all programs. Thus, since\nsignificantly reusable portions or blocks of the memory\narray are simultaneously erased, the reprogramming not\nonly needs a long Lime, but also is inconvenient. It may be\nappreciated that such problems seriously occur when the\no memory density becomes more higher. To solve these prob-\nlems, it is made possible only to erase all memory transistors\nin a selected memory block. However, in the case of an\nEEPROM using the above-mentioned improved erasing and\nprogramming techniques, to prevent the erasing of all\nas memory transistors in an unselected block, it is required that\na high voltage equal to an erase voltage or a high voltage of\nabout 18 volts or more be placed on their control gates.\n\nCase 9:02-cv-00058-JH\n\nDocument I\n,546,341\n\nFUed 03/05/2Q02 Page 69 of 101\nThus, this technology has a drawback that a decoding circuit\nfor performing a block erasing operation becomes compli-\ncated in design. In addition, when the density of the\nEEPROM cells increases, an on-chip occupying area of the\ndecoder increases, thereby making it difficult to design the ~\ndecoder.\nAnother problem area of the prior art is that of program-\ning. To prevent the progranuning of non-programmed\nmemory transistors, which must maintain previous data, of\nmemory transistors on a selected word line, it is required that ~\neach of the bit lines corresponding to the non-programmed\nmemory transistors be raised to the intermediate, i.e. the\nprogram inhibiting voltage, via a charge pump circuit con-\nnected thereto. In addition, when the memory capacity is\nincreased, the number of bit lines or the length of each bit\nline is increased. Consequently, it is necessary that a high\nvoltage generating circuit on the same chip for supplying the\nhigh voltages to the charge pump circuits has a high per-\nformance. Such a high voltage generating circuit and the\ncharge pump circuits give a problem in increasing the area\noccupied by the on-chip peripheral circuits. 20\nConventional EEPROMs include a page program mode\nfor high-speed programming. The page programming opera-\ntion is composed of a data loading operation and a program-\nming operation. The data loading operation comprises ~\nsequentially latching or storing data of a byte size from\ninput/output terminals to a data register. The programming\noperation comprises simultaneously writing the data stored\nin the data register into memory transistors on a selected\nword line via bit lines. The page programming technology 30\non an EEPROM with NAND cells is disclosed in the IEEE\nJOURNAL OF SOLID-STATE CIRCUITS, VOL. 25, NO.\n, pp 417 to 423, APRIL 1990.\nConventional EEPROMs employ a programming verifi-\ncation technique to enhance their reliability. The verification ~\nmeans checking to determine if programmed cells are pro-\ngramnied so as to have desired threshold voltages. Tech-\nnologies of the programming verification may be classified\ninto an external verification technique controlled by a micro-\nprocessor and an internal verification technique performed ~\nby an on-chip verification circuit. The external verification\nteclmique is disclosed in the IEEE JOURNAL OF SOLID-\nSTATE CIRCUITS, VOL. 26, NO.4, pp 492 to 495, April\nand U.S. Pat. No. 5,053,990. The external verification\ntechnique has a problem in that it takes a predetermined long ~\ntime to determine if programmed cells are well programmed.\nIn addition, whenever reprogramming is performed after the\nfailure of the programming, it is necessary that the data\nloading operation is performed again. However, the internal\nverifying technique has an advantage that the programming ~\nverification is performed at a higher speed. The internal\nverifying technique is disclosed in Korean Patent Laid Open\nNO. 91-17445 and U.S. PAT. NO. 4,811.294. In these\ndocuments, the verification is performed in such a manner\nthat comparator means compare data stored in a data register ~\nwith data read out in pages from memory cells via sense\namplifiers. However, such a scheme employing comparator\nmeans increases the area occupied by on-chip peripheral\ncircuits.\nSUMMARY OF THE INVENTION\nIt is therefore an object of the present invention to provide\na nonvolatile semiconductor memory with NAND struc-\ntured cells which can reduce the size of chip.\nIt is another object of the present invention to provide a\nnonvolatile semiconductor memory with NAN!) structured\ncells which can reduce power consumption.\nIt is further object of the present invention to provide a\nnonvolatile semiconductor memory which performs an eras-\ning of selected one of memory blocks.\nIt is still further object of the present invention to provide\na nonvolatile semiconductor memory which is program-\nmable without application of a program inhibition voltage of\nhigh voltages on unselected bit lines in order to reduce a chip\nsize and power consumption.\nIt is another object of the present invention to provide\nmethods for block erasing and programing which are\ncapable of reducing on-chip occupying area and power\nconsumption in a nonvolatile semiconductor memory with\nNAND structured cells.\nIt is another object of the present invention to provide a\nnonvolatile semiconductor memory in which on-chip area of\nperipheral circuits can be reduced in size.\nIt is further object of the present invention to provide a\nnonvolatile semiconductor memory in which over program-\nming can be prevented.\nAccording to an aspect of the present invention, a non-\nvolatile semiconductor memory includes, word lines formed\nover a surface of a semiconductor substrate; cell units\narranged on said surface to form an array, each said unit\nincluding at least one memory transistor which has source\nand drain regions fonned in said substrate but separated by\na channel region, a charge storage layer formed over the\nchannel region, and a control gate formed over the floating\ngate and coupled to a corresponding one of said word lines,\nsaid array being divided into a plurality of memory blocks\neach having a certain number of cell units; and means,\nresponsive to an address in a data erase mode, for applying\nan erase voltage to said substrate, and simultaneously float-\ning word Lines of memory blocks unselected by said address,\nwhereby erasure of memory transistors of said unselected\nmemory blocks is prevented by capacitive coupling of a\npredetennincd amount of said erase voltage to the word lines\nof said unselected memory blocks.\nAccording to another aspect of the present invention, a\nnonvolatile semiconductor memory includes, a semiconduc-\ntor substrate having a well region; memory transistors\nformed on the well region and arranged in a matrix form of\nrows and columns, the memory transistors comprising cell\nunits each of which has a predetermined number of memory\ntransistors connected in series, and first and second termi-\nnals at its both ends, cell units in respective rows constitut-\ning a memory block, each memory transistor having source\nand drain regions formed in the well region but separated by\na channel region, a floating gate formed over the channel\nregion to store charge representing binary data, and a control\ngate formed over the floating gate; word lines each being\nconnected to control gates of memory transistors in a\ncorresponding row; bit lines generally intersecting the word\nlines; a common source line; first and second selection lines\ngenerally in parallel with the word lines; first selection\ntransistors respectively connected between first terminals of\ncell units in each memory block and corresponding bit lines\nfor selectively connecting thercbetwecn, gates of first selec-\ntion transisLors associated with each memory block being\nconnected to a corresponding first selection line; second\nselection transistors connected between second terminals of\ncell units in each memory block and the common source line\nfor selectively connecting therebetween, gates of second\nselection transistors associated with each memory block\nbeing connected to a corresponding second selection line;\ndata register connected to the bit lines for providing binary\ndata to the bit lines, the register providing logic high level\n\nCase 9:02-cv-00058~JH\n\nDocument I\n,546,341\n\nFHed 03/05/2002\n\nPage 70 of 101\nvoltages to bit lines associated with memory transistors\nprogrammed to one binary data of the binary data while\nproviding reference voltages to bit lines associated with\nmemory transistors programmed to the other binary data\nthereof; and control means connected to the word lines and\nthe first and second selection lines for applying a program\nvoltage to a selected one of word lines of a selected memory\nblock and pass voltages to unselected word lines of the\nunselected memory block while applying a logic high level\nvoltage to the first selection line associated with the selected\nmemory block and rendering nonconductive second selec-\ntion transistors associated therewith, whereby channel\nregions and source and drain junctions of memory transis-\ntors in the selected memory block are capacitively charged\nto program inhibition voltages.\nAccording to another aspect of the present invention, a\nmethod for programming memory transistors in a row in a\nsemiconductor memory which comprises a semiconductor\nsubstrate; memory transistors formed on a surface of the\nsubstrate and arranged in rows and columns, the memory\ntransistors comprising cell units each of which has a prede-\ntermined number of memory transistors connected in series,\nand first and second terminals at its both ends, each memory\ntransistor having source and drain regions formed in the\nsubstrate but separated by a channel region, a floating gate\nformed over the channel region to store binary data, and a\ncontrol gate formed over the floating gate, cell units in\nrespective rows constituting a memory block; word lines\neach being connected to control gates of memory transistors\nin a corresponding row; bit lines generally intersecting the\nword lines, the first terminal of each of cell units of each\nmemory block being connected to a corresponding one of\nthe bit lines via a first selection transistor~ and a common\nsource line connected to the second terminal of each of cell\nunits via a second selection transistors, the method includes\nthe steps of applying a program voltage to a selected word\nline of a selected memory block and a pass voltage lower\nthan the program voltage to the remaining word lines\nthereof, while applying a logic high level voltage lower than\nthe .pass voltage to gates of first selection transistors asso-\nciated with the selected memory block and rendering non-\nconductive second selection transistors associated therewith,\nthe logic high level voltage corresponding to a logic high\nstate; and applying a logic low level voltage corresponding\nto a logic low state to bit lines associated with memory\ntransistors programmed from one binary data to the other\nbinary data, while applying the logic high level voltage to bit\nlines associated with memory transistors not programmed,\nwhereby channel regions and source and drain junctions of\nthe nonprogrammed memory transistors are capacitively\ncharged to a voltage level between the logic high level\nvoltage and the program voltage so as to prevent program-\nming, while those of the programmed memory.\n\n\nBRIEF DESCRIPTION OF DRAWING\nFor a better understanding of the invention, and to show\nhow embodiments of the same may be carried into effect,\nreference will now be made, by way of example, to the 60\naccompanying diagrammatic drawings, in which:\nFIG. 1 shows a schematic block diagram of an electrically\nerasable and programmable read-only memory according to\nthe present invention;\nFIG. 2 is comprised of FIGS. 2a and 2b: FIG. 2a\nillustrating the arrangement of memory cells within first and\nsecond memory blocks associated with a k-tb column block,\nand transfer transistor arrays connected thereto; and FIG. 2b\nshowing an input/output buffer, a column decoder and\nselection circuit, a data register and sense amplifiers asso-\nciated with the k-th column block;\nFIG. 3 shows a plan view of a pattern for one of a plurality\nof NAND cells constituting a memory cell array;\nFIG. 4 shows a cross-sectional view of the NAND cell\ntaken substantially along line IV-IV of FIG. 3;\nFIG. 5 shows a schematic circuit diagram of a block\nselection control circuit used in an embodiment of FIG. 2;\nFIG. 6 shows a schematic circuit diagram of a control gate\ndriving circuit used in embodiments of FIG. 2 and FIG. 13;\nFIG. 7 shows a schematic circuit diagram of a source line\nis driving circuit used in the embodiment of FIG. 2;\nFIG. 8a shows a circuit diagram of a tristate inventer used\nin FIG. 2b;\nFIG. Sb shows a circuit diagram of a tristate NAND gate\nused in FIG. 6;\nFIG. Sc shows a schematic timing circuit diagram for\ngenerating control signals *6 and 4~ used in the block\nselection control circuit of FIG. 5;\nFIG. 9 shows a program determination circuit and is\ncomprised of FIGS. 9a and 9b, in which FIG. 9a is a circuit\ndiagram showing a portion of the program determination\ncircuit and FIG. 9b is a circuit diagram showing a summa-\ntion circuit;\nFIG. 10 shows a timing chart of various control signals\nused in a block erasing mode according to a first embodi-\nment of the present invention;\nFIG. 11 shows a timing chart of various control signals\nused in a programming mode according to the first embodi-\nment of the present invention;\nFIG. 12 shows a timing chart of various control signals\nused in a programming verification mode and a reading\nmode according to the first and modified embodiments of the\npresent invention;\nFIG. 13 is a circuit diagram showing a schematic modified\nembodiment and is comprised of FIGS. 13a and 2b, in which\nFIG. 13a is a circuit diagram illustrating an arrangement of\nmemory transistors within an i-th memory block having\nshared word lines in the k-th column bloclq\n~ FIG. 14 shows a schematic circuit diagram of a block\nselection control circuit associated with the modified\nembodiment of FIG. 13;\nFIG. 15 shows a schematic circuit diagram of a ground\nline driving circuit associated with the modified embodiment\nso of FIG. 13;\nFIG. 16 shows a timing chart of various control signals\nused in a block erasing mode of the modified embodiment;\nand\nFIG. 17 shows a timing chart of various control signals\n~ used in a programming mode of the modified embodiment.\nIn the figures, like reference numerals denote like or\ncorresponding parts.\n\nDErAILED DESCRIPTION OF THE\nPREFERRED EMBODIMENTS\nIn the following description, numerous specific details,\nsuch as memory cells, the number of NAND cells, the\nnumber of bit lines, the value of voltages, circuit elements\nand parts and so on, are set forth in order to provide a\nthorough understanding of the present invention. It will be\n\n\nCase 9:02-cv-00058~H\n\nDocument I\n,546,341\n\nFHed 03./05/2002\n\nPage 71 of 101\nunderstood by those skilled in the art that other embodi-\nments of the present invention may be practiced without\nthese specific details, or with alternative specific details.\nThe term \"memory transistor\" as used herein refers to a\nfloating gate MOS PET having a source, a drain, a floating 5\ngate and a control gate. The term \"programming\" is used to\ndescribe the writing of data into selected memory transis-\ntors. The term \"NAND cell charging\" is defined as the\ncharging of the channel and the,source and drain junction\ncapacitors of respective memory transistors constituting the 10\nNAND cell to a predetermined potential.\nIn the following description, symbols k and i are respec-\ntively used for those parts associated with a k-th column\nblock and an i-th memory block. Symbol j represents a\nnotation associated with aj-th word line. 15\nThe term \"ground potential\" (or like terms such as\n\"ground voltage\" or \"earth\" potential or voltage\" is used\nconveniently in this specification to denote a reference\npotential. As will be understood by those skilled in the art,\nalthough such reference potential may typically be zero 20\npotential, it is not essential that it is so, and may be a\nreference potential other than zero.\nAn example of an EEPROM of the present invention is\nfabricated by using CMOS manufacturing technologies on a\ncommon chip, in which depletion mode n-channel MOS ~\ntransistors each having a threshold voltage of -2 to -3 volts\n(hereinafter referred to as D-type transistors), enhancement\nmode n-channel MOS transistors each having a threshold\nvoltage of about 0.7 volts (hereinafter referred to as n-chan-\nnel transistors) and p-channel MOS transistors each having 30\na threshold voltage of about -0.9 volts (hereinafter referred\nto as p-channel transistors) are employed.\nFIG. 1 illustrates a schematic block diagram of one\nexample of an EEPROM according to the present invention.\nFIG. 2 is composed of FIG. 2a and FIG. 2b in parallel\nrelationship with each other, and shows, for the convenience\nof illustration, only those elements associated with the k-th\ninput/output terminal I/Ok, a memory cell array 10, input\nand output buffers 26 and 28, a column decoder 30, a column\nselection circuit 32, a data register and sense amplifier 12\nand a transmission transistor array 34-i which is connected\nwith the memory cell array 10 and constitutes a portion of\na block selection control circuit 18. It should be noted that\nelements associated with the remaining input/output termi-\nnals are identical to those associated with the terminal I/Ok.\nReferring now to FIGS. land 2, the memory cell array 10\nof the present EEPROM is composed of NAND cells NU\narranged in a matrix form of 1,024 rows and 2,048 columns,\nand includes 1,024 memory blocks BK1 to BK1024 divided 50\nin a row direction. Each NAND cell is composed of memory\ntransistors Ml to MS whose drain-source paths are con-\nnected in series between the source of a first selection\ntransistor ST1 and the drain of a second selection transistor\nST2. Gates of the first and second selection transistors ST1 55\nand ST2 and control gates of the memory transistors Ml to\nM8 are respectively connected to first and second selection\nlines SL1 and SL2 perpendicular to bit lines BLk-1 to\nBLk-256 (k=l ,2 8) and word lines WL1 to WLS. Thus,\nthe memory transistors Ml to M8 are disposed at intersec- 60\ntions of the word lines WL1 to WL8 and the bit lines BLk-1\nto BLk-256. Drains of the first selection transistors ST1 are\nrespectively connected with corresponding bit lines, and\nsources of the second selection transistors ST2 are con-\nnected to a common source line CSL. Consequently, the 65\nmemory cell array 10 is comprised of memory cells of a total\nof l,024x8x2,048 (=16,777,216), and each memory block is\ncomprised of memory cells of a total of 8 x2,048 (=16.384).\nThe memory cell array 10 is divided into eight column\nblocks Bk (k=I,2 8) respectively corresponding to\ninput/output terminals 1/01 to 1/08, and each column block\nhas 256 bit lines or column lines which are parallel in a\ncolumn direction. Thus, each column block includes\nmemory cells totalling 256 Kbit (=l,024x256).\nThe memory cell array 10 is formed on a p-well region in\na semiconductor substrate. FIGS. 3 and 4 respectively show\na plan view and a cross-sectional view of one of the NAND\ncells NU constituting the memory cell array 10.\nReferring to FIGS. 3 and 4, the semiconductor substrate\nis of a p-type silicon monocrystalline material which is\ncut on the (1,0,0) crystal orientation at an impurity concen-\ntration of about lxlO'4 atoms/cm3. A p-type well region 76\nwith an impurity concentration of about 2x10'6 atoms/cm3\nis formed having a depth of about 4~rm from a main surface\nof the substrate 72. The well region 76 is surrounded by\na n-type well region 74 of about lOjim in depth with an\nimpurity concentration of about 5x10'5 atoms/cm3. Heavily\ndoped N~ regions 80 to 92 are formed on the main surface\nof the well region 76 and separated by each of a plurality\nof channel regions 94. One part of the N~ region 80 is a\ncontact region connected via a contact hole 96 to a bit line\nBL of a metal material, such as an aluminum, which extends\nover an insulation layer 112, and the other part of the N~\nregion 80 also serves as a drain region of the first selection\ntransistor ST1. The N~ regions 82 to 90 serve as conunon\nsource-drain regions of two adjacent transistors of transis-\ntors ST1, Ml to M8 and ST2. One part of the N~ region 92\nis a source region of the second selection transistor ST2, and\nthe other part of the N~ region 92 serves as buried common\nsource line CSL. However, the line CSL may be a conductor\nlayer which is insulatively formed within the insulating layer\ncontacting with the N~ source region 92 of the transistor\nST2 via a contact hole. Gate layers 98 and 100 of a\nrefractory metal silicide material, such as a tungsten silicide,\neach of which has a thickness of about I ,500A, are respec-\ntively formed on gate insulating layers 102 of about 300A\nthickness, overlying channel regions of the first and second\nselection transistors ST1 and ST2.\nFloating gate layers 104 of a polycrystalline silicon mate-\nrial are insulatively formed with a thickness of about I,500A\non gate insulating layers 106 of about IOOA thickness\noverlying channel regions 94 of memory transistors Ml to\nM8, respectively. Control gates 108 of the same material and\nthickness as the gate layers 98 and 100 are respectively\nformed over the floating gate layers 104 interposing inter-\nmediate insulating layers 100, such as ONO insulating\nlayers of silicon dioxide-silicon nitride-silicon dioxide mate-\nrials, of about 250A thickness. The gate layers 98 and 100\nand the control gate layers 108 are respectively shared by the\nfirst and second selection lines SL1 and SL2 and word lines\nWL1 to WL8, i.e. conductor layers which are fabricated\nfrom the same material as the gate and control gate layers 98,\nand 108. The gate layers 98 and 100, control gate layers\n, floating gate layers 104, the first and second selection\nlines SL1 and SL2, and word lines WL1 to WL8 are\ninsulated from one another with an insulating layer 112 of\ninsulating materials, such as a silicon dioxide and a BPSG\nor a PSG.\nThe bit line BL is connected with the contact region 80 via\nthe contact hole 96 and extends in a column direction on the\ninsulating layer 112. The p-type well region 76 and the\nn-type well region 74 are connected to a well electrode 114\nin common via contact holes (not shown). An erasing\nvoltage is applied to the well electrode 114 in an erasing\n\n\nCase 9:02-cv-00058-JH\n\nDocument I\n,546,341\n\nFHed 03/05/2002\n\nPage 72 of 101\noperation, and a reference potential, i.e. ground potential, is\napplied to the well electrode 114 in operations except the\nerasing operation, i.e. in programming, programming veri-\nfication and reading operations. However, the substrate 72 is\nalways at the reference potential. The memory cell array 10 ~\nmay also be formed on a p-type well region formed in an\nn-type monocrystalline silicon substrate.\nReturning now to FIGS. I and 2, the block selection\ncontrol circuit 18 serves to select a predetermined memory\nblock of the memory blocks BK1 to BK1024, and to provide ~\ncontrol signals on control gate lines CGL1 to CGL8 from a\ncontrol gate driving circuit 20 to word lines WL1 to WLS in\nthe selected memory block according to various operation\nmodes, such as the erasing, programming, programming\nverification and reading modes. In FIG. 2a, illustration is\nmade of transfer transistor arrays 34-i constituting a portion\nof the block selection control circuit 18. Each of the transfer\ntransistor arrays 34-i includes transfer transistors BTI to\nBT1O for connecting the first and second selection gate lines\nSGL1-l and SGLi-2 and control gate lines CGL1 to CGL8\nto the first and second selection lines SL1 and SL2 and word ~\nlines WL1 to WL8, respectively.\nAccording to one feature of the illustrated embodiment of\nthe present invention, the block selection control circuit 18\nrenders nonconductive the transfer transistors associated\nwith unselected memory blocks in an erasing operation,\nthereby causing word lines in unselected memory blocks to\nbecome floating. In a programming operation, the block\nselection control circuit 18 renders conductive the second\ntransistor ST2 in a selected memory block, thereby charging 30\nthe program inhibition voltage from a source line driving\ncircuit 22 to channels and source and drain junctions of\nmemory transistors in the selected memory block.\nFIG. S shows a schematic circuit diagram for a block\nselection control circuit 18 connected to a transfer transistor ~\narray 34-i of FIG. 2a. For example, in the case of i=2, lines\nSGL2-1, SGL2-2 and BSC2 of FIG. 5 are respectively\nconnected to lines SGL2-1, SGL2-2 and BSC2 of the\ntransfer transistor array 34-2 associated with the second\nmemory block BK2 as shown in FIG. 2a. Thus, it should be ~\nunderstood that though FIG. 5 shows, for the convenience of\nillustration, only a single circuit for selecting the i-th\nmemory block BIG, the block selection control circuit of\nFiG. 5 corresponding to each of memory blocks SKi to\nBK1024 resides on the present EEPROM chip as a periph- ~s\neral circuit.\nReferring now to FIG. 5, NAND gate 120 is a row\ndecoder for receiving address signals P1, QI and RI and a\nreset signal Xd. The address signals P1, QI and RI are signals\npredecocled by row address signals from a predecoder (not 50\nshown) for predecoding row address signals A11,~ to A~,\nA~ which are output from an address buffer for storing a\nrow address a11 to a~ from external address input terminals.\nThe row decoder 120 provides a logic low state of 0 volts\n(hereinafter referred to as an \"L\" state or an \"L\" level) on a 55\nline 122 when selected, and outputs a logic high state of 5\nvolts (hereinafter referred to as an \"H\" state or an \"H\" level)\nthereon when unselected. Two input terminals of NAND\ngate 124 are connected to the line 122 and a signal BLK,\nrespectively. The signal BLK is a control signal for setting 60\nword lines WL1 to WL8 to the reference potential before or\nafter the respective operations, as will be discussed herein-\nafter. The output of the NAND gate 124 is connected to the\nfirst selection gate line SGLi-1 and to the block selection\ncontrol line BSCi via a current path of D-type transistor 126 65\nfor inhibiting the transfer of a high voltage. The gate of the\ntransistor 126 is connected to a program control signal PGM\nfor maintaining an \"L\" state in a programming operation. A\ncharge pump circuit 128 is connected with the block selec-\ntion control line BSCI for providing, when the line BSCi is\nselected, a program voltage `~pgm on the line BSCi by the\npumping of a clock 4~ in the programming operation. The\ncharge pump circuit 128 is a known circuit comprised of\nn-channel transistors 130 and 132 and a MOS capacitor 134.\nTwo input tenninals of NAND gate 136 are respectively\nconnected with an erase control signal ERA and the line 122.\nA transfer gate 148 composed of n-channel transistor 140\nand p-channel transistor 142 is connected between the\noutput of the NAND gate 136 and a connecting node 146.\nThe gate of n-channel transistor 140 is connected to a control\nsignal 4'6. and the gate of p-channel transistor 142 is con-\nnected to the complement signal of $~ via an inverter 138.\nThe current path of n-channel transistor 144 is connected\nbetween the node 146 and the reference potential, and its\ngate is connected with a control signal $7. The source-to-\ndrain current path of D-type transistor 150 for preventing the\ntransfer of a high voltage is connected between the node 146\nand the second selection gate line SGLi-2, and its gate is\nconnected to a control signal WE. A charge pump circuit 152\nhaving the same construction as the circuit 128 is connected\nto the second selection gate line SGLI-2 for providing a pass\nvoltage V,,~ thereon during the programming operation\nwhen the line SGLi-2 is selected.\nFIG. 8c is a schematic circuit diagram for generating the\ncontrol signals $6 and $7 as used in FIG. 5. In an erasing\noperation or mode, $7 and $7 are all in \"L\" states, and in a\nNAND cell charging operation as will be discussed later, 46\nis in \"H\" state and $7 is in \"L\" state. In programming\nverification and reading operations, $7 is in \"H\" state and $7\nis in \"L\" state.\nFIG. 6 illustrates one of eight control gate driving circuits,\ni.e. the j-th control gate driving circuit which constitutes\ncontrol gate driving means and is associated with the j-th\nword line. The outputs of the control gate driving circuits are\nrespectively connected to control gate lines CGLI to CGLS\nwhich are respectively connected to word lines WL1 to WL8\nvia transfer transistor arrays 34-i. From the point of view of\nreduction of total chip size, it would be preferable that the\ncontrol gate driving circuits be provided in common in an\non-chip peripheral circuit so as to drive word lines of a\nselected memory block according to various operation\nmodes.\nReferring now to FIG. 6, NAND gate 154 is a row\ndecoder receiving row address signals A8/~, AC)~ and\nA10/A~ from address buffer (not shown). The decoder 154\noutputs \"L\" state upon selection of the line CGLJ while\noutputting \"H\" state upon unselection thereof. The output of\nthe decoder 154 and a control signal PVF are respectively\nconnected to two input terminals of NOR gate 173. An\noutput signal $7 of the NOR gate 173 and its complement\nsignal $7 via an inverter 174 are provided to control a tristate\nNAND gate 158 and a verifying voltage generator 164. The\ncontrol signal PVF maintains an \"L\" state only in a pro-\ngramming verification operation. Thus, in every operation\nexcepting the programming verification operation, the con-\ntrol signal PVF stays at \"H\" level, thereby causing the signal\n$7 to be in an \"L\" state while causing the signal TO~Y~ to be\nin an \"H\" state. In the programming verification operation,\nif the line CGLj is selected, 4,, becomes \"H\" state and its\ncomplement 4, becomes \"L\" state while, if the line CGLJ is\nunselected, 4,, becomes \"L\" state and 4,, becomes \"H\" state.\nNAND gate 156 inputs the output of the decoder 154 and\ncontrol signals DS and ERA, respectively. Two input termi-\nnals of the tristate NAND gate 158 are respectively con-\n\nCase 9:02-cv-00058~JH\n\nDocument I\n,546,341\n\nFHed 03/05/2002\n\nPage 73 of 101\nnected to an output line 160 of the NAND gate 156 and the\ncontrol signal PGM. The tristate NAND gate 158 illustrated\nin FIG. Sb is enabled in response to $,, at \"L\" level and\n~ at \"H\" level while becoming high impedance with 4., at\n\"H\" level and 4, at \"L\" level. Thus, in the programming 5\nverification operation, the NAND gate 158 stays in the high\nimpedance state only at the time when the line CGLj is\nselected. The output of the NAND gate 158 is connected to\na connecting node 162 to which the verifying voltage\ngenerator 164 is connected.\nThe verifying voltage generator 164 is comprised of a\np-channel transistor 166 and n-channel transistors 168, 170\nand 172 whose current paths are connected in series between\nthe power supply voltage Vcc and the reference potential.\nThe gate of the p-channel transistor 166 is connected to a\nchip enable signal ~, and gates of the transistors 168 and\nare connected to the signal 4,, from the NOR gates 173.\nDrain and gate of the transistor 172 are connected in\ncommon. The verifying voltage generator 164 is enabled by\n,. at \"H\" level only in the programming verification opera-\ntion, thereby producing a verifying voltage of about 0.8 volts\nto the connecting node 162. Connected between the con-\nnecting node 162 and the control gate line CGLj is the\nsource-to-drain current path of D-type transistor 176 for\ninhibiting the transfer of a high voltage, the gate of which is\nconnected to the control signal PGM.\nTwo input terminals of NAND gate 178 are respectively\nconnected to the output of the NAND gate 156 and the clock\nRfrom a ring oscillator (not shown). Between the output of\nthe NAND gate 178 and the gate of a driving n-channel\ntransistor 182 is connected a charge pump circuit 180 which\nhas the same construction as the above-mentioned charge\npump circuit. Drain and source of the transistor 182 are\nconnected to the program voltage V~,,, and the control gate\nline CGLJ, respectively. Inverter 190 receives the program ~\ncontrol signal POM, and the current path of D-type transistor\nfor preventing the transfer of a high voltage is connected\nbetween the output of the inverter 190 and the gate of the\ntransistor 182 which is connected to the control signal PGM.\nAs will be discussed hereinafter, a circuit 196 which is\ncomprised of NAND gate 178, the charge pump circuit 180\nand the driving transistor 182 provides means for supplying\nthe program voltage Vpg,, to the control gate line CGLj\nwhen the line CGLj has been selected by row address signals\nA8/~, A91A and A1Q/k in a program mode.\nTwo input terminals of NOR gate 188 are respectively\nconnected to the output of the NAND gate 156 and the clock\n$R' Between the output of the NOR gate 188 and the gate of\na driving n-channel transistor 184 is connected a charge\npump circuit 186. Drain and source of the transistor 184 are\nrespectively connected to the pass voltage V,,..~ and the\ncontrol gate line CGLJ. Between a connecting node 202 and\nthe gate of the transistor 184 is connected the current path of\nD-type transistor 194 for preventing the transfer of a high\nvoltage, the gate of which is connected to the control signal ~\nPGM. As will be discussed hereinafter, a circuit 200 which\nis comprised of NOR gate 188, the charge pump circuit 186\nand the driving transistor 184 provides means for supplying\nthe pass voltage V,,,., to the control gate line CGLj when the\nline CGLJ is selected by the row address signals in the ~\nprogram mode.\nFIG. 7 shows a schematic circuit diagram of a source line\ndriving circuit which is connected in common to the com-\nmon source line CSL as shown in FIG. 2a. The source line\ndriving circuit 22 is composed of an inverter 204 whose 65\ninput terminal is connected to the control signal PGM, a\nD-type transistor 206 whose current path is connected\nbetween the output terminal of the inverter 204 and the\ncommon source line and whose gate is connected to the\ncontrol signal PGM, and a charge pump circuit 208 con-\nnected to the common source line CSL. The charge pump\ncircuit 208 serves to boost the common source line to a\nprogram inhibition voltage V,,1 in the program mode.\nThe input/output buffer 16 is comprised of the input buffer\nand the output buffer 28 which are each connected to\ninput/output terminals. The input buffer 26 connected to\neach of input/output terminals 1/01 to 1/08 is a conventional\ncircuit for converting a byte of data (8-bit data) therefrom to\nCMOS level data and temporarily storing it. Output buffers\nare conventional circuits to simultaneously output 8-bit\ndata read out from the corresponding column blocks to the\ncorresponding input/output terminals.\nThe column decoder and selection circuit 14 of FIG. 2b is\ncomprised of the column decoder 30 and the column selec-\ntion circuit 32. The column selection circuit 32 associated\nwith each of the column blocks is comprised of transfer\ntransistors Ti to T256, source-to-drain paths of which are\nrespectively connected between a common bus line CBLk\nand lines DLk-1 to DLk-256. Gates of the transfer transistors\nTi to T256 are respectively connected to parallel lines ILl\nto 11,256 which are connected to the column decoder 30.\nThe column decoder 30 selects one of the lines ILl to\nTL256 in response to column address signals from address\nbuffers (not shown), thereby rendering conductive transfer\ntransistors connected with the selected line.\nThe data register and sense amplifier 12 is connected\nbetween the lines DLk-1 to DLk-256 and bit lines BLk-1 to\nBLk-256 which are associated with the corresponding col-\numn block, as shown in FIG. 26. In series between the bit\nlines BLk-i to BLk-256 and nodes 36 are respectively\nconnected drain-to-source paths of D-type transistors 38 and\n. Gates of the D-type transistors 38 are connected to the\npower supply voltage Vcc to prevent the transfer of high\nvoltages induced on the bit lines BLk-i to BLk-256 in a\nblock erasing operation. Gates of the D-type transistors 40\nare connected to a control signal 4~ staying at \"H\" level of\nabout 5 volts during programming. Between the nodes 36\nand nodes 42 are respectively connected drain-to-source\npaths of n-channel transistors 44. Gates of the transistors 44\nare connected to a control line SBL staying at \"H\" level\nduring programming. Between the nodes 42 and nodes 46\nare respectively connected latches PBk-1 to PBk-256 con-\nstituting the data register which is referred to as a page\nbuffer. Each of the latches is comprised of two inverters\ncross connected. The latches PBk-1 to PBk-256 serve not\nonly as a page buffer for temporarily storing data so as to\nsimultaneously write the data into memory cells via respec-\ntive corresponding bit lines in a programming operation, but\nalso as verifying detectors for determining if the program\nwas well performed in a programming verification operation\nand as sense amplifiers for sensing and amplifying data on\nbit lines which is read out from memory cells in a reading\noperation. A tristate inverter 48 and an n-channel transistor\nare connected in parallel between each of the nodes 42\nand its corresponding ope of the lines DLk-1 to DLk-256.\nEach tristate inv~rter 48, which is referred to as a clocked\nCMOS inverter, is enabled by a control signal 4,4 at \"H\" level\nwhile becoming high impedance by the signal $7 at \"L\"\nlevel. Thus, each of the inverters 48 serves as a buffer amp,\nbeing enabled in programming verification and reading\noperations. N-channel transistors 49 whose gates are con-\nnected to a control signal $7 are transfer transistors for\ntransferring input data to the corresponding latches PBk-1 to\nPBk-256 in a programming operation. The tristate inverter\n\n\nCase 9:02-cv-00058~JH\n\nDocument I\n,546,341\n\nFHed 03/05/2002\n\nPage 74 of 101\n which is used in the present embodiment is illustrated as\na schematic circuit diagram in FIG. 8a. Between each of\nnodes 46 and the reference potential are serially connected\ncurrent paths of n-channel transistors 50 and 52. Gates of the\ntransistors 52 are connected to a control signal 42. staying at ~\n\"H\" level during a verification sensing period in a program-\nming verification operation and during a read sensing period\nin a read operation. Gates of the transistors 50 are respec-\ntively connected to the nodes 36, and drain-to-source paths\nof n-channel transistors 37 are respectively connected 10\nbetween the nodes 36 and the reference potential. Gates of\nthe transistors 37 are connected in common to a line DCB to\nwhich a control signal is applied to cause bit lines to be\ndischarged after completion of erasing and programming\noperations and to reset the data register to \"L\" state, i.e. \"C\"\ndata prior to a reading operation. 15\nThe data register and sense amplifier 12 includes a\nconstant current source circuit 33, which is referred to as a\ncurrent mirror, according to the present embodiment. The\nconstant current source circuit 33 comprises a reference 20\nportion 64 which is enabled in programming verification and\nreading operations and disabled in erasing and programming\noperations; and current source portions 66 comprised of\np-channel transistors 54 whose drain-to-source paths are\nrespectively connected between gates of the transistors ~ 25\nand the power supply voltage Vcc. The reference portion 64\nis comprised of p-channel transistors 56 and 58 and n-chan-\nnel transistors 60 and 62 to serve as a reference for the\ncurrent source transistors 54. Source-to-drain paths of the\np-channel transistors 56 and 58 are connected in parallel ~\nbetween the power supply voltage Vcc and a line 68, and the\ngate of the p-channel transistor 58 is connected to the line\n. Drain-to-source paths of the n-channel transistors 60 and\nare connected in series between the line 68 and the\nreference potential. The gate of the n-channel transistor 60\nis connected to a reference voltage V,,,1 of about 2 volts.\nGates of the transistors 56 and 62 are connected to a control\nsignal $7, and gates of the current source transistors 54 are\nconnected to the line 68. Thus, in programming verification\nand reading operations, the current source transistors 54\nconnected to the reference portion 64 which is enabled by\nthe control signal $7 serve to provide a constant current of\nabout 4pA to bit lines BLk-1 to BLk-256.\nA programming determination circuit 24 of FIG. I is\nconnected via lines 70 to lines DLk-l to DLk-256 of FIG. 26\nto serve to determine if every programmed memory tran-\nsistor reaches the range of desired threshold voltages in a\nprogramming verification operation.\nFIG. 9 shows a schematic circuit diagram of the program-\nming determination circuit 24. It should be noted that the 50\ncircuitry of FIG. 9a is a portion of the programming deter-\nmination circuit 24 associated with the k-th column block\nClik, and eight circuits corresponding to the respective ones\nof column blocks present as a peripheral circuit on the\non-chip EEPROM. A circuit shown in FIG. 91~ is a summa- 55\nLion circuit to perform a summation function for providing\nan \"L\" level when any one of signals FP1 to FF8 is \"L\"\nlevel. Referring to FIG. 9a, drain-to-source paths of n-chan-\nnel transistors 212 to 216 are connected in parallel between\na line 210 and the reference potential, and gates of the 60\ntransistors 212 to 216 are respectively connected to lines 70\nof FIG. 26. Current paths of p-channel transistors 218 and\nD-type transistor 220 arc connected in andes, and the gate of\nthe transistor 218 is connected to a control signal SUP\nstaying at \"L\" level in a programming verification operation 65\nwhile the gate of the transistor 220 is connected to the line\n. The transistors 212 to 220 constitute a NOR gate 234.\nTwo input terminals of NOR gate 222 are respectively\nconnected to the line 210 and a control signal SFP which\nbecomes \"L\" state only upon a verifying check. The input of\nan inverter 224 is connected to the output of the NOR gate\n, and the output terminal of the inverter 224 outputs FPk.\nThe summation circuit 236 of FIG. 9b is comprised of\nNAND gate 226 connected to lines FF1 to FF4; NAND gate\nconnected with signals FF5 to FF8; and NOR gate 230\nconnected to outputs of the NAND gates 226 and 228.\nReferring now to the timing charts of FIG. 1010 FIG. 12,\nan explanation wifi be given of operations and features of the\nfirst embodiment shown in FIGS. 1 to 9.\n\nBlock Erasing Mode\n\nIn a block erasing mode, the data register and sense\namplifier 12, the column decoder and selection circuit 14,\nthe input/output buffer 16 and the programming determina-\ntion circuit 24 are all in off states. Explained in more detail,\nthe column decoder 30 of FIG. 2b is reset, thereby rendering\ntransfer transistors Ti to T256 nonconductive. Control sig-\nnals 4~ to45 and signals on lines DCB and SBL are held in\n\"L\" states, so that the data register and sense amplifier 12\nbecome nonconductive. The control signal SUP of FIG. 9a\nis held in \"H\" state, and the programming determination\ncircuit 24 is thereby nonconductive. The source line driving\ncircuit 22 provides \"L\" state, i.e. the reference potential of\nO volts on the common source line CSL by PGM staying at\n\"H\" level.\nNow, an explanation will be given in conjunction with the\ntiming chart of FIG. 10, assuming that simultaneous block\nerasing is performed on data stored in memory transistors in\nthe memory block BK1.\nThe time interval between t, and t2 is a period for\ndischarging all word lines WL1 to WL8 to the reference\npotential. During this period, NAND gate 124 of FIG. S\nretains \"H\" level with the controlsignal BLK at \"L\" level,\nand D-type transistor 126 is conducting with PGM at \"H\"\nlevel. Thus, the block selection control line BSCi stays at\n\"H\" level of 5 volts. At this time, the charge pump circuit\nis in a nonconducting state. Consequently, in this period,\nall of the block selection control lines BSC1 to BSC1O24\nmaintain the potential of 5 volts. On the other hand, in this\nperiod, since control signals PVF and PGM stay at \"H\"\nlevels and the control signal ERA is at \"L\" level, the outputs\nof NAND gate 156 and tristate NAND gates 158 remain at\n\"H\" level and \"L\" level, respectively. At this time, the\ntristate inverter 164 is in a high impedance state. Thus, the\ncontrol gate line CGLj stays at \"L\" level of 0 volts via\nturned-on D-type transistor 176. Consequently, all of the\ncontrol gate lines CGL1 to CGL8 maintain \"L\" level during\nthis period. Transfer transistors BT1 to BT1O are all turned\non by the potential of the block selection control lines BSC1\nto BSC1O24 of 5 volts, and word lines WL1 to WLS are all\ndischarged to the reference potential.\nThe time duration between t2 and t3 is a period to erase all\nmemory cells in only a selected memory block. At Lime t2,\nthe decoder 120 receives address signals P1, QI and Rl which\nare all at \"H\" levels to select the memory block BK1, and the\noutput of the decoder 120 thereby goes to \"L\" level. Thus,\nthe output of NAND gate 124 goes to \"H\" level. Conse-\nquently, the block selection control line BSC1 correspond-\ning to the selected memory block BK! remains at the\npotential of 5 volts during the period between t2 and t3.\nHowever, decoders 120 associated with unselected memory\nblocks BK2 to BK1024 output \"H\" levels since at least one\n\nCase 9:02-cv-00058JH\n\nDocument I\n,546,341\n\nFHed 03/05/2002\n\nPage 75 of 101\nof the address signals P1, QI and RI is \"L\" level. Conse-\nquently, block selection control lines BSC2 to BSC1O24\nassociated with the unselected memory blocks go to the\nreference potential of 0 volts. Thus, transfer transistors in the\ntransfer transistor array 34-1 are all turned on, and word ~\nlines WL1 to WLS in the memory block BK1 thereby go to\nthe reference potential. However, since the transfer transis-\ntor arrays 34-2 to 3-1024 connected with unselected memory\nblocks BK2 to BK1024 are all turned off, word lines\nassociated therewith go to floating states. 10\nAt Lime t2, the erase voltage Vera of about 20 volts is\napplied to the p-type well region 76 and the n-type well\nregion 74 via the well electrode 114 of FIG. 4. During the\ntime interval between t2 and t3, i.e. during the time period of\nabout 10 msec, floating gates of memory transistors in the\nselected memory block BK1 accumulate holes by means of\nthe F-N tunneling which is generated by the application of\nthe erase voltage Vera to their channel, source and drain\nregions and that of the reference potential to their control\ngates. Thus, all of the memory transistors in the memory\nblock BK1 are changed into D-type transistors having\nthreshold voltages of about -3 volts. That is, all memory\ntransistors in the memory block BK! are erased to binary\nzero data.\nHowever, in the case when the erase voltage vera is\napplied to the p-well and N-well regions 76 and 74 via the\nwell electrode 114 at Lime t2, since word lines in unselected\nmemory block BK2 to BK1024 are then in floating states,\nthe word lines are thereby charged to substantially the erase\nvoltage Vera by a capacitive coupling. Thus, the charged\nvoltage of the word lines in the unselected memory blocks\nsufficiently reduces the electric field between the channel\nregion and the control gate of each memory transistor such\nthat its erasure can be prevented. The inventors have dis-\ncovered that word lines in unselected memory blocks were\ncharged to an amount of 80 to 90 percent of the erase voltage\nV,,,,,, and data of programmed memory transistors in the\nunselected memory blocks was not destroyed or disturbed.\nThus, in the block erasing of the present embodiment, since\nit is unnecessary to apply the program inhibition voltage\nfrom a voltage boosting circuit to word lines in unselected\nmemory blocks, a reduction of the area occupied by the chip\nas well as the prevention of power consumption the area can\neffectively be accomplished. Moreover, the present inven-\ntion has an advantage of increasing effective memory array\narea whilst reducing peripheral circuit area on a chip surface\nof a fixed size. This results in increasing the memory\ncapacity of the EEPROM.\nIn the above-mentioned block erasing operation, the erase\nvoltage applied to the well electrode 114 is coupled as well ~\non the floated word lines as on floated bit lines. Thus, the bit\nlines are also charged to the erase voltage of about 20 volts\nin the block erase operation. To prevent voltage-induced\nstress on transistors 40 of FIG. 26 due to the charged erase\nvoltage, D-type transistors 38, whose gates are connected to ~\nthe power supply voltage Vcc, are respectively connected\nbetween bit lines BLk-1 to BLk-256 and the transistors 40.\nDuring the block erasing operation between ~ and t3, the\nfirst selection line SL1 of the selected memory block BK!\nmaintains a potential of about 4.3 volts, and the second\nselection line SL2 of the block BKI is in a floating state\nsince control signals $~ and 4~ are at \"L\" levels, thereby\nrendering transistors 140 to 144 of FIG. 5 nonconductive.\nThe floating state of the second selection line SL2 thereof\nprevents current flowing via the line SL2 from the well\nelectrode 114 when one or some of the second selection\ntransistors ST2 thereof failed. During the block erasing\noperation, the voltage relationship of significant portions of\nselected and unselected memory blocks can be summarized\nin the following TABLE I.\n\n\n\nTABLE 1\n\n\n\nVoltage States\n\nVoltage States\n\n\nRr Selected\n\nFor Unselected\n\n\nMcmory Block\n\nMemory Blocks\n\nFirst Selection Line SL1\n.3 V\nV\n\nWont Lines WLI to WL8\nV\n\nApproximately 20 V\n\nSecond Selection Line SL2\n\nFloating\n\nFloating\n\nWcllElecteode\nV\nV\n\nTurning to FIG. 10, the time duration between t3 and ~ is\na period to discharge the charged voltage on bit lines and\nword lines. At time 13, the block erasing operation terminates\nand the erase voltage Vera goes, to the reference potential\nwhile control signals WE and ERA go to \"H\" leveL Between\nt~ and t4, the output of NAND gate 156 stays at \"H\" level\nwith the control signal DS at \"L\" level. Thus, the output of\nNAND gate 158 goes to \"L\" level with the control signal\nPGM at \"H\" level. Consequently, control gate lines CGL1 to\nCGLS maintain \"L\" levels between 13 and t4. During this\nperiod, the output of NAND gate 124 of FIG. 5 stays at \"H\"\n~ level with the control signal BLK at \"L\" level. Thus, each of\nthe block selection control lines BSC1 to BSC1O24 goes to\na potential of 5 volts. Consequently, all transfer transistors\nBT1 to BT1O are turned on, and all word lines WL1 to WLS\nare discharged to the reference potential. On the other hand,\nthe first and second selection lines SL1 and SL2 are also\ndischarged to a potential of 5 volts.\nAt Lime t3, the line DCB goes to \"H\" level and $~ also\ngoes to \"H\" level. Thus, the erase voltage charged on bit\nlines discharges to \"L\" level via transistors 37 shown in FIG.\nb.\nAt time t4, control signals BLK and DS go to \"if' levels\nand X,1goes to \"U' level. Thus, NAND gate 120 of FIG. 5\ngoes to \"H\" level, and the first and second gate lines SGLi-!\n~ to SGLi-2 and block selection control lines BSCi go to the.\nreference potential.\n\nProgram Mode\nThe present EEPROM performs a data loading operation\nto store data input via input/output terminals into data\nlatches PBk-1 to PBk-256 prior to a programming operation\nafter an erasing operation.\nData loading operation is accomplished prior to a time t1\nof FIG. 11. During the data loading operation, control\nsignals Xd, $2, 4~ and 4)4, program voltage V,,Zm. pass\nvoltage Vu,,.,, p-well region 76, program inhibition voltage\nV,,1 and lines SBL and DCB stay at \"L\" levels, and control\nsignals WE, PGM, SLE, BLK, DS, ERA, PVF, SUP $R' 4~\nand 4~ are at \"H\" levels. As can be seen in FIG. 5, since Xd\nis \"L\" level and BLK., ERA, SLE, WE and PGM are all \"H\"\nlevels, block selection gate lines BSC1 to BSC1O24 stay at\n\"L\" levels, thereby rendering transfer transistor arrays 34-!\nto 34-1024 nonconductive. With the line SBL at \"L\" level,\n~ connection of data latches PBk-1 to PBk-256 to bit lines\nBLk-1 to BLk-256 is inhibited. The constant current circuit\nand tristate inverters 48 of FIG. 2b are in nonconducting\nstales with signals 4)3 and 4)~ at \"L\" levels.\nAddress inputting to external address input terminals is\ncomposed of row address a8 to a~ and column address ~ to\na7. The row address a8 to a20 inputs to select one of memory\nblocks and one of the word lines during the data loading\n\nCase 9:02-cv-0005&-dH Document I\n,546,341\n\nFHed 03/05/200.2\n\nPage 76 of 101\noperation so as to write data on all bit lines into memory\ncells at one time, i.e., the perform a page program in the\nprogramming operation after the completion of the data\nloading operation. The column address a0 to a7 is address\nsignals having 256 cycles during the data loading operation.\nThe column decoder 30 of FIG. 2b responds to the column\naddress of 256 cycles based on the toggling of external write\nenable Signal WE5 to render transfer transistors Ti to `1256\nconductive in sequence. At the same time, input buffer 26\ncorresponding to the respective column blocks sequentially\noutputs data input to the corresponding input/output termi-\nnal in response to the toggling of \\VEr Thus, oUtput data\nfrom the respective input buffers 26 is stored in sequence\ninto data latches PRk-1 to PBk-256 via sequentially turned-\non transfer transistors Ti to T256 and corresponding transfer 15\ntransistors 49.\nAfter the above-mentioned data loading operation, the\nprogramming operation is started. One characteristic feature\nof the present embodiment is that the programming opera-\ntion includes the NAND cell charging operation.\nFor the convenience of explanation of the programming\noperation, it is assumed that data stored in the data latches\nis to be written into memory transistors M4 connected to a\nword line WL4 in the memory block BKI.\nThe programming operation is perfonned during the time\nperiod between t5 and t3 as shown in FIG. II. During this\nperiod, p-well region 76, signals WE, PGM, 4)2' 4~' 4)~ and\n~ arid the line DCB stay at \"L\" levels while signals Xd,\nBLK, DS, ERA and 4)~ and the line SBL are all at \"H\" levels.\nThe clock $R' the program voltage V,,5,,, (=18 volts), the pass\nvoltage V,,oa (=10 volts) and the program inhibition voltage\nV,,1 (=7 volts) are supplied during this period. On the other\nhand, the row address a8 to a~, which is inputted during the\nabove-mentioned data loading operation, is latched in the\naddress buffer (not shown). Address signals P1, Ql and Rl\nwhich arc generated by predecoding address signals A,1,\n~7 to A20, ~ of the latched address, are input to the\ndecoder 120 of FIG. 5. Address signals A8,~ to A,0,Aj of\nthe latched address are input to the decoder 154 of FIG. 6.\nAt time t1, the control signal Xd goes to \"H\" level, and\naddress signals P1, QI and RI selecting the memory block\nBK! are input to the NAND gate 120 of FIG. 5. Then, the\noutput of the gate 120 goes to \"L\" level, and outputs of\nNAND gates 124 and 136 go to \"H\" levels. Thus, the first\nselection gate line SGLi-1 goes to a potential of 5 volts, and\nthe block selection control line BSC1 is boosted to the\nprogram voltage V,,9,,, of 18 volts by the pumping operation\nof the charge pump circuit 128. On the other hand, the\nsecond selection gate line SGL1-2 is boosted to the pass\nvoltage V,,~, of 10 volts by the pumping operation of the\ncharge pump circuit 152 with \"H\" level transferred via\ntransfer transistors 140, 142 and 150. Each decoder 120\nassociated with unselected memory blocks BK2 to BK1024\ngoes to \"H\" level, and the output of each NAND gate 124\ncorresponding thereto goes to \"L\" level. Thus, unselected\nblock selection control lines BSC2 to BSC1O24 go to a\nreference potential of 0 volts.\nAt time t1, the program control signal PGM goes to \"L\"\nlevel and the common source line CSL, which is the output\nline of the source line driving circuit 22 of FIG. 7, is boosted\nto the program inhibition voltage V,,1. That is, if PGM goes\nto \"L\" level, the common source line CSL goes to the\nabsolute value, for example 2 to 3 volts, of the threshold\nvoltage of D-type transistor 206 and is thereby boosted to the\nprogram inhibition voltage V,,1 by means of the charge pump\ncircuit 208.\nA~p~eviously mentioned, since address signals A8,A~ to\nA,0,A10 selecting the word line WL4 were input to the\ndecoder 154 of FIG. 6 in the previous data loading operation,\nthe output of the decoder 154 associated with CGL4 is at \"L\"\n~ level, and the outputs of the decoders 154 associated with\nunselected word lines WLI to WL3 and WLS to WL8 are at\n\"H\" levels. Thus, the output of NAND gate 156 associated\nwith the selected word line WL4 is at \"H\" level, and the\noutput of NAND gates 156 associated with the unselected\nto word lines are at \"L\" levels. At time 13, the clock 4)~ is\ngenerated. Then, NAND gate 178 and NOR gate 188 asso-\nciated with the selected word line WL4 respectively output\nthe clock 4iR and \"L\" level, thereby providing the program\nvoltage Vpgm on the selected control gate line CGL4. On\nthe contraty, NOR gates 188 associated with unselected\nword lines output the clock $R' thereby providing the pass\nvoltage V,, on unselected control gate lines CGL1 to CGL3\nand CGL5 to CGLS.\nAt time t1, the line SBL goes to \"H\" level. Thus, transfer\ntransistors of FIG. 2b are all turned on so as to transfer data\nstored in latches PBk-1 to PBk-256 to corresponding bit\nlines BLk-1 to BLk-256. All memory transistors of the\nselected memory block BK1 in the previous block erase\nmode were erased to \"L\" levels, i.e. logic \"0\" data. In the\n~ data loading operation after a block erasing mode, latches\ncorresponding to memory transistors which are to write \"H\"\nlevels, i.e. logic \"1\" data were stored to \"L\" level, i.e. logic\n\"0\" data while latches corresponding to memory transistors\nwhich are to write logic \"0\" data were stored to logic \"1\"\ndata. For the convenience of explanation, assume that logic\n\"I\" data is written into a memory transistor 240 which is\nconnected to the selected word line WL4 and bit line BL1-2\nof memory block BK1 in the \ufffd column block CB1 of FIG.\na while logic \"0\" data is written into the remaining memory\n~ transistors connected to the word line WL4 thereof. Then,\nthe latch PB1-2 has already stored logic \"0\" data while the\nremaining latches have already stored logic \"1\" data in the\ndata loading operation. Thus, after time 13, the conduction of\ntransfer transistors 44 causes the bit line BLI-2 to go to \"L\"\n~ level and the remaining bit lines to go to \"H\" levels of 5\nvolts.\nConsequently, during the Lime duration between t, and t2,\nthe transfer transistor array 34-1 of FIG. 2a is conducting,\nand the first and second selection lines SL1 and SL2 in the\nselected memory block BK! respectively maintain 5 volts\nand V,,,, (=10 volts) while the selected word line WL4 and\nunselected word lines WL1 to WL3 and WLS to WLS\nmaintain V,,8,,, (=18 volts) and V,,,,, respectively. During the\nprogramming operation, since the common source line CSL\nso maintains the program inhibition voltage V,,, (=7 volts), the\nsecond selection transistor ST2 and memory transistors Ml\nto MS in the block BK1 are all turned on, and the first\nselection transistor 242 connected to the bit line BL1-2 is\nturned on while remaining first selection transistors exelud-\ntag the translator 242 in the block BK1 are turned off. Thus,\ncurrent paths of memory transistors in the NAND cell\nincluding the memory transistor 240 are connected with the\nbit line BL1-2, and channels of the memory transistors and\nthe respective junction capacitor of their sources and drains\nso are thereby discharged to a reference potential of 0 volts.\nHowever, first selection transistors STI associated with\nmemory transistors which are to write logic \"0\" data are\nturned off, and channels of memory transistors in the NAND\ncells associated therewith and the respective junction capaci-\ntors of their sources and drains are charged to the program\ninhibition voltage Vi,, (=7 volts). Thus, during the Lime\nperiod of about 100 ~isec between ti and t2, a NAND cell\n\n* Case 9:02-cv-00058~.tH\n\nDocument I\n,546,341\n\nFHed 03/05/2002\n\nPage 77 of 101\ncharging operation associated with memory transistors\nwhich are programmed to logic \"0\" data is carried out.\nThrning to FIG. 11, the Lime duration between t2 and t3,\ni.e. the period of about 2 msec, is a period to perform\nsubstantial programming. At time t2, the signal SLE goes to s\n\"H\" level and, as can be seen in FIG. 8c, 46 goes from \"H\"\nlevel to \"L\" level while 4~ goes from \"L\" level to \"H\" level.\nThus, transistors 144 of FIG. 5 are turned on, thereby\ncausing all of second gate lines SGLi-2 to be connected with\nthe reference potential. Thus, all of second selection tran-\nsistors ST2 in the selected memory block BK! are turned\noff. During this period, the program voltage V,,,,,, of about\nvolts is applied on the word line WL4 in the selected\nmemory block BK1, and source, drain and channel of the\nmemory transistor 240 are applied to 0 volts. Thus, the\nfloating gate of the transistor 240 is accumulated with\nelectrons by the F-N tunneling, thereby causing the transis-\ntor 240 to be changed into an enhancement mode transistor\nhaving a threshold voltage of about 0.8 volts. However,\nsince junction capacitors of sources and drains of memory\ntransistors excepting the transistor 240 and their channels\nare charged to the program inhibition voltage V,,,, injection\nof electrons into floating gates of these transistors is inhib-\nited and these transistors remain as depletion mode transis-\ntors storing logic \"0\" data. That is, NAND cells associated\nwith memory cells which are programmed to logic \"0\" data\nare blocked from connection to corresponding bit lines by\nthe above-mentioned NAND cell charging, thereby being\nprevented from writing.\nAs discussed above, the voltage relationship of significant\nportions during the NAND cell charging and the program-\nming operation can be summarized in the following TABLE\n.\n\n\n\nVoltage States\n\nVoltage States\n\n\nfluting NANI)\n\nDuring\n\n\nCcli\n\nProgrananing\n\n\nCharging Period\n\nPeriod\n\nPIrsL selection Line SLI\nV\nV\n\nOf Selected Memory Btock\n\n\n\nUnselectedWordLinca\nOf Selected Memory Block\n\nV,,,,,=1OV\n\nV~,,=l0V\n\nSelectedWordUneOf\nSelected Memory Block\n\nV1,~,,,=l8V\n\nV,,~l8V\n\nSecondSctectionlineSL2\nOf Selected Memory Block\n\nV,,,=IOV\n\nOV\n\nCommon Source Line CSL\nWdllElectrode\n\nV,~ = 7 V\nOv\n\n`I,,, = 7 V\noV\n\nThe time period between t3 and t5, i.e. the period of 500\nnsec, is a period to discharge the boosted voltage on the bit\nlines and the word lines. At time t3, control signals WE and\nPGM and the line DCB go to \"H\" levels, and control signals\nBLK and DS, voltages Vpgm, V,,,,, and V,,, and the line SBL\ngo to \"L\" levels of 0 volts. The clock 4~R stops pulsing to be\nfixed at \"H\" level at the time t3. On the other hand, during\nthis period, 4~ maintains \"H\" level and 42 and 4~ maintain\n\"L\" levels. Thus, the source line driving circuit 22 outputs\nthe reference potential on the common source line CSL.\nControl gate lines CGL1 to CGL8 of FIG. 6 go to a potential\nof 0 volts, and block selection control lines BSC1 to\nBSC1O24 of FIG. S go to a potential of 5 volts. This results\nin causing all word lines to be discharged to the reference\npotential. At time t4, Xd goes to \"L\" level and BLK and DS\ngo to \"H\" levels. Thus, during the time period between t4\nand t5, block selection control lines BSCI and first and\nsecond selection gate lines SGLi-1 and SGLi-2 go to the\nreference potential. On the other hand, since the line DCB\nand the signal $j are at \"H\" levels during the time period\nbetween t3 and ~, the boosted voltages on the bit lines are\ndischarged to the reference potential via transistors 37. At\ntime t5, the signal $~ goes to \"L\" level.\n\nProgramming Verification Mode\nThe programming verification mode is performed imme-\ndiately after the programming mode. The programming\nverification operation of the present invention is similar to\nthe reading operation as will be discussed later. The differ-\nence as compared with the reading operation is that the\nvoltage applied to a selected word line is a minimum\nis threshold voltage which is to be written into memory\ntransistors. This minimum threshold voltage will be referred\nto as a programming verification voltage, It is assumed that\nthe programming verification voltage is 0.8 volts in the\npresent embodiment.\nThe programming verification operation is carried out\nimmediately after Lime t5 in FIG. 11, and a timing chart of\nthe programming verification operation is of the time period\nbetween t2 and t4 as shown in FIG. 12. At the initiation of\nthe programming verification, Le. at Lime t5 of FIG. 11 or\ntime t2 of FIG. 12, control signals Xd, $~ and 4t~ go to \"H\"\nlevels and signals 4,' PVF and SUP and the line DCB go to\n\"L\" levels. Thus, during the programming verification\noperation, control signals WE, PGM, SLE, Xd, BLK, DS,\nERA, $~ and 4t~ and the clock ~ maintain \"H\" levels, and\nvoltages V,,gm, Vp,,, and V,,,. lines SBL and DCB and control\nsignals 4~, 4~, PVF and SUP maintain \"L\" levels.\nIt is now assumed that the programming verification\noperation is performed to determine if a memory transistor\nof FIG. 2a which was written to a logic \"1\" data in the\n~ previous programming mode was programmed with a\ndesired minimum threshold voltage.\nWhere a command for executing a programming verifi-\ncation after completion of programming operation is input to\nEEPROM from the microprocessor via input/output tenni-\nnals or other terminals or where a programming verification\noperation is automatically carried out after a programming\noperation, data stored into latches PBk-1 to PBk-256 in the\nprogramming operation is succeeded without reset by the\n~ programming verification operation. Thus, at the beginning\nof the programming verification operation, the latch PB1-2\nis storing logic \"0\" data and the remaining latches are storing\nlogic \"1\" data.\nAt time t2 of FIG. 12, the control signal Xd goes to \"H\"\n~ level and the decoder 120 of FIG. 5 then outputs \"L\" level\nin response to address signals P1, Ql and RI designating the\nmemory block BK!. Then, since 4~ and 4~ respectively\nmaintain \"H\" level and \"L\" level, first and second selection\nlines SGLi-1 and SGL1-2 and the block selection control\n~ line BSC1 go to \"H\" levels of 5 volts.\nAt time t2, the control signal PVF goes to \"L\" level and\naddress signals A8/A~ to A11/~ designating the word line\nWL4 are fed to the decoder 154 of FIG. 6. Then, NAND gate\nbecomes of high impedance and the verifying voltage\nso generator 164 provides the verifying voltage of 0.8 volts on\nthe control gate line CGL4. However, each decoder 154\nassociated with unselected word lines WL1 to WL3 and\nWLS to WL8 output \"H\" levels. Then, the verifying voltage\ngenerator 164 becomes high impedance and NAND gate 158\noutputs \"H\" level. Thus, control gate lines CGL1 to CGL3\nand CGLS to CGL8 go to \"H\" level of 5 volts. On the other\nhand, since PGM maintains \"H\" level at t2, the source line\n\nTABLE 2\n\n* Case 9:02-cv-00058-JH\n\nDocument I\n,546,341\n\nFHed 03./05/2002\n\nPage 78 of 101\ndriving circuit 22 of FIG. 7 provides the reference potential\non the common selection line CSL.\nConsequently, the transfer transistor array 34-1 of FIG. 2a\nis conductive and the first and second selection lines SL1\nand SL2 and unselected word lines WL1 to WL.3 and WLS\nto WLS go to the potential of 5 volts while the selected word\nline WL4 goes to the potential of 0.8 volts. Thus, transistors\nconnected with the selection lines SL1 and SL2 and the\nunselected word lines are turned on.\nAt time t2, the control signal $~ goes to \"H\" level, thereby io\ncausing the constant current circuit 33 of FIG. 2b to be\nenabled. Thus, the constant current transistors 54 supply\nconstant current of about 4~A to bit lines via connecting\nnodes 36 and transistors 40 and 38.\nAssume that the programmed memory transistor 240 has i~\nfailed to program, i.e. the threshold voltage of the transistor\nwas below the program verit~ing voltage of 0.8 volts.\nThen, the transistor 240 is turned on and the bit line BL1-2\nconnected thereto goes to the reference potential of 0 volts.\nSince all transistors of NAND cells in the memory block ~\nBK1 which are connected with bit lines excluding the bit\nline BLI-2 are turned on, the bit lines also go to the\nreference potential. The period of time when word lines\nWL1 to WLS and bit lines are established to the predeter-\nmined voltages in such a manner is a period of about 2psec ~\nbetween t2 and t3 of FIG. 12.\nThe time period between t3 and t4 of FIG. 12, i.e. the\nperiod of about 500 nsec, is for verilication sensing. The\ncontrol signal $~ goes to \"H\" level at time t3, and transistors\nof FIG. 2b are thereby turned on. The transistor 50 whose 30\ngate is connected with the bit line BL1-2 via transistors 38\nand 40 is turned off by the reference potential on the bit line\nBL1-2, thereby causing the latch PB1-2 to maintain logic\n\"0\" data. Similarly, since other bit lines are also at the\nreference potential, transistors 50 associated with these bit 35\nlines are turned off and latches excepting the latch PBI-2\nthereby maintain previously stored logic \"I\" data. Verifica-\ntion sensing data stored in the latches PElt-i to PBk-256 by\nthe above-mentioned verification sensing operation is con-\nnected to gates of transistors 212 to 216 of FIG. 9a via 40\nturned-on inverters 48 and lines 70. Thus, the \"L\" level\nverification sensing data stored in the latch PB1-2 is sup-\nplied via corresponding inverter 48 to the gate of transistor\nwhich constitutes NOR gate 234 of FIG. 9a associated\nwith the first column block CM, thereby rendering the 45\ntransistor 214 conductive and causing the line 210 to be\ndischarged to the reference potential. Consequently, since\nthe signal SF? goes to \"L\" level only when the programming\nverification is checked, FP1 goes to \"L\" level. However,\nsince latches in other column blocks CB2 to CB8 store \"H\" 50\nlevels, transistors 212 to 216 of NOR gate 234 correspond-\ning to each one of the blocks CB2 to CBS are in noncon-\nductive states. Thus, each line 210 maintains \"H\" level by\nmeans of pull-up transistors 218 and 220 and FP2 to FP8\nthereby stay at \"H\" levels. Thus, the output line 232 of the 55\nsummation circuit 236 of FIG. 9b goes from \"H\" level to \"L\"\nlevel. This represents that the memory transistor 240 was\nundesirably programmed. That is, it is checked that the\nthreshold voltage of the memory transistor 240 did not reach\nat a preset minimum threshold voltage. A program determi- so\nnation signal PDS on the line 232 is connected to a timing\ncircuit (not shown) which generates Liming signals between\nt, and t5 as shown in FIG. 11 so as to perform a reprogram-\nming in response to the signal PDS being at \"L\" level. That\nis, reprogramming operation is automatically performed. It 65\nwould be noted that the reprogramming operation of the\npresent embodiment may automatically be performed by the\ninternal circuit of the present EEPROM without request of\neither reprogramming control or reloading of data from a\nmicroprocessor. However, if necessary, the microprocessor\nmay control the reprogramming operation in response to the\nsignal PDS from one of the input/output terminals of the\npresent EEPROM chip.\nAssuming that the memory transistor 240 reached the\ndesired threshold voltage of 0.8 volts by the reprogramming\noperation, then the transistor 240 is in a nonconductive state\nduring the programming verification operation performed\nafter the reprogramming operation. Thus, the bit line BL1-2\nis charged to the potential of about 2 to 3 volts by the\nconstant current supplied via the constant current transistor\n, thereby rendering conductive the transistor 50 connected\nwith the bit line BL1-2. Consequently, the verification\nsensing data of latch PB1-2 is changed from logic \"0\" data\nto logic \"I\" data. As previously discussed, other latches are\nstoring logic \"1\" verification sensing data. Thus, all of the\nlatches PBk-1 to PBk-256 store logic \"1\" verification sens-\ning data. That is, if all memory transistors were well\nprogrammed in the page programming operation, verifica-\nLion sensing data stored in the latches is changed into logic\n\"1\". Then, transistors 212 to 216 constituting NOR gates 234\nof FIG. 9a are all turned off, and signals FP1 to FP8 go to\n\"H\" levels with the signal SF? at \"L\" level during the check\nof programming verification. Consequently, the summation\ncircuit 236 of FIG. 9b outputs the program determination\nsignal PDS, which is at \"if' level. This represents that the\nprogramming operation had successfully been performed.\nNow assume that some of memory transistors pro-\ngrammed with logic \"1\" had successfully been programmed\nand the remainder had unsuccessfully been programmed.\nThen, during the followed programming verification opera-\ntion, latches corresponding to the former memory transistors\nare changed so as to store logic \"I\" data, while latches\ncorresponding to the latter memory transistors maintain\nlogic \"0\" data. Since latches in the former case are storing\nlogic \"1\" data, their corresponding bit lines are charged to\nthe potential of 5 volts during the followed reprogramming\noperation. However, in the same manner as the above-\nmentioned programming operation, since, in the reprogram-\nming operation, a selected first selection line stays at 5 volts\nand junctions of sources and drains of memory transistors\nand their channels are charged to the program inhibition\nvoltage of 7 volts, first transistors connected with the\ncharged bit lines on the selected first selection line are in\nnonconductive states. Thus, during the reprogramming\noperation, the successfully programmed memory transistors\nare prevented from programming by the charged program\ninhibition voltages. However, in the case of the latter, i.e. the\nunsuccessfully programmed memory transistors, since their\ncorresponding latches arc storing logic \"0\" data, reprogram-\nming is performed only on them. With such repeating\noperations, if all memory transistors on a selected word line\nwhich are programmed with logic \"1\" data were success-\nfully programmed, the program determination signal PDS\noutputs \"H\" level during the abovementioned programming\nverification operation, and the reprogramming operation is\nterminated. The present circuit used in the above-mentioned\nprogramming verification operation may also be applied to\nEEPROMs with NOR-type memory arrays.\nThe programming verification techniques as discussed\nabove have various advantages as follows. First, the pro-\ngramming verification operation can automatically carried\nout by the internal circuit without the control of an external\nmicroprocessor. Second, since the data register is used as\ndata latches in a data loading mode, verification sensing\n\n* Case 9:02-cv-00058-JH\n\nDocument I\n,546,341\n\nFHed 03./05/200~\n\nPage 79 of 101\ncircuits in a programming verification mode and sense\namplifiers in a reading mode, as will be discussed herein-\nbelow, simplification of peripheral circuits may be accom-\nplished. Third, the threshold voltages of programmed\nmemory transistors may be Lightly distributed within a 5\nnarrow range above a preset minimum threshold voltage,\nand over-programming may be prevented. The tight distri-\nbution of threshold voltages can be accomplished by the\nexecution of the programming operation within a shorter\nperiod, since successfully programmed memory transistors\nare automatically inhibited from programming due to the\nchanged data of their corresponding latches.\nReading Mode\nFIG. 12 illustrates a timing chart of the reading operation\naccording to the present embodiment.\nThe time period between ti and t2 in the drawing is a\nperiod to discharge word lines WL1 to WL8 and all bit lines\nBLk-1 to ELk-256 to the reference potential and to reset so\nthat latches PBk-1 to PBk-256 stores logic \"0\" data. During\nthis period, the control signal 4~ and lines SBL and DCB\nstay at \"H\" levels. Thus, bit lines BLk-1 to BLk-256 are\ndischarged to the reference potential via the transistor 37 of\nFIG. 2b, and latches PBk-1 to PBk-256 are reset to logic \"0\"\ndata by the conduction of transistors 37 and 44. During the\nLime period between t1 and t2, a timing chart of control\nsignals WE, PGM, SLE, Xd, BLK, DS and ERA, the clock\nR and voltages Vpgm, V,,,, and V,,, is identical to the timing\nchart between t3 and t5 shown in FIG. II. Control signals\nPVF and SUP keep \"H\" levels during operations excepting\nthe programming verification operation.\nThe time period between t2 and t4 is a period for sensing\ndata read out from memory cells and storing the sensing data\ninto latches PBk-1 to PBk-256. During the period, WE,\nPGM, SLE, Xd, ELK, DS, ERA, 4~, 4~ and $R maintain \"H\"\nlevels, and ~pgm' ~ V,,,, lines SBL and DCB, $~ and 4~\nkeep \"L\" levels.\nAn explanation will now be given, assuming that a\nreading operation is performed from memory transistors ~\nconnected to the word line WL4 in the memory block BK1\nwhich was page programmed in the above-mentioned pro-\ngramming mode.\nOperation between t~ and t3 is performed in a similar\nmanner as the verification operation as discussed above.\nThus, an explanation will be given in brief. The block\nselection circuit of FIG. 5 associated with the selected\nmemory block BK1 makes first and second selection gate\nlines SGLi-1 and SGL1-2 and the block selection control\nlines BSC1 held at 5 volts in response to address signals P1,\nQl and RI addressing the block 131(1. Since the control signal\nPVF is at \"H\" level, the verifying voltage generator 164 of\nFIG. 6 is in a high impedance state and the NAND gate 158\nis being enabled. Thus, the control gate line CGL4 corre-\nsponding to the selected word line WL4 is at the reference\npotential of 0 volts in response to address signals A8/A~ to\nA10/A~ designating the word line WL4. However, control\ngate lines CGL1 to CGL3 and CGL5 to CGL8 correspond-\ning to unselected word lines WL1 to WL3 and WLS to WLS\nare at \"H\" levels of 5 volts. On the other hand, the source\nline driving circuit 22 of FIG. 7 outputs the reference\npotential on the common source line CSL. Consequently, the\ntransfer transistor array 34-1 of FIG. 2a is conductive, and\nfirst and second selection lines SLI and SL2 and unselected\nword lines WL1 to WL3 and WL5 to WL8 in the block BK1\nare thereby at 5 volts while the selected word line WL4\ntherein is at 0 volts.\nThe control signal 4)3 goes to \"H\" levels at time t2, thereby\ncausing the current source circuit 33 to be enabled. Thus, the\nconstant current transistors 54 supply the current of about\n~iA onto bit lines BLk-1 to BLk-256 via connecting nodes\nand transistors 40 and 38. Since only the memory\ntransistor 240 is programmed with logic \"I\" the bit line\nBL1-2 is charged to about 2 to 3 volts and the remaining bit\nlines go to 0 volts. At time t3 of FIG. 12, the control signal\n)2 goes to \"H\" level, thereby rendering transistors 52 of FIG.\nb conductive. Then, only the transistor 50 associated with\nthe bit line BLI-2 is turned on, thereby making the latch\nPB1-2 sense and store the logic \"1\". However, remaining\nlatches continuously store logic \"0\" based on the previously\nmentioned reset operation since transistors 50 are turned off.\nThat is, page reading is accomplished. Data stored in the\nlatches PBk-1 to PBk-256 is output to input/output terminals\n/01 to 1/08 by a byte (8 bits) via inverters 48, transfer\ntransistors Ti to `1256 turned on in sequence in response to\ncolumn address of 256 cycles and toggles of \\VE~,, and\noutput buffer 28.\n\nModified Embodiments\nThe EEPROM of the first embodiment explained in\nconnection with FIG. 1 to FIG. 12 comprises the memory\narray including 1024 memory blocks each of which has\nNAND cells arranged in the same rows, and a source line\ndriving circuit for generating the program inhibition voltage\nprior to the programming or reprogramming operation in\norder to charge it to the NAND cells. However, it should be\nnoted that the present invention is not limited to such an\nembodiment. For example, the memory array used in other\nembodiments of the present invention may be comprised of\nmemory blocks having shared word lines as discussed\nhereinafter. To charge the program inhibition voltage to\nNAND cell, a capacitive coupling way from control gates\nmay be applied with no use of the source line driving circuit.\nThis modified embodiment is illustrated in FIG. 13 to FIG.\n.\nFIG. 13 consists of FIG. 13a and FIG. 2b. FIG. 13a shows\na memory array composed of memory blocks having shared\nword lines, and FIG. 2b shows the already discussed periph-\neral circuit connected with the memory array of FIG. 13a.\nFor simplification of the drawing, FIG. 13a shows only\nthe arrangement of memory cells and shared word lines\nwhich are associated with the k-th column block in the i-th\nmemory block SBK1. However, it should be noted that a\nmemory array 10 having memory cells of 16 mega bits as\nshown in FIG. 13a is arranged in the same manner as the\nmemory array of FIG. 2a excepting the shared word lines.\nRefening to FIG. 13a, each of memory blocks SBKi (i=l,\n, 3 512) is comprised of two submemory blocks, i.e.\nan upper memory block or a first submemory block IJSBKi\n~ and a lower memory block or a second submemory block\nLSBKI. Each of the upper and lower memory btocks USBKi\nand LSBKI has the same configuration as each of the\nmemory blocks of FIG. 2a. Word lines WL1 to WLS in the\nupper memory block USBKi are correspondingly connected\nso with word lines WL1 to WLS in the lower memory block\nLSBKI. That is, the upper memory block USBKI shares the\nword lines WL1 to WL8 with the lower memory block\nLSBK1.\nThe word lines WL1 to WL8 are respectively connected\nto control gate lines CGL1 to CGLS via current paths of\ntransfer transistors 13T2 to J3T9. A first upper selection line\nUSL1 and a first lower selection line LSL1 are connected to\n\n\n-. * Case 9:02-cv-00058-JH\n\nDocument I\n,546,341\n\nFHed 03./05/20j~2\n\nPage 80 of 101\nupper and lower selection gale lines USGLI and LSGLi via\ncurrent paths of transfer transistors BT1 and BT11, respec-\ntively. Second upper and second lower selection lines USL2\nand LSL2 are connected to upper and lower ground selection\nlines UGSL and LGSL via current paths of transfer transis- 5\ntoes 13110 and BT12, respectively. Sources of second upper\nand lower selection transistors UST2 and LST2 are con-\nnected to a common source line CSL which is connected to\nthe reference potential, i.e. the ground. Drains of first upper\nand lower selection transistors UST1 and LST1 are respec- 10\ntively connected to corresponding bit lines.\nThe control gate lines CGL1 to CGL8 are connected to the\ncontrol gate driving circuit 20 explained in connection with\nFIG. 6. Upper and lower selection gate lines USGLi and\nLSGLI are respectively connected to corresponding block ~\nselection control circuits 318 of FIG. 14. Each of the block\nselection control circuits 318 serves to select one of upper\nand lower memory blocks in a selected memory block\ndesignated by address according to respective operation\nmodes. It should be noted that the block selection control\ncircuits 318 corresponding to the respective memory blocks\nSBK1 are provided on the substrate of the on-chip EEPROM.\nThus, it would be appreciated that two memory blocks\nsubstantially share one block selection control circuit since\neach block selection control circuit controls one memory\nblock comprised of upper and lower memory blocks. This\nresults in relatively increasing the area of memory array on\nthe chip substrate of fixed size so as to increase the memory\nstorage capacity since the chip occupying area of the periph-\neral circuit is decreased.\nThe upper ground selection line UGSL and the lower\nground selection line LGSL are connected to a ground line\ndriving circuit 320 illustrated in FIG. 15. The ground line\ndriving circuit 320 is a circuit connected in common with\nupper ground selection lines UGSL and lower ground selec-\ntion lines LGSL in memory block SBKi. The ground line\nchiving circuit 320 serves to provide proper voltages onto\nthe upper and lower ground selection lines UGSL and LGSL\naccording to the respective operation modes.\nReferring to FIG. 14 showing the block selection control\ncircuit which controls the i-th memory block SBKi, a\ndecoder 322 receives address signals P1, Ql and RI and the\ncontrol signal Xd. The address signals P1, Ql and RI are\nsignals predecoded by address signals A12/X~ to A~/A~ of\nrow address signals A11/~ to AZdA from address buffer\n(not shown). The row address signal A11/A~7 is input to a\ntiming circuit (not shown) in order to generate control\nsignals ~ A11I,X~ and A1~,A~ for selecting one\nof either the upper memory block US~Ki or the lower\nmemory block LSBK1 according to the respective operation\nmodes. Logic states of these control signals according to the\nrespective operation modes are given in the following\nTABLE 3, wherein \"H\" represents \"H\" level of 5 volts and\n\"L\" represents \"U' level of 0 volts.\n\n\nTABLE 3\n\n\nUpper Mcmocy Block\nSelection A1, = H\n\nLower Memory Block\nSelection A,, = L\n\nReading,\nProgramming\nErasing And Programming\nMode Verification Mode\n\nReading.\nProgramming\nErasing And Programming\nMode Vetificatioti Mode\n\n\nH H It\n\n\n\nUpper Memory Block\nSelection A,, = H\n\nLower Memory Block\nSelection A,, = L\n\n\nReading,\n\nReading,\n\n\nProgramming\n\nProgramming\n\n\nErasing And Programming\n\nEzasing And Programming\n\n\nMode Verification Mode\n\nMode\n\nA,,,\n\nL L\nL H\n\nL H\nL L\n\nX~\n\nH L\n\nH H\n\nThe output of the decoder 322 is connected to one input\nterminal of NAND gate 324 and an input terminal of an\ninverter 326. The other input terminal of NAND gate 324 is\nconnected to the erase control signal ERA. The output of the\nNAND gate 324 is connected to the upper selection gate line\nUSGLI via a CMOS transfer gate 328, which consists of\na-channel transistor 350 and p-channel transistor 352, and\nthe current path of D-type transistor 330. Between a con-\nnecting node 358 and the reference potential is connected\nthe current path of n-channel transistor 332. Gates of\nN-channel transistors 350 and 332, p-channel transistor 352\nand D type transistor 330 are connected to control signals\nA,,,,, A111, A110 and WE,,,, respectively. The control signal\nWE,,, is at \"L\" level during the block erasing operation and\nis at \"H\" level during remaining operations. The output of\nthe NAND gate 324 is also connected to the lower selection\n~ gate line LSGLi via a CMOS transfer gate 334, which\nconsists of n-channel transistor 354 and p-channel transistor\n, and the current path of D-type transistor 336. The\ncurrent path of n-channel transistor 338 is connected\nbetween a connecting node 360 and the reference potential.\nGates of n-channel transistors 354 and 338, p-channel tran-\nsistor 356 and D-type transistor 336 are connected to control\nsignals A~, A111, A111 and WE,,,, respectively. The output of\nthe inverter 326 is connected to the block selection control\nline BSCi via current paths of D-type transistor 340 and\nn-channel transistor 342,.which are connected in parallel,\nand the current path of D-type transistor 344. The gate of the\nD-type transistor 340 is connected to the output of the\ndecoder 322, and gates of the n-channel transistor 342 and\nthe D-type transistor 344 are connected to the power supply\n~ potential Vcc of 5 volts. Two input terminals of NOR gale\nare connected to the clock 4t~ and the output of the\ndecoder 322, respectively. Between the output of the NOR\ngate 346 and the line BSCi is connected a charge pump\ncircuit 348.\n~ If address signals selecting the memory block SBKI input\nto the block selection control circuit 318, the block selection\ncontrol line BSCi is at a potential of about 4.3 volts in\nerasing, programming verification and reading modes, and is\nat the program voltage V,~,,, of 18 volts in a programming\n~ mode. On the contrary, the block selection control line of\nrespective ones of block selection control circuits associated\nwith unselected memory blocks is at the reference potential\nof 0 volts in all modes.\nIf the memory block SBK1 is designated by the address\nso signal and the address signal All is at \"H\" level, the upper\nselection gate line USGL1 is at a potential of 5 volts in a\nprogramming, a programming verification and a reading\nmodes, and the lower selection gate line LSGLI is at a\npotential of 0 volts by conduction of the transistor 338 in\nsaid modes. Similarly, if the memory block SBK1 is\naddressed by the address signal and the address signal A,,\nis at \"L\" level, the lower selection gate line LSGLi is at a\nTABLE 3-continued\n\nA,,,,\n\nA,,1\n\nL\nH\n\nL\nII\nL\n\nL\nL\n\nL\nL\n\nCase 9:02-cv-00058-JH\n\nDocument I\n,546,341\n\nF~ed 03/05/2O~2 Page 81 of 101\npotential of 5 volts in programming, programming verifica-\ntion and reading modes, and the upper selection gate line\nUSC3Li is at a potential of 0 volts by conduction of the\ntransistor 332 in said modes. On the other hand, upper and\nlower selection gate lines USGLI and LSGLI are both in ~\nfloating states of about 2 to 3 volts in a block erasing mode.\nReferring to FIG. 15, the ground line driving circuit 320\nis comprised of inverters 362 to 374 and NOR gates 376 and\n. `The driving circuit 320 outputs 0 volts onto upper and\nlower ground selection lines IJGSL and LGSL in a program-\nming mode. If the upper memory block is selected in reading\nand programming verification modes, the upper ground\nselection line UGSL goes to \"H\" level of 5 volts, and the\nlower ground selection line LGSL goes to \"L\" level of 0\nVolts. However, if the lower memory block is selected in\nreading and programming verification modes, the lower\nground selection line LGSL goes to \"H\" level of 5 volts, and\nthe upper ground selection line UGSL goes to \"L\" levels of\nvolts. On the other hand, upper and lower ground selection\nlines UGSL and LGSL go to \"H\" levels of 5 volts in a block\nerasing mode.\nOperations of the modified embodiment are almost the\nsame as those of the first embodiment, excepting operation\nto select either upper or lower memory block and operation\nto charge NAND cells by way of a capacitive coupling\ntechnique in a programming operation. Thus, a brief expla- ~\nnation of operation of the modified embodiment will be\ngiven, referring to the accompanying timing charts.\nFIG. 16 shows a timing chart of the block erasing mode.\nIn the drawing, the time period between t1 and t2 is for\ndischarging all word lines in the memory array it) to the\nreference potential of 0 volts. In this period, control gate\nlines COL1 to CGLS are at the reference potential as\ndiscussed in connection with FIG. 6. During this period,\nBLK maintains \"L\" level, and the predecoder (not shown)\ngenerates address signals P1, QI and RI being at \"H\" levels\nin response to the signal BLK. Thus, the decoder of FIG. 14\noutputs \"L\" level. Consequently, block selection control\nlines BSC1 to BSCS12 are all at the potential of about 4.3\nvolts, and transfer transistors BT2 to BT9 of transfer tran-\nsistor arrays 34-1 to 34-512 of FIG. 13a are all turned on,\nthereby grounding all word lines.\nThe time period between t~ and t3 of FIG. 16 is for erasing\na selected memory block During the period, control gate\nlines CGL1 to CGLS remain the reference potential identical\nto the case between t1 to t2. The block selection control\ncircuit 318 of FIG. 14 associated with the selected memory\nblock outputs the potential of about 4.3 volts onto a selected\nblock selection control line. However, the block selection\ncontrol circuits associated with unselected memory blocks\noutput the reference potential onto unselected block selec-\ntion control lines. Thus, word lines of upper and lower\nmemory blocks in the selected memory block at time t2 are\nall at the reference potential, and all of word lines in\nunselected memory block are in floating states. However,\nsince the erase voltage V,,,, of 20 volts is applied to the well\nelectrode 114 of FIG. 4 at time t2, all word lines in the\nunselected memory blocks arc capacitively coupled to about\nvolts, and data of memory transistors in the unselected\nmemory blocks is not erased. However, during the time\nperiod between t2 and t3, every memory transistor in the\nselected memory block is changed into a D-type transistor\nhaving a threshold voltage of about -2 to -3 volts by the\nerase voltage which is applied between its channel and\ncontrol gate. That is, logic \"0\" data is stored. 65\nOn the other hand, during the block erasing period\nbetween t2 and t3, since the selected block selection control\nline is at the potential of about 4.3 volts, and upper and lower\nselection gate lines USGLi and LSGLi are at about 2 to 3\nvolts, and upper and lower ground selection lines UGSL and\nLGSL are at 5 volts, the first upper and lower selection lines\nUSL1 and LSLI associated with the selected memory block\nare at about 2 to 3 volts and the second upper and lower\nselection lines USL2 and LSL2 associated with the selected\nmemory block are in floating states. Thus, when any one of\nthe second upper and lower transistors connected with the\nsecond upper and lower selection lines fails, the flow of\nleakage current is prevented via the second upper and lower\nselection lines USL2 and LSLZ from the well electrode 114.\nDuring the block erasing operation, the voltage relationship\nof significant portions may be summarized in the following\nis TABLE 4.\n\nTABLE 4\n\n\n\nSelected Memory\nBlock\n\nUnselected Metnosy\nBlock\n\nFirst Upper And Lower\n\nApproximately\n\nFloating\n\nSelection Line, USL1\n-3 V\n\n\nAnd LSL1\n\n\n\nWord Lines WLI to WLS\nV\n\nApproximately 20 V\n\nSecond Upper And Lower\n\nFloating\n\nFloating\n\nSelection Lines USL2\n\n\n\nand LSL2\n\n\n\nWellElectrode\nV\nV\n\nThe time period between t3 and t4 of FIG. 16 is for\ndischarging word lines in unselected memory blocks to the\nreference potential. During this period, control gate lines\nCGL1 to CGL8 maintain the reference potential by the\ncontrol signal DS as previously discussed in connection with\nFIG. 6. The control signal BLK maintains all block selection\n~ control lines BSC1 to BSCS12 to about 43 volts, thereby\ncausing au word lines to be discharged to the reference\npotential. Upper and lower gate lines UGLi and LSGLi are\nalso maintained at the reference potential by Xd. On the\nother hand, the line DCB being at \"H\" level causes bit lines\nto be discharged to the reference potential.\nFIG. 17 shows a timing chart of the programming mode\nof the modified embodiment. Referring to FIG. 17, the data\nloading operation is performed prior to time t5. The data\nloading operation is performed in the same manner as that of\nthe first embodiment as discussed in connection with FIG.\nb. The time period between t1 and t2 is for writing data into\nselected memory transistors. As discussed in the data load-\ning operation of the first embodiment, bit lines correspond-\ning to memory transistors into which logic \"1\" data is\nwritten are at \"L\" level of 0 volts while bit lines correspond-\ning to memory transistors into which logic \"0\" data is\nwritten are at \"H\" levels of 5 volts. After the time t,, the\nselected control gate line goes to the program voltage V~8,,,\nof 18 volts, and unselected control gate lines go to the pass\nvoltage V,,,,1 of 10 volts as previously discussed in connec-\ntion with FIG. 6. It is now assumed that the fourth control\ngate line CGL4 was designated by address signals. Then, the\ncontrol gate line CGL4 goes to the program voltage V,,~,,, of\nvolts and control gate lines CGL1 to CGL3 and COLS to\nCOLS go to the pass voltage V,we of 10 volts. It is also\nassumed that the third memory block was designated by\naddress signal and the address signal A1, was \"H\" level.\nThen, the decoder 322 of FIG. 14 outputs \"L\" level and the\nblock selection control line BSC3 goes to the program\nvoltage Vpgm of 18 volts after the time t1. At this time, the\nupper selection gate line USGL3 goes to the potential of 5\nvolts and the lower selection gate line LSGL3 goes to the\n\nso\n\nCase 9:02-cv-00058-JH\n\nDocument I\n,546,341\n\nFHed 03/05/200.2\n\nPage 82 of 101\nreference potential. Thus, the transfer transistor array 34-3\nof FIG. 13a is turned on. On the other hand, the ground line\ndriving circuit 320 of FIG. 15 provides the reference poten-\ntial onto the lines UGSL and LGSL during the programming\nperiod. Thus, the second upper and lower selection transis- 5\ntors UST2 and LST2 in the upper and lower memory blocks\nUSBK3 and LSBK3 are all nonconductive. The first lower\nselection line LSL1 in the lower memory block LSBK3 also\ngoes to the reference voltage via the transfer transistor BT11,\nthereby causing the first lower selection transistors LST1 to\nbe turned off. However, the first upper selection line USL1\nin the upper memory block USBK3 goes to \"H\" level of 5\nvolts via the transfer transistor BT1. During the above-\nmentioned programming operation, the voltage relationship\nof significant portions may be summarized in the following\nTABLE 5.\n\n\n\nTABLE 5\n\n\nSc\n\nlected Memory Block\n\nUnselected Lower\n\n\nSelected Upper\n\n\nMemory Block\n\nMemory Block\n\nSclectcdFirstUpper\n\nSV\n\n-\n\nSclectcd Line USL1\n\n\n\nUnselected First Lower\n\n-\nV\n\nSelected Line LSL1\n\n\n\nSciectedWordUne\ntJnseleciedWordLinc\n\nV,,~~I8V\nV~=l0V\n\nV,,~=1SV\nV,,,\"lOV\n\nSclecled Second Upper\nV\n\n-.\n\nSelection Line USL2\n\n\n\nUnselected Second Lower\n\n-\nV\n\nSelection Line LSL2\n\n\n\nWellEiccirode\n\nOV\n\nOV\nThus, during the programming operation, the high voltage\napplied onto word lines WL1 to WL8 causes the NAND cell\ncharging of upper and lower memory blocks USBK3 and\nLSBK3. Thus, since the first upper selection line USL1 is at\nthe potential of 5 volts, and bit lines associated with memory\ntransistors into which logic \"0\" data is written are at 5 volts\nwhile bit lines associated with memory transistors into\nwhich logic \"1\" data is written are at the reference potential\nof 0 volts, first upper selection transistors in the upper\nmemory block USBK3 which are connected with the latter\nmemory transistors are turned on, and first upper selection\ntransistors in the memory block USBK3 which are con-\nnected with the former memory transistors are turned off.\nThus, sources, drains and channels of memory transistors in\nNAND cells associated with the former memory transistors\ngo to the reference potential, and NAND cells associated\nwith the latter memory transistors are charged to a high\nvoltage. Consequently, during the programming period,\nfloating gates of the former memory transistors connected\nwith the upper word line WL4 accumulate electrons by way\nof the F-N tunneling, thereby changing into enhancement\ntransistors having a threshold voltage of about 0.8 volts.\nThat is, logic \"1\" data is stored. However, since channels of\nthe latter memory transistors and junction capacitors of their\nsources and drains are charged with a high voltage, the\nprogramming of these memory transistors is prevented.\nIn the same manner, the first lower selection line LSL1 so\nand the second lower selection line LSLZ in the unselected\nlower memory block LSBK3 are at the reference potential,\nand the first and the second lower selection transistors LST1\nand LST2 which are respectively connected to the lines\nLSL1 and LSL2 are thereby turned off. Thus, channels of\nmemory transistors of NAND cells in the lower memory\nblock LSBK3 and junction capacitors of their sources and\ndrains are charged with a high voltage so as to prevent\nprogramming.\nAt the time t2, the programming operation is terminated\nand the clock ~R stops clocking. Thus, the charge pump\ncircuit 348 is disabled and BSC3 thereby falls to the poten-\ntial of 5 volts. During the time period between t2 and t3, the\ncontrol signal DS at \"L\" level causes control gate lines\nCGL1 to CGL8 to be grounded. Thus, word linds in the\nmemory block SBK3 are discharged to the reference poten-\ntial. During the time period between t3 and t4, block selec-\ntion control lines BSC1 to BSCS12 and upper selection gate\nlines USGL1 to USGLS12 are discharged to the reference\npotential.\nThe programming verification operation may be per-\n`s formed from the time t4 of FIG. 17. The programming\nverification operation is similar to that of the first embodi-\nmenL The difference as compared with the first embodiment\nis in that the present embodiment has the block selection\ncontrol circuit for selecting one of either the upper or lower\nmemory block in a selected memory block. If the upper\nmemory block USBKi in a selected memory block is\nselected by means of the block selection control circuit of\nFIG. 14 in the programming verification operation, a\nselected block selection control line BSCi goes to the\n~ potential of about 4.3 volts, and the upper selection gate line\nUSGLi goes to the potential of 5 volts. Then, the ground line\ndriving circuit 320 of FIG. 15 outputs \"H\" level of 5 volts\nonto the upper selection gate line UGSL and \"L\" level of 0\nvolts onto the lower selection gate line LGSL. As discussed\nin connection with the first embodiment with reference to\nFIG. 6, in the programming verification operation, a selected\ncontrol gate line is at the program verifying voltage of 0.8\nvolts and unselected control gate lines are at the potential of\nvolts. Thus, the line BSCi of about 4.3 volts connected to\n~ the transfer transistor array 34i of FIG. 13a goes to a\npotential of about 7 volts since the potential of 5 volts on the\nunselected control gate lines is transferred from drains of\ntransfer transistors to their gates by way of capacitive\ncoupling. This operation is also identical in a reading\n~ operation. Consequently, a selected word line in the upper\nmemory block USBKi goes to the verifying voltage of 0.8\nvolts and unselected word lines go to the potential of 5 volts.\nThe first and second upper selection lines USL1 and USL2\nalso go to the potential of 5 volts. Thus, second selection\n~ transistors UST2 in the block USBKi are turned on, thereby\nconnecting NAND cells in the block USBKi to the grounded\ncommon source line CSL. However, the first and second\nlower selection lines LSL1 and LSL2 in the lower memory-\nblock. LSBKI are at the reference potential and the block\n~ LSBKi are at the reference potential and the block LSBKi\nare-at the reference potential and the block LSBKi is thereby\nunselected. The following programming verification and\nreprogramming operations are the same as operations\nexplained in the first embodiment in connection with the\n~ timing chart during the time period between t2 and t4 of FIG.\n.\nIn the modified embodiment, programming and repro-\ngramming techniques do not need a program inhibition\nvoltage generator connected with the respective bit lines to\ninhibit programming of logic \"0\" programmed cells and\nreprogramming of successfully logic \"1\" programmed cells.\nThus, the simplification of a peripheral circuit and the\nreduction of on-chip area can be accomplished. Otherwise,\nsince the program inhibition voltage is automatically gen-\nerated by the capacitive coupling technique during the\nprogramming and reprogramming operations, the program-\nming and reprogramming operations may be executed at a\nCase 9:02-cv-00058-JH\n\nDocument I\n,546,341\n\nFHed 03/05/2002\n\nPage 83 of 101\nhigh speed. Thus, since the present embodiment employs a\nself-program inhibition technique, the above-mentioned\nadvantages may be accomplished.\nIn the reading operation of the modified embodiment, a\nselected word line of 0 volts is used instead of the selected 5\nword line of 0.8 volts in the above-mentioned programming\nverification operation. Operation to select memory transis-\ntors in the reading operation is the same as that in the\nprograming verification operation. Page reading, page read-\nout sensing and the output from data output terminals are 10\nalso the same as operations explained in the first embodi-\nment in connection with FIG. 12.\nThus, EEPROMs of embodiments of the present inven-\ntion as described above can be designed so as to have\ncapabilities and reliability of improved programming, block\nerasing and programming verification. The peripheral cir-\ncuits associated with a reading and a programming verifi-\ncation according to embodiments of the invention can also\nbe used in a nonvolatile semiconductor memory with a\nNOR-type memory array.\nWhat is claimed is:\n. A nonvolatile semiconductor memory comprising:\nword lines formed over a surface of a semiconductor\nsubstrate;\ncell units arranged on said surface to form an array, each ~\nsaid unit including at least one memory transistor\nwhich has source and drain regions formed in said\nsubstrate and separated by a channel region; a floating\ngate formed over said channel region, and a control\ngate formed over said floating gate and coupled to a\ncorresponding one of said word lines, said array being\ndivided into a plurality of memory blocks each having\na plurality of cell units; and\na control circuit, responsive to an address, in a data erase\nmode, for applying an erase voltage to said substrate, ~\nand for floating word lines of memory blocks unse-\nlected by said address so that erasure of data in memory\ntransistors of said unselected memory blocks is pre-\nvented by capacitive coupling of a predetermined\namount of said erase voltage to said word lines of said ~\nunselected memory blocks.\n. A method for erasing data stored in a nonvolatile\nsemiconductor memory, during a data erase mode of opera-\ntion thereof, said memory comprising an array of cell units\nformed on a surface of a semiconductor substrate, each said ~\ncell unit including at least one memory transistor for storage\nof data each of said memory transistors having a floating\ngate and a control gate coupled to a corresponding one of a\nplurality of word lines, said array being divided into a\nplurality of memory blocks each being comprised of a\nplurality of cell units, said method comprising the steps of:\napplying an erase voltage to said substrate;\napplying a reference voltage to word lines of a selected\nmemory block in order to erase data of memory tran- ~\nsisters in said selected memory block; and\nfloating word lines of unselected memory blocks such that\nsaid data in said memory transistors of said unselected\nmemory blocks is prevented from erasure by capacitive\ncoupling of a predetermined amount of said erase\nvoltage to said word lines of said unselected memory\nblocks.\n. A method for preventing erasure of data in memory\ntransistors in unselected memory blocks in a nonvolatile\nsemiconductor memory, wherein said memory comprises a 65\nmultiplicity of cell units formed on a surface of a semicon-\nductor substrate and configured in an array, each cell unit\nhaving at least one memory transistor which has a source, a\ndrain, a floating gate, and a control gate connected to a\ncorresponding one of a plurality of word lines, wherein said\narray is divided into a plurality of memory blocks each\nincluding a plurality of said cell units and word lines, said\nmethod comprising the steps of:\nfloating word lines of said unselected memory blocks; and\napplying an erase voltage to said substrate so that data in\nsaid memory transistors of said unselected memory\nblocks is prevented from being erased by capacitive\ncoupling of a predetermined quantity of said erase\nvoltage to said word lines of said unselected memory\nblocks.\n. A method for preventing erasure of data in unselected\ncell units in a nonvolatile semiconductor memory, wherein\neach cell unit is formed on a surface of a semiconductor\nsubstrate and includes a plurality of memory transistors\nconnected in series, each said memory transistor having\nsource and drain regions formed in said substrate and\nseparated by a channel region, a floating gate formed over\nsaid channel region to store binary data, and a control gate\nformed over said floating gate, respective control gates of\nsaid memory transistors of said cell unit being connected to\nrespective ones of a plurality of word lines, said method\ncomprising the steps of:\napplying an erase voltage to said substrate; and\ncapacitively charging said word lines of said unselected\ncell units to a pretermined amount of said erase voltage.\n. An electrically erasable and programmable read-only\n~ memory comprising:\na semiconductor substrate;\nan array of cell units, said cell units arranged in rows and\ncolumns on said substrate, said array being divided into\na plurality of memory blocks, with each memory block\nbeing defined by at least a given one of said rows of\nsaid cell units, each of said cell units including a\npredetermined number of series connected memory\ntransistors and each of said memory transistors having\na floating gate and control gate;\na plurality of word lines arranged such that said control\ngates of memory transistors in a given row are con-\nnected to a same word line and said control gates of the\nmemory transistors in a given column are connected to\ndifferent word lines; and\na control circuit for floating word lines of unselected\nmemory blocks and applying an erase potential to said\nsubstrate so that data in memory transistors of said\nunselected memory blocks is prevented from being\nerased by capacitive coupling of a predetermined quan-\ntity of said erase potential to said word lines of said\nunselected memory blocks.\n. An electrically erasable and programmable rend-only\nmemory as recited in claim 5, wherein said control circuit\napplies a low potential to word lines of a selected memory\nblock thereof in order to erase data of memory transistors of\nsaid selected memory block.\n. An electrically erasable and programmable read-only\nmemory as recited in claim 6, wherein said erase potential\nis a high potential and said low potential is a ground\npotential.\n. An electrically erasable and programmable read-only\nmemory comprising:\na semiconductor substrate;\na multiplicity of memory transistors arranged in rows and\ncolumns, each memory transistor including a floating\ngate and a control gate;\n\nCase 9:02-cv-00058-JH\n\nDocument I\n,546,341\n\nFHed 03/05/2002\n\nPage 84 of 101\na plurality of word lines each connected to said control\ngates of respective ones of said memory transistors in\na corresponding row;\na control circuit, responsive to an address in a data erase\nmode, for floating word lines unselected by said ~\naddress, and for applying an erase voltage to said\nsubstrate so that erasure of data in memory transistors\nassociated with said unselected word lines is prevented\nby capacitive coupling of a predetermined amount of\nsaid erase voltage to said unselected word lines. 10\n. An electrically erasable and programmable read-only\nmemory comprising:\na semiconductor substrate;\na multiplicity of memory transistors arranged in rows and\ncolumns on said substrate to define a plurality of cell\nunits each of which includes a predetermined number\nof series-connected memory transistors, each of said\nmemory transistors having a floating gate and a control\ngate;\na plurality of memory blocks being defined by respective\nrows of said cell units;\na plurality of word lines each connected to the control\ngates of the respective ones of the memory transistors\nin a corresponding row; and\na control circuit for floating word lines of memory blocks\nnot required to be erased and applying an erase poten-\ntial to said substrate, thereby capacitively coupling a\npredetermined amount of said erase potential to said\nfloated word lines to prevent erasure of data in said\nmemory transistors connected to said floated word\nlines.\n\n* * * * *\n\n[54] AUTO-PROGRAM CIRCUiT IN A\nNONVOLATILE SEMICONDUCTOR\nMEMORY DEVICE\n\n[75] Inventors: Jin-Ki Kim; Hyung-Kyu Lim;\nSung-Soo Lee, all of Seoul, Rep. of\nKorea\n\n[73] Assignee: Samsung Electronics Co., Ltd.,\nSuwon, Rep. of Korea\n\n[21] AppL No.: 526~422\n\n[22] Filed: Sep. 11, 1995\n\n[30] Foreign Application Priority Data\n\n\n[51] hit. CL6 ~_......... GUC 7/00; G11C 16/04\n[52] U.S. Cl. ~ 365/185.22; 365/185.2;\n/189.07; 365/189.09\n[58] Field of Search ...~............ 365/189.01, 185.01,\n/182, 218\n\n(56] References Cited\n\nTanaka Ct al. ......_. .... 365/185\n\nEndoh et al ......._ 371t21.5\nHarasietal. ............................ 365t218\n\nKato Ct al. ~ 365/189.01\nHarari ......... .......... 365/185\n\nSawadaetal ~ 365/185\nPrimary Euzininer-Viet Q. Nguyen\nAuome~ Agenz or Finn-Cushman Darby & Cushman, IP\nGroup of Pillsbury Madison & Sutro LLP\n[57] ABSTRACT\nAn auto-program voltage generator in a nonvolatile semi-\nconductor memory having a plurality of floating gate type\nmemory cells, program circuit for programming selected\nmemory cells, and program verification circuit for verifying\nwhether or not the selected memory cells are successfully\nprogrammed comprises a high voltage generator for gener-\nating a program voltage, a trimming circuit for detecting the\nlevel of the program voltage to inorease sequentially the\nprogram voltage within a predetermined voltage range every\ntime the selected memory cells are not successfully\nprogrammed, a comparing circuit for comparing the\ndetected voltage level with a reference voltage and then\ngenerating a comparing signal, and a high voltage genera-\ntion control circuit for activating the high voltage generator\nin response to the comparing signaL\nClaims, 10 Drawing Sheets\n\nCase 9:02-cv-00058-~jH\n\nUnited States Patent [19]\nKim et al,\n\nDocum~~F,.j~i~\nUSOO5& 9A\n[11] Patent Number: 5,642,309\n[45] Date of Patent: Jun. 24, 1997\n,379,256\n,386,422\n,396,468\n,428,569\n,434,825\n,450,341\n/1995\n/1995\n/1995\n/1995\n/1995\n/1995\n\nSep. 9, 1994 [KR]\nJan. 24, 1995 [KR]\n\nRep. of Korea .................. 22769/1994\n\nRep. of Korea ..........~. 1144/1995\n\nU.S. PATENT DOCUMENTS\n,291,446 3/1994 Van Buskirk et al. .~...... 365/189.09\n\nEXHIBIT\n\n\nLb\n\n- Case 9:02-cv-00058-JH Document I\n\nU.S. Patent J~. 24, i~\n\nFHed O3./O5/2OO~ Page 86 of I 01\n\nSheet 1 of 10 5,642,309\n\nFIG. I\n\nCase 9:02-cv-00058-JH Document I FUed 03/05/2QQ2 Page 87 of 101\n\nU.S. Patent\n\nJun. 24, 1997\n\nSheet 2 of 10\n,642,309\n\nI\n\nFIG. 2\nCK\n 90\n\nFIG. 4\n\nCase 9:02-cv-00058-JH Document I\n\nFHed 03/05/2002\n\nPage 88 of 101\n\nU.S. Patent\nJun. 24, 1997\n\nSheet 3 of 10\n,642,309\n\nAA\nCO\n\nN\n~.\n-j\n\n+\n\nCY)\n\nH\n\n\n\nCase 9:02-cv-00058~H Document I\n\nFHed 03./05/2002 Page 89 of 101\n\nU.S. Patent\n\n\nSapgm\nPDS\nPCout\n\nJun. 24, 1997\n\n\nLPi\nNO\nLP2\nNi\nLP3\nN2\nLP4\nN3\nLP5\nN4\nLP6\nN5\nLP7\nN6\n\nSheet 4 of 10\n\n\nRST\n,642,309\nPGM\n\nFIG. 5\n\nPCout\n\nFIG. 6\n\nC)\nDi\nCD\nN)\nC~)\nC\n\ncn\ncc\nI\n\nC\nC~)\nC\nS\nCD\n\n\nm\nCD\na\np\nci\ncn\nN)\n\n\n\nfsi Di\n`9 (0\nCD\n\n\n`Lo\no\n~0\n-a\n\nSapgm\n\nPGM\nPGMs\n~sp\nLPi\nLP2\nLP3\nLP4\nTRMp,.\nTRMP2\nTRMpa\nTRMP4\n\n\nVpgrn\nPDS\n\nFIG. 7\n\nTIME\n\nbJ\n\n\n<Eo\n~C\\J\n>\n~\n\nU\n-J\n>-\na-\n\n-J\n\nct~\na-\nC'4\n)\n\n\nc\\1\n)\n\nU.S. Patent\n\nCase 9:02-cv-00058~JH Document I\n\nJun. 24, 1997\n\nSheet 6 of 10\n\nFHed 03/05/2002 Page 91 of 101\n,642,309\nN\n\n(.0\n\nIt)\n~-)\n)\n\nN\n\n(0\n\nIt)\n\n>\n\nCase 9:02-cv-00058~H Document I\n\nU.S. Patent Jun. 24,1997\n\nFHed 03./05/2002 Page 92 of 101\n\nSheet 7 of 10 5,642,309\n\n\n* . .\n\n\n* . .\n\n\n* S *\n\n\nS S S\n\nFIG. 9\n\nNUm\n\nS S *\n\nS ~ S\n\nBLm\n\nCase 9:02-cv-00058~JH Document I\n\nU.S. Patent Jun. 24, 1997\n\nFHed 03./05/2002 Page 93 of 101\n\nSheet 8 of 10 5,642,309\n/\n\nFIG. 10\n\nCase 9:02-cv-00058~JH Document I FHed 03./05/20fl2 Page 94 of 101\n\nUS. Patent Jun. 24, 1997 Sheet 9 of 10 5,642,309\n\n\nPGM\nPGMs\n~sp\n\nLPi\nLP2\nLP~\nLP4\nTRMpj\n\nTIME\n\nFIG. 11\n\nCase 9:02-cv-00058~JH Document I\n\nU.S. Patent Jun. 24,1997\n\n\nVOLT\n\n\nFHed 03./05/2002 Page 95 of 101\n\nSheet 10 of 10 5,642,309\n\n\n ~ I\n ----;, I\n\n::::::::~::~`~ 1\n ----w__ I I\nI\nI I\n--~ I I\nI I ~ I\nI Ii II\nI It I\nI I I\n-- -. .-~.-.\n\nI\n\n\n~\nI\nI\n\n~\nI\n~\n\n\n~\n\n\n\n---.\n\n.---\n\n.- .- . j-.. -~ --\n-.,-- --I.- -\n\n.-\n\nVpgmmax\n\n\nVpassmax\n\n\nPROGRAM LOOP(CYCLE)\n\nVcc\n~~192O\n\n\nFIG. 12\n\nCase 9:02-cv-00058~JH Document I\n,642,309\n\nFHed 03./05/2002\n\nPage 96 of 101\nAUTO-PROGRAM CIRCUiT IN A\nNONVOLATILE SEMICONDUCTOR\nMEMORY DEVICE\n\n\nBACKGROUND OF THE INVENTION\n. FIeld of the Invention\nThe present invention relates to a nonvolatile semicon-\nductor memory device, and more particularly to an auto-\nprogram circuit in the nonvolatile semiconductor memoiy\ndevice.\n. Desoription of the Related Arts\nA memory cell array with NAND structured cells has a\nplurality of NAND cell units arranged in a matrix with\ncolumns and rows. FIG. 9 is an equivalent circuit diagram\nshowing a part of the memory cell array with conventional\nNAND structured cells. Referring to the figure, each of the\nNAND cell units NU1 to NUm has a first selection transistor\nwith its drain connected to the corresponding bit line\nand a second selection transistor 121 with its source con-\nnected to a common source line CSL The drain-source\nchannels of memory cell transistors Ml to M8 (hereinafter\nreferred to as \"memory cells\") are serially connected\nbetween a source of the first selection transistor 120 and a\ndrain of the second selection transistor 121. The gates of the\nfirst selection transistors 120, the control gates of the\nmemory cells Ml to M8 and the gates of the second\nselection transistors 121 are connected to a first selection\nline SL1, word lines WL1 to WLS and a second selection\nline SL2, respectively. The first and second selection tran-\nsistors 120 and 121 and the memory cells Ml to MS are\nformed in the P type well formed on the main surface of a\nsemiconductor substrate. The source-drain common region\nbetween the source of the first selection transistor 120 and\nthe drain of the memory ccli Ml, the source-drain common\nregions of the memory cells Ml to M8, and the drain-source\ncommon region between the drain of the second selection\ntransistor 121 and the source of the memory cell MS are\nformed in the P type weli. A floating gate made of polyslli-\ncon is formed on each channel of the memory cells Ml to\nMS through a tunnel oxide layez and a floating gate made of\npolysilicon or of metal silicide with high melting point is\nformed thereon through an intermediate insulating layec\nThe drain regions of the first selection transistors 120\nformed in the P type well are respectively connected to the\ncorresponding bit lines made of metal silicide with high\nmelting point or metal through openings, the source regions\nof the second selection transistors 121 formed in the P type\nwell are connected to the common source line CSL made of\nthe metal silicide with high melting point or metaL The erase\noperation for the memory cells is performed before\nprogramming, i.e., writing data.\nThe erase operation for the memory cells is performed by\napplying erase voltage of about 20 V to the P type well\nregion and reference voltage, i.e., ground voltage to the\nword lines WL1 to WLS. With the electrons stored in the\nfloating gates being emitted to the P type well region through\nthe tunnel oxide layer, the memory cells are changed to\nenhancement mode transistors. It can be assumed that the ~\nerased memory cells store the data \"1\".\nThe programming operation for the memory cells con-\nnectedto the selected word line, i.e., the writing operation of\nthe data \"0\" is performed by applying program voltage of\nabout 18 V to the selected word line and the reference\nvoltage, i.e., the ground voltage Vss to the sources and\ndrains of the memory cells in which the data \"0\"iS written.\nThen, the floating gates of the memory cells to be pro-\ngrammed accumulate the electrons thorough the tunnel\noxide layers, and these memory cells are changed to the\ndepletion mode transistors.\nAfter programming, the program verification operation is\nperformed to verify whether or not the selected memory\ncells arc successfully programmed to have a predetermined\nconstant threshold voltage value. These erase, program and\nprogram verification techniques are disdosed in the Korean\nPatent Publication No. 94-18870 published Aug. 19, 1994\nand assigned to the present inventor.\nAs the capacitance of the EEPROM has become highly\nintegrated, the size of the memory cell, such as the width and\nthickness of the gate oxide layer and the width and length of\nthe channel region, has been reduced. However, variance of\nthe manufacturing process can not secure the uniformity of\nthe width and thickness of the gate oxide layer, intermediate\ninsulating layer and channel region. This makes the thresh-\nold voltage values of the programmed memory cells\nunequal. If at least one of the programmed memory cells\ndoes not reach a desired threshold voltage, error data is read\nout. In order to solve such a problem, a program verification\ndevice has been proposed for verifying whether or not the\nselected memory cells are successfully programmed. For\nexample, such a program verification technique Is disclosed\nin the aforementioned Korean Patent Publication No.\n-18870. However, as the reprogram operation is per-\nformed after the program verification operation with a\nprogram voltage of constant level, the threshold voltages of\nthe programmed memory cells are still unequal. The van-\nance of the circumstance conditions such as a power supply\nvoltage or an operating temperature may deteriorate the\nreliability of the EEPROM.\nSUMMARY OF THE INVENTION\n~ It is therefore an object of the present invention to provide\na nonvolatile semiconductor memory capable of maintain-\ning a uniform threshold voltage of the memory cells to be\nprogrammed regardless of the variance of the operating\ntemperature and power supply voltage.\nit is another object of the present invention to provide the\nnonvolatile semiconductor memory capable of enhancing\nthe reliability thereof regardless of the variance of the\nprocess.\nTo achieve the above objects of the present invention, an\nauto-program voltage generator of the nonvolatile semicon-\nductor memory having a plurality of floating gate type\nmemory cells, a program circuit for programming the\nselected memory cells, and a program verification circuit for\nverifying whether or not the selected memory cells are\nsuccessfully programmed, comprises a high voltage genera-\ntor for generating a program voltage, a trimming circuit for\ndetecting the level of the program voltage so as to sequen-\ntially increase the program voltage within a predetermined\nvoltage range every time the selected memory cells are not\nsuccessfully programmed, a comparing circuit for compar-\ning the detected voltage level with a reference voltage and\nthen generating a comparing signal, and a high voltage\ngeneration control circuit for activating the high voltage\ngenerator in response to the comparing signal.\nBRIEF DESCRIPTION OF THE DRAWINGS\n\nIn the detailed description of the preferred embodiment of\nthe present invention presented below, reference is made to\nthe accompanying drawings, in which:\nFIG. 1 is a diagram illustrating a program voltage gen-\nerator according to a preferred embodiment of the present\ninvention;\n\nCase 9:02-cv-00058-JH Document I\n,642,309\n\nFHed 03./05/2002\n\nPage 97 of 101\nFIG. 2 is a diagram illustrating a trimming signal gen-\nerator according to the preferred embodiment of the present\ninvention;\nFIG. 3A is a diagram illustrating a binary counter accord-\ning to the preferred embodiment of the present invention;\nFIG. 3B is a diagram illustrating each stage in the binary\ncounter of FIG. 3A;\nFIG. 4 is illustrates a clock signal generator for generating\na clock signal for driving the binary counter of FIG. 3A;\nFIG. 5 is a diagram illustrating a control signal generator\naccording to the preferred embodiment of the present inven-\ntion;\nFIG. 6 is a diagram illustrating a loop counter according\nto the preferred embodiment of the present invention;\nFIG. ~ is a liming diagram showing the operations of each\npart of the circuits related to the program voltage generator\naccording to the preferred embodiment of the present inven-\ntion;\nFIG. 8 is a diagram showing the relation between the\nprogram loop and the program voltage according to the\npreferred embodiment of the present invention;\nFIG. 9 is an equivalent circuit diagram showing a part of\nthe memory cell array with conventional NAN]) structured\nmemory cells;\nFIG. 10 is a schematic circuit diagram showing a pass\nvoltage generator according to the preferred embodiment of\nthe present invention;\nFIG. U isa timing diagram showing the operation of each\npart of the circuits related to the pass voltage generator\naccording to the preferred embodiment of the present inven-\ntion; and\nFIG. 12 is a diagram showing the relation between the\nprogram loop and the program voltage and pass voltage\naccording to the preferred embodiment of the present inven-\ntion.\nDEFAJLED DESCR1F11ON OF THE\nPREFER1~ED EMBODIMENT\nN-channel transistors of depletion mode (hereinafter\nreferred to as \"1) type transistors\") having a threshold\nvoltage of -1.8 V, N-channel MOS transistors of enhance-\nment mode (hereinafter referred to as `~ type transistors\")\nhaving the threshold voltage of 0.7 V, and P-channel MOS\ntransistors (hereinafter referred to as `P type transistors\")\nhaving the threshold voltage of -0.9 V are employed in the\npresent invention.\nFIG. 1 illustrates a program voltage generator 200. In the\nfigure, a high voltage generator 10 functions to generate a\nprogram voltage Vpgm in response to a Charge pumping\nsignal 4~pp and its complementary signal 4>pp outputted from\na high voltage generation control circuit 20. The high\nvoltage generator 10 is a well-known circuit for generating\nthe program voltage Vpgm higher than the power supply\nvoltage Vcc by utilizing a charge pumping method. The high\nvoltage generator 10 comprises an N type transistor 17 for\nproviding an initial voltage Vcc-Vth to a node 1, N type\ntransistors 11 to 16 having their own Channels serially\nconnected between the node 1 and an output node 2, and\nMOS capacitors 3 to 8 respectively connected to the gates of\nthe N type transistors 11 to 16. The gates of the N type\ntransistors 11 to 16 are respectively connected to their\ndrains, and the drain-source common nodes of odd MOS\ncapacitors 3,5, and 7 and the drain-source common nodes of\neven MOS capacitors 4,6, and S are connected to the charge\npumping signal $pp and its complementary signal ~pp,\nrespectively.\nThe channels of the D type transistors 18 and 19 are\nserially connected between the output node 2 of the high\nvoltage generator 10 and the power supply voltage Vcc, and\nthe gates thereof are respectively connected to a program\n~ control signal I\ufffdand the power supply voltage Vcc. At the\ncompletion of the program operation, the D type transistors\nand 19 function to discharge the program voltage Vpgni\nto the power supply voltage Vcc.\nA trimming circuit 30 for sequentially increasing the\n~ program voltage Vpgni during the program operation is\nconnected to the output node 2. Between the ground voltage\nVss and the output node 2 is connected the trimming circuit\nin which the channel of an N type transistor 31 and the\nresistors R1 to R10, R,, and Rm are serially connected one\nanother and the gate of the N type transistor 31 is connected\nto the progra~n control signal ~ through an inverter 32. A\nconnection node 37 between the resistors R,, and R10 IS\nconnected to a connection node 38 between the resistor R1\nand the drain of the N type transistor 31 through the channel\nof an N type transIstor 33. The connection nodes between the\nresistors R10 to R1 are respectively connected to the con-\nnection node 38 through the channels of the transistors 34\nand 35. The gates of the transistors 33 to 35 are respectively\nconnected to the trimming signals TRM~ to TRMp~. The\ntransistors 33 to 35 are bypass means for bypassing the\nresistors R1 to R10, sequentially.\nAcomparing circuit 40 functions to compare the reference\nvoltage Vpref with the voltage Vss of the connection node\nbetween the resistors Rm and R,,. In the comparing circuit\n~o 40, the channel of a iransistor 41 is connected between the\nground voltage Vss and a common node 46, and the gate\nthereof is connected to the program control signal PGM\nthrough an investor 47. A first branch in which the Channels\nof the P type transistor 44 and N type transistor 42 are\n~ serially connected and a second brandi in which the chan-\nnels of the P type transistor 45 and N type transistor 43 are\nserially connected are connected in parallel between the\npower supply voltage Vcc and the common node 46. The\ngates of the P type transistors 44 and 45 are commonly\n~ connected each other and are also connected to a connection\nnode 48 between the P type transistor 45 and the N type\ntransistor 43. The reference voltage Vpref, i.e., about L67 V\nIs applied to the gate of the N type transistor 43. The gate of\nthe N type transistor 42 Is connected to the common node 36.\n~ The connection node 49 between the P type transistor 44 and\nthe N type transistor 42 serves as an output terminal of the\ncomparing circuit 40. The comparing circuit 40 outputs the\nlogic \"low\" state if the voltage V36>the reference voltage\nVpref, and outputs the logic \"high\" state if V~<Vprd.\n~o The high voltage generation control circuit 20 is con-\nnected between the comparing circuit 40 and the high\nvoltage generator 10 and functions to control the program\nvoltage Vpgm to maintain a predetermined constant voltage\nleveL The high voltage generation control circuit 20 corn-\nss prises a NAND gate 22 having one input connected to the\nconnection node 49 and the other connected to the program\ncontrol signal POM through an inverter 21. The first inputs of\nthe NAN]) gates 24 and 25 receive the output of the NAN])\ngate 22 through an invorter 23, and the second inputs thereof\n~o respectively receive the clock pulses ~p and ~p from a ring\noscillator (not shown). At this time, the clock pulses ~p and\n~p have the frequency of about 8 MHz. The NAN]) gates 24\nand 25 output the charge pumping signals ~pp and ~pp\nthrough inverters 26 and 27.\nes If V~>Vpref, the high voltage generation control circuit\nis inactivated, and if V~<Vpref, it becomes activated.\nThus, if the program voltage Vpgrn increases, the voltage\n\nPage 98 of 101\n\nS\n\n\nv-~('\ufffdRi+R2\ufffd.+R10+R,,+R,,\n\n\nv~vprq~('+ km\n- R2+...+RlO+R,+Rm ).\n\n\nI _________\n~\n\nAs can be seen from the above equations, when the\ntransistors 35 to 33 are sequentially turned on, the program\nvoltage on the output node 2 are sequentially increased.\nAccordingly, by sequentially peiforining the program and\nprogram verification operations with increasing the program\nvoltage sequentially within a predetermined voltage range,\ni.e., from 15 V to 19.5 V, the memory cells having constant\nthreshold voltages regardless of various Changes such as the\nChange of the process and the change of the circumstance\nconditions can be implemented.\nFIG. 2 is a trimming signal generator 300 for generating\ntrimming signals which sequentially increase the program\nvoltage Vpgm with sequentially turning on the transistors 35\nto 33 in FIG. 1 The trimming signal generator 300 has a\nplurality of NOR gates 51 toSS which receive the combi-\nnations of the output signals LP1 to LP4 of a binary counter\nand their complementary signals L~to ii. The output of the\nNOR gate 55 is coupled to one input of a NOR gate 56 in\na flip-flop. The output of the NOR gate 56 is applied to the\nNOR gates si toSS through an inverter 58, and also to one\ninput of a NOR gate 57. The other input of the NOR gate 57\nin the flip-flop is coupled to the program control signal\n~, and the output thereof is connected to the trimming\nsignal TRM,,~0 and also to the other input of the NOR gate\n. During the program operation, the flip-flop composed of\nthe NOR gates 56 and 57 latches the trixnnilng signal\nIP~MP~O to the logic \"high\" state if the NOR gate 55 is\nselected, i.e., the NOR gate 55 outputs the logic \"high\" state.\nThe investor 58 provides the output of the NOR gate 56 as\na feedback signaL Thus, the NOR gates 56 and 57 and the\ninvestor 58 are latch means for latching the trimming signals\nTRMJ.~ to TRM~O to the logic \"low\" state. Therefore, if the\nselected memory cell is not successfully programmed even\nafter the completion of the tenth program verification\noperation, the program operations thereafter maintain the\nincreased maximum program voltage Vpgmmax level, i.e.,\n.5 V according to the preferred embodiment of the present\ninvention. As the maximum program voltage Vpgmmax is\nselected as the value capable of preventing the junction\n\nF~ed 03./05/2002\nbreakdown and the break down of the gate oxide layer of the\nmemory cell, it should be noted that the present invention is\nnot limited to the maxiniuin program voltage level of 19.5\nV. In addition, the present invention employs 10 trimming\nsignals, however, it is not limited thereto, either. However,\nit is desired that the program voltage Av to be increased\nevery program operation should be below 1 V, preferably\nbelow 0.5 V.\nFIG. 3A shows the binary counter and FIG. 3B a sche-\nmatic circuit diagram of each stage in the binary counter of\nFIG. 3A.\nReferring to FIG. 3B, the channels of N type transistors 65\nto 6$ are serially connected between an output terminal oi+1\n). and its complementary output terminal ~i+1, the gates of the\ntransistors 66 and 67 are commonly connected to a coniple-\nmentary clock input terminal ~i, and the gates of the\ntransistors 65 and 68 to the clock input terminal ci. An\ninverter 64 is connected between the output terminal oi+1\nand its complementary output terminal ~i+1, a second input\n(2) ~ of a NAN]) gate 61 is coupled to2 connection node between\nthe transistors 65 and 66, and the output thereof to a\nconnection node between the transistors 66 and 67 through\nan inverter 63. A second input of the NAN]) gate 62 is\ncoupled to a connection node between the transistors 67 and\n~ 68, and the output thereof to the complementary output\n(3) terminal ~i+l. Thus, if the reset signal of logic \"low\" state\nis applied to a reset terminal ~, the output terminal oi+3\nbecomes the logic \"low\" state and its complementary output\nterminal oi+1 becomes the logic \"high\" state. In addition,\n~ every time the input of the input terminal o~ goes from the\nlogic \"high\" state to the logic \"low\" state, the output state of\nthe output terminal oH-i is changed.\nThe binary counter 400 of FIG. 3A is composed of 7\nstages serially connected one another. The reset terminal\ni is coupled to the reset signal ~, and the clock input\nterminal 01 and its complementary dock input terminal 61 at\nthe first stage are respectively connected to the dock signal\nCK and its coniplementaiy clock signal ~. The 7 stages 71\nto 77 output complementary counting signals ii~ to 1i, and\n~ the4 stages7lto74outputthecounting signalsLP1 toLP4.\nEvery time the clock signal CK goes to the logic \"low\" state,\nthe counting signals l2~ to LP4 are counted up and the\ncomplementary counting signals 12~ to tP~ are conntcd\ndown.\nFIG. 4 is a circuit diagram showing a dock signal\ngenerator for generating the clock signal to be provided to\nthe binary counter 400 of FIG. 3A. In the figure, a program\nand verification signal i\ufffds generated from a timer (not\nshown) in response to the program control signal ~61~1. The\nclock signal generator comprises a short pulse generator 80\ncomposed of inverters 81 to 83 and a NAND gate 84,\ninverters 85 toSS, and NOR gates 89 and 90. The NOR gates\nand 90 are comprised in a flip-flop. The short pulse\ngenerator 80 generates the short pulse of logic \"low\" state\nss when the program and verification signal 1i61j goes to the\nlogic \"high\" state.\nFIG. S is a schematic circuit diagram of a control signal\ngenerator for generating the reset signal ~ and the program\ncontrol signal ~ The control signal generator of FIG. S\ngenerates the reset signal xsr through a short pulse generator\nand inverters 92 and 93 in response to an auto-program\nflag signal Sapgm outputted from a command register (not\nshown). The auto-program flag signal Sapgni is applied to a\nfirst input of a NOR gate 95 through an invertor 94, a\nprogram detection signal PDS to a second input thereof and\na loop counting signal PCout to a third input thereof. The\nNOR gate 95 outputs the program control signal ~\n\nCase 9:02-cv-00058~.tH Document I\n,64.2,309\n\nV~ also increases. Therefore, the high voltage generation\ncontrol circuit 20 is inactivated and thus the high voltage\ngenerator 10 reduces the program voltage Vpgin. On the\nother hand, if the program voltage Vpgsn is too low, the high\nvoltage generator 10 increases the program voltage Vpgm.\nHence, the program voltage Vpgni maintains a constant\nvoltage level by the control of the high voltage generation\ncontrol circuit 20,\nAt the turn off state of the transistors 33 to 35, the initial\nprogram voltage Vpginin on the output node 2 can be\nrepresented as follows:\n\nAt the turn on state of the transistor 35, the program\nvoltage V~1,,,1 on the output node 2 can be represented as\nfollows:\n\nAt the turn on state of the transistor 34, the program\nvoltage ~ on the output node 2 can be represented as\nfollows:\n\nPage 99 of 101\nthrough an inverter 96. The program detection signal PDS is\ngenerated according to the program verification operation. If\nall the selected memory cells have been successfully\nprogrammed, the program detection signal PDS becomes the\nlogic \"high\" state. On the contrary, if at least one of the ~\nselected memory cells has not been successfully\nprogrammed, the program detection signal PDS becomes the\nlogic \"low\" state. Such a program verification technique is\ndisclosed in the aforementioned Korean Patent Publication\nNo. 94-18870.\nFIG. 6 shows a loop counting circuit 500 for generating\nthe loop counting signal PCout. The loop counting circuit\nis a logic circuit composed of NAND gates 101 to HO\nand a NOR gate 111. The complementary counting signals\nLi~ to i~ are applied from the binary counter 400 to the\nNAND gates 101 to 107, respectively. The terminals NO to\nN6 are connected to the ground voltage Vss or to the power\nsupply voltage Vcc according to the loop counting fre-\nquency. As the loop counting frequency is set to 20 accord-\ning to the preferred embodiment of the present invention, the\nterminals N2 and NS are connected to the power supply\nvoltage Vcc, and the reni~ining terminals NO, Ni, N3, N4,\nand N6 are connected to the ground voltage Vss.\nThe auto-program circuit according to the preferred\nembodiment will be described with reference to the timing\ndiagram of FIG. 7.\nAs shown in FIG. 7, the auto-program operation starts in\nresponse to the transition of the auto-program flag signal\nSapgm. from the logic \"low\" state to the logic \"high\" state.\nAs the program detection signal PDS and the loop counting\nsignal PCout are in the logic \"low\" state at the beginning of\nthe auto-program operation, the control signal generator\ngenerates the program control signal PGM of logic \"low\"\nstate in response to the transition of the auto-program flag\nsignal Sapgm from the logic `low\" state In the logic \"high\"\nstate. In addition, in response to the auto-program flag signal\nSapgm which goes to the logic \"high\" state, the short pulse\ngenerator 91 generates the short pulse of logic \"low\" state\nand thereby the binary counter 400 of FIG. 3A is reseL As\nshown in FIG. 7, the timer (not shown) generates the\nprogram and verification signal POMs in response to the\ntransition of the program control signal from the logic\n\"high\" state to the logic \"low\" state. The program and\nverification signal ~ is the dock pulse which has the\nlogic \"low\" state of 30 psec and the logic \"high\" state of 10\npsec when the program control signal ~6~i is in the logic\nlow\". The duration when the program control signal\nremains the logic \"low\" state is for the program operation,\nand the duration when the program control signal remains\nthe logic \"high\" state is for the program verification opera-\ntion.\nAt time t1 of FIG. 7, in response to the transition of the\nprogram control signal i6~i from the logic \"high\" state to the\nlogic \"low\" state, the program voltage generator 200 of FIG.\nis enabled. That is, the transistor 41 is turned on, thus\nactivating the comparing circuit 40, and the transistor 31 is\nturned on, thus activating the trimming circuit 30. At the\nbeginning of the operation, as Vpref>Vre, the comparing\ncircuit 40 outputs the logic \"high\" state. Hence, the inverter\noutputs the logic \"high\" state and thereby the high\nvoltage generation control circuit 20 generates the charge\npumping signal ~pp and its complementary signal 4~pp.\nThus, the high voltage generator 10 generates the gradually\nincreasing high voltage by the signals 4pp and ~pp. The\nprogram voltage Vpgm increases until the voltage V35 at the\nconnection node 36 reaches the reference voltage Vpref.\nConsequentially, the program voltage Vpgm maintains the\n\nF~ed 03/05/200~\ninitial program voltage Vpgmin shown in the above-\ndescribed equation (1). The technique for programming the\nselected memory cells with the program voltage Vpgm is\ndisclosed in the Korean Patent Publication No. 94-18870.\nAt thue t2, the program and verification signal ~ goes\nto the logic \"high\" state, and the program verification\noperation for the programmed memray cells is performed\nduring the time between t1 and t2. In response to the program\nand verification signal ~ which goes to the logic \"high\"\nif) state at time t2, the short pulse generator 80 of FIG. 4\ngenerates the short pulse and the inverter 86 generates the\nshort pulse signal ~sp of logic \"low\" state. The clock signal\nCK is generated as a similar signal to the short pulse signal\nisp. Then, the binary counter 400 of FIG. 3A makes the\ncounting signal LP1 the logic \"high\" state as shown in FIG.\n. Thereby, the NOR gate 51 of FIG. 2 generates the\ntrimming signalTRM~1 of logic \"high\" state.Thus,withthe\nturn on state of the transistor 35 of FIG. 1, the resistor R1 is\nbypassed, and the voltage V36 at the connection node 36\nbecomes smaller than the reference voltage Vpref. As a\nresult, the high voltage generation control circuit 20 is\nactivated and the high voltage generator 10 generates the\nincreased program voltage Vpgmi as shown in the above\nequation (2).\nIf the selected memory cells are not successfully pro-\ngrammed during the program verification operation between\nthe time t2 and t3, i.e., the duration of 10 psec, reprogram\noperation is automatically perfonned with the increased\nprogram voltage Vpgmi during the time between t3 and t4.\nAt time t4, if the program and verification signal ~\ngoes to the logic \"high\" state, the short pulse generator 80\nof FIG. 4 generates the short pulse of logic \"low\" state, and\nthe inverter 86 outputs the short pulse ~sp of logic \"low\"\nstate as shown in FIG. 7. The dock signal CK becomes the\nshort pulse of logic low\" state, and the counting signals 1P1\nand 122 of the binary counter 400 become the logic low\"\nand logic \"high\" states, respectively. Thus, the NOR gate 52\nof FIG. 2 generates the trimming signal TRM~ which goes\nto the logic \"high\" state. In response to the trimming signal\nTRM~ of logic \"high\" state, the resistors R1 and R2 of FIG.\nare bypassed, and the voltage V~ at the connection node\nbecomes smaller than the reference voltage Vpref.\nHence, the high voltage generation control circuit 20 is\n~ activated, and thereby the high voltage generator 10 gener-\nates the program voltage ~ as shown in the above\nequation (3).\nIf the selected memory cells are not successfully pro-\ngrammed regardless of the reprogram operation, the pro-\n~ grain operation is performed again during the time between\nt, and t~. In the same way, with the sequential increase of the\nprogram voltage, the program and program verification\noperations are automatically performed until all the selected\nmemory cells are successfully programmed.\nThe timing diagram of FIG. 7 shows the case that the\nselected memory cells are successfully programmed at the\nfilth program operation. After the completion of the fifth\nprogram operation, the program detection signal PDS indi-\ncating that the selected memory cells have been successfully\nprogrammed goes to the logic \"high\" state at the program\nverification operation between the time t10 and t11. Thereby,\nthe control signal generator of FIG. S makes the program\ncontrol signal ~ logic \"high\" state, and the circuits related\nto the program like a ring counter (not shown) are inacti-\nvated. After about 2.5 psec after the program control signal\nPOM goes to the logic \"high\" state, the auto-program flag\nsignal Sapgtn becomes the logic low\" state. It is possible to\n\nCase 9:02-cv-00058~J-H Document I\n,642,309\n\nCase 9~02-cv~00058-jH Document I\n,642,309\n\nF~ed 03/05/2002 Fage 100 of 101\ndetect how many program loops are occurred duri~g~the 2.5\npsec with the complementary counting signals LP1 to LP7\noutputted from the binary counter 400.\nFIG. $ is a diagram showing the relation between the\nprogram 1oop and the program voltage according to the\npreferred embodiment of the present invention. Referring to\nFIG. 8, the program operations for the selected memory cells\ncan be performed as much as 20 times. The program voltage\nVpgm sequentially increases from 15 V to 19.5 V by 0.5 V\nuntil the tenth program operation. During the eleventh to\ntwentieth program operations, the program voltage Vpgni\nmaintains the maximum constant voltage level Vpgmmax of\n.5 V by the latch operation of the flip-flop composed of the\nNOR gates 56 and 57. If the selected memory cells are not\nsuccessfully programmed after the twentieth program\noperation, the loop counting circuit 500 of FIG. 6 generates\nthe loop counting signal PCout which goes to the logic\n\"high\" state, and thereby the control signal generator of FIG.\ngenerates the program control signal ~i which goes to\nthe logic \"high\" state, thus stopping the generation of the\nprogram voltage Vpgni.\nAs described above, the auto-program voltage generator\ngenerates the program voltage which increases sequentially\nwithin a predetermined voltage range depending on the\nprogram loop according to the present invention. The pro-\ngram voltage is supplied to the selected word line. However,\nthe variance of the threshold voltage and the stress of the\nmemory cells which should not be programmed among the\nmemory cells connected to the selected word line should be\nprevented.\nIn the program operation of the conventional technique,\nthe pass voltage Vpass, i.e., a constant voltage of 10 V is\napplied to the unselected word lines. For enample, assuming\nthat the word line WL2 is selected, the maximum program\nvoltage Vpgmniax increased according to the program ioop,\ni.e., 19.5 V is applied to the selected word line WLZ the\nmemory cell M2 within the NAND cell unit NU2 should be\nprogrammed as data \"0\", and the memory celiM2 within the\nNAN!) cell unit NU1 should be kept as the erase state, i.e.,\ndata \"1\", the power supply voltage Vcc of 5 V is applied to\nthe first selection line SL1, the constant pass voltage Vpass\nof 10 V to the unselected word lines WL1 and WL3 to WLS,\nand the ground voltage Vss to the second selection line SL2\nduring the program operation. At the same time, the ground\nvoltage Vss Is applied to the bit line BL2 related to the\nmemory cell M2 which is to be programmed as the data \"0\"\nwithin the NAND cell unit NU2, and the power supply\nvoltage Vcc of 5 V is applied to the bit line BL1 related to\nthe memory cell M2 which should be in the erase state, i.e.,\nthe data \"1\" within the NAND cell unit NU1. Then, the first\nselection transistor 120 within the NANI) cell unit NU2 is\nturned on and thereby the memory cell M2 within the\nNAND cell unit NU2 is programmed as the data \"0\".\nHowever, as the power supply voltage Vcc of 5 V is applied\nto the bit line BL1 connected to the NAND cell unit NU1\nand to the gate of the first selection transistor 120 within the\nNAND cell unit NU1 and the pass voltage Vpass of 10 V is\napplied to the control gate of the memory cell Ml within the\nNAN!) cell unit NU1, the source of the first selection\ntransistor 120 is charged with the pass voltage Vpass, and\nthereby the first selection transistor 120 is turned off. Thus,\nthe source and drain of the memory cell M2 within the\nNAND cell unit NU1 are charged with the pass voltage\nVpass (=10 V), and the increased program voltage of 19.5 V\nis abruptly applied to the control gate of the memory cell\nM2. Therefore, the memory cell M2 within the NAND cell\nunit NTJ1 receives the voltage stress of 9.5 V and thereby the\nthin tunnel oxide layer due to the variance of the manufac-\nturing process or the intermediate insulating layer is broken\ndown. Meanwhile, the threshold voltage of the memory cell\nM2 within the NANI) cell unit NIJ2 is varied. Therefore, the\n~ application of the constant pass voltage Vpass to the unse-\nlected word lines deteriorates the reliability of the\nEEPROM. To solve such a problem, the preferred embodi-\nment of the present invention will be described with refer-\nence to FIGS. 10 to 12.\nFIG. 10 shows a pass voltage generator for generating the\npass voltage to be applied to the unselected word lines.\nReferring to the figure, the pass voltage generator 600 has\nthe same structure as the program voltage generator 200 of\nFIG. 1 except that the values of the resistors R1' to R10', R~'\nand Rm' in the pass voltage generator 600 are different from\nthose of the resistors R1 to R10, R~ and Rm in the program\nvoltage generator 200, and that the pass voltage Vpass\ninstead of the program voltage Vpgm is outputted from the\noutput node 2. The control signal generators shown in FIGS.\nto 6 are also employed to control the pass voltage\ngenerator 600. The pass voltage generator 600 generates the\npass voltage Vpass which increases sequentially from the\ninitial pass voltage Vpassin of 8 V to the maximum pass\nvoltage Vpassmnax of 12.5 V according to the program 1oop.\nThe generation of the increasing pass voltage Vpass can be\nimplemented by using the proper values of the resistors R1'\nto R1~, R,, and R,,,. The operations of the pass voltage\ngenerator 600 are identical to those of the program voltage\ngenerator 200 except the value of the pass voltage Vpass,\nand such will not be described. The control signal generators\nshown in FIGS. 2 to 6 are employed in the pass voltage\ngenerator 600 of FIG. 10, and such will not be described,\neither.\nFIG. U is a timing diagram for describing the operations\n~ of the pass voltage generator of FIG. 10. FIG. 11 is identical\nto FIG. 7 except that the pass voltage Vpass is generated\ninstead of the program voltage Vpgm.\nFIG. 12 is a diagram showing the relation between the\nprogram voltage Vpgni and the pass voltage Vpass accord-\ningtotheprogramloop.Ascanbesecninthcflgure,the\nvoltage difference between the program voltage Vpgm and\nthe pass voltage Vpass maintains 5 V until the tenth program\noperation. Such a voltage difference can be set properly\naccording to the structure or properties of the memory cells\n~ to prevent the insulation break down or the variance of the\nthreshold voltage of the memory cells which should not be\nprogrammed.\nAs described above, since the auto-program voltage gen-\nerator and the pass voltage generator according to the\nso present invention generate the program voltage and pass\nvoltage which increase sequentially within a predetermined\nvoltage range, the reliability of the chip can be enhanced\nwithout the break down of the insulating layer or the\nvariance of the threshold voltage of the niemosy cells which\nss should not be programmed. In addition, it is possible to\nachieve a uniform threshold voltages, and to enhance the\nperformance of the chip regardless of the change in process\nand the circumstance condition.\nWhat is claimed is:\nso 1. Au auto-program voltage generator in a nonvolatile\nsemiconductor memory having a plurality of floating gate\ntype memory cells, program means for programming\nselected memory cells, and program verification means for\nverifying whether or not said selected memory cells are\nsuccessfully programmed, said auto-program voltage gen-\nerator comprising:\n\na high voltage generator for generating a program voltage;\n\nCase 9:02-cv-00058-jH\n\nDocument I\n,642,309\n\nF~ed 03/05/2002 Fage 101 of 101\na trimming circuit for causing said program voltage to\nincrease sequentially within a predetermined voltage\nrange every time one of said selected memory cells is\nnot successfully programmed, said trimming circuit\nsequentially outputting a detected voltage level signal\ncorresponding to said sequentially increasing program\nvoltage;\na comparing circuit for comparing said detected voltage\nlevel signal with a reference voltage and then generat-\ning a comparing signal when said detected voltage level\nsignal is less than said reference voltage; and\na high voltage generation control circuit for activating\nsaid high voltage generator in response to said com-\nparing signal.\n. The auto-program voltage generator according to claim ~\n, wherein said trimming circuit comprises a plurality of\nresistors serially connected between a program voltage\ngeneration terminal of said high voltage generator and a\nsecond reference voltage, and a plurality of transistors for\nrespectively bypassing each of said plurality of resistors in\norder to increase sequentially said program voltage.\n. The auto-program voltage generator according to claim\n, wherein said trimming circuit comprises a plurality of\nbypass means to increase sequentially said program voltage~\n. The auto-program voltage generator according to claim ~\n, further comprising a trimming signal generator connected\nto said plurality of bypass means, for generating trimming\nsignals that are respectively supplied to each of said bypass\nmeans and allow for increasing sequentially said program\nvoltage. 30\n. The auto-program voltage generator according to claim\n, wherein said trimming signal generator comprises latch\nmeans for generating a constant voltage for each of said\ntrimming signals after said program voltage has been\nsequentially increased.\n. The auto-program voltage generator according to claim\n, further comprising a binary counter connected to said\ntrimming signal generator, for sequentially activating said\nplurality of bypass means.\n. The auto-program voltage generator according to claim 40\n, further comprising a binary counter connected to said\ntrimming signal generator, for sequentially activating said\nplurality of bypass means.\n. The auto-program voltage generator according to claim\n, further comprising a ioop counting circuit for stopping the\ngeneration of said program voltage in response to counting\nsignals outputted from said binary counter.\n. An auto-program voltage generating method of a non-\nvolatile semiconductor memory which performs sequen-\ntiaily program and program verification operations, said\nsequential program using a program voltage that is sequen-\ntially increased within a predetermined voltage range and\nthen maintained at a constant voltage level when program-\nruing a selected memory cell that is not successfully pro-\ngrammed.\n. The method according to daim 9, wherein said\nconstant voltage level is set to prevent junction break down\nand break down of a gate oxide layer of memosy cells.\n. The method according to claim 9, wherein said\npredetermined voltage range is from about 15 V to 19.5 V.\n. The auto-program voltage generator according to\nclaim!, where said sequentially increasing program voltage\nincreases in increments that are each less than 1 volt.\n. The auto-program voltage generator according to\nclaim!, wherein said sequentially increasing program volt-\nage increases in increments that are each less than 0.5 volts.\n. The method according to claim 9, where said sequen-\ntially increasing program voltage increases in increments\nthat are each less than 1 volt.\n. The method according to claim 9, wherein said\nsequentially increasing program voltage increases in incre..\nments that are each less than 0.5 volts.\n. The method according to claim 11, where said sequen-\ntinily increasing program voltage increases in increments\nthat are each less than 1 volt.\n. The method according to claim U, wherein said\nsequentially increasing program voltage increases in incre-\nments that are each less than 0.5 volts.\n. The auto-program voltage generator according to\nclaim 1, wherein said memory cells arc programmed in one\nof two states and said sequentially increasing program\nvoltage is used to change each selected memory cell from\none of said states to another of said states.\n. The method according to claim 9, wherein said\nmemory cells are programmed in one of two states and said\nsequentially increasing program voltage is used to change\neach selected memory cell from one of said states to another\nof said states.\n* * * * *\n\n"
        }
      ], 
      "filed_on": "2002-03-05T00:00:00", 
      "id": 13922, 
      "nice_text": "Original Complaint filed. Cause: 35:271 Patent Infringement (djh) (Entered: 03/05/2002)", 
      "number": 1, 
      "tags": [
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          "@id": "http://lexmachina.com/vocab/tags#14", 
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    }, 
    {
      "@id": "http://lexmachina.com/data/docket-entry/13927", 
      "documents": [
        {
          "@id": "http://lexmachina.com/data/documents/4000106540", 
          "id": 4000106540, 
          "text": "UNITED STATES DISTRICT COURT\nEASTERN DISTRICT OF TEXAS\n\n\nREPORT ON THE FILING OR DETERMINATION\nOF AN ACTION\nREGARDING A PATENT OR TRADEMARK\n\n\nCommissioner of Patents and Trademarks\nWashington, DC 20231\n\n\nIn compliance with 35 U.S.C. Sec. 290 and/or 15 U.S.C. Sec. 1116\nyou are hereby advised of the following:\n\nthat a court action has been filed on a patent or trademark.\nA copy of the complaint is attached.\n\nI that a final decision or judgment has been rendered in a case\nconcerning a patent or a trademark. A copy of the order or\njudgment is attached.\n\nDAVID J. MALAND\n\nCLERK OF COURT\n\n\nby Debbie Haschke, Deputy\n\n"
        }
      ], 
      "filed_on": "2002-03-05T00:00:00", 
      "id": 13927, 
      "nice_text": "Form mailed to Commissioner of Patents and Trademarks. (djh) (Entered: 03/05/2002)", 
      "number": 3, 
      "tags": []
    }, 
    {
      "@id": "http://lexmachina.com/data/docket-entry/13929", 
      "documents": [], 
      "filed_on": "2002-03-20T00:00:00", 
      "id": 13929, 
      "nice_text": "Motion by Sandisk Corporation for Ariana M. Chung-Han to appear pro hac vice (djh) Modified on 03/22/2002 (Entered: 03/22/2002)", 
      "number": 5, 
      "tags": []
    }, 
    {
      "@id": "http://lexmachina.com/data/docket-entry/13931", 
      "documents": [], 
      "filed_on": "2002-03-20T00:00:00", 
      "id": 13931, 
      "nice_text": "Motion by Sandisk Corporation for kimberly P Zapata to appear pro hac vice (djh) (Entered: 03/22/2002)", 
      "number": 7, 
      "tags": []
    }, 
    {
      "@id": "http://lexmachina.com/data/docket-entry/13932", 
      "documents": [
        {
          "@id": "http://lexmachina.com/data/documents/4000117134", 
          "id": 4000117134, 
          "text": "UNITED STATES DISTRICT COURT\nEASTERN DISTRICT OF TEXAS \ufffd~ ~T 23 P~~i 1;~ 5J\nLUFKIN DIVISION\n\n\nS~ISUNG ELECTRONICS CO., LTD., \ufffd\nPlaintiff \ufffd CIVIL ACTION NO. 9:02CV58\n\ufffd Judge Hannah\n\ufffd\n\ufffd\nSANDISK CORPORATION, \ufffd\n\nDefendant.\n\n\nMOTION TO APPEAR PRO HAC VICE\n\nTO THE HONORABLE JUDGE OF SAID COURT:\n\nCOMES NOW James C. Yoon, and makes this motion to appear pro hac vice in the above\nentitledlnumbered cause. In support thereof, Movant would respectfully show the Court as follows:\n. Movant's address is Wilson Sonsini Goodrich & Rosati, 650 Page Mill Road,\nPalo Alto, CA 94304.\n. Movant is representing Defendant SanDisk Corporation.\n. Movant was admitted to practice by the State of California in 1995.\n. Movant is in good standing and is otherwise eligible to practice before this Court.\n. Movant is not currently suspended or disbarred in any other Court.\n. There are no pending grievances or other criminal matters pending against Movant.\n. Movant has been admitted to practice in the following courts: Supreme Court, State\nof California; Unites States District Court, Northern District of California; United States Court of\nAppeals, Ninth Circuit; United States Court of Appeals for the Federal Circuit; United States District\nCourt, District of Arizona; United States Patent and Trademark Office.\n. Movant has read and will comply with the Local Rules of the Eastern District of\nTexas, including Rule AT-3, the \"Standards of Practice to be Observed by Attorneys.\"\n\n\nC:\\NrPo~CML\\21 I 1535_I.DOC (1507)\n\nWHEREFORE, PREMISES CONSIDERED, Movant prays that the Court grant this Motion to\nAppear Pro Hac Vice in this matter.\n\n\nRespectfully Submitted,\n\n\nJames Cyoon/\n\nWILSON SONSINI GOODRICH & ROSATI\nPage Mill Road\nPalo Alto, CA 94304\n.493.9300\n\n\nCertificate of Service\n\n\nThis motion was forwarded to all attorneys of record on ____________________\n,\n\nC:\\NrPortbI\\PALIB I \\.KDP\\2 111535_I .DOC (1496)\n\nUNITED STATES DISTRICT COURT\nEASTERN DISTRICT OF TEXAS\nLUFKIN DIVISION\n\n\nSAMSUNG ELECTRONICS CO., LTD., \ufffd\nPlaintiff, \ufffd CIVIL ACTION NO. 9:02CV58\n\ufffd Judge Hannah\n\ufffd\n\ufffd\nSANDISK CORPORATION, \ufffd\n\nDefendant. \ufffd\n\n\nORDER PRO HAC VICE\n\nCame on this day to be considered the Motion for Admission Pro Hac Vice of James C. Yoon\n\nfor purposes of the above-entitled and numbered cause. After careful consideration, the Court is of\n\nthe opinion that the motion is good, and should, in all things, be granted with the following order\n\nissuing.\n\nIt is therefore\n\nOR1~ERED that the movant's Motion for Admission Pro Hac Vice is hereby GRANTED. It\n\nis further\n\nORDERED that James C. Yoon is hereby ADMITTED to the United States District Court\n\nfor the Eastern District of Texas for purposes of the above-entitled and numbered action.\n\n\nIT IS SO ORDERED.\n\n\nSIGNED this day of , ___________\n\n\nUNITED STATES DISTRICT JUDGE\n\n\nC;\\NrPortbl\\PALIBI\\CML\\21 12146_I .DOC (757)\n\n"
        }
      ], 
      "filed_on": "2002-03-20T00:00:00", 
      "id": 13932, 
      "nice_text": "Motion by Sandisk Corporation for James Yoon to appear pro hac vice (djh) (Entered: 03/22/2002)", 
      "number": 8, 
      "tags": []
    }, 
    {
      "@id": "http://lexmachina.com/data/docket-entry/2002343033", 
      "documents": [], 
      "filed_on": "2002-03-20T00:00:00", 
      "id": 2002343033, 
      "nice_text": "PHV Filing Fee paid by atty Wilson Sonsini Goodrich & Rosati; PHV FILING FEE $ 75.00 RECEIPT # 617644 for Juli M. Holloway, Ariana M. Chung-Han, and Karen L Jennings (djh) (Entered: 03/22/2002)", 
      "number": null, 
      "tags": []
    }, 
    {
      "@id": "http://lexmachina.com/data/docket-entry/13936", 
      "documents": [], 
      "filed_on": "2002-03-27T00:00:00", 
      "id": 13936, 
      "nice_text": "ORDER granting [9-1] motion for James Otteson to appear pro hac vice (signed by Judge John Hannah Jr) cc: attys, JH 3/27/02 (djh) (Entered: 03/27/2002)", 
      "number": 10, 
      "tags": [
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          "@id": "http://lexmachina.com/vocab/tags#2", 
          "id": 2, 
          "name": "Order", 
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    {
      "@id": "http://lexmachina.com/data/docket-entry/13937", 
      "documents": [], 
      "filed_on": "2002-03-27T00:00:00", 
      "id": 13937, 
      "nice_text": "ORDER granting [8-1] motion for James Yoon to appear pro hac vice (signed by Judge John Hannah Jr) cc; attys, JH 3/27/02 (djh) (Entered: 03/27/2002)", 
      "number": 11, 
      "tags": [
        {
          "@id": "http://lexmachina.com/vocab/tags#2", 
          "id": 2, 
          "name": "Order", 
          "visible": 1
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    }, 
    {
      "@id": "http://lexmachina.com/data/docket-entry/13938", 
      "documents": [], 
      "filed_on": "2002-03-27T00:00:00", 
      "id": 13938, 
      "nice_text": "ORDER granting [7-1] motion for kimberly P Zapata to appear pro hac vice (signed by Judge John Hannah Jr) cc; attys, JH 3/27/02 (djh) (Entered: 03/27/2002)", 
      "number": 12, 
      "tags": [
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          "@id": "http://lexmachina.com/vocab/tags#2", 
          "id": 2, 
          "name": "Order", 
          "visible": 1
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    }, 
    {
      "@id": "http://lexmachina.com/data/docket-entry/13939", 
      "documents": [], 
      "filed_on": "2002-03-27T00:00:00", 
      "id": 13939, 
      "nice_text": "ORDER granting [6-1] motion for Julie M. Holloway to appear pro hac vice (signed by Judge John Hannah Jr) cc; attys, JH 3/27/02 (djh) (Entered: 03/27/2002)", 
      "number": 13, 
      "tags": [
        {
          "@id": "http://lexmachina.com/vocab/tags#2", 
          "id": 2, 
          "name": "Order", 
          "visible": 1
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    {
      "@id": "http://lexmachina.com/data/docket-entry/13940", 
      "documents": [], 
      "filed_on": "2002-03-27T00:00:00", 
      "id": 13940, 
      "nice_text": "ORDER granting [5-1] motion for Ariana M. Chung-Han to appear pro hac vice (signed by Judge John Hannah Jr) cc: attys, JH 3/27/02 (djh) (Entered: 03/27/2002)", 
      "number": 14, 
      "tags": [
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          "@id": "http://lexmachina.com/vocab/tags#2", 
          "id": 2, 
          "name": "Order", 
          "visible": 1
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    }, 
    {
      "@id": "http://lexmachina.com/data/docket-entry/13941", 
      "documents": [], 
      "filed_on": "2002-03-27T00:00:00", 
      "id": 13941, 
      "nice_text": "ORDER granting [4-1] motion for Karen L. Jennings to appear pro hac vice (signed by Judge John Hannah Jr) cc: attys, JH 3/27/02 (djh) (Entered: 03/27/2002)", 
      "number": 15, 
      "tags": [
        {
          "@id": "http://lexmachina.com/vocab/tags#2", 
          "id": 2, 
          "name": "Order", 
          "visible": 1
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    {
      "@id": "http://lexmachina.com/data/docket-entry/13943", 
      "documents": [
        {
          "@id": "http://lexmachina.com/data/documents/4000010158", 
          "id": 4000010158, 
          "text": "WAR 2 8 2002\n\ni~- INTEE UNITED STATES DISTRICT COURT\ntL~ ~FOR THE EASTERN DISTRICT OF TEXA~ ~`~1'~ MALAND,CLERK\nLUFKIN DIVISION `)~PJTy_____________\n\n\nSAMSUNG ELECTRONICS, CO., LTD., \ufffd CIVIL ACTION NO. 9:02cv58\n\ufffd Judge Hannah\nPlaintiff, \ufffd\n\ufffd\nv. \ufffd\n\ufffd\nSANDISK CORPORATION, \ufffd\n\ufffd\nDefendant. \ufffd\n\ufffd\n\nDEFENDANT SANDISK CORPORATION'S\nANSWER TO COMPLAINT AND COUNTERCLAIMS\n\nDefendant SanDisk Corporation (\"SanDisk\") answers the Complaint of Samsung\n\nElectronics, Co., Ltd. (\"Samsung\") as follows:\n. SanDisk lacks sufficient knowledge or information to form a belief as to the truth\n\nof the averments contained in Paragraph 1.\n. SanDisk admits that it is organized under the laws of Delaware and that its\n\nprincipal place of business in Sunnyvale, California. SanDisk denies the remaining averments\n\ncontained in Paragraph 2.\n. In answer to Paragraph 3 of the Complaint, SanDisk states as follows: SanDisk\n\nadmits that this Court has subject matter jurisdiction , but denies that SanDisk infringes\n\nSamsung' s patents.\n. SanDisk denies the averments contained in Paragraph 4 of the Complaint.\n\nDEFENDANT SANDISK CoRFo1~TIoN's 1 C:\\Windows\\TEMP\\21 15376_I .DOC\nANSWER To COMPLAINT AND\nCOUNTERCLAIMS\n. SanDisk lacks sufficient knowledge or information to form a belief as to the truth\n\nof the averments contained in Paragraph 5.\n. In answer to Paragraph 6 of the Complaint, SanDisk states as follows: SanDisk\n\nadmits that flash memory products can be removable memory cards that can be found in digital\n\ncameras, digital music players, digital camcorders, handheld PCs, eBooks, and newer cellular\n\nphone technology, as well as other emerging products but denies the remaining averments of\n\nParagraph 6.\n. In answer to Paragraph 7 of the Complaint, SanDisk states as follows: SanDisk\n\nadmits that it manufactures and supplies flash memory cards in consumer, OEM, and industrial\n\nmarkets. SanDisk also admits that one of its products is the CompactFlashTM but denies that the\n\nCompactFlash, or any other product distributed by SanDisk, infringes any Samsung patents.\n. SanDisk admits that it sells memory products through intermediaries, including\n\nwholesalers, distributors, value-added resellers, and retailers. SanDisk admits that the retailers\n\nthat sell its flash memory cards are located throughout the United States and that some of these\n\nretailers may reside in the Eastern District of Texas. SanDisk admits that retailers that sell its\n\nflash memory cards may include Circuit City, K-Mart, Office Depot, Target, Sears, Office Max,\n\nStaples, Eckerd drug stores, and Walgreen. SanDisk denies the remaining averments contained\n\nin paragraph 9.\n. SanDisk admits that it has sold flash memory cards to original equipment\n\nmanufacturers (\"OEMs\"), including Cannon, Hewlett-Packard, Fujitsu, Motorola, Kodak,\n\nPanasonic, and Polaroid. SanDisk admits that it sells flash memory cards to private label\n\npartners that re-brand the SanDisk products under a different trade name. SanDisk lacks\n\nsufficient knowledge or information to form a belief as to the truth of the remaining averments in\n\nparagraph 9.\n\nDEFENDANT SANDISK CoRPoR.~tTioN's 2 C:\\Windows\\TEMP\\21 15376_i .DOC\nANSWER To COMPLAINT\n. In answer to Paragraph 10 of the Complaint, SanDisk states as follows: SanDisk\n\nadmits that it markets, promotes, sells and offers for sale certain types of flash memory products\n\nin Texas. SanDisk admits that it uses distributors and manufacturer representatives to sell its\n\nproducts in Texas. However, SanDisk specifically denies that it has a direct sales office in\n\nTexas, and denies the remaining allegations of paragraph 10.\n. In answer to Paragraph 11 of the Complaint, SanDisk states as follows: SanDisk\n\nadmits that it sells its flash memory products on Amazon.com' s Internet website. SanDisk lacks\n\nsufficient knowledge or information to form a belief as to the truth of the other averments\n\ncontained in Paragraph 11.\n. In answer to Paragraph 12 of the Complaint, SanDisk states as follows: SanDisk\n\nadmits that it markets, promotes, sells, offers for sale, or leases its flash memory products\n\nthroughout the United States, which may include the Lufkin Division. However, SanDisk denies\n\nthat it \"directly\" markets, promotes, sells, offers for sale, or lease its flash memory products in\n\nthe Lufkin Division. SanDisk admits that it employs wholesalers, distributors, value-added\n\nresellers and retailers to market, promote, sell, offer for sale, or lease its flash memory cards.\n\nSanDisk lacks sufficient knowledge or information to form a belief as to the truth of the\n\nremaining averments contained in Paragraph 12.\n. In answer to Paragraph 13 of the Complaint, SanDisk states as follows: SanDisk\n\nadmits that it has sold and is currently selling CompactFlashTM cards and other products\n\nthroughout the United States, which may include the Lufkin Division, but denies that it\n\n\"directly\" sells its products in the Lufkin Division. SanDisk also admits that it employs a variety\n\nof means, including wholesalers, distributors, value-added resellers and retailers, to sell its flash\n\nmemory products. SanDisk lacks sufficient knowledge or information to form a belief as to the\n\ntruth of the remaining averments contained in Paragraph 13.\n\nDEFENDANT SANDISK CORPORATION'S 3 C:\\Windows\\TEMP~2I 15376_I.DOC\nANSWER To COMPLAINT\n\n\nDEFENDANT SANDISK CoRPoRATIoN's 4 C:\\Wmdows\\TEMP\\2 115376_I .DOC\nANSWER To COMPLAINT\n. In answer to Paragraph 14 of the Complaint, SanDisk states as follows: SanDisk\n\nadmits that its flash memory products, including the CompactFlashTM product line have been\n\nsold and are currently being sold throughout the United States, which may include the Lufkin\n\nDivision. SanDisk also admits that it employs a variety of means, including wholesalers,\n\ndistributors, value-added resellers and retailers, to sell its flash memory products. SanDisk\n\nfurther admits that, under certain conditions, retail outlets have the right to return any unsold\n\nSanDisk flash memory product, including the CompactFlashTM product line, directly to SanDisk.\n\nSanDisk lacks sufficient knowledge or information to form a belief as to the truth of the\n\nremaining averments contained in Paragraph 14.\n. In answer to Paragraph 15 of the Complaint, SanDisk states as follows: SanDisk\n\nadmits that its flash memory products, including the CompactFlashTM product line have been\n\nsold and are currently being sold throughout the United States, which may include the Luflun\n\nDivision. SanDisk also admits that it employs a variety of means, including wholesalers,\n\ndistributors, value-added resellers and retailers, to sell its flash memory products. SanDisk\n\nfurther admits that, under certain conditions, retail outlets have the right to return any unsold\n\nSanDisk flash memory product, including the CompactFlashTM product line, directly to SanDisk.\n\nSanDisk lacks sufficient knowledge or information to form a belief as to the truth of the\n\nremaining averments contained in Paragraph 15.\n. In answer to Paragraph 16 of the Complaint, SanDisk states as follows: SanDisk\n\nadmits that its flash memory cards, including the CompactFlashTM product line, have been\n\nincorporated into a variety of OEM products, including Kodak, Polaroid, Nikon and Hewlett-\n\nPackard digital cameras. SanDisk lacks sufficient knowledge or information to form a belief as\n\nto the truth of the remaining averments contained in Paragraph 16.\n\n\nDEFENDANT SANDISK CoRPoRATION's 4 C:\\Windows\\TEMP\\21 15376_i .DOC\nANSWER To COMPLAINT\n. In answer to Paragraph 17 of the Complaint, SanDisk states as follows: SanDisk\n\nadmits its flash memory cards, including the CompactFlashTM product line, have been promoted,\n\nadvertised and offered for sale throughout the United States, may include the Lufkin Division.\n\nSanDisk lacks sufficient knowledge or information to form a belief as to the truth of the\n\nremaining averments contained in Paragraph 17.\n. SanDisk denies the averments contained in Paragraph 18.\n. In answer to Paragraph 19 of the Complaint, SanDisk states as follows: SanDisk\n\nadmits that it has offered cash rebates on some flash memory products, including the\n\nCompactFlashTM product line to consumers throughout the United States. SanDisk also admits\n\nthat during these promotional events, consumers can sometimes obtain rebate information and\n\ncertificates for SanDisk's products from various retail outlets located throughout the United\n\nStates. SanDisk further admits that rebate information can be found on SanDisk's Internet\n\nwebsite. SanDisk lacks sufficient knowledge or information to form a belief as to the truth of the\n\nremaining averments contained in Paragraph 19.\n. In answer to Paragraph 20 of the Complaint, SanDisk states as follows: SanDisk\n\nadmits that it has offered and continues to offer warranties on its flash memory products,\n\nincluding the CompactFlash~ product line. SanDisk also admits consumers can obtain warranty\n\ninformation and warranty registration material for SanDisk products at retail outlets in the United\n\nStates that sell SanDisk flash memory products, including the CompactFlash~ product line.\n\nSanDisk also admits that warranty information and warranty registration materials for SanDisk\n\nflash memory products are included within the package of each retail SanDisk product sold.\n\nSanDisk also admits that warranty information and warranty registration materials for SanDisk\n\nflash memory products can be obtained from its Internet website. SanDisk lacks sufficient\n\n\nDEFENDANT SANDISK CORPORATION'S 5 C:\\Windows\\TEMP\\2 I 15376_I .DOC\nANSWER To COMPLAINT\n\nknowledge or information to form a belief as to the truth of the remaining averments contained in\n\nParagraph 20.\n. SanDisk denies that it offers a \"five-year warranty on all of its flash memory\n\nproducts, including products in the CompactFlashTM product line.\" SanDisk admits that the\n\nwarranty for some of its products includes, in part, the language recited in Paragraph 21 of the\n\nComplaint.\n. SanDisk admits that the packaging containing its flash memory cards includes\n\nwarranty registration materials. SanDisk admits that the warranty registration material includes a\n\nreference to the website URL for a SanDisk website. SanDisk denies the remaining averments in\n\nparagraph 22.\n. In answer to Paragraph 23 of the Complaint, SanDisk states as follows: SanDisk\n\nadmits that any consumer for its products who has access to the Internet has access to the\n\nwebsite, which is located at http://www.sandisk.comlmain.htm. SanDisk lacks sufficient\n\nknowledge or information to form a belief as to the truth of the remaining averments contained in\n\nParagraph 23.\n. In answer to Paragraph 24 of the Complaint, SanDisk states as follows: SanDisk\n\nadmits that it has a website, run by a distributor, that allows any consumer with access to the\n\nInternet to shop for, order and purchase a full range of SanDisk's flash memory products.\n\nSanDisk also admits that no consumer with access to the Internet, including those located in the\n\nLulkin Division, is prevented from accessing its website. SanDisk lacks sufficient knowledge or\n\ninformation to form a belief as to the truth of the remaining averments contained in\n\nParagraph 24.\n. SanDisk admits the averment of contained in paragraph 25.\n\n\nDEFENDANT SANDISK CORPORATION'S 6 C:\\Windows\\TEMPV21 I 5376_i.DOC\nANSWER To COMPLAINT\n. SanDisk admits that its website, run by a distributor, provides warranty\n\ninformation related to SanDisk flash memory cards. SanDisk admits that no consumer with\n\naccess to the Internet, including those located in the Lufkin Division, is prevented from accessing\n\nwarranty information. SanDisk denies the remaining averments contained in paragraph 26.\n. SanDisk admits that its website, run by a distributor, allows consumers to register\n\nwarranty information for its flash memory cards. SanDisk admits that no consumer with access\n\nto the Internet, including those located in the Lufkin Division, is prevented from accessing this\n\ninformation. SanDisk admits that registration of a flash memory card for warranty purposes\n\nrequires an individual to complete several fields of inquiry and provide information to SanDisk,\n\nincluding the consumer's residence and where the SanDisk product was purchased.\n. In answer to Paragraph 28 of the Complaint, SanDisk states as follows: SanDisk\n\nadmits that its website provides any consumer with access to the Internet, cash rebates and cash\n\nrebate information, and does not restrict access to any consumers, including those residing in the\n\nLufkin Division. SanDisk also admits that the content of the URLs set forth in Paragraph 28\n\ninclude the information set forth in Paragraph 28. SanDisk lacks sufficient knowledge or\n\ninformation to form a belief as to the truth of the remaining averments contained in\n\nParagraph 28.\n. In answer to Paragraph 29 of the Complaint, SanDisk states as follows: SanDisk\n\nadmits that the website referred to in Paragraph 29 provides any consumer with access to the\n\nInternet the information necessary to contact technical support staff via e-mail or telephone with\n\nquestions regarding customer service or technical support relating to all of its products. SanDisk\n\nalso admits that no consumer with access to the Internet, including those located in the Lulkin\n\nDivision is prevented from accessing this information.\n\n\nDEFENDANT SANDISK CORPORATION'S 7 C:\\Windows\\TEMP\\21 15376 1.DOC\nANSWER To COMPLAINT\n. In answer to Paragraph 30 of the Complaint, SanDisk states as follows: SanDisk\n\nadmits that the website located at the referenced URL includes the cited language and does not\n\nrestrict any consumer with access to the Internet from accessing the website. SanDisk lacks\n\nsufficient knowledge or information to form a belief as to the truth of the remaining averments\n\ncontained in Paragraph 30.\n. In answer to Paragraph 31 of the Complaint, SanDisk states as follows: SanDisk\n\ndenies that consumers can download software upgrades for its flash memory cards. SanDisk\n\nadmits that it does not restrict or otherwise prevent individuals residing in the Lufkin Division\n\nfrom accessing the website run by SanDisk's distributor. The remaining portion of paragraph 31\n\nis ambiguous and, therefore, SanDisk does not possess sufficient information to respond to the\n\nremaining averments of the paragraph.\n. In answer to Paragraph 32 of the Complaint, SanDisk states as follows: SanDisk\n\nadmits that it allows any consumer with access to the Internet the option to enroll in the quarterly\n\nproduct e-mail list distributed by SanDisk. SanDisk also admits that no consumer with access to\n\nInternet is prevented from receiving this list if he or she chooses to.\n. Except as specifically admitted in the preceding paragraphs, SanDisk denies the\n\nallegations of Paragraph 33 of the Complaint.\n. SanDisk realleges and incorporates herein its responses to Paragraphs 1-33 of the\n\nComplaint.\n. In answer to Paragraph 35 of the Complaint, SanDisk states as follows: SanDisk\n\nadmits that Exhibit A to the Complaint appears to be a copy of United States Patent No.\n,473,563 (\"the `563 patent\") issued December 5, 1995 and assigned to Samsung Electronics,\n\nInc. SanDisk lacks sufficient knowledge or information to form a belief as to the truth of the\n\nremaining averments contained in Paragraph 35.\n\nDEFENDANT SANDISK CoRPoRATIoN's 8 C:\\Windows\\TEMP\\2i 15376 I.DOC\nANSWER To COMPLAINT\n. SanDisk denies the averments contained in Paragraph 36 of the Complaint.\n. SanDisk denies the averments contained in Paragraph 37 of the Complaint.\n. SanDisk denies the averments contained in Paragraph 38 of the Complaint.\n. SanDisk denies the averments contained in Paragraph 39 of the Complaint.\n. SanDisk realleges and incorporates herein its responses to Paragraphs 1-39 of the\n\nComplaint.\n. In answer to Paragraph 41 of the Complaint, SanDisk states as follows: SanDisk\n\nadmits that Exhibit B to the Complaint appears to be a copy of United States Patent No.\n,514,889 (\"the `889 patent\") issued May 7, 1996 and assigned to Samsung Electronics, Inc.\n\nSanDisk lacks sufficient knowledge or information to form a belief as to the truth of the\n\nremaining averments contained in Paragraph 41.\n. SanDisk denies the averments contained in Paragraph 42 of the Complaint.\n. SanDisk denies the averments contained in Paragraph 43 of the Complaint.\n. SanDisk denies the averments contained in Paragraph 44 of the Complaint.\n. SanDisk denies the averments contained in Paragraph 45 of the Complaint.\n. SanDisk realleges and incorporates herein its responses to Paragraphs 1-45 of the\n\nComplaint.\n. In answer to Paragraph 47 of the Complaint, SanDisk states as follows: SanDisk\n\nadmits that Exhibit C to the Complaint appears to be a copy of United States Patent No.\n,546,341 (\"the `341 patent\") issued August 13, 1996 and assigned to Samsung Electronics, Inc.\n\nSanDisk lacks sufficient knowledge or information to form a belief as to the truth of the\n\nremaining averments contained in Paragraph 47.\n. SanDisk denies the averments contained in Paragraph 48 of the Complaint.\n. SanDisk denies the averments contained in Paragraph 49 of the Complaint.\n\nDEFENDANT SANDISK CORPORATION'S 9 C:\\Windows\\TEMP\\21 15376_1.DOC\nANSWER To COMPLAINT\n. SanDisk denies the averments contained in Paragraph 50 of the Complaint.\n. SanDisk denies the averments contained in Paragraph 51 of the Complaint.\n. SanDisk realleges and incorporates herein its responses to Paragraphs 1-51 of the\n\nComplaint.\n. In answer to Paragraph 53 of the Complaint, SanDisk states as follows: SanDisk\n\nadmits that Exhibit D to the Complaint appears to be a copy of United States Patent No.\n,642,309 (\"the `309 patent\") issued June 24, 1997 and assigned to Samsung Electronics, Inc.\n\nSanDisk lacks sufficient knowledge or information to form a belief as to the truth of the\n\nremaining averments contained in Paragraph 53.\n. SanDisk denies the averments contained in Paragraph 54 of the Complaint.\n. SanDisk denies the averments contained in Paragraph 55 of the Complaint.\n. SanDisk denies the averments contained in Paragraph 56 of the Complaint.\n. SanDisk denies the averments contained in Paragraph 57 of the Complaint.\n. SanDisk realleges and incorporates herein its responses to Paragraphs 1-57 of the\n\nComplaint.\n. SanDisk denies the averments contained in Paragraph 59 of the Complaint\n\nAFFIRMATIVE DEFENSES\n\nFIRST AFFIRMATIVE DEFENSE\n. As a first and separate affirmative defense, SanDisk alleges that it has not\n\ninfringed, directly or indirectly, literally or by the doctrine of equivalents, any valid claims of the\n\n`563, the `889, the `341, and the `309 patents.\n\nSECOND AFFIRMATIVE DEFENSE\n. As a second and separate affirmative defense, SanDisk alleges that the `563, the\n\n`889, the `341 and the `309 patents are invalid under 35 U.S.C. \ufffd~ 102, 103 and!or 112.\n\nDEFENDANT SANDISK CORPORATION'S 10 C:\\Windows\\TEMP\\21 15376_I .DOC\nANSWER To COMPLAINT\n\nTHIRD AFFIRMATIVE DEFENSE\n. As a third and separate affirmative defense, SanDisk alleges that Samsung's claim\n\nis barred by the doctrine of estoppel.\n\nFOURTH AFFIRMATIVE DEFENSE\n. As a fourth and separate affirmative defense, SanDisk alleges that Samsung has\n\nwaived the claim it asserts in this Action.\n\nFIFTH AFFIRMATIVE DEFENSE\n. As a fifth and separate affirmative defense, SanDisk alleges that Samsung's\n\nclaims are barred by its unclean hands.\n\nSIXTH AFFIRMATIVE DEFENSE\n. As a sixth and separate affirmative defense, SanDisk alleges that Samsung's\n\nclaims for patent infringement are barred in that SanDisk has license and/or sublicense rights\n\n(whether express or implied) to the `563, the `889, the `341, and the `309 patents.\n\nSEVENTH AFFIRMATIVE DEFENSE\n. As a seventh and separate affirmative defense, SanDisk alleges that Samsung's\n\nclaims for patent infringement are barred by the doctrine of patent exhaustion.\n\nEIGHTH AFFIRMATIVE DEFENSE\n. As an eighth and separate affirmative defense, SanDisk alleges that Samsung has\n\nreleased any claim for infringement of the `563, the `889, the `341, and the `309 patents.\n\nCOUNTERCLAIMS\n\nTHE PARTIES\n. SanDisk is a Delaware corporation with its principal place of business in\n\nSunnyvale, California.\n\n\nDEFENDANT SANDISK CORPORATION'S 11 C:\\WindowsVfEMP\\21 15376_I.DOC\nANSWER To COMPLAINT\n. On information and belief Samsung is a company duly organized under the laws\n\nof South Korea with its principal place of business located at 416 Maetan-3 Dong, Paldal-Gu,\n\nSuwon City, Kyungi-Do, Korea.\n\nJURISDICTION AND VENUE\n. This Court has subject matter jurisdiction over SanDisk's patent counterclaims\n\npursuant to 28 U.S.C. \ufffd 1338(a), because those counterclaims arise under the patent laws of the\n\nUnited States, 35 U.S.C. \ufffd 1 et seq. This Court has jurisdiction over SanDisk's counterclaim for\n\nbreach of contract pursuant to 28 U.S.C. \ufffd 1332, because it is a controversy between SanDisk, a\n\ncitizen of Delaware and California, and Samsung, a citizen of Korea, and the amount in\n\ncontroversy exceeds $75,000.\n. As alleged above in Paragraph 4, SanDisk contends that venue is improper in this\n\nDistrict for Samsung's claims of patent infringement against SanDisk. Accordingly, within the\n\nnext week, SanDisk will file a motion for transfer of venue to the Northern District of California\n\npursuant to 28 U.S.C. \ufffd 1404(a). Nevertheless, and in the event the Court denies SanDisk's\n\nmotion for transfer of venue, SanDisk alleges that venue is proper for SanDisk's counterclaims\n\nbecause they are compulsory counterclaims. In that event, venue is proper in this District for\n\nSanDisk's declaratory judgment patent counterclaims pursuant to 28 U.S.C. \ufffd 1391(b) and\n(b). SanDisk's counterclaim for breach of contract is proper in this District under 28 U.S.C.\n(a)(2), in that a substantial part of the events giving rise to that counterclaim occurred in this\n\nDistrict through Samsung's improper filing of a patent infringement action in this District in\n\nbreach of its contractual obligations to SanDisk.\n\nFIRST COUNTERCLAIM\n. Samsung claims that it is the owner of the `563 patent; that the patent is valid; and\n\nthat SanDisk infringes the patent.\n\nDEFENDANT SANDISK CORPORATION'S 12 C:\\Windows\\TEMP\\21 15376 l.DOC\nANSWER To COMPLAINT\n. SanDisk contends that the `563 patent is not valid and/or is not infringed.\n\nAccordingly, a valid and justiciable controversy has arisen and exists between Samsung and\n\nSanDisk. SanDisk desires a judicial determination and declaration of the respective rights and\n\nduties of the parties herein. Such a determination and declaration is necessary and appropriate at\n\nthis time in order that the parties may ascertain their respective rights and duties.\n\nSECOND COUNTERCLAIM\n. Samsung claims that it is the owner of the `889 patent; that the patent is valid; and\n\nthat SanDisk infringes the patent.\n. SanDisk contends that the `889 patent is not valid and/or is not infringed.\n\nAccordingly, a valid and justiciable controversy has arisen and exists between Samsung and\n\nSanDisk. SanDisk desires a judicial determination and declaration of the respective rights and\n\nduties of the parties herein. Such a determination and declaration is necessary and appropriate at\n\nthis time in order that the parties may ascertain their respective rights and duties.\n\nTHIRD COUNTERCLAIM\n. Samsung claims that it is the owner of the `341 patent; that the patent is valid; and\n\nthat SanDisk infringes the patent.\n. SanDisk contends that the `341 patent is not valid and/or is not infringed.\n\nAccordingly, a valid and justiciable controversy has arisen and exists between Samsung and\n\nSanDisk. SanDisk desires a judicial determination and declaration of the respective rights and\n\nduties of the parties herein. Such a determination and declaration is necessary and appropriate at\n\nthis time in order that the parties may ascertain their respective rights and duties.\n\nFOURTH COUNTERCLAIM\n. Samsung claims that it is the owner of the `309 patent; that the patent is valid; and\n\nthat SanDisk infringes the patent.\n\nDEFENDANT SANDISK CORPORATION'S 13 C:\\Windows\\TEMP\\21 15376_1.DOC\nANSWER To COMPLAINT\n. SanDisk contends that the `309 patent is not valid and/or is not infringed.\n\nAccordingly, a valid and justiciable controversy has arisen and exists between Samsung and\n\nSanDisk. SanDisk desires a judicial determination and declaration of the respective rights and\n\nduties of the parties herein. Such a determination and declaration is necessary and appropriate at\n\nthis time in order that the parties may ascertain their respective rights and duties.\n\nFIFTH COUNTERCLAIM\n. On October 3, 1995, Samsung sued SanDisk in the Northern District of California\n\nasserting that SanDisk's products infringed two Samsung patents, and seeking a declaration of\n\ninvalidity and non-infringement as to five SanDisk patents, including SanDisk's U.S. Patent Nos.\n,172,338 and 5,418,752 (the \"338 patent\" and \"752 patent,\" respectively).\n. In January 1996, SanDisk sued ~amsung in the United States International Trade\n\nCommission (\"ITC\") alleging that Samsung infringed the `338 and `752 patents.\n. The litigation in the Northern District of California was stayed pending resolution\n\nof the ITC litigation.\n. On April 15, 1997, the ITC affirmed an administrative law judge's finding that\n\ncertain Samsung flash memory devices infringed the `338 and `752 patents.\n. Following the ITC ruling in SanDisk's favor, the parties negotiated a Settlement\n\nand Patent Cross License Agreement (the \"Agreement\"). The Agreement resolved both the ITC\n\ncase and the district court case filed by Samsung in the Northern District of California.\n. The Agreement provided SanDisk with a license to manufacture various types of\n\nflash memory products under Samsung's patents.\n. The parties agreed that the Agreement would be governed by the laws of the State\n\nof California, and agreed to jurisdiction in the Northern District of California for any action\n\nbrought pursuant to the Agreement.\n\nDEFENDANT SANDISK CORPORATION'S 14 C:\\Windows\\TEMP\\21 15376 1.DOC\nANSWER To COMPLAINT\n. The Agreement has not been modified, rescinded or revoked by the parties since\n\nits effective date of August 14, 1997.\n. On March 5, 2002, Samsung filed suit against SanDisk in the Eastern District of\n\nTexas, Lufkin Division, alleging that certain nonvolatile semiconductor memory products made,\n\nused, sold, offered for sale, leased or imported by SanDisk infringe four United States patents\n\nassigned to Samsung.\n. The products named in Samsung's Complaint are covered by the Agreement.\n. Accordingly, Samsung's assertion of these patents against SanDisk's licensed\n\nproducts directly implicates the parties' Agreement, which directs that any such dispute must be\n\nlitigated in the Northern District of California.\n. Paragraphs 1-90 are hereby incorporated by reference as if set forth fully herein.\n. The Agreement between SanDisk and Samsung is valid and subsisting.\n. SanDisk has substantially performed all of its duties under the Agreement.\n. Samsung has materially breached the express terms of the Agreement by filing a\n\npatent infringement suit against licensed SanDisk products in the Eastern District of Texas,\n\nLufkin Division in violation of the express terms of the Agreement.\n. SanDisk has been and continues to be harmed by Samsung's breach of the express\n\nterms of the Agreement.\n\n\nWHEREFORE, SanDisk requests that the Court enter judgment in their favor and against\n\nSamsung as follows:\n\n(a) Denying the relief requested by Samsung's Complaint;\n\n\nDEFENDANT SANDISK CORPORATION'S 15 C:\\Windows\\TEMP\\21 15376_I.DOC\nANSWER To COMPLAINT\n\n(b) For a declaration that the `563, the `889, the `341 and the `309 patents are invalid\n\nand not infringed by SanDisk;\n\n(c) For a declaration that SanDisk's rights under the Settlement and Patent Cross\n\nLicense Agreement between SanDisk and Samsung dated August 14, 1997 are valid and\n\nsubsisting;\n\n(d) For a declaration that Samsung has breached the express terms of the Settlement\n\nand Patent Cross License Agreement between SanDisk and Samsung dated August 14, 1997;\n\n(e) A preliminary and permanent injunction enjoining Samsung, its officers, agents,\n\nservants, employees, attorneys and those persons on active concert or participation with any of\n\nfrom any further breach of either the express or implied terms of the Settlement and Patent Cross\n\nLicense Agreement between SanDisk and Samsung dated August 14, 1997;\n\n(f) A dismissal of Samsung's claims based on Samsung's improper selection of\n\nvenue pursuant to the express terms of the Settlement and Patent Cross License Agreement\n\nbetween SanDisk and Samsung dated August 14, 1997;\n\n(g) An award to SanDisk of damages in an amount adequate to compensate SanDisk\n\nfor any and all damages resulting from Samsung's breach of the express and/or implied terms of\n\nthe Settlement and Patent Cross License Agreement between SanDisk and Samsung dated\n\nAugust 14, 1997, and interest on that amount;\n\n(h) An award to SanDisk of its attorney fees and costs; and\n\n\nDEFENDANT SANDISK CORPORATION'S 16 C:\\Windows\\TEMP\\21 15376_l.DOC\nANSWER To COMPLAINT\n\n(i) Such other relief as the Court deems proper.\n\nDated: March 28, 2002\n\n\nOF COUNSEL:\nMichael A. Ladra\nJames C. Ottesen\nJames C. Yoon\nWILSON SONSINT GOODRICH & ROSATI\nProfessional Corporation\nPage Mill Road\nPalo Alto, CA 94304-1050\nTelephone: (650) 493-9300\nFacsimile: (650) 565-5100\n\nDEFENDANT SANIMSK CORPORATION'S\nANSWER To COMPLAINT\n\nC:\\Windows\\TEMP\\21 15376_I .DOC\n\nState Bar\nRAMEY & FLOCK, P.C.\nE. Ferguson St.\nFirst Place\nTyler, TX 75702\nTelephone: (903) 597-3301\nFacsimile: (903) 597-2413\nCERTIFICATE OF SERVICE\n\nI hereby certif~i that on March 28, 2002, copies of the foregoing DEFENDANT\nSANDISK CORPORATION'S ANSWER TO COMPLAINT AND COUNTERCLAIMS\nwere served upon the following parties as indicated:\n\nGeorge E. Chandler, Esq.\nTHE LAW OFFICES OF GEORGE CHANDLER\nE. Frank Poland Professional Building\nPost Office Box 340\nLufkin, Texas 75902\nBus: (936) 632-7778\nFax: (936) 632-1304\n\n\nClayton E. Dark, Jr., Esq.\nTHE LAW OFFICES OF CLAYTON E. DARK JR.\nPost Office Box 2207\nLufkin, Texas 75902\nBus: (936) 637-1733\nFax: (936) 637-2897\n\n\nR. W. (\"Ricky\") Richards, Esq.\nTHE RICHARDS LAW FIRM\nPost Office Box 1309\nJacksonville, Texas 75766\nBus: (903) 586-2544\nFax: (903) 586-6529\n\nVia First Class Mail\nVia Hand Delivery\nVia Overnight Courier\nVia Facsimile\n\n\nVia First Class Mail\nVia Hand Delivery\nVia Overnight Courier\nVia Facsimile\n\n\n( ) Via First Class Mail\n( ) Via Hand Delivery\n(~-) Via Overnight Courier\n( `-~ Via Facsimile\n\nClaude E. Welch, Esq.\nTHE LAW OFFICES OF CLAUDE E. WELCH\nPost Office Box 1574\nLufkin, Texas 75902\nBus: (936) 639-3311\nFax: (936) 639-3049\n\n\nDEFENDANT SANDISK CORPORATION'S\nANSWER To COMPLAINT\n\n( ) Via First Class Mail\n( ) Via Hand Delivery\n(~4 Via Overnight Courier\n( -~J Via Facsimile\n\n( )\n( )\n((4\n(~\n\n\n( )\n( )\n(~1\n~\nC:\\Windows\\TEMP\\2 1153761 .DOC\n\nDavid J. Healey, Esq.\nAnita E. Kadala, Esq.\nWElL, GOTSHAL & MANAGS LLP\nLouisiana, Suite 1600\nHouston, Texas 77002\nBus: (713) 546-5000\nFax: (713) 224-9511\n\nVia First Class Mail\nVia Hand Delivery\nVia Overnight Courier\nVia Facsimile\n\n( )\n( )\n(`1\n\n\nC:\\Windows\\TEMP\\21 15376_I .DOC\n\nDEFENDANT SANDISK CORPORATION'S\nANSWER To COMPLAINT\n"
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      "filed_on": "2002-03-28T00:00:00", 
      "id": 13943, 
      "nice_text": "Counterclaim by Sandisk Corporation against Samsung Electronics (mll) (Entered: 04/01/2002)", 
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          "text": "Case 9:02~cv-00058-JH Document 17 F~ed 03128/2002 Page 1 of 4\n\nFILED\n- k.\n`~c\n\n\np~ MAR 23 2002\nUNITED STATES DISTRICT COURT ~ J.MALJ~DCL~J1K\n`~cj~-~ TEX~)R THE EASTERN DISTRICT OF TEXA~~J~\nLUFKIN DIVISION\n\n\nSAMSLJNG ELECTRONICS, CO., LTD., \ufffd CIVIL ACTION NO. 9:02CV58\n\ufffd Judge Hannah\nPlaintiff, \ufffd\n\ufffd\nv. \ufffd\n\ufffd\nSANDISK CORPORATION, \ufffd\n\ufffd\nDefendant. \ufffd\n\ufffd\n\nDEFENDANT SANDISK CORPORATION'S\nCORPORATE DISCLOSURE STATEMENT\n\nPursuant to Local Rule CV-l0(d), SanDisk Corporation, (\"SanDisk\") files this Corporate\n\nDisclosure Statement and provides this identification of all of its parent corporations and those\n\npublicly held companies that own 10% or more of the party's stock.\n. SanDisk has no parent corporation.\n. There are no publicly held companies that ow 0% or more of SanDisk's stock.\n\nDated: March 28, 2002 ~\n\n\nTrac r wfor\nAttorney-In-C arg for efendant\nState Bar No. 050 000\nRAMEY&FL K,P.C.\nE. Ferguson St.\nFirst Place\nTyler, TX 75702\nTelephone: (903) 597-3301\nFacsimile: (903) 597-2413\n\nDEFENDANT SANDISK C0RP0R&TI0N's 1 C:\\Windows\\TEMP\\2 115456_I .DOC\nCORPORATE DISCLOSURE STATEMENT\n\nCase 9:02~cv-00058-JH Document 17 F~ed 03128/2002 Page 2 of 4\n\n\nOF COUNSEL:\nMichael A. Ladra\nJames C. Ottesen\nJames C. Yoon\nWILSON SONSINT GOODRICH & ROSATI\nProfessional Corporation\nPage Mill Road\nPalo Alto, CA 94304-1050\nTelephone: (650) 493-9300\nFacsimile: (650) 565-5100\n\n\nDEFENDANT SANDISK C0IUORATI0N's 2 C:\\Windows\\TEMP\\21 15456 I.DOC\nANSWER To COMPLAINT\n\nCase 9:02~cv-00058-JH Document 17\n\nF~ed 03128/2002 Page 3 of 4\n\nCERTIFICATE OF SERVICE\n\nI hereby certify that on March 28, 2002, copies of the foregoing DEFENDANT\nSANDISK CORPORATION'S CORPORATE DISCLOSURE STATEMENT were served\nupon the following parties as indicated:\n\nGeorge E. Chandler, Esq.\nTHE LAW OFFICES OF GEORGE CHANDLER\nE. Frank Poland Professional Building\nPost Office Box 340\nLufkin, Texas 75902\nBus: (936) 632-7778\nFax: (936) 632-1304\n\n\nClayton E. Dark, Jr., Esq.\nTHE LAW OFFICES OF CLAYTON E. DARK JR.\nPost Office Box 2207\nLufkin, Texas 75902\nBus: (936) 637-1733\nFax: (936) 637-2897\n\n\nR. W. (\"Ricky\") Richards, Esq.\nTHE RICHARDS LAW FIRM\nPost Office Box 1309\nJacksonville, Texas 75766\nBus: (903) 586-2544\nFax: (903) 586-6529\n\n\nClaude E. Welch, Esq.\nTHE LAW OFFICES OF CLAUDE E. WELCH\nPost Office Box 1574\nLufkin, Texas 75902\nBus: (936) 639-3311\nFax: (936) 639-3049\n\n( ) Via First Class Mail\n( ) Via Hand Delivery\n(i4 Via Overnight Courier\n( \"5 Via Facsimile\n\n\n( ) Via First Class Mail\n( ) Via Hand Delivery\n(~) Via Overnight Courier\n( `~) Via Facsimile\n\n( )\n( )\n\n\n( )\n( )\n(h-.-)\n\nVia First Class Mail\nVia Hand Delivery\nVia Overnight Courier\nVia Facsimile\n\n\nVia First Class Mail\nVia Hand Delivery\nVia Overnight Courier\nVia Facsimile\n\nDEFENDANT SANDISK CoI~poRATIoN's\nANSWER To COMPLAINT\nC:\\Windows\\TEMP\\2 1154561 .DOC\n\nCase 9:02~cv-00058-JH Document 17\n\nF~ed 03128/2002 Page 4 of 4\n\nDavid J. Healey, Esq.\nAnita E. Kadala, Esq.\nWElL, GOTSHAL & MANAGS LLP\nLouisiana, Suite 1600\nHouston, Texas 77002\nBus: (713) 546-5000\nFax: (713) 224-9511\n\n\nDEFENDANT SANDISK CORPORATION'S\nANSWER To COMPLAINT\n\n( ) Via First Class Mail\n( ) Via Hand Delivery\n(~_-) Via Overnight Courier\n( -~J Via Facsimile\n\n\nC:\\Windows\\TEMP\\21 154561 .DOC\n"
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      "filed_on": "2002-03-28T00:00:00", 
      "id": 13944, 
      "nice_text": "Notice of corporate disclosure by Sandisk Corporation (mll) (Entered: 04/01/2002)", 
      "number": 17, 
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      "filed_on": "2002-04-03T00:00:00", 
      "id": 13946, 
      "nice_text": "ORDER granting [18-1] motion for leave to file 1st amended complaint (signed by Judge John Hannah Jr) cc; attys, JH 4/3/02 (djh) (Entered: 04/03/2002)", 
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          "@id": "http://lexmachina.com/data/documents/254", 
          "id": 254, 
          "text": "Case 9:02-cv-0005~JH Document 20 F~ed 04/0312002 Page 1 of 127\n\n\nFILED - CLERK\nU.S. D Tfl~T~T COURT\nIN THE UNITED STATES DISTRICT COURT\n~ ?O~ .) C~.\nFOR THE EASTERN DISTRICT OF TEXAS, ~* li Ii ) Ft\nLUFKIN DIVISION TX EASTE~ - UFKtN\n\n\nSAMSUNG ELECTRONICS CO., LTD., \ufffd\n\ufffd\nPlaintiff, \ufffd\n\ufffd CIVIL ACTION NO. 9:02ev58\nv. \ufffd Judge Hannah\n\ufffd\nSANDISK CORPORATION, \ufffd\n\ufffd\nDefendant. \ufffd\n\nFIRST AMENDED COMPLAINT\n\nSamsung Electronics Co., Ltd., complains of SanDisk Corporation for violations of the\n\nUnited States patent laws. Samsung alleges as follows:\n\nPARTIES\n. Samsung Electronics Co., Ltd., (\"Samsung\") is a company organized under the laws of South\n\nKorea with its principal place of business located at 416 Maetan-3 Dong, Paldal-Gu, Suwon City,\n\nKyungki-Do, Korea.\n. On information and belief, SanDisk Corporation (\"SanDisk\") is a company organized under\n\nthe laws of Delaware with its principal place of business in Sunnyvale, California. SanDisk has\n\nappeared in this action and no further service of process is needed.\n\nJURISDICTION\n. This is an action arising under the United States patent laws, 35 U.S.C. \ufffd 101 etseq. This\n\nCourthassubjectmatterjurisdictionunder35U.S.C. \ufffd~ 271,281,and28U.S.C. \ufffd \ufffd 1331 and 1338\n\n(a).\n\nCase 9:O2-cv-O0O5~JH Document 20 FUed 04/03/2002 Page 2 of 127\n\n\nVENUE\n. Venue over Samsung' s claims is proper in this district pursuant to 28 U.S.C. \ufffd \ufffd 1391 (b)-(c),\n\nand 1400(b) because SanDisk resides in this judicial district, part of Samsung's causes of action\n\narose in this judicial district, including acts of patent infringement.\n\nBACKGROUND FACTS COMMON TO ALL CLAIMS\n. Samsung is the world's leading manufacturer of semiconductor memory products. Samsung\n\ncurrently manufactures, distributes and sells dozens of memory products throughout the world,\n\nincluding the United States. One of these memory products is a NAND flash card, which is\n\ncommonly referred to in the industry as a NAND flash memory product.\n. NAND flash memory products are typically removable memory cards that are often found\n\nin digital cameras, digital music players, digital camcorders, handheld PCs, e-Books, and newer\n\ncellular phone technology, as well as other emerging products.\n. SanDisk manufactures and supplies NAND flash memory products in consumer, OEM, and\n\nindustrial markets. More specifically, SanDisk supplies, at least, the CompactFlashTM product line\n\nwhich comprises NAND flash memory products, With, at least, its CompactFlashTM products that\n\ninclude NAND flash memory products, SanDisk infringes Samsung's patents.\n. SanDisk directly sells its NAND flash memory products around the world and through\n\nintermediaries, including wholesalers, distributors, value-added resellers, and retailers located\n\nthroughout the United States and specifically in this judicial district. Retailers of SanDisk NAND\n\nflash memory products include Circuit City, K-Mart, Office Depot, Target, Sears, Office Max,\n\nStaples, Eckerd drug stores and Waigreens drug stores, among others.\n. SanDisk also sells its NAND flash memory products to and through original equipment\n\nmanufacturers (\"OEMs\"), including Cannon, Hewlett-Packard, Fujitsu, Motorola, Kodak, Panasonic,\n\nCase 9:02-cv-O0O5~JH Document 20 F~ed 04/03/2002 Page 3 of 127\n\n\nand Polaroid, among others. SanDisk also sells NAND flash memory products to private label\n\npartners that re-brand the SanDisk products under a different trade name, which are then sold directly\n\nto consumers or installed into consumer products.\n. As part of its sales of NAND flash memory products in the United States, SanDisk markets,\n\npromotes, sells and offers for sale a full range of its NAND flash memory products in Texas.\n\nSanDisk markets its NAND flash memory products in Texas by using a direct sales organization and\n\nnumerous distributors and manufacturers' representatives. In fact, SanDisk even has a direct sales\n\noffice in Texas to support its OEM customers and its distribution and manufacturer representatives.\n. On information and belief, SanDisk NAND flash memory products, including the\n\nCompactFlashTM product line, have been sold and are currently being sold on Amazon.com's\n\nwebsite, which is available to consumers residing in the Lufkin Division. On information and belief\n\nand according to information provided by Amazon.com, based on purchases made via the\n\nAmazon.com website, the SanDisk 128MB CompactFlashTM card ranks among the top selling\n\nelectronic products purchased by consumers in Texas. SanDisk and Amazon.com do not restrict or\n\notherwise prevent consumers residing in the Lufkin Division from purchasing SanDisk NAND flash\n\nmemory products on the Amazon.com website.\n. On information and belief, SanDisk directly markets, promotes, sells, offers for sale, or leases\n\nits NAND flash memory products, including the CompactFlashTM product line, in numerous\n\nlocations throughout the Lufkin Division of the Eastern District of Texas (\"Lufkin Division\"). On\n\ninformation and belief, SanDisk also markets, promotes, sells, offers for sale, or leases its NAND\n\nflash memory products, including the CompactFlashTM product line, in numerous locations\n\nCase 9:02-cv-O0O58~JH Document 20 F~ed 04/0312002 Page 4 of 127\n\n\nthroughout the Lulkin Division by way of intermediaries, such as wholesalers, distributors, value-\n\nadded resellers and retailers.\n. SanDisk has sold and is currently selling a full range of its NAND flash memory products\n\nin the Lufkin Division. The SanDisk NAND flash memory products being sold in the Lufkin\n\nDivision include the CompactFlashTM product line. SanDisk is selling these NAND flash memory\n\nproducts either directly or indirectly through wholesalers, distributors, or value-added resellers, to\n\nvarious retail outlets located in Angelina and Nacogdoches Counties. These NAND flash memory\n\nproducts are in turn sold to consumers and end-users of the NAND flash memory products who\n\nreside in the Lufkin Division.\n. On information and belief, SanDisk NAND flash memory products, including the\n\nCompactFlashTM product line, have been sold and are currently being sold in Lufkin, Angelina\n\nCounty, Texas at the following retail outlets: Sears, which is located at the Lufkin Mall, 4600 S.\n\nMedford Dr., Lulkin, Texas 75901; Walgreens drugstore, which is located at 102 N. Timberland\n\nDr., Lufkin, Texas 75901; two Eckerd drugstores, which are located at 1204 E. Lufkin Avenue, and\n\nat 923 Frank Street, Lufkin, Texas 75901; Target, which is located at 4200 5. Medford Drive,\n\nLufkin, Texas 75901; Circuit City, which is located at 4600 S. Medford Drive, Lufkin, Texas 75901;\n\nOffice Depot, which is located at 4210 S. Medford Drive, Lufkin, Texas 75901; and OfficeMax,\n\nwhich is located at 2429 South John Reddit Drive, Lufldn, Texas 75901. Dozens, if not hundreds,\n\nofSanDiskNAND flash memory products are offered for sale to consumers at these locations within\n\nthe Lufkin Division. On information and belief, each of these retail outlets receives NAND flash\n\nmemory products either directly from SanDisk or indirectly through intermediaries, such as\n\nwholesalers, distributors or value-added resellers. On information and belief, under certain\n\nconditions, these retail outlets have the right to return any unsold SanDisk NAND flash memory\n\nCase 9:02-cv-O0O5~JH Document 20 F~ed 04/03/2002 Page 5 of 127\n\n\nproduct inventory directly to SanDisk, including any unsold NAND flash memory products in the\n\nCompactFlashTM product line.\n. On information and belief, SanDisk NAND flash memory products, including the\n\nCompactFlashTM product line, have been sold and are currently being sold in Nacogdoches,\n\nNacogdoches County, Texas at the following retail outlets: Staples, which is located at 4608 North\n\nStreet, Nacogdoches, Texas 75961; and Eckerd drugstore located at 1424 North Street, Nacogdoches,\n\nTexas 75961. Dozens of SanDisk products are offered for sale to consumers at these locations within\n\nthe Lufkin Division. On information and belief, each of these retail outlets receives NAND flash\n\nmemory products either directly from SanDisk or indirectly through intermediaries, such as\n\nwholesalers, distributors or value-added resellers. On information and belief, under certain\n\nconditions these retail outlets have the right to return any unsold SanDisk NAND flash memory\n\nproduct inventory directly to SanDisk, including any unsold products in the CompactFlashTM product\n\nline.\n. On information and belief, SanDisk NAND flash memory products, including products\n\nwithin the CompactFlashTM product line, have been incorporated into the following OEM products\n\nthat have been and are currently being sold in the Lufkin Division: Kodak digital cameras; Polaroid\n\ndigital cameras; Nikon digital cameras; and Hewlett-Packard digital cameras.\n. On information and belief, SanDisk products, including the CompactFlashTM product line,\n\nare being promoted, advertised and offered for sale in the Lufkin Division. More specifically,\n\nSanDisk products have been promoted, advertised, and offered for sale in Waigreens circular\n\nadvertisements that were included in fks newspaper, the Lulkin Daily News, on February 17,\n. SanDisk also promotes, advertises and offers for sale its NAND flash memory products on\n\nits website, which is described more fully in the following paragraphs.\n\nCase 9:02-cv-O0O5~JH Document 20 F~ed 04/0312002 Page $ of 127\n. On information and belief, SanDisk has knowingly and intentionally formed a channel of\n\ndistribution for its NAND flash memory products, including the CompactFlashTM product line, into\n\nthe Lulkin Division. SanDisk knows or should have known that the Lufkin Division was a\n\ntermination point of its distribution channel for NAND flash memory products, including the\n\nCompactFlashTM product line.\n. On information and belief, SanDisk has offered cash rebates on sales ofNAND flash memory\n\nproducts sold to consumers in the United States. Cash rebates have been offered for SanDisk's\n\nNAND flash memory products, including the CompactFlashTM product line, that were and are sold\n\nto consumers in the Lufkin Division. On information and belief, during SanDisk promotional\n\nevents, consumers can ordinarily obtain rebate information and rebate certificates for SanDisk's\n\nNAND flash memory products directly from the retail outlets located in the Lufkin Division that sell\n\nSanDisk NAND flash memory products, including the CompactFlashTM product line. This\n\ninformation can also be obtained on SanDisk's website, which is described more fully in the\n\nfollowing paragraphs.\n. On information and belief, SanDisk has offered and continues to offer warranties on its\n\nNAND flash memory products sold to consumers in the United States. Warranties have been offered\n\nand continue to be offered on SanDisk's NAND flash memory products, including the\n\nCompactFlashTM product line, to consumers residing in the Lufkin Division. On information and\n\nbelief, consumers can obtain warranty information and warranty registration materials for SanDisk's\n\nproducts from the retail outlets located in the Luf kin Division that sell SanDisk NAND flash memory\n\nproducts, including the CompactFlashTM product line. On information and belief, SanDisk warranty\n\ninformation and warranty registration materials for SanDisk's NAND flash memory products are\n\nCase 9:02-cv-O0O5~JH Document 20 F~ed 04/0312002 Page 7 of 127\n\n\nincluded within the package of each retail SanDisk product sold. This information can also be\n\nobtained on SanDisk's website, which is described more fully in the following paragraphs.\n. On information and belief, SanDisk offers a five-year warranty on at least some of its NAND\n\nflash memory products, including products in the CompactFlashTM product line. The SanDisk\n\nwarranty provides that SanDisk \"will repair or replace a NAND flash memory card free of charge\n\nif it ever fails within 5 years from the date of purchase.. . SanDisk will inspect the product and at\n\nits option, repair or replace the product. SanDisk will ship out a product with equal or greater\n\ncapacity.\"\n. The SanDisk warranty registration material on its NAND flash memory products, including\n\nthe CompactFlashTM product line, which is enclosed within the package of each retail product,\n\nrequire the consumer to complete a mail-in card enclosed with the product and mail the registration\n\nmaterials to SanDisk's Warranty Registration division. This warranty registration material refers\n\nconsumers to SanDisk's website, which is described more fully in the following paragraphs.\n. On information and belief, SanDisk engages in substantial e-commerce by way of the internet\n\nor world-wide web and does business in the Lufkin Division through its interactive website, which\n\nis located at http://w'ww.sandisk.comlmain.htm.\n. SanDisk's website is highly interactive in its promotion, advertising and marketing of\n\nSanDisk' s NAND flash memory products. The SanDisk website allows consumers to shop for, order\n\nand purchase a full range of SanDisk's NAND flash memory products. Consumers in Texas,\n\nincluding consumers residing in the Lufkin Division, have purchased SanDisk's NAND flash\n\nmemory products, including products from the CompactFlashTM product line, through SanDisk's\n\nwebsite. SanDisk does not restrict or otherwise prevent consumers residing in the Lufkin Division\n\nfrom purchasing SanDisk's NAND flash memory products on or through its website.\n\nCase 9:02-cv-O0O~JH Document 20 F~ed 04/0312002 Page 8 of 127\n. SanDisk has shipped NAND flash memory products, including products from the\n\nCompactFlashTM product line, purchased through SanDisk's website to consumers residing in the\n\nLufkin Division.\n. SanDisk's website provides consumers with warranty information related to its NAND flash\n\nmemory products, including its CompactFlashTM product line. See\n\nhttp ://www. sandisk.comltechlrw cf. asp. SanDisk does not restrict or otherwise prevent consumers\n\nresiding in the Lufkin Division from initiating warranty claims or obtaining warranty information\n\nabout SanDisk's NAND flash memory products from its website.\n. SanDisk allows consumers to register warranty information for its NAND flash memory\n\nproducts, including products from the CompactFlashTM product line, through its website. See\n\nhttp ://www.sandisk.comltech!prod-reg.asp. To register a NAND flash memory product for warranty\n\npurposes, the consumer must complete several fields of inquiry and provide requested information\n\nto SanDisk, including the consumer's residence and where the SanDisk product was purchased. See\n\nId. SanDisk does not restrict or otherwise prevent consumers residing in the Lulkin Division from\n\nregistering SanDisk's NAND flash memory products on or through its website.\n. SanDisk's website provides consumers residing in the Lufkin Division with cash rebates and\n\ncash rebate information on its NAND flash memory products. See\n\nhttp://www.sandisk.com/techlrebates.asp. As can be seen from the SanDisk website, rebates are\n\noffered on various SanDisk products, including CompactFlashTM cards, and from various retail\n\nmerchants. See and click on the Circuit City hyperlinkat http://www.sandisk.comltecblrebates.asp.\n\nSanDisk's website also instructs consumers on the proper procedure for obtaining a delayed rebate\n\npayment on any applicable SanDisk product. See and click on hyperlink \"Why haven't I received\n\nby rebate yet?\" at http://www.sandisk.comltech!faqsearch.asp. SanDisk does not restrict or\n\nCase 9:02-cv-O0O5~JH Document 20 FUed O4i03/2G~2 Page 9 of 127\n\n\notherwise prevent consumers residing in the Lufkin Division from obtaining rebates and rebate\n\ninformation on SanDisk's NAND flash memory products from its website.\n. SanDisk invites consumers to interact with its technical support staff via e-mail or telephone\n\nwith respect to customer service issues or technical support that consumers need for the proper\n\noperation and use of SanDisk's NAND flash memory products, including the CompactFlashTM\n\nproduct line. See http://www.sandisk.com/techlcontact.asp. SanDisk does not restrict or otherwise\n\nprevent consumers residing in the Lufkin Division from obtaining customer service information or\n\ntechnical support for SanDisk's NAND flash memory products from its website.\n. SanDisk invites consumers to interact with its website by allowing consumers to \"design\n\nproducts which use SanDisk cards, NAND flash memory chips [including CompactFlashTM\n\nproducts] and other SanDisk technology.\" See http://www.sandisk.comltechloem_designls_oem.asp.\n\nSanDisk does not restrict or otherwise prevent consumers residing in the Lulkin Division from\n\ninteracting with the SanDisk website to design products that incorporate SanDisk's NAND flash\n\nmemory products.\n. SanDisk invites consumers to interact with its website by allowing consumers to download\n\nsoftware upgrades for various consumer devices so that SanDisk's NAND flash memory products,\n\nincluding products from the CompactFlashTM product line, are compatible with the consumer devices\n\nwith which they are installed. See http://www.sandisk.com/techlsdownloads.asp. On information\n\nand belief, certain consumer products will not function unless the consumer downloads the\n\nappropriate software (e.g., drivers) from SanDisk's website. SanDisk does not restrict or otherwise\n\nprevent consumers residing in the Lufkin Division from interacting with the SanDisk website to\n\ndownload software so that SanDisk's NAND flash memory products can be installed in consumer\n\ndevices.\n\nCase 9:O2-cv~0005$~'H Document 20 F~ed 04103/2002 Page 10 of 127\n. SanDisk invites consumers to interact with SanDisk by allowing consumers the option to\n\nenroll in SanDisk's quarterly product e-mail list that is distributed to consumers by SanDisk. See\n\nhttp:1/www.sandisk.comltechlprod-reg.asp. SanDisk does not restrict or otherwise prevent\n\nconsumers residing in the Lufkin Division from receiving SanDisk's quarterly product e-mail list.\n. As the preceding paragraphs show, SanDisk clearly does business in the Lufkin Division by\n\nvirtue of its established channels of distribution and interactive website.\n\nCOUNT ONE\nInfringement of United States Patent No. 5,473,563\n. Samsung incorporates by reference paragraphs 1 through 33 as though fully set forth herein.\n. Samsung is the sole owner of the entire right, title, and interest in United States Patent No.\n,473,563 (\"the `563 patent\"), which was duly and legally issued to Samsung on December 5, 1995,\n\nand entitled \"Nonvolatile Semiconductor Memory.\" A copy of the `563 patent is attached hereto as\n\nExhibit A.\n. Samsung has never licensed or permitted SanDisk to practice any of the claims granted in\n\nthe `563 patent.\n. On information and belief, SanDisk has infringed the `563 patent, literally or by equivalents,\n\nby making, using, selling, offering for sale, leasing, or importing NAND flash memory products into\n\nthe United States, including the Lufkin Division, that infringe one or more of the claims of the `563\n\npatent. On information and belief, SanDisk continues to engage in such acts of infringement.\n. On information and belief, SanDisk, with full knowledge of Samsung's ownership interests\n\nin the `563 patent, has intentionally induced and is currently inducing others to infringe the `563\n\npatent, or has contributed to the infringement of the `563 patent by actively and knowingly aiding\n\nand abetting others to make, use, sell, offer for sale, lease, or import NAND flash memory products\n\nCase 9:O2-cv~0005~JH Document 20 F~ed 04103/2002 Page Ii of 127\n\n\ninto the United States, including the Lufkin Division, that infringe one or more of the claims of the\n\n`563 patent, either literally or by equivalents.\n. SanDisk' s infringement of the `563 patent has been willful, and any further infringement of\n\nthe `563 patent by SanDisk would be with full knowledge of Samsung's legal interest in the `563\n\npatent and would be deliberate and willful.\n\nCOUNT TWO\nInfringement of United States Patent No. 5,514,889\n. Samsung incorporates by reference paragraphs 1 through 39 as though fully set forth herein.\n. Samsung is the sole owner of the entire right, title, and interest in United States Patent No.\n,514,889 (\"the `889 patent\"), which was duly and legally issued to Samsung on May 7, 1996, and\n\nentitled \"Non-Volatile Semiconductor Memory Device and Method for Manufacturing the Same.\"\n\nA copy of the `889 patent is attached hereto as Exhibit B.\n. Samsung has never licensed or permitted SanDisk to practice any of the claims granted in\n\nthe `889 patent.\n. On information and belief, SanDisk has infringed the `889 patent, literally or by equivalents,\n\nby making, using, selling, offering for sale, leasing, or importing NAND flash memory products into\n\nthe United States, including the Lufkin Division, that infringe one or more of the claims of the `889\n\npatent. On information and belief, SanDisk continues to engage in such acts of infringement.\n. On information and belief, SanDisk, with full knowledge of Samsung's ownership interests\n\nin the `889 patent, has intentionally induced and is currently inducing others to infringe the `889\n\npatent, or has contributed to the infringement of the `889 patent by actively and knowingly aiding\n\nand abetting others to make, use, sell, offer for sale, lease or import NAND flash memory products\n\nCase 9:O2-ev~O0O5$-JH Document 20 FUed 04103120&2 Page 12 of 127\n\n\ninto the United States, including the Lufkin Division, that infringe one or more of the claims of the\n\n`889 patent, either literally or by equivalents.\n. SanDisk's infringement of the `889 patent has been willful, and any further infringement of\n\nthe `889 patent by SanDisk would be with full knowledge of Samsung's legal interest in the `889\n\npatent and would be deliberate and willful.\n\nCOUNT THREE\nInfringement of United States Patent No. 5,546,341\n. Samsung incorporates by reference paragraphs 1 through 45 as though fully set forth herein.\n. Samsung is the sole owner of the entire right, title, and interest in United States Patent No.\n,546,341 (\"the `341 patent\"), which was duly and legally issued to Samsung on August 13, 1996,\n\nand entitled \"Nonvolatile Semiconductor Memory.\" A copy of the `341 patent is attached hereto as\n\nExhibit C.\n. Samsung has never licensed or permitted SanDisk to practice any of the claims granted in\n\nthe `341 patent.\n. On information and belief, SanDisk has infringed the `341 patent, literally or by equivalents,\n\nby making, using, selling, offering for sale, leasing, or importing NAND flash memory products into\n\nthe United States, including the Lufkin Division, that infringe one or more of the claims of the `341\n\npatent. On information and belief, SanDisk continues to engage in such acts of infringement.\n. On information and belief, SanDisk, with full knowledge of Samsung's ownership interests\n\nin the `341 patent, has intentionally induced and is currently inducing others to infringe the `341\n\npatent, or has contributed to the infringement of the `341 patent by actively and knowingly aiding\n\nand abetting others to make, use, sell, offer for sale, lease, or import NAND flash memory products\n\nCase 9:O2-cv~0005$~H Document 20 F~ed 0410312002 Page 13. of 127\n\n\ninto the United States, including the Lufkin Division, that infringe one or more of the claims of the\n\n`341 patent, either literally or by equivalents.\n. SanDisk's infringement of the `341 patent has been willful, and any further infringement of\n\nthe `341 patent by SanDisk would be with full knowledge of Samsung's legal interest in the `341\n\npatent and would be deliberate and willful.\n\nCOUNT FOUR\nInfringement of United States Patent No. 5,642,309\n. Samsung incorporates by reference paragraphs 1 through 51 as though fully set forth herein.\n. Samsung is the sole owner of the entire right, title, and interest in United States Patent No.\n,642,309 (\"the `309 patent\"), which was duly and legally issued to Samsung on June 24, 1997, and\n\nentitled \"Auto-Program Circuit in a Nonvolatile Semiconductor Memory Device.\" A copy of the\n\n`309 patent is attached hereto as Exhibit D.\n. Samsung has never licensed or permitted SanDisk to practice any of the claims granted in\n\nthe `309 patent.\n. On information and belief, SanDisk has infringed the `309 patent, literally or by equivalents,\n\nby making, using, selling, offering for sale, leasing, or importing NAND flash memory products into\n\nthe United States, including the Lufkin Division, that infringe one or more of the claims of the `309\n\npatent. On information and belief, SanDisk continues to engage in such acts of infringement.\n. On information and belief, SanDisk, with full knowledge of Samsung's ownership interests\n\nin the `309 patent, has intentionally induced and is currently inducing others to infringe the `309\n\npatent, or has contributed to the infringement of the `309 patent by actively and knowingly aiding\n\nand abetting others to make, use, sell, offer for sale, lease or import NAND flash memory products\n\nCase 9:O2-cv~00058~J~H Document 20 F~ed 04103/2002 Page 14 of 127\n\n\ninto the United States, including the Lufkin Division, that infringe one or more of the claims of the\n\n`309 patent, either literally or by equivalents.\n. SanDisk's infringement of the `309 patent has been willful, and any further infringement of\n\nthe `309 patent by SanDisk would be with full knowledge of Samsung's legal interest in the `309\n\npatent and would be deliberate and willful.\n\nCOUNT FIVE\nPreliminary and Permanent Injunction\n. Samsung incorporates by reference paragraphs 1 through 57 as though fully set forth herein.\n. As a consequence of SanDisk's activities described herein, Samsung has been irreparably\n\nharmed to an extent yet ascertained, and will continue to be irreparably harmed by such activities in\n\nthe future unless SanDisk is enjoined by this Court from engaging in said activities. Samsung has\n\nno adequate remedy at law.\n. Samsung is only seeking relief against SanDisk's NAND flash memory products.\n\nPRAYER FOR RELIEF\n\nWHEREFORE, Samsung requests that this Court enterjudgment against SanDisk and grant\n\nSamsung the following relief:\n. Issue a preliminary injunction enjoining SanDisk from making, using, selling,\noffering for sale, leasing, or importing NAND flash memory products that infringe\non one or more claims of the following Samsung's patents:\n\n(a) United States Patent No. 5,473,563;\n(b) United States PatentNo. 5,514,889;\n(c) United States Patent No. 5,546,341; and\n(d) United States Patent No. 5,642,309;\n. Upon final hearing, permanently enjoin SanDisk from any such activity as described\nin paragraph 1;\n. Find that SanDisk's infringement through its NAND flash memory products of\nSamsung's patents was and is willful;\n\nCase 9:O2-cv~0005$~H Document 20 F~ed 041O312O~2 Page 15 of 127\n. Find that this an exceptional case and award Samsung reasonable attorneys fees in\naccordance with 35 U.S.C. \ufffd 285; and\n. Award Samsung the costs it has incurred to prosecute this action.\n\nDated: _____________, 2002. Respectfully submitted,\n\n\nGeorge E. Chandler\nAttorney-In-Charge for Plaintiff\nSamsung Electronics Co., Ltd.\nState Bar No. 04094000\nCHANDLER LAW OFFICES\nE. Frank Poland Professional Building\nP.O. Box 340\nLufkin, Texas 75902\nTelephone: (936) 632-7778\nFacsimile: (936) 632-1304\nE-mail: gchandler~chandlerlawoffices.com\n\nOF COUNSEL:\n\nTHE LAW OFFICES OF CLAYTON E. DARK, JR.\nClayton E. Dark, Jr.\nState Bar No. 05384500\nP.O. Box 2207\nLuficin, Texas 75902\nTelephone: (936) 637-1733\nFacsimile: (936) 637-2897\n\nTHE RICHARDS LAW FIRM\nR.W. (\"Ricky\") Richards\nState Bar No. 16854100\nP.O. Box 1309\nJacksonville, Texas 75766\nTelephone: (903) 586-2544\nFacsimile: (903) 586-6529\n\nTHE LAW OFFICES OF CLAUDE E. WELCH\nClaude E. Welch\nState Bar No. 21120500\n\nCase 9:02-cv~OOO5$~JH Document 20 F~ed 04/03/2002 Page 16 of 127\n\nCertifIcate of Service\n\nI hereby certify that a true and correct copy of the foregoing was served in\ncompliance with Rule 5 of the Federal Rules of Civil Procedure on April 1, 2002, on the\nfollowing:\n\nTracy Crawford\nRAMEY & FLOCK, P.C.\nE. Ferguson St.\nFirst Place\nTyler, TX 75702\nTelephone: (903) 597-3301\nFacsimile: (903) 597-2413\n\nMichael A. Ladra\nJames C. Ottesen\nJames C. Yoon\nWILSON SONSINI GOODRICH & ROSATI\nProfessional Corporation\nPage Mill Road\nPalo Alto, CA 94304-1050\nTelephone: (903) 493-9300\nFacsimile: (903) 565-5100\n\nCase 9:O2~-cv~0005~JH Document 20 F~ed 04/03/2002 Page 17 of 127\n\n\nUNITED STATES DISTRICT COURT\nEASTERN DISTRICT OF TEXAS\nLUFKIN DIVISION\n\nSAMSUNG ELECTRONICS CO., LTD.,\n\nPlaintiff\nCIVIL ACTION NO. 9:02CV58\nvs. Judge Hannah\n\nSANDISK CORPORATION,\n\nDefendant.\n\nORDER\nOn this day, came on to be considered the Plaintiff's Unopposed Motion for Leave to\n\nFile First Amended Complaint and after having considered same, the Court is of the opinion\n\nthat said Motion should be granted.\n\nIt is therefore ORDERED that the Plaintiff's Unopposed Motion for Leave to File First\n\nAmended Complaint is hereby GRANTED.\n\nSIGNED this ________ day of ___________________, 2002.\n\n\nUNITED STATES DISTRICT JUDGE\n\nCase 9:02-cv~0005$~JH Document 20 Filed 04/03120&2 Page 18 of 127\n\nIIHIRlIIIII1IhllUhfflhIl1llll~UIli\nUS005473563A\n\nUnited States Patent (199]\nSuh et aL\n\n(111 Patent Number:\n(451 Date of Patent:\n,473,563\nDec. 5, 1995\n\n[54] NONVOLATILE SEMICONDUCTOR\nMEMORY\n\n[75] Inventors: Kang D. Sub, Almyaxig; I'm KL Kim,\nSeoul; Jeong E Chof, Kwacheteon, all\nof Rep. of Korea\n\n[73] Assignee: San~ung Electronics Co., LUlL,\nSuwon, Rep. of Korea\n\n[21] AppL No.: 171,300\n(2.2] Filed: Dec. 22, 1993\n[30] Foreign Application Priority Data\nIan. 13. 1993 [KR] Rep. of ICorea - 1993.390\n(51] mt.. a.6 ____... GUC 7/00; Gi:iiC 11/40\n[52] U.S. Cl. ....___.. 365/185.13; 36~5/189.0l;\n.05; 36651230.06\n(581 FIeld of Search ...._..._..._._ 365/11185, 218,\n/900, 189.01, lS9.0~)5, 230.06\n[56]\n\nReferences Cited\nU.S. PAT~T DOCUMENTS\n,053,990 1(W1991 l(reifels ct aL.\n,313,432 5/1994 Un ~ ii. -_. 33651230.06\n,345,418 9/1994 (usia _.._..~--.- 365/185\nFOREIGN PATENT DOCUMENTS\n/1991 Rap. of Xmas.\nOTh~ PUBLICATIONS\n\"New Device Technologies For 5V-On1y4MbEEEPROM\nWith NAND Structure Cell\" by M. Momodomi4, R. Kir-\nisawa, R. Nakayama., S. Aritonae, T. Endob, Y. Itoh,i, Y. Iwata,\nFL Oodaira, T. Thuaka, M. Chiba, R. ShiroU~a, and F.\nMasuoka. ULSI Research Center~ Toshiba Coo poration.\n-1EDM 88.\n\"A Nand Strnctured Cell With A New Prograrnanixing Thch-\nnology For Highly Reliable 5V-Only Flash ~R1tOM\", It\n\nKmsawa. S. Aritome, R. Nakaysma, T. Endob, It Shirota.\nand F. Masuoka, 1990 Symposium ocx VLSI Technology.\n\"A High-Density NAND EEPROM With Block-Page Pro-\ngramrning For Microcomputer Applications\", Y. Iwata, M.\nMoinodomi, T. Thnaka. H. Oodaira. Y. Itoh, R. Nakayaxna,\nIt Kirisawa, S. Aritome, T. Endoh, It Shirota, K. Ohuchi,\nand F. Masuoka 1990 IEEE\nA 4-Mb NAND EEPROM with light Programmed Vt\nDistribution, M. Momodomu, T. Tanaka, Y. Iwata, Y.\nTanaka, H. Oodaira, Y. Itoh, R. Shirota, IC Ohuchi and F.\nMasuoka 1990 IEEE.\n\nPr\ufffdE.zaminer-Tan T. Nguyen\nAttorney, Ageig or Finn-Robert A. Westerlund; Stephen R.\nWhitt,~ aiarles It Donoh.oe\n\n[571\n\nABSTRACT\nA nonvolatile semiconductor memory device comprising an\narray of cell units, each cell unit including at least one\nmemory transistor which has a floating gate and a control\ngate, the array being divided into a plurality of memory\nblocks each having a certain number of cell units. A selected\nmemory block is erased by an erase voltage applied to a\nsemiconductor substrate while unselected memory blocks\nare prevented from erasing by capacitive coupling of the\nerase voltage to coated word lines connected to control gales\nof memory transistors of the unselected memory blocks. In\na program mode where a program voltage is applied to a\nselected word line of a selected memory block and a pass\nvoltage is applied to unselected word lines of the selected\nmemory block, channel regions and source and drain junc-\ntions of memory transistors of cell units in the selected\nmemory block arc charged to a program inl~bition voltage.\n(1,aimd regions and source and drain junctions of cell units\nassociated with memy transistors programmed to the other\nbinary data are discharged to be programmed while those of\ncell units associated with nonprogrammed memory transis-\ntori are maintained to the program inhibition voltage to\n- programmin~\nO~lms, 19 DrawIng Sheets\n\nCase 9:02-cv~OOO58-JH Document 20 F~ed 04/03/2002\n\nPage 19 of 127\n\nU.S. Patent\n\nDec. 5, 1995\n\nSheet 1 of 19\n,473,563\n\nI/O 1 I/O 2 I/O 3 * * * I/O 7 I/O 8\n\nFIG. 1\n\nCase 9:02-cv~0005.8-JH Document 20 F~ed 04/03/2002 Page 20 of 127\n\nSGL1 -1\nBT 1\n~\n\n~ - \n~\n\nC\n\nCG\n\nCGL6\nB1~7~ p\nCGL7'-~--~----~-- - \n\nSGL1 -2..~~--~~__--fl'L_\n\nBT1O~'\n\nSGL2-2'-.--~-----L~--\n\nCG\n\nCGL7\n\nCG L6~ - Hi\n\nCGL5~ ---- HL\n\nCGL4~------HIl\nCGL3~------H~\n\nCGL2~-----Hi\nCGL1'-~----I[-\n\nSGL2-1~\n\n\nBSC2 34-2 BLL-U\n____ - ___________ - I - I -\n\nU.S. Patent\n\nDec. 5, 1995\n\nSheet 2 of 19 5,473,563\nNU\n\n/ CBL(A1=1,2 ,8)\n\nFIG. 2a\n\nCase 9:02-cv~OOQ5.~-jH Document 20 F~ed 04/03/2002\n\nPage2l of 127\n\nU.S. Patent\n\nDec. 5, 1995\n\nSheet 3 of 19\n,473,563\n\nI/O A.\n\nFIG. 2b\n\nCase 9:02-cv~000S8-JH Document 20 F~ed 04/03/2602\n\nPage 22 of 127\n\nU.S. Patent\n\nDcc. 5, 1995\n\nSheet 4 of 19\n\n---s.jv\nI--\nBL\nNU\n\n_\\ 1~i96\n'-4\n\n_____ r'>._STi\nI I\n-t \ufffd\n\n\n~1\n\n~-~-*\n\n-I-\n\nI\nI\n\n~=#\n-i\nI\n\n\nI\n=~\nI\n\n\nrM7\n-H :: ~ \ufffd\n\n~oH1__\n,473,563\n\nr\n-f\n\nt~WL1\n\n\nWL7\n\n()\n\n\nS1O4-~ \ufffdU'\n-\n\nS\nCSL-\n ~1\n\n\nL\n\n__4-~sL2\n\nL \n\n---~Iv\n~~~~\n-1\n\nFIG. 3\n\nCase 9:02-cv~000S6-JH Document 20 F~ed 04/03/2602 Page 23. of 127\n\nU.S. Patent\n\n\nN\n-J\n~\n\nDec. 5, 1995\n\nSheet 5 of 19\n,473,563\n\n-J\nV)\n\nCase 9:02-cv~0005&jH\n\nDocument 20 F~ed 04/03/2002\n\nPage 24 of 127\n\nU.S. Patent\n\nDec. 5, 1995\n\nSheet 6 of 19\n\n\nc'.1\n,473,563\n\n-J\n(I)\n\nE\nax\n~\n>\n\nc~\nN')\n\n\n(I\n\nC\n~\n>\n\nU,\n\n\n/\n\niN\nN')\n\n-J\nU)\n\nto\nCs4.\n\n*\n\nUi\n`a\n\n\n`a\nUi\nC'\n\n(,~=1,2, ... ,8)\nCD\n\nA8or~8\nAgorAg\nAlOor Ai\nCGL/\n\nQA ~I)\n\na\n.'\n\nFIG. 6\n\nCase 9:02-cv~0005.~-jH Document 20 F~ed 04/03/2902\n\nPage 26 of 127\n\nU.S. Patent\n\nDec. 5, 1995\n\nSheet 8 of 19\n,473,563\n\nVcc\nH\nPGM\n\n\n/\n\nVpi\nFIG. 7\nFIG. 8a\nFIG. 8\n\nCase 9:02-cv~0005i~-JH Document 20\n\nF~ed 04/03/2002\n\nPage 27 of 127\n\nU.S. Patent\n\nDec. 5, 1995\n\nSheet 9 of 19\n,473,563\n\n\n~-1\n-I\n\n\n\ufffd\n\n\n\n\n\n\n\nTO 162\n\nPGM\n\n\nFIG. 8b\n\n\n\ufffdE ~ ~EEi07\nPGM\n\n\nFIG. 8c\n\nCase 9:02-cv~000~-JH Document 20 F~ed 04/03/2602 Page 28 of 127\n\nU.S. Patent\n\nDec. 5, 1995\n\nSheet 10 of 19\n,473,563\nHd7~Hd\nfit\n\n\nVcc\nH\n/\n(~~=1,2 .8)\n\n\n\nFPL\nSFP\n\nFP1\nFP2\nFP3\nFP4\n\nFP5\nFP6\nFP7\nFP8\n\nFIG. 9a\n\n\nFIG. 9\n\nPDS\n\n\n--220\n`7-\nFIG. 9b\n\nCase 9:02-cv~0005B~JH Document 20 F~ed 04/03/2002 Page 29 of 127\n\nU.S. Patent\n\n\nWE\n\nERA\n\nPGM\n\nSLE\n\nVpgm\n\nVpas\n\n\ufffd\n\nXd\n\nBLK\n\nDS\n\nVera\n\nDCB\n\nSBL\n\nDec. 5, 1995\n\nSheet 11 of 19\n,473,563\n\nFIG. 10\n\nCase 9:02-cv~0005e-JH Document 20 F~ed 04/03/2002 Page 30 of 127\n\nU.S. Patent\n\n\nPGM\n\nSLE\n\n\nBLK\n\nDS\n\nERA\n\n\ufffd\n\nVpgm\n\nVpas\n\nVpi\n\n\ufffdBL\n\nDCB\n\nDec. 5, 1995\n\nSheet 12 of 19\n,473,563\n\nFIG. 11\n\nCase 9:02-cv~0005~JH Document 20 F~ed 04/03/2002 Page 31 of 127\n\n\nU.S. Patent Dec. 5,1995 Sheet 13 of 19 5,473,563\n\n\nSBL~] --\n\n\nDCB~J 1\n\n\n- 5V--\n\nDS0v\n\n\ufffd\nV -\nov - ______ _________________\nV -\nov\n\nti 13\n\n\nFIG. 12\n\nCase 9:02-cv~0005~JH Document 20 F~ed 04/03/20e2 Page 32 of 127\n\nU.S. Patent\n\n\nCGL1\nCG L2\nCGL3\nCGL4\nCGL5\nCG L6\nCG L7\nCGL8\nUSGL~.\n\nDec. 5, 1995\n\nSheet 14 of 19\n,473,563\n\nc=1,2,3 ,512.)\n\n____ SBK~\n- - I - I -\n\nFIG. 13a\n\nCase 9:02~cv~0005~JH\n\nDocument 20\n\nFUed 04/03/2002\n\nPage 33. of 127\n\nU.S. Patent\n\n.,~\n-J\n(I,\n\nDec. 5, 1995\n\nSheet 15 of 19\n\n\n..~\n-J\n(I)\n-J\n,473,563\n\niN\n..~\n- 0\n\nU)\nED\n\nN')\niN\n\nII\n~\n\naD\nN')\n\n*\nN')\n\nU,\nN)\n\nCD.\nN')\n~\n<\n\nP.-,-\n<\n\n\ntL-J\nN)\n\niN\n*\n\nI C)\nr-1 C-)\n>\n\na,\nN')\n\niN\nN)\n\nCase 9:02-cv~0005~RJH Document 20 F~ed 04/03/2002\n\nPage 34 of 127\n\nU.S. Patent\n~4)\n\nDec. 5, 1995\n\n\n(.0\nF~~)\n\n\n(.0\nN-\n\n\nc'J\n(0\np()\n\nSheet 16 of 19\n\n\n-J\n(I)\nC,\n-I\n,473,563\n\n-J\nC,,\n\nN\nPr)\n\nN\nPr)\n~\n<\n\nCase 9:02-cv~0005~RJH Document 20\n\nF~ed 04/03/2002 Page 35 of 127\n\nU.S. Patent\n\nDec. 5, 1995\n\nSheet 17 of 19\n,473,563\n\n\nWEm\n\nERA\n\nPGM\n\nVpgm\n\nVpas\n\n\n\ufffd\n\nXd\n\nBLLK\n\n\nDS\n\nVera\n\nDCB\nV\nOv\nv\nOv\nV\nOv\nV\nV\nV\nV\nV\nOv\nV\nv\nV\ncv\nV\nOv\nV\nOv\n\ni-I--\nIi\n\n\nPt\n~3 14t5\n\n\nI\n\n\n~l ~2\n\nFIG~ 16\n\nCase 9:02-cv~0005$-JH Document 20 F~ed 04/03/2002 Page 36 of 127\n\n\nU.S. Patent Dec. 5,1995 Sheet 18 of 19 5,473,563\n\n\n~5V ___________\nOv I______\nV ______________________I\n\n\n____ 5V\nPGM0v I\n\n~5V__ -i--i-\nOv\n\n.~5V I I\nLJ\nERA 5V I\n\n_______ I.\nI I\n\n\nvp~18V______\nOv\n\nVpas~V I\nOv\nV ______ _______________________I___\n\ufffd\nV\nSBL _____\n\nov lii\nV\nDCB _____ ____________________\nv\n\nti 13 t4\n\nFIG. 17\n\nCase 9:02-cv~0005$-JH Document 20 F~ed 04/03/2002 Page 37 of 127\n\n\nU.S. Patent Dec. 5,1995 Sheet 19 of 19 5,473,563\n\n\nFIG. 2a FIG. 13a\n\n\nFIG. 2b FIG. 13b\n\n\nFIG.2 FIG. 13\n\n\nFIG. 18\n\nCase 9:02-cv-0005$-JH\n\nDocument 20 F~ed 04/03/2002\n\nPage 38 of 127\nNONVOLATILE SEMICONDUCTOR\nMEMORY\n\nFIELD OF THE INVEN'FION\nThe present invention relates to electrically erasable and\nprogrammable nonvolatile semiconductor memories and,\nmore particularly, but not exclusively, to electrically eras-\nable and programmable nonvolatile semiconductor memo-\nries with NAND structured cells.\n\nBACKGROUND OF THE INVENTION\nVarious systems controlled by recent computers or micro-\nprocessors require the development of an electrically eras- t5\nable and progr~mrnshle read-only memory (hereinafter\nreferred to as a EEPROM) of a high density. Particularly,\nsince the use of a hard disk with a rotary magnetic disk as\na secondary storage occupies a relatively large area in a\nportable computer system such as a battery-powered corn- 20\nputer system of notebook size, system designers take much\ninterest in the development of EEPROMs of high density\nand high performance occupying a smaller area To achieve\na high density EEPROM, it is a major problem to reduce the\narea occupied by memory cells. Th solve such a problem, an 25\nEEPROM has been developed which contains NAND struc-\ntured cells being capable of decreasing the number of\nselection transistors per cell and contact boles coupled with\na bit line. Such a NAND structured cell is disclosed in the\nIEDM, pp 412 to 415, 1988 under the title of \"NEW 30\nDEVICE TECHNOLOGIES FOR 5 V-ONLY 4 Mb\nEEPROM WITH NAND SiRUCTURE CELL\". This\nNAND structured cell (hereinafter referred to as a NAND\ncell unit or a NAN1) cell) is comprised of a first selection\ntransistor whose drain is connected to the corresponding bit 35\nline via a contact hole; a second selection transistor whose\nsource is connected to a common source line; and eight\nmemory transistors whose channels are connected in series\nbetween the source of the first selection transistor and the\ndrain of the second selection transistor. The NAND cell is 40\nformed on a p-type semiconductor substrate, and each\nmemory transistor includes a floating gate layer formed on\na gaze oxide layer over a channel region between its sowce\nand drain regions and a control gate layer separated from the\nfloating gate layer by an intermediate insulating layenTo 45\nprogram of write a selected n~nory transistor in the NAND\ncell, operation of simultaneously erasing all memory tran-\nsistors therein must be followed by the programming opera-\ntion. The simultaneous erasum is performed by applying 0\nvolts to the bit line arid rising the gate of the first selection so\ntransistor aM mol gates of all memory transistors to 17\nvolts. This ~ all memory transistors to be changed into\nenhacetneri -~ trmn~iito~~ which am assumed as binary\nlogic \"1\" programmed transistors. To program a selected\nmemory transistor to a binary logic \"CT', 22 volts are applied 55\nto the bit line, the gate of the first selection transistor and\ncontrol gates of memory transistors between the first selec-\ntion transistor and the selected memory transistor, while 0\nvolts are applied to the control gate of the selected memory\ntransistor, control gazes of memory transistor between the 60\nselected memory transistor and the common source line, and\nthe gale of the second selection transistor. Thus, the selected\nmemory transistor is changed into a depletion mode tran-\nsistor by the Fowler-Nortiheim tunneling (F-N tunneling) of\nholes from its drain to its floating gate. However, the 65\nproblem of programming in this manner is that a portion of\nthe gate oxide of the selected memory transistor is subjected\nto a stress induced by application of the high voltage to its\ndrain, and the partially stressed gate oxide causes leakage\ncurrent to flow. This results in degrading more and more the\ndata retention capability of the memory cell according to an\n~ increase of the number of cycles of erasing and/or program-\nming, thereby reducing the reliability of the EEPROM. To\nsolve this problem, an improved device structure, in which\nthe NAND cells are formed on a p-type well region ixnbed-\nded in an n-type semiconductor substrate, and further\n~ improved erasing and programming technologies utiliring\nthe improved device structure are disclosed in the sympo-\nsium on VLSI Technology, pp 129 to 130, 1990 under the\ntitle of \"A NAND STRUCI1JRED CELL WITH A NEW\nPROGRAMMING TECHNOLOGY FOR HIGHLY REU-\nABLE 5 V-ONLY FLASH EEPROM\".\nErasure of all memory transistors in this NAND cell is\nperformed by applying 0 volts to all control gazes and a high\npotential of 20 volts to the p-type well region and the n-type\nsubstrate, thereby uniformly extracting electrons from their\nfloating gates to the well region. As a result, each memory\ntransistor has a threshold voltage of about -4 volts which\nrepresents a state of depletion mode, i.e. a logic \"0\". To\nprogram a selected memory transistor in the NAND cell, a\nhigh voltage of 20 volts is applied to the gate of the first\nselection transistor and the control gaze of the selected\nmemory transistor, while 0 volts are applied to the gate of\nthe second selection transistor, and an intermediate voltage\nof 7 volts is applied to control gates of unselected memory\ntransistors. If the selected memory transistor is to be written\nor programmed into a logic \"1\", 0 volts are applied to the bit\nline connected with the NAND cell, thereby injecting elec-\ntions into the floating gate of the selected memory transistor.\nThis results in causing the selected memory transistor to\nbecome enhancement mode. On the contrary, if the selected\nmemory transistor is to be programmed to a logic \"0\". a\nprogram inhibition voltage of 7 volts instead of 0 volt is\napplied to the bit line to inhibit the programming of the\nselected memory transistor. Since such a programming\noperation uniformly injects electrons from the p-type well to\nits floating gale via its gate oxide layer, the partial stress on\nthe thin gate oxide layer does not occur to a significant\ndegree, and the gale oxide leakage current may thus be\nprevented.\nHowever, when the memory capacity becomes high, such\nways of uniform erasing and programming cause problems\nin the case that system designers want to erase a portion or\na block of previously written or programmed memory cells\nin order to reprogram. In this case, a conventional approach\nis to simultaneously erase all memory transistors in a\nmemory cell array, i.e. to carry out a flash erasure, and then\nto newly reprogram the content of all programs. Thus, since\nsignificantly reusable portions or blocks of the memory\narray are simultaneously erased, the reprogramming not\nonly needs a long time, but also is inconvenient It may be\nappreciated that such problems seriously occur when the\nmemory density becomes more highet To solve these prob-\nlerns, it is made possible only to erase all memory transistors\nin a selected memory block. However, in the case of an\nEEPROM using the above-mentioned improved erasing and\nprogramming techniques, to prevent the erasing of all\nmemory transistors in an unselected block, it is required that\na high voltage equal to an erase voltage or a high voltage of\nabout 18 volta or more be placed on their control gates.\nThus, this technology has a drawback that a decoding circuit\nfor performing a block erasing operation becomes compli-\ncated on design. In addition, when the density of the\nEEPROM cells increases, an on-chip occupying area of the\n,473,563\n\nCase 9:02-cv-0005$-JH Document 20 F~ed 04/03/2002 Page 39 of 127\n,473,563\ndecoder increaaes, thereby making it difficult to design the\ndecodet\nAnother problem for the prior art is that of programming.\nTo prevent the programming of non-programmed memory\ntransistors, which must maintain previous data, of memory\ntransistors on a selected word line, it is required that each of\nbit lines corresponding to the non-programmed memory\ntransistors be raised to the intermediate, Le. the program\ninhibiting voltage, via a charge pump circuit connected\nthereto. In addition, when the memory capacity is increased,\nthe number of bit lines or the length of each bit line is\nincreased. Consequently, it is necessary that a high voltage\ngenerating circuit on the same chip for supplying the high\nvoltages to the charge pump circuits has a high performance.\nSuch a high voltage generating circuit and the charge pump\ncircuits give a problem in increasing the area occupied by\nthe on-chip peripheral circuits.\nConventional EEPROMs include a page program mode\nfor high-speed programming. The page programming opera-\ntion is composed of a data loading operation and a program-\nming operation. The data loading operation comprises\nsequentially latching or storing data of a byte size from\ninput/output terminals to a data register. The programming\noperation comprises simultaneously writing the data stored\nin the data register into memory transistors on a selected\nword line via bit lines. The page programming technology\non an EEPROM with NAND cells is disclosed in the IEEE\nJOURNAL OF SOLID-STATE CIRCUITS, VOL 25, NO.\n,pp417to423,APRIL199O.\nConventional EEPROMs employ a programming verifi-\ncation technique to enhance their reliability. The verification\nmeans checking to determine if programmed cells are pro-\ngraznmed so as to have desired threshold voltages. Tech-\nnologies of the programming verification may be classified\ninto an external verification technique controlled by a micro-\nprocessor and an internal verification technique performed\nby an on-chip verification circuit The external verification\ntechnique is disclosed in the IEEE JOURNAL OF SOLID-\nSTATE CIRCUITS, VOL 26, NO.4, pp 492 to 495, April\nand U.S Pat No. 5,053,990. The external verification\ntechnique has a problem in that it takes a predetermined long\ntime to determine if progranuned cells am well programmed.\nIn addition, whenever reprogramming is performed after the\nfailure of the programming, it is necessary that the data\nloading operation is performed again. However, the internal\nverifying technique has an advantage that the programming\nverification is performed at a higher speed. The internal\nverifying technique is disclosed in ICorean Patent Laid Open\nNO. 91-17445 aM ItS. Pat. No. 4,811,294. In these docu-\nments, the ssii&ation is performed in such a manner that\ncomparaict assus compare data stored in a data register\nwith data raM out in pages from memory cells via sense\namplifiers. However, such a scheme employing comparator\nmeans increases an occupied area of on-chip peripheral\ncircuits.\n\nSUMMARY OF THE INVENTION\nIt is therefore an object of the present invention to provide\na nonvolatile semiconductor memory with NAND struc-\ntured cells which can reduce the size of chip.\nIt is another object of the present invention to provide a\nnonvolatile semiconductor memory with NAND stnattured\ncells which can reduce power consumption.\nIt is further object of the present invention to provide a\nnonvolatile semiconductor memory which performs an eras-\nlag of selected one of memory blocks.\nIt is still further object of the present invention to provide\na nonvolatile semiconductor memory which is program-\nmable without application of a program inhibition voltage of\nhigh voltages on unselected bit lines in order to reduce a chip\nsize and power consumption.\nIt is another object of the present invention to provide\nmethods for block erasing and programming which are\ncapable of redncing on-chip occupying area and power\nconsumption in a nonvolatile semiconductor memory with\nNAND structured cells.\nIt is another object of the present invention to provide a\nnonvolatile semiconductor memory in which on-chip area of\nperipheral circuits can be reduced in size.\nIt is further object of the present invention to provide a\nnonvolatile semiconductor memory in which over program-\nming can be prevented.\nAccording to an aspect of the present invention, a non-\n~ volatile semiconductor memory includes, word lines formed\nover a surface of a semiconductor substrate; cell units\narranged on said surface to form en array, each said unit\nincluding at least one memory transistor which has source\nand drain regions formed in said substrate but separated by\n~ a channel region, a charge storage layer formed over the\nchannel region, and a control gaze formed over the floating\ngaze and coupled to a corresponding one of said woid lines,\nsaid array being divided into a plurality of memory blocks\neach having a certain number of cell units; and means,\nresponsive to an address in a data erase mode, for applying\nan erase voltage to said substrate, and simultaneously float-\ning word lines of memory blocks unselected by said address,\nwhereby erasure of memory transistors of said unselected\nmemory blocks is prevented by capacitive coupling of a\npredetermined amount of said erase voltage to the word lines\nof said unselected memory blocks.\nAccording to another aspect of the present invention, a\nnonvolatile semiconductor memory includes, a semiconduc-\ntor substrate having a well region; memory transistors\nformed on the well region and arranged in a matrix form of\nrows and columns, the memory transistors comprising cell\nunits each of which has a predetermined number of memory\ntransistors connected in series, and first and second termi-\nnals at its both ends, cell units in respective rows constitut-\nlag a memory block, each memory transistor having source\nand drain regions formed in the well region but separated by\na channel region, a floating gate formed over the channel\nregion to store charge representing binary data, and a control\ngale formed over the floating gaze; word lines each being\nso connected to control gates of memory transistors in a\ncorresponding row; bit lines generally intersecting the word\nlines; a common source line; first and second selection lines\ngenerally in parallel with the word lines; first selection\ntransistors respectively connected between first terminals of\ncell units in each memory block and corresponding bit lines\nfor selectively connecting therebetween, gates of first selec-\ntion transistors associated with each memory block being\nconnected to a corresponding first selection line; second\nselection transistors connected between second terminals of\ncell units in each memory block and the common source line\nfor selectively connecting therebetween, gates of second\nselection transistors associated with each memory block\nbeing connected to a corresponding second selection line;\ndata register connected to the bit lines for providing binary\ndata to the bit lines, the register providing logic high level\nvoltages to bit lines associated with memory transistors\nprogrammed to one binary data of the binary data while\nCase 9:02-cv-00058~JH Document 20 F~ed 04/03/2002 Page 40 of 127\n,473,563\nproviding refareoce voltages to bit lines associated with\nmemory transistors programmed to the other binary data\nthereof; and control means connected to the word lines and\nthe first and second selection lines for applying a program\nvoltage to a selected one of word lines of a selected memory S\nblock and pass voltages to unselected word lines of the\nunselected memory block while applying a logic high level\nvoltage to the first selection line associated with the selected\nmemory block and rendering nonconductive second selec-\ntion transistors associated therewith, whereby channel io\nregions and source and drain junctions of memory transis-\ntors in the selected memory block are capacitively charged\nto program inhibition voltages.\nAccording to another aspect of the present invention, a\nmethod for programming memory transistors in a row in a\nsemiconductor memory which comprises a semiconductor\nsubstrate; memory transistors formed on a surface of the\nsubstrate and arranged in rows and columns, the memory\ntransistors comprising cell units each of which has a prede-\ntemiined number of memory transistors connected in series,\nand first and second terminals at its both ends, each memory\ntransistor having source and drain regions formed in the\nsubstrate but separated by a channel region, a floating gate\nformed over the channel region to store binary data, and a\ncontrol gate formed over the floating gate, cell units in\nrespective rows constituting a memory block; word lines\neach being connected to control gates of memory transistors\nin a corresponding row; bit lines generally intersecting the\nword lines, the first terminal of each of cell units of each\nmemory block being connected to a corresponding one of\nthe bit lines via a first selection transistor, and a common\nsource line connected to the second terminal of each of cell\nunits via a second selection transistors, the method includes\nthe steps of applying a program voltage to a selected word\nline of a selected memory block and a pass voltage lower\nthan the program voltage to the remaining word lines\nthereof, while applying a logic high level voltage lower than\nthe pass voltage to gates of first selection transistors asso-\nciated with the selected memory block and rendering non-\nconductive second selection transistors associated therewith,\nthe logic high level voltage corresponding to a logic high\nstate; and applying a logic low level voltage corresponding\nto a logic low stare to bit lines assocrated with memory\ntransistors programmed from one binary data to the other\nbinary data, while applying the logic high level voltage to bit\nlines associated with memory transistors not programmed.\nwhereby channel regions and source and drain junctions of\nthe nonprogrammed memory transistors are capacitively\ncharged to a voltage level between the logic high level\nvoltage and ~ gram voltage so as to prevent program-\nming. whilc ~se of the programmed memory.\n\nBR1~ DESCRIPTION OF DRAWING\nFor a better understanding of the invention, and to show\nhow embodiments of the same may be carried into effect,\nreference will now be made, by way of example, to the\naccompanying diagr~mmithc drawings, in whichi\nFIG. 1 shows a schematic block diagram of an electrically 60\nerasable and programni~1ile read-only memory according to\nthe present invention,\nFIG. 2 is comprised of FIGS. 2a and 2b: FIG. 2a\nillustrating the arrangement of memory cells within a first\nand a second memory blocks associated with a k-tb column\nblock, and transfer transistor arrays connected thereto; and\nFIG. 2b showing an input/output buffer, a column decoder\nand selection circuit, a data register and sense amplifiers\nassociated with the k-th col~ bl~\nFIG. 3 shows a plane view of layout pattern for one of\nNAND cells constituting a memory ccli array;\nFIG. 4 shows a cross-sectional view of NAND cdl taken\nsubitantiaily along line IV-IV of FIG. 3;\nFIG. 5 shows a schematic circuit diagram of a block\nselection control circuit used in an embodiment of FIG. 2;\nFIG. 6 shows a schematic circuit diagram of a control gate\ndriving circuit used in embodiments of FIG. 2 and FIG. 13;\nFIG. 7 shows a schematic circuit diagram of a source line\ndriving circuit used in the embodiment of FIG. 2;\nFIG. 8a shows a circuit diagram of a tristale inverter used\n~ inFIG.2b;\nFIG. 8b shows a circuit diagram of a trrstate NAN]) gate\nused in FIG. 6;\nFIG. 8c shows a schematic timing circuit diagram for\n~ generating control signals ~6 and ~ used in the block\nselection control circuit of FIG. 5;\nFIG. 9 shows a program determination circuit comprised\nof FIGS. 9a and 9b, in which FIG. 9a is a circuit diagram\nshowing a portion of the program determination circuit and\n~ FIG. 9b is a circuit diagram showing a summation circuit\nFIG. 10 shows a timing chart of various control signals\nused in a block erasing mode according to the first embodi-\nment of the present invention;\nFIG. U shows a timing chart of various control signals\nused in a programming mode according to the first embodi-\nment of the present invention;\nFIG. 12 shows a timing chart of various control signals\nused in a programming verification mode and a reading\nmode according to the first and modified embodiments of the\npresent invention;\nFIG. 13 is a circuit diagram showing a schematic modified\nembodiment comprised of FIGS. 13a and 2b, in which FIG.\na is a circuit diagram illustrating the arrangement of\nmemory transistors within an i-tb memory block having\nshared word lines in the k-tb column block,\nFIG. 14 shows a schematic circuit diagram of a block\nselection control circuit associated with the modified\nembodiment of FIG. 13;\nFIG. 15 shows a schematic circuit diagram of a ground\nline driving circuit associated with the modified embodiment\nof FIG. 13;\nFIG. 16 shows a timing chart of various control signals\nused in a block erasing mode of the modified embodiment;\nFIG. 17 shows a timing chart of various control signals\nused in a programming mode of the modified embodiment\nand\nFIG. 18 is a diagram showing the manner in which the\n~ separate sheets of drawings of FIGS. 2a and 2b, and FIGS.\na and 2b.\nIn the figures, like reference numerals denote like or\ncorresponding parts.\n\nDErAILED DESCRIPTION OF THE\nPREFERRED EMBODIMENTS\nIn the following description, numerous specific details,\nsuch as memory cells, the number of NAND cells, the\nnumber of bit lines, the value of voltages, circuit elements\nand parts and so on, are set forth in order to provide a\nthorough understanding of the present invention. It will be\n\n\n\nso\n\nCase 9:02-cv-0005~JH Document 20 F~ed 04/03/20.02 Page 41 of 127\n,473,563\nunderstood by those skilled in the art that other embodi-\nments of the ~seent invention may be practiced without\nthese specific derails, or with alternative specific details\nThe term \"memory transisro?' as used herein refers to a\nfloating gate MOS FE~ having a source, a drain, a floating 5\ngate and a control gate. The term \"programming\" is used to\ndescribe the writing of data into selected memory transis-\ntors. The term \"NAND cell charging\" is defined to the\ncharging of the channel and the source and drain junction\ncapacitors of the respective memory transistors constituting\nthe NAND cell to a predetermined potentiaL\nIn the following description, symbols k and i are respec-\ntively used for those parts associated with a k-tb column\nblock and an i-tb memory block~ Symbol j represents a\nnotation associated with a j-th word line. 15\nThe term \"ground potential\" (or like terms such as\n\"ground voltage\" or \"earth\" potential or voltage\" is used\nconveniently in this specification to denote a reference\npotential. As will be understood by those skilled in the art,\nalthough such reference potential may typically be zero\npotential, it is not essential that it is so, and may be a\nreference potential other than zero.\nAn example of an EEPROM of the present invention is\nfabricated by using CMOS manufacturing technologies on a\ncommon chip, in which depletion mode n-channel MOS ~\ntransistors each having a threshold voltage of -2 to -3 volts\n(hereinafter referred to as D-type transistors), enhancement\nmode n-channel MOS transistors each having a threshold\nvoltage of about 0.7 volta (hereinafter referred to as n-chan-\nnel transistors) and p-channel MOS transistors each having 30\na threshold voltage of about -0.9 volts (hereinafter referred\nto as p-channel transistors) are employed.\nFIG. 1 illustrates a schematic block diagram of one\nexample of an EEPROM according to the present invention.\nFIG. 2 is composed of FIG. 2a and FIG. 2b in parallel\nrelationship with each other, and shows, for theconvenience\nof illustration, only those elements associated with the k-th\ninput/output terminal UOlc a memory cell array 10, an input\nand an output buffers 26 and 28, a column decoder 30, a ~\ncolumn selection circuit 32, a data register and sense ampli-\nfier 12 and a transmission transistor array 34-i which is\nconnected with the memory cell array 10 and constitutes a\nportion of a block selection control circuit 1& It should be\nnoted that elements associated with the remaining input/ ~\noutput terminals are identical to those associated with the\nterminal 110k\nReferring now to FIGS. land 2, the memory cell array 10\nof the prescri EEPROM is composed of NAND cells NU\narranged in a~ix form of 1,024 rows and 2,048 columns, so\nand includN 1,024 memory blocks SKi to BK 1024 divided\nin a row ~ Each NAND cell is composed of memory\ntransistors ~fl to MS whose drain-source paths are con-\nnected in series between the sorn*cc of a first selection\ntransistor ST1 and the drain of a second selection transistor 55\nST2. Gates of the first and second selection transistors ST1\nand ST2 and control gates of the memory transistors Ml to\nM8 are respectively connected to first and second selection\nlines SL1 and SL2 perpendicular to bit lines BLk-1 to\nBLk-256 (k=1,2 8) and word lines WLI to WLS. Thus, 60\nthe memory transistors Ml to MS are disposed at intersec-\ntions of the word lines WL1 to WLS and the bit lines BLk-1\nto BLk-2S6. Drains of the first selection transistors ST1 are\nrespectively connected with corresponding bit lines, and\nsources of the second selection transistors STS are con- 65\nnected to a common source line CSL. Consequently, the\nmemory cell array 10 is comprised of memory cells of a total\nof 1 ,024x8x2,048 (=16,777,216), and each memory block is\ncomprised of memory cells of a total of Sx 2,048 (16,384).\nThe memory cell array 10 is divided into eight column\nblocks Bk (k=l,2, . . . , 8) respectively corresponding to\ninput/output terminals 1/01 to 1/08, and each column block\nhas 256 bit lines or column lines which are parallel in a\ncolumn direction. Thus, each column block includes\nmemory cells totalling 256 Kbit (=l,024x256).\nThe memory cell array 10 is formed on a p-well region in\na semiconductor substrate. FIGS. 3 and 4 respectively show\na plan view and a cross-sectional view of one of NAND cells\nNU constituting the memory cell array 10.\nReferring to FIGS. 3 and 4, the semiconductor substrate\nis of a p-type silicon monocrystalline material which is\nart on the (1,0,0) crystal orientation at an impurity concen-\ntration of about 7xlO'4 atoms/cm3. A p-type well region 76\nwith an impurity concentration of about 2xlO'6 atoms./cm3\nis formed having a depth of about 4pm from a main surface\nof the substrate 72. The well region 76 is surrounded by\na n-type well region 74 of about 10 pm in depth with an\nimpurity concentration of about 5x10'5 atoms/cm3. Heavily\ndoped N~ regions 80 to 92 are formed on the main surface\nof the well region 76 and separated by each of a plurality\nof channel regions 94. One part of the N region ~ is a\ncontact region connected via a contact bole 96 to a bit line\nBL of a metal material, such as an aluminum, which extends\nover an insulation layer 112, and the other part of the N~\nregion 80 also serves as a drain region of the first selection\ntransistor ST1. The N~ regions 82 to 90 serve as common\nsource-drain regions of two adjacent transistors of lransis-\ntoes 511, Ml to MS and 512. One part of the N'~ region 92\nis a source region of the second selection transistor ST2, and\nthe other part of the N region 92 serves as buried common\nsource line CSL However, the line CSL may be a conductor\nlayer which is insulatively formed within the insulating layer\ncontacting with the N~ source region 92 of the transistor\nST2 via a contact hole. Gate layers 98 and 100 of a\nrefractory metal silicide material, such as a tungsten suicide,\neach of which has a thickness of about 1,500 A, are\nrespectively formed on gale insulating layers 102 of about\nA thickness, overlying channel regions of the first and\nsecond selection transistors 511 and ST2.\nFloating gate layers 104 of a polycrystafline silicon mate-\nrial are insulalively formed with a thickness of about 1,500\nA on gate insulating layers 106 of about 100 A thickness\noverlying channel regions 94 of memory transistors Ml to\nMS. respectively. Control gates 108 of the same material and\nthickness as the gate layers 98 and 100 are respectively\nformed over the floating gate layers 104 interposing inter-\nmediate insulating layers 100, such as ONO insulating\nlayers of silicon dioxide-silicon nitride-silicon dioxide mate-\nrials, of about 250 A thickness. The gate layers 98 and 100\nand the control gate layers 108am respectively shared by the\nfirst and second selection lines SL1 and SL2 and word lines\nWLI to WL8, i.e. conductor layers which are fabricated\nfrom the same material as the gate and control gate layers 98,\nand 108. The gate layers 98 and 100, control gate layers\n, floating gate layers 104, the first and second selection\nlines SL1 and SL2, and word lines WL1 to WLS are\ninsulated from one another with an insulating layer 112 of\ninsulating materials, such as a silicon dioxide and a BPSG\nor a PSG.\nThe bit line BLis connected with the contact region 80 via\nthe contact hole 96 and extends ins column direction on the\ninsulating layer 112. The p-type well region 76 and the\nn-type well region 74 arc connected to a well electrode 114\nin common via contact holes (not shown). An erasing\n\nCase 9:02-cv-0005$RJH Document 20 F~ed 04/03/2002 Page 42 of 127\n,473,563\nvoltage is app&ied to the well electrode 114 in an erasing\noperation, and a reference potential, i.e. ground potential is\napplied to the well electrode 114 in operations except the\nerasing operation, i.e. in a programming, programming\nverification and reading operations. However, the substrate 5\nis always at the reference potential. The memory cell\narray 10 may also be formed on a p-type well region formed\nin an n-type monocystafline silicon substrate.\nReturning now to FIGS. 1 and 2, the block selection\ncontrol circuit 18 serves to select a predetermined memory 10\nblock of the memory blocks BK1 to BK1024, and to provide\ncontrol signals on control gate lines CGLI to CGLS from a\ncontrol gate driving circuit 20 to word lines V~Uto WLS in\nthe selected memory block according to various operation\nmodes, such as the erasing, programming, programming 15\nverification and reading modes. In FIG. 2a, ifiustration is\nmade of transfer transistor arrays 34-i constituting a portion\nof the block selection control circuit 18. Each of the transfer\ntransistor arrays 34-i includes transfer transistors ST1 to\nBT1O for connecting the first and second selection gate lines 20\nSGLi-l and SGLi-2 and control gate lines CGL1 to CGL8\nto the first and second selection lines SL1 and SL2 and word\nlines WL1 to WL8, respectively.\nAccording to one feature of the illustrated embodiment of\nthe present invention, the block selection control circuit 18 ~\nrenders nonconduclive the transfer transistors associated\nwith unselected memory blocks in an erasing operation,\nthereby causing word lines in unselected memory blocks to\nbecome floating. In a programming operation, the block\nselection control circuit 18 renders conductive the second ~\ntransistor 512 in a selected memory block, thereby charging\nthe program inhibition voltage from a source line driving\ncircuit 22 to channels and source and drain junctions of\nmemory transistors in the selected memory block.\nFIG. 5 shows a schematic circuit diagram for a block\nselection control circuit 18 connected to a transfer transistor\narray 34-i of FIG. 2a. For example, in the case of i=2, lines\nSGL2-1, SGL2-2 and BSC2 of FIG. S are respectively\nconnected to lines SGL2-1, SGL2-2 and BSC2 of the\ntransfer transistor array 34-2 associated with the second\nmemory block BK2 as shown in FIG. 2a~ Thus, it should be\nunderstood that though FIG. 5 shows, for the convenience of\nillustration, only a single circuit for selecting the i-tb\nmemory block BIG, the block selection control circuit of\nFIG. 5 corresponding to each of memory blocks BKI to\nBK1024 resides on the present EEPROM chip as a periph-\neral circuit.\nReferring now to FIG. 5, NAND gate 120 is a row\ndecoder for Uving address signals P1, QI, and Ri and a\nreset signal U. The address signals P1, Qi and RI are signals\npredecoded by anw address signals from a predecoder (not\nshown) for~&coding row address signalsA11,A11 toA~,\nA~ which are output from an address buffer for storing a\nrow address a11 to a,~, from external address input terminals. 55\nThe row decoder 120 provides a logic low state of 0 volts\n(hereinafter referred to as an \"L\" state or an \"L\" level) on a\nline 122 when selected, and outputs a logic high state of 5\nvolts (hereinafter referred to as an \"H\" state or an \"H\" level)\nthereon when unselected. Two input terminals of NAND 60\ngate 124 are connected to the line 122 and a signal ~EK,\nrespectively. The signal ~tK is a control signal for setting\nword lines WL1 to WLS to the reference potential before or\nafter the respective operations, as will be discussed herein-\nafter. The output of the NAND gaze 124 is connected to the\nfirst selection gate line SGLi-1 and to the block selection\ncontrol line BSCi via a current path of D-type transistor 126\nfor inhibiting the transfer of a high voltage. The gate of the\ntransistor 126 is connected to a program control signal\nP~M for maintaining an \"L\" state in a programming opera-\ntion. A charge pump circuit 128 is connected with the block\nselection control line BSCi for providing, when the line\nBSC1 is selected, a program voltage V,,,,,,oo the line BSCi\nby the pumping of a clock $R in the programming operation.\nThe charge pump circuit 128 is a known circuit comprised\nof n-channel transistors 130 and 1.32 and a MOS capacitor\n.\nTwo input terminals of NAND gate 136 are respectively\nconnected with an erase control signal ~k and the line 1.22.\nA transfer gate 148 composed of n-channel transistor 140\nand p-channel transistor 142 is connected between the\noutput of the NAND gate 136 and a connecting node 146.\nThe gate of n-channel transistor 140 is connected to a control\nsignal $6, and the gaze of p-channel transistor 142 is con-\nnected to the complement signal of $~ via an inverter 138.\nThe current path of n-channel transistor 144 is connected\nbetween the node 146 and the reference potential, and its\ngate is connected with a control signal $7. The source-to-\ndrain current path of D-type transistor 150 for preventing the\ntransfer of a high voltage is connected between the node 146\nand the second selection gate line SGLi-2, and its gate is\nconnected to a control signal W~. A charge pump circuit 152\nhaving the same construction as the circuit 128 is connected\nto the second selection gate line SGLi-2 for providing a pass\nvoltage V thereon during the programming operation\nwhen the f~'e SGLI-2 is selected.\nFIG. Sc is a schematic circuit diagram for generating the\ncontrol signals $6 and $7 as used in FIG. S. In an erasing\noperation or mode, $6 and $7 are all in \"L\" states, and in a\nNAND cell charging operation as will be discussed later, $~\nis in \"H\" state and $7 is in\"L\" state. In programming\nverf\ufffdion and reading operations, $6 is in \"H\" state and $7\nis in \"L\" state.\nFIG. 6 illustrates one of eight control gate driving circuits,\ni.e. the i-tb control gate driving circuit which constitutes\ncontrol gate driving means and is associated with the j-th\nword line. The outputs of the control gate driving circuits are\nrespectively connected to control gate lines CGLI to COLS\nwhich are respectively connected to word lines WL1 to WLS\nvia transfer transistor arrays 34-i. From the point of view of\nreduction of total chip size, it would be preferable that the\ncontrol gate driving circuits be provided in common in an\non-chip peripheral circuit so as to drive word lines of a\nselected memory block according to various operation\nmodes.\nReferring now to FIG. 6, NAND gate 154 isa row\ndecoder receiving row address signals A5/~, A9/A9 and\nA1dX from address buffer (not shown). The decoder 154\noutputs \"L\" state upon selection of the line CGLj while\noutputting \"H\" state upon unselection thereof. The output of\nthe decoder 154 and a control signal PVP are respectively\nconnected to two input terminals of NOR gate 173. An\noutput signal $,. of the NOR gale 173 and its complement\nsignal ~ via an inverter 174 are provided to control a\ntristate NAND gate 158 and a verifying voltage generator\n. The control signal PV~ maintains an \"L\" state only in\na programming verification operation. Thus, in every opera-\ntion excepting the programming verification operation, the\ncontrol signal PVF stays at \"H\" level, thereby causing the\nsignal $,, to be in an `V' state while causing the signal\nto be in an \"H\" state. In the programming verification\noperation, if the line CGLj is selected, $, becomes \"H\" state\nand its complement I!1 becomes \"I]' state while, if the line\nCase 9:02-cv-0005$JH Document 20 F~ed 04/03/20e2 Page 43 of 127\n,473,563\nCGLJ is in~4eeti.t1. $, becomes \"L\" state and ~ becomes\n\"H\" state. NAND gate 156 inputs the output of the decoder\nand control signals ~ and ERX, respectively. Two\ninput terminals of the tristate NAND gate 158 are respec-\ntivelyconnectedtoanotrtputlinel600ftheNANDgatels6 3\nand the control signal P~M. The thstate NAND gate 158\nWustrated in FIG. Sb is enabled in response to 4,, at \"U' level\nand ~ at \"H\" level while becoming high impedance with 4,.\nat `H\" level and ~ at \"L\" leveL Thus, in the programming\nverification operation, the NAND gate 158 stays in the high 10\nimpedance state only at the time when the line COLj is\nselected. The output of the NANI) gate 158 is connected to\na connecting node 162 to which the verifying voltage\ngenerator 164 is connected.\nThe verifying voltage generator 164 is comprised of a\np-channel transistor 166 and n-channel transistors 168, 170\nand 172 whose current paths are connected in series between\nthe power supply voltage Vcc and the reference potential.\nThe gate of the p-channel transistor 166 is connected to a\nchip enable signal ~, and gates of the transistors 168 and 20\nare connected to the signal 4,, from the NOR gates 173.\nDrain and gate of the transistor 172 are connected in\ncommon. The verifying voltage generator 164 is enabled by\n,. at \"H\" level only in the programming verification opera-\ntion, thereby producing a verifying voltage of about 0.2 volts ~\nto the connecting node 162. Connected between the con-\nnecting node 162 and the control gate line CGLJ is the\nsource-to-drain current path of D-type transistor 176 for\ninhibiting the transfer of a high voltage, the gate of which is\nconnected to the control signal ~M. 30\nTwo input terminals of NAND gate 175 are respectively\nconnected to the output of the NAND gate 156 and the clock\nRfrom a ring oscillator (not shown). Between the output of\nthe NAND gate 178 and the gate of a driving n-channel\ntransistor 182 is connected a charge pump circuit 180 which\nhas the same construction as the above-mentioned charge\npump circuit. Drain and source of the transistor 182 are\nconnected to the program voltage Vi,,,, and the control gate\nline CGLJ, respectively. Inverter 190 receives the program\ncontrol signal P~M, and the current path of D-type transistor\nfor preventing the transfer of a high voltage is connected\nbetween the output of the inverter 190 and the gate of the\ntransistor 182 which is connected to the control signal\nP~M. As will be discussed hereinafter, a circuit 196 which\nis comprised of NAND gate 178, the charge pump circuit\nand the driving transistor 182 provides means for\nsupplying the program voltage V,,,1, to the control gate line\nCGLJ when the line CGLJ has been selected by row address\nsignals A,/A, A,/~ and AiO/~ in a program\nTwo inp* ~n~h of NOR gate 188 are respectively\nconnected te~e output of the NAND gale 156 and the clock\n+R Betwe~ ~ output of the NOR gate 188 and the gate of\na driving n-~nn~i transistor 184 is connected a charge\npump circuit 186. Drain and Source of the transistor 184 are ~\nrespectively connected to the pass voltage V~, and the\ncontrol gale line CGLJ. Between a connecting node 202 and\nthe gate of the transistor 184 is connected the current path of\nD-type transistor 194 for preventing the transfer of a high\nvoltage, the gate of which is connected to the control signal ~\nPGM. As will be discussed hereinafter; a circuit 200 which\nis comprised of NOR gate 188, the charge pump circuit and\nthe transistor 184 provides means for supplying the pass\nvoltage V~,, to the control gate line CGLJ when the line\nCGLJ is selected by the row address signals in the program ~\nmode.\nFIG. 7 shows a schematic circuit diagram of a source line\ndriving circuit which is connected in common to the corn-\nmon source line CSL as shown in FIG. 2a. The source line\ndriving circuit 22 is composed of an inverter 204 whose\ninput terminal is connected to the control signal P~M, a\nD-type transistor 206 whose current path is connected\nbetween the output terminal of the inverter 204 and the\ncommon source line and whose gate is connected to the\ncontrol signal P~M, and a charge pump circuit connected to\nthe common source line CSL The charge pump circuit\nserves to boost the common source line to a program\ninhibition voltage V,~ in the program mode.\nThe input/output buffer 16 is comprised of the input buffer\nand the output buffer 28 which are each connected to\ninput/output terminals. The input buffer 26 connected to\neach of input/output terminals 1/01 to 1/08 is a conventional\ncircuit for converting a byte of data (8-hit data) therefrom to\nCMOS level data and temporarily storing it. Output buffers\nare conventional circuits to simultaneously output 8-bit\ndata read out from the corresponding column blocks to the\ncorresponding input/output terminals.\nThe column decoder and selection circuit 14 of FIG. 26 is\ncomprised of the column decoder 30 and the column selec-\ntion circuit 32. The column selection circuit 32 associated\nwith each of column blocks is comprised of transfer tran-\nsistors Ti to T256, source-to-drain paths of which are\nrespectively connected between a common bus line CBLk\nand lines DLk-1 to DLk-256. Gates of the transfer transistors\nTi to T256 are respectively connected to parallel lines TL1\nto TL256 which are connected to the column decoder 30.\nThe column decoder 30 selects one of the lines Thi to\nTL256 in response to column address signals from address\nbuffers not shown, thereby rendering conductive transfer\ntransistors connected with the selected line.\nThe data register and sense amplifier 12 is connected\nbetween the lines DLk-1 to DLk-256 and bit lines BLk-l to\nBLk-256 which am associated with the corresponding ool-\nunm block, as shown in FIG. 26. In series between the bit\nlines BLk-l to BLk-256 and nodes 36 are respectively\nconnected drain-to-source paths of 1)-type transistors 38 and\n. Gates of the D-type transistors 38 are connected to the\npower supply voltage Vcc to prevent the transfer of high\nvoltages induced on the bit lines BLk-1 to BLk-256 in a\nblock erasing operation. Gates of the D-type transistors 40\nare connected to a control signal $~ staying at \"H\" level of\nabout 5 volts during programming. Between the nodes 36\nand nodes 42 are respectively connected drain-to-source\npaths of n-channel transistors 44. Gates of the transistors 44\nare connected to a control line SBL staying at \"H\" level\nduring programming. Between the nodes 42 and nodes 46\nare respectively connected latches PBk-1 to PBk-256 con-\nstituting the data register which is referred to as a page\nbuffer. Each of the latches is comprised of two inverters\ncross connected. The latches P8k-i to PBk-256 serve not\nonly as a page buffer for temporarily storing data so as to\nsimultaneously write the data into memory cells via respec-\ntive corresponding bit lines in a programming operation, but\nalso as verifying detectors for determining if the program\nwas well performed in a programming verification operation\nand as sense ampli0ers for sensing and amplifying data on\nbit lines which is read out from memory cells in a reading\noperation. A tristate inverter 45 and an n-channel transistor\nare connected in parallel between each of nodes 42 and\nits cosresponding one of the lines DLk-1 to DLk-256. Each\nInstate inverter 48, which is referred to as a clocked CMOS\ninventor, is enabled by a control signal $4 at \"IF' level while\nbecoming high impedance by the signal 4, at \"U' level.\nThus, each of the inverters 48 serves as a buffer snip, being\n\nPage 44 of 127\n\nCase 9:02-cv-0005ERJH Document 20 F~ed 04/03/2O~2\n,473,563\nenabled in ~ugrsmIning verification and reading operations.\nN-channel ~ansis*on 49 whose gates are connected to a\ncontrol signal $~ are transfer transistors for transferring input\ndata to the corresponding latches P8k-i to PBk-256 in a\nprogramming operation. The tristale inverter 48 which is ~\nused in the present embodiment is illustrated as a schematic\ncircuit diagram in FIG. 8g. Between each of nodes 46 and\nthe reference potential are serially connected current paths\nof n-channel transistors 50 and 52. Gates of the transistors\nare connected to a control signal 42 staying at \"H\" level\nduring a verification sensing period in a programming\nverification operation and during a read sensing period in a\nread operation. Gates of the transistors 50 ate respectively\nconnected to the nodes 36, and drain-to-source paths of\nn-channel transistors 37 arc respectively connected between\nthe nodes 36 and the reference potential. Gates of the 15\ntransistors 37 ore connected in common to a line DCB to\nwhich a control signal is applied to cause bit lines to be\ndischarged after completion of erasing and programming\noperations and to reset the data register to \"L\" state, i.e. \"0\"\ndata prior to a reading operation.\nThe data register and sense amplifier 12 includes a\nconstant current source circuit 33, which is referred to as a\ncurrent mirror, according to the present embodiment. The\nconstant current source circuit 33 comprises a reference\nportion 64 which is enabled in programming verification and\nreading operations and disabled in erasing and programming\noperations; and current source portions 66 comprised of\np-channel transistors 54 whose drain-to-source paths are\nrespectively connected between gates of the transistors 50\nand the power supply voltage Vcc. The reference portion 64\nis comprised of p-channel transistors 56 and 58 and n-chan-\nnel transistors 60 and 62 to serve as a reference for the\ncurrent source transistors 54. Source-to-drain paths of the\np-channel transistors 56 and 58 are connected in parallel ~\nbetween the power supply voltage Vcc and a line 68, and the\ngate of the p-channel transistor 58 is connected to the line\n. Drain-to-source paths of the n-channel transistors 60 and\nare connected in series between the line 68 and the\nreference potential. The gate of the n-channel transistor 60\nis connected to a reference voltage V,,~ of about 2 volts.\nGales of the transistors 56 and 62 are connected to a control\nsignal 42, and gates of the current source transistors 54 axe\nconnected to the line 68. Thus, in programming verification\nand reading operations, the orm~L source Inansistors 54\nconnected to the reference portion 64 which ii enabled by\nthe control signal 42 serve to provide a constant current of\nabout 4 ~aA to bit lines BLk-1 to BLk-256.\nA programming determination circuit 24 of FIG. 1 is\nconnected via ~es 70 to lines DLk-1 to DLk-256 of FIG. 2b ~\nto serve to d.,.ine if every programmed memory tran-\nsistor reacb~ the range of desired threshold voltages in a\nprogr~rn1mIIg ,es\ufffdfrcatioc operation.\nFIG. 9 shows a .th~ni~ric circuit diagram of the program-\nming determination circuit 24. It should be noted that the 55\ncircuitry of FIG. 9a is a portion of the programming deter-\nmination circuit 24 associated with the k-th column block\nCBk, and eight circuits corresponding to the respective ones\nof column blocks present as a peripheral circuit on the\non-chip EEPROM. A circuit shown in FIG. 9b is a summa- 60\ntion circuit to perform a summation function for providing\nan \"L\" level when any one of signals FP1 to FF5 is \"L\"\nlevel. Referring to FIG. 9a, drain-to-source paths of n-chin-\nrid transistors 212 to 216 are connected in parallel between\na line 210 and the reference potential, and gates of the 65\ntransistors 212 to 216 are respectively connected to lines 70\nof FIG. 2b. Current paths of p-channel transistors 215 and\nD-type transistor 220 are connected in series, and the gate of\nthe transistor 218 is connected to a control signal SUP\nstaying at \"L\" level in a programming verification operation\nwhile the gaze of the transistor 220 is connected to the line\n. The transistors 212 to 220 constitute a NOR gaze 234.\nTwo input terminals of NOR gate 222 are respectively\nconnected to the line 210 and a control signal ~FP which\nbecomes \"L\" state only upon a verifying check The input of\nan inverter 224 is connected to the output of the NOR gate\n, and the output terminal of the inverter 224 outputs FPk.\nThe summation circuit 236 of FIG. 9b is comprised of\nNAND gate 226 connected to lines FF1 to FF4; NAND gate\nconnected with signals FF5 to FF5; and NOR gaze 230\nconnected to outputs of the NAND gates 226 and 228.\nReferring now to the timing charts of FIG. 10 to FIG. 12,\nan explanation will be given of operations and features of the\nfirst embodiment shown in FIGS. 1 to 9.\nBlock Erasing Mode\nIn a block erasing mode, the data register and sense\namplifier 12, the column decoder and selection circuit 14,\nthe input/output buffer 16 and the programming determina-\ntion circuit 24 are all in off states. Explained in more detail,\nthe column decoder 30 of FIG. 2b is reset, thereby rendering\ntransfer transistors Ti to 1'256 nonconductive. Control sig-\nnals 42 to 42 and signals on lines DCB and SBL ore held in\n\"L\" states, so that the data register and sense amplifier 12\nbecome nonconductive. The control signal SUP of FIG. 9a\nis held in \"H\" state, and the programming determination\ncircuit 24 is thereby nonconductive. The source line driving\ncircuit 22 provides \"I..\" state, ~e. the reference potential of\nvolts on the common source line CSL by PC~M staying at\n\"H\" level.\nNow, an explanation will be given in conjunction with the\ntiming chart of FIG. 10, assuming that simultaneous block\nerasing is performed on data stored in memory transistors in\nthe memory block BK1.\n`The time interval between t1 and 2 is a period for\ndischarging all word lines WL1 to WLS to the reference\npotential. During this period, NAND gaze 124 of FiG. 5\nretains \"IF' level with the control signal ~LK at \"L\" level,\nand D-type transistor 126 is conducting with P~M at \"H\"\nlevel. Thus, the block selection control line BSCi stays at\n\"H\" level of 5 volts. At this time, the charge pump circuit\nis in a nonconducting state. Consequently, in this period,\nall of the block selection control lines BSC1 to BSC1O24\nmaintain the potential of 5 volts. On the other hand, in this\nperiod, since control signals FVP and P~M stay at \"H\"\nlevels and the control signal ER~ is at \"L\" level, the outputs\nof NAND gate 156 and tristate NAND gates 158 remain at\n\"H\" level and \"L\" level, respectively. At this time, the\nthstate inverter 164 is in a high impedance state. Thus, the\ncontrol gate line CGLI stays at \"L\" level of 0 volts via\nturned-on D-type transistor 176. Consequently, all of control\ngate lines CGLI to CGL8 maintain \"L\" level during this\nperiod. Transfer transistors BT1 to BTIO are all turned on by\nthe potential of the block selection control lines BSC1 to\nBSC1O24 of 5 volts, and word lines WL1 to WL8 are all\ndischarged to the reference potential.\nThe time duration between t2 and t3 is a period to erase all\nmemory cells in only a selected memory block At time t2.\nthe decoder 120 receives address signals P1, QI and Ri which\narc all at \"IF' levels to select the memory block BK1, and the\noutput of the decoder 120 thereby goes to \"L\" level. Thus,\nthe output of NAND gate 124 goes t\ufffd' level. Conse-\nquently, the block selection control line BSC1 correspond-\ning to the selected memory block BK1 remains at the\n\nCase 9:02-cv-0005~JH Document 20 F~ed 04/03/20e2 Page 45 of 127\n,473,563\n\nis\npotential of 5 volta during the period between t2 and t~.\nHowever, decoders 120 associated with unselected memory\nblocks BK2 to BK1024 output \"H\" levels since at least one\nof the address signals Pt, QI and RI is \"L\" level. Conse-\nquently, block selection control lines BSC2 to BSC1O24 ~\nassociated with the unselected memory blocks go to the\nreference potentiai of 0 volts. Thus, transfer transistors in the\ntransfer transistor array 34-1 are all turned on, and word\nlines WL1 to WLS in the memory block BK! thereby go to\nthe reference potential. However, since the transfer transis-\ntor arrays 34-2 to 3-1024 connected with unselected memory\nblocks BK2 to BK1024 are all turned off, word lines\nassociated therewith go to floating states.\nAt time t2, the erase voltage Vera of about 20 volts is\napplied to the p-type well region 76 and the n-type well\nregion 74 via the well electrode 114 of FIG. 4. During the ~\ntime interval between t2 and t3, i.e. during the time period of\nabout 10 msec, floating gates of memory transistors in the\nselected memory block BK1 accumulate boles by means of\nthe F-N tunneling which is generated by the application of\nthe erase voltage Vera to their channel, source and drain 21)\nregions and that of the reference potential to their control\ngales. Thus, all of the memory transistors in the memory\nblock BKI are changed into D-type transistors having\nthreshold voltages of about -3 volts. That is. all memory\ntransistors in the memory block BKI are erased to binary ~\nzero da~\nHowever, in the case when the erase voltage V~ is\napplied to the p-well and N-well regions 76 and 74 via the\nwell electrode 114 at tUne t2, since word lines in unselected\nmemory block BK2 to BK1024 are then in floating states,\nthe word lines are thereby charged to substantially the erase\nvoltage Vera by a capacitive coupling. Thus, the charged\nvoltage of the word lines in the unselected memory blocks\nsufficiently reduces the electric field between the channel\nregion and the control gaze of each memory transistor such\nthat its erasure can be prevented. The inventors have dis-\ncovered that word lines in unselected memory blocks were\ncharged to amount of 80 to 90 percent of the erase voltage\nV,,,, and data of programmed memory transistors in the\nunselected memory blocks was not destroyed or disturbed.\nThus, in the block erasing of the present embodiment, since\nit is unnecessary to apply the program inhibition voltage\nfrom a voltage boosting circuit to word lines in unselected\nmemory blocks, a reduction of as well as the prevention of\npower consumption the area occupied by the chip. More-\nover, the present invention has an advantage of increasing\neffective memory array area whilst reducing peripheral\ncircuit area on a chip surface of a fixed size. This results in\nincreasing iha anemory capacity of the EEPROM.\nIn the sbus-mentioned block erasing operation, the erase\nvoltage ivplI~I to the well electrode 114 is coupled as well\non the flod word lines as on floated bit lines. Thus, the bit\nlines are also charged to the erase voltage of about 20 volts\nin the block erase operation. To prevent voltage-induced\nstress on transistors 40 of FIG. 2b due to the charged erase\nvoltage, D-type transistors 38, whose gates are connected to\nthe power supply voltage Vcc, are respectively connected\nbetween bit lines BLk-1 to BLk-256 and the transistors 40.\nDuring the block erasing operation between t2 and L3, the\nfirst selection line SL1 of the selected memory block BK!\nmaintains a potential of about 4.3 volts, and the second\nselection line SL2 of the block BKI is in a floating state\nsince control signals $6 and 42 are at \"L\" levels, thereby\nrendering transistors 140 to 144 of FIG. S nonconductive.\nThe floating state of the second selection line SL2 thereof\nprevents current flowing via the line SL2 from the well\nelectrode 114 when one or some of the second selection\ntransistort ST2 thereof failed. During the block erasing\noperation, the voltage relationship of significant portions of\nselected and unselected memory blocks can be summarized\nin the following TABLE 1.\n\n\n\n~btage Scares\nFor Selected Memory\nBlock\n\n\\t,Img: Stares\nFor Unietected\nMcnct~ry BIOCkI\n\nRnt Selection Line\n.3 V\nV\n\nSL1\n\n\n\nWord Lines WLI\nV\n\nApproximately 20 V\n\nto WU\n\n\n\nSecond Selection\n\nFloating\n\nFloating\n\nLine SI.2\n\n\n\nWeU3ecuo~\nV\nV\n\nThrning to FIG. 10, the time duration between t~ and t5 is\na period to discharge the charged voltage on bit lines and\nword lines. At time t3, the block erasing operation terminates\nand the erase voltage Vera goes to the reference potential\nwhile control signals WE and E~X go to \"H\" levels.\nBetween t3 and t4, the output of NAND gate 156 stays at \"H\"\nlevel with the control signal T5~ at \"L\" level. Thus, the\noutput of NAND gate 158 goes to \"L\" level with the control\nsignal P~]M at \"IF' leveL Consequently, control gate lines\nCOLI to CGL8 maintain `V' levels between t3 and t4.\nDuring this period, the output of NAND gate 124 of FIG. S\n~ stays at \"H\" level with the control signal EL~ at \"I..\" leveL\nThus, each of block selection control lines BSCI to\nBSC1O24 goes to a potential of 5 volts. Consequently, all\ntransfer transistors BT1 to BT1O are turned on, and all word\nlines WL1 to WLS are discharged to the reference potential.\nOn the other hand, the first and second selection lines SL1\nand SL2 are also discharged to a potential of 5 volts.\nAt time t3, the line DCB goes to \"H\" level and 42 also\ngoes to \"H\" level. Thus, the erase voltage charged on bit\nlines discharges to \"L\" level via transistors 37 shown in FIG.\nb.\nAt lime t4, control signals ~LK and D~ go to \"IF' levels\nand X goes to \"L\" leveL Thus, NAND gate 120 of FIG. 5\ngoes to \"H\" level, and the first and second gate lines SGL1-1\nto SGLI-2 and block selection control lines BSC1 go to the\nreference potential.\nProgram Mode\nThe present EEPROM performs a data loading operation\nto store data input via input/output terminals into data\nlatches PBk-1 to PBk-256 prior to a programming operation\nso alter an erasing operation.\nData loading operation is accomplished prior to a time t1\nof FIG. 11. During the data loading operation, control\nsignals X, *2~ 42 and 42, program voltage Vi,,,,,, pass\n~ voltage V,~,, p-well region 76, program inhibition voltage\nV,,~ and lines SBL and DCB stay at \"L\" levels, and control\nsignals W~ P~M, SEE, fltI~ !5~, ERA, PVF, SUP *R, $5\nand 42 am at \"IF' levels. As can be seen in FIG. 5, since\nXis \"L\" level and ELK, EEX SLE WE and P~M are all\n~ \"H\" levels, block selection gate lines BSC1 to BSC1O24 stay\nat \"L\" levels, thereby rendering transfer transistor arrays\n-1 to 34-1024 nonconductive. With the line SBL at \"L\"\nlevel, connection of data latches PBk-1 to PBk-256 to bit\nlines 81k-i to BLk-256 is inhibited. The constant current\ncircuit33andtriszaze inverters48of FIG. 2b arein non-\nconducting states with signals 42 and $~ at \"L\" levels.\nAddress inputting to external address input terminals is\n\nCase 9:02-cv-0005$~JH Document 20 F~ed 04/03/2082 Page 46 of 127\n,473,563\ncomposed of rew address a, to a~, and column address a~ to\na,,. The row address a, to a2~, inputs to select one of memory\nblocks and one of word lines during the data loading\noperation so as to write data on all bit lines into memory\ncells at one time, i.e., perform a page program in the ~\nprogramming operation after the completion of the data\nloading operation. The column address a, to a, is address\nsignals having 256 cycles during the data loading operation.\nThe column decoder 30 of FIG. 2b responds to the column\naddress of 256_\ufffd~cs based on the toggling of external write\nenable signal WE to render transfer transistors Ti to T256\nconductive in sequence. At the same time, input buffer 26\ncorresponding to the respective column blocks sequentially\noutputs data input to the corresponding input/output termi-\nnal in response to the toggling of WE. Thus, output data\nfrom the respective input buffers 26 is stored in sequence\ninto data latches PBk-1 to PBk-256 via sequentially turned-\non transfer transistors Ti to T256 and corresponding transfer\ntransistors 49.\nAfter the above-mentioned data loading operation, the w\nprogramming operation is started. One characteristic feature\nof the present embodiment is that the programming opera-\ntion includes the NAND cell charging operation.\nFor the convenience of explanation on the programming\noperation, it is assumed that data stored in the data latches 25\nis to be written into memory transistors M4 connected to a\nword line WL4 in the memory block BK1.\nThe programming operation is performed during the time\nperiod between t1 and t3 as shown in FIG. U. During this\nperiod, p-well region 76, signals WE, ~M, ~ 42 and 30\nand the line DCB stay at `L\" levels while signals X~l,\nELK, ~, E~X and 42 and the line SBL are all at \"H' levels.\nThe clock $~, the program voltage V,,,,, (=18 volts), the pass\nvoltage V,,,3 (=10 volts) and the program inhibition voltage\nV,,~ (=7 volts) axe supplied during this period. On the other ~\nhand, the row address a, to a~, wlsich is inputted during the\nabove-mentioned data loading operation, is latched in the\naddress buffer (not shown). Address signals Fl, QI and RI\nwhich are generated by predecoding address signals A11,\nto Az,, A of the latched address, are input to the ~\ndecoder 120 of FIG. 5. Address signals A,, ~ to A1~,\nA~ of the latched address input to the decoder 154 of FIG.\n.\nAt time 11, the control signal X~ goes to \"If' level, and ~\naddress signals P1, Ql aix! RI selecting the memory block\nare input to the NAND gate 120 of FIG. 5. Then, the\noutput of the gate 120 goes to \"L\" level, and outputs of\nNAND gates 124 and 136 go to \"H\" levels. Thus, the first\nselection g~ ~ SOLI-1 goes to a potential of 5 volts, and so\nthe block s~cljr'n control line BSC1 is boosted to the\nprogram vO~Sl V,,,.1 of 18 volts by the pumping operation\nof the chasp pump circuit 120 On the other hand, the\nsecond selection gate line SGL1-2 is boosted to the pass\nvoltage V,,,, of 10 volta by the pumping operation of the ~\ncharge pump circuit 152 with \"H\" level transferred via\ntransfer transistors 140, 142 and 150. Each decoder 120\nassociated with unselected memory blocks BK2 to BK1024\ngoes to \"IF' level, and the output of each NAND gate 124\ncorresponding thereto goes to \"1..\" level. Thus, unselected ~\nblock selection control lines BSC2 to BSC1O24 go to a\nreference potential of 0 volts.\nAt time L1, the program control signal P~3M goes to `L\"\nlevel and the common source line CSL, which is the output\nline of the source line chiving circuit 22 of FIG. 7, is boosted 65\nto the program inhibition voltage V~. That is, if P~M goes\nto \"L\" level, the common source line CSL goes to the\nabsolute value, for example 2 to 3 volts, of the threshold\nvoltage of D-type transistor 206 and is thereby boosted to the\nprogram inhibition voltage V,,~ by means of the charge pump\ncircuit 208.\nAs previously mentioned, since address signals A,, A to\nA10, X selecting the word line WL4 were input to the\ndecoder 154 of FIG. 6 in the previous data loading operation,\nthe output of the decoder 154 associated with CGL4 is at \"L\"\nlevel, and the outputs of the decoders 154 associated with\nto unselected word lines WL1 to WL3 and WLS to WL8 are at\n\"H\" levels. Thus, the output of NAND gate 156 associated\nwith the selected word line WL4 is at \"H\" level, and the\noutput of NAND gates 156 associated with the unselected\nword lines are at \"L\" levels. At time t1, the clock $~ is\n~ generated. Then, NAND gate 178 and NOR gate 108 asso-\nciated with the selected word line WL4 respectively output\nthe clock $R and \"L\" level, thereby providing the program\nvoltage Vpgm on the selected control gate line COLA. On\nthe contrary, NOR gates 188 associated with unselected\nword lines output the clock 42, thereby providing the pass\nvoltage V,,,, on unselected control gate lines CGL1 to CGL3\nand CGLS to COLt\nAt time t1, the line SBL goes to \"H' level. Thus, transfer\ntransistors of FIG. 2b are all turned on so as to transfer data\nstored in latches P8k-i to PBk-256 to corresponding bit\nlines ELk-i to BLk-256. All memory transistors of the\nselected memory block BKI in the previous block erase\nmode were erased to \"L\" levels, i.e. logic \"0\" data. In the\ndata loading operation after a block erasing mode, latches\ncorresponding to memory transistors which are to write \"H\"\nlevels, i.e. logic \"1\" data were stored to \"L\" level, i.e. logic\n\"0\" data while latches corresponding to memory transistors\nwhich are to write logic \"0\" data were stored to logic \"1\"\ndais. For the convenience of explanation, assume that logic\n\"1\" data is written into a memory transistor 240 which is\nconnected to the selected word line WL4 and bit line BL1-2\nof memory block BK1 in the first column block CB1 of FIG.\na while logic \"0\" data is written into the remaining memory\ntransistors connected to the word line WL4 thereof. Then,\nthe latch P81-2 has already stored logic \"0\" data while the\nremaining latches have already stored logic \"1\" data in the\ndata loading operation. Thus, after time t1, the conduction of\ntransfer transistors 44 causes the bit line BU-2 to go to \"L\"\nlevel and the remaining bit lines to go to \"H\" levels of 5\nvolts.\nConsequently, during the time duration between t1 and t~,\nthe transfer transistor array 34-1 of FIG. 2a is conducting,\nand the first and second selection lines SL1 and SL2 in the\nselected memory block BK1 respectively maintain 5 volts\nand V,,, (=10 volts) while the selected word line WL4 and\nunselected word lines WL1 to WL3 and WL5 to WL8\nmaintain V,,,,,1 (=18 volts) and V,,,,, respectively. During the\nprogramming operation, since the common source line CSL\nmaintains the program inhibition voltage V,,~ (=7 volts), the\nsecond selection transistor ST2 and memory transistors Mi\nto M8 in the block BK1 are all turned on, and the first\nselection transistor 242 connected to the bit line BL1-.2 is\nturned on while remaining first selection transistors exclud-\ning the transistor 242 in the block BK1 are turned off. Thus,\ncurrent paths of memory transistors in the NAND cell\nincluding the memory transistor 240 are connected with the\nbit line BL1-2, and channels of the memory transistors and\nthe respective junction capacitor of their sources and drains\nare thereby discharged to a reference potential of 0 volts.\nHowever, first selection transistors ST1 associated with\nmemory transistors which are to write logic \"0\" data are\nturned off, and channels of memory transistors in the NAND\n\nCase 9:02-cv-0005$~JH DocLirnent 20 F~ed 04/03/2092 Page 47 of 127\n,473,563\ncells associ*ed therewith and the respective junction capaci-\ntors of their soerces and drains are charged to the program\ninhibition voltage V,,~ (=7 volts). Thus, during the time\nperiod of about 100 jisec between t1 and t2, a NAND cell\ncharging operation associated with memory transistors ~\nwhich are programmed to logic \"0\" data is carried out.\nTurning to FIG. 11, the time duration between ~ and ~,\ni.e. the period of about 2 msec is a petiod~perform\nsubstantial programming. At time ~, the signal SLE goes to\n\"lf'leveland,ascanbesecninFlG.8c,$3goesfrom\"H\" ~\nlevel to \"L\" level while $3 goes from \"L\" level to \"H\" level.\nThus, transistors 144 of FIG. 5 are turned on, thereby\ncausing all of second gate lines SGLI-2 to be connected with\nthe reference potential. Thus, all of second selection tran-\nsistors ST2 in the selected memory block BKI are turned\noff. During this period, the program voltage V,, of about\nvolts is applied on the word line WL4 in selected\nmemory block BKI, and source, drain and channel of the\nmemory transistor 240 are applied to 0 volts. Thus, the\nfloating gate of the transistor 240 is accumulated with\nelectrons by the F-N tunneling, thereby causing the transis-\ntor 240 to be changed into an enhancement mode transistor\nhaving a threshold voltage of about 0.8 volts. However,\nsince junction capacitors of sources and drains of memory\ntransistors excepting the transistor 240 and their channels\nare charged to the program inhibition voltage V,,, injection\nof electrons into floating gates of these transistors is inhib-\nited and these transistors remain as depletion mode transis-\ntors storing logic \"0\" daIs. That is, NAND cells associated\nwith memory cells which are programmed to logic \"0\" data\nare blocked from connection to corresponding bit lines by\nthe above-mentioned NAND cell charging, thereby being\nprevented from writing.\nAs discussed above, the voltage relationship of significant\nportions during the NAND cell charging and the program- ~\nming operation can be summarized in the following TABLE\n.\n\nTABLE 2\n\n\n%bkagr Stses\n\nVokage Soces\n\nDuring NAND CeO\n\nDuring Fl~.gr~iimng\n\nQz~ng Paiod\n\nPrrtod\n\n\nRrstSekciionL~\n\nSV\n\nSV\n\n$11 Of Selea~ed\n\n\n\nMemOry Block\n\n\n\nU~~'-4W,~d\nUric, Of Seiccied\n\nV,= by\n\nV,... by\n\nMemory Block\n\n\n\nSe1ecicdV,~~dl.\ufffd\nV,,..~18V\n\nV1,,..18V\n\nOf Selected Meiii.\n\n\n\nory Block\n\n\n\nSccoadSclmct~s\nUse mi O( ~-\n\nV,_=IOV\n\nOV\n\ned Memory I~\n\n\n\nCc,iwicnS~\nLine ~L\n\nV,1=7V\n\nV,~=7V\n\nWeflniectrods\n\nOV\n\nOV\n\nThe time period between 13 and t5. i.e. the period of 500\nnsec, is a period to discharge the boosted voltage on the bit\nlines and the word lines. At time t3, control signals W'~ and\nP~M and the line DCB go to \"If' levels, aix! control signals\n~EK and DS, voltages V,,,,.,, V,,,.1. and V,,~ and the line SBL\ngo to \"L\" levels of 0 volta. The clock 42 stops pulsing to be\nfixed at \"IF' level at the time t~. On the other hind, during\nthis period, 4, mriintnine \"H\" level and $2 and $3 maintain\n\"L\" levels. Thus, the source line driving circuit 22 outputs\nthe reference potential on the common source line CSL\nControl gate lines CGL1 to CGL8 of FIG. 6 go to a potential\nof 0 volts, and block selection control lines ESC1 to\nSC1024 of FiG. 5 go to a potential of 5 volts. This results\nin causing all word lines to be discharged to the reference\n~~entia1. At time 14. Xd goes to \"L\" level and ~tK and\nDS go to \"H\" levels. Thus, during the time period between\nand ~, block selection control lines BSCi and first and\nsecond selection gate line.s SGU-1 and SGLI-2 go to the\nreference potential. On the other hand, since the line DCB\nand the signal 4, are at \"H\" levels during the time period\nbetween t~ and ~, the boosted voltages on the bit lines are\ndischarged to the reference potential via transistors 37. At\ntime t5, the signal 4, goes to \"L\" level.\nProgramming Verification Mode\nThe programming verification mode is performed imme-\ndiately after the programming mode. The programming\nverification operation of the present invention is similar to\nthe reading operation as will be discussed later. The differ-\nence as compared with the reading operation is that the\nvoltage applied to a selected word line is a minimum\nthreshold voltage which is to be written into memory\ntransistors. This minimum threshold voltage will be referred\nto as a programming verification voltage. It is assumed that\nthe programming verification voltage is 0.8 volts in the\npresent embodiment.\nThe programming verification operation is carried out\nimmediately after time 13 in FIG. II, and a Liming chart of\nthe programming verification operation is of the time period\nbetween t~ and t4 as shown in FIG. ii At the initiation of\nthe programming verification, i.e. at time 13 of FIG. U or\ntime 12 of FIG. 12, control signals X~, $3and $4 go to \"H\"\nlevels and signals $,, PVP and SUP and the line DCB go to\n\"L\" levels. Thus, during the programming verification\noperation, control signals W~, P~M, SEE, Xi!, ~LK, ~,\n$3 and 42 and the clock 42 maintain \"IF' levels, and\nvoltages V,,,,,,1 ~and V,~lines SBL and DCB and control\nsignals 4,, $3, PVF and SUP mnintain \"L\" levels.\nit is now assumed that the progranuning verification\noperation is performed to determine if a memory transistor\nof FIG. 2a which was written to a logic \"1\" data in the\n~\ufffd previous programming mode was programmed with a\ndesired minimum threshold voltage.\nWhere a command for executing a programming verifi-\ncation after completion of programming operation is input to\nEUPROM from the microprocessor via input/output tenth-\noils or otl~ terminals or where a programming verification\noperation is automatically carried out alter a programming\noperation, data stored into latches PBk-1 to PBk-256 in the\nprogramming operation is succeeded without reset by the\nso programming verification operation. Thus, at the beginning\nof the programming verification operation, the latch PBi-2\nis storing logic \"0\" data and the remaining latches are storing\nlogic `1\" data.\nAt time 13 of FIG. 12, the control signal X~ goes to \"H'\n~ level and the decoder 120 of FIG. 5 then outputs \"L\" level\nin response to address signals Pt, Ql and RI designating the\nmemory block BK1. Then, since $6 and $3 respectively\n~~*\"H' level and \"L\" level, first and second selection\nlines SGL1-1 and SGL1-2 and the block selection control\n~ line BSC1 go to \"H\" levels of 5 volts.\nAt time ~` the control signal PVF goes to \"L\" level and\naddress signals A5/~ to A,~,/X designating the word line\nWIA are fed to the decoder 154 of FIG. 6. Then, NAND gate\nbecomes of high impedance and the verifying voltage\nas generator 164 provides the verifying voltage of 0.8 volts on\nthe control gate line CGL4. However, each decoder 154\nassociated with unselected word lines WL1 to WL3 and\n\nCase 9:02-cv-0005$RJH Document 20 F~ed 04/03/2002 Page 48 of 127\n,473,563\nWLS to WLI ci~put \"H\" levels. Then, the verifying voltage\ngenerator 164 becomes high impedance and NAND gate 158\noutputs \"H\" level. Thus, control gate lines CGLI to CGL3\nand CGLS to COL8 go to \"If' level of 5 volts. On the other\nhand, since P~M maintains \"IF' level at 13, the source line\ndriving circuit 22 of FIG. 7 provides the reference potential\non the common selection line CSL.\nConsequently, the transfer transistor array 34-1 of FIG. 2a\nis conductive and the ~rst and second selection lines SL1\nand SL2 and unselected word lines WL1 to WL3 and WLS\nto WLS go to the potential of 5 volts while the selected word\nline WL4 goes to the potential of 0.8 volts. Thus, transistors\nconnected with the selection lines SL1 and SL2 and the\nunselected word lines me turned on.\nAt time t2, the control signal $3 goes to \"H\" level, thereby\ncausing the constant current circuit 33 of FIG. 2b to be\nenabled. Thus, the constant current transistors 54 supply\nconstant current of about 4 ~iA to bit lines via connecting\nnodes 36 and transistors 40 and 38.\nAssume that the programmed memory transistor 240 has 20\nfailed to program, i.e. the threshold voltage of the transistor\nwas below the program verifying voltage of 0.8 volts.\nThen, the transistor 240 is turned on and the bit line BLI-2\nconnected thereto goes to the reference potential of 0 volts.\nSince all transistors of NAND cells in the memory block ~\nBK1 which are connected with bit lines excluding the bit\nline BL1-2 are turned on, the bit lines also go to the\nreference potentiaL The period of time when word lines\nWL1 to WL8 and bit lines arc established to the predeter-\nmined voltages in such a Trtanr~r is a period of about 2 j~sec ~\nbetween t2 and t3 of FIG. 12.\nThe time period between ~ and t4 of FIG. 12, i.e. the\nperiod of about 500 nsec, is for verification sensing. The\ncontrol signal $3 goes to \"H\" level at time 1,, and transistors\nof FIG. 2b are thereby turned on. The transistor 50 whose 35\ngate is connected with the bit line BL1-2 via transistors 38\nand 40 is turned off by the reference potential on the bit line\nBL1-2, thereby causing the latch PBI-2 to maintain logic\n\"0\" data. Similarly, since other bit lines are also at the\nreference potential, transistors 50 associated with these bit 40\nlines are turned off and latches excepting the latch PB1.2\nthereby maintain previously stored logic \"1\" data. Verifica-\ntion sensing data stored in the latches PBk-1 to PBk-256 by\nthe above-mentioned verification sensing operation is con-\nnected to gates of transistors 212 to 216 of FIG. 9a via 45\nturned-on inverters 48 aix! lines 70. Thus, the `V level\nverification sensing data stored in the latch P31-2 is sup-\nplied via corresponding inverter 48 to the gate of transistor\nwhich constitutes NOR gate 234 of FIG. 9a associated\nwith the first column block CB1, thereby rendering the 50\ntransistor 214 cooductive and causing the line 210 to be\ndischarged * ~ reference potentiaL Consequently, since\nthe signal ~poes to \"L\" level oniy when the programming\nverification is checked, FF1 goes to \"L\" level. However,\nsince latches in other column blocks CB2 to CB8 store \"H\" 55\nlevels, transistors 212 to 216 of NOR gate 234 correspond-\ning to each one of the blocks CB2 to CB8 am in noncon-\nductive states. Thus, each line 210 maintains \"H\" level by\nmeans of pull-up transistors 218 and 220 and FF2 to FF8\nthereby stay at \"H\" levels. Thus, the output line 232 of the 60\nsummation circuit 236 of FIG. 9b goes from \"H\" level to \"U'\nlevel. This represents that the memory transistor 240 was\nundesirably programmed. That is, it is checked that the\nthreshold voltage of the memory transistor 240 did ont reach\nat a preset minin,iim threshold voltage. A program determi- as\nnation signal PDS on the line 232 is connected to a timing\ncircuit (not shown) which generates timing signals between\nt, and 13 as shown in FIG. II so as to perform a reprogram-\nming in response to the signal PDS being at \"L\" level. That\nis, reprogramming operation is automatically performed. it\nwould be noted that the reprogramming operation of the\n~ present embodiment may automatically be performed by the\ninternal circuit of the present EEPROM without request of\neither reprogramming control or reloading of data from a\nmicroprocessor. However, if necessary, the microprocessor\nmay control the reprogramming operation in response to the\nsignal PDS from one of the input/output terminals of the\npresent EEPROM chip.\nAssuming that the memory transistor 240 reached the\ndesired threshold voltage of 0.8 volts by the reprogramming\noperation, then the transistor 240 is in a nonconducnve state\n~ during the programming verification operation performed\nalter the reprogramming operation. Thus, the bit line BL1-2\nis charged to the potential of about 2 to 3 volta by the\nconstant current supplied via the constant current transistor\n, thereby rendering conductive the transistor 50 connected\nwith the bit line BL1-2. Consequently, the verification\nsensing data of latch P81-2 is changed from logic \"0\" data\nto logic \"I\" data. As previously discussed, other latches are\nstoring logic \"1\" verificmion sensing data. Thus, all of the\nlatches P3k-I to PBk-256 store logic \"I\" verification sens-\ning data That is, if all memory transistors were well\nprogrammed in the page programming operation, verifica-\ntion sensing data stored in the latches is changed into logic\n\"1\". Then, transistors 212 to 216 constituting NOR gates 234\nof FIG. 9a are all turned off, and signals FF1 to FF8 go to\n\"IF' levels with the signal SPP at \"L\" level during the check\nof programming verification. Consequently, the siimmsrion\ncircuit 236 of FIG. 9b outputs the program determination\nsignal PDS, which is at \"H\" leveL This represents that the\nprogramming operation had successfully been performed.\nNow assume that some of memory transistors pro-\ngrammed with logic \"1\" had successfully been programmed\nand the remainder had unsuccessfully been prograinxneii\nThen, during the followed programming verification opera-\ntion, latches corresponding to the former memory transistors\nare changed so as to store logic \"1\" data, while latches\ncorresponding to the latter memory transistors maintain\nlogic \"0\" data. Since latches in the former case are storing\nlogic \"1\" data, their corresponding bit lines are charged to\nthe potential of 5 volts during the followed reprogramming\noperation. However, in the same manner as the above-\nmentioned programming operation, since, in the reprogram-\nming operation, a selected first selection line stays at 5 volts\nand junctions of sources and drains of memory transistors\nand their channels are charged to the program inhibition\nvoltage of 7 volts, first transistors connected with the\ncharged bit lines on the selected first selection line are in\nnonconductive statea Thus, during the reprogramming\noperation, the successfully programmed memory transistors\nare prevented from programming by the charged program\ninhibition voltages. However, in the case of the latter, i.e. the\nunsuccessfully programmed memory transistors, since their\ncorresponding latches are storing logic \"0\" data, reprogram-\nming is performed only on them. With such repeating\noperations, if all memory transistors on a selected word line\nwhich are programmed with logic \"I\" data was successfully\nprogrammed, the program determination signal PDS outputs\n\"If' level during the above-mentioned programming verifi-\ncation operation, and the reprogramming operation is ter-\nminated. The present circuit used in the above-mentioned\nprogramming verification operation may also be applied to\nEEPROMs with NOR-type memory arrays.\n\nThe programming verification techniques as discussed\n\nCase 9:02-cv-O0Q5$~.jH\n\nDocument 20 F~ed 04/03./2e02 Page 49 of 127\n,473,563\nabove have v~ions advantages as followa. First, the pro-\ngramming verification operation can automatically carried\nout by the internal circuit without the control of an external\nmicroprocessor. Second, since the data register is used as\ndata latches in a data loading mode, verification sensing ~\ncircuits in a programming venfication mode and sense\namplifiers in a reading mode, as will be discussed herein-\nbelow. simplification of peripheral circuits may be accom-\nplished. Third, the threshold voltages of programmed\nmemory transistors may be tightly distributed within a\nnarrow range above a preset minimum threshold voltage,\nand over-programming may be prevented. The tight distri-\nbution of threshold voltages can be accomplished by the\nexecution of the programming operation within a shorter\nperiod, since successfully programmed memory transistors\nare automatically inhibited from programming due to the\nchanged data of their corresponding latches.\nReading Mode\nFIG. 12 illustrates a timing chart of the reading operation\naccording to the present embodiment. 20\nThe time period between t1 and t2 in the drawing is a\nperiod to discharge word lines WL1 to WL8 and all bit lines\nBLk-l to ELk-256 to the reference potential and to reset so\nthat latches PBk-1 to PBk-256 stores logic \"0\" data. During\nthis period, the control signal $~ and lines SBL and DCB\nstay ax \"if' levels. Thus, bit lines ELk-i to BLk-256 are\ndischarged to the reference potential via the transistor 37 of\nFIG. 2b, and latches PBk-1 to PBk-256 are reset to logic \"if'\ndata by the conduction of transistors 37 and 44. During the\ndine period between t and ~ dining chart of control\nsignals W~, PGM, St~ ~ llLI~, ~ and ~X, the clock\n$~ and and voltages V,~,,, V~, and V,,~ is identical to the\ntiming chart between t3 and t5 shown in FIG. 11. Control\nsignals PVP and ~ keep \"H\" levels during operations\nexcepting the programming verification operation.\nThe dine period between t2 and t4 is a period for sensing\ndata read out from memory cells and storing the sensing data\ninto latches PBk-1 to PBk-256. During the period, W~,\nP~M, 511, X~, ~ ~, ~X $~, +4 and $~ maintain \"H\"\nlevels, and Vp,m, V,,~,.,, V~, lines SBL and DCB, $~ and 4~\nkeep \"L\" levels.\nAn explanation will now be given, assuming that a\nreading operation is performed from memory transistors\nconnected to the word line WL4 in the memory block BK1\nwhich was page programmed in the above-mentioned pro-\ngramming mode.\nOperation between \ufffd2 and t3 is performed in a similar\nmanner as the verification operation as discussed above.\nThus, an apI~iadon will be given in brief. The block\nselection ~t of FIG. S associated with the selected\nmemory basis BKI makes first and second selection gate\nlines SGL1-1 SGLI-2 and the block selection control\nlines BSC1 ~ld at 5 volts in response to address signals Pt,\nQl and Ri addressing the block BKL Since the control signal\nPVF is at \"H\" level, the verifying voltage generator 164 of\nFIG. 6 is in a high impedance state and the NAND gate 15$\nis being enabled. Thus, the control gate line CGL4 corre-\nsponding to the selected word line WL4 is at the reference\npotential of 0 volts in response to address signals A8/A to\nA,0/X designating the word line WL4. However, control\ngate lines CGL1 to CGL3 and CGLS to CGLX correspond-\ning to unselected word lines WL1 to WL3 and WL5 to WLS\nare at \"H\" levels of 5 volts. On the other hand, the source\nline driving circuit 22 of FIG. 7 outputs the reference\npotential on the common source line CSL. Consequently, the\ntransfer transistor array 34-1 of FIG. 2a is conductive, and\n\n\n\nfirst and second selection lines SL1 and SL2 and unselected\nword lines WL1 to WL3 and WL5 to WL8 in the block BK1\nare thereby at 5 volts while the selected word line WL4\ntherein is at 0 volts.\nThe control signal ~ goes to \"H\" levels at time 12, thereby\ncausing the current source circuit 33 to be enabled. Thus, the\nconstant current transistors 54 supply the current of about 4\njA onto bit lines BLk-l to BLk-256 via connecting nodes 36\nand transistors 40 and 38. Since only the memory transistor\nis programmed with logic \"1\", the bit line RL1-2 is\ncharged to about 2 to 3 volts and the remaining bit lines\nbecomes 0 volts. At time t3 of FIG. 12, the control signal ~\ngoes to \"H\" level, thereby rendering transistors 52 of FIG.\nb conductive. Then, only the transistor 50 associated with\nthe bit fine BL1-2 is turned on. thereby making the latch\nPB1-2 sense and store the logic \"1\". However, remaining\nlatches continuously store logic \"0\" based on the previously\nmentioned reset operation since transistors 50 are turned off.\nThat is, page reading is accomplished. Data stored in the\nlatches PBk-1 to PBk-2S6 is output to input/output terminals\n/01 to 1/08 by a byte (8 bits) via inverters 48, transfer\ntransistors Ti to T256 turned on in sequence in response to\ncohunn address of 256 cycles and toggles of W~ and\noutput buffer 2&\nModified Embodiments\nThe EEPROM of the first embodiment explained in\nconnection with FIG. 1 to FIG. 12 comprises the memory\narray including 1024 memory blocks each of which has\nNAND cells arranged in the same rows, and a source line\ndriving circuit for generating the program inhibition voltage\nprior to the programming or reprogramming operation in\norder to charge it to the NAND cells. However, it should be\nnoted that the present invention is not limited to such an\nembodiment. For example, the memory array used in other\nembodiments of the present invention may be comprised of\nmemory blocks having shared word lines as discussed\nhereinafter. To charge the program inhibition voltage to\nNAND cell, a capacitive coupling way from control gates\nmay be applied with no use of the source line driving circuit.\nThis modified embodiment is illustrated in FIG. 13 to FIG.\n.\nFIG. 13 consists of FIG. 13a and FIG. 2b. FIG. 13a shows\na memory array composed of memory blocks having shared\nword lines, and FIG. 2b shows the ahesdy discussed periph-\neral circuit connected with the memory array of FIG. 13a.\nFor simplification of the drawing, FIG. 13a shows only\nthe arrangement of memory cells and shared word lines\nwhich are associated with the k-th column block in the i-th\nmemory block SBKi. However, it should be noted that a\nmemory array 10 having memory cells of 16 mega bits as\nshown in FIG. 13a is arranged in the same manna as the\nmemory array of FIG. 2a excepting the shared word lines.\nReferring to FIG. 13a, each of memory blocks SI~Ki (i =1,\ns 2, 3 512) is comprised of two submemory blocks, Le.\nan upper memory block or a first submemory block USBKI\nand a lower memory block or a second subrnemocy block\nLSBKI. Each of the upper and lower memory blocks USBKi\nand LSBKi has the same configuration as each of memory\nso blocks of FIG. 2a. Wordlines WL1 to WL8 inthe upper\nmemory block USBKi are correspondingly connected with\nword lines WLI to WL8 in the lower memory block LSBKi.\nThat is, the upper memory block USBKi shares the word\nlines WL1 to WLS with the lower memory block LSBKI.\n~ The word lines WL1 to WLS are respectively connected\nto control gate lines CGLI to CGL8 via current paths of\ntransfer transistors BT2 to BT9. A first upper selection line\nCase 9:02-cv-0005~JH Document 20 F~ed 04/03/2002 Page 50 of 127\n,473,563\nUSL1 and a fiat lower selection line LSL1 are connected to\nupper and lower selection gale lines USGU and LSGU via\ncurrent paths of transfer transistors BT1 and BTII, respec-\ntively. Second upper and a second lower selection lines\nIJSL2 and LSL2 are connected to upper and lower ground s\nselection lines UGSL and LGSL via current paths of transfer\ntransistors BTIO and BTI2, respectively. Sources of second\nupper and lower selection transistors UST2 and LST2 are\nconnected to a common source line CSL which is connected\nto the reference potential, i.e., the ground. Drains of first ~\nupper and lower selection transistors UST1 and LST1 are\nrespectively connected to corresponding bit lines.\nThe control gate lines CGL1 to CGL8 are connected to the\ncontrol gaze driving circuit 20 explained in connection with\nFIG. 6. Upper and Lower selection gaze lines USGLi and ~\nLSGLi are respectively connected to corresponding block\nselection control circuits 318 of FIG. 14. Each of block\nselection control circuits 318 serves to select one of upper\nand lower memory blocks in a selected memory block\ndesignated by address according to respective operation ~\nmodes. It should be noted that the block selection control\ncircuits 318 corresponding to the respective memory blocks\nSBKi are provided on the substrate of on-chip EEPROM.\nThus, it would be appreciated that two memory blocks\nsubstantially share one block selection control circuit since\neach block selection control circuit controls one memory\nblock comprised of upper and lower memory blocks. This\nresults in relatively increasing the area of memory array on\nthe chip substrate of fixed size so as to increase the memory\nstorage capacity since the chip occupying area of the periph-\neral circuit is decreased. 30\nThe upper ground selection line UGSL and the lower\nground selection line LGSL are connected to a ground line\ndriving circuit 320 illustrated in FIG. 15. The ground line\ndriving circuit 320 is a circuit connected in common with\nupper ground selection lines UGSL and lower ground selec- ~s\ntion lines LGSL in memory block SBK1. The ground line\ndriving circuit 320 serves to provide proper voltages onto\nthe upper and lower ground selection lines UGSL and LGSL\naccording to the respective operation modes.\nReferring to FIG. 14 showing the block selection control 40\ncircuit which controls the i-th memory block SBKi, a\ndecoder 322 receives address signals P1, QI and Ri and the\ncontrol signal xa The address signals P1, Qi and RI are\nsignals predecoded by address signals A1~ to A,~Th of\nrow address signals A1 1/A7 to A~X from address buffer ~5\n(not shown). The row address signal A11/~ is input to a\ntiming circuit (not shown) in order to generate control\nsignals A11,,, X~, A112, ~ A111, 7~ for selecting one of\neither the upper me~ry block USBKI or the lower memory\nblock LSBIG ~ding to the respective operation modes. ~\nLogic stares d~se control signals according to the respec-\ntive operads. ~des am given hr the following TABLE 3.\nWherein \"W re\ufffdsents \"H\" level of 5 volts and \"L\"\nrepresents 1..\" level of 0 volts.\n\n\n\nTABLE 3\n\n\n\n\nUpp~ Mc~y\nBtock Sctecthm\nA11=H\n\n\n~- -\nBlock Selcc*ion\nA11=L\n\nEsas-\nang\nMode\n\nRe~nL\nProgriinnieg\nAnd Pro~oing\n%~ificano~ Mode\n\nEru-\nrng\nMode\n\nRasthug.\n~\nAnd Progoamxidng\n`*oibcaliott Mode\n\n\n\n\nUpp~ Mmxry\nBlock Selocaon\nA~1=H\n\n\nLo~ Mc~y\nBlock Selecdei,\nA,,=L\n\nEr~-\niog\nMode\n\n~L\nProgrinarang\nAnd Pxogrlnming\nVertfication Mode\n\nErao-\ntog\nMode\n\nProgranatng\nAnd Progr,mtning\nVaific~io11 Mode\n\nL\nL\nX~ H\n\nL\nH\nL\n\nL\nL\nH\n\nH\nL\nH\n\nThe output of the decoder 322 is connected to one input\nterminal of NAND gate 324 and sri input terminal of an\ninverter 326. The other input terminal of NAND gate 324 is\nconnected to the erase control signal ~X The output of the\nNAND gate 324 is connected to the upper selection gaze line\nUSGU via a CMOS transfer gaze 328, which consists of\nn-channel transistor 350 and p-channel transistor 352, and\nthe current path of D-type transistor 330. Between a con-\nnecting node 358 and the reference potential is connected\nthe current path of n-channel transistor 332. Gates of\nN-channel transistors 350 and 332, p-channel transistor 352\nand D-type transistor 330 are connected to control signals\nA11,,, X~, A~ and W~, respectively. The control signal\nWE is at \"1,\" level during the block erasing operation and\nis at \"H\" level during remaining operations. The output of\nthe NAND gaze 324 is also connected to the lower selection\ngate line LSGL1 via a CMOS transfer gale 334, which\nconsists of n-channel transistor 354 and p-channel transistor\n, and the current path of D-type transistor 336. The\ncurrent path of n-channel transistor 338 is connected\nbetween a connecting node 360 and the reference potential.\nGates of n-channel transistors 354 and 338, p-channel tran-\nsistor 356 and D-type transistor 336 are connected to control\nsignals ~ A1~, A112 and W~, respectively. The output of\nthe inverter 326 is connected to the block selection control\nline BSCi via current paths of D-type transistor 340 and\nn-channel transistor 342, which are connected in parallel,\nand the current path of D-type transistor 344. The gate of the\nD-type transistor 340 is connected to the output of the\ndecoder 322, and gates of the n-channel transistor 342 and\nthe D-typc transistor 344 arc connected to the power supply\npotential Vcc of 5 volts. Two input terminals of NOR gale\nare connected to the clock 4R and the output of the\ndecoder 322, respectively. Between the output of the NOR\ngate 346 and the line BSCi is connected a charge pump\ncircuit 348.\nIf address signals selecting the memory block SBKi input\nto the block selection control circuit 318, the block selection\ncontrol line BSCI is at a potential of about 4.3 volts in\nerasing, programming verification and reading modes, and is\nat the program voltage V,,,., of 18 volts in a programming\nmode. On the contrary, the block selection control line of\nrespective ones of block selection control circuits associated\nwith unselected memory blocks is at the reference potential\nof 0 volts in all modes.\nso If the memory block SBKi is designated by the address\nsignal and the address signal A11 is at \"H\" level, the upper\nselection gate line USGL1 is at a potential of 5 volts in a\nprogramming, a programming verification and a reading\nmodes, and the lower selection gate line LSGU is at a\nas potetialof0voltsbycontiOflofth~fl5iStor33Sm\nsaid modes. Similarly, if the memory block SBKi is\naddressed by the address signal and the address signal A11\nTABLE 3-continued\nA H H H\nI L L\nA~11 L H L\n\nL\nH\n\nL\n\nCase 9:02-cv-0005S-JH Document 20 F~ed 04/03/2002 Page 51 of 127\n,473,563\nis at \"L\" level, the lower selection gate line LSGU is at a\npotential of 5 %V113 in programming, programming vedflca-\ntion and reading modes, and the upper selection gate line\nUSGLI is it * potential of 0 volts by conduction of the\ntransistor 332 in said modes. On the other hand., upper and ~\nlower selection gaze lines USGU and LSGL1 are both in\nfloating staxet of about 2 to 3 volts in a block erasing mode.\nRefernng to FIG. 15, the ground line driving circuit 320\nis comprised of inverters 362 to 374 and NOR gazes 376 and\n. The driving circuit 320 outputs 0 volts onto upper and\nlower ground selection lines UGSL and LGSL in a program-\nming mode. If the upper memory block is selected in rending\nand programming verification modes, the upper ground\nselection line UGSL goes to \"H\" level of 5 volts, and the\nlower ground selection line LGSL goes to \"L\" level of 0\nvolts. However, if the lower memory block is selected in\nreading and programming verification modes, the lower\nground selection line LGSL goes to \"H\" level of 5 volts, and\nthe upper ground selection line UGSL goes to \"I]' levels of\nvolts. On the other band, upper and lower ground selection\nlines UGSL and LGSL go to \"H\" levels of 5 volts in a block\nerasing mode.\nbetween t~ and t3, since the selected block selection control\nline is at the potential of about 4.3 volts, and upper and lower\nselection gate lines USGLI and LSGLi are at about 2 to 3\nvolts, and upper and lower ground selection lines UGSL and\nLGSL are at 5 volts, the first upper and lower selection lines\nUSL1 and LSL1 associated with the selected memory block\nare ax about 2 to 3 volts and the second upper and lower\nselection lines USL2 and LSL2 associated with the selected\nmemory block are in floating states. Thus, when any one of\nthe second upper and lower transistors connected with the\nsecond upper and lower selection lines fails, the flow of\nleakage current is prevented via the second upper and lower\nselection lines USL2 and LSL2 from the well electrode 114.\nDuring the block erasing operation, the voltage relationship\nof significant portions may be summarized in the following\n~5 TABLE 4.\n\n\nOperations of the modified embodiment are almost the\nsame as those of the first embodiment, excepting operation\nto select either upper or lower memory block and operation\nto charge NAND cells by way of a capacitive coupling 2~\ntechnique in a programming operation. Thus, a brief expla-\nnation of operation of the modified embodiment will be\ngiven, referring to the accompanying timing charts.\nFIG. 16 shows a timing chart of the block erasing mode.\nIn the drawing, the time period between t1 and t2 is for\ndischarging all word lines in the memory array 10 to the\nreference potential of 0 volts. In this period, control gate\nlines CGL1 to CGIJ are at the reference potential as\ndiscussed in connection with FIG. 6. During this period,\n~tK maintains \"L\" level, and the predecoder (not shown)\ngenerates address signals P1, Ql and RI being at \"H\" levels\nin response to the signal ~1X Thus, the decoder of FIG. 14\noutputs \"L\" leveL Consequently, block selection control\nlines BSCI to BSCSI2 are all at the potential of about 4.3\nvolts, and transfer transistors BT2 to BT9 of transfer tran-\nsistor arrays 34-1 to 34-512 of FIG. L3a are all turned on,\nthereby grounding all word limes.\nThe time period between t2 and t, of FIG. 16 is for erasing\na selected memory block. During tin period. control gate\nlines CGL1 to CGLS remain the reference potential identical\nto the case between t1 to t2. The block selection control\ncircuit 318 of FIG. 14 associated with the selected memory\nblock outputs the potential of about 4.3 volts onto a selected\nblock ~a4~c~nn control line, however, the block selection ~\ncontrol c\ufffdassociated with unselected memory blocks\noutput tin ~usce potential onto unselected block selec-\ntion control lInes. Thus, word lines of upper and lower\nmemory blocks in the selected memory block at time t2 are\nall at the reference potential, and all of word lines in ~\nunselected memory block are in floating states. However,\nsince the erase voltage V,,.,, of 20 volts is applied to the well\nelectrode 114 of FIG. 4 at time t2, all word lines in the\nunselected memory blocks are capacitively coupled to about\nvolts, and data of memory transistors in the unselected so\nmemory blocks is not erased. However, during the time\nperiod between t2 and t3, every memory transistor in the\nselected memory block is changed into a D-type transistor\nhaving a threshold voltage of about -2 to -3 volts by the\nerase voltage which is applied between its channel and as\ncontrol gate. That is, logic \"0\" data is stored.\nOn the other hand, during the block erasing period\nTABLE 4\n\n\n\nSelected Memoty\n\nUu~elocted Men~y\n\n\nBlock\n\nBlock\n\nHEit Upper And Lower\n\nAplxox\ufffdy\n\nHalting\n\nSelection Li~s USL1\n.-3 V\n\n\nAnd LSL1\n\n\n\nWord Lieca WLI to\nV\n\nA~tpeoxixn~cly 20 V\n\nw~\n\n\n\nSe~d Upper And\n\nFloating\n\nHosting\n\nLower Selection Lines\n\n\n\nUSLZ And LSL2\n\n\n\nWellElectrode\nV\nV\nThe time period between t3 and t4 of FIG. 16 is for\ndischarging word lines in unselected memory blocks to the\nreference potential. During this period. control gate lines\nCGL1 to CGL8 maintain the reference potential by the\ncontrol signal 1~ as previously discussed in connection with\n~ FIG. 6. The control signal ~LI~ maintains all block selection\ncontrol lines BSC1 to BSC512 to about 4.3 volts, thereby\ncausing all word lines to be discharged to the reference\npotential. Upper and lower gate lines UGLi and LSGLi are\nalso maintained to the reference potential by X~. On the\n~ other hand, the line DCB being at \"If' level causes bit lines\nto be discharged to the reference potential.\nFIG. 17 shows a liming chart of the programming mode\nof the modified enlbOdimenL Referring to FIG. 17, the data\nloading operation is performed prior to time t1. The data\nloading operation is performed in the same manner as that of\nthe first embodiment as discussed in connection with FIG.\nb. The time period between t1 and t2 is for writing data into\nselected memory transistors. As discussed in the data load-\ning operation of the first embodiment, bit lines correspond-\ning to memory transistors into which logic \"I\" data is\nwritten are at \"L\" level of 0 volts while bit lines correspond-\ning to memory transistors into which logic \"0\" data is\nwritten are at \"H\" levels of 5 volts. After the time t1, the\nselected control gate line goes to the program voltage V,,,,,,\nof 18 volts, and unselected control gate lines go to the pass\nvoltage V~ of 10 volts as previously discussed in connec-\ntion with FIG. 6. It is now assumed that the fourth control\ngaze line CGL4 was designated by address signals. Then, the\ncontrol gate line CGL4 goes to the program voltage V,,,,, of\nvolts and control gate lines CGL1 to CGL3 and COL5 to\nCGU go to the pass voltage V,,,, of 10 volts. It is also\nassumed that the third memory block was designated by\naddress signal and the address signal A11 was \"If' level.\nThen, the decoder 322 of FIG. 14 outputs \"L\" level and the\nblock selection control line BSC3 goes to the program\nvoltage V,,,,, of 18 volts after the time t1. At this time, the\nupper selection gate line USGL3 goes to the potential of 5\n\nCase 9:02-cv-0005~JH Document 20 F~ed 04/03/2002 Page 52 of 127\n,473,563\nvolts and the lower selection gate line LSGL3 goes to the\nreference poteadaL Thus, the transfer transistor array 34-3\nof FIG. 13a ii turned urn. On the other band, the ground line\ndriving circuit 320 of FIG. 15 provides the reference poten.\ntial onto the lines UGSL and LGSL during the programming 5\nperiod. Thus, the second upper and lower selection transis-\ntors UST2 and LST2 in the upper and lower memory blocks\nUSBK3 and LSBK3 are all nonconduclive. The first lower\nselection line LSL1 in the lower memory block LSBK3 also\ngoes to the reference voltage via the transfer transistor BT1I,\nthereby causing the first lower selection transistors LST1 to\nbe turned off. However, the first upper selection line USL1\nin the upper memory block USBK3 goes to \"H\" level of 5\nvolts via the transfer transistor BT1. During the above-\nmentioned programming operation, the voltage relationship\nof significant portions may be summarized in the following\nTABLE 5.\n\n\nSe\n\nlected M~esxy Block\n\nUnselected Lower\n\n\nSelected Upper\n\n\nMen~y Block\n\nMensxy Block\n\nSclectedFfrstUpper\nSelected Line USL1\nV\n\n-\n\nUnselected Firtt Lower\n\n-\nV\n\nSelected Line LSL1\n\n\n\nSelected Wood Line\nUnselected Wned Line\nSelected Second Upper\nSelection Line USL2\nUnselected Second Lower\n\nV,_,, ,,~\nV,,.. - ~o\nV\n\n-\n\nVs,,,,, - iv\nV~... ~,,\n-\nV\n\nSelection Une LSL2\n\n\n\nWeflElecitode\n\nOV\n\nOV\n\nThus, during the programming operation, the high voltage\napplied onto word lines WL1 to WL8 causes the NAND cell\ncharging of upper and lower memory blocks USBK3 and\nLSBK3. Thus, since the first upper selection line USL1 is at\nthe potential of 5 volts, and bit lines associated with memory\ntransistors into which logic \"0\" data is written are at 5 volts\nwhile bit lines associated with memory transistors into\nwhich logic \"1\" data is written are at the reference potential\nof 0 volts, first upper selection transistors in the upper\nmemory block USBK3 which are connected with the latter\nmemory transistors are turned on. and first upper selection\ntransistors in the memory block USBK3 which are con-\nnected with the former memory transistors axe turned off.\nThus, sources, drilus and channels of memory transistors in\nNAND cells associated with the former memory transistors\ngo to the r,4~iw~ potential, and NAND cells associated\nwith the l~ssr ~y transistors are charged to a high\nvoltage. C--i~--~ly, during the programming period,\nfloating gates ~ the former memory transistors connected\nwith the upper word line WL4 accumulate electrons by way\nof the F-N timneling, tl~thy changing into enhancement\ntransistors having a thieshold voltage of about 0.8 volts.\nThat is, logic \"I\" data is stored. However, since channels of\nthe latter memory transistors and junction capacitors of their\nsources and drains are charged with a high voltage, the\nprogramming of these memory transistors is prevented, so\nIn the same manner, the first lower selection line LSL1\nand the second lower selection line LSL2 in the unselected\nlower memory block LSBK3 are at the reference potential,\nand the first and the second lower selection transistors LST1\nand LST2 which axe respectively connected to the lines\nLSL1 and LSL2 are thereby turned off~ Thus, channels of\nmemory transistors of NAND cells in the lower memory\nblock LSBK3 and junction capacitors of their sources and\ndrains are charged with a high Voltage SO as to prevent\nprogramming.\nAt the time t2, the programming operation is terminated\nand the clock SR steps clocking. Thus, the charge pump\ncircuit 348 is disabled and BSC3 thereby falls to the poten-\ntial of S volts. During the time period between t2 and t1, the\ncontrol signal ~ at \"L\" level causes control gaze lines\nCGL1 to CGL8 to be grounded. Thus, word lines in the\nmemory block SBK3 are discharged to the reference poten-\ntial. During the time period between t3 and t4, block selec-\ntion control lines BSC1 to BSCS12 and upper selection gate\nlines USGL1 to USGL512 are discharged to the reference\npotential.\nThe programming verification operation may be per-\nformed from the time t4 of FIG. 17. The programming\nverification operation is similar to that of the first embodi-\nmerit. The difference as compared with the first embodiment\nis in that the present embodiment has the block selection\n~ control circuit for selecting one of either the upper or lower\nmemory block in a selected memory block If the upper\nmemory block USBK1 in a selected memory block is\nselected by means of the block selection control circuit of\nFIG. 14 in the programming verification operation, a\n~ selected block selection control line BSCI goes to the\npotential of about 43 volts, and the upper selection gate line\nUSGLI goes to the potential of 5 volts. Then, the ground line\ndriving circuit 320 of FIG. 15 outputs \"H\" level of 5 volts\nonto the upper selection gate line UGSL and `U' level of 0\n~ volts onto the lower selection gate line LGSL. As discussed\nin connection with the first embodiment with reference to\nFIG. 6, in the programming verification operation, a selected\ncontrol gate line is at the program verifying voltage of 0.8\nvolts and unselected control gaze lines are at the potential of\n~ 5 volts. Thus, the line BSQ of about 4.3 volts connected to\nthe transfer transistor array 34-i of FIG. 13a goes to the\npotential of about 7 volts since the potential of 5 volts on the\nunselected control gate lines is transferred from drains of\ntransfer transistors to their gates by way of capacitive\n~ coupling. This operation is also identical in a reading\noperation. Consequently, a selected word line in the upper\nmemory block USBK1 goes to the verifying voltage of 0.8\nvolts and unselected word lines go to the potential of 5 volts.\nThe first and second upper selection lines USL1 and USL2\n~ also go to the potential of 5 volts. Thus, second selection\ntransistors UST2 in the block USEKi are turned on, thereby\nconnecting NAND cells in the block US~Ki to the grounded\ncommon source line CSL. However, the first and second\nlower selection lines LSL1 and LSL2 in the lower memory\nblock LSBKi are at the reference potential and the block\nLSBKi are at the reference potential and the block LSBKi\nare at the reference potential and the block LSBKI is thereby\nunselected. The following programming verification and\nreprogramming operations are the same as operations\n~ explained in the first embodiment in connection with the\ntinning chart during the time period between t2 and t4 of FIG.\n.\nIn the modified embodiment, programming and repro-\ngramming techniques do not need a program inhibition\nvoltage generator connected with the respective bit lines to\ninhibit programming of logic \"0\" programmed cells and\nreprogramming of successfully logic \"1\" programmed cells.\nThus, the simplification of a peripheral circuit and the\nreduction of on-chip area can be accomplished. Otherwise,\nsince the program inhibition voltage is automatically gen-\ncrated by the capacitive coupling technique during the\nprogramming and reprogramming operations, the program.\nTABLE 5\nCase 9:02-cv-0005S~JH Document 20 F~ed 04/03/2002 Page 53 of 127\n,473,563\nrning and reprogramming operations may be executed at a\nhigh speed. Thus, since the present embodiment employs a\nself.prograrn inhibition technique, the above-mentioned\nadvantages may be accomplished.\nIn the reading operation of the modified embodiment, a 5\nselected word line of 0 volts is used instead of the selected\nword line of 0.8 volts in the above-mentioned programming\nverification operation. Operation to select memory transis-\ntors in the reading operation is the same as that in the\nprogramming verification operation. Page reading, page 10\nread-out sensing and the output from data output terminals\nare also the same as operations explained in the first embodi-\nment in connection with FIG. 12.\nThus, EEPROMs of embodiments of the present inven-\ntion as described above can be designed so as to have ~\ncapabilities and reliability of improved programming, block\nerasing and programming verification. The peripheral cir-\ncuits associated with a reading and a programming verifi-\ncation according to embodiments of the invention can also\nbe used in a nonvolatile semiconductor memory with a\nNOR-type memory array.\nWhat is claimed is:\n. A nonvolatile semiconductor memory comprising:\na semiconductor substrate having a well region;\na multiplicity of memory transistors formed in said well 25\nregion and arranged in a matrix form of rows and\ncolumns, said memory transistors being configured into\na plurality of cell units each comprised of a plurality of\nsaid memory transistors connected in series, each of\nsaid memory transistors having source and drain 30\nregions formed in said well region of said substrate and\nseparated by a channel region, a floating gate formed\nover said channel region to store charge representing\nbinary data, and a control gaze formed over said floating\ngate; 35\na plurality of word lines each of which is connected to\nsaid control gates of respective ones of said memory\ntransistors in a corresponding row;\nbit lines generally intersecting said word lines;\na plurality of pairs of first selection lines and second\nselection lines arranged generally in parallel with said\nword lines, with said first and second selection lines of\neach pair thereof being disposed above and below,\nrespectively, uppermost and lowermost word lines of a\ncorresponding memory block comprised of a predeter-\nmined number of said cell units;\na plurality of first selection transistors associated with\neach said memory block, said first selection transistors\nof e~ ~.d memory block being connected between a\nfirst ~Mmsde of respective memory transistors of an\nupp~..uI row of said memory block and correspond-\ning ~s o( said bit lines, with a corresponding one of\nsaid first selection lines associated with said memory\nblock being coupled to a gate electrode of respective ~\nones of said first selection transistors associated with\nsaid memory block;\na plurality of second selection transistors associated with\neach said memory block, said second selection transis-\ntors of each said memory block being connected 60\nbetween a first electrode of respective memory transis-\ntors of a lowermost row of said memory block and said\ncorresponding ones of said bit lines, with a correspond-\ning one of said second selection lines associated with\nsaid memory block being coupled to a gate electrode of\nrespective ones of said second selection transistors\nassociated with said memory block;\na common source line coupled between respective elec-\ntrodes of said first selection transistors and said second\nselection transistors associated with adjacent ones of\nsaid memory blocks, respectively;\na data register connected to said bit lines for providing\nbinary data to said bit lines, said register providing\nlogic high level voltages to bit lines associated with\nmemory transistors programmed to first binary data,\nwhile providing reference voltages to bit lines associ-\nated with memory transistors programmed to second\nbinary data; and\ncontrol means connected to said word lines and said first\nand second selection lines for applying a program\nvoltage to a selected one of said word lines of a selected\nmemory block and pass voltages to remaining, unse-\nlected word lines of said selected memory block, and\nfor applying a logic high level voltage to said first\nselection line associated with said selected memory\nblock and rendering nonconductive said second selec-\ntion transistors associated therewith, whereby channel\nregions and source and drain junctions of memory\ntransistors in said selected memory block are capaci-\ntively charged to program inhibition voltages.\n. A method for programming a cell unit in an electrically\nerasable programmable read only memory, said cell unit\nbeing formed on a surface of a semiconductor substrate and\nhaving a plurality of memory transistors connected in series,\neach said memory transistor having source and drain regions\nformed in said substrate and separated by a channel region,\na floating gate formed over said channel region to store first\nbinary data, and a control gate formed over said floating\ngate, said method comprising the steps of:\ncharging said channel region and source and drain junc-\ntions of each of said memory transistors to a program\ninhibition voltage;\nmaintaining said program inhibition voltage when a\nselected memory transistor is not programmed to sec-\nond binary data, while discharging said program inhi-\nbition voltage to a low potential when said selected\nmemory transistor is programmed to said second binary\ndata; and\napplying a program voltage to said control gate of said\nselected memory transistor.\n. A method for progr~mmrng a cell unit in a sernicon-\nductor memory, said cell unit being formed on a surface of\na semiconductor substrate and having a plurality of memory\ntransistors connecting in series, each said memory transistor\nhaving source and drain regions formed in said substrate and\n~ separated by a channel region, a floating gate formed over\nsaid channel region to store first binary data, and a control\ngate formed over said floating gate, said method comprising\nthe steps of:\napplying a first high voltage to said control gate of a\nselected one of said memory transistors and a second\nhigh voltage lower than said first high voltage to said\ncontrol gates of remaining, unselected ones of said\nmemory transistors, whereby said channel region and\nsource and drain junctions of said memory transistors\nof said unit are capacitively charged to a uniform\npredetermined charged voltage; and\ndischarging said charged voltage when said selected\nmemory transistor is programmed to second binary data\nwhile maintaining said charged voltage when said\nselected memory transistor is not programmed to said\nsecond binary data.\n. A method for programming a nonvolatile semiconduc-\n\nCase 9:02-cv-0005S-'JH Document 20 F~ed 04/03/2002 Page 54 of 127\n,473,563\ntor memory w~th comprises a mulitplicity of memory\ntransistors formed in a semiconductor substrate and arranged\nin a matrix of rows and columns, said memory transistors\nbeing configured into a plurality of cell units each comprised\nof a plurality of said memory transistors connected in series, ~\neadr of said memory transistors having source and drain\nregions formed in said substrate and separated by a channel\nregion, a floating gate formed over said channel region to\nstore first and second binary data, and a control gate formed\nover said floating gate, a plurality of word lines each of\nwhich is connected to said control gates of respective ones\nof said memory transistors in a corresponding row; bit lines\ngenerally intersecting said word lines; a plurality of pairs of\nfirst selection lines and second selection lines arranged\ngenerally in parallel with said word lines, with said first and\nsecond selection lines of each pair thereof being disposed `~\nabove and below, respectively, uppermost and lowermost\nword lines of a corresponding memory block comprised of\na predetermined number of said cell units; a plurality of first\nselection transistors associated with each said memory\nblock, said first selection transistors of each said memory 20\nblock being connected between a first electrode of respective\nmemory transistors of an uppermost row of said memory\nblock and corresponding ones of said bit lines, with a\ncorresponding one of said first selection lines associated\nwith said memory block being coupled to a gate electrode of ~\nrespective ones of said first selection transistors associated\nwith said memory block; a plurality of second selection\ntransistors associated with each said memory block, said\nsecond selection transistors of each said memory block\nbeing connected between a first electrode of respective 30\nmemory transistors of a lowermost row of said memory\nblock and said corresponding ones of said bit lines, with a\ncorresponding one of said second selection lines associated\nwith said memory block being coupled to a gate electrode of\nrespective ones of said second selection transistors associ- ~\nated with said memory block; a common source line coupled\nbetween respective electrodes of said first selection transis-\ntors and said second selection transistors associated with\nadjacent ones of said memory blocks, respectively, said\nmethod comprising the steps of: 40\napplying a program voltage to a selected word line of a\nselected memory block and a pass voltage lower than\nsaid program voltage to remaining, unselected word\nlines of said selected memory block, while applying a\nlogic high level voltage lower than said pass voltage to\nsaid gate electrodes of said first selection transistors\nassociated with said selected memory block and ren-\ndering no~uctive said selection transistors associ-\nated with said selected memory block, said logic high ~\nlevel vo~agc corresponding to a logic high state; and\napplying * ~gic low level voltage corresponding to a\nlogic low state to respective ones of said bit lines\nassociated with selected ones of said memory transis-\ntors being programmed from said first binary data to ~\nsaid second binary data, while applying said logic high\nlevel voltage to respective ones of said bit lines asso-\nciated with unselected ones of said memory transistors\nnot being programmed, whereby channel regions and\nsource and drain junctions of said unselected memory 60\ntransistors are capacitively charged to a voltage level\nbetween said logic high level voltage and said program\nvoltage so as to prevent programming of said unse-\nlected memory transistors.\n. A semiconductor memory, comprising: 65\na memory cell array including a multiplicity of cell units\narranged in a matrix form having rows and columns,\nfirst and second selection lines, row lines and column\nlines;\nwherein each of said cell units includes a plurality of\nmemory transistors connected in series between a first\nerminal and a second terminal, a first selection uan-\nsistor connected between said first terminal and a\ncorresponding one of said column lines and a second\nselection transistor connected between said second\nterminal and a common source line;\nwherein a plurality of memory blocks arc defined by\nrespective rows of said cell units;\nwherein each of said memory transistors includes source\nand drain regions formed in a semiconductor substrate\nand separated by a channel region in said substrate, a\nfloating gate formed over said channel region for\nelectrically storing first and second data, and a control\ngate formed over said floating gate, said control gates\nof said memory transistors in each of said rows being\ncommonly connected to a corresponding one of said\nrow lines;\nwherein each of said first and second selection transistors\nhas a gate, said gates of said first selection transistors\nin each of said memory blocks being commonly con-\nnected to a corresponding one of said first selection\nlines, and said gates of said second selection transistors\nin each of said memory blocks being commonly con-\nnected to a corresponding one of said second selection\nlines;\ndata latch means connected to said column lines for\nstoring said first and second data, and for providing a\nfirst potential corresponding to said first data to a first\nset of said column lines, to thereby render nonconduc-\ntive said first selection transistors connected to said first\nset of said column lines, and for providing a second\npotential corresponding to said second data to a second\nset of said column lines, to thereby render conductive\nsaid first selection transistors connected to said second\nset of said column lines; and,\ndecoding means for selecting one of said memory blocks\nand one of said row lines in said selected memory\nblock, for applying a program potential to said selected\nrow line and a pass potential lower than said program\npotential to remaining, unselected ones of said row\nlines in said selected memory block, and for applying\na third potential to said first selection line in said\nselected memory block, and a nonconduction signal to\nsaid second selection line in said selected memory\nblock, whereby all of said second selection transistors\nin said selected memory block are rendered noncon-\nductive, said memory transistors on said selected row\nline associated with said first set of column lines are\nprevented from being programmed by virtue of uni-\nform, capacitive charging of their source and drain\njunctions to a program inhibition potential due to\nnonconduction of said first selection transistors asso-\nciated with said first set of column lines, while source\nand drain junctions of said memory transistors in said\nselected memory block associated with said second set\nof column lines axe discharged to said second potential\nso as to be programmed by a potential difference\nbetween said second potential and said program poten-\ntial.\n. The semiconductor memory as set forth in claim 5.\nwherein said first potential is a power supply potential and\nsaid second potential is a ground potential.\n\n* * S * *\n\nCase 9:02-cv-00058~JH Document 20 F~ed 04/03/2002 Page 55 of 127\n\nUnited States Patent ~\nCho et at.\n\n(54] NON-VOLATILE SEMICONDUCTOR\nMEMORY DEVICE AND METHOD F(~OR\nMANTJFAC~UR1NG TEE SAME\n\n[75] Inventors: Myoung-kwan Cho; Jeoug-h~iyuk Chol,\nboth of Kyungki, Rep. of Kore~a\n\n[73] Assignee: Samsung Electronies Ce,, Ltd~L,\nSuwon, Rep. of Korea\n\n[21] AppI. No.: 107,901\n[22] Filed: Aug. 18, 1993\n\n[30] Foreign Application Priority Data\nAug. 18. 1993 [KR] Rep. of Korea ..... ~.... 14810/92\n[51) mt. ci6 ~ HOIJ1L 29f788\n(52) U.S. Cl. _. ....~. .. 257/316; 2571371;.; 257/548;\n[58) FIeld of Search ~ 25711/316, 371,\n/7/548. 324\n\n[56) References Cited\nU.S. PATENT DOCUMENTS\n,907,058 3/1990 Sakal ___~_._. 257/371\n,063,431 11/1991 Ohahinra ____.. 257/316\n,341,342 8/1994 Brsbmbhaa ._..._.... 257/316\n\nPrimary Examiner-Edward Wojciechowicz\nAttorney, Agent, or Firm-Qishinan Darby & Cushman\n\n\n[57] ABSTRACT\n\nAn EEPROM device in which a high voltage is applied to\nthe chip during the memory cell operation and a method for\nthe manufacturing the same are disclosed. On a P-type\nsemiconductor substrate, a first N-well is formed in a surface\nportion of the substrate in the cell array region and a second\nN-well is formed in a first surface of the substrate in the\nperipheral circuit region. An EEPROM memory cell is\nformed on the first P-well and a first NMOS transistor is\nformed on the second P-well. Also, a second NMOS tran-\nsistor is formed on a second surface portion of the semi-\nconductor substrate in the p&pheral circuit 10 region and a\nPMOS transistor is formed on the second N-well. The\nimpurity concentrations of the first and second P-wells are\ncontrolled in accordance with the characteristic of the MOS\ntransistors to be formed. Further, a second NMOS transistor\nhaving a resistance against a high voltage is directly formed\non the P-type substrate. Thus, the electric characteristic of\nthe EEPROM device is enhanced.\n\nin mu w IIW 11111 Ih~ J liii flu HId 11111111 fill II~\nUS0055 14889A\n\n(1'] Patent Number: 5,514,889\n[45] Date of Patent: May 7, 1996\n\nCELL\nARRAY REGION\nClaims, U Drawing Sheets\n\nI. ~PERIPI-~ERAL CIRCUIT REGION\n\nLL\n\n-J--\n\nCase 9:02-cv-00056~JH Document 20 F~ed 04/03/2002 Page 56 of 127\n\nU.S. Patent\n\nMay 7, 11996\n\n\nFIG. I\n\nSheet 1 of Li\n,514,889\n\nPER! PHERAL\n\nCIRCUIT REGION\nI\n\n~CELL ARRAY REGION\nLJ\n\nFIG.2\n\nSELECTED\nBIT LiNE\nBL( I)\n\nUNSELECTED\nBIT LINE\nBL(2)\n\nERASE\nBLft) BL(2)\nOPEN OPEN\n\nWRITE\nBLtI) BL(2)\nO.3V 7V\n\n\nSELLECT GATE\n\nI\n\n~v\n\nTv\n\nCODNTROL GATE\n\nI\n\nOv\nV\n\nCODNTROL GATE\nOV\nV\n\nCOONTROL GATE\nov\nV\n\nCOONTROL GATE\n\nN\n\nOV\nV\n\nSELLECT GATE\nV\n\nOV\n\nS~DURCE\nP--WELL\nN--SUBSTRATE\n\n\nOPEN\nV\nZOV\n\nOv\nOV\nOV\n\nCase 9:02-cv-0005$~JH\n\nDocument 20\n\nHIed 04/03/20.02\n\nPage 57 of 127\n\nU.S. Patent\n\nMay 7, : 1996\n\n\nFIG. 3\n\nSheet 2 of 11\n,514,889\n\nCELL\nARRAY REGION\nJ~L\n\nPERIPHERAL CIRCUIT REGION\n\nCase 9:02-cv-0005$~JH\n\nDocument 20 F~!ed 04/03/2002\n\nPage 58 of 127\n\nU.S. Patent\n\n\nU..\n\nMay 7, 1996\n\nSheet 3 of U\n,514,889\n\nCase 9:02-cv-00058~JH\n\nDocument 20 HIed 04/03/20.02\n\nPage 59 of 127\n\nMay 7, 11996\n\nSheet 4 of ii\n,514,889\n\nU.S. Patent\n\n(0\n(\nU-\n\nCase 9:02~cv~00058~JH\n\nDocument 20 HIed 04/03/2002 Page 60 of 127\n\nU.S. Patent\n\nSheet 5 of U\n,514,889\n\nMay 7, 11996\n\nCase 9:02~cv~00058~JH Document 20\n\nRIed 04/03/2002\n\nPage 61 of 127\n\nU.S. Patent\nU-\n\nMay 7, 11996\n\nSheet 6 of 11\n,514,889\n\nCase 9:02~cv~00058~JH\n\nDocument 20 HIed 04/03/2002\n\nPage 62 of 127\n\nU.S. Patent\n\nCs':;\n\nMay 7, 1996\n\nSheet 7 of 11\n,514,889\n\nC~4\n\nCase 9:02~cv~0005~JH Document 20 HIed 04/03/2002 Page 63 of 127\n\nU.S. Patent\n\n\nf1~\n(9\nU-\n\nMay 7, 1 1996\n\nSheet 8 of 11\n,514,889\n\nCase 9:02~cv~0005$JH Document 20 HIed 04/03/2002 Page 64 of 127\n\nU.S. Patent\n\nU-\n\nMay 7, ] 1996\n\nSheet 9 of 11\n,514,889\n\nCase 9:02~cv~0005~JH Document 20 HIed 04/03/2002\n\nPage 65 of 127\n\nU.S. Patent\n\n\n(9\n\nMay 7, 1(996\n\nSheet 10 of U\n,514,889\n\nCase 9:02~cv~00058~dH\n\nDocument 20 HIed 04/03/2002 Page 66 of 127\n\nU.S. Patent\n\n\nCo\n(9\nLi.\n\nMay 7, 11996\n\nSheet 11 of 11\n,514,889\n\nCase 9:02~cv~00058~JH Document 20 HIed 04/03/2002\n,514,889\n\nPage 67 of 127\nNON-VOLATILE SEMmC0NDUCrODR\nMEMORY DEVICE AND METHOD FOR\nMANUPACrURIr4G THE SAME\n\nBACKGROUND OF THE INVENTIONN\nThe present invention relates to an electricall)ly erasable\nand prograxmriahlc read only memory (EEPROM)L) de'iice as\na non-volatile semiconductor memory device and d a method\nfor manufacturing the same, and, more particulalariy, to an\nEEPROM device in which a high voltage is applDliedto the\nchip during memory cell operation and a methood for the\nmanufacturing the same.\nAlong with the progress of computer systems, th~he need for\nlarge-capacity non-volatile memories adaptable e to high-\nspeed operation, such as memory cards, has i increased.\nAmong these non-volatile memories, there basis been an\nincreased need for EEPROMs comprised of a fionating gate\nand a control gate and which can electrically erase and\nprogram data. Therefore, a variety of cell suuarctures for\nEEPROMs have been suggested for providing hi~igber inte-\ngration density, larger capacity and faster petforirmance.\nA NAND-structured memory cell has been de%rveloped in\norder to achieve cell area reduction without stre~essing the\nfabrication technology. An advanced NAND structtured flash\nEEPROM has been suggested (see \"A 2.3 unit Mearmory Cell\nStructure For NAN!) EEPROMf by R. Shirota et * aL IEDM,\n. pp 103-106).\nFIG.1 is a sectional view illustrating the abovwe NAND-\nstructured EEPROM which is manufactured sara follows.\nFirst, a first P.weIl 2 (in a cell array region) andd a second\nP-well 3 (in a peripheral circuit region) are fonrined in the\nupper portion of an N-type semiconductor substrswe 1. Then,\na cell array comprised of an EEPROM is formeted on first\nP-well 2, an NMOS transistor of the peripheral ii circuit is\nformed on a portion of second P-well 3, and an NJ-well 4 on\nwhich a PMOS transistor of the peripheral circuirit is to be\nformed, is formed in a portion of second P-well 33. In order\nto manufacture the above EEPROM, ions are I implanted ~\nthree times for forming three impurity-doped oregions (or\nbulks): one for forming first P-well 2 on which thee cell array\nis to be formed, one far forming second P-well 33 on which\nthe NMOS trauslator of the peripheral thvuit is foarmed, and\none fir forming N-well 4 on which PMOS trinsisistor of the\nperipheral circuit is formed.\nFIG. 2 shows a portion of an equivalent circuit daliagrarn of\non E~'ROM device using the aforementioned coanventional\nEEPROM call ~I an erase snd write (or progranxn) opera-\ntion. The ,~.... operation of a selected cell, is c,carried out ~\nby cbargth~ aiac*ru.~s into the floating gate and nraising the\ncell', thL,\ufffdJ voltage. This is accomplished byy applying\n.3 V to a r5~4 bit line BL(1) of the cell arra~ay and 7 V\nto an unw4\"cted bit line BL(2) of the cell array ass a program\npreventing voltage, and applying 10 V to the uunselected ~\ncontrol gate and 18 V to the selected control gatate, respec.\ntively. The iSV applied to the selected cell's conirrrol gates is\ncoupled so that about 10 V is induced at the floathigig gale and\n.3 V is transferred to the selected cell's channelel. Then, a\nnearly 10 MeV field applied between the oppositite sides of ~\na nearly 100 A-thick tunnel oxide layer whisich exists\nbetween the channel and floating gate, causes lithe floating\ngate electrode to be charged with electrons by thiie Fouler-\nNordheim (F-N) tunnelling effect Thus, a datum iii written\ninto the selected memory cell.\nto thereby lower the threshold voltage of the cell, is accom-\nplished by applying 20 V to the P-well 2 on which the cell\narray is formed, opening the bit-line and source-line, and\ngrounding the control gate. Thereby, the electrons within the\nS floating gate are discharged by the field between the ends of\nthe tunnel oxide layer. Here, in order to protect the transistor\nof the penphcrai circuit which operates ax +5 V (Vcc) from\nthe approximately 20 V applied to the P-well 2 of the cell\narray during the erase operation. transistors are formed on\nio another P-well 3 which is electrically isolated and indepen-\ndent of the P-well 2 of the cell array.\nA read operation is performed according to the data\ndetermination. The data is determined by the bit-line current\npath fluctuating between \"on\" and \"oft\" states according to\n~ the positive or negative value of the threshold voltage of the\nselected cells.\nFor manufacturing the above conventional NAND\nEEPROM device, a photolithography process for forming\nthe well structures is performed twice: First, that is, for\nformingafiistP-well2onwhichacellarrayistobeformed\nand a second P-well 3 on which the NMOS transistor of the\nperipheral circuit is to be formed, Second for forming an\nN-well 4 which is located within the second P-well 3, on\n`which the PMOS transistor of the peripheral circuit is to be\n~ formed on the N-type semiconductor substrate L\nHowever, the conventional NAND EEPROM device as\ndescribed above exhibits certain drawbacks. First, since the\nN-type substrate 1 is applied with a high voltage concur-\n~ rently with the erase operation which applies 20 V to the\nP-well 2 on which the cell array exists, transistors cannot be\nformed directly on the N-type substrate 1. Also, since the\ntransistors of the peripheral circuit are formed on a P-well 3\nand an N-well 4 within this P-well 3, the bulk resistance is\nincreased. Accordingly, lazchup and other delitosious elec-\ntrical characteristics occur.\n\nSUMMARY OF THE INVENTION\nFor solving the above-mentioned problems, an object of\nthe present invention is to provide a non-volatile memory\ndevice which can be manufactured by independently con-\ntrolling the bulk regions used in the cell array and peripheral\ndrmiit revons\nAnother ol~ect of the present invention Is to provide a\nsuitable method for manufacturing a non-volatile memory\nchavlce~\nTO accomplish the aforementioned objects, the present\ninvention provides a semicontin~!iw memory device com-\npcisIng~ a semiconductor substrate of a first conductivity\ntype which is divided Into a cell array region and a periph-\neral circuit region; a first imparity-doped region of the first\nconductivity type formed in the surface portion of the\nsemiconductor substrate in the cell array region; a second\nimpurity-doped region of a second conductivity type formed\nin the surface portion of the semiconductor substrate in the\ncell array region, the second impurity-doped region enclos-\ning the first impurity-doped region; and a memory cell\ncomprised of a fourth source region and a fourth drain region\nformed on the surface portion of the first impurity-doped\nregion and of a floating electrode formed on the first\nImpurity-doped region and a control electrode formed on the\nfloating electrode. In the peripheral circuit region, the semi-\nconductor memory device may further comprise a third\nimpurity-doped region of the first conductivity type formed\nin a first surface portion of the semiconductor substrate in\nthe peripheral circuit region; a first MOS transistor corn-\n\nConversely, the erase operation, which is csrricied out by\ndischarging the electrons within the floating gate electrode\n\nPage 68 of 127\n\nCase 9~02~cv~0005$~JH Document 20 F~ed 04/03/2092\n,514,889\nprised of a first gaze electrode formed on the thirird impurity-\ndoped region and first source and drain regiorisis formed in\nsurface paribas of the third impurity-doped xegiaon; a second\nMOS comprised of second source e and drain\nregions formed in a second surface portion of tithe semicon- 5\nducror substrate in the peripheral circuit region *2nd a second\ngate electrode formed on the semiconductor s substrate; a\nfourth impurity-doped region of the second oconductivity\ntype formed in a third surface portion of the serrmiconductcc\nsubstrate itt the peripheral circuit region; a I third MOS\ntransistor comprised of third source and drarain regions\nformed in surface portions of the fourth imp\ufffdty-doped\nregion and a third gate electrode formed on r the fourth\nimpurity-doped region.\nIn order to achieve another object, the preseitnt invention\nprovides a method for manufacturing a semnicooxiuctor\nmemory device comprising the steps of: providiling a semi-\nconductor substrate of a first conductivity type d defined into\na cell array region and a peripheral circuit regidon; forming\na second impurity-doped region of a second ononductivity\ntype in a surface portion of the semiconductor r substrate in\nthe cell array region; forming a first impurity-ddoped region\nof the first conductivity type enclosed by the firarat impurity-\ndoped region; and forming a memory device ( on the first\nimpurity-doped region. The memory device is a formed by\nforming a first conductive layer pattern on the tirarst impurity-\ndoped region, forming an insulating layer pattearm covering\nthe first conductive layer pattern, forming a secaond conduc-\ntive layer pattern on the insulating pattern, patitterning the\nsecond conductive layer pattern, the insulating lalayer pattern\nand the first conductive layer pattern sequentlall}4y, to thereby\nform a control gate electrode and a floating gatctc electrode.\nand implanting an impurity into the first impipruity-doped\nregion to thereby form a source region and a drainin region of\nthe memory device.\nIn accordance with one embodiment of the pruesent inven-\ntion, in the peripheral circuit region; a third imp\ufffdity-doped\nregion of the first conductivity type in a first surfrface portion\nof the semiconductor substrate in the penph\ufffdal circuit\nregion may be formed, and a fourth impunty-ddoped region ~\nof the second conductivity type in a third surfacce portion of\nthe semiconductor substrate in the peripheral cixrrcuit may be\nformed.\nThe second end fcerth impurity-doped regloces are pref- ~\ncrably formed by forming a first oxide layer ann the semi-\nconductor substrate, forming an antioxidative hlayer on the\nfirst oxide Layer, farming a pbaroresist pattern c on the anti-\noxidative layer which exposes portions of the antal-oxldative\nlayer wham the ~corvS end fourth Lmp~nity-dopped regions ~\nare to be *wancd etching the exposed portions i of the anti-\noxidadv~ leer, and implanting a second condonctivity type\nimpurity ~ ~face portions of the semiconaductor sub-\nstrate vl& the etched portion of the inti-oxidathtve layer.\nThe first ~ third Impurity-doped regions ma'ay be formed~\nby forming a first oxide layer and an ti-oxidatifive layer on\nthe semiconductor substrate exchrding a portio2u where the\nsecond impurity-doped region is formed, formiting a second\noxide layer on the second impurity-doped regioon. forming a\nphotoresist pattern exposing a portion of the se'~econd oxide ~o\nlayer where the first impurity-doped region Is tao be farmed\nand a portion of the anti-oxidative layer wberem the third\nimpurity-doped region Is to be formed, and theno implanting\na first conductivity type impurity into the seioonductor\nsubstrate.\nAccording to one embodiment of the presennit invention,\nthe first conductivity type impurity is firstly iropplanted at a\nfirst acceleration energy such that the first conductivity type\nimpurity penetrates the second oxide layer and the attti-\noxidative layer~ and secondly implanted at a second accel-\neration energy such that the first conductivity type impurity\npenetrates the anti-oxidative layer but not the second oxide\nlayer.\nAccording to another embodiment of the present inven-\ntion, the second oxide layer is etched using the photoresiat\npattern as an etching mask to thereby expose a surface\nportion of the semiconductor substrate where the first impu-\nrity-doped region is to be formed. The first conductivity type\nimpurity is firstly implanted at a first acceleration enez-gy\nsuch that the first conductivity type impurity does not\npenetrate the arni-oxidative layer, and secondly implanted at\na second acceleration energy such that the first conductivity\ntype impurity penetrates the anti-oxidative layer.\nAccording to still another embodiment of the present\ninvention, the first conductivity type impurity is firstly\nimplanted at a first acceleration energy such that the first\nconductivity type impurity penetrates the anti-oxidative\nlayer but not the second oxide layer, the second oxide layer\nis etched using the phocoresist pattern as an etching mask to\nthereby expose a surface portion of the semiconductor\nsubstrate where the first impurity-doped region is to be\n~ formed, and then the first conductivity type Impurity is\nsecondly implanted at a second acceleration energy such that\nthe first conductivity type impurity penetrates the anti-\noxidaiive layer.\nThe NAND-stnictured EEPROM according to the present\ninvention comprises EEPROM cells formed on the pocket\nP-well. The impurity concentration of the pocket P-well may\nbe controlled independently from the P-well which is\nfarmed in the peripheral circuit region. Therefore, an\nEFPROM device having two P-wells in the cell array region\nand the peripheral circuit region, respectively, of which the\nconcentrations may controlled according to the device char-\nacteristic and independently from each other, may be\nobtained.\nAlso, an NMOS transistor of the peripheral circuit region\nwhich is operated at a high voltage may be formed directly\non the P-type semiconductor substrate, thus enhancing the\nresistance thereof against the high voltage. In the ~nt~me,\nthe thar~eristics of the NMO$ translator of the peripheral\ncircuit region which is operated at Vcc, are controlled by\nforming the NMOS transistor on the P-well of the peripheral\ncircuit region to thereby enhance the punch-through char-\nacteristics thereof.\n\nOF ThE DRAWINGS\nThe above object and other advantages of the present\ninvention will become more apparent by describing in detail\na preferred embodiment thereof with reference to the\nattached drawings in which\nFIG. 1 is a sectional view showing the conventional\nNAND-strucwied EEPROM;\nFIG. 2 shows a portion of an equivalent circuit diagram of\nan EEPROM device using a conventional NAND-structured\nEEPROM cell and an erase and write (or program) operation\nti~eof.\nFIG. 3 is a sectional view showing a structure of a\nNAND-structured EEPROM according to one embodiment\nof the present invention;\nFIGS. 4 through 12 are sectional views Illustrating a\nmethod for manufacturing a NAND-structured EEPROM\n\nCase 9:02-cv~00058~JH Document 20 F~ed 04/03/2002 Page 69 of 127\n,514,889\n\nS\ndevice according to a first embodiment of th& present\ninvention;\nFIGS. 13 and 14 are sectional views illustrating g a method\nfor manufacturing a NAND-structured EEPRODM device\naccording to a second embodiment of the present t invention; 5\nFIG. 15 is a sectional view illustrating a mmethod for\nmanufacturing a NAND-structured EEPROM~{ device\naccording to a third embodiment of the present irinvention;\nFIGS. 16 and 17 are sectional views illustrating g a method\nfor manufacturing a NAND-structured EEPRODM device\naccording to a fourth embodiment of the present i invention;\nand\nFIG. 18 is a sectional view illustrating a mmethod for\nmanufacturing a NAND-stnictured EEPROMivI device i~\naccording to a fifth embodiment of the present innventiom\n\nDESCRiPTION OF THE PREFERREDD\nEMBODIMENT\nHereinafter, the present invention is to be desiscribed in\nmore detail in reference with the attached drawinngs.\nFIG. 3 is a sectional view of a NAND-t-strucrured\nEEPROM device according to one embodimerent of the\npresent invention.\nInto a semiconductor substrate of a first cooducttivity type\n(having a low concentration), e.g., P-type semisicoaductor\nsubstrate 10, a second conductivity type impurity ( (an ion) is\nimplanted to thereby form a plurality of second coonductivity\ntype impurity-doped regions. i.e., N-wells. Thes~e N-wells\ninclude a first N-well 11 as a second impurity-dopped region\n(of a second conductivity type) formed in the cccl array\nregion and a second N-well 12 as a fourth impunnty-doped\nregion (of a second conductivity type) in a thirird surface\nportion of the semiconductor substrate in the ~pcripheral\ncircuit region.\nA first conductivity type impurity is implanted i into a first\nN-well U of the cell array region, to thereby foxxm a first\nP-well 13 as a first impurity-doped region of a flrsrst conduc-\ntivity type in the cell array region. On first P-wwell 13, an\nEEPROM device having source and drain regionais (formed\nin the surface portions of first P-well 13) and a flocating gate\nformed on the first P-well 13 mal a conn~l gate fformed on\nthe floating electrode, Is fanned. Since first NN-wefl U\nencloses first P-well 13. the first P-well 13 Ia i generally\nreferred to as a pocket P-well.\nIn the peripheral circuit region (having no cell stand includ-\ning second N-well 12) of P4ype semiconductor sulabstrate 10,\nfor operating the cell array, a second P-well 141 as a third\nimpurity-doped region of a first conductivity type ~ is formed\nin a first ~`e portico of aenuconductor substrtrate 10 by\nimpl2nhing ~ Impurity having a first conductivity.y type (the\nsame condoctivity type as t~ of iemiconductor substrate\n) into a first portion of the peripheral circuit region of\nsemiconductor substrate 10, while excluding ththe portion\nwhere second N-well 12 is formed.\nOn second P-well 14, a first MOS transistor (thirat is, first\nNMOS transistor) is formed which comprises fl~rst source\nand drain regions formed in surface portions a of second ~\nP-well 14, and a first gate electrode formed on secoond P-well\n.\nIn a second portion of the peripheral circuit region of\nP-type semiconductor substrate 10 (excluding these portions\nwhere second N-well 12 and second P-well 14 aree formed). 65\na second MOS transistor (second NMOS Iransistator) which\nhas a resistance against high voltage is forrnedd between\nsecond P-well 14 and second N-well 12. The second MOS\ntranslator includes second source and drain regions formed\nin second surface portions of semiconductor substrate 10\nand a second gate electrode formed on semiconductor sub-\nstrate 10.\nOn second N-well 12. a third MOS transistor (PMOS\ntransistor) having third source and drain regions in surface\nportions of second N-well 12 and a third gaze electrode on\nsecond N-well 12, are formed.\nSince the second NMOS transistor is formed directly on\nthe P-type semiconductor substrate 10, the reverse bias\ncharacteristic between the N+ doped region of the NMOS\ntransistor and the P-type semiconductor substrate 10 having\na low impurity concentration is improved. The second\nNMOS transistor has a gate insulating layer whose thickness\nis thicker than that of first NMOS transistor. Also, using a\nP-type semiconductor substrate 10 having a low impurity\nconcentration improves the body effect. An NMOS transis-\ntor of the peripheral circuit, which does not have a resistance\nessentially against a high voltage, is formed on second\nP-well 14, thus improving the punch-through characteristic\nof the short channeL\nThe characteristic of second N-well 12 on which a PMOS\ntransistor of the peripheral circuit is formed should be\ncontrolled according to the PMOS characteristic and the\nisolation characteristics thereof. Since second N-well 12 is\nformed simultaneously with the first N-well U wherein first\nP-well 13 (the pocket P-well) is to be formed, the change in\nthe characteristics of second N-well 12 should accompany\nthe characteristic change in first N-well U. This in turn\ncauses the characteristic of first P-well 13 to change. When\n~ini1llt2nPously forming first P-well 13 and second P-well 14\nby using the same photomask and the same ion-implantation\n~ processes, in order to optimize first P-well 13 according to\nthe change in the characteristic of first N-well U, the\ncharacteristic of second P-well 14 is undeabibly changed.\nTo solve this problem, aphorolithography process should be\nadded for forming first P-well 13 and second P-well 14\n~ separately, which is undesirable.\nIn the present invention, a method for manufacturing the\nabove E~ROM device without an &lditional photolithog.\nraphy process is ~xovided. Hereinafter, the method will be\ndescribed hi detail with reference to the following cmbodi-\nmentL\n\nEmh~ment I\nFIGS. 4 through 12 are sectional views illustrating a\nmethod for manufacturing a NAND-stiuctured BEPROM\ndevice according to a first embodiment of the present\ninvention.\nFIG. 4 is a sectional view illustrating a step of forming a\nfirst N-well 24 as a second impurity-doped region and a\nsecond N-well 24A as a fourth impurity-doped region in an\nupper surface portion of P-type semiconductor substrate 20.\nMore particularly, on a first conductivity type semiconductor\nsubstrate, for example, <100>-oriented P-type semiconduc-\ntor sub~ate 20 having a resistance of 1811cm, a first oxide\nlayer 21 is firstly formed to a thickness of 380 A, as in the\nconventional N-well formation. Thereafter~ on first oxide\nLayer 21, a silicon nitride layer 22 as an anti-oxidative layer\nis formed by depositing silicon nitride to a thickness of about\nA via a conventional chemical vapor deposition (CVD)\nmethod. Thereafter, a photoresist is coated on the silicon\nnitride layer 22 to thereby form a photoresist film (not\nshown). Then, the photoresiat ifim is exposed using a\n\nCase 9:02-cv-0005$cJH Document 20 F~ed 04/03/20Q2\n,514,889\n\nPage 70 of 127\nphocomask for forming first and second N-well ~ 24 and 24A\nand dcvsicped to form a first photoresist pattern ((not shown)\nwhich exposes a portion of silicon nitride layer 222. Using the\nfirst phororesist pattern as an etching mask, a premieterrumned\nportion of silicon nitride layer 22 is etched,, to thereby ~\nexpose surface portions of semiconductor staubstrate 20\nwhere first N-well 24 of the cell array region r and second\nN-well 24A of the peripheral circuit region are too be formed.\nThen, a second conductivity type impurity (N.typrpc impurity)\nsuch as phosphor (P) is ion-implanted at a r dosage of\nl.lXlOi3 atoms/cm1 and at art acceleration voltitage of 150\nKeY, and then the first photoresist pattern is remeroved. Next,\nthe substrate is heat-treated at a temperature of a about 1150'\nC. for seventeen hours, to thereby not only a activate the\ndoped N-type impurity, but also diffuse the dop~ed impurity\ninto semiconductor substrate 20. As a tesult, firstat N-well 24\nof the cell array region and second N-well 2 24A of the\nperipheral circuit region are formed.\nHere, during the heat-treatment, second oxidde layers 23\nand 23A of the respective cell array region and~d peripheral\ncircuit region are grown to a thickness of 4,500 AA where the\nportions of silicon nitride layer 22 have been etetebed.\nFIG. ~ is a sectional view for illustrating a step p of forming\na second photoresist pattern 26 for forming a firast P-well as\na first impurity-doped region and a second P-weld as a third\nimpurity-doped region, and then firstly implaneiting a first\nconductivity type impurity. After the step of RG.. 4, a second\nphotozesist is coated on the resultant, thereby y forming a\nsecond photaresist film. The second photoreusist film is\nexposed using a phocomask for forming the flrstz and second\nP-wells and then developed to thereby formn a second\nphotoresist pattern for forming the first and seccond P-wells\nwhich expose a portion (excluding the edge I portion) of\nsecond oxide layer 23 of the cell array region sand a portion\nof silicon nitride layer 22 where second P-we'd! is to be\nformed. Then, a portion (excluding the surrouvnding edge\nportions) of second oxide layer 23 of the cell asarray region\nwhich is formed on first N-well 24 is wet-etcbesed using an\noxide etchant, to thereby expose the surface portion of\nsemiconductor substrate 20 where first N-well 224 has been\nformed- At this time, since silicon nitride layer 222 has a low\netching selectivity with respect to the oxide rt~th~t~t used in\nthe above wct-ctching when eoxnp.rcd to the sesecood oxide\nlayer 23, the exposed portion of silicon sitride laytyu 25*3 not\netched away. T~eafter, a first crv~thicthity type ~ impurity (a\nP-type impurity such as boron) Ii firstly lon-Impplanted at a\ndosage of O3xiO\" stoo*3/an2 and at a low a acceleration\nvoltage of 50 KeV for forming the pocket P.weflll of the cell\narray region. Under the above conditions, tithe exposed\nportion olMlicon nitride layer 22 prevents the imprpurity from\ndoping Imo the substrate. Thus, only a portion off first N-well\nis doped with P-type impurities via the expoused surface\nportion of .rmleo~vinctor substrate 20.\nFIG. dii a sectional view Illustrating a step o of secondly\nimplanting a that conductivity type impurity tothhereby form 55\na first P-well 27 and a second P-well 27A. AAfI& firstly\nimplanting the first conductivity type impurit$y at a low\nenergy, in order to form second P-well 27A of these peripheral\ncircuit region, the same impurity as that firstly itimplanted is\nimplanted at a dose of 1 .5x1013 atoms/cm2 at an a acceleration 60\nvoltage of 130 KeV (by which boron can penetrtatc silicon\nnitride layer 22 having a thickness of about t 2.000 A).\nwithout removing second phocoresist pattern a 26. After\nremoving second photoresist pattern 26, a drive'e-in step is\nperformed at a temperature of 1,150\ufffd C. for eig~t hours, to 65\ncomplete first (pocket) P-well 27 (as a first lrnpwinixy-dopcd\nregion) of the cell stray urea and second P-wellll 27A (as a\nthird impurity-doped region) of the peripheral circuit region.\nSecond P-well 27A is formed in a first surface portion of\nsemiconductor substrate 20 in the peripheral circuit region.\nFIG. 7 ii a sectional view Illustrating a step of forming a\nplurality of field oxide layers 23, a first gaze oxide layer 29\nof the peripheralcircuitregion, atunneloxide Iayer3oofthe\ncell array region, and first polysilicon layer pattern 31 for\nforming floating electrode of a NAND-rtructirred EEPROM\ncell of the cell array. More particularly, after the drive-in step\nof FIG. 6, silicon nitride layer 22, the 20 remaining second\noxide layers 23 and 23A, and first oxide layer 21 are\nremoved- Then, via a conventional LOCOS process, a\nplurality of field oxide layer 28 for electrically isolating\ndevices are formed on semiconductor substrate 20, and then\na first gate oxide layer 29 is formed to a thickness of 200 A\non the whole surface portion of semiconductor substrate 20\nexcluding the portions where field oxide layers 28 have been\nformed. Next, in order to selectively form tunnel oxide layer\nin the cell array region which is thinner than first gate\noxide layer 29, a portico of first gate oxide layer 29 in the\ncell array region is removed via a conventional photolithog-\nraphy process. After removing the photoresist pattern used\nin the photoithography process, a tunnel oxide layer 30 is\nformed to a thickness of tOO A on first P-well of cell array\nregion. Thereafter, for forming a first. conductive layer for\nforming a floating gate of an EEPROM device, a first\npoLysilicon is deposited to athicknessof 1,500 A, to thereby\nform a first polysilicon Iayen The first polysilicon layer is\ndoped with phosphorous ions so as to have a sheet resistance\nof 100Q~. thereby forming a first conductive layer for\nforming the floating gate. Then, the first conductive layer is\npatterned by a conventional photolithography process, to\nthereby form a first conductive layer pattern 31 on the cell\narray region.\nFIG. i is a sectional view Illustrating an insulating layer\n~ pattern 32 covering first conductive layer pattern 31 and\nimplanting an impurity for controlling the threshold voltage\nof the peripheral circuit region. After the step of FIG. 7, an\noxide/nitiide/oxide (ONO) layer is formed to a thickness of\nA/200 A/30 A as an insulating layer on the whole\nsurface of the resultant. Thereafter, a third photoresist pat-\ntern 33 Is formed which covers the cell array region and\nexposes the peripheral circuit region. Using third photoresist\npastern as an etching mask, the ONO film is etched to\nthereby ~m insulating layer pattern 32 covering that con-\ndu~ve layer pattern 3L At this time, first gate oxide layer\n~ 29 which ii formed on the peripheral circuit region, is\nthm\ufffd~~usly removed, to thereby expose the surface of\nsemiconductor substrate 20 of the peripheral circuit region.\nThereafter, in order to control the threshold voltage of\n~ peripheral circuit region, while leaving third phocoresist\npastern 33, a first conductivity type (P-type) impurity, such\nas boron, is ion-implanted through the exposed surface of\nsemi-conductor substrate 20 at a dosage of 2.OxlO\" szorna/\ncm2 and atm acceleration voltage of 50 KeY, and then third\nphotoresist pattern 33 Is removed.\nThereafter, an ion-Implantation process is performed for\ndifferentiattng the threshold of the NMOS transistors of the\nperipheral circuit More particularly, a region where an\nNMOS transistor of the peripheral circuit is to be formed.\ni.e., second P-well VA, is exposed by forming a fourth\npbotoresist pattern (not shown) and then, a first conductivity\ntype (P-type) impurity, such as boron, is iou-implanted\nthrough the exposed region at a dosage of 6.OxlO'1 ~s/\ncm2 and at an acceleration voltage of 50 KeY. Thereafter, the\nfourth photoresist pattern Is removed.\nThen, in order to form a normally on (operable) NMOS\ntransistor of the peripheral circuit directly on semiconductor\nIs\n\nCase 9:02-cv~0005$~JH Document 20 F~ed 04/03/2002\n,514,889\n\nPage 71 of 127\nsubstrate 2* (but not on second N-well 24A noor second\nP-well 27A). $ fifth photoresist pattern (not a shown) is\nformed to expose a portion of semiconductor sutibstrste 20\nbetween second P-well VA and second N-well 2~24A in the\nperipheral circuit section. Through the exposed I poruon, a ~\nsecond conductivity type (N4ype) inipurit? such a as arsenic\n(As) is ion-implanted at a dosage of 2.2x10 2atommalcrn2 and\nat an acceleration voltage of 30 KeV. Next, the flfifth photo-\nresist pattern is removed.\nFIG. 9 is a sectional view illustrating a step of fforming a\nsecond gale oxide layer 34 and partially removinng second\ngate oxide layer 34 on second N-well 24A and secoond P-well\nA. After removing the fifth photoresist patterirn. second\ngate oxide layer 34 is grown to a thickness of 2000 A via a\nthermal oxidation, on the whole surface of the e resultant\nexcluding the cell array region where insulating layiyer pattern\ncovers. Thereafter, a photoresist is coated on then resultant\nto form a photoresist film, which is exposed usin~g a photo-\nmask and then developed to form a sixth photoresisist pattern\nexposing a portion of second gaze oxide layer 334 formed\non both second N-well 24A and second P-well 27t7A. Using\nsixth photoresist pattern 35 as an etching mask, then exposed\nportion (which is formed in the peripheral tirctruit region\nexcluding the region where a PMOS transistonr and an\nNMOS transistor having a resistance against a hig.gh voltage ~\nare to be formed) of second gate oxide layer 34 con second\nP-well VA and second N-well 24A, is partially reramoved via\na conventional etching method.\nFIG. 10 is a sectional view illustrating a step obf forming\na third gate oxide layer 36 and forming gaze electrcrodes 39a, ~\nb and 39c of the transistors of the peripheral circmuit and a\ncomposite conductive pastern 39b for forming coontrol gate\nelectrodes of the cell array EEPROMs. After remonving sixth\nphotoresist pattern 35. on the surface region oof second\nP-well VA and second N-well 24A (where seccond gate ~\noxide layer 34 has been etched), third gate oxide ilayer 36 is\ngrown to have a thickness of about 180 A, via a con'uventional\nthermal oxidation process. During the thermal oxiadation for\nforming third gate oxide layer 36, second gaze oxidde layer 34\n(which is formed between second P-well VA annd second ~\nN-well 24A and has not 5 been etched in the abo'ove step of\nFIG. 9) grows to a greater thickness than itsts original\nthickness of 200 A. Reference ni~il 34' repreresenta the\nndditionally grown second gaze oxide layer.\nThereafter, on whole surface of the resultant, sen a second 45\nconductive layer for forming the co~ol gate elecctrades of\nthe cell array and the gate electrodes of the trmssislstor of the\nperipheral cimit. a second pc~ysilieon Is depoaite~ed to form\na second polysilicon layer having a thirki~1 of ab\ufffdt 1,500\nA, and thai phosphorous is doped so that th&~e second 50\npolysilicon lq~ has a sheet resistance of 100Q11.i Then, on\nthe second pa~pifl1con layer, a refractory metal silielcide layer\nis formed by depositing a urfrac*osy metal silicidde (such as\nWSi) to a ____ of 1,500 A. Thereafter, the ccompoaite\nconductive layer consisting of the second polyallilicon layer 55\nand the refr~ay metal siliclchi layer is pauernncd via a\nphotolithography process using a seventh photoresizist pattern\n. Thus, first, second and third gate electrodes 39~*z. 395 and\nc of first, second and third MOS transistors of tithe periph-\neral circuit consisting of first, second and third pattxtcrns 37a, 60\nb and 37c of second polysiliccu layer pattern i and first,\nsecond and third refractory metal suicide Layer pastttcm 38a,\nand 38c are formed. Also, a composite patterun 39d for\nforming control gate electrode of the cell srraay (which\ncovers insulating layer pattern 32) consisting off a fourth as\nsecond polysiiicon layer pattern 37d and fourth r refractory\nmetal silicide layer pattern 38d, is formed.\nAccording to the above method, since the NMOS tran-\nsistor's gate formed directly on P-type semiconductor sub-\nstate 20 which operates at a high voltage of about 20 V\nduring the cell program/erase operation, has the thickly\ngrown second gate oxide layer 34' as a gaze oxide layer, its\nrcsistance against high voltage is improved. In the mean-\ntime, the NMOS transistor formed on second P-well VA\nwhich operates at Vcc (which is a low voltage) uses third\ngaze oxide layer 36 as a gaze insulating layer (which is\nrelatively thin when compared to that of the NMOS tan-\nsistor formed directly on semiconductor substrate 20).\nTherefore, the punch-through characteristic the NMOS tran-\nsistor is improved.\nFIG. ii is a sectional view illustaung a step of forming\na control gate electrode 42 and a floating gaze electrode 31A\nof the cell array. After removing sixth photoresist pattern 40\nin FIG. 10, a seventh photoresist pattern 43 for forming the\ncontrol and floating electrode of an EEPROM which covers\nthe peripheral circuit region is formed on the resultant.\nUsing seventh photoresist pattern 43 as an etching mask,\nfourth refractory metal suicide layer pattern 38d, second\npolysilicon layer pastern 37d, insulating layer pastern 32 and\nfirst polysilicon layer pattern 31 are sequentially etched to\nthereby form the floalmg gate electrode 31A and control gate\nelectrode 42 (consisting of a fifth second polysilicon layer\npattern 37e end a fifth refractory metal silicide layer pattern\ne) of the cell array.\nFIG. 12 is a sectional view illustrating a step of cornplet-\ning the E~ROM cells and first, second and third MOS\ntransistors of the peripheral circuit. After removing seventh\nphotoresist pattern 43, N-type and P-type impurities are\nion-Implanted to the resultant, and heat-treatment is per-\nformed for activating and diffusing the implanted ions via a\nconventional MOS transistor-forming process. Therefore, an\ncell consisting of floating gate electrode 31A\nformed on first P-well 27, a control gaze electrode 42 formed\non floating gale electrode 31A. and a fourth source and drain\nregions 44d is formed. In the peripheral circuit region, a first\nMOS transistor (an first NMOS transistor) consisting of first\ngaze electrode 39a formed on second P-well VA. and first\nsource and drain regions formed in the surface portions of\nsecond P-well VA is formed. Also, on a secood portion of\n~ substrate 20 in the peripheral circuit region,\na second MOS transistor (a second NMOS trmnstetnr) con-\nnating of second gate electrode 395 sad second s~arce sad\ndrain regions 44a formed in the second surface portions of\nsemiconductor substrate 20 in the perIpl~al circuit region,\nis formed. On second 15N-welI 24A, a third MOS transistor\n(a PMOS transistor of the peripheral circuit) consisting of a\nthird gate electrode 39c formed on second N-well 24A and\na third source and drain regions 44c formed in the surface\nportions of second N-well, is formed. Thus, two NMOS\nand one PMOS transistor of the peripheral circuit\naxe formed in the peripheral circuit region.\nSubsequent steps (not shown) such as a metallization\nprocess, a process for forming insulation interlayer. and a\nplanarizalion process, are performed to thereby complete the\nEEPROM device of the present invention, in the same\nmani~r as in the case of a conventional memory device.\nTherefore, detailed descriptions thereof will be omitted.\n\n\nEmbodiment 2\nFIGS. 13 and 14 are sectional views illustrating a method\nfor manufacturing a NAND-structured EEPROM device\naccording to a second embodiment of the present invention-.\n\nCase 9:02-.cv-.0005$~JH Document 20 F~ed 04/03/20~2\n\nPage 72 of 127\nFIG. 13 Ii a sectional view illustrating a ststep of firstly\nimplanting a first conductivity type impurity.\nThe same procedure as shown in FIG. 4 of EEmbodiment\nI is performed. After forming second photoresisist pattern 26\nin the same manner as in Embodiment 1, booron is ion- ~\nimplanted at a dosage of l.ixlO'3 aLcrns1cm~i2 and at an\nacceleration energy such that the boron penetrates first and\nsecond oxide layers 21 and 23 and silicon nithtide layer 22,\nfor example, at an acceleration voltage of 240) Xcv.\nFIG. 14 is a sectional view illustrating a step p of secondly 10\nimplanting a first conductivity type impurity. AAfter the step\nof FIG. 1.3, boron is ion-implanted at a dose of 00.5~l0'~ and\nat an acceleration energy such that the boroon penetrates\nsilicon nitride layer 22 but not second oxide lay~er 23, Ic., at\nan acceleration voltage of 130 KeV. Thereafter, r. in the same\nmanner as in Embodiment 1, after removing sciecond photo-\nresist pattern 26, a drive-in step is performoed, to thus\ncomplete first (pocket) P-well 27 of the cell arnray area and\nsecond P-well 27A of the peripheral circuit reg~gion.\nThereafter, subsequent steps are performed i in the same\nmanner as described with respect to FIGS. 7 thlirough 12 of\nEmbodiment 1, so the detailed descriptions therireof omitted.\n\nEmbodiment 3\nFIG. 15 is a sectional view illustrating a method for\nmanufacturing a NAND-structured EEPRCOM device\naccording to a third embodiment of the presentit invention.\nFIG. 15 is a sectional view illustrating a step p of implant- ~\ning a first conductivity type impurity. In Embod\ufffds 1 and\n, the first conductivity type impurity is implannied via two\nimplantation steps. However, in the present emboodiment. the\nfirst conductivity type impirity is implanted jusist once.\nAfter forming second phocoresist pattern 26 armd removing ~\nthe exposed second oxide layer 23 by the wet-etetching in the\nsame manner as in- Embodiment 1, for formingg first P-well\nand second P-well 27A, boron is implanted \ufffd at a dose of\nl.5xlO'3 atomslcm2 and at an acceleration enezpgy such that\nthe boron penetrates silicon nitride layer 22.. for r example, at\nan acceleration voltage of 240 KeV. With ck\ufffdanging the\nthickeess of silicon nitride layer 2Z the doped aamount of the\nimpurity (that is, boron) which forms second I P-well VA\nmay be controlled.\nThereafter, the subsequent steps ste perforirmed in the as\nsame minr~ as in- Embodiment 1 (i.e, thos4se shown in\nFIGS. 7 through 12).\n\nEmbodiment 4\nFIGS. 1~ sad 17 ste sectional views rllusuatuang a method\nfor m-~.rIn44 a NAND-structured EEPRROM device\naccordin io a fourth embodiment of the preserant invention.\nFIG. 16 Is a sectional view Illustrating a stctep of firstly\nimplanting a first conductivity type im~nity. Aftfter perform- ~\ning the step of P10.4 of Embodiment I * second.d phocoresist\npattern 26 is formed in- the same manner as in EEznbodiment\n. Thereafter, boron is ion-implanted at a dosage e of l.5x10'3\natoms/cm2 and at an acceleration energy ,uchli that boron\npenetrates silicon nitride layer 22 but not aecondd oxide layer 60\n, for example, at an acceleration voltage of 2240 KeV.\nP10.17 Is a sectional view illustrating a step a of secondly\nimplanting a first conductivity type impurity. AMer the step\nof FIG. 16, the exposed portion of second oxidde layer 23 ii\nremoved by the wet-etchin\ufffdand then boronn is ion-Ian- 63\nplanted at a dosage of l.OxlO ~ and at en accelerstation energy\nsuch that boron- penetrates silicon nitride 1a~yer 22, for\nexample, at an acceleration energy of 240 KeV. Thereafter,\na drive-in step is performed in the same manner as in\nEmbodiment 1, to thereby form first P-well 27 and second\nP-well VA.\nThe subsequent steps are performed in the same manner\nas those of FIGS. 7 through 12. Accordingly, the detailed\ndescriptions thereof are omitted.\nEmbodiment 5\nFIG. 18 is a sectional view illustrating- a method for\nmanufacturing a NAND-structured EEPROM device\naccording to a fifth embodiment of the present invention.\nIn the present embodiment, controlling the concentration\nof the impurity for forming first P-well 27 and second P-well\n~ VA separately and independently, is 5 unnecessary.\nFIG. 18 is a sectional view illustrating a step of implant-\ning a first conductivity type impurity. After performing the\nstep of FIG. 4 of Embodiment 1. nitride layer 22 (which is\nused as an inti-oxidative Layer) and first oxide layer 21 are\nremoved by wet etching, thereby exposing the whole surface\nof semiconductor substrate 20. Thereafter, an oxide layer\nB is grown to a tltickneas of about 500 A via a conven-\ntional thermal oxidation. Then, second photoresist pattern 26\nis formed in the same manner as in Embodiment 1. to\nthereby expose the portions of oxide layer 23B where first\nP-well and second P-well are to be fanned.\nNext, boron is ion-implanted at a dosage of l.5x1013 and\nat an acceleration energy such that boron penetrates oxide\nB.\nThe subsequent steps are performed in- the same manner\nas those of FIGS. 7 through 11 Accordingly, the detailed\ndeaaipcions thereof are omitted.\nThe NAND-stnictrrred EEPROM device according to the\npresent invention comprises ~PROM cells formed on a\npocket P-well. The impurity co~ntralion of the pocket\nP-well is cootrofled independently form the P-weU formed\nin the peripheral circitit region. Therefore, an EEPROM\ndevice having two P-wells in- the cell array region and the\nperipheral circuit peripheral circuit region of which the\nconcentrations may controlled according to device charac-\nteriatics and independently from each other, can be obtained.\nAccording to one embodiment of the present invention, an\nNMOS n~n~ of the peripheral circuit region which is\noperated * a high voltage is formed dir~ly on the P-type\nsemiconductor substrate. Therefore, the resistance thereof\nagainst the high voltage is enhanced. Further; an NMOS\ntransistor of the peripheral circuit region which is operated\nat Von, is formed on the P-well of the peripheral circuit\nregion the characteristics of which are controlled indepen-\ndently from the PlO well of the cell army region. This\nenhances the punch-through characteristic.\nAlso, according to a method for manufacturing a NAND\nstructured E~ROM memory device, using only a twice-\nperformed pbocolithography process may separately and\nindependently control the characteristics of the P-wells of\nthe cell array region and the peripheral circint region.\nTherefore, the characteristics of the P-wells are differenti-\nated so that the transistor characteristic of the peripheral\ncircuits can be differentiated.\nConsequently, the present Invention can provide a non-\nvolatile semiconductor memory device having an excellent\ncharacteristic in spite of the shortened steps of the whole\n\nWhile the present invention has been particularly shown\nand described with reference to particular embodiments\n,514,889\n\nCase 9:02-cv~0005&JH Document 20 F~ed 04/03/2G02 Page 73 of 127\n,514,889\nthereof, it will be understood by those skilled in tithe art that\nvarious changes in form and details may be effectcted therein\nwithout departing from the spirit and scope of thee invention\nas defined by the appended claims.\nWhat is claimed is: 5\n. An EEPROM semiconductor memory devicce compris-\ning:\na semiconductor substrate having a first conducw*ivity type,\nsaid semiconductor substrate being divided I into a cell\narray region and a peripheral circuit region~ 10\na first impurity-doped region having said first c coriductiv-\nity type formed in a first surface portioun of said\nsemiconductor substrate in said cell array reegion;\na second impurity-doped region having a seconjnd conduc-\ntivity type formed in- said first surface portition of said\nsemiconductor substrate in said cell array retgion, said\nsecond impurity-doped region enclosing said first\nimpurity-doped region;\na memory cell comprising:\na memory source region and a memory drrrain region\nformed on a surface portion of said first ;t impurity-\ndoped region, and\na floating electrode formed on said first impusirity-doped\nregiooandacontrolelectrodeformedonisaidfloat- ~\ning electrode;\na third impurity-doped region having said flrsrst conduc-\ntivity type formed in a first surface poniaon in said\nperipheral circuit region of said semiconduluctor sub-\n\na first MOS transistor comprising:\nfirst source and drain regions formed in- irespective\nsurface portions of said third impunty-dop\ufffd region.\nand\na first gate electrode formed on said third I impurity- 35\ndoped regioe; a second MOS transistor cmomprising\nsecond source and drain regions formed c directly in-\nrespective second surface portions in saraid periph-\neral circuit region of said semiconductorir substrate,\nand\na second gate electrode formed on said seramiconduc-\nicr substrate;\na fourth impurity-doped region having said aencond con-\nductivity type and being formed In a thirird wrface\nportion in- said peripheral th~niit region of a said semi-\nconductor anheaale and\na third MOS transistor compising\nthird source and drain regions formed i respective\nsusfane portions of said fourth impurrity-doped ~\nreglc~ and\na t~ ~ electrode formed on said fourth h impurity-\n- regi~\n. 1~ ~OM semiconductor memory devitice accord-\ning to claim 1. wberein said first and second MOS il transistors\nare NMOS transistors, and said third MOS transisistor is a\nPMOS\n. The EEPROM semiconductor memory deviace accord-\ning to claim 1, wherein a first gate insulating fllilm of said\nsecond MOS transistor is thicker than a second ~ gate insu-\nlating film of said first MOS transistor.\n. The EEPROM semiconductor memory device accord-\ning to claim 1, wherein said second MOS transistor is\nformed between said first MOS transistor and said third\nMOS transistor.\n. The EEPROM semiconductor memory device accord-\ning to claim 1, wherein a first impurity concentration of said\nfirst impurity-doped region is controlled independently from\na second impurity concentration of said third impurity-\ndoped region.\n. The EEPROM semiconductor memory device accord-\ning to claim 1. wherein said first conductivity type is P-type\nand said second conductivity type is N-type.\n. An EEPROM semiconductor memory device coinpris-\ning:\na P-type semiconductor substrate which is divided into a\ncell array region and a peripheral circuit region;\na first P-well formed in a surface portion in said cell array\nregion of said semiconductor substrate;\na first N-well formed in- said surface portion in- said cell\n~ array region of said semiconductor substrate, said first\nN-well enclosing said first P-well;\na memory cell comprising:\na memory source region and a memory drain region\nformed on a surface portion- of said first P-well.\na floating electrode formed on- said first P-well, and\na control electrode formed over said floating electrode;\na second P-well formed in a first surface portion of said\nperipheral circuit region of said semiconductor sub-\na first NMOS transistor comprising:\nfirst source and drain regions formed in- respective\nsurface portions of said second P-well, and\na first gate electrode formed on said second P-well;\na second NMOS transistor cornpnsing\nsecond source and drain regions formed directly ins\nsecond surface portion of said peripheral circuit\nregion of said semiconductor substrate, and\na second gate electrode formed on said second surface\nportion of said peripheral circuit region of said\nsemiconductor substrate;\na second N-well formed in- a third surface portion of said\nperipheral circuit region of said semiconductor sub-\nstrate; and\na PMOS transistor comprising:\nthird source and drain regions formed in- a surface\nportion of said second N-well, and\na third gale eIe~ode formed on said second N-welL\n. The EEPROM semiconductor memory device accord-\ning to claim 7, wherein said first N-well and said second\nN-well are formed substantially simultaneously, and said\nfirst P-well and said second P-well are formed substantially\nindependently.\n. The EEPROM semiconductor memory device accord-\ning to claim 1, wherein said first impurity-doped region and\nsaid third impurity-doped region are formed substantially\nsimultaneously, and said second impurity-doped region and\nsaid fourth impurity-doped region are formed substantially\nindependently.\n\n* * * * *\n\nCase 9:02-cv~0005&JH Document 20 F~ed 04/03/2e02 Page 74 of 127\n\n(541 NONVOLATILE SEMICONDUCTOR\nMEMORY\n\n(75] Inventors: Kang D. Suh, Ahnyang; Jin K. Kim,\nSeoul; Jeotig H. Chol, Kwacheon, all\nof Rep. of Korea\n\n[73] Assignee: Samsung Electronics Co., Ltd.,\nSuwon, Rep. of Korea\n\n[21] AppI. No.: 441,477\n\n[22] Flied: May 15, 1995\n\nRelated U.S. Application Data\n(62] Division of Set No. 171,300, Dcc. 22, 1993, Pat. No.\n,473,563.\n\n(30] Foreign Application Priority Data\nIan. 13. 1993 (KR] Rep. of Korea ......._...._~.. 390/1993\n\n\n[51] tnt. a.6 .~ ~_......._ ... GIIC 16100\n\n[52] US. CL .._..._.....-__-. 365/18533; 365/185.29;\n/218\n[58] Field of Search .......__~_....-..-.. 365/185,218,\n/900, 185,29, 18533\n\n[56] References Cited\n\nU.S. PATENT DOCUMENTS\n,811,294\n/1989\n\nKobsyssin 365/185.22\n,949,309\n/1990\n\nRan 365/185.33\n,047,981\n/1991\n\nGill at a!. ...._..... 365/185.33\n.053,990\n/1991\n\nKreifels .__._ 3641900\n,126,808\n/1992\n\nMonlalvo et a! ..._... 365118533\n,185,718\n/1993\n\nRinerson it aL 365/185.33\n,191,556\n/1993\n\nRsdjy 365/185.33\n,245,570\n/1993\n\nFazio at aL - 365/18533\n,270,980\n/1993\n\nPathak at aL 365/11533\n,297.081\n/1994\n\nChifla 365/185\n.408.429\n/1995\n\nSaw~ 365/183.33\n/1992 Germany\n-17445 11/1991 R~. of Korea.\n/1993 tinted Kingdom.\nOTHER PUBUCATIONS\nMonodomi et al. \"New Device Technologies for 5V-Only\nMb EEPROM With NAND Smicture Cell\", CH2528-X/\n/0000-0412 IEEE (1988) pp. IEDM 88-4l2.-IEDM\n-415.\nKirisawa et al, \"A NAND Structured Cell with a new\nProgramming Technology for Highly Reliable 5V-Only\nFlash EEPROM\", 1990 Symposium on VLSI Technology, 4\nJun. 1990, CH 2874-6, 90/0000-0129 1990 IEEE, Hono-\nlulu, US pp. 129-130.\n(List continued on next page.)\n\nPnmary Examiner-Tan T. Nguyen\nAttorney, Agent, or Firm-Cushman. Darby & Cushman,\nLLR\n(57] ABSTRACT\nA nonvolatile semiconductor memory device comprising an\narray of cell units, each cell unit including ax least one\nmemory transistor which has a floating gate and a control\ngate, the array being divided into a plurality of memory\nblocks each having a certain number of cell units. A selected\nmemory block is erased by an erase voltage applied to a\nsemiconductor substrate while unselected memory blocks\nare prevented from erasing by capacitive coupling of the\nerase voltage to floated word lines connected to control gates\nof memory transistors of the unselected rn-emory blocks. In\na program inn-dc where a program voltage is applied to a\nselected. word line of a selected memory block and a pass\nvoltage is applied to unselected word lines of the selected\nmemory block., channel regions and source and drain junc-\ntions of memory transistors of cell units in the selected\nmemory block are charged to a program inhibition voltage.\nChannel regions and source and drain junctions of cell units\nassociated with memory transistors programmed to the other\nbinary data are discharged to be programmed while those of\ncell ~ta associated with nooprogrammed memory Umeis-\ntors are i~r~~n~d to the program inhibition voltage to\nprevent programming.\n\nUnited States Patent [191\nSuh et al.\n\nI lOll lUll ll 11111 OIl 11111 11111 I.~ illIl 11111 11111 11110 III 11111 Ill\nUS00554.6341A\n\n(11] Patent Number: 5,546,341\n(451 Date of Patent: Aug. 13, 1996\n\nFOREIGN PATENT DOCUMEIITS\n/1993 Eampean Pit. Off..\naalms, 18 DrawIng Sheets\n\nCase 9:02-cv-0005&JH Document 20 F~ed 04/0312-e02 Page 75 of 127\n,546,341\nPage 2 ____________ __________\n\nOTHER PUBUCATIONS\n\nlwata ex al., \"A High-Density NAND EEPROM with\nBlock-Page Programming for Microcomputer Applica-\ntions\". IEEE Journal of Solid-State Circuits. vol. 25, 2, Apr.\n, pp. 417-423.\n\nMomodorni et al, \"A 4-Mb NAND EEPROM with Tight\nProgrammed V1 Distribution\", IEEE Journal of Solid State\nCircuits, vol. 26, No. 4. Apr. 1991. pp. 492-495.\nEndoh eta! \"A study of high performance NAND stnicturai\nEEPROMs\", IEICE Transactions on Electronics, vol. E75C.\nNo. 11, Nov. 1992, Tokyo, JP pp. 1351-1356.\n\nCase 9:02.-cv-0005&jH\n\nDocument 20 F~ed 04/03/2602\n\nPage 76 of 127\n\nU.S. Patent\n\nAug. 13, 1996\n\nSheet 1 of 18\n,546,341\n\nCSL-\nSOURCE 1\nL[NEDRMNG I-\nCIRCUIT\n\nCOLUMN DECODER AND\nSELECTION CIRCUIT\n\n\n. . .\n\n\nINPUT/OUTPUT BUFFER\n\nFIG. 1\n-\n\nBLOCK\nSELECTION\nCONTROL\nCIRCUIT\n\n\n\nBK 1\n\n\n\nBK2\n\n\n\nBK1 024\n\n\n- ~BL3\n~-BL2\n\n* ..\nL2048\n\nH CGL8\nCGL1-I I\nNCGL2\n\np\n\nBL1-\n\nCONTROL\nGATE DRIVING\nCIRCUIT\n-~(\n~\n-\n\nDATA REGISTER AND SENSE AMP\n\n-10\n\n\n-12\n\n\nH\n\n\n-16\n\n- I I ~ I\n\n\nPROGRAMMING\nDETERMINA11ON\nCIRCUIT\n\n\n\nI\n\n\nA\n\nA\n\nA\n\nA\n\nA\n\nI/O 1\n\nI/O 2 I/O 3\n\n- I/O 7 I/O 8\n\nCase 9:02-cv-0005&JH Document 20 F~ed 04/03/2602 Page 77 of 127\n,546,341\n/CB&.(A.=1P2 ~8)\n\nSGL1-1\nBT 1\nCCL 1\n\n~ M27~\nCGL3'.-~----~- ~71l\nCGL4~-~~_ft~_ ____~7~\nCGL5-~---~- ~~7ll\nCGL6~-~---~-- ~~~7lI\n\nCGL7~-~-- ---;;;711\nCGL8~-~---------~1\nSG Li -2 ~.-~---~- -----\nT101 ST2~\nSG L2- 2-~--~--\nCGL8~-~----I--\nM8~\nCGL7~------Hl~\nCGL6~------HI\nCGL5~-~---~I- -HI\nCGL4~----HI\nCG L3.-.-~----T[-\nCCL2\"-~-----I--\n\n\nSGL2-\n\n\nBSC2342 BL~-1I BLL-2I\n_____ - _______________ - I - I --\n\nU.S. Patent\n\nAug. 13, 1996 Sheet 2 of 18\n\nST 1\n\nFIG. 2a\n\nCase 9 :02.-cv-00058-.j H\n\nDocument 20 F~ed 04/03/2002\n\nPage 78 of 127\n\nU.S. Patent\n\nAug. 13, 1996\n\nSheet 3 of 18\n,546,341\n\n\nI/OL\n\n``\nCOLUMN\nDECODER\n\n/\njINPUT BUFFERF26\n\n\nI BUFFER F281\n.J OUTPUT ______\n\nFIG. 2b\n\nCase 9:02-cv-0005~JH Document 20 F~ed 04/03/2602\n\nPage 79 of 127\n\nU.S. Patent\n\nCSL\n\nAug. 13, 1996\n\nSheet 4 of 18\n\n\nWL1\n\n\nWL7\n\n\nWLB\n\n\nSL2\n,546,341\n\nr~\n\nSL1\n\n\nFIG. 3\n\nCase 9:02-cv-0005$~JH Document 20 F~ed 04/03/2662 Page 80 of 127\n\nU.S. Patent\n\nAug. 13, 1996\n\nSheet 5 of 18\n,546,341\n\n(0 ~-\nN N\n\nOZ1\nN\n\nCase 9:02-cv-OOO5~jH\n\nDocument 20 H led 04/03/2662\n\nPage 81 of 127\n\nU.S. Patent\n\nAug. 13, 1996\n\nSheet 6 of 18\n,546,341\n\n\n~C)\n(I,\n\nE\n~\n>\n\n-j\nU)\n\nC')\n\na-\n>\n\nN\n\naD\n\n\n(`4\n\n\n/\n\nN\n\nN\n~4~j\n\n(`4\n\n\n(0\n(`4\n~~\n\n\n-J\n(1)\n\n\n\nU-~\n~\n\n(0\n\nto\n\nto\n(`4\n\nCase 9:02-cv-QOQ5$~jH Document 20 HIed 04/03/2002\n\nPage 82 of 127\n\nU.S. Patent\n\n\naD\n\n\nN\n\nII\n..~\n\nAug. 13, 1996\n\nSheet 7 of 18\n,546,341\n\n(`4\no aD\n\naD\nN\n\nco\n\naDO)1...\n\nLL~..\nCase 9:02-cv-0005$JH Document 20 HIed 04/03/2002\n\nPage 83. of 127\n\nU.S. Patent\n\n\nPGM\n\nAug. 13, 1996\n\nSheet 8 of 18\n\n\nVpi\n,546,341\n\n\nL\n\nVcc\nH\nPGM\n\n\n/\n\nFIG. 7\nFIG. 8a\nFIG. 8\n\nCase 9:02-cv-0005~$-JH Document 20 HIed 04/03/2002\n\nPage 84 of 127\n\nU.S. Patent\nAug. 13, 1996\n\n\n\ufffdH\n\nSheet 9 of 18\n,546,341\n\nFIG. 86\n\n\nERA\n\nS LE ~ 06\n\nPGM\n\n\nFIG. 8c\n\n\nTO 162\nCase 9:02-cv-OOa5B-jH Document 20 HIed 04/03/2002\n\nPage 85 of 127\n\nU.S. Patent\n\nAug. 13, 1996\n\nSheet 10 of 18\n,546,341\n\nFP1\nFP2\nFP3\nFP4\n\nFP5\nFP6\nFP7\nFP8\n\nFIG. 9a\n\nPDS\n\nVcc\nsupH\n\n-218\n-220\n\n(L=1,2 `8)\n~\nSEP\n\n/4\n\n\n/\n\n\nFIG. 9b\n\nFIG. 9\n\nCase 9:02-cv-000~-JH Document 20 HIed 04/03/2002 Page 86 of 127\n\nERA\n\nPGM\n\n~LE\n\nVpgm\n\nVpas\n\n\ufffd\n\nXd\n\nBLK\n\nDS\n\nVera\n\nDCB\n\nSBL\n\nAug. 13, 1996 Sheet 11 of 18 5,546,341\n\nU.S. Patent\nV\nWE\n____ 5V\nov\n____ 5V\n\nFIG. 10\n\nCase 9:02-cv-0005$-JH Document 20 HIed 04/03/2002 Page 87 of 127\n\n- 5V\nWEov\n____ 5V\n\n\nPGM\n____ 5V\n\nSLE\n- 5V\nXd\n~5V\nBLK\n- 5V\nDS OV\n____ 5V\n\nERA\nV\n\ufffd\nV\nVpgm\n\nby\nVpas\nOv\n.7V\nVpi\nOV\nV\nov\nV\nSBL\nV\nDCB\n\nAug. 13, 1996\n\nSheet 12 of 18\n,546,341\n\nU.S. Patent\n\nFIG. 11\n\nCase 9:02~-cv~0005&JH Document 20 HIed 04/03/2002 Page 88 of 127\n\n\nU.S. Patent Aug. 13, 1996 Sheet 13 of 18 5,546,341\n\n\nSBL~J\n\n\nDCB~\n\n\n_5V- I\nDSov\nV I\n\ufffd\nV I\n\ufffd1\n\n\n\ufffd\nFIG. 12\n\nCase 9:02~-cv~0005$-Jft Document 20 HIed 04/03/2002-.. Page 89 of 127\n\nU.S. Patent\n\n\nCGL1\nCGL2\nCGL3\nC G L4\nCGL5\nCGL6\nCGL7\nCGL8\nUSGL~.\n\nAug. 13, 1996\n\nSheet 14 of 18\n,546,341\n\n(~=1,2,3 ,512.)\n-i' BSC1 10\n\nLSGLt\n\nFIG. 13a\n\nCase 9:02~-cv~0005$-J~ Document 20 HIed 04/03/2002\n\nPage 9Oof 127\n\nU.S. Patent\n\nAug. 13, 1996\n\nSheet 15 of 18\n,546,341\n\nLL~) ..~\n- 0 0\nC_fl : U) C_f)\n\nN\n~ ND\n\n~- ND\n< 1\nJi\n\nE\na-\n>\nU')\nND\nND\n.~\n< ND\n(0\nND\n\n(`1\nN')\n<\n\nL'-\n<\n\n\nND\n\n(N\n\nI 0\nI-jo\n>\n~\n\nND\n\n(`4\nND\n\n(`1\n(`.1\nLi,\n\nQ-GQ~\n\nCase 9:02~-cv~0005$-J+-l Document 20 HIed 04/03/200~\n\nPage 91 of 127\n\nU.S. Patent\nN)\n\n(0\n\n\n(0\nN\nN)\n\n\nc\\1\n(0\n\nAug. 13, 1996\n\nSheet 16 of 18\n\n\n-J\n(1)\nC)\n-J\n,546,341\n\n-J\n(~f)\nC)\n=\nN\nN)\n\nN\n\n-S\n<\n\nCase 9:02~-cv~0005$4H Document 20 HIed 04/03/200~ Page 92 of 127\n\n\nU.S. Patent Aug. 13, 1996 Sheet 17 of 18 5,546,341\nV\ni~OV~ I\nV\nOv I.\n\n____ 5V I\n\nERA ________________________\n\n___ 5V-\n\nPGM\nV-\nVpgrn\n\nI I\nV F\nVpas\nV -~\n\ufffd I\nV-\nOV I1[\ni I\n\n___ 5V\n\n\nOv I\n\n- -\n\n\noV\nV\ncv lit\nVera ____ ____\nV _ LL\nDCB I I__________________\nv-~\n\n~1 ~2 13 1415\n\n\nFIG. 16\n\nCase 9:02~-cv~0005$-d-H Document 20 HIed 04/03/2004~ Page 93. of 127\n\n\nU.S. Patent Aug. 13, 1996 Sheet 18 of 18 5,546,341\n\n\n_5V F\nWEm\n\n____ 5v\n\n\nPGM ov\n\n\nERA\nR ~Ullhi ___ -\nV\nVpgm ______ ___\n\n\nby\nVpas ____ __ -\n\n\nOi I\n\n\nSBL~ I __ -\n\nDCB~ ii\nFIG. 17\n\nCase 9:02-cv-0005$-~J-H Document 20 HIed 04/03/200a Page 94 of 127\n.546,341\nNONVOLATILE SEMiCONDUCTOR\n?V~MORY\n\nThis is a division of application Ser. No. 07/171.300,\n\nfiled Dcc. 22, 1993. now U.S. Pat. No. 5,473,563. 5\n\nFIELD OF THE INVENTION\nThc present invention relates to electrically erasable and\nprogrammable nonvolatile semiconductor memories and.\nmore particularly, but not exclusively, to electrically eras-\nable and programmable nonvolatile semiconductor memo-\nries with NAND structured cells.\n\nBACKGROUND OF THE INVENTION\nVarious systems controlled by recent computers or micro-\nprocessors require the development of an electrically eras-\nable and programmable read-only memory (hereinafter\nreferred to as a EEPROM) of a high density. Particularly, ~\nsince the use of a hard disk with a rotary magnetic disk as\na secondary storage occupies a relatively large area in a\nportable computer system such as a battery-powered com-\nputer system of notebook size, system designers take much\ninterest in the development of EEPROMs of high density 25\nand high performance occupying a smaller area. To achieve\na high density EEPROM, it is a major problem to reduce the\narea occupied by memory cells. To solve such a problem, an\nEEPROM has been developed which contains NAND stoic-\ntured cells being capable of decreasing the number of 30\nselection transistors per cell and contact holes coupled with\na bit line. Such a NAND structured cell is disclosed in the\nIEDM, pp 412 to 415, 1988 under the title of ~`NEW\nDEVICE TECHNOLOGIES FOR 5V-ONLY 4 Mb\nEEPROM wmi NAND ~UCflJRE CELL\". This 35\nNAND structured cell (hereinafter referred to as aNAND\ncell unit or a NAND cell) is comprised of a first selection\ntransistor whose drain is connected to the corresponding bit\nline via a contact hole; a second selection transistor whose\nsource is connected to a common source line; and eight 40\nmemory transistors whose channels are connected in series\nbetween the source of the first selection transistor and the\ndrain of the second selection transistor. The NAND cell is\nformed on a p-type semiconductor substrate, and each\nmemory transistor includes a floating gale layer formed on 45\na gate oxide layer over a channel region between its source\nand drain regions and a control gate layer separated from the\nfloating gale layer by an intermediate insulating layen Th\nprogram of write a selected memory transistor in the NAND\ncell, an operation af simultaneously erasing all mensosy 50\ntransistors ther~ an~t be followed by the programming\nopcration. The el~laneous ensure ii performed by apply-\ning 0 volta to the bit line said raising the gate of the first\nselection transistor and control gates of all memory transis-\ntors to 17 volts. This causes all memory transistors to be 55\nchanged into enhancement mode transistors which are\nassumed as binary logic \"I\" programmed transistors. Th\nprogram a selected memory transistor to a binary logic\"0\"\nvolts are applied to the bit line, the gate of the first\nselection transistor and control gales of memory transistors 60\nbetween the first selection transistor and the selected\nmemory transistor, while 0 volts are applied to the control\ngate of the selected memory transistor, control gates of\nmemory transistor between the selected memory transistor\nand the common source line, and the gate of the second es\nselection transistor. Thus, the selected memory transistor is\nchanged into a depletion mode transistor by the Fowler.\nNordheim tunneling (F-N tunneling) of holes from its drain\nto its floating gate. However, the problem of programming\nin this manner is that a portion of the gate oxide of the\nselected memory transistor is subjected to a stress induced\nby application of the high voltage to its drain, and the\npartially stressed gate oxide causes leakage current to flow.\nThis results in degrading more and more the data retention\ncapability of the memory cell according to an increase of the\nnumber of cycles of erasing and/or programming, thereby\nreducing the reliability of the EEPROM. To solve this\nproblem, an improved device structure, in which the NAND\ncells are formed on a p-type well region irnbedded in an\nn-type semiconductor substrate, and further improved eras-\ning and programming technologies utilizing the improved\ndevice structure arc disclosed in the symposium on VLSI\nTechnology,pp 129to 130, l990undcrthetideof\"ANAND\nSTRUCTURED CELL WITH A NEW PROGRAMMING\nTECHNOLOGY FOR HIGHLY RELIABLE 5V-ONLY\nFLASH EEPROM\".\nErasure of all memory transistors in this NAND call is\nperformed by applying 0 volts to all control gates and a high\npotentIal of 20 volts to the p-type well region and the n-type\nsubstrate, thereby uniformly extracting electrons from their\nfloating gates to the well region. As a result, each memory\ntransistor has a threshold voltage of about -4 volts which\nrepresents a state of depletion mode, ~e. a logic \"0\". To\nprogram a selected memory transistor in the NAND cell, a\nhigh voltage of 20 volts is applied to the gate of the first\nselection transistor and the control gate of the selected\nmemory transistor, while 0 volts are applied to the gate of\nthe second selection transistor, and an intermediate voltage\nof 7 volts is applied to control gates of unselected memory\ntransistors. If the selected memory transistor is to be written\norprograznmed into a logic \"1\", 0 volts are applied to the bit\nline connected with the NAND cell, thereby injecting elec-\ntrons into the floating gate of the selected memory transistor.\nThis results in causing the selected memory transistor to\nbecome enhancement mode. On the contrary, if the selected\nmemory transistor is to be programmed to a logic \"0\", a\nprogram inhibition voltage of 7 volts instead of 0 volts is\napplied to the bit line to inhibit the programming of the\ns~1ected memory transistor. Since such a programming\noperation uniformly ix~jects electroes from the p-type well to\nits floating gate via its gate oxide layer, the partial s~eu on\nthe thin gate oxide layer does not ocerir to a significant\ndegree, and the gate oxide leakage current may thus be\npreventedi\nHowever, when the memory capacity becomes high, such\nways of uniform erasing and programming cause problems\nin the case that system designers want to erase a portion or\na block of previously written or programmed memory cells\nin order to reprogram. In this case, a conventional approach\nis to simultaneously erase all memory transistors in a\nmemory cell array, IC. to carry out a flash erasure, and then\nto newly reprogram the content of all programs. Thus, since\nsignificantly reusable portioni or blocks of the memory\narray are simultaneously erased, the reprogramming not\nonly needs a long time, but also is inconvenienL It may be\nappreciated that such problems seriously occur when the\nmemory density becomes more higher. To solve these prob-\nlems, it is made possible only to erase all memory transistors\nin a selected memory block. However, in the case of an\nEEPROM using the above-mentioned improved erasing and\nprogramming techniques, to prevent the erasing of all\nmemory transistors in an unselected block, It is required that\na high voltage equal to an erase voltage or a high voltage of\nabout 18 volta or more be placed on their control gates.\n\nI0\n\nCase 9:02~-cv~0005$-J-H Document 20 F~ed 04/03/200a Page 95 of 127\n,546,341\nThus, this techoology has a drawback that a decoding circuit\nfor performing a block erasing operation becomes compli-\nrated in design. In addition, when the density of the\nEEPROM cells increases, an on-chip occupying area of the\ndecoder increases, thereby making it difficult to design the\ndecoder.\nAnother problem area of the prior art is that of program-\ning. To prevent the pr-ogramming of non-programmed\nmemory transistors, which must maintain previous data, of\nmemory transistors on a selected word line, it is required that\neach of the bit lines corresponding to the non-programmed\nmemory transistors be raised to the intermediate, i.e. the\nprogram inhibiting voltage, via a charge pump circuit con-\nnected thereto. In addition, when the memory capacity is\nincreased, the number of bit lines or the length of each bit\nline is increased. Consequently, it is necessary that a high\nvoltage generating circuit on the same chip for supplying the\nhigh voltages to the charge pump circuits has a high per-\nformance. Such a high voltage generating circuit and the\ncharge pump circuits give a problem in increasing the area\noccupied by the on-chip peripheral circuits.\nConventional EEPROMs include a page program mode\nfor high-speed programming. The page programming opera-\ntion is composed of a data loading operation and a program-\nming operation. The data loading operation comprises ~\nsequentially latching or storing data of a byte size from\ninput/output terminals to a data register. The programming\noperation comprises simultaneously writing the data stored\nin the data register into memory transistors on a selected\nword line via bit lines. The page programming technology ~\non an EEPROM with NAND cells is disclosed in the IEEE\nJOURNAL OF SOLID-STATE CIRCUITS, VOL 25, NO.\n, pp 417 to 423, APRIL 1990.\nConventional EEPROMs employ a programming verifi-\ncation technique to enhance their reliability. The verification ~\nmeans checking to determine if programmed cells are pro-\ngrammed so as to have desired threshold voltages. Tech-\nnologies of the programming verification may be classified\ninto an external verification technique controlled by a micro-\nprocessor and an internal verification technique performed ~\nby an on-chip verification circuiL The external verification\ntechnique is disclosed in the IEEE JOURNAL OP SOLID-\nSTATh CIRCUITS, VOL. 26, NO.4, pp 492 to 495, AprIl\nand US. PaL No. 5,053,990. The external verlficmlon\ntechnique has a problem in that it takes a predetermined long ~\nto determine if programmed cells are well programmed.\nIn addition, whenever reprogramming is performed after the\nfailure of the programming, It Is nec'~'y that the data\nloading operation ii performed again. However, the internal\nverifying techelqu~ baa an advantage that the programming\nverification Is ~u1oruied at a higher speed. The internal\nverifying `~qu- 1* disclosed in Korean Patent Laid Open\nNO. 9l-l74'~ aid US. PAT. NO. 4,811,294. In these\ndocuments, the ,utdcadon is performed in such a manner\nthat comparator n~is compare data stored in a data register\nwith data read out in pages from memory cells via sense\namplifiers. However, such a scheme employing comparator\nmeans increases the area occupied by on-chip peripheral\ncircuits.\nSUMMARY OF THE INVENTION\nIt is therefore an object of the present invention to provide\na nonvolatile semiconductor memory with NAND struc-\ntarred cells which can reduce the size of chip.\nIt is another object of the present invention to provide a\nnonvolatile semiconductor memory with NAND sznrctured\ncells which can reduce power consumption.\nIt is further object of the present invention to provide a\nnonvolatile semiconductor memory which performs an eras-\ning of selected one of memory blocks.\nIt is still further object of the present invention to provide\na nonvolatile semiconductor memory which is program-\nmable without application of a program inhibition voltage of\nhigh voltages on unselected bit lines in order to reduce a chip\nsize and power consumption.\nIt is another object of the present invention to provide\nmethods for block erasing and programing which are\ncapable of reducing on-chip occupying area and power\nconsumption in a nonvolatile semiconductor memory with\nNAND structured cells.\nIt is another object of the present invention to provide a\n~ nonvolatile semiconductor memory in which on-chip area of\nperipheral circuits can be reduced in size.\nit is further object of the present invention to provide a\nnonvolatile semiconductor memory in which over program-\nming can be prevented.\nAccording to an aspect of the present invention, a non-\nvolatile semiconductor memory includes, word lines formed\nover a surface of a semiconductor substrate; cell units\narranged on said surface to form an array, each said unit\nincluding at least one memory transistor which has source\nand drain regions formed in said substrate but separated by\na channel region, a charge storage layer formed over the\nchannel region, and a control gate formed over the floating\ngate and coupled to * corresponding one of said word lines,\nsaid array being divided into a plurality of memory blocks\neach having a certain number of call units; and means,\nresponsive to an address in a data erase mode, for applying\nan erase voltage to said substrate, and simultaneously float-\ning word lines of ~ory blocks unselected by said address,\nwhereby erasure of memory transistors of said unselected\nmemory blocks is prevented by capacitive coupling of a\npredetermined amount of said erase voltage to the word lines\nof said unselected memory blocks.\nAccording to another aspect of the present invention, a\nnonvolatile semiconductor memory includes, a semiconduc-\ntor substrate having a well region, memory transistors\nformed on the well region arid arranged in a matrix form of\nrows and columns. the memory transistors comprising cell\nunits each of which has a predetermined number of memory\ntransistors connected in senes, and first and second ternn-\nusia at its both ends, cell units in respective mows constitut-\ning a memory block, each memory transistor having source\nand drain regions formed in the well region but separated by\na channel region, a floating gate formed over the channel\nrcgiontostorcchargerepresentingbinarydata,andacontroi\ngaze formed over the floating gate; word lines each being\nconnected to control gazes of memory transistors in a\ncorresponding row; hit lines generally intersecting the word\nlines; a common source line; first and second selection lines\ngenerally in parallel with the word tines; first selection\ntransistors respectively connected between first terminals of\ncell units in each memory block and corresponding bit lines\nfor selectively connecting therebetween, gates of first selec-\ntion transistors associated with each memory block being\nconnected to a corresponding first selection line; second\nselection transistors connected between second terminals of\ncell units in each memory block and the common source line\nfor selectively connecting therebetwcen, gates of second\nselection transistors associated with each memory block\nbeing connected to a corresponding second selection line;\ndata register connected to the bit lines for providing binary\ndata to the bit lines, the register providing logic high level\n\nCase 9:02-cv~0005$-~H Document 20 F~ed 04/03/2002~ Page 96 of 127\n,546,341\nvoltages to bit lines associated with memory transistors\nprogrammed to one binary data of the binary data while\nproviding referenee voltages to bit lines associated with\nmemory transistors programmed to the other binary data\nthereof; and control means connected to the word lines and s\nthe first and second selection lines for applying a program\nvoltage to a selected one of word lines of a selected memory\nblock and pass voltages to unselected word lines of the\nunselected memory block while applying a logic high level\nvol tage to the first selection line associated with the selected\nmemory block and rendering nonconductive second selec-\ntion transistors associated therewith, whereby channel\nregions and source and drain junctions of memory t.ransis-\ntots in the selected memory block are capacitively charged\nto program inhibition voltages.\nAccording to another aspect of the present invention, a\nmethod for programming memory transistors in a row in a\nsemiconductor memory which comprises a semiconductor\nsubstrate; memory transistors formed on a surface of the\nsubstrate and arranged in rows and columns, the memory\ntransistors comprising cell units each of which has a prede-\ntermined number of memory transistors connected in series,\nand first and second terminals at its both ends, each memory\ntransistor having source and drain regions formed in the\nsubstrate but separated by a channel region, a floating gate\nformed over the channel region to store binary data, and a\ncontrol gate formed over the floating gate, cell units in\nrespective rows constituting a memory block; word lines\neach being connected to control gates of memory transistors\nin a corresponding row; bit lines generally intersecting the\nword lines, the first terminal of each of cell units of each\nmemory block being connected to a corresponding one of\nthe bit lines via a first selection transistor and a common\nsource line connected to the second terminal of each of cell\nunits via a second selection transistors, the method includes\nthe steps of applying * program voltage to a selected word\nline of a selected memory block and a pass voltage lower\nthan the program voltage to the remaining word lines\nthereof, while applying a logic high level voltage lower than\nthe .pass voltage to gates of first selection transistors asso-\nciated with the selected memory block and tendering non-\nconductive second selection transistors associated therewith,\nthe logic high level voltage corresponding to a logic high\nstate; sad applying a logic low level voltage corresponding\nto a logic low state to bit lines associated with memory\ntransistors programmed from one binary data to the other\nbinary data, while applying the logic high level voltage to bit\nlines associated w~b memory transistors net programmed.\nwhereby channel a~glons and source and drain junctions of\nthe nonprogr2i~ memory transistors are capacitively\ncharged to a voltage level between the logic high level\nvoltage and the program voltage so as to prevent program-\nming, while those of the programmed memory.\n\nBRIEF DESCRIPTION OF DRAWING\nFor a better understanding of the invention, and to show\nhow embodiments of the same may be carried into effect,\nreference will now be made, by way of example, to the 60\naccompanying diagrammatic drawings, in which:\nFIG. 1 shows a schcmaxic block diagram of as electrically\nerasable and programmable read-only memory according to\nthe present invention,\nFIG. 2 is comprised of FIGS. 2a and 2b: FIG. 2a ~\nillustrating thc arrangement of memory cells within first and\nsecond memory blocks associated with a k-tb colunm block,\nand transfer transistor arrays connected thereto; and FIG. 2b\nshowing an input/output buffer, a column decoder and\nselection circuit, a data register and sense amplifiers asso-\nciated with the k-tb column block;\nFIG. 3 shows a plan view of a pattern for one of a plurality\nof NAND cells constituting a memory cell array;\nFIG. 4 shows a cross-sectional view of the NAND cell\ntaken substantially along line lV-IV of FIG. 3;\nFIG. 5 shows a schematic circuit diagram of a block\nselection control circuit used in an embodiment of FIG. 2;\nFIG. 6 shows a schematic circuit diagram of a control gale\ndriving circuit used in embodiments of FIG. 2 and FIG. 13;\nFIG. 7 shows a schematic circuit diagram of a source line\ndriving circuit used in the embodiment of FIG. 2;\nFIG. 8~ shows a circuit diagram of a thstate inventer used\nin FIG. 2b;\nFIG. Sb shows a circuit diagram of a tristate NAND gaze\nused in FIG. 6;\nFIG. Sc shows a schematic timing circuit diagram for\ngenerating control signals $~ and $7 used in the block\nselection control circuit of FIG. 5;\nFIG. 9 shows a program determination circuit and is\n~ comprised of FIGS. 9a and 9b, in which FIG. 9a is a circuit\ndiagram showing a portion of the program determination\ncircuit and FIG. 9b is a circuit diagram showing a samuna-\ntion circuit,\nFIG. 10 shows a tinting chart of various control signals\nso used in a block erasing mode according to a first embodi-\nment of the present invention;\nFIG. 11 shows a timing chart of various control signals\nused ina programming mode according to the first embodi-\nment of the present invention,\n\" FIG. 12 shows a timing chart of various control signals\nused in a programming verification mode and a reading\nmode according to the first and modified embodiments of the\npresent invention;\nFIG. 13 is a circuit diagram showing a schematic modified\nembodiment and is comprised of FIGS. L3a and 2b, in which\nFIG. 13a is a circuit diagram illustrating an arrangement of\nmemory transistors within an i-tb ~ory block having\nshared word lines In the k-tb column block;\n~ FIG. 14 shows a schematic circuit diagram of a block\nselection control circuit associated with the modified\nensbodinamt of FIG. 13;\nFIG. 15 shows a schematic circuit diagram of a ground\nline driving circuit associated with the modified embodiment\nof FIG. 13;\nFIG. 16 shows a timing chart of various control signals\nused in a block erasing mode of the modified embodiment;\nand\nFIG. 17 shows a timing chart of various control signals\nss used in a programming mode of the modified embodiment\nIn the figures, like reference numerals denote like or\ncorresponding parts.\n\nOF THE\nPREFERRED EMBODIMENTS\nIn the following description, numerous specific details,\nsuch as memory cells, the number of NAND cells, the\nnumber of bit lines, the value of voltages, circuit elements\nand parts and so on, are set forth in order to provide a\nthorough understanding of the present invention. It will be\n\nCase 9:02-cv-0005$-JH Document 20 F~ed 04/03/2002- Page 97 of 127\n,546,341\nunderstood by those skilled in the art that other embodi-\nments of the present invention may be practiced without\nthese specific details, or with alternative specific details.\nThe term \"memory transistor\" as used herein refers to a\nfloating gate MOS FF1' having a source, a drain, a floating\ngate and a control gate. The term \"programming\" is used to\ndesathe the writing of data into selected memory transis-\ntors. The term `NAND cell charging\" is defined as the\ncharging of the channel and the~source and drain junction\ncapacitors of respective memory transistors constituting the\nNAN!) cell to a predetermined potential.\nIn the following description, symbols k and i arc respec-\ntively used for those parts associated with a k-th column\nblock and an i-th memory block. Symbol j represents a\nnotation associated with a j-th word line, is\nThe term \"ground potential\" (or like terms such as\n\"ground voltage\" or \"earth\" potential or voltage\" is used\nconveniently in this specification to denote a reference\npotential. As will be understood by those skilled in the art,\nalthough such reference potential may typically be zero\npotential, it is not essential that it is so, and may be a\nreference potential other than zero.\nAn example of an EEPROM of the present invention is\nfabricated by using CMOS manufacturing technologies on a\ncommon chip, in which depletion mode a-channel MOS\ntransistors each having a threshold voltage of -2 to -3 volts\n(hereinafter referred to as D-.type transistors), enhancement\nmode n-channel MOS transistors each having a threshold\nvoltage of about 0.7 volts (hereinafter referred to as n-chan-\nnel transistors) and p-channel MOS transistors each having\na threshold voltage of about -0.9 volts (hereinafter referred\nto as p-channel transistors) are employed.\nFIG. 1 illustrates a schematic block diagram of one\nexample of an EEPROM according to the present invention.\nFIG. 2 is composed of FIG. 2a and FIG. 2b in parallel\nrelationship with each other, and shows, for the convenience\nof illustration, only those elements associated with the k-th\ninput/output terminal tX)k, a memory cell array 10. input\nand output buffers 26 and 28, a column decoder 30, a column\nselection circuit 32. a data register and sense amplifier 12\nand a transmission transistor array 34-i which is connected\nwith the snemnry cell array 10 and coestitotes a portion of\na block selection control circuit 18. It should be noted th~\n~Iema'i~tt associated with the re~naining input/output terusi-\noats am-c identical to those associated with the ta'niinal I~\nReferring now to FIGS. 1 and 2. the memory cell array 10\nof the present E~'ROM is composed of NAND cells NU\narranged in * ~ix tbxm of 1,024 rows and 2,048 columns,\nand includes l,~4 ~ory blocks BK1 to BK1024 divided\nin a row direntlal. Each NAND ccliii composed of memory\ntransistors Ml ~ Ml whose drain-source paths are con-\nnected in scs4es between the source of a first selection\ntransistor ST1 and the drain of a second selection transistor\nST2. Gates of the first and second selection transistors ST1\nand ST2 and control gases of the memory transistors Ml to\nMS are respectively connected to first and second selection\nlines SLI and SL2 perpendicular to bit lines BLk-1 to\n,2,...,8) and word lines WL,1 to WLS. Thus,\nthe memory transistors Ml to MS are disposed at intersec-\ntions of the word lines WL1 to WLZ and the bit lines ELk-i\nto BLk-256. Drains of the first selection transistors ST1 are\nrespectively connected with corresponding bit lines, and\nsources of the second selection transistors ST2 are con-\nnected to a common source line CSL. Consequently, the\nmemory cell array 10 Is comprised of memory cells of a total\nof l,0244x2,048 (=16,777,216), and each memory block is\ncomprised of memory cells of a total of 8 x2,048 (=16,384).\nThe memory cell array 10 is divided into eight column\nblocks Bk (k=l,2,..,8) respectively corresponding to\ninpwloutput terminals 1/01 to I/OS, and each column block\nhas256biclinesorcotumnlineswhichareparallelina\ncolumn direction. Thus. each column block includes\nmemory cells totalLing 256 Kbit (=1 ,024x256),\nThe memory cell array 10 is formed on a p-well region in\na semiconductor substrate. FIGS. 3 arid 4 respectively show\na plan view and a cross-sectional view of one of the NAND\ncells NU constituting the memory cell array 10.\nReferring to FIGS. 3 and 4, the semiconductor substrate\nis of a p-type silicon monoa-ystalline material which is\ncut on the (1,0,0) crystal orientation at an impurity concen-\ntration of about 7xlO'4 atoms/cm3. A p-type well region 76\nwith an impurity concentration of about 2x1016 atoms/cm3\nis formed having a depth of about 4j.sm from a main surface\nof the substrate 72. The well region 76 is surrounded by\na n-type well region 74 of about Oum in depth with an\nimpurity concentration of about 5x1C~ atoms/cm3, Heavily\ndoped N4 regions SO tofl am formed on the main surface\nof the well region 76 and separated by each of a plurality\nof channel regions 94. One part of the N4 region ~ is a\ncontact region connected via a contact bole 96 to a bit line\n~ BLofametalmaterial.suchasanaluminum,whichextends\nover an insulation layer 112, and the other part of the N~\nregion 80 also serves as a drain region of the first selection\ntransistor STh The N'~ regions 82 to 90 serve as common\nsource-drain regions of two adjacent transistors of transis-\n~ torsl,MltoM8andSTlOnepartoftheN4regiOfl92\nis a source region of the second selection transistor ST2, and\nthe other part of the N4 region 92 serves as buried common\nsource line CSL. However, the line CSL may be a conductor\nlayer which is insulatively formed within the insulating layer\ncontacting with the N source region fl of the transistor\nST1 via a contact hole. Gate layers 9$ and 100 of a\nrefractory metal silicide material, such as a tungsten suicide.\neach of which has a thickness of about 1,500A, am respec-\ntively formed on gate insulating layers 102 of about 300A\n~ thickness, overlying channel regions of the first and second\nselection transistors ST1 and ST2.\nFloating gaze layers 104 of a polycrysialline silicon mate-\nrial am insulatively formed with a thickness of about i,ZOOA\non gate insulating layers 106 of thout boA iM~4n.53\n~ overlying 0kmwI regions 94 of memory transistors Ml to\nMl. respectively. Control gates 10$ of the same material and\nthfrfrn~a! as the gaze layers 98 and 100 are respectively\nformed over the floating gate layers 104 interposing inter-\nmediate insulating layers 100, such as ONO insulating\n~ layers of silicon dioxide-silicon nitride-silicon dioxide mate-\nrials, of about 250A thickness. The gate layers 9$ and 100\nand the control gate layers 108 axe respectively shared by the\nfirst and second selection lines SL1 and SL2 and word lines\nWU to WLS, Ic. conductor layers which are fabricated\n~ from the same material as the gate and control gate layers 98,\nand 108. The gate layers 98 and 100, control gale layers\n, floating gaze layers 104, the first and second selection\nlines SLI arid SL2, and word lines WL1 to V/LI are\ninsulated from one another with an insulating layer 112 of\n~ insulating materials. such as a silicon dioxide and aBPSG\nor a P5G.\nThebitlineBLis connected with thecontactregion SO via\nthe contact hole 96 and extends in a column direction on the\ninsulating layer lit The p-type well region 76 and the\nn.ypewellregion74areConflectedtoawelletectrodeil4\nin common via contact holes (not shown). An erasing\nvoltage is applied to the well electrode 114 in an erasing\n\nat\n\nS\n\nCase 9:02-cv~0005$-J*~ Document 20 F~ed 04/03/2002~ Page 98 of 127\n,546,341\noperation, arid a refarance potential, i.e. ground potential, is\napplied to the well electrode 114 in operations except the\nerasing operation, i.e. in programming, programming veri-\nfIcation and reading operations. However, the substrate 72 is\nalways at the reference potential. The memory cell may10 ~\nmay also be formed on a p-type well region formed in an\nn-type monocrystalline silicon substrate.\nRcturning now to FIGS. 1 and 2, the block selection\ncontrol circuit 18 serves to select a predetermined memory\nblock of the memory blocks BK1 to BK1024. and to provide to\ncontrol signals on control gate lines COL1 to CGL8 from a\ncontrol gale driving circuit 20 to word lines WL1 to V/LI in\nthe selected memory block according to various operation\nmodes, such as the erasing, programming, programming\nverification and reading modes. In FIG. 2a, illustration is\nmade of transfer transistor arrays 34-i constituting a portion\nof the block selection control circuit 18. Each of the transfer\ntransistor arrays 34-i includes transfer transistors BT1 to\nBTIO for connecting the first and second selection gate lines\nSGU-1 and SGLi-2 and control gate lines CGL1 to CGLS\nto the first and second selection lines SL1 and SL2 and word ~\nlines WLI to WLS. respectively.\nAccording to one feature of the illustrated embodiment of\nthe present invention, the block selection control circuit 18\nrenders noncociductive the transfer transistors associated\nwith unselected memory blocks in an erasing operation,\nthereby causing word lines in unselected memory blocks to\nbecome floating. In a programming operation, the block\nselection control circuit 18 renders conductive the second\ntransistor ST1 in a selected memory block, thereby charging ~\nthe program inhibition voltage from a source line driving\ncircuit 22 to channels and source and drain junctions of\nmemory transistors in the selected memory block.\nFIG. 5 shows a schematic circuit diagram for a block\nselection control circuit 18 connected to a transfer transistor ~\narmy 34-i of FIG. 2a. For example, in the case of 1=2. lines\nSGL2-2 and BSC2 of FIG. 5 are respectively\nconnected to lines SGL2-1, SGL2-2 arid BSC2 of the\ntransfer transistor army 34-2 associated with the second\nmemory block BK2 as shown in FIG. 2a. Thus, it should be so\nunderstood that though FIG. 5 shows, for the convenience of\nillustration, only a single circuit for selecting the i-tb\nmemory block BKI. the block selection control circuit of\nFIG. S corresponding to each of memory blocks BK1 to\nBK1024 resides on the present EEPROM chip am a periph- ~\nersi circuit.\nReferring now to FIG. 5, NAND gate 120 ii a row\ndecoder for receiving address sIgnals P1, QI and RI and a\nreact signal Xd. 1~ address sIgnals P1. QI and Ri are signals\npredecoded by suw ~ress signals from a predecoder (not\nshown) for predeluting row address signals A1,~X7 to Am.\nA~ which we ~_ from an address buffer for storing a\nrow address a~1 to a~ from external address input terminals.\nThe row decoder 120 provides a logic low state of 0 volts\n(hereinafter referred to as an \"L\" state or an \"L\" level) on a\nline 122 when selected, and outputs a logic high state of 5\nvolts (hereinafter referred to as an \"H\" state or an \"H\" level)\nthereon when unselected. Two input tenitinals of NAND\ngate 124 are connected to the line 122 and a signal BLK,\nrespectively. The signal BLK is a control signal for setting\nword lines WL1 to WLI to the reference potential before or\nafter the respective operations, as will be disc\"~'ed heroin-\nafter. The output of the NAND gate 124 is ctxwccted to the\nfirst selection gate line SGU-1 and to the block selection\ncontrol line BS(~ via a current path of D-type transistor 126\nfor inhibiting the transfer of a high voltage. The gate of the\ntransistor 126 is connected to a program control signal PGM\nfor maintaining an \"L\" state in a programming operation. A\ncharge pump circuit 128 is connected with the block selec-\ntion control line BSCI for providing, when the line BSCI is\nselected, a program voltage V,,,,, on the line BSCI by the\npumping of a clock $R itt the programming operation. The\ncharge pump circuit 128 is a known circuit comprised of\nn-channel transistors 130 and 1.32 and a MOS capacitor 134.\nTwo input terminals of NAND gate 136 are respectively\nconnected with an erase control signal ERA and the line 122.\nA transfer gate 148 composed of n-channel transistor 140\nand p-channel transistor 142 is connected between the\noutput of the NAND gate 1.36 and a connecting node 146.\nThe gate of n-channel transistor 140 is connected to a control\nsignal $6' and the gate of p-channel transistor 142 is con-\nnected to the complement signal of $~ via an inverter 138.\nThe current path of n-channel transistor 144 is connected\nbetween the node 146 and the reference potential, and its\ngaze is connected with a control signal 47. The sotrite-to-\ndrain current path of D-type transistor 150 for preventing the\ntransfer of a high voltage is connected between the node 146\nand the second selection gaze line SGLi-2, and its gaze is\nconnected to a control signal WE. A charge pump circuit 152\nhaving the same construction as the circuit 1.28 is connected\nto the second selection gate line SGU-2 for providing a pass\nvoltage V thereon during the programming operation\nwhen the ~e SGLI-2 is selected.\nFIG. Sc is a schematic circuit diagram for generating the\ncontrol signals $5 and 4.~ as used in FIG. 5. In an erasing\noperation or mode, 46 and 47 are all in \"L\" states, and in a\nNAND cell charging operation as will be discussed later. 46\nis in \"H\" stale and 4~ is in \"L\" state. In programming\nverification and reading operations, $6 is in \"H\" state and 47\nis in \"L\" state.\nFIG. 6 mustrates one of eight control gate driving circuits,\ni.e. the j-th control gate driving crzcut which constitutes\ncontrol gate driving means and is associated with the j-th\nword line. The outputs of the control gate driving circuits are\nrespectively connected to control gale lines CGL1 to CGL8\nwhich am respectively connected to word lines WLI to WL8\nvia transfer transistor arrays 34-i. From the point of view of\nreduction of total chip size, it would be preferable that the\nco~ol gaze driving circuits be provided in common in an\non-chip peripheral circuit so am to drive word lines of a\nselected memory block according to various operation\n\nReferring now to FIG. 6, NAND gate 154 is a row\ndecoder receiving row address signals A/A, A,/~ and\nA1~ from address buffer (not shown). The decoder 154\noutputs \"L\" state upon selection of the line CCLI while\nso outputting \"H\" state upon unselection thereof. The output of\nthe decoder 154 and a control signal PVF are respectively\nconnected to two input terminals of NOR gate 173. An\noutput signal 4, of the NOR gate 173 and its complement\nsignal j via an inverter 174 are provided to control a tiistate\nss NAND gate 158 and a verifying voltage generator 164. The\ncontrol signal PVF maintains an \"L\" stale only in a pro-\ngramming verification operation. Thus, in every operation\nexcepting the programming verification operation, the con-\ntrol signal PVF stays at \"H\" level, thereby causing the signal\n~\nin an \"H\" state. In the programming verification operation,\nif the line COLJ is selected, 4, becomes \"H\" state and its\ncomplement j becomes \"L\" state while, if the line CGLJ is\nunselected,$, becomes 1..\" state and 4, becomes \"H\" state.\nNAND gaze 156 inputs the output of the decoder 154 and\ncontrol signals DS and ERA, respectively. Two input termi-\nnals of the Instate NAND gate 158 are respectively con-\n\nCase 9:02-cv~0005$-J1H Document 20 F~ed 04/03/200~ Page 99 of 127\n,546,341\n\nII\nnected to an output line 160 of the NAND gate 156 and the\ncontrol signal PGM. The tnistate HAND gate 15$ illustrated\nin FIG. Sb is cnabled in response to 4,, at \"L\" level and\nat \"H\" level while becoming high impedance with 4,. at\n\"H\" level and 4, at \"U' level. Thus, in the programming\nverification operation, the NAND gate 158 stays in the high\nimpedance state only at the rime when the line CGLj is\nselected. The output of the NAND gate 158 is connected to\na connecting node 162 to which the verifying voltage\ngenerator 164 is connected. 10\nThe verifying voltage generator 164 is comprised of a\np-channel transistor 166 and n-channel transistors 168, 170\nand 172 whose current paths are connected in series between\nthe power supply voltage Vcc and the reference potential.\nThe gate of the p-channel transistor 166 is connected to a\nchip enable signal C~. and gates of the transistors 168 and `~\nare connected to the signal 4, from the NOR gates 173.\nDrain and gate of the transistor 172 are connected in\ncommon. The verifying voltage generator 164 is enabled by\n*~ at \"H\" level only in the programming verification opera-\ntion, thereby producing a verifying voltage of about 0.1 volts ~\nto the connecting node 162. Connected between the con-\nnecting node 162 and the control gate line CGLj is the\nsource-to-drain current path of D-type transistor 176 for\ninhibiting the transfer of a high voltage, the gate of which is\nconnected to the control signal PGM.\nTwo input terminals of NAND gate 178 are respectively\nconnected to the output of the NAND gate 156 and the clock\n$R from a ring oscillator (not shown). Between the output of\nthe HAND gaLe 178 and the gate of a driving n-channel\ntransistor 182 is connected a charge pump circuIt 180 which\nhas the same construction as the above-mentioned charge\npump circuiL Drain arid source of the transistor 182 are\nconnected to the program voltage V and the control gate\nline CGLJ, respectively. Inverter 1~receives the program ~\ncontrol signal POM, and the current path of D-type transistor\nfor preventing the transfer of a high voltage is connected\nbetween the output of the inventer 190 and the gate of the\ntransistor 182 which is connected to the control signal POM.\nAs will be discussed hereinafter, a circuit 196 which is\ncomprised of NAND gate 178, the charge pump circuit 180\nand the driving transistor 182 provides means for supplying\nthe program voltage V to the control gate line CGLJ\nwhen the line CCLI has ~n selected by row address signals\nA,/~, A,/~ and A10/X In a program mode.\nTwo input terminals of NOR gate 188 am respectively\nconnected to the output of the NAND gaze 156 and the clock\n$~. Between the output of the NOR gaze 188 and the gate of\na driving n.~an&'I transistor 184 Ii connected a charge\npump circuit lit Drain and source of the transistor 184 are\nrespectively ~ to the pass voltage ViM1 and the\ncontrol gate lIne ~Lj. Between a connecting node 202 and\nthe gale of the trssaistor 184 is connected the Q.ulent path of\nD-type transistor 194 for preventing the transfer of a high\nvoltage, the gate of which is connected to the control signal ~\nPGM. As will be discussed hereinafter, a circuit 200 which\nis comprised of NOR gate 18$, the charge pump circuit 186\nand the driving transistor 184 provides means for supplying\nthe pass voltage V,, to the control gate line CGLJ when the\nline CGLJ is selected by the row address signals in the ~o\nprogram mode.\nFIG. 7 shows a schematic circuit diagram of a source line\ndriving circuit which is connected in common to the com-\nmon source line CII.. as shown in FIG. 2a. The source line\ndriving circuit 22 is composed of an inverter 204 whose\ninput terminal is connected to the control signal PGM, a\nD-zype transistor 206 whose current path is connected\nbetween the output terminal of the inverter 204 and the\ncommon source line and whose gate is connected to the\ncontrol signal PGM, and a charge pump circuit 208 con-\nnected to the common source line CSL. The charge pump\ncircuit 208 serves to boost the common source line to a\nprogram inhibition voltage v,,4 in the program mode.\nThe input/output buffer 16 is comprised of the input buffer\nand the output buffer 2$ which are each connected to\ninput/output terminals. The input buffer 26 connected to\neach of input/output terminals 1/01 to 1/08 is a conventional\ncircuit for converting a byte of data (8-bit data) therefrom to\nCMOS level data and temporarily storing iL Output buffers\nare conventional circuits to simultaneously output 8-bit\ndata read out from the corresponding column blocks to the\ncorresponding input/output terminals.\nThe column decoder and selection circuit 14 of FIG. 2b is\ncomprised of the column decoder 30 and the column selec-\ntion circuit 32. The column selection circuit 32 associated\nwith each of the column blocks is comprised of transfer\ntransistors Ti to T256, source-to-drain paths of which are\nrespectively connected between a common bus line CBLk\nand lines DLk-l to DLk-256. Gates of the transfer transistors\nTi to T256 are respectively connected to parallel lines TLI\nto Th256 which are connected to the column decoder 30.\nThe column decoder 30 selects one of the lines TLI to\nTh256 in response to column address signals from address\nbuffers (not shown), thereby rendering conductive transfer\ntransistors connected with the selected line.\nThe data register and sense amplifier 12 is connected\nbetween the lines DLk-1 to DLk-256 and bit lines BLk-1 to\nBLk-256 which are associated with the corresponding col-\nunm block, as shown in FIG. 2b. In series between the bit\nlines BLk-1 to BLk-256 and nodes 36 are respectively\nconnected drain-to-source paths of D-type transistors 38 and\n. Gates of the D-type transistors 38 are connected to the\npower supply voltage Vcc to prevent the transfer of high\nvoltages Induced on the bit lines BLk-1 to BLk-256 in a\nblock erasing operation. Gates of the D-type transistors 40\nare connected to a control signal 4~ staying at \"If' level of\nabout 5 volts during programming. Between the nodes 36\nand nodes 42 are respectively connected drain-to-source\npaths of n-channel transistors 44. Gates of the transistors 44\nare connected to a control line SBL staying at \"H\" level\nduring programming. Between the nodes 42 and nodes 46\nare respectively onr~~.cted latches PBk-l to PBk-236 con-\nsziwting the data register which is referred to as a page\nbuffen Each of the latches is comprised of two investors\neross connected. The latches PBk-1 to PBk-256 serve not\nonly as a page buffer for temporarily storing data so as to\nsimultaneously write the dais into memory cells via respec-\ntive corresponding bit lines ins programming operation, but\nalso as verifying detectors for determining if the program\nwas well performed in a programming verification operation\nand as sense amplifiers for sensing and amplifying data on\nbit lines which is read out from memory cells in a reading\noperation. A thstate inverter 4$ and an n-channel transistor\nare connected in parallel between each of the nodes 42\nand its corresponding o~e of the lines DLk-1 to DLk-256.\nEach thstate inverter 4$, which is referred to as a clocked\nCMOS inverter. is enabled by a control signal 4. at \"H\" level\nwhile becoming high impedance by the signal $,~ at \"U'\nlevel. Thus, each of the Invuten 48 serves as a buffer amp,\nbeing enabled in progninmiing verification and reading\noperations. N-channel transistors 49 whose gates are con-\nmeted to a control signal 45 are transfer transistors for\ntransferring input data to the corresponding latches PBk-1 to\nPBk-256 in a programming operation. The tristate inventor\nCase 9:02-cv-00058-JH-~ Document 20 FHed 04/03/2002- Page 100 of 127\n,546,341\n which is used in the present embodiment is illustrated as\na schematic circuit diagram in FIG. 8a. Between each of\nnodes 46 and the reference potential are serially connected\ncurmot paths of n-channel transistors 50 and 52. Gates of the\ntransistors 52 are connected to a control signal 43, staying at s\n\"H\" level during a verification sensing period in a program-\nming verification operation and during a read sensing period\nin a rend operation. Gates of the transistors 50 are respec-\ntively connected to the nodes 36, and drain-to-source paths\nof n-channel transistors 37 are respectively connected\nbetween the nodes 36 and the reference potential. Gates of\nthe transistors 37 are connected in common to a line DCB to\nwhich a control signal is applied to cause bit lines to be\ndischarged after completion of erasing and programming\noperations and to reset the data register to \"L\" state, i.e. \"0\"\ndata prior to a reading operation. 15\nThe data register and sense amplifier 12 includes a\nconstant current source circuit 33. which is referred to as a\ncurrent mirror, according to the present embodimenL The\nconstant current source circuit 33 comprises a reference\nportion 64 which is enabled in programming verification and\nreading operations and disabled in erasing and programming\noperations; and current source portions 66 comprised of\np-channel transistors 54 whose drain-to-source paths are\nrespectively connected between gates of the transistors 50\nand the power supply voltage Von. The reference portion 64\nis comprised of p-channel transistors 56 and 58 and n-chan-\nnel transistors 60 and 62 to serve as a reference for the\ncurrent source transistors 54. Source-to-drain paths of the\np-channel transistors 56 and 58 are connected in parallel\nbetween the power supply voltage Vcc and a line 68. and the\ngate of the p-channel transistor 58 is connected to the line\n. Drain-to-source paths of the n-channel transistors 60 and\nare connected in series between the line 68 and the\nreference potential. The gate of the n-channel transistor 60\nis connected to a reference voltage V,,,~ of about 2 volts.\nGates of the transistors 56 and 62 are connected to a control\nsignal 43. and gates of the current source transistors 54 are\nconnected to the line 68. Thus, in programming verification\nand reading operations, the current source transistors 54\nconnected to the reference portion 64 which is enabled by\nthe control signal 43 serve to provide a constant current of\nabout 4iiA to bit lines BLk-1 to BLk-256.\nA programming determination circuit 24 of FIG. 1 is\nconnected via lines 70 to lines DLk-l to DLk-256 ot'FIG. 2b ~\nto serve to determine if every programmed memory tran-\nsistor reaches the range of desired threshold voltages in a\nprogramming verification operation.\nFIG. 9 shows a ~9i~in.tin cir~tit diagram of the program-\nruing det~m.-~ circuit 24. It should be noted that the 50\ncircuitry of FIG. ~ is portion of the programming deter-\nmination drasit ~ usociafr~d with the k-th column block\nCBk, and eigti drcsIts corresponding to the respective ones\nof column blocks present as a peripheral circuit on the\non-chip EEPROM. A circuit shown in FIG. 9b is a summa-\ntion circuit to perform a summation function for providing\nan \"U' level when any one of signals FF1 to FF8 is \"I..\"\nlevel. Referring to FIG. 9a, drain-to-source paths of n-chan-\nnel transistors 212 to 216 are connected in parallel between\na line 210 and the reference potential, and gates of the\ntransistors 212 to 216 are respectively connected to lines 70\nof FIG. 2b. Current paths of p-channel transistors 218 and\nD-type transistor 220 are connected in series, and the gate of\nthe transistor 218 is connected to a control signal SUP\nstaying at \"U' level in a programming verification operation\nwhile the gate of the transistor 220 is connected to the line\n. The transistors 212 to 220 constitute a NOR gate 234.\nTwo input terminals of NOR gate 222 are respectively\nconnected to the line 210 and a control signal SFP which\nbecomes \"L\" state only upon a verifying check. The input of\nan inverter 224 is connected to the output of the NOR gate\n, and the output terminal of the investor 224 outputs FPk.\nThe summation circuit 236 of FIG. 9b is comprised of\nNAND gate 226 connected to lines FPI to FP4; NAND gate\nconnected with signals FF5 to FF8; and NOR. gate 230\nconnected to outputs of the NAN1) gates 226 and 228.\nReferring now to the timing charts of FIG. 10 to FIG. 12,\nan explanation will be given of operations and features of the\nfirst embodiment shown in FIGS. ito 9.\n\nBlock Erasing Mode\nIn a block erasing mode, the data register and sense\namplifier 12, the column decoder and selection circuit 14,\nthe input/output buffer 16 and the programming determina-\ntion cimiit 24 are all in off states. Explained in more detail,\n~ the column decoder 30 of FIG. 2b is reset, thereby rendering\ntransfer transistors Ti to `1256 nonconductive. Control sig-\nnals 4~ to 4~ and signals on lines DCB and SBL are held in\n\"I..\" stares, so that the data register and sense amplifier 12\nbecome nonconductive. The control signal SUP of FIG. 9a\n~ is held in \"H\" state, arid the programming determination\ncircuit 24 is thereby nooconductive. The source line driving\ncircuit 22 provides \"U' state, Le. the reference potential of\nvolts on the common source line CSL by POM staying at\n\"If' level.\nNow, an explanation will be given in conjunction with the\ntiming chart of FIG. 10, assuming that simultaneous block\nerasing is performed on data stored in memory transistors in\nthe memory block BK1.\nThe time interval between t1 and t2 is a period for\ndischarging all word lines WL1 to WLZ to the reference\npotential. During his period, NAND gate 124 of FIG. 5\nretains \"H\" level with the control signal BLK at \"U' level,\nand D-type transistor 126 is conducting with PGM at \"H\"\nlevel. Thus, the block selection control line BSQ stays at\n\"H\" level of 5 volts. At this time, the charge pump circuit\nis ins nonconducting state. Consequently, in this period,\nall of the block selection co~oL lines BSC1 to BSC1O24\nm~ii~~ the potential of 5 volta. On the other hand, in this\nperiod, since control signals PVP and POM stay at \"H\"\nlevels and the control signal ERA is at \"U' level, the outputs\nof NAND gate 156 and tristate HAND gates 158 remain at\n\"H\" level and \"L\" level, respectively. At this time, the\nthatate Investor 164 is in a high impedance state. Thus, the\ncontrol gate line CGLJ stays at \"L\" level of 0 volts via\nturned-on D-type transistor 176. Consequently, all of the\ncontrol gate lines COL1 to COL8 ~~~nt~in \"U' level during\nthis period. Transfer transistors BTI to BT1O are all turned\non by the potential of the block selection control lines BSCI\n~ toBSCl024of5volts,andwocdlinesWLltoWL8ar'eall\ndischarged to the reference potential.\nThe time duration between t2 and t3 is a period to erase ill\nmemory cells in only a selected memory block. At time t2,\nthe decoder 120 receives address signals Pt, Ql and Ri which\nso arc all at \"H\" levels to select the memory block BK1, and the\noutput of the decoder 120 thereby goes to `V level. Thus,\nthe output of NAND gate 124 goes to \"H\" level. Conse-\nquently, the block selection control line BSC1 correspond-\ning to the selected memory block BK1 remains at the\npotential of 5 volts during the period between t2 and t,.\nHowever, decoders 120 associated with unselected memory\nblocks BK2 to BK1024 output \"H\" levels since at least one\n\nCase 9:02~cv-00058~-Jft Document 20 FUed 04/03/2002- Page 101 of 127\n,546,34j\nof the address signals Pt. QI and Ri is \"L\" level. Conse-\nquently, block selection control lines BSC2 to BSC1O24\nassociated with the unselected memory blocks go to the\nreference potential of 0 volta. Thus, transfer transistors in the\ntransfer transistor array 34-i are all turned on. and word ~\nlines WL1 to WLS in the memory block BKI thereby go to\nthe reference potential. However, since the transfer transis-\ntor arrays 34-2 to 3-1024 connected with unselected memory\nblocks BK2 to BK1024 are all turned off, word lines\nassociated therewith go to floating states. to\nAt time t2, the erase voltage Vera of about 20 volts is\napplied to the p-type well region 76 and the n-type well\nregion 74 via the well electrode 114 of FIG. 4. During the\ntime interval between t2 and t3, i.e. during the time period of\nabout 10 macc, floating gates of memory transistors in the\nselected memory block EKI accumulate holes by means of\nthe F-N tunneling which is generated by the application of\nthe erase voltage Vera to their channel, source and drain\nregions and that of the reference potential to their control\ngates. Thus, all of the memory transistors in the memory\nblock SKi are changed into D-type transistors having\nthreshold voltages of about -3 volts. That is, all memory\ntransistors in the memory block BK1 are erased to binary\nzero dax&\nHowever, in the case when the erase voltage V,,..~ is\napplied to the p-well and N-well regions 76 and 74 via the\nwell electrode 114 at time t1, since word lines in unselected\nmemory block BK2 to BK1024 are then in floating stares,\nthe word lines are thereby charged to substantially the erase\nvoltage Vera by a capacitive coupling. Thus, the charged ~\nvoltage of the word lines in the unselected memory blocks\nsufficiently reduces the electhc field between the channel\nregion and the control gate of each memory transistor such\nthat its erasure can be prevented. The inventors have dis-\ncovered that word lines in unselected memory blocks were\ncharged to an amount of 80 to 90 percent of the erase voltage\nV~, and data of programmed memory transistors in the\nunselected memory blocks was not destroyed or disturbed.\nThus, in the block erasing of the present embodiment, since\nit is unnecessary to apply the program inhibition voltage ~\nfrom a voltage boosting circuit to word lines in unselected\nmemory blocks, a reduction of the area occupied by the chip\nas well as the prevention of power consumption the area can\nefectiveiy be accomplished. Moreover, the aesea Inven-\ntion has an advantage of Increasing effec*lve memory array ~\nar-ca whilst reducing peripheral cira\ufffdarea on a chip surface\nof a fixed size. This results In increasing the memory\ncapacity of the EEPROM.\nIn the above-~oocd block erasing operation, the erase\nvoltage applied ~ the well electrode 1141* coupled as well ~\non the floated weed lines as on floated bit lines. Thus, the bit\nlines are also ~ged to the erase voltage of about ~) volts\nin the block aese operation. `lb prevent voltage-induced\nstress on transiston 40 of FIG. 2b due to the charged erase\nvoltage, D-type transIstors 38, whose gates are connected to ~\nthe power supply voltage Vcc, en respectively connected\nbetween bit lines BLk-1 to BLk-256 and the transIstors 40.\nDuring the block erasing operation between t2 and t3, the\nfirst selection line SLI of the selected memory block BK1\nmaintains a potential of about 4.3 volts, and the second so\nselection line SL2 of the block SKI is in a floating state\nsince control signals 46 and 4~ are at \"U' levels, thereby\nrendering transistors 140 to 144 of P10.5 nonconductive.\nThe floating state of the second selection line SL2 thereof\nprevents current flowing via the line SL2 from the well 65\nelectrode 114 when one or some of the second selection\ntransistors ST2 thereof failed. During the block erasing\noperation, the voltage relationship of significant portions of\nselected and unselected memory blocks can be summarized\nin the following TABLE I.\n\n\n\nTABLE I\n\n\n\nVotrage Scasi\nFur Sc~ec*ed\n\nVolca~c States\nFor Unselened\n\n\nMcm~ Block\n\nMemory BlOCkS\n\nFmi Selecdo.t LIne SLI\n.3 V\nV\n\nWted Uj~s WLI to WLZ\nV\n\nApproximately 20 V\n\nSeQ~Dd S&crIoa Line SL2\n\nFloinog\n\nFloaCkg\n\nWeU~trodc\nV\n\nWV\n\nTurning to FIG. 10. the time duration between t3 and t3 is\naperiodlodischargethechargedvolzageoabitljnesarjd\nword lines. At time t3, the block erasing operation terminates\nand the erase voltage Vera goes, to the reference potential\nwhile control signals WE and ERA go to \"H\" level. Between\nt3 and t4, the output of NAND gaze 156 stays at \"H\" level\nwith the control signal DS at \"U' level. Thus, the output of\nNAND gate 158 goes to \"U' level with the control signal\nPOM at \"H\" level. Consequently, control gate lines COL1 to\nCOLZ maintain `V levels between t3 and t4. During this\nperiod, the output of NAND gate 124 of FIG. S stays at \"H\"\nlevel with the control signal BLK at \"U' level. Thus, each of\nthe block selection control lines ESC1to BSC1O24 goes to\na potential of 5 volts. Consequently, all transfer transistors\nBTI to BTIO are turned on. and all word lines WL1 to WLS\nare discharged to the reference potential. On the other hand,\nthe first and second selection lines SL1 and SL2 are also\ndischarged to a potential of 5 volts.\nAt time t,. the line DCB goes to \"H\" level and $~ also\ngoes to \"H\" level. Thus, the erase voltage charged on bit\nlines discharges to \"U' level via transistors 37 shown in FIG.\nb.\nAi time t4, control signals BLK and DS go to \"H\" levels\nand X~oes to \"U' level. Thus. NAND gate 120 of FIG. S\ngoes to \"H\" level, and the first and second gate lines SGLi-1\nto SGLi-2 and block selection control lines BSCI go to the\nreference potential.\n\nProgram Mode\nThe presast ~R.OM perfonns a data loading operation\nto store data Input via input/output teiminal, into data\nlatches PBk-1 to PBk-256 prior to a programming operation\nafter an erasing operation.\nData loading operation is accomplished prior to a time t1\nof FIG. 11. During the data loading operation, control\nsignals Xd, 42, 4~ and 43, program voltage V,,,,,, pass\nvoltage V~, p-well region 76, program inhibition voltage\nV,,~ and lines SBL and DCB stay at \"U' levels, and control\nsignals WE, PGM, SLE, BLK, DS, ERA. PVF, SUP 4,,, 4~\nand 4~ are at \"H\" levels. As can be seen in FIG. 5, since Xd\nis \"L\" level and ELK, ERA, SLE, WE and PGM are all \"H\"\nlevels, block selection gaze lines BSCI to BSC1O24 stay at\n\"1..\" levels, thereby rendering transfer transistor arrays 34-1\nto 34-1024 nonconductive. WIth the line SBL at \"L\" level,\nconnection of data latches PBk-1 to PBk-256 to bit lines\nSlit-i to BLk-256 is inhibited. The constant current circuit\nand tristaze inverters 48 of FIG. 2b are in nonconducting\nstates with signals 43 and 4,, at `V levels.\nAddress inputting to external address input terminals is\ncomposed of row address a, to a~ and column address a0 to\n*7. The row address a, to a~ inputs to select one of memory\nblocks and one of the word lines during the data loading\n\nCase 9:02-cv-00058-JH Document 20 FHed 04/03/2002-\n,546,341\n\nPage 102 of 127\noperation so as to wiite data on all bit lines into memory\ncells at one time, i.e.. the perform a page program in the\nprogramming operation after the completion of the data\nloading operation. The column address a0 to a, is address\nsignals having 256 cycles during the data loading operation. 5\nThe column decoder 30 of FIG. 2b responds to the column\naddress of 256 cycles based on the toggling of external write\nenable Signal WE, to render transfer transistors TI to T256\nconductive in sequence. At the same time, input buffer 26\ncorresponding to the respective column blocks sequentially to\noutputs data input to the corresponding input/output termi-\nnal in response to the toggling of \\VE0. Thus, output data\nfrom the respective input buffers 26 is stored in sequence\ninto data latches P8k-i to PBk-256 via sequentially turned-\non transfer transistors Ti to T256 and corresponding transfer ts\ntransistors 49.\nAfter the above-mentioned data loading operation, the\nprogramming operation is started. One characteristic feature\nof the present embodiment is that the programming opera-\ntion includes the NAND cell charging operation.\nFor the convenience of explanation of the programming\noperation, it is assumed that data stored in the data latches\nis to be written into memory transistors M4 connected to a\nword line WL4 in the memory block SKi.\nThe programming operation is performed during the time\nperiod between t1 and t, as shown in FIG. U. During this\nperiod, p-well region 76, signals WE. PGM, 43. 43, 4,, and\nand the line DCB stay at 1..\" levels while signals Xci,\nBLK, DS, ERA and 4~ and the line SBL are all at \"H\" levels.\nThe clock 4,,, the program voltage Va,,, (=18 volts), the pass\nvoltage V,,, (=10 volts) and the program inhibition voltage\nV,,~ (=7 volts) are supplied during this period. On the other\nhand, the row address a,to a~ which is inputted during the\nabove-mentioned data loading operation, is latched in the\naddress buffer (not shown). Address signals Pt, QL sod RI\nwhich are generated by predecoding address signals A11,\nX~ to Am, X~ of the latched address, are input to the\ndecoder 120 of FIG. 5. Address signals A,?~ to A10,X~ of\nthe latched address are input to the decoder 154 of FIG. 6.\nAt time t1, the control signal Xd goes to \"H\" level, and\naddress signals P1, QI and RI selecting the memory block\nBK1 are Input to the NAND gaze 120 of FIG. 5. Then, the\noutput of the gate 120 goes to \"U' level, arid outputs of\nNAND gazes 124 and 136 go to \"H\" tevela. Thus, the first\nselection gate line SGU-i goes to a potential of 5 volts, and\nthe block selection control line BSC1 is boosted to the\nprogram voltage V,,,, of 18 volts by the pumping operation\nof the charge ~ cIrcuit 128. On the other band, the\nsecond selection g~a line SGL1-2 is boosted to the pass\nvoltage V~ of 10 volts by the pumping operation of the\ncharge pump di~t 152 with \"H' level transferred via\ntransfer transiato~ 140, 142 and 150. Each decoder 1.20\nassociated with unselected memory blocks BK2 to BK1024\ngoes to \"H\" level, and the output of each NAND gaze 124\ncorresponding thereto goes to \"U' level. Thrs, unselected\nblock selection control lines BSC2 to BSC1O24 go to a\nreference potential of 0 volts.\nAt time t,, the program control signal PGM goes to `V'\nlevel and the common source line CSL, which is the Output\nline of the source line driving circuit 22 of FIG. ~, is boosted\nto the program inhibition voltage V,~ That is, if PGM goes\nto \"U' level, the common source line CSL goes to the\nabsolute value, for example 2 to 3 volts, of the threshold\nvoltage of D-type transistor 206 and is thereby boosted to the\nprogram inhibition voltage V,,~ by means of the charge pump\ncircuit 208.\nA~eviously mentioned, since address signals A~ to\nA1~,.A10 selecting the word line WL4 were input to the\ndecoder 154 of FIG. 6 in the previous data loading operation,\nthe output of the decoder 154 associated with CGL4 is at \"U'\nlevel, and the outputs of the decoders 154 associated with\nunselected word lines WLI to WL3 and WLS to WLS are at\n\"H\" levels. Thus, the output of NAND gaze 156 associated\nwith the selected word line WL4 is at \"H\" level, and the\noutput of NAND gates 1S6 associated with the unselected\nword lines are at \"1.\" levels. At lime t1, the clock 4,~ is\ngenerated. Then, NAND gaze 178 and NOR gaze 188 asso-\nciated with the selected word line WL4 respectively output\nthe clock 4,, and \"L\" level, thereby providing the program\nvoltage Vpgm on the selected control gale line CGL4. On\nthe contrary, NOR gazes 188 associated with unselected\nword lines output the clock 4,,, thereby providing the pass\nvoltage V~, on unselected control gaze lines CGL1 to CGL3\nand CGLS to COLt\nAt time t1, the line SBL goes to \"H\" level. Thus, transfer\ntransistors of FIG. 2b are all turned on so as to transfer data\nstored in latches PBk-1 to PBk-256 to corresponding bit\nlines BLk-1 to BLk-256. All memory transistors of the\nselected memory block BK1 in the previous block erase\nmode were erased to \"U' levels, Ic. logic \"0\" data. In the\ndata loading operation after a block erasing mode, latches\ncorresponding to memory transistors which are to write \"if'\nlevels, Le. logic \"1\" data were stored to \"L\" level, i.e. logic\n\"0\" data while latches corresponding to memory transistors\nwhich are to write logic \"0\" data were stored to logic \"I\"\n~ data. For the convenience of explanation, assume that logic\n\"1\" data is written into a memory transistor 240 which is\nconnected to the selected word line WL4 and bit line BL1-2\nof memory block BK1 in the first colu block CB1 of FIG.\na while logic \"0\" data is written into the remaining memory\n~ transistors connected to the word line WL4 thereof~ Then,\nthe latch P51-2 has already stored logic \"0\" data while the\nremaining latches have already stored logic `T' data in the\ndata loading operation. Thus, after time t1, the conduction of\ntransfer transistors 44 causes the bit line BLI-2 to go to \"U'\n~ levelandtherexnainingbitlincstogoto\"H\"levelsof5\nvolts.\nConsequently, during the time duration between t1 and t2,\nthe transfer transistor array 34-1 of FIG. 2a is conducting,\nand the first and second selection lines SU and SL2 in the\n~s y1~trd memory block BK1 respectively maintain S volts\nand V,,., (=10 volts) while the selee~d word line WIA and\nunse'ee'~~d word lines WL1 to WL3 and WLS to WL8\nmaint~inV,,,_(=l8 volts) arid V, respectively. During the\nprogramming operation, since the common source Uric CSL\n~o mctintmn' the program inhibition voltage V,~ (~7 volts), the\nsecond selection transistor ST2 and memory transistors Ml\nto MX in the block BK1 are all turned ott, and the first\nseIe~on transistor 242 connected to the bit line BL1-2 is\nturned on while remaining first selection transistors exolud-\nss lag the transistor 242 in the block BK1 are turned off. Thus,\ncurrent paths of memory transistors in the NAND cell\nincluding the memory transistor 240 are connected with the\nbit line SLi-2, and channels of the memory transistors and\nthe respective junction capacitor of their sources and drains\nare thereby discharged to a reference potential of 0 volts.\nHowever, first selection transistors ST1 associated with\nmemory transistors which are to write logic \"0\" data are\nturned off, and channels of memory transistors in the NAND\ncells associated there with and the respective junction capaci-\ntOti of their sources and drains are charged to the program\ninhibition voltage V,~ (=7 volts). Thus, during the time\nperiod of about 100 p5cc between Li and t2, aNAND cell\n\nCase 9:02-cv-00058-JH Document 20 F~ed 04/03/2002~ Page 103 of 127\n,546,341\ncharging operation associated with memory transistors\nwhich are programmed to logic \"0\" data is carried out\nThrning to PIG. U, the lime duration between t~ and L3,\ni.e. the period of about 2 macc, is a period to perform\nsubstantial programming. At time LI. the signal SLE goes to 5\n\"FF' level and, as can be seen in FIG. Sc, $~ goes from \"if'\nlevel to \"L\" level while 4, goes from \"L\" level to \"H\" level.\nThus, transistors ~44 of FIG. 5 axe turned on, thereby\ncausing all of second gate lines SGLi-2 to be connected with\nthe reference potential. Thus, all of second selection tran- ~\nsisters ST2 in the selected memory block BK1 are turned\noff. During this period, the program voltage V,,_ of about\nvolts is applied on the word line WL4 in the selected\nmemory block BK1, and source, drain and channel of the\nmemory transistor 240 arc applied to 0 volts. Thus, the ~\nfloating gate of the transistor 240 is accumulated with\nelectrons by the F-N tunneling, thereby causing the transis-\ntor 240 to be changed into an enhancement mode transistor\nhaving a threshold voltage of about 0.8 volts. However,\nsince junction capacitors of sources and drains of memory ~\ntransistors excepting the transistor 240 and their channels\nare charged to the program inhibition voltage V,,,., injection\nof electrons into floating gates of these transistors is inhib-\nited and these transistors remain as depletion mode transis-\ntors storing logic \"0\" data. That is, NAND cells associated ~\nwith memory cells which are programmed to logic \"0\" data\nare blocked from connection to corresponding bit lines by\nthe above-mentioned NAND cell charging, thereby being\nprevented from writing.\nAs discussed above, the voltage relationship of significant 30\nportions dining the NAND cell charging and the program-\nming operation can be summarized in the following TABLE\n.\n\nTABLE 2\n\n\n\ufffd~btagc Sr~s\n\n~b~e S~\n\nN~\n\nD~\n\nCaB\n\nr,u~g\n\nCaar5log Pcnod\n\nPafod\n\n\nHni~~O,L\ufffdSL1\n\nSV\n\nSV\n\nOf Selecied Mei~y Block\n\n\n\nUcelecwdW~dUDes\nOf Seloc~d M~y Block\n\nV~-10V\n\nV,..~10V\n\n~~i~or\n&~ond M~ Block\n\nv,,,_.isv\n\nv,,,,.tav\n\nSe~S1~~~L1ocSU\nOf Setcc~d M~y Block\n\nV,,,,.IOV\n\nOV\n\nWe11Elecu~\n\nV,.7V\nOV\n\nV0'.7v\nOV\n\n\nThe lime podod between t~ sod t1, Ic. the period of 500 so\nnsec, isa period b lisch.xge the boosted voltage on the bit\nlines and the ~sud lines, At time t,, control signals WE and\nPOM and the be DC~ go to \"if' levels, and control signals\nBLK and DS, voltages Vi,,,,,, Vi,,, and V,,~ and the line SBL\ngoto\"L\"lcvdsof0volta.Theclock4,,stopspulsingtobe 55\nfixed at \"H\" level at the time LI. On the other hand, during\nthis period, 4~ m'int'4na \"if' level arid $~ and, maintain\n\"L\" levels. Thus, the source line driving circuit 22 outputs\nthe reference potential on the common source line (~L\nControl gate lines COL1 to CGL8 of FIG. 6 go to a potential 60\nof 0 volts, and block selection control lines BSC1 to\nBSCIO24 of FIG. Sgo to a potential of 5 volts. This results\nin causing all word lines to be discharged to the reference\npotential, At time t4, Xd goes to `V level and BLK and DS\ngo to \"H\" levels. Thus, during the time period between t4 65\nand t5, block selection control lines BSCI and first and\nsecond selection gate lines SGU-1 and SGLI-2 go to the\nreference potential. On the other hand, since the line DCB\nand the signal $~ axe at \"H\" levels dining the time period\nbetween t3 and LI~ the boosted voltages on the bit lines are\ndischarged to the reference potential via transistors 37. Az\ntime LI. the signal $~ goes to \"L\" level.\n\nProgramming Verification Mode\nThe programming verification mode is performed imnie-\ndiazely after the programming mode. The programming\nverification operation of the present invention is similar to\nthe reading operation as viii be discussed lazen The differ-\nence as compared with the reading operation is that the\nvoltage applied to a selected word line is a minimum\nthreshold voltage which is to be written into memory\ntransistors. This minimum threshold voltage will be referred\nto as a programming verificadon voltage. It is assumed that\nthe programming verification voltage is 0.8 volts in the\npresent embodiment.\nThe programming verification operation is carried out\nimmediately after ~ LI in FIG. 11, and a timing chart of\nthe programming verification operation is of the time period\nbetween t2 and t4 as shown in FIG. 12. At the initiation of\nthe programming verification, Ic. at time LI of FIG. ii or\ntime t2 of FIG. 12, control signals Xd, $2 and 4,~ go to \"if'\nlevels and signals $~, PVF arid SUP and the line DCB go to\n\"U' levels. Thus, during the programming verification\noperation. control signals WE, PGM, SLE, Xd, ELK, DS,\nERA, $2 and $~ and the clock 4, maintain \"H\" levels, and\nvoltages V,~, Vi,,,, and Vi,,, lines SBL and DCB and control\nsignals 4,, 4,, PVF and SUP maintain \"L\" levels.\nIt is now assumed that the programming verification\noperation is performed to determine if a memory transistor\nof FIG. 2a which was written to a logic \"1\" data in the\n\" previous programming mode was programmed with a\ndesired minimum threshold voltage.\nWhete a command for executing a programming verifi-\ncation after completion of programming operation is input to\nEEPROM from the microprocessor via input/output termi-\nnals or other terminals or where a programming verification\noperation is automatically carried out after a programming\noperation, data stored into latches PBk-1 to PSk..256 in the\nprogramming operation is succeeded without reset by the\n~ programming verification operation. Thus, at the beginning\nof the prograrriniang verification operation, the latch P81.2\nis storing logic \"0\" data and the naming latches are storing\nlogic \"I\" data.\nAr time t2 of FIG. 12, the control signal Xd goes to \"H\"\nlevel and the decoder 120 of FIG, S then outputs \"U' level\nin response to address signals Pt, Ql and Ri designating the\nmemory block BK1. Then, since $2 and 4, respectively\nmaintain \"H\" level and `V' level, first and second selection\nlines SGLI-1 and SGL1.2 and the block selection control\nline BSC1 go to \"H\" levels of 5 volts.\nAt time LI~ the control signal PVF goes to \"I..\" level and\naddress signals A~ to A,~ designating the word line\nWIA are fed to the decoder 154 of FIG. 6. Then, NAND gate\nbecomes of high impedance and the verifying voltage\ngenerator i64 provides the verifying voltage of 0.8 volts on\nthe control gate line COLA. However, each decoder 154\nassociated with unselected word lines WL1 to WL3 and\nWLS to WLS output \"H\" levels. Then, the verifying voltage\ngenerator 164 becomes high impedance and NAND pie 158\noutputs \"H\" level, Thus, control gate lines CCLI to COL3\nand COLS to CCLX go to \"H\" level of 5 volts. On the other\nhand, since POM mainraina \"H\" level at t2, the source line\n\nCase 9:02-cv-00058-JH Document 20 FHed 04/03/2002-\n,546,341\n\nPage 104 of 127\ndriving circuit 22 of FIG. 7 provides the reference potential\non the common selection line CSL\nConsequently, the transfer transistor array 34-1 of FIG. 2a\nis conductive and the first and second selection lines SL1\nand SLZ and unselected word lines WL1 to WL3 and WLS 5\nto WU go to the potential of 5 volts while the selected word\nlinc WL4 goes to the poential of 0.8 volts. Thus, transistors\nconnected with the selection Lines SLI and SL2 and the\nunselected word lines are turned on.\nAt time LI~ the control signal $2 goes to \"H\" level, thereby\ncausing the constant current circuit 33 of FIG. 2b to be\nenabled. Thus, the constant current transistors 54 supply\nconstant current of about 4~iA to bit lines via connecting\nnodes 36 and transistors 40 and 38.\nAssume that the programmed memory transistor 240 has\nfailed to program, i.e. the threshold voltage of the transistor\nwas below the program verifying voltage of 0.8 volts.\nThen, the transistor 240 is turned on and the bit line BL1-2\nconnected thereto goes to the reference potential of 0 volts.\nSince all transistors of NAND cells in the memory block\nBK1 which are connected with bit lines excluding the bit\nline BL1-2 are turned on, the bit lines also go to the\nreference potential. The period of time when word lines\nWL1 to WLX and bit lines are established to the predeter-\nmined voltages in such a manner is a period of about 2,usec\nbetween LI and t3 of FIG. ii\nThe time period between LI and t4 of FIG. 1.2, i.e. the\nperiod of about 500 nsec, is for verification sensing. The\ncontrol signal $2 goes to \"H\" level at time LI~ and transistors\nof FIG. 2b are thereby turned on. The transistor 50 whose\ngate is connected with the bit line BL1-2 via transistors 38\nand 40 is turned off by the reference potential on the bit line\nBL1-2, thereby causing the latch PB1-2 to maintain logic\n\"0\" data. Similarly, since other' bit lines am also at the\nreference potential, transistors 50 associated with these bit\nlines are turned off and latches excepting the latch PB1-2\nthereby maintain previously stored logic \"1\" data. Verifica-\ntion sensing data stored in the latches PBk-1 to PBk-256 by\nthe above-mentioned verification sensing operation is con-\nnected to gates of transistors 212 to 216 of FIG. 90 via\nturned-on inveriers 48 and lines 70. Thus, the \"U' level\nverification sensing data stored in the latch PB1-2 is rop-\nplied via corresponding inverta' 48 to the gate of transistor\nwhich constitutes NOR gate 234 C(P!G. 90 sso'~'~\nwith the first column block CB1, tberd,y rendering the\ntransistor 214 conductive and causing the line 210 to be\ndischarged to the reference potentiaL Consequently, sums\nthe signal SF? goes to \"U' level only wtmn the programming\nverification is diett&. F?1 goes to \"L\" level. However,\nsince latches in other column blocks CB2 to CBS store \"H\"\nlevels, transistors m to 216 of NOR gaze 234 correspond-\ning to each one of the blocks CB2 to CBS are in noocon-\nductive states. Thea, each line 210 maintain \"H\" level by\nmeans of pull-up transistors 218 and 220 and FP2 to FP8\nthereby stay at \"H\" levels. Thus, the output line 232 of the\nsummation circuit 236 of FIG. 9b goes from \"H\" level to \"L\"\nlcvel. This represents that the memory transistor 240 was\nundesirably programmed. That is, it is checked that the\nthreshold voltage of the memory transistor 240 did not reach\nat a preset minimum threshold voltage. A program detciTni-\nnation signal PDS on the line 232 is connected to a timing\ncircuit (not shown) which generates timing signals between\nt, and LI as shown in FIG. 11 so as to perform a reprogram-\nming in response to the signal PDS being at \"U' level. That\nis, reprogramming operation is automatically performed. It\nwould be noted that the reprogramming operation of the\npresent embodiment may automatically be performed by the\ninternal circuit of the present EEPROM without request of\neither reprogramming control or reloading of data from a\nmioroprocessor. However, if necessary, the microprocessor\nmay control the reprogramming operation in response to the\nsignal PDS from one of the input/output terminals of the\npresent EEPROM chip.\nAssuming that the memory transistor 240 reached the\ndesired threshold voltage of 0.8 volts by the reprc'gramming\noperation, then the transistor 240 is in a noriconductive state\nduring the programming verification operation performed\nafter the reprogramming operation. Thus, the bit line BL1-2\nis charged to the potential of about 2 to 3 volts by the\nconstant current supplied via the constant current transistor\n, thereby rendering conductive the transistor 50 connected\nwith the bit line BL1-2. Consequently, the verification\nsensing data of latch PB 1-2 is changed from logic \"0\" data\nto logic \"I\" data. As previously discussed, other latches are\nstoring logic \"I\" verification sensing data. Thus, all of the\nlatches PBk-1 to PBk-256 store logic \"1\" verification sens-\ning data. That is. if all memory transistors were well\nprogrammed in the page programming operation, verifica-\ntion sensing data stored in the latches is changed into logic\nThen, transistors 212 to 216 constituting NOR gates 234\nof FIG. 9a are all turned off, and signals FP1 to FPS go to\n\"H\" levels with the signal SF? at `1.~\" level during the check\nof programming verification. Consequently, the summation\ncircuit 236 of FIG. 9b outputs the program determination\nsignal PDS, which is at \"H\" level. This represents that the\nprogramming operation had successfully been performed.\n~ Now assume that some of memory transistors pro-\ngrammed with logic \"1\" had successfully been programmed\nand the remainder had unsuccessfully been programmed.\nThen, during the followed programming verification opera-\ntion, latches corresponding to the former memory transistors\nare changed so as to store logic \"1\" data, while latches\ncorresponding to the latter memory transistors maintain\nlogic \"0\" data. Since latches in the former case are storing\nlogic \"1\" data, their corresponding bit lines are charged to\nthe potential of 5 volta during the followed reprogramming\n~ operation. However, in the same manner as the above-\nmentioned programming operation, since, in the reprogram-\nming operation, a ..I~nd first selection tine stays itS volts\nand jiactiocs at sources and &ains of memory transistors\nand their ____ am charged so the program inhibItion\n~ voltage of 7 vulZ*, first translators orimiected with the\ncharged bit lines on the selected first selection line are in\nnonconductive states, Thus, during the reprogramming\noperation, the ~iicce~afuUy programmed memory transistors\nare prevented from programming by the charged program\n~ inhibition voltages. However, in tim case of the latter, Ic. the\nunsuccessfully programmed memory transistors, since their\ncorresponding latches are storing logic \"0\" data, reprogram-\nming is performed only on them. With such repeating\noperations, if all memory transistors on a selected word line\n~ which are programmed with logic \"1\" data were success-\nfully programmed, the program determination signal PDS\noutputs \"H\" level during the aboveixmniioned programming\nverification operation, and the reprogramming operation is\nterminated. The present circuit used in the above-mentioned\n~ programming verification operation may also be applied to\nwith NOR-type memory arrays.\nThe programming verification techniques as discussed\nabove have various advantages as follows. First, the pro-\ngramming verification operation can automatically carried\nout by the internal circuit without the control of an external\nmicroprocessor. Second, since the data register is used as\ndata latches in a data loading mode, verification sensing\n\nl0\nCase 9:02-cv-00058-JH Document 20 FHed 04/03/2002- Page 105 of 127\n,546,341\n\nReading Mode\nThe control signal 43 goes to \"H\" levels at time t2. thereby\ncausing th~ current source circuit 33 to be enabled. Thus, the\nconstant current transistors 54 supply the current of about\niiA onto bit lines BLk-1 to SLk-256 via connecting nodes\nand transistors 40 and 38. Since only the memory\ntransistor 240 is programmed with logic \"I\" the bit line\nBLI-2 is charged to about 2 to 3 volts and the remaining bit\nlines go to 0 volts. At time t, of FIG. 12, the control signal\ngoes to \"H\" level, thereby rendering transistors 52 of FIG.\nb conductive. Then, only the transistor 50 associated with\nthe bit line RL1-2 is turned on, thereby making the latch\nPB1-2 sense and store the logic \"1\". However, remaining\nlatches continuously store logic \"0\" based on the previously\nmentioned reset operation since transistors 50 are turned off.\nThat is, page reading is accomplished. Data stored in the\nlatches PBk-i to PBk-256 is output to input/output terminals\nto 1108 by a byte (8 bits) via inverters 48, transfer\ntransistors Ti to T256 turned on in sequence in response to\ncolumn address of 256 cycles and toggles of WE,, and\noutput buffer 28.\n\nModified Embodiments\n\nThe EEPROM of the first embodiment explained in\nconnection with FIG. 1 to FIG. 12 comprises the memory\narray including 1024 memory blocks each of which has\nNAND cells arranged in the same rows, and a source line\ndriving circuit for generating the program inhibition voltage\nprior to the programming or reprogramming operation in\nordertochargeittotheNANDcells.However,itsbouldbe\nnoted that the present invention is not limited to such an\nembodiment For example, the memory array used in other\nembodiments of the present invention may be comprised of\nmemory blocks having shared word lines as discussed\nhereinafter. To charge the program inhibition voltage to\nNAND cell, a capacitive coupling way from control gates\nmaybe applied with no use of the source line driving circuit\nThis modified embodiment is illustrated in FIG. 13 to FIG.\n.\nFIG. 13 consists of FIG. 13a and FIG. 2b, FIG. L3a shows\na memory ~ay composed of memory blocks having shared\nword lines, and FIG. 2b shows the already discussed periph-\neral chenit connected with the memory army of PIG. 13a,\nFor simpliflc~on at the &awing. PIG, 13a ihows only\nthe arrangement of memery cells and shared word lines\nwhich are associated with the k-rh column block in the i-rh\nmemory block SBKL However it should be noted that a\nmemory array 10 having memory cells of 16 mega bits as\nshown in FIG. 13a is arranged In the same manner as the\nmemory array of FIG. 2a excepting the shared word lines.\nReferring to FIG. 13a, each of memory blocks SBKI (i~l,\n, 3,,.., 512) is comprised of two submemory blocks, i.e.\nan upper memory block or a first submemory block USBKi\nand a lower memory block or a second submemory block\nEach of the upper and lower memory blocks USBKI\nand LSBK1 has the same configuration as each of the\nmemory blocks of FIG. 2a. Word lines WL1 to WLS in the\nupper memory block USBKi axe correspondingly connected\nwith word lines WL1 to WL3 in the lower memory block\nThat is, the upper memory block USBKI shares the\nword lines WL1 to WIJ with the lower memory block\nLSBKL\n~ word lines V/Li to WL8 are respectively connected\ntO control gate lines CGL1 to CCLI via current part of\ntransfer transistors BT2 to BT9. A first upper selection line\nand a first lower selection line ISL1 are connected to\ncircuits in a programming verification mode and sense\namplifiers in a reading mode, as will be discussed herein-\nbelow, simplification of peripheral circuits may be accom-\nplished. Third, the threshold voltages of programmed\nmemory transistors may be tightly distributed within a 5\nnarrow range above a preset minimum threshold voltage.\nand over-programming may be prevented. The tight disui-\nbution of threshold voltages can be accomplished by the\nexecution of the programming operation within a shorter\nperiod, since successfully programmed memory transistors to\nare automatically inhibited from programming due to the\nchanged data of their corresponding latches.\n\nFIG. 12 illustrates a timing chart of the reading operation 15\naccording to the present embodiment\nThe time period between ti and t2 in the drawing is a\nperiod to discharge word lines WL1 to WL8 and all bit lines\nELk-i to BLk-256 to the reference potential and to reset so\nthat latches PBk-1 to PBk-256 stores logic \"0\" data. During\nthis period, the control signal $~ and lines SBL and DCB\nstay at \"H\" levels. Thus, bit lines BLk-1 to BLk-256 are\ndischarged to the reference potential via the transistor 37 of\nFIG. 2b, and latches PBk-i to PBk-256 are reset to logic \"0\"\ndata by the conduction of transistors 37 and 44. During the\ntime period between t1 and t2, a timing chait of control\nsignals WE, PGM, SLE, Xd. BLK, DS and ERA, the clock\n$R and voltages V,,,,,, V,~,, and V,,~ is identical to the timing\nchart between t3 and t5 shown in FIG. U. Control signals\nPVF and SUP keep \"H\" levels during operations excepting\nthe programming verification operation.\nThe time period between t2 and t4 is a period for sensing\ndata read out from memory cells and storing the sensing data\ninto latches PBk-1 to PBk-256. During the period. WE,\nDS, ERA, 43,43 and $R maintain \"If'\nlevels, and V ~, V,,,,,, V,,4, lines SBL and DCB, 43 and $~\nkeep \"L\" lev~!s.\nAn explanation will now be given, assuming that a\nreading operation is performed from memory transistors ~\nconnected to the word line WL4 in the memory block BK1\nwhich was page programmed in the above-mentioned pro-\ngrammmg modc.\nOperation between t2 and t3 is performed In a similar\nmeaner as the verification operation as discussed shove.\nThus, an explanation will be given in brief. The block\nselection circuit of FIG. 5 associated with the selected\nmemory block EK1 snakes first and second selection gaze\nlines SGLI-1 asxi SGL1-2 and the block selection control\nlines BSCI heM itS volts in response to ad&ess signals Pt,\nand Ri iJd.~ug the block BK1. Since the control signal\nPVF is at `W ips'cI, the verifying voltage generator 164 of\nFIG. 6is in a ~gh hopedance state and the NAND gate 158\nis being enabled. Thus, the control gate line CGL4 corre-\nsponding to the ~`ecte'1 word line WL4 is at the reference 55\npotential of 0 volts in response to address signals A/~ to\nA1~,/A10 designating the word line WL4. However, control\ngaze lines CGLI to CCIL3 and CCLI to CCLI correspond-\ning to unselected word lines WL1 to WL3 and WLS to WL8\nare at \"H\" levels of S volts. On the other hand, the source 60\nline driving circuit 22 of FIG. 7 outputs the reference\npotential on the common source line CSL. Consequently, the\ntransfer transistor array 34-1 of FIG. 2a is conductive, and\nfirst and second selection lines SL1 and SL2 and unselected\nword lines WL1 to WL3 and WLS to WL8 in the block BK1\nare thereby at 5 volts while the selected word line WL4\ntherein is itO volts.\n\nCase 9:02-cv-00058-JH Document 20 FHed 04/03/2002- Page 106 of 127\n,546,341\nupper and lower selection gaze lines USGLi and LSGL1 via\ncurrent paths of transfer transistors BT1 and 8Th, respec-\ntively. Second upper and second lower selection lines USL2\nand LSL2 are connected to upper and lower ground selection\nlines UGSL and LGSL via current paths of transfer transis-\nand BT12, respectively. Sources of second upper\nand lower selection transistors UST2 and LST2 are con-\nnected to a common source line CSL which is connected to\nthe reference potential, i.e. the ground. Drains of first upper\nand lower selection t.ransistors UST1 and LST1 are respec- 10\nLively connected to corresponding bit lines.\nThe control gaze lines CGL1 to CCLI are connected to the\ncontrol gate driving circuit 20 explained in connection with\nFIG. 6. Upper and lower selection gate lines USGLi and\nLSGLI are respectively connected to corresponding block `~\nselection control circuits 318 of FIG. 14. Each of the block\nselection control circuits 318 serves to select one of upper\nand tower memory blocks in a selected memory block\ndesignated by address according to respective operation\nmodes. It should be noted that the block selection control\ncircuits 318 corresponding to the respective memory blocks\nare provided on the substrate of the on-chip EEPROM.\nThus, it would be appreciated that two memory blocks\nsubstantially share one block selection control circuit since\neach block selection control circuit controls one memory\nblock comprised of upper and lower memory blocks. This\nresults in relatively increasing the area of memory array on\nthe chip substrate of fixed size so as to increase the memory\nstorage capacity since the chip occupying area of the periph-\neral circuit is decreased.\nThe upper ground selection line UGSL and the lower\nground selection line LOSL are connected to a ground line\ndriving circuit 320 illustrated in FIG. 15. The ground line\ndriving circuit 320 is a circuit connected in common with\nupper ground selection lines UGSL and lower ground selec-\ntion lines LGSL in memory block SBKI. The ground line\ndriving circuit 320 serves to provide proper voltages onto\nthe upper and lower ground selection lines UGSL and LGSL\naccording to the respective operation mod\ufffd\nReferring to FIG. 14 showing the block selection control\ncircuit which controls the i-rh memory block SBK1. a\ndecoder 322 recaves address signals P1, QL and Ri and the\ncontrol signal Xd. The address signals Pt, QI and RI am\nsignals predecoded by address signals A12/~ to A~JA of ~\nrow address signals A11/~ to Aan/A from address buffer\n(not shown). The row address signal A11/~ is input to a\ntiming circuit (not shown) In order to generate control\nsignals A11~~ A,11'X~ and AI~J.A7~ for selecting one\nof either the vp,~ anemory block USBKI or the lower ~\nmemory block L~X1 according to the respective operation\nmodes. Logic states of these control signals according to the\nrespective operatIon modes are given in the following\nTABLE 3, wherein \"If' represents \"if' level of 5 volts and\n\"L\" represents \"L\" level of 0 volts.\n\n\nTABLE 3\n\n\nOppcr Mc~y Block\nSelec*ionA11.H\n\nLow Meaney Block\nSeIectto@A11~L\n\nRea~\n-\nEzi*inj And P~o\ufffd~n~\nMode Vndfl~ee Mode\n\nR~\n-\nErodog And ~\nMode WdiCndOC Mode\n\n\nA,,~\n\nH\n\nH\n\nH\n\nL\n\nX~\n\nL\n\nL\n\nL\n\nH\n\nA111\n\nL\n\nH\n\nL\n\nL\n\n\n\nTABLE 3-continued\n\n\nUppa Mcz~y Block\nSclecdooA,1=H\n\nLown~ Menory Block\nSc1ecri~A,1~L\nReading,\nPro\ufffdxnng\nEzioing And Pmgzino~ng\nMode Vth5cgloe Mode\n\n\nReading.\nPm\ufffdg\nEraiieg And Pm\ufffdnang\nMode Wn5catou Mode\n\nX~j~\nA111\nX\n\nL L\nL H\nH L\n\nL H\nL L\nH H\n\nThe output of the decoder 322 is connected to one input\nterminal of NAND gaze 324 and an input terminal of an\ninverter 326. The other input terminal of NAND gaze 324 is\nconnected to the erase control signal ERA. The output of the\nNAND gaze 324 is connected to the upper selection gate line\nUSGU via a CMOS transfer gaze 328, which consists of\nn-channel transistor 350 aix! p-channel transistor 352, and\nthe current path of D-type transistor 330. Between a con-\nnecting node 358 and the reference potential is connected\nthe current path of n-channel transistor 332. Gates of\nN-channel transistors 350 and 332. p-channel transistor 352\nand D type transistor 330 are connected to control signals\nA11~, X~, X and WE~,, respectively. The control signal\nWE,, is at \"1? level during the block erasing operation and\nis at \"H\" level during ri~~T~aining operations. The output of\nthe NAND gate 324 is also connected to the lower selection\ngate line LSGU via a CMOS transfer gaze 334, which\nconsists of n-channel transistor 354 and p-channel transistor\n, and the current path of D-type transistor 336. The\ncurrent path of n-channel transistor 338 is connected\nbetween a connecting node 360 and the reference potential.\nGates of n-d~~nni transistors 354 and 338, p-channel tran-\nsistor 356 and D-type transistor 336 are connected to control\nsignals Z~, A11,, A111 and WE.~,, respectively. `fl~ output of\nthe investor 326 is connected to the block selection control\nline BSCI via current paths of D-type transistor 340 and\nn-channel transistor 342,.which are connected in parallel,\nand the current path of D-type transistor 344. The gate of the\nD-type transistor 340 is connected to the output of the\ndecoder 322, arid gates of the n-channel transistor 342 and\nthe D-type transistor 344 am connected to the power supply\npotential Vcc of 5 volts, Two input terminali of NOR gate\nare connected to the clock 43, and the output of the\ndecoder 322~ respectively. Between the output of the NOR\ngate 346 and the line BSCI Is connected a chaign pump\ncwctnt 348.\nIf address signals selecting the memory block SBKI input\nto the block selection control circuit 318, the block selection\ncontrol line BSCi is at a potential of about 4.3 volta in\nerasing, programming verification and reading modes, and is\nat the program voltage V,,. of 18 volts in a programming\nmode. On the contrary, the block selection control line of\nrespective ones of block selection control circuits associated\nwith unselected memory blocks is at the reference potential\nof 0 volts in all modes.\nIf the memory block SBKi is designated by the address\nsignal and the address signal AU is at \"H\" level, the upper\nselection gaze line USGU is at a potential of 5 volts in a\nprogramming, a programming verification arid a reading\nmodes, and the lower selection gaze line LSGLA is at a\npotential of 0 volts by conduction of the transistor 338 ia\nsaid modes. Similarly, if the memory block SBKI is\naddressed by the address signal and the address signal A11\nis at \"1? level, the lower selection gate line LSGU is at a\nCase 9:02-cv-00058-JH Document 20 FHed 04/03/2002- Page 107 of 127\n,546,341\npotential of 5 volts in programming, programming verifica-\ntion and reading modes, and the upper selection gaze line\nUSGLi is at a potential of 0 volts by conduction of the\ntransistor 332 in said modes. On the other hand, upper and\nlower selection gale lines USGLi and LSGU are both in ~\nfloating states of about 2 to 3 volts in a block erasing mode.\nReferring to FIG. 15, the ground line driving circuit 320\nis comprised of inverters 362 to 374 and NOR gazes 376 and\n. The driving circuit 320 outputs 0 volts onto upper and\nlower ground selection lines UGSL and LGSL in a program- ~\nming mode. If the upper memory block is selected in reading\nand programming verification modes, the upper ground\nselection line UGSL goes to \"H\" level of 5 volts, and the\ntower ground selection line LGSL goes to \"L\" level of 0\nVolts. However, if the lower memory block is selected in\nreading and progranaxning vthficajion modes, the lower\nground selection line LGSL goes to \"H\" level of 5 volts, and\nthe upper ground selection line UGSL goes to \"L\" levels of\nvolts. On the other hand, upper and lower ground selection\nlines UGSL and LGSL go to \"H\" levels of 5 volts in a block\nerasing mode.\nOperations of the modified embodiment are almost the\nsame as those of the first embodiment, excepting operation\nto select either upper or lower memory block and operation\nto charge NAND cells by way of a capacitive coupling\ntechnique in a programming operation. Thus, a brief expla- ~\nnation of operation of the modified embodiment will be\ngiven, referring to the accompanying timing charts.\nFIG. 16 shows a timing chart of the block erasing mode.\nIn the drawing, the time period between t5 and t2 is for\ndischarging all word lines in the memory array 10 to the\nreference potential of 0 volts. In this period, control gate\nlines COLI to CGLS are at the reference potential as\ndiscussed in cormection with FIG. 6. During this period,\nBLK maintains \"U' level, and the predecoder (not shown) ~\ngenerates address signals P1, QI and Ri being at \"H\" levels\nin response to the signal BLK~ Thus, the decoder of FIG. 14\noutputs \"L\" level. Consequently, block selection control\nlines BSC1 to BSC512 are all at the potential of about 4.3\nvolts, and transfer transistors BT2 to B'I~ of transfer tran-\nsistor arrays 34-1 to 34-512 of FIG. l3a are all turned on,\nthereby grounding all word lines.\nThe time period between t2 and t, of FIG. 16 is for eruing\na selected memory block. During the period, onenoL gaze\nlines COL1 to CGU remain the reference potential identical ~\nto the case between t~ to t2. The block selection coi~oI\ncircuit 318 of FIG. 14 associated with the selected memory\nblock outputs the potential of about 4.3 volts onto a selected\nblock selection control line. Howevu~ the block selection\ncontrol cirenita .sodw'd with unselected memory blocks ~\noutput the r~f.i.~'t potential onto unselected block selec-\ntion control lbaes. Thus, word lines of upper and lower\nmemory block bathe selected memory block at time ~ are\nall at the reference potential, and all of word lines in\nunselected memory block are in floating states. However, ~\nsince the erase voltage V~,, of 20 volts is applied to the well\nelectrode 114 of FIG. 4 at time t~, all word lines in the\nunselected memory blocks arc capacitively coupled to about\nvolts, and data of memory transistors in the unselected\nmemory blocks is not erased. However; during the time\nperiod between t2 and t3, every memory transistor In the\nselected memory block is changed into a D-type transistor\nhaving a threshold voltage of about -2 to -3 volts by the\nerase voltage which is applied between its channel and\ncontrol gate. That is, logic \"0\" data is stored.\nOn the other hand, during the block erasing period\nbetween t2 and t,, since the selected block selection control\nline is at the potential of about 4.3 volts, and upper and lower\nselection gate lines USOLI and L.SGU are at about 2 to 3\nvolts, and upper and lower ground selection lines IJGSL and\nLGSL are at 5 volts, the first upper and lower selection lines\nUSL1 and LSL1 associated with the selected memory block\nare at about 2 to 3 volts and the second upper arid lower\nselection lines USL2 and LSL2 associated with the selected\nmemory block are in floating states. l'hus, when any one of\nthe second upper and lower transistors connected with the\nsecond upper and lower selection lines fails, the flow of\nleakage current is prevented via the second upper and lower\nselection lines USL2 and LSL2 from the well electrode 114.\nDuring the block erasing operation, the voltage relationship\nof significant portions may be summarized in the following\nTABLE 4.\n\n\n\nSelected Meencry\nStock\n\nUnselected Mensery\nBlock\n\nPtxit Uppec And Low~\nSelection Liner USLI\n\nApproximately\n-3 V\n\nHo.iing\n\nAnd LSLI\n\n\n\nWorsi Uner WLI xc WLZ\nSeonod Upper And Lower\nSeleedon Uma USL2\nV\nflosdeg\n\nApproximately ~ V\nF1cati~g\n\nand LSL2\n\n\n\nWeliriectrode\nV\nV\n\nThe time period between t3 and t4 of FIG. 16 is for\ndischarging word lines in unselected memory blocks to the\nreference potential During this period, control gate lines\nCGLI to CGLS maintain the reference potential by the\ncontrol signal DS as previously discussed in connection with\nFIG. 6. The control signal BLK nlnxntnina all block selection\ncontrol lines ESCI to BSCSI2 to about 4.3 volts, thereby\ncausing all word lines to be discharged to the reference\npotential. Upper and lower gate lines UGU and LSGU are\nalso maintained at the reference potential by Xd. On the\nother hand, the line DCB being at \"H\" level causes bit lines\nto be discharged to the reference potentiaL\nFIG. 17 shows a timing chart of the programming mode\nof the modified embodiment. Referring to FIG. 17, the data\nloading operation is performed prior to time t1. The data\nloading operation is performed in the same meaner as that of\nthe first embodiment as discussed in connection with FIG.\nb. The time period between t1 and ciii for writing data Into\nselected memory transistors. As discussed in the data load-\ning operation of the first embodiment, bit lines correspond-\ning to memory transistors into which logic \"1\" data is\nwritten are at \"L\" level of 0 volts while bit lines correspond-\ning to memory transistors into which logic 17' data is\nwritten are at \"H\" levels of 5 volts. After the time t1, the\nselected control gate line goes to the program voltage V,,,,\nof 18 volts, and unselected control gate lines go to the pass\nvoltage V,,~, of 10 volts as previously discussed in connec-\ntion with FIG. 6. It is now assumed that the fourth control\ngate line CGL4 was designated by address signals. Then, the\ncontrol gate line COLA goes to the program voltage V,,, of\nvolts and control gate lines CGL1 to CGL3 and CGLS to\nso COL8gotothepass voltage V,,,,of l0volts.Itis also\nassumed that the third memory block was designated by\naddress signal arid the address signal A11 was \"If' level.\nThen, the decoder 322 of FIG. 14 outputs \"L\" level and the\nblock selection control line BSC3 goes to the program\nvoltage V,,,,, of 18 volts after the time t1. At this time, the\nupper selection gate line USGL3 goes to the potential of 5\nvolts and the lower selection gate line LSGL3 goes to the\n\nTABLE 4\n\nCase 9:02~cv~000584H Document 20 FHed 04/03/2002\n,546,341\n\nPage 108 of 127\nreference potential. Thus, the transfer transistor array 34-3\nof FIG. 13a is wrnedoo. On the other hand, the ground line\ndriving circuit 320 of FIG. 15 provides the reference poten-\ntial onto the lines UGSL arid LGSL during the programming\nperiod. Thus, the second upper and lower selection transis- 5\ntors UST2 and LST2 in the upper and lower memory blocks\nUSBK3 arid LSBK3 are all nonconductive. The first lower\nselection line LSL1 in the lower memory block LSBK3 also\ngoes to the reference voltage via the transfer transistor BT11,\nthereby causing the first lower selection transistors LSTI to\nbe turned off. However, the first upper selection line USL1\nin the upper memory block USBK3 goes to \"H\" level of 5\nvolts via the transfer transistor BT1. During the above-\nmentioned programming operation, the voltage relationship\nof significant portions may be summarized in the following\nTABLE 5.\n\n\n\nTABLE 5\n\n\nSe\n\ntoned Memory Block\n\nUnselected Lowm\n\n\nSelected Upper\n\n\nMemory Block\n\nMemory Block\n\nSelected Pint Upper\n\nSV\n\n-\n\nSelected Line USLI\n\n\n\nUn..I~M First Lower\n\n-\nV\n\nSelected Line LSLI\n\n\n\nSelected Werd Line\nU'~\"WordLine\nSelected Second Upper\n\nV,,,.,. ISV\nV,,,=IOV\nV\n\nV * ISV\n~=tOV\n-\n\nSelection Lion USL2\n\n\n\nUnselected Second Lower\n\n-\nV\n\nSelection Line LSL2\n\n\n\nWcllElcclxodc\n\nOV\n\nOV\n\nThus, during the programming operation, the high voltage\napplied onto word lines WL1 to WL8 causes the NAND cell\ncharging of upper and lower memory blocks USBK3 and\nLSBIC3. Thus, since the first upper selection line USL1 is at\nthe potential of 5 volts, and bit lines associated with memory\ntransistors into which logic \"0\" data is written are at 5 volts\nwhile bit lines associated with memory transistors into\nwhich logic \"1\" data is written are at the reference potential\nof 0 volts, first upper selection transistors in the upper\nmemory block USBK3 which are connected with the latter\nmemory transistors am turned on, arid ~xst upper selection\ntransistors in the memory block USBIC3 which ate con-\nnected with the former ntemo~y transistors am turned off.\nThis, sources, drains and channels of memory transistors in\nNAND cells associated with the fanner memory transistors\ngo to the x~uuiss potaxial, and NAND cells associated\nwith the latter ~ay transistors are charged to a high\nvoltage. C- :~1Iy, during the programming period,\nfloating gates at the 1~mer memory transistors connected\nwith the upper watd line WL4 ~umulate electrons by way\nof the F-N ?~t~wling, thereby changing into enhancement\ntransistors having a threshold voltage of about 0.8 volts.\nThat is, logic \"1\" data is stored. However, since channels of\nthe latter memory transistors and junction capacitors of their\nsources and drains are charged with a high voltage, the\nprogramming of these memory transistors is prevented.\nIn the same manner, the first lower selection line LSL1\nand the second lower selection line LSLZ in the unselected\nlower memory block L.SBK3 are at the reference potential,\nand the first and the second lower selection transistors LST1\nand LST2 which are respectively connected to the lines\nLSL1 and LSL2 are thereby turned off. Thus, channels of 65\nmemory transistors of NAND cells in the lower memory\nblock LSBK3 and junction capacitors of their sources and\ndrains are charged with a high voltage so as to prevent\nprogramming.\nAt the time t2, the programming operation is terminated\nand the clock $, stops clockng. Thus, the charge pump\ncircuit 348 is disabled and BSC3 thereby falls to the poten-\ntial of 5 volts. During the time period between t1 and LI~ the\ncontrol signal DS at \"L\" level causes control gate lines\nto CGL8 in be grounded. Thus, word iinC~ in the\nmemory block SBK3 are discharged to the reference pocen-\n~ us!. During the time period between t, and t4. block selec-\ntion control lines BSC1 to BSCSI2 and upper selection gate\nlines USGL1 to USGL512 are discharged to the reference\npotential.\nThe programming verification operation may be per.\nformed from the time t4 of FIG. 17. The programming\nverification operation is similar to that of the first embodi-\nmerit. The difference as compared with the first embodiment\nis in that the present embodiment has the block selection\ncontrol circuit for selecting one of either the upper or lower\n~ memory block in a selected memory block. If the upper\nmemory block USBKi in a selected memory block is\nselected by means of the block selection control circuit of\nFIG. 14 in the programming verification operation, a\nselected block selection control line BSCI goes to the\n~ potential of about 4.3 volts, and the upper selection gate line\nUSGU goes to the potential of 5 volts. Then, the ground line\ndriving circuit 320 of FIG. 15 outputs \"If' level of 5 volts\nonto the uppe selection gate line UGSL and \"L\" level of 0\nvolts onto the lower selection gate line LGSL As discussed\nin connection with the first embodiment with reference to\nFIG. 6, in the programming verification operation, a selected\ncontrol gate line is at the program verifying voltage of 0.8\nvolts and unselected control gaze lines are at the potential of\nvolts. Thus, the line BSCI of about 43 volts connected to\n~ the transfer transistor array 34i of FIG. 13a goes to a\npotential of about 7 voha since the potential of 5 volts on the\nunselect~ri control gate lines is transferred from drains of\ntransfer transistors to their gales by way of capacitive\ncoupling. This operation is also identical in a reading\n~ operation. Consequently, a selected wont line in the upper\nmemory block USBKi goes to the verifying voltage of 0.8\nvolts and unselected word lines go to the potential of 5 volta.\nfirst arid second upper selection lines USL.1 and USL2\nalso go to the potential of S volts. Thus, second selection\n~ transistors UST2 In the block USBKi are tinned on, thereby\nconnecting NAND cells In the block USBKI to the grounded\ncommon source line CSL However, the first and second\nlower selection lines LSL1 and LSL2 in the lower memory-\nblock LSBKI are at the reference potential and the block\nare at the reference potential and the block LSBKI\nare at the rekrcnce potential and the block LSBKI is thereby\nunselected. The following programming verification and\nreprogramming operations are the same as operations\nexplained in the first embodiment in connection with the\ntiming chart during the time period between LI and (4 of FIG.\n.\nIn the modified embodiment, programming and repro-\ngrainming techniques do not need a program inhibition\nvoltage generator connected with the respective bit lines to\ninhibit programming of logic \"0\" programmed cells and\nreprogramming of successfully logic \"1\" programmed cells.\nThus, the simplification of a peripheral circuit and the\nreduction of on-chip area can be accomplished. Otherwise,\nsince the program inhibition voltage is automatically gen-\nerated by the capacitive coupling technique during the\nprogramming and reprogrnmtning operations, the program-\nming and reprogramming operations may be executed at a\n\nCase 9:02~cv~000584H Document 20 FHed 04/03/2002\n,546,341\n\nPage 109 of 127\nhigh speed. Thus, since the present embodiment employs a\nself-program inhibition technique, the above-mentioned\nadvantages may be accomplished.\nIn the reading operation of the modified embodiment, a\nselected word line of 0 volts is used instead of the selected 5\nword line of 0.8 volts in the above-mentioned programming\nverification operation. Operation to select memory transis-\ntors in the reading operation is the same as that in the\nprograming verification operation. Page reading, page read-\nout sensing and the output from data output terminals are\nalso the same as operations explained in the first embodi-\nment in connection with FIG. 12.\nThus, EEPROMs of embodiments of the present inven-\ntion as described above can be designed so as to have\ncapabilities and reliability of improved programming, block is\nerasing and programming verification. The peripheral cir-\ncuits associated with a reading and a programming verifi-\ncation according to embodiments of the invention can also\nbe used in a nonvolatile semiconductor memory with a\nNOR-type memory array.\nWhat is claimed is:\n. A nonvolatile semiconductor memory comprising:\nword lines formed over a surface of a semiconductor\nsubstrate;\ncell units arranged on said surface to form an array, each ~\nsaid unit including at least one memory transistor\nwhich has source and drain regions formed in said\nsubstrate and separated by a channel region; a floating\ngate formed over said channel region, and a control\ngate formed over said floating gate and coupled to a 30\ncorresponding one of said word lines, said array being\ndivided into a plurality of memory blocks each having\na plurality of cell units; and\na control circuit, responsive to sit address. ins data erase\nmode, for applying an erase voltage to said substrate, ~\nand for floating word lines of memory blocks unse-\nlected by said address so that erasure of data in memory\ntransistors of said unselected memory blocks is pre-\nvented by capacitive coupling of a predetermined\namount of said erase voltage to said wont lines of said ~\nunselected memory blocks.\n. A method for erasing data stored in a nonvolatile\nsemiconductor memory, during a data erase mode of opera-\ntion thereof, said memory cociprising an army of cdl units\nformed on a surface of a sesnic~1n~rw substrate. each said ~\ncell unit including at least one memory transistor for storage\nof data each of said memory transistors having a floating\ngaze and a control gate coupled to a cocresponding one of a\nplurality of word lines, said array being divided into a\nplurality of ine~~ blocks each being comprised of a\nplurality of cdl ~ta, said method comprising the steps of:\napplying an c~e voltage to said substrate;\napplying a reference voltage to word lines of a selected\nmemory block in order to erase data of memory nan- ~\nin said selected memory block; and\nfloating word lines of unselected memory blocks such chat\nsaid data in said memory transistors of said unselected\nmemory blocks is prevented from erasure by capacitive\ncoupling of a predetermined amount of said erase so\nvoltage to said wont lines of said tmeclected memory\nblocks.\n. A method for preventing erasure of data in memory\ntransistors in unselected memory blocks in a nonvolatile\nsemiconductor memory, wherein said memory comprises a 65\nmultiplicity of cell units formed on a surface of a semicon-\nductor substrate and configured in an army, each cell unit\nhaving at least one memory transistor which has a source, a\ndrain, a floating gate, and a control gate connected to a\ncorresponding one of a plurality of word lines, wherein said\narray is divided into a plurality of memory blocks each\nincluding a plurality of said cell units and word lines, said\nmethod comprising the steps of:\nfloating word lines of said unselected memory blocks; and\napplying an erase voltage to said substrate sn that data in\nsaid memory transistors of said unselected memory\nblocks is prevented from being erased by capacitive\ncoupling of a predetermined quantity of said erase\nvoltage to said word lines of said unselected memory\nblocks.\n. A method for preventing erasure of data in unselected\ncell units in a nonvolatile semiconductor memory, wherein\neach cell unit is formed on a surface of a semiconductor\nsubstrate and includes a plurality of memory transistors\nconnected in series, each said memory transistor having\nsource and drain regions formed in said substrate and\nseparated by a channel region, a floating gate formed over\n~ said ith2nn~I region to score binary data, and a control gate\nformed over said floating gate, respective control gates of\nsaid memory transistors of said cell unit being connected to\nrespective ones of a plurality of word lines, said method\ncomprising the steps of:\napplying an erase voltage to said substrate; and\ncapacitively charging said word lines of said unselected\ncell units to a pretermined amount of said erase voltage.\n. An electrically erasable and programmable read-only\nmemory comprising:\na semiconductor substrate;\nan array of cell units, said cell units arranged in rows and\ncolumns on said substrate, said array being divided into\na plurality of memory blocks, with each memory block\nbeing defined by at least a given one of said rows of\nsaid cell units, each of said cell units including a\npredetermined number of series connected memory\ntransistors and each of said memory transistors having\na floating gate and control gate;\na plurality of word lines arranged such that said control\ngazes of memory transistors in a given row are con-\nnected to a same ward line and said control gates of the\nmemory transistors in a given column am connected to\ndifferent word lines; and\na control circuit for floating word lines of unselected\nblocks and applying an erase potential to said\nsubstrate so that data in memory transistors of said\nunselected memory blocks is prevented from being\nerased by capacitive coupling of a predetermined quan-\ntity of said erase potential to said word lines of said\nunselected memory blocks.\n. An electrically erasable and programmable read-only\nmemory as recited in claimS, wherein said control circuit\napplies a low potential to word lines of a selected memory\nblock thereof in order to erase data of memory transistors of\nsaid selected memory block.\n. An electrically erasable and programmable read-only\nmemory as recited in claim 6, wherein said erase potential\nis a high potential and said low potential is a ground\npotentiaL\n. An electrically erasable and programmable read-only\nmemory comprising:\na semiconductor substrate;\na multiplicity of memory transistors arranged in rows and\ncolumns, each memory transistor including a floating\ngate and a control gate;\n\nCase 9:02~cv~00058~H Document 20 FHed 04/03/20G2 Page 110 of 127\n,546,341\na plurality of word lines each connected to said control\ngates of respective ones of said memory transistors in\na corresponding tow;\na control circuit, responsive to an address in a data erase\nmodc, for floating word lines unselected by said\naddress, and for applying an erase voltage to said\nsubstrate so that erasure of data in memory transistors\nassociated with said unselected word lines is prevented\nby capacitive coupling of a predetermined amount of\nsaid erase voltage to said unselected word lines.\n. An electrically erasable and programmable read-only\nmemory comprising:\na semiconductor substrate;\na multiplicity of memory transistors arranged in rows and\ncolumns on said substrate to define a plurality of cell\nunits each of which includes a predetermined number\nof scncs-connccted memory transistors, each of said\nmemory transistors having a floating gate and a connul\ngate;\na plurality of memory blocks being defined by respective\nrows of said cell units;\na plurality of word lines each connected to the control\ngates of the respective ones of the memory transistors\nin a corresponding row; and\na control circuit for floating word lines of memory blocks\nnot required to be erased and applying an erase poten-\ntial to said substrate, thereby capacitively coupling a\npredetermined amount of said erase potential to said\nfloated word lines to prevent erasure of data in said\nmemory transistors connected to said floated word\nlines.\n\n* * * * I\n\nCase 9:02~cv~00058~JH Document 20 FHed 04/03/2002 Page 111 of 127\n\n[54] AUTO.PROGRAM CIRCUIT TN A\nNONVOLATILE SEMICONDUCrOR\nMEMORY DEVICE\n\n[75] Inventors: Jin-KI Kim; Hyung-Kyu Urn;\nSung-Soo Lee, all of Seoul. Rep. of\nKorea\n\n(731 Assignee: Samsung Electronics Co., Ltd.,\nSuwon, Rep. of Korea\n\n[21] AppL No.: 526~422\n\n[221 Filedi Sep. 11, 1995\n\n[30] Foreign Application Priority Data\nSep. 9, 1994 [KR] Rep. of Korea 22769/1994\nJan. 24, 1995 [KR] Rep. of Korea _~.._._. 1144/1995\n[51] Tnt. CL6 -----.____ GI1C 7/00; G1IC 1&~)4\n(52] U.S. CL ____...___ 365/185.22; 365/185.2;\n/189.07; 365/189.09\n[58] FIeld of Search ..__ - 365/189.01, 185.01,\n/182, 218\n\n(56]\n\nRderences Qted\nUS. PAThNT DOCU?~NTS\n,379,2.56 1/1995 TanakaetaL _.__----. 365/185\n.386,422 1/1995 Endth et .1. ...__.~_. 37lt2L5\n,396,468 3/1995 Harari et al. ___. 365'2l8\n,428,569 6f 1995 Kato et al. ___.~_~ 365/189.01\n,434,825 7/1995 Harari .._..__.......~.... 365/185\n,450,341 9/1995 Sawada Ct al. ____~. 365/185\nPrimary Eramine,'-Viet Q. Nguyen\nA#orrs~ Agenl or Finn-Cushnraa Darby & Cushman, IP\nGroup of Pillsbury Madison & Sutro LLP\n\n(57]\n\nABS~RAC~\nAn auto-program voltage generator in a nonvolatile semi-\nconductor memory having a plurality of floating gate t~e\nmemory cells, program circuit for progran~ming selected\nmemory cells, and program verification circuit for verifying\nwhether or not the selected memory cells are successfully\nprogrammed comprises a high voltage generator for gener-\nating a program voltage, a trimming draiit for detecting the\nlevel of the program voltage to inorease sequentially the\nprogram voltage within a predetermined voltage range every\ntime the selected memory cells are not successfully\nprogrammed, a comparing circuit for comparing the\ndetected voltage level with a reference voltage and then\ngenerating a comparing signal, and a high voltage genera-\ntion control circuit for activating the high voltage generator\nIn response to the comparing signaL\n\nUnited States Patent (l9~\nKim et aL\n\nl1L\nUS0056. )9A\n[11] Patent Number: 5,642,309\n(451 Date of Patent: Jun. 24, 1997\n,291,446 3/1994 Van Ba\ufffd~i1 et aL -. 365/189.09\nClaims, 10 Drawing Sheets\n\nCase 9:02~cv~000584H Document 20 FHed 04/03/2002\n\nPage 112 of 127\n\nU.S. Patent\n\nJun. 24, 1997\n\nSheet 1 of 10\n,642,309\nFIG. I\n\nCase 9:02~cv~000584H Document 20\n\nFHed 04/03/2002 Page 113 of 127\n\nU.S. Patent\n\n\nPGM~\n\nJun. 24, 1997\n\nSheet 2 of 10\n,642,309\n\nLP4\n\nLP2 LPi\n 7\n\nTRMpi\n\nTRMp2\n\nTRMp3\n\nTRMp9\n\nFIG. 2\nFIG.\nCase 9:02~cv~00058~JH Document 20\n\nFHed 04/03/2002\n\nPage 114 of 127\n\nU.S. Patent\n\nJun. 24, 1997\n\nSheet 3 of 10\n,642,309\n~.\n-J\n~\n\n+ +\nb `0\n\n(o\\\n\nCf D\n\nCo\n\nA\nCase 9:02~cv~00058~H Document 20\n\nFHed 04/03/2002 Page 115 of 127\n\nU.S. Patent\n\nJun. 24, 1997\n\nSheet 4 of 10\n,642,309\n\nSapgm\nPDS\nPCout\n\nLPi\nNO\nLP2\nNi\nLP3\nN2\nLP4\nN3\n\nFIG.\n\n\nFGM\n\nFIG. 5\n\n\n\nPCout\n\nN6\n\n~m\nCD\na\n% 0\no\n-`a\nCA)\no\nSapgm\nPGM\nPGMs\n~sP\nLPi\nLID2\nLID4\nTRMpi\nTRMp2\nTRMpa\nTRMP4\n\n\nVpgzn\nPDS\n\nC)\nCD\nC,)\nCD\n(0\nN)\nC)\nC\n\n(71\nco\nI\n\nC\nID\n\n\na-\n\nFIG. 7\n\nTIME\n\n(n\n\n\nLa\nC\n\\0\n\nN)\n-4\n\nCase 9:02~cv~000584H Document 20 FHed 04/03/2002\n\nPage 117 of 127\n\nU.S. Patent\n\nJun. 24, 1997\n\nSheet 6 of 10\n\n-J\n>-\n~\n\n-J\n:\n\n~\n,642,309\n\n<Eo c ~ r~- c.o LI) o\n~- ~- ~- ~- ~-\n>\n\nCase 9:02~cv~000584H Document 20\n\nU.S. Patent jun. 24, 1997\n\nFHed 04/03/2002 Page 118 of 127\n\nSheet 7 of 10 5,642,309\n\n\n* . I\n\n\n. . I\n\n\n* a *\n\n\na S S\n\nFIG. 9\n\n. I S\n\n\n. I I\n\nBLm\n\nCase 9:02~cv~00058~H Document 20 FHed 04/03/2002 Page 119 of 127\n\nU.S. Patent\n\nJun. 24, 1997\n\nSheet 8 of 10\n,642,309\n/\n\nFIG. 10\n\nCase 9:02~cv~00058~H Document 20 FHed 04/03/2002 Page 120 of 127\n\nU.S. Patent\n\n\nPGM\nFGMs\n~sP\nLP~\nLP4\nTRMpi\nTRMP2\nTRMPS\nTRMp4\n\nJun. 24, 1997\n\nSheet 9 of 10\n,642,309\n\nTIME\n\nFIG. 11\n\nCase 9:02~cv~00058~dH Document 20 FHed 04/03/2002 Page 121 of 127\n\nU.S. Patent\n\n\nVOLT\n\nJun. 24, 1997\n\nSheet 10 of 10\n,642,309\n\n\n\n\na\nFIG. 12\n\nVpgmmax\n\n\nVpassmax\n\n\nPROGRAM LOOP(CYCLE)\n\nCase 9:02~cv~00058~dH Document 20 FHed 04/03/2002\n\nPage 122 of 127\nAUTO-PROGRAM CIRCUIT IN A\nNONVOLATILE SEMICONDUCTOR\nMEMORY DEVICE\n. FIeld of the invention\nThe present invention relates to a nonvolatile semicon-\nductor memory device, and more particularly to an auto-\n~rogram circuit in the nonvolatile semiconductor memory\ndevice.\n. Desoription of the Related Arts\nA memory cell array with NAND structured cells has a\nplurality of NAND cell units arranged in a matrix with\ncolumns and rows. FIG. 9 is an equivalent circuit diagram\nshowing a part of the memory cell array with conventional\nNANT) structured cells. Referring to the figure, each of the\nNAND cell units NUI to NlJm has a first selection transistor\nwith its drain connected to the corresponding bit line\nand a second selection transistor 121 with its source con-\nnected to a common source line CSL The drain-source\nchannels of memory cell transistors Ml to M8 (hereinafter\nreferred to as \"memory cell?) are serially connected\nbetween a source of the first selection transistor 1.20 and a\ndrain of the second selection transistor 121. The gates of the\nfirst selection transistors 1.20, the control gates of the\nmemory cells Ml to MS and the gates of the second\nselection transistors 121 are connected to a first selection\nline SL1, word lines WL1 to WLS and a second selection\nline SL2, respectively. The first and second selection tran-\nsistors 120 and 121 and the memory cells Ml to MS are\nformed in the P type well fanned on the main surface of a\nsemiconductor sub~ate. The source-drain common region\nbetween the source of the first selection transistor 120 and\nthe drain of the memory ccli Ml, the source-drain common\nregions of the memory cells Ml to MS, and the drain-source\ncommon region between the drain of the second selection\ntransistor 121 and the source of the n~nory cell MS are\nformed in the P type well.. A floating gate mede of polysili-\ncon is fanned on each channel of the nrnw~y cells Ml to\nMS tLaough a tunnel oxide Layer, and a floating gale made of\npolysilicon or of metal flidd~ with high t'~\"g point Is\nf~d thereon through an in~diatc Insnl~4ng 1a~u~\nThe drain regions of the first selection transistors 120\nformed in the P type well am respectively connected to the\ncorresponding bit lines made ci ~1 silidde with high\nmelting point or ~L through openings, the source regions\nof the second se.k~os transistors 121 formed in the P type\nwell are connected ~ the c~mI1~ ~o~jj~e (51_ made of\nthe metal silicide with high ~IHng point or metaL The erase\noperation for the memory cells Is performed before\nprogramming, i.e., writing data.\nThe erase operation for the memory cells Is performed by\napplying erase voltage of about 20 V to the P type well\nregion and reference voltage, i.e., ground voltage to the\nword lines WL1 to WLS. With the ele~oos stored in the\nfloating gates being emitted to the P type well region tia~ough\nthe tunnel oxide Layer, the memory cells are ctanged to\nenhancement mode transistors. It can be assumed that the ~\nerased memory cells store the data \"1\".\nThe programming operation for the ma~in~y cells con-\nnected to the selected word line, i.e., the writing operation of\nthe data \"0\" Is performed by applying program voltage of\nabout 18 V to the selected word line and the reference\nvoltage, Le the ground voltage Vss to the sources and\ndrains of the memory cells in which the data \"0\" is written.\nThen, the floating gates of the mc~y cells to be pro-\ngrammed accumulate the electrons thorough the tunnel\noxide layers, and these memory cells are changed to the\ndepletion mode transistors.\nAfter programming, the proc verification operation is\nperformed to verify whether or not the selected memory\ncells are successfully programmed to have a predetermined\nconstant threshold voltage value. These erase, program and\nprogram verification techniques are disclosed in the Korean\nPatent Publication No. 94-18870 published Aug. 19, 1994\nand assigned to the present inventor.\nAs the capacitance of the EEPROM has become highly\nintegrated, the size of the memory cell, such as the width and\nthickness of the gate oxide layer and the width and length of\nthe channel region, has been reduced. However, variance of\nthe manufacturing process can not secure the uniformity of\nthe wi~kh and thickness of the gate oxide layer, intermediate\ninsulating layer and channel region. This makes the thresh-\nold voltage values of the programmed memory cells\nunequaL If at least one of the programmed memory cells\ndoes not reach a desired threshold voltage, emor data is read\nout. In order to solve such a problem, a program verification\ndevice has been proposed for verifying whether or not the\nselected memory cells are successfully programmed. For\nexample, audi a program verification technique is disclosed\n~ the aforementioned Korean Patent Publication No.\n-18870. However, as the reprogram operation is per-\nfanned after the program verification operation with a\nprogram voltage of constant level, the threshold voltages of\nthe pio~ramu~d memory celia are still unequal The van-\nance of the circumstance conditions such as a power supply\nvoltage or an operating temperature may deteriorate the\nreliability of the E~ROM~\n\nOF THE\nas It Is therefore an object of the present invention to provide\na nonvolatile semiconductor memory capable of maintain-\ning a nnif~ tlffeshold voltage of the memory cells to be\nprogrammed regardless of the variance of the operating\ntemperature and power supply voltage.\n~o it is another object of the present invention to provide the\nnonvolatile semiconductor me~~y capable of enhancing\nthe relIalalHty thereof regardless of the variance ci the\n~oceas.\nTo achieve the above objects of the present invention, an\nauto-program voltage generator of the nonvolatile semicon-\nductor m~nvIy having a plurality of floating gate type\nmemory cells, a program circuit for programming the\nselected ma.nw~y cells, and a program verification circuit for\nverifying whether or not the selected memory cells are\nsuccessfully programmed, comprises a high voltage genera-\ntor for generating a program voltage, a trimming circuit for\ndetecting the level of the program voltage so as to sequen-\ntially inorease the program voltage within a predetermined\nvoltage range every time the selected mmnory cells are not\nsuccessfully programmed, a comparing circuit for compar-\ning the detected voltage lcvd with a reference voltage and\nthen generating a comparing signal, and a high voltage\ngeneration co~ol circuit for activating the high voltage\nge~ator In response to the comparing signal.\nBRIEF DESCRIFI'ION OF TIlE DRAWINGS\nIn the detailed desoription of the prefrered embodiment of\nthe present invention presented below, reference is made to\nthe accompanying drawings, in whidu\nFIG. 1 is a diagram illustrating a program voltage gen-\nerator according to a preferred embodiment of the present\nInvention;\n,642,309\n\nBACKGROUND OF THE INVENI'ION\n\nCase 9:02~cv~00O58-~H\n\nDocument 20 F~ed 04/03/2062\n,642,309\n\nPage 123 of 127\nFIG. 2 is a diagram illustrating a thmming signal gen.\neratci according to the preferred embodiment of the present\ninvention;\nFIG. 3A is a diagram illustrating a binary counter accord-\ning to the preferred embodiment of the present invention;\nFIG. 3B is a diagram illustrating each stage in the binary\ncounter of FIG. 3A\nFIG. 4 is illustrates a clock signal generator for generating\na clock signal for driving the binary counter of FIG. 3A;\nFIG. ~ is a diagram illustrating a control signal generatcc\naccording to the preferred embodiment of the present inven-\ntion;\nFIG. 6 is a diagram illustrating a ioop counter according\nto the preferred embodiment of the present invention;\nFIG. 7 is a timing diagram showing the operations of each\npaxt of the cfraiits related to the program voltage generator\naccording to the preferred embodiment of the present inven-\ntion;\nFiG. 8 is a diagram showing the relation between the\nprogram ioop and the program voltage acarding to the\npreferred embodiment of the present invention;\nFIG. 9 is an equivalent circoit diagram showing a part of\nthe memory cell array with conventional NAN]) structured\nmemory cells;\nFIG. 10 is a schematic circuit diagram showing a pass\nvoltage generator according to the jrefetred embodiment of\nthe present invention;\nFIG. 11 is a timing diagram showing the operation of each\npart of the circuits related to the pass voltage generator\naccording to the preferred embodiment of the present inven-\ntion; and\nFIG. U Is a diagram showing the relation between the\nprogram ioop and the program voltage and pass voltage\naccording to the preferred embodiment of the present inven-\ntion.\nOF TEE\nPR~ERRED EMBODIMENT\nN-channel transistors of depletion mode (hereinafter\nreferred to as \"0 type transistors\") having a threshold\nvoltage of -1.8 V, N-channel MOS transistors of inhance~\nmeet mode (hereinafter referred to as \"N type translators\")\nhaving the threshold voltage of 0.7 V, and P-channel MOS\ntransistors (hereinafter ref~ed to as `P type transistors\")\nhaving the t~eshold voltage of -0.9 V are employed in the\npresent invention.\nPIG. 1 Illustrates a program voltage generator 200. In the\nfigure, a high voIta ge.erator ii functions to generate a\nprogram voltage `4gni In response to a charge pumping\nsignal $pp and Its c l~n~ntary signal pp ot4uued from\na high voltage g~~ion control circuit 20. The high\nvoltage generator ii is a well-known circuit for generating\nthe program voltage Vpgin higher than the power supply\nvoltage Vcc by ufThring a charge pninping method. The high\nvoltage generator 10 comprises an N type transistor 17 for\nproviding an initial voltage Vcc-Vth to a node 1, N type\ntransistors U to 16 having their own channels serially\nconnected between the node 1 and an output node 2, and\nMOS capacitors 3 to 8 respectively connected to the gates of\nthe N type transistors U to 16. The gates of the N type\ntransistors 11 to 16 are respectively connected to their\nand the chain-source common nodes of odd MOS\ncapacitors 3,5, and 7 and the drain-source common nodes of\neven MOS capacitors 4,6, and 8 are connected to the charge\npumping signal 4\ufffdand its complementary signal ~pp,\nrespectively.\nThe channels of the I) type transistors 18 and 19 are\nserially connected between the output node 2 of the high\nvoltage generator 10 and the power supply voltage Vcc, and\nthe gates thereof are respectively connected to a program\n~ control signal POM and the power supply voltage Vcc. At the\ncompletion of the program operation, the D type transistors\nand 19 ftnction to discharge the program voltage Vpgm\nto the power supply voltage Vec.\nA trimming circuit 30 for sequentially increasing the\n~ program voltage Vpgxn during the program operation is\nconnected to the output node 2. Between the ground voltage\nVss and the output node 2 is connected the trimniing circuit\nin which the channel of an N type transistor 31 and the\nresistors R1 to R10, P.,, and R,,, are serially connected one\n~ another and the gate of the N type transistor 31 is connected\nto the program control signal ~i through an inverter 32. A\nconnection node 37 between the resistors P.,, and P.10 is\nconnected to a connection node 38 between the resistor R~\nand the drain of the N type transistor 31 through the channel\nof an N type transistor 33. The connection nodes between the\nresistors P.10 to R1 are respectively connected to the con-\nnection node 38 through the channels of the transistors 34\nand 35. The gates of the transistors 33 to 35 are respectively\nconnected to the trimming signals ThM~ toThM,~. The\n~ transistors 33 to 35 are bypass means for bypassing the\nresistors R1 to R10, sequentially.\nAcompaning &coit4O functions to compare the reference\nvoltage Vpref with the voltage V,5 of the connection node\nbetween the resistors R,~ and R,,. In the comparing circuit\n~o 40, the channel of a transistor 41 is connected between the\nground voltage Vu and a common node 46, and the gate\nthereof is connected to the program control signal PGM\nthrough an lnverter 47. A that heandi In which the channels\nof the P type transistor 44 and N type transistor 42 are\n~ serially connected and a second Inandi in which the chan-\nnels of the Ptypelransistor4s andNtype transistor 43 are\naerially connected are connected in parallel between the\npower supply voltage Vcc and the common node 46. The\ngates of the P type transistors 44 and 45 are commonly\n~ connected each other and are also connected to a connection\nnode 48 between the P type transistor 45 and the N type\ntransistor 43. The reference voltage Vpref~, i.e., about 1.67 V\nis applied to the gate o(theN type b~~~or43. The gate of\nthe N type wazslstor 42 ii connected to the common node 36.\n~ The connection node ~ between the P type transistor 44 and\nthe N type transIstor 42 serves as an output terminal of the\ncomparing circuit 40. The comparing cIrcuit 40 outputs the\nlogic \"low\" state If the voltage Vu>the reference voltage\nVprd, and outputs the logic \"high\" state if V,6<Vpref.\n~ The high voltage generation control circuit 20 is con-\nnected between the comparing circuit 40 and the high\nvoltage generator ii and fbnnions to control the program\nvoltage Vpgm to msi'~a4n a predetermined constant voltage\nleveL The high voltage generation control circuit 20 corn-\nss prises a NAND gate 22 having one input connected to the\nconnection node 49 and the other connected to the program\ncontrol signal ~ through an inverter 21. The first inputs of\nthe NAND gates 24 and 25 receive the output of the NAN])\ngate 22 through an inverter 23, and the secocd inputs thereof\nto respectively receive the dock pulses ~p and ~p from a ring\noscillator (not shown). At this time, the clock pulses ~p and\n~p have the frequency of about 8 MHz. The NAN]) gates 24\nand 25 output the charge pumping signals ~pp and ~pp\nthrough Investors 26 and 27.\nIf V,5>Vpref, the high voltage generation control circuit\nis Inactivated, and if V~<Vpref, it becomes activated.\nThus, if the program voltage Vpgan increases, the voltage\n\nCase 9:02~cv~00058~H Document 20 FHed 04/03/2002\n\nPage 124 of 127\nV,5 also inaease$. Therefore, the high voltage generation\ncontrol cIrcuit 24 is inactivated and thus the high voltage\ngenerator II redeces the program voltage Vpgm. On the\nother hand, if the program voltage Vpgm is too low, the high\nvoltage generator LI inaeases the program voltage Vpgm. s\nHence, the program voltage Vpgm maintains a constant\nvoltage level by the control of the high voltage generation\ncontrol crQit 20.\nAt the turn off state of the transistors 33 to 35, the initial\nprogram voltage Vpgmin on the output node 2 can be\nrepresented as follows:\n\n/ R.\nVpgmue=Vprrf~t+ R1+R2+...+R10+R.,+R.\n\n\nAt the turn on state of the transistor 35,the program\nvoltage V,,,,,,1 on the output node 2 can be represented as\nfollows:\n\nv,,., =VprOt( 1 + R,+.. .+R10+R.1+R. )\n\nAt the U~n on state of the transistor 34, the program\nvoltage V,,,,,,2 on the output node 2 can be represented as\nfollows:\n\n\n= R,+...+R~+R.+R.. ).\nvp_ ~+\n\nAs can be seen from the above equations, when the\ntransistors 35 to 33 are sequentially turned on., the program\nvoltage on the output node 2 am sequentially inereased.\nAccordingly, by sequentially performing the program and\nprogram verification operations with iner'easing the program\nvoltage sequentially within a predetermined voltage range,\ni.e., from 15 V to 19.5 V, the m~nc'y cells having constant\nthreshold voltages regardless of various changes such as the\nchange of the process and the change of the circumstance\nconditions can be implemented.\nFIG. 2 is a trimming signal generator 340 for generating\ntrimming rignali which sequentially inorease the program\nvoltage Vpgm with sequentially turning on the transistors 35\nto 33 in PIG. 1. The trlrnm~ng signal generator 311 has a\np&orallty of NOR gates SI toSS whidi receive the coanbi-\nnations of~ output signals 12, to 124 of a blixy counter\nand their compIPm~Jd~1ey signals i~ to 1i. The output of the\nNOR gate 55 is coupled to one input of a NOR gate 56 in\na flip-flop. The output 1 the NOR gate 56 Is spplied to the\nNOR gates 51 toSS ~uugh an Investor 58, and also to cue\ninput of a NOR gate 57. The utt~ input ci the NOR gate 57\nin the fiip.flcp is ~kid to the 5~ogram control signal\n~ and the ouqU thereof Is connected to the trimming\nsignal TRM,10 and also to the other input of the NOR gate\n. During the program operation, the flip-flop composed ci\nthe NOR gates 56 and 57 latdies the trimming signal\nTRM,.~O to the logic high\" state if the NOR gate 55 is\nselected, i.e., the NOR gate 55 outputs the logic high\" state.\nThe investor 58 provides the output of the NOR gate 56 as\na feedback signaL Thus, the NOR gates 56 and 57 and the\ninvestor 58 are latch means for latching the trimming signals\nTRM,., to TRM,.~, to the logic low\" state. Therefore, If the\nselected memory cell Is not successfully programmed even\nafter the completion of the tenth program verification\noperation, the program operations thereafter maintain the\ninoreased maximum program voltage Vpgxnmax level, i.e.,\n.5 V according to the pref~ed embodiment of the present\ninvention. As the maximum program voltage Vpgmmax is\nselected as the value capable of preventing the junction\nbreak down and the break down of the gate oxide layer of the\nmemory cell, it should be noted that the present invention is\nnor limited to the maximum program voltage level of 19.5\nV. In additioa, the present invention employs 10 trimming\nsignals, however, it Is not limited thereto, either~ However,\nit is desired that the program voltage ~v to be inereased\nevery program operation should be below 1 V, preferably\nbelow 0.5 V.\nFIG. 3A shows the binary counter and FIG. 3B a sche-\nmatic circuit diagram of each stage in the binary counter of\nFIG. 3A.\nReferring to FIG. 3B, the channels of N type transistors 65\n(1) to 68 are serially connected between an output terminal oi+l\nand its complementary output terminal ~i+l, the gates of the\ntransistors 66 and 67 are commonly connected to a comple-\nmentary clock input terminal ~i, and the gates of the\ntransistors 65 and 68 to the clock input terminal ci. An\ninvestor 64 is connected between the output tfrmin~] oi+1\nand its complementary output terminal ~i+1, a second input\n(2) ~ of a NAN]) gate 61 is coupled to.a connection node between\nthe transistors 65 and 66, and the output thereof to a\nconnection node between the transistors 66 and 67 through\nan inverter 63. A second input of the NAN]) gate 62 is\ncoupled to a conne~on node between the transistors 67 and\n~ 68, and the output thereof to the complementary output\nterminal ~i+1. Thus, If the reset signal of logic low\" state\nis applied to a reset tm~1ins1 1, the output terminal 01+3\nbecomes the logic low\" state and Its complementary output\nt~min~1 ~1+l becomes the logic Thigh\" state. In addition,\n,~, every time the Input of the Input t~min~l ci goes from the\nlogic \"high\" state to the logic low\" state, the output state of\nthe output t~rninal oi+1 is changed.\nThe binary counter 400 of FIG. 3A Is composed of 7\nstages serially connected one another. The reset 1~~nTha1\n~ I Is coupled to the reset signal i~, and the clock Inj~ut\nterminal Ci and its mpfrmn~i~y dock Input terminal 04 at\nthe first stage are respectively connected to the dock signal\nCX and Its complementary dock signal ~. The 7 stages 71\nto 77 output ccnnplementaiy counting signals ~ to i~ and\n~4, the4stages7lto74oatputthecountingsignalsLP1toLP4.\nEvery time the clock signal CX goes to the logic \"low\" state,\nthe counting sipais I2~ to LP4 am counted up and the\ncon\ufffdsnentaxy counting signals 1i to i~ are counted\ndOWL\n~j FK~. ~ is a clrailt diagram showing a clock signaL\ngc1~ator for generating the dock signal to be provided to\nthe binary counter 400 of PIG. 3A. In the figure, a program\nand verification signal ~ is generated from a limes (not\nshown) In response to the program control signal POM. The\nso dock signal geuemtcr comprises a short pulse generator $4\ncomposed of Investors 81 to 83 and a NAND gate 84,\ninvestors 85 to 88, and NOR gates 89 and 90. The NOR gates\nand 90 are comprised In a flip-flop. The short pulse\ngenerator 80 generates the short pulse of ~ low\" state\nss when the program and verification signal ~a goes to the\nlogic high\" state.\nFIG. S Is a schematic circuit diagram of a control signal\ngenerator for generating the reset signal i~ and the program\ncontrol signal ~ The control signal generator of FIG. 5\ngenerates the reset signal Lcr through a short pulse generator\nand inverters 92 and 93 in response to an auto-program\nflag signal Sapgxn outputted from a command register (not\nshown). The auto.program flag signal Sapgm is applied to a\nfirst input of a NOR gate 95 through an investor 94, a\nprogram detection signal PDS to a second Input thereof and\na loop counting signal PCout to a third input thereof. The\nNCR gate 95 outputs the program control signal POM\n,642,309\n\nCase 9:02-cv~00O58~jH\n\nDocument 20 F~ed 04/03/2002 Page 125 of 127\nthrough an investor 94. The program detection signal PDS is\ngenerated according to the program verification operatwn. If\nall the selected men~y cells have been successfully\nprogrammed, the program detection signal PDS becomes the\nlogic \"high\" state. On the contrary, if at least one of the\nselected memory cells has not been successfully\nprogrammed, the program detection signal PDS becomes the\nlogic \"low\" state. Such a program verification technique is\ndisclosed in the aforementioned Korean Patent Publication\nNo. 94.18870.\nFIG. 6 shows a loop counting circuit 500 for generating\nthe ioop counting signal PCout The loop counting circuit\nis a logic circuit composed of NAND gates 101 to 110\nand a NOR gate 111. The complementary counting signals\nu'~ to LP7 are applied from the binary counter 400 to the\nNAND gates 101 to 107, respectively. The temiinals NO to\nN6 are connected to the ground voltage Vss or to the power\nsupply voltage Vcc according to the ioop counting fre-\nquency. As the loop counting frequency is set to 20 accord-\ning to the preferred embodiment of the present invention, the\n_____ N2 and N5 are connected to the power supply\nvoltage Vcc, and the rem~ining terminals NO, Ni, N3, N4,\nand N6 are connected to the ground voltage Vu.\nThe auto-program circuit according to the preferred\nembodiment will be described with reference to the timing\ndiagram of FIG. 7.\nAs shown in FIG. 7, the auto-program operation starts in\nresponse to the transition of the auto-program flag signal\nSapgrn from the logic \"low\" state to the logic \"high\" state.\nAs the program detection signal PDS and the loop counting\nsignal PCout are in the logic \"low\" state at the beginning of\nthe auto-program operation, the control signal generator\ngenerates the program control signal ~~-- ci logic low\"\nstate in response to the transition of the auto-program flag\nsignal Sapgrn from the logic \"low\" date In the logic \"high\"\nstate. In addition, In response to the auto-program flag signal\nSapgm which goes to the logic \"high\" state, the short pulse\ngenerator 91 generates the short pulse of logic low\" state\nand thereby the binary counter 400 of FIG. 3A Is reset. As\nshown in FIG. 7, the timer (not shown) generates the\nprogram and verification signal ~ In response to the\ntransition of the program control signal from the logic\n\"high\" state to the logic low\" ~. The program and\nverification signal ~ Is the dock pulse which has the\nlogic low\" state of 30 psec and the logic 111gb\" state of 10\npsec when the program control signal ~ Is In the logic\nlow\". The duration when the program oo~ol signal\nremains the logic low\" date Is for the program operation.\nand the duration wben the program control signal r~1uin~\nthe logic \"high\" s~m Is for the program verification opera-\ntion.\nAt time t1 of P10.7, in response to the transition of the\nprogram control signaI~froan the logic \"high\" state to the\nlogic low\" state, the program voltage generator 200 of FIG.\nus enabled. That is, the transistor 41 is turned on, thus\nactivating the comparing circuit 40, and the transistor 31 is\nturned on, thus activating the trimming circuit 30. At the\nbeginning of the operation, as Vpret>V~, the comparing\nCircuit 40 outputs the logic \"high\" date. Hence, the investor\noutputs the logic \"high\" slate and thereby the high\nvoltage generation control circuit 20 generates the charge\npumping signal $pp and its complementary signal ~p.\nThus, the high voltage generator 10 generates the gradually\ninereasing high voltage by the signals pp and ~pp. The\nprogram voltage Vpgm Inoreases until the voltage V,4~ at the\nconnection node 36 reaches the reference voltage Vpref.\nConsequentially, the program voltage Vpgm maintains the\ninitial program voltage Vpgmin shown in the above-\ndesaibed equation (1). The technique for programming the\nselected memory cells with the program voltage Vpgni is\ndisclosed in the Korean Patent Publication No. 94-18870.\nAt time t~, the program and verification signal ~ goes\nto the logic \"high\" state, and the program verification\noperation for the programmed memory cells is performed\nduring the time between t1 and La~ In response to the program\nand verification signal ~ which goes to the logic \"high\"\n~ state at time t2, the short pulse generator 80 of FIG. 4\ngenerates the short pulse and the ijiverter 86 generates the\nshort pulse signal ~sp of logic \"low\" state. The clock signal\nCK is generated as a similar signal to the short pulse signal\nisp. Then, the binary counter 400 of FIG. 3A makes the\n`5 counting signal LP1 the logic \"high\" state as shown in FIG.\n. Thereby, the NOR gate 51 of FIG. 2 generates the\ntrimming signal TRM,.~ of logic \"high\" state. Thus, with the\nturn on state of the transistor3s of FIG. l, thercsistorR1 is\nbypassed, and the voltage V~ at the connection node 36\n~ becomes smaller than the reference voltage Vprei As a\nresult, the high voltage generation control circuit 20 is\nactivated and the high voltage generator 10 generates the\ninoreased program voltage V~ as shown in the above\nequation (2).\n~ If the selected nieinory cells are not successfully pro.\ngranimed during the program verification operation between\nthe time t2 and t,, i.e., the duration of 10 p5cc, reprogram\noperation is automatically performed with the iixzcased\nprogram voltage V~,1 during the time between t, and t4.\nAt time t4, if the program and verification signal ~.-`\ngoes to the logic \"high\" state, the short pulse generator 80\nof FIG. 4 generates the short pulse of logic low\" state, and\nthe Investor 86 outputs the short pulse ~sp of logic low\"\nstate as shown In FIG. 7. The dock signal CX becomes the\nshort pulse of logic low\" state, and the counting signals LP~\nand I2~ of the binary counter 400 become the logic low\"\nand logic \"high\" states, respectively. Thus, the NOR gate 52\nof P10.2 generates the trimming signal Tl~M,~ which goes\nto the logic \"high\" state. In response to the frimming signal\nTRM,2 of logic \"high\" state, the resistors R1 and R2 of FIG.\nare bypassed, and the voltage V,6 at the connection node\nbecomes \"for than the reference voltage Vprd.\nHence, the high voltage geom~alion control circuit 20 is\n~ activated, and thereby the high voltage genemtor 14 gener-\nates the program voltage V,~ as shown In the above\nequation (3).\nIf the selected n~ory cells are not successfully pro-\ngrammed regardless of the r~ogram operation, the pro-\n~o grain operation is performed again during the time between\nLa and t6. In the same way, with the sequential Inorease of the\nprogram voltage, the program and program verification\noperations are antonaatically performed until all the selected\nmemory cells are successfully programmed.\nThe timing diagram ci FIG. 7 shows the case that the\nselected memay cells are successfully programmed at the\nfifth program operation. After the completion of the fifth\nprogram operation, the program detection signal PDS indi-\ncating that the selected ~ory cells have been successfully\nprogrammed goes to the logic \"high\" state at the program\nverification operation between the time t50 and t~. Thereby,\nthe control 11~ generator of FIG. S makes the program\ncontrol signal .~*.` logic \"high\" state, and the circuits related\nto the program like a ring counter (not shown) are macti-\nvated. After about 2.5 p5CC after the program control signal\ngoes to the logic \"high\" state, the auto-program flag\nsignal Sapgm becomes the logic \"low\" date. It Is possible to\n,642,309\n\nCase 9:02~cv~00O58~jH\n\nDocument 20 FHed 04!03/20U2 Page 126 of 127\ndetect how many program Loops are oc~ed durin~ the 2.5\npsec with the complementary counting signals t2~ tO 12,\noutputted from the binay counter 444.\nFIG. 8 is a diagram showing the relation between the\nprogram Loop and the program voltage according to the\npreferred embodiment of the present invention. Refemng to\nFIG. 8, the program operations for the selected memory cells\ncan be performed as mudi as 20 times. The program voltage\nVpgm sequentially increases from 13 V to 19.5 V by 0.5 V\nuntil the tenth program operation. During the eleventh to\ntwentieth program operations, the program voltage Vpgm\nmaintains the maximum constant voltage level Vpgmmax of\nV by the latd, operation of the flip-flop composed of the\nNOR gates 56 and 57. If the selected memory cells are not\nsuccessfully programmed after the twentieth program\noperation, the 1oop counting circuit 500 of FIG. 6 generates\nthe ioop counting signal PCout which goes to the logic\n\"high\" state, and thereby the control signal generator of FIG.\ngenerates the program control signal ~i which goes to\nthe logic \"high\" state, thus stopping the generation of the\nprogram voltage Vpgin.\nAs desaibed above, the auto-program voltage generator\ngenerates the program voltage which inoreascs sequentially\nwithin a predetermined voltage range depending on the\nprogram loop according to the present invention. The pro-\ngram voltage is supplied to the selected word line. However,\nthe variance of the threshold voltage and the stress of the\nmemory cells which should not be programmed among the\nmemory cells connected to the selected word line should be\nprevented.\nIn the program operation of the conventional technique,\nthe pass voltage Vpass, i.e., a constant voltage of 10 V Is\napplied to the unselected word lines. For eraniple, assuming\nthat the word line WL2 Is selected, the i~&~frn~.m program\nvoltage Vpgmmax inoreased according to the program loop,\nLe., 19.5 V Is applied to the selected word line WT.2, the\nmemory cell M2 within the NAND cell unit NU2 should be\npro~iswwed as data \"0\", and the m~n~*y cell M2 within the\nNAND cell unit NU1 should be kept as the erase state, I.e.,\ndata \"1\", the power supply voltage Vco of 5 V is applied to\nthe first selection line SL1. the constant pans voltage Vpass\noflOVttheunseleedwordlinesWL1adWL3toWLg~\nand the ground voltage Vu to the second selection line SL2\n~n~ing the program operation. AX the same time, the ground\nvoltage Vu Is applied to the bit line BL2 related to the\nmei~ry cell M2 which Is to be progranuned as the data \"0\"\nwithin the NA}ID cell unit NUZ and the power supply\nvo1tageVccof5VI1~licdtothetitlineBL1relatedto\nthe memory cell MI w~th should be in the er~e date, i.e.,\nthe data \"1\" within the NA.ND cell unit NUt Then, the first\nselection transistor 124 withIn the NAND cell unit NUZ is\nturned on and thereby the n~~nrsy cdl MI within the\nNAN]) ccii unit NU2 is programmed as the data \"0\".\nHowever, as the power supply voltage Vcc 15 V is applied\nto the bit line BL1 connected to the NAND cell unit NU1\nand to the gate of the first selection transistor 120 within the\nNAN]) cell wilt NUI and the pass voltage Vpass of 10 V is\napplied to the control gate of the memory cell Ml within the\nNAND cell wilt NU1, the source of the first selection\ntransistor 124 Is charged with the pass voltage Vpass, and\nthereby the first selection transistor 120 is nirned off. Thus,\nthe source and drain of the memory cell MI within the\nNAN]) cell unit NU1 are charged with the pass voltage\nVpass (=10 V), and the inereased program voltage of 19.5 V\nis abruptly applied to the control gate of the memory cell\nM2. Therefore, the memory cell MI within the NAND cell\nunit NtJI receives the voltage stress of 9.5 V and thereby the\nthin tunnel oxide layer due to the variance of the manufac-\nturing process or the int~ediate insulating layer is broken\ndown. Meanwhile, the threshold voltage of the memory cell\nMi within the NAND cell unit NU2 is varied. Therefcre, the\n~ application of the constant pass voltage Vpass to the unse-\nlected word lines deteriorates the reliability of the\nEEPROM.. To solve such a problem, the preferred embodi-\nment of the present invention will be desoribed with refer-\nence to FIGS. 19 to 12..\nFIG. 10 shows a pass voltage generator for generating the\npass voltage to be applied to the unselected word lines.\nReferring to the figure, the pass voltage generator 600 has\nthe same structure as the program voltage generator 204) of\nFIG. 1 except that the values of the resistors R1' to R10, R~'\nand Rm' in the pass voltage generator 604 are different from\nthose of the resistors R1 to R~4,, R,, and R,~ in the program\nvoltage generator 200, and that the pass voltage Vpass\ninstead of the program voltage Vpgni is outputted from the\noutput node 2. The control signal generators shown in FIGS.\nto 6 are also employed to control the pass voltage\ngenerator 604. The pass voltage generator 604 generates the\npass voltage Vpass which increases sequentially from the\ninitial pass voltage Vpassin of 8 V to the maximum pass\nvoltage Vpassniax of 123 V according to the program loop.\nThe generation of the increasing pass voltage Vpass can be\nimplemented by using the proper values of the resistors R1'\nto R10, R,, and R,,,. The operations of the pass voltage\ngenerator 600 are identical to those of the program voltage\ngc1~ator 200 encept the value of the pass voltage Vpass,\nand audi will not be desaibed. The control signal generators\nshown in FIGS. 2 to 6 are employed In the pass voltage\ngenerator 600 of FIG. 10, and such will not be described,\ndth~\nPIG. 11 is a timing diagram for desaibing the operations\n~ of the pass voltage generator of FIG~ 10. FIG~ ~ is identical\nto P10.7 except that the pass voltage Vpass is generated\nInstead of the program voltage Vpgni.\nFIG. 12 is a diagram showing the relation between the\nprogram voltage Vpgm and the pass voltage Vpass accord-\n~o Ing to the program loop. As can be seen in the figure, the\nvoltage difference between the program voltage Vpgm and\nthe pus voltage Vpass maintaIns 5 V until the tenth program\noperation. Such a voltage difference can be ant properly\nacc*rding to the struenne or properties of the m~.y cells\nto prevent the insulation break down or the variance of the\nthreshold voltage of the nw~~y cells which should out be\n\nAs desaibed above, since the auto-program voltage gen-\nerator and the pass voltage generator according to the\nso present invention ge~ate the program voltage and pass\nvoltage which increase sequentially within a predetermined\nvoltage range, the reliability of the chip can be enhanced\nwithout the break down 1 the insulating Layer or the\nvariance of the threshold voltage of the memory cells which\nss should not be programmed. In addition, it is possible to\nachieve a uniform threshold voltages, and to enhance the\nperformance of the drip regardless of the change in process\nand the circumstance condition.\nWhat is claimed Is:\n. An auto-program voltage generator In a nonvolatile\nsemiconductor memory having a plurality of floating gate\ntype memory cells, program means for progr~Tnming\n~ memory cells, and program verification means for\nverifying whether or not said selected memory cells are\nsuccessfully programmed, said auto.program voltage gen-\nerator cornprking:\na high voltage generator for generating a program voltage;\n,642,309\n\nCase 9:02~cv~00058~H Document 20 FHed 04/03/200~\n\nPage 127 of 127\na trimming drcei for causing said program voltage to\nincrease seque~ally within a predetermined voltage\nrange every time one of said selected memory celLs is\nnot successfully programmed, said trimming cira.rit\nsequentially outputting a detected voltage level signal\ncorresponding to said sequentially increasing program\nvoltage;\na comparing circuit for comparing said detected voltage\nlevel signal with a reference voltage and then generat-\ning a comparing signal when said detected voltage level\nsignal is less than said reference voltage; and\na high voltage generation control circuit for activating\nsaid high voltage generator in response to said com-\nparing signal.\n. The auto-program voltage generator according to claim\n, wherein said trimming circuit comprises a plurality of\nresistors serially connected between a program voltage\ngeneration terminal of said high voltage generator and a\nsecond reference voltage, and a plurality of transistors for\nrespectively bypassing each of said plurality of resistors in\norder to increase sequentially said program voltage.\n. The auto-program voltage generator according to claim\n, wherein said trimming circuit comprises a plurality of\nbypass means to increase sequentially said program voltage.\n. The auto-program voltage generator according to claim\n, further comprising a trimming signal generator connected\nto said plurality of bypass means, for generating trimming\nsignals that are respectively supplied to each of said bypass\nmeans and allow for increasing sequentially said program\nvoltage.\n. The auto-program voltage generator according to claim\n, wherein said trimming signal generator comprises latch\nmeans for generating a constant voltage for each of said\ntrimming signals after said program voltage has been\nsequentially increased.\n. The auto-program voltage generator according to claim\n, further comprising a binary counter connected to said\ntrimming signal generator, for sequentially activating said\nplurality of bypass n~ans\n. The auto-program voltage generator according to claim\n, further comprising a binasy counter connected to said\ntrimming signal generator, for sequentially activating said\nplurality of bypass\n. The auto-program voltage generator according to claim\n, further comprising a loop counting circuit for stoj\ufffdg the\ngeneration of said program voltage in response to counting\nsignals outputted from said binary counZer~\n. An auto-program voltage generating method of a non-\nvolatile semiconductor memory which performs sequen-\n~ tinily program and program verification operations, said\nsequential program using a program voltage that is sequen-\ntially increased within a predetermined voltage range and\nthen maintained at a constant voltage level when program-\nming a selected memory cell that is not successfully pro-\n. The method according to claim 9, wherein said\nconstant voltage level is set to prevent junction break down\nand break down of a gate oxide layer of memory cells.\n. The method according to claim 9, wherein said\n~ predetermined voltage range is from about 15 V to 19.5 V.\n. The auto-program voltage generator according to\nclaim 1, where said sequentially increasing program voltage\nincreases in increments that are each less than 1 volL\n. The auto-program voltage generator according to\n~ claim 1, wherein said sequentially Increasing program volt-\nage increases in increments that are each less than 0.5 volts.\n. The method according to claim 9, where said sequen-\ntially increasing program voltage increases in increments\nthat are each less than 1 volt.\n~ 15. The method according to daim 9, wherein said\nsequentially Increasing program voltage increases In incre-\nments that are each less than 0.5 volts.\n. The method according to claim U, where said sequen-\ntially increasing program voltage increases in increments\n~ that are each less than 1 volt.\n. The method according to claim U, wherein said\nsequentially increasing program voltage increases in incre-\nments that are each less ihan 0.5 volts.\n. The auto-program voltage generator according to\n~ claim 1, wherein said ~ory cells are programmed in one\nof two states and said sequentially increasing program\nvoltage is used to change each selected memtry cell from\none of said states to another of said states.\n. The method according to claim 9, wherein said\nmemory cells are programmed in one of two states and said\nsequentially increasing program voltage is used to change\neach selected m~iiwiy ccli from one of said dates to another\nof said\n,642,309\n\n* * * * *\n\n"
        }
      ], 
      "filed_on": "2002-04-03T00:00:00", 
      "id": 13947, 
      "nice_text": "First Amended complaint by Samsung Electronics , amending [1-1] complaint (djh) (Entered: 04/03/2002)", 
      "number": 20, 
      "tags": [
        {
          "@id": "http://lexmachina.com/vocab/tags#14", 
          "id": 14, 
          "name": "Complaint/Counterclaim", 
          "visible": 1
        }, 
        {
          "@id": "http://lexmachina.com/vocab/tags#74", 
          "id": 74, 
          "name": "Pleading", 
          "visible": 1
        }
      ]
    }, 
    {
      "@id": "http://lexmachina.com/data/docket-entry/13948", 
      "documents": [], 
      "filed_on": "2002-04-03T00:00:00", 
      "id": 13948, 
      "nice_text": "ORDER setting scheduling conference for 4/15/02 at 3:00 in Tyler, Texas scheduling conference for 3:00 4/15/02 before Judge John Hannah Jr (signed by Judge John Hannah Jr) cc; attys, JH 4/3/02 (djh) (Entered: 04/03/2002)", 
      "number": 21, 
      "tags": [
        {
          "@id": "http://lexmachina.com/vocab/tags#2", 
          "id": 2, 
          "name": "Order", 
          "visible": 1
        }
      ]
    }, 
    {
      "@id": "http://lexmachina.com/data/docket-entry/13950", 
      "documents": [], 
      "filed_on": "2002-04-03T00:00:00", 
      "id": 13950, 
      "nice_text": "PHV Filing Fee paid by atty Michael Ladra; PHV FILING FEE $ 25.00 RECEIPT # 61780 (djh) (Entered: 04/08/2002)", 
      "number": null, 
      "tags": []
    }, 
    {
      "@id": "http://lexmachina.com/data/docket-entry/13952", 
      "documents": [], 
      "filed_on": "2002-04-09T00:00:00", 
      "id": 13952, 
      "nice_text": "MOTION by Sandisk Corporation to transfer venue (NOTE: the Motion to Transfer and Exhibit 13 to the Declaration of James C. Yoon ARE SEALED. The remainder of the document is UNSEALED pursuant to #30 Order unsealing same) (kjr) (Entered: 04/19/2002)", 
      "number": 25, 
      "tags": []
    }, 
    {
      "@id": "http://lexmachina.com/data/docket-entry/13953", 
      "documents": [], 
      "filed_on": "2002-04-10T00:00:00", 
      "id": 13953, 
      "nice_text": "Request for Hearing on Motion to Transfer Venue by Sandisk Corporation (fnt) (Entered: 04/10/2002)", 
      "number": 23, 
      "tags": []
    }, 
    {
      "@id": "http://lexmachina.com/data/docket-entry/13954", 
      "documents": [], 
      "filed_on": "2002-04-11T00:00:00", 
      "id": 13954, 
      "nice_text": "ORDER sealing SanDisk's Motion to Transfer Venue and all accompanying documents ( signed by Judge John Hannah Jr. ) cc JH, parties 4/11/02 (kjr) (Entered: 04/11/2002)", 
      "number": 26, 
      "tags": [
        {
          "@id": "http://lexmachina.com/vocab/tags#2", 
          "id": 2, 
          "name": "Order", 
          "visible": 1
        }
      ]
    }, 
    {
      "@id": "http://lexmachina.com/data/docket-entry/13955", 
      "documents": [], 
      "filed_on": "2002-04-15T00:00:00", 
      "id": 13955, 
      "nice_text": "ORDER granting [22-1] motion for Michael A. Ladra to appear pro hac vice (signed by Judge John Hannah Jr) cc; attys, JH 4/15/02 (djh) (Entered: 04/15/2002)", 
      "number": 27, 
      "tags": [
        {
          "@id": "http://lexmachina.com/vocab/tags#2", 
          "id": 2, 
          "name": "Order", 
          "visible": 1
        }
      ]
    }, 
    {
      "@id": "http://lexmachina.com/data/docket-entry/13957", 
      "documents": [], 
      "filed_on": "2002-04-15T00:00:00", 
      "id": 13957, 
      "nice_text": "Minutes Re: [0-0] Scheduling conference by Judge John Hannah Jr. on 4/15/02 (Ct rep/ECRO: Ron Mason) (pad) (Entered: 04/15/2002)", 
      "number": 28, 
      "tags": []
    }, 
    {
      "@id": "http://lexmachina.com/data/docket-entry/13958", 
      "documents": [], 
      "filed_on": "2002-04-18T00:00:00", 
      "id": 13958, 
      "nice_text": "Scheduling order setting following deadlines: Discovery shall begin as of 4/15/02 and disclosure shall be due within 30 days of that date. No deposition shall last longer than 6 hrs, except that depositions of experts and/or inventors may take up to 12 hrs. No more than 10 people per side may be deposed without further orders from the Court. Parties will submit an agreed master expert list by 4/19/02. The parties will have until 4/19/02 to brief the Court on the issue of the protective order ( signed by Judge John Hannah Jr. ) cc JH, parties 4/18/02 (kjr) (Entered: 04/18/2002)", 
      "number": 29, 
      "tags": [
        {
          "@id": "http://lexmachina.com/vocab/tags#2", 
          "id": 2, 
          "name": "Order", 
          "visible": 1
        }
      ]
    }, 
    {
      "@id": "http://lexmachina.com/data/docket-entry/13959", 
      "documents": [
        {
          "@id": "http://lexmachina.com/data/documents/4000096377", 
          "id": 4000096377, 
          "text": "IN THE UNITED STATES DISTRICT COU1{T -\nFOR THE EASTERN DISTRICT OF TEXAS\nLUFKIN DIVISION ,\n\nSAMSUNG ELECTRONICS \ufffd\nCO.,LTD., \ufffd 0':\n\ufffd\nPlaintiff, \ufffd\n\ufffd\nv. \ufffd No. 9:02-cv-58\n\ufffd\nSANDISK CORPORATION, \ufffd\n\ufffd\nDefendant. \ufffd\nAMENDED SEALING ORDER\n\nThe Court amends it April 11, 2002 Order Sealing SanDisk's Motion to\n\nTransfer Venue and Supporting Declarations and Exhibits as follows:\n. SanDisk's Motion to Transfer Venue, filed April 9, 2002, shall remain\n\nUNDER SEAL.\n. Exhibit 13 to the Declaration of James C. Yoon, filed April 9, 2002, shall\n\nremain UNDER SEAL.\n. All other filings by SanDisk made on April 9, 2002, are to be placed in the\n\npublic record and are NO LONGER SEALED.\n. All parties and counsel, except in-house counsel until further ruling from\n\nthis Court, are permitted access to SanDisk's Motion to Transfer and to Exhibit 13\n\nto the Declaration of James C. Yoon, filed April 9, 2002.\n\nIt is SO ORDERED.\n\nSIGNED this ~ r~tL~1~y of cI\ufffd=.\ufffdThA...9~ 2002.\n\n\nU ted States District Judge\n\n"
        }
      ], 
      "filed_on": "2002-04-18T00:00:00", 
      "id": 13959, 
      "nice_text": "AMENDED SEALING ORDER (1) SanDisk's motion to transfer venue filed 4/9/02 shall remain UNDER SEAL; (2) Exhibit 13 to the Declaration of James C. Yoon, filed 4/9/02, shall remain UNDER SEAL; (3) all other filings by SanDisk made on 4/9/02 are to be placed in the public record and are NO LONGER SEALED; (4) all parties & counsel, except in-house counsel, until further ruling from the court, are permitted access to SanDick's motion to transfer venue and to Exhibit 13 to the Declaration of James C. Yoon, filed 4/9/02 cc JH, parties 4/18/02 ( signed by Judge John Hannah Jr. ) (kjr) (Entered: 04/18/2002)", 
      "number": 30, 
      "tags": [
        {
          "@id": "http://lexmachina.com/vocab/tags#2", 
          "id": 2, 
          "name": "Order", 
          "visible": 1
        }, 
        {
          "@id": "http://lexmachina.com/vocab/tags#111", 
          "id": 111, 
          "name": "Order re: Transfer", 
          "visible": 1
        }
      ]
    }, 
    {
      "@id": "http://lexmachina.com/data/docket-entry/13960", 
      "documents": [], 
      "filed_on": "2002-04-18T00:00:00", 
      "id": 13960, 
      "nice_text": "Unsealed #24 Motion to Seal and appropriate portions of #25 Motion to Transfer (per court order) (kjr) (Entered: 04/19/2002)", 
      "number": null, 
      "tags": []
    }, 
    {
      "@id": "http://lexmachina.com/data/docket-entry/13961", 
      "documents": [], 
      "filed_on": "2002-04-19T00:00:00", 
      "id": 13961, 
      "nice_text": "UNOPPOSED MOTION by Sandisk Corporation to extend time for filing and agreed master expert list (djh) (Entered: 04/22/2002)", 
      "number": 31, 
      "tags": []
    }, 
    {
      "@id": "http://lexmachina.com/data/docket-entry/13962", 
      "documents": [], 
      "filed_on": "2002-04-19T00:00:00", 
      "id": 13962, 
      "nice_text": "UNOPPOSED MOTION by Sandisk Corporation to extend time for filing and agreed master expert list (djh) (Entered: 04/23/2002)", 
      "number": 33, 
      "tags": []
    }, 
    {
      "@id": "http://lexmachina.com/data/docket-entry/13963", 
      "documents": [], 
      "filed_on": "2002-04-22T00:00:00", 
      "id": 13963, 
      "nice_text": "ORDER granting [31-1] motion to extend time for filing and agreed master expert list. The Dft shall have an additional 5 business days i which to file an agreed master expert list. Said list shall be due on or before 4/26/02` notice of compliance due for 4/26/02 for Sandisk Corporation (signed by Judge John Hannah Jr) cc; attys, JH 4/22/02 (djh) (Entered: 04/22/2002)", 
      "number": 32, 
      "tags": [
        {
          "@id": "http://lexmachina.com/vocab/tags#2", 
          "id": 2, 
          "name": "Order", 
          "visible": 1
        }
      ]
    }, 
    {
      "@id": "http://lexmachina.com/data/docket-entry/13964", 
      "documents": [], 
      "filed_on": "2002-04-24T00:00:00", 
      "id": 13964, 
      "nice_text": "Letter Brief filed by Sandisk Corporation re protective order (kjr) (Entered: 04/24/2002)", 
      "number": 34, 
      "tags": []
    }, 
    {
      "@id": "http://lexmachina.com/data/docket-entry/13965", 
      "documents": [], 
      "filed_on": "2002-04-24T00:00:00", 
      "id": 13965, 
      "nice_text": "Scheduling order setting length and manner of taking depositions, interrogatories, document production & technology tutorial and setting following deadlines: discovery commences - 4/15/02; initial disclosures - 5/15/02; technology & patent tutorial at 9:00 am 6/17/02 in Tyler; expert reports - 7/15/02; rebuttal expert reports - 8/1/02; fact & expert discovery closes - 8/19/02; venue hearing at 9:00 am 8/26/02 in Tyler; filing dispositive motions - 8/30/02; joint pretrial order - 9/30/02; trial at 9:00 am 10/21/02 in Tyler ( signed by Judge John Hannah Jr. ) cc JH, parties 4/24/02 (kjr) (Entered: 04/24/2002)", 
      "number": 35, 
      "tags": [
        {
          "@id": "http://lexmachina.com/vocab/tags#2", 
          "id": 2, 
          "name": "Order", 
          "visible": 1
        }
      ]
    }, 
    {
      "@id": "http://lexmachina.com/data/docket-entry/13966", 
      "documents": [], 
      "filed_on": "2002-04-24T00:00:00", 
      "id": 13966, 
      "nice_text": "MOTION by Samsung Electronics to seal response to Sandisk's motion to transfer venue (kjr) (Entered: 04/24/2002)", 
      "number": 36, 
      "tags": []
    }, 
    {
      "@id": "http://lexmachina.com/data/docket-entry/13967", 
      "documents": [], 
      "filed_on": "2002-04-24T00:00:00", 
      "id": 13967, 
      "nice_text": "Affidavit by Samsung Electronics Re: [37-1] response to motion to transfer venue (kjr) (Entered: 04/24/2002)", 
      "number": 38, 
      "tags": []
    }, 
    {
      "@id": "http://lexmachina.com/data/docket-entry/13968", 
      "documents": [], 
      "filed_on": "2002-04-24T00:00:00", 
      "id": 13968, 
      "nice_text": "(WITNDRAWN) MOTION by Samsung Electronics to dismiss Sandisk Corporation's Fifth Counterclaim (kjr) Modified on 05/20/2002 (Entered: 04/24/2002)", 
      "number": 39, 
      "tags": []
    }, 
    {
      "@id": "http://lexmachina.com/data/docket-entry/13969", 
      "documents": [], 
      "filed_on": "2002-04-24T00:00:00", 
      "id": 13969, 
      "nice_text": "(UNOPPOSED) MOTION by Sandisk Corporation to reseal specified records and modify the court's amended seal order (fnt) (Entered: 04/24/2002)", 
      "number": 40, 
      "tags": []
    }, 
    {
      "@id": "http://lexmachina.com/data/docket-entry/2002343034", 
      "documents": [], 
      "filed_on": "2002-04-26T00:00:00", 
      "id": 2002343034, 
      "nice_text": "Notice to court of SanDisk submission of individuals for consideration as Special Master (fnt) (Entered: 04/29/2002)", 
      "number": null, 
      "tags": []
    }, 
    {
      "@id": "http://lexmachina.com/data/docket-entry/13973", 
      "documents": [], 
      "filed_on": "2002-04-30T00:00:00", 
      "id": 13973, 
      "nice_text": "ORDER granting [36-1] motion to seal response to Sandisk's motion to transfer venue (signed by Judge John Hannah Jr) cc; attys, JH 4/30/02 (djh) (Entered: 04/30/2002)", 
      "number": 42, 
      "tags": [
        {
          "@id": "http://lexmachina.com/vocab/tags#2", 
          "id": 2, 
          "name": "Order", 
          "visible": 1
        }
      ]
    }, 
    {
      "@id": "http://lexmachina.com/data/docket-entry/13974", 
      "documents": [], 
      "filed_on": "2002-04-30T00:00:00", 
      "id": 13974, 
      "nice_text": "ORDER granting [24-1] motion to seal SanDisk's Motion to Transfer Venue and accompanying declarations as follows: SanDisk's Motion to Transfer Venue Filed on 4/19/02 shall remain under seal; Exhibit 13 to the Declaration of James C. Yoon Filed 4/9/02 shall remain under seal; Paragraphs 4,6,7 and 8 of the Declaration of Michael Gray shall remain under seal; Paragraphs 5,6,7 and 9 of the Declaration of Kevin Conley shall remain under seal; and all parties and counsel including Samsung in house counsel, are permitted access to SanDisk's Motion to Transfer and to Exhibit 13 to the Declaration of James C. Yoon (signed by Judge John Hannah Jr) cc; attys, JH 4/30/02 (djh) (Entered: 04/30/2002)", 
      "number": 43, 
      "tags": [
        {
          "@id": "http://lexmachina.com/vocab/tags#2", 
          "id": 2, 
          "name": "Order", 
          "visible": 1
        }, 
        {
          "@id": "http://lexmachina.com/vocab/tags#111", 
          "id": 111, 
          "name": "Order re: Transfer", 
          "visible": 1
        }
      ]
    }, 
    {
      "@id": "http://lexmachina.com/data/docket-entry/13975", 
      "documents": [], 
      "filed_on": "2002-04-30T00:00:00", 
      "id": 13975, 
      "nice_text": "PROTECTIVE ORDER regarding confidential information (signed by Judge John Hannah Jr) cc: attys, JH 4/30/02 (djh) (Entered: 04/30/2002)", 
      "number": 44, 
      "tags": [
        {
          "@id": "http://lexmachina.com/vocab/tags#2", 
          "id": 2, 
          "name": "Order", 
          "visible": 1
        }
      ]
    }, 
    {
      "@id": "http://lexmachina.com/data/docket-entry/13976", 
      "documents": [], 
      "filed_on": "2002-04-30T00:00:00", 
      "id": 13976, 
      "nice_text": "MOTION by Samsung Electronics for leave to file response to dft's motion to transfer venue to the Northern District of California pursuant to 28 U S C 1404 (a) (djh) (Entered: 04/30/2002)", 
      "number": 45, 
      "tags": []
    }, 
    {
      "@id": "http://lexmachina.com/data/docket-entry/13977", 
      "documents": [], 
      "filed_on": "2002-05-01T00:00:00", 
      "id": 13977, 
      "nice_text": "Transcript of Scheduling Conference filed . Court Reporter: Ron Mason ( 51 pages) (djh) (Entered: 05/01/2002)", 
      "number": 46, 
      "tags": []
    }, 
    {
      "@id": "http://lexmachina.com/data/docket-entry/13978", 
      "documents": [], 
      "filed_on": "2002-05-02T00:00:00", 
      "id": 13978, 
      "nice_text": "(UNOPPOSED) MOTION by Sandisk Corporation to extend time to reply to pla Samsung's response to dft Sandisk's Motion to Transfer Venue to the Northern Dist of CA (fnt) (Entered: 05/02/2002)", 
      "number": 47, 
      "tags": []
    }, 
    {
      "@id": "http://lexmachina.com/data/docket-entry/13979", 
      "documents": [], 
      "filed_on": "2002-05-06T00:00:00", 
      "id": 13979, 
      "nice_text": "ORDER granting [45-1] motion for leave to file response to dft's motion to transfer venue to the Northern District of California pursuant to 28 U S C 1404 (a) ( signed by Judge John Hannah Jr) cc: attys, JH 5/6/02 (djh) (Entered: 05/06/2002)", 
      "number": 48, 
      "tags": [
        {
          "@id": "http://lexmachina.com/vocab/tags#2", 
          "id": 2, 
          "name": "Order", 
          "visible": 1
        }
      ]
    }, 
    {
      "@id": "http://lexmachina.com/data/docket-entry/13980", 
      "documents": [], 
      "filed_on": "2002-05-06T00:00:00", 
      "id": 13980, 
      "nice_text": "ORDER granting [47-1] motion to extend time to reply to pla Samsung's response to dft Sandisk's Motion to Transfer Venue to the Northern Dist of CA, set notice of compliance due for 5/10/02 for Sandisk Corporation ( signed by Judge John Hannah Jr) cc; attys, JH 5/6/02 (djh) (Entered: 05/06/2002)", 
      "number": 49, 
      "tags": [
        {
          "@id": "http://lexmachina.com/vocab/tags#2", 
          "id": 2, 
          "name": "Order", 
          "visible": 1
        }
      ]
    }, 
    {
      "@id": "http://lexmachina.com/data/docket-entry/13981", 
      "documents": [], 
      "filed_on": "2002-05-07T00:00:00", 
      "id": 13981, 
      "nice_text": "MOTION by Samsung Electronics to withdraw [39-1] motion to dismiss Sandisk Corporation's Fifth Counterclaim (djh) (Entered: 05/07/2002)", 
      "number": 50, 
      "tags": []
    }, 
    {
      "@id": "http://lexmachina.com/data/docket-entry/13982", 
      "documents": [], 
      "filed_on": "2002-05-10T00:00:00", 
      "id": 13982, 
      "nice_text": "MOTION by Sandisk Corporation to seal reply to pla's response to dft's motion to transfer enue to the NDTX and exhibits (fnt) (Entered: 05/10/2002)", 
      "number": 51, 
      "tags": []
    }, 
    {
      "@id": "http://lexmachina.com/data/docket-entry/13983", 
      "documents": [], 
      "filed_on": "2002-05-10T00:00:00", 
      "id": 13983, 
      "nice_text": "MOTION by Sandisk Corporation to exceed page limitation Reply to Pla's response to dft Motion to Transfer Venue to the Northern Dist of CA (fnt) (Entered: 05/10/2002)", 
      "number": 52, 
      "tags": []
    }, 
    {
      "@id": "http://lexmachina.com/data/docket-entry/13984", 
      "documents": [], 
      "filed_on": "2002-05-14T00:00:00", 
      "id": 13984, 
      "nice_text": "MOTION by Sandisk Corporation to shorten the time period for Samsung's response to Sandisk Corp's Motion for Reconsideration of scheduling order (fnt) (Entered: 05/15/2002)", 
      "number": 56, 
      "tags": []
    }, 
    {
      "@id": "http://lexmachina.com/data/docket-entry/13985", 
      "documents": [], 
      "filed_on": "2002-05-14T00:00:00", 
      "id": 13985, 
      "nice_text": "Request for Oral Argument by Sandisk Corporation (fnt) (Entered: 05/15/2002)", 
      "number": 57, 
      "tags": []
    }, 
    {
      "@id": "http://lexmachina.com/data/docket-entry/13986", 
      "documents": [], 
      "filed_on": "2002-05-15T00:00:00", 
      "id": 13986, 
      "nice_text": "MOTION by Sandisk Corporation for reconsideration of [35-1] Scheduling order , for modification of discovery period and deadlines (djh) (Entered: 05/15/2002)", 
      "number": 53, 
      "tags": []
    }, 
    {
      "@id": "http://lexmachina.com/data/docket-entry/13987", 
      "documents": [
        {
          "@id": "http://lexmachina.com/data/documents/4000107451", 
          "id": 4000107451, 
          "text": "FILED - CLERK\nU.S. DtSTf~;~ COURT\nB7 ~Y 15 AM Ii: 16\nTX EASTERN - I ~1N\n\n~` IN THE UNITED STATES DISTRICT COURT\n`3 EASTERN DISTRICT OF TEXAS\nLUFKIN DIVISION\n\nSAMSUNG ELECTRONICS CO., LTD. \ufffd\n\ufffd\nVS. \ufffd CIVIL ACTION NO. 9:02CV58\n\ufffd JUDGE HANNAH\nSANDISK CORPORATION \ufffd\n\nORDER\n\nOn this day came onto be considered Plaintiffis Motion to Withdraw Samsung's Motion to\n\nDismiss SanDisk's Fifth Counter Claim and the Court finds that it is unopposed and should be\n\nGranted.\n\nIt is, therefore, ORDERED that Samsung Electronics Co., Ltd., Plaintiff is permitted to\n\nwithdraw it's Motion to Dismiss SanDisk Corporation's Fifth Counter Claim without prejudice to\n\nPlaintiff's refihing of same.\n\nSIGNED this day of May, 2002.\n\n\n~\n\n\n"
        }
      ], 
      "filed_on": "2002-05-15T00:00:00", 
      "id": 13987, 
      "nice_text": "ORDER granting [50-1] motion to withdraw [39-1] motion to dismiss Sandisk Corporation's Fifth Counterclaim without prejudice to pla's refiling of same (signed by Judge John Hannah Jr) cc: attys, JH 5/15/02 (djh) Modified on 05/15/2002 (Entered: 05/15/2002)", 
      "number": 54, 
      "tags": [
        {
          "@id": "http://lexmachina.com/vocab/tags#2", 
          "id": 2, 
          "name": "Order", 
          "visible": 1
        }, 
        {
          "@id": "http://lexmachina.com/vocab/tags#104", 
          "id": 104, 
          "name": "Order re: Dismissal", 
          "visible": 1
        }
      ]
    }, 
    {
      "@id": "http://lexmachina.com/data/docket-entry/13988", 
      "documents": [], 
      "filed_on": "2002-05-15T00:00:00", 
      "id": 13988, 
      "nice_text": "ORDER granting [52-1] motion to exceed page limitation Reply to Pla's response to dft Motion to Transfer Venue to the Northern Dist of CA. Dft shall have 5 additional pages to respond to pla's Samsung's response to dft Sandisk's motion transfer to transfer venue to the Northern District of CA. Dft Sandisk's reply will now be no more than 10 pages in length excluding exhibits (signed by Judge John Hannah Jr) cc: attys, JH 5/15/02 (djh) Modified on 05/15/2002 (Entered: 05/15/2002)", 
      "number": 55, 
      "tags": [
        {
          "@id": "http://lexmachina.com/vocab/tags#2", 
          "id": 2, 
          "name": "Order", 
          "visible": 1
        }
      ]
    }, 
    {
      "@id": "http://lexmachina.com/data/docket-entry/13989", 
      "documents": [], 
      "filed_on": "2002-05-15T00:00:00", 
      "id": 13989, 
      "nice_text": "ORDER granting [51-1] motion to seal reply to pla's response to dft's motion to transfer enue to the NDTX and exhibits ( signed by Judge John Hannah Jr) cc; attys, JH 5/15/02 (djh) (Entered: 05/15/2002)", 
      "number": 58, 
      "tags": [
        {
          "@id": "http://lexmachina.com/vocab/tags#2", 
          "id": 2, 
          "name": "Order", 
          "visible": 1
        }
      ]
    }, 
    {
      "@id": "http://lexmachina.com/data/docket-entry/13990", 
      "documents": [], 
      "filed_on": "2002-05-15T00:00:00", 
      "id": 13990, 
      "nice_text": "Notice of initial disclosure by Samsung Electronics (djh) (Entered: 05/16/2002)", 
      "number": 60, 
      "tags": []
    }, 
    {
      "@id": "http://lexmachina.com/data/docket-entry/13992", 
      "documents": [], 
      "filed_on": "2002-05-16T00:00:00", 
      "id": 13992, 
      "nice_text": "MOTION by Samsung Electronics for more definite statement of Sandisk Corporations' Amended Counterclaims and Affirmative Defenses (kjr) (Entered: 05/17/2002)", 
      "number": 62, 
      "tags": []
    }, 
    {
      "@id": "http://lexmachina.com/data/docket-entry/13993", 
      "documents": [], 
      "filed_on": "2002-05-22T00:00:00", 
      "id": 13993, 
      "nice_text": "(Supplemental) Brief in support of dft's Motion for Recondiseration of the Court's 4/24/02 scheduling order and for modification of discovery period and deadlines filed by Sandisk Corporation (fnt) (Entered: 05/23/2002)", 
      "number": 63, 
      "tags": []
    }, 
    {
      "@id": "http://lexmachina.com/data/docket-entry/13994", 
      "documents": [], 
      "filed_on": "2002-05-23T00:00:00", 
      "id": 13994, 
      "nice_text": "Notice of attorney appearance for Sandisk Corporation by Samuel Franklin Baxter, Peter John Ayers (kjr) (Entered: 05/23/2002)", 
      "number": 64, 
      "tags": []
    }, 
    {
      "@id": "http://lexmachina.com/data/docket-entry/13995", 
      "documents": [], 
      "filed_on": "2002-05-28T00:00:00", 
      "id": 13995, 
      "nice_text": "MOTION by Samsung Electronics to exceed page limitation Response to Sandisk Corp motion for reconsideration of the court's 4/24/02 scheduling order and for modification of the discovery period deadlines (djh) (Entered: 05/29/2002)", 
      "number": 65, 
      "tags": []
    }, 
    {
      "@id": "http://lexmachina.com/data/docket-entry/13996", 
      "documents": [], 
      "filed_on": "2002-05-28T00:00:00", 
      "id": 13996, 
      "nice_text": "MOTION by Samsung Electronics to voluntarily dismiss Count 4 of pla's 1st amd cmp (djh) (Entered: 05/29/2002)", 
      "number": 66, 
      "tags": []
    }, 
    {
      "@id": "http://lexmachina.com/data/docket-entry/13997", 
      "documents": [], 
      "filed_on": "2002-05-31T00:00:00", 
      "id": 13997, 
      "nice_text": "Response (in opposition) by Sandisk Corporation to [62-1] motion for more definite statement of Sandisk Corporations' Amended Counterclaims and Affirmative Defenses (fnt) (Entered: 06/04/2002)", 
      "number": 69, 
      "tags": []
    }, 
    {
      "@id": "http://lexmachina.com/data/docket-entry/13998", 
      "documents": [], 
      "filed_on": "2002-06-03T00:00:00", 
      "id": 13998, 
      "nice_text": "ORDER granting [65-1] motion to exceed page limitation Response to Sandisk Corp motion for reconsideration of the court's 4/24/02 scheduling order and for modification of the discovery period deadlines ( signed by Judge John Hannah Jr. ) cc JH, parties 6/3/02 (kjr) (Entered: 06/03/2002)", 
      "number": 67, 
      "tags": [
        {
          "@id": "http://lexmachina.com/vocab/tags#2", 
          "id": 2, 
          "name": "Order", 
          "visible": 1
        }
      ]
    }, 
    {
      "@id": "http://lexmachina.com/data/docket-entry/13999", 
      "documents": [], 
      "filed_on": "2002-06-03T00:00:00", 
      "id": 13999, 
      "nice_text": "Response by Samsung Electronics to [53-1] motion for reconsideration of [35-1] Scheduling order (kjr) (Entered: 06/03/2002)", 
      "number": 68, 
      "tags": []
    }, 
    {
      "@id": "http://lexmachina.com/data/docket-entry/14000", 
      "documents": [], 
      "filed_on": "2002-06-04T00:00:00", 
      "id": 14000, 
      "nice_text": "ORDER appointing Gale R. Peterson as technical advisor. Mr. Peterson shall keep track of his time and submit a monthly statement to the court showing the hours expended. The parties are each directed to pay one-half, at a total rate of $475 per hour for time spent reviewing materials at the court's request as well as providing direct consultation to the court. The court taxes such costs to the parties pursuant to its inherent power to do so. Mr. Peterson will execute an affidavit indicating his understanding of this order prior to beginning his engagement. ( signed by Judge John Hannah Jr. ) cc JH, parties 6/4/02 (kjr) (Entered: 06/04/2002)", 
      "number": 70, 
      "tags": [
        {
          "@id": "http://lexmachina.com/vocab/tags#2", 
          "id": 2, 
          "name": "Order", 
          "visible": 1
        }
      ]
    }, 
    {
      "@id": "http://lexmachina.com/data/docket-entry/14001", 
      "documents": [], 
      "filed_on": "2002-06-04T00:00:00", 
      "id": 14001, 
      "nice_text": "ORDER sua sponte continuing the tutorial scheduled for Monday, 6/17/02 at 9:00 am in Tyler Texas to Thursday, 7/11/02 at 9:00 am in Tyler Texas. ( signed by Judge John Hannah Jr. ) cc JH, parties 6/4/02 (kjr) (Entered: 06/04/2002)", 
      "number": 71, 
      "tags": [
        {
          "@id": "http://lexmachina.com/vocab/tags#2", 
          "id": 2, 
          "name": "Order", 
          "visible": 1
        }
      ]
    }, 
    {
      "@id": "http://lexmachina.com/data/docket-entry/14002", 
      "documents": [], 
      "filed_on": "2002-06-04T00:00:00", 
      "id": 14002, 
      "nice_text": "Fax noticing receipt of #70 Order appointing technical advisor to attorney George Edmond Chandler for Samsung Electronics 6/4/02 15:41. (kjr) (Entered: 06/04/2002)", 
      "number": 72, 
      "tags": []
    }, 
    {
      "@id": "http://lexmachina.com/data/docket-entry/14003", 
      "documents": [], 
      "filed_on": "2002-06-04T00:00:00", 
      "id": 14003, 
      "nice_text": "Fax noticing receipt of #70 Order appointing technical expert to attorney Herschel Tracy Crawford for Sandisk Corporation 6/4/02 15:46. (kjr) (Entered: 06/05/2002)", 
      "number": 73, 
      "tags": []
    }, 
    {
      "@id": "http://lexmachina.com/data/docket-entry/14004", 
      "documents": [], 
      "filed_on": "2002-06-04T00:00:00", 
      "id": 14004, 
      "nice_text": "MOTION by Sandisk Corporation to exceed page limitation Reply to Pla's Response to dft's Motion for Reconsideration of the Court's 4/24/02 scheduling order and for modification of the discovery period and deadlines (fnt) (Entered: 06/05/2002)", 
      "number": 75, 
      "tags": []
    }, 
    {
      "@id": "http://lexmachina.com/data/docket-entry/14006", 
      "documents": [], 
      "filed_on": "2002-06-07T00:00:00", 
      "id": 14006, 
      "nice_text": "MOTION by Samsung Electronics for leave to file exhibits in support of its memorandum in response to Sandisk Corp's mo for reconsideration of the Court's 4/24/02 scheduling order and for modification of the discovery period and deadlines (djh) (Entered: 06/07/2002)", 
      "number": 76, 
      "tags": []
    }, 
    {
      "@id": "http://lexmachina.com/data/docket-entry/14008", 
      "documents": [], 
      "filed_on": "2002-06-10T00:00:00", 
      "id": 14008, 
      "nice_text": "Response by Samsung Electronics to [62-1] motion for more definite statement of Sandisk Corporations' Amended Counterclaims and Affirmative Defenses (djh) (Entered: 06/11/2002)", 
      "number": 77, 
      "tags": []
    }, 
    {
      "@id": "http://lexmachina.com/data/docket-entry/2002343035", 
      "documents": [], 
      "filed_on": "2002-06-10T00:00:00", 
      "id": 2002343035, 
      "nice_text": "Acknowledgement from Gale Peterson ofc of receiving a copy of the file (djh) (Entered: 06/10/2002)", 
      "number": null, 
      "tags": []
    }, 
    {
      "@id": "http://lexmachina.com/data/docket-entry/14009", 
      "documents": [], 
      "filed_on": "2002-06-10T00:00:00", 
      "id": 14009, 
      "nice_text": "(UNOPPOSED) MOTION by Sandisk Corporation for hearing (fnt) (Entered: 06/11/2002)", 
      "number": 78, 
      "tags": []
    }, 
    {
      "@id": "http://lexmachina.com/data/docket-entry/14010", 
      "documents": [], 
      "filed_on": "2002-06-10T00:00:00", 
      "id": 14010, 
      "nice_text": "Motion by Sandisk Corporation with memorandum in support to disqualify Weil, Gotshal & Manges, LLP (fnt) (Entered: 06/11/2002)", 
      "number": 79, 
      "tags": []
    }, 
    {
      "@id": "http://lexmachina.com/data/docket-entry/14011", 
      "documents": [], 
      "filed_on": "2002-06-11T00:00:00", 
      "id": 14011, 
      "nice_text": "Sur-Reply by Samsung Electronics to Sandisk's reply brief in support of Sandisk's [53-1] motion for reconsideration of [35-1] Scheduling order (djh) (Entered: 06/12/2002)", 
      "number": 80, 
      "tags": []
    }, 
    {
      "@id": "http://lexmachina.com/data/docket-entry/14012", 
      "documents": [], 
      "filed_on": "2002-06-12T00:00:00", 
      "id": 14012, 
      "nice_text": "ORDER granting [75-1] motion to exceed page limitation Reply to Pla's Response to dft's Motion for Reconsideration of the Court's 4/24/02 scheduling order and for modification of the discovery period and deadlines. SanDisk may file a reply in exces of 5 pages in length in pla's response to dft SanDisk's motion for reconsideration of the Court's 4/24/02 scheduling order and for modification of the discovery period and deadlines (signed by Judge John Hannah Jr) cc; attys, JH 6/12/02 (djh) (Entered: 06/12/2002)", 
      "number": 81, 
      "tags": [
        {
          "@id": "http://lexmachina.com/vocab/tags#2", 
          "id": 2, 
          "name": "Order", 
          "visible": 1
        }
      ]
    }, 
    {
      "@id": "http://lexmachina.com/data/docket-entry/14013", 
      "documents": [], 
      "filed_on": "2002-06-12T00:00:00", 
      "id": 14013, 
      "nice_text": "Reply brief by Sandisk Corporation to [53-1] SanDisk's motion for reconsideration of [35-1] Scheduling order (djh) (Entered: 06/12/2002)", 
      "number": 82, 
      "tags": []
    }, 
    {
      "@id": "http://lexmachina.com/data/docket-entry/14014", 
      "documents": [], 
      "filed_on": "2002-06-12T00:00:00", 
      "id": 14014, 
      "nice_text": "ORDER mooting [56-1] motion to shorten the time period for Samsung's response to Sandisk Corp's Motion for Reconsideration of scheduling order. On June 3, 2002 the district clerk's office received and entered Samsung's response (#68) (signed by Judge John Hannah Jr) cc; attys, JH 6/12/02 (djh) (Entered: 06/12/2002)", 
      "number": 83, 
      "tags": [
        {
          "@id": "http://lexmachina.com/vocab/tags#2", 
          "id": 2, 
          "name": "Order", 
          "visible": 1
        }
      ]
    }, 
    {
      "@id": "http://lexmachina.com/data/docket-entry/14015", 
      "documents": [], 
      "filed_on": "2002-06-12T00:00:00", 
      "id": 14015, 
      "nice_text": "ORDER granting [76-1] motion for leave to file exhibits in support of its memorandum in response to Sandisk Corp's mo for reconsideration of the Court's 4/24/02 scheduling order and for modification of the discovery period and deadlines ( signed by Judge John Hannah Jr) cc; attys, JH 6/12/02 (djh) (Entered: 06/12/2002)", 
      "number": 84, 
      "tags": [
        {
          "@id": "http://lexmachina.com/vocab/tags#2", 
          "id": 2, 
          "name": "Order", 
          "visible": 1
        }
      ]
    }, 
    {
      "@id": "http://lexmachina.com/data/docket-entry/14016", 
      "documents": [], 
      "filed_on": "2002-06-12T00:00:00", 
      "id": 14016, 
      "nice_text": "Exhibits by Samsung Electronics memorandum in response to Sandisk Corp's motion for reconsideration of the court's 4/24/02 scheduling order and for modification of the discovery period and deadlines filed 5/28/02 document number 68 (djh) (Entered: 06/12/2002)", 
      "number": 85, 
      "tags": []
    }, 
    {
      "@id": "http://lexmachina.com/data/docket-entry/14017", 
      "documents": [], 
      "filed_on": "2002-06-12T00:00:00", 
      "id": 14017, 
      "nice_text": "Notice response to the appointment of Mr. Peterson as Special Master by Sandisk Corporation (fnt) (Entered: 06/13/2002)", 
      "number": 86, 
      "tags": []
    }, 
    {
      "@id": "http://lexmachina.com/data/docket-entry/14018", 
      "documents": [], 
      "filed_on": "2002-06-13T00:00:00", 
      "id": 14018, 
      "nice_text": "Stipulation of dismissal with prejudice pursuant to FRCP 41(a)(1)(ii) of Samsung's claim of infringement of US Patent 5,642,309 and Sandisk's counterclaim of noninfringement and invaliditiy of US Patent 5,642,309 (kjr) (Entered: 06/14/2002)", 
      "number": 87, 
      "tags": []
    }, 
    {
      "@id": "http://lexmachina.com/data/docket-entry/14019", 
      "documents": [], 
      "filed_on": "2002-06-14T00:00:00", 
      "id": 14019, 
      "nice_text": "ORDER granting [78-1], [57-1] motions for hearing, Motion hearing set for 7/11/02 for [53-1] motion for reconsideration of [35-1] Scheduling order and [53-2] motion for modification of discovery period and deadlines . The hearing is set following the technology tutorial and continuing day to day if necessary. ( signed by Judge John Hannah Jr. ) cc JH, parties 6/14/02 (kjr) (Entered: 06/14/2002)", 
      "number": 88, 
      "tags": [
        {
          "@id": "http://lexmachina.com/vocab/tags#2", 
          "id": 2, 
          "name": "Order", 
          "visible": 1
        }
      ]
    }, 
    {
      "@id": "http://lexmachina.com/data/docket-entry/14020", 
      "documents": [
        {
          "@id": "http://lexmachina.com/data/documents/6", 
          "id": 6, 
          "text": "Case 9:02~cv~00058-JH Document 89 FHed 06117/2002 Page 1 of 2\n\n\n~` / IN THE UNITED STATES DISTRIC~t~J~1\nFOR THE EASTERN DISTRICT O~ITi~XAS ~.\n/V 17\nVJ LUFKIN DIVISION ?1i~l ~\n~\nSAMSUNG ELECTRONICS CO., \ufffd J\nLTD. \ufffd\nPlaintiff \ufffd\n\ufffd\nV. \ufffd\n\n\ufffd\nSANDISK CORPORATION, \ufffd\nDefendant. \ufffd\n\ufffd No. 9:02-cv-58\nSANDISK CORPORATION, \ufffd\nCounterclaimant, \ufffd\n\ufffd\nv. \ufffd\n\ufffd\nSAMSUNG ELECTRONICS CO., \ufffd\nLTD., \ufffd\nCounterdefendant. \ufffd\n\nORDER\n\nBefore the Court is the Motion for Voluntary Dismissal of Count IV of\n\nPlaintiffs First Amended Complaint (Doe. #66). Pursuant to the Parties' Stipulation\n\nin accordance with Federal Rule of Civil Procedure 41 (a)( 1 )(k) (Doe. #87), Plaintiffs\n\nclaim of infringement of U.S. Patent No. 5,642,309 against SanDisk Corporation and\n\nDefendant's counterclaim for declaratory judgment of noninfringement and/or\n\ninvalidity of U.S. Patent No. 5,642,309 are hereby DISMISSED with prejudice.\n\nAll other claims remain on file and are not affected by this Stipulation or Order.\n\nIT IS SO ORDERED.\n\nCase 9:02~cv~00058-JH Document 89 FHed 06/17/2002 Page 2 of 2\n\n\n~f~A\nSIGNED this ( ~ day of June, 2002.\n\n\nJO HANNAH, JR.\nUni ed States District Judge\n\n"
        }
      ], 
      "filed_on": "2002-06-17T00:00:00", 
      "id": 14020, 
      "nice_text": "ORDER granting [66-1] motion to voluntarily dismiss Count 4 of pla's 1st amd cmp. Pla's claim of infringement of U S Patent No. 5,642,309 agains Sandisk Corp and Dft counterclaim for declaratory judgment of noninfringement and/or invalidty of U S Patent No. 5,642,309 are hereby DISMISSED with prejudice. All other claims remain on file and are not affected by this stipulation of order (signed by Judge John Hannah Jr) cc; attys, JH 6/17/02 (djh) (Entered: 06/17/2002)", 
      "number": 89, 
      "tags": [
        {
          "@id": "http://lexmachina.com/vocab/tags#2", 
          "id": 2, 
          "name": "Order", 
          "visible": 1
        }, 
        {
          "@id": "http://lexmachina.com/vocab/tags#104", 
          "id": 104, 
          "name": "Order re: Dismissal", 
          "visible": 1
        }
      ]
    }, 
    {
      "@id": "http://lexmachina.com/data/docket-entry/14021", 
      "documents": [], 
      "filed_on": "2002-06-18T00:00:00", 
      "id": 14021, 
      "nice_text": "MOTION by Sandisk Corporation to extend time of hearing on its motion to transfer venue (fnt) (Entered: 06/19/2002)", 
      "number": 90, 
      "tags": []
    }, 
    {
      "@id": "http://lexmachina.com/data/docket-entry/14022", 
      "documents": [], 
      "filed_on": "2002-06-19T00:00:00", 
      "id": 14022, 
      "nice_text": "MOTION by Sandisk Corporation for leave to file supplemental brief and materials in support of dft Sandisk Corp motion for reconsideration of the Court's 4/24/02 scheduling order (djh) (Entered: 06/21/2002)", 
      "number": 92, 
      "tags": []
    }, 
    {
      "@id": "http://lexmachina.com/data/docket-entry/14023", 
      "documents": [], 
      "filed_on": "2002-06-20T00:00:00", 
      "id": 14023, 
      "nice_text": "MOTION by Samsung Electronics to disqualify McKool Smith PC (djh) (Entered: 06/20/2002)", 
      "number": 91, 
      "tags": []
    }, 
    {
      "@id": "http://lexmachina.com/data/docket-entry/14024", 
      "documents": [], 
      "filed_on": "2002-06-24T00:00:00", 
      "id": 14024, 
      "nice_text": "ORDER granting [92-1] motion for leave to file supplemental brief and materials in support of dft Sandisk Corp motion for reconsideration of the Court's 4/24/02 scheduling order (signed by Judge John Hannah Jr) cc; attys, JH 6/24/02 (djh) (Entered: 06/24/2002)", 
      "number": 93, 
      "tags": [
        {
          "@id": "http://lexmachina.com/vocab/tags#2", 
          "id": 2, 
          "name": "Order", 
          "visible": 1
        }
      ]
    }, 
    {
      "@id": "http://lexmachina.com/data/docket-entry/14025", 
      "documents": [], 
      "filed_on": "2002-06-24T00:00:00", 
      "id": 14025, 
      "nice_text": "Supplemental brief filed by Sandisk Corporation n support of motion for reconsideration of the Court's order 4/24/02 scheduling order (djh) (Entered: 06/24/2002)", 
      "number": 94, 
      "tags": []
    }, 
    {
      "@id": "http://lexmachina.com/data/docket-entry/14026", 
      "documents": [], 
      "filed_on": "2002-06-25T00:00:00", 
      "id": 14026, 
      "nice_text": "MOTION by Samsung Electronics to strike Sandisk Corp demand for jury trial (djh) (Entered: 06/25/2002)", 
      "number": 95, 
      "tags": []
    }, 
    {
      "@id": "http://lexmachina.com/data/docket-entry/14027", 
      "documents": [], 
      "filed_on": "2002-06-25T00:00:00", 
      "id": 14027, 
      "nice_text": "JOINT AND AGREED MOTION by Samsung Electronics, Sandisk Corporation to set aside deadlines for responsive pleadings to the pending motions to disqualify original set in [35-1] Scheduling order (djh) (Entered: 06/26/2002)", 
      "number": 96, 
      "tags": []
    }, 
    {
      "@id": "http://lexmachina.com/data/docket-entry/14029", 
      "documents": [], 
      "filed_on": "2002-06-28T00:00:00", 
      "id": 14029, 
      "nice_text": "ORDER that dft's \"discovery hotline\" request for an order to compel pla to provide a more complete response to dft's interrogatory #10 is denied without prejudice. This matter can be addressed at the 7/11/02 scheduled motion hearing. The deadline for expert reports are extended to 7/22/02; rebuttal expert reports are extended to 8/8/02, which will in no way affect the trial date of 10/21/02. ( signed by Magistrate Judge Judith K. Guthrie ) cc JKG, parties 6/28/02 (kjr) (Entered: 06/28/2002)", 
      "number": 97, 
      "tags": [
        {
          "@id": "http://lexmachina.com/vocab/tags#2", 
          "id": 2, 
          "name": "Order", 
          "visible": 1
        }
      ]
    }, 
    {
      "@id": "http://lexmachina.com/data/docket-entry/14030", 
      "documents": [], 
      "filed_on": "2002-07-01T00:00:00", 
      "id": 14030, 
      "nice_text": "Transcript of Hotline Call Hearing on Motion to Compel Pla's to answer interrogatory No. 10 before the Honorable Judith K. Guthrie, held 4:00 p.m. on 6/26/02 filed . Court Reporter: Shea Sloan ( 34 pages) (fnt) (Entered: 07/01/2002)", 
      "number": 98, 
      "tags": []
    }, 
    {
      "@id": "http://lexmachina.com/data/docket-entry/14031", 
      "documents": [], 
      "filed_on": "2002-07-01T00:00:00", 
      "id": 14031, 
      "nice_text": "OPPOSED MOTION by Samsung Electronics for leave to file Response to SanDisk Corp Motion to disqualify Weil, Gotshal & Manges LLP and brief in support thereof (djh) (Entered: 07/02/2002)", 
      "number": 99, 
      "tags": []
    }, 
    {
      "@id": "http://lexmachina.com/data/docket-entry/14032", 
      "documents": [], 
      "filed_on": "2002-07-02T00:00:00", 
      "id": 14032, 
      "nice_text": "ORDER denying [90-1] motion to extend time of hearing on its motion to transfer venue. The hearing will remain on the 8/26/02 scheduled date (signed by Judge John Hannah Jr) cc: attys, JH 7/2/02 (djh) (Entered: 07/02/2002)", 
      "number": 100, 
      "tags": [
        {
          "@id": "http://lexmachina.com/vocab/tags#2", 
          "id": 2, 
          "name": "Order", 
          "visible": 1
        }
      ]
    }, 
    {
      "@id": "http://lexmachina.com/data/docket-entry/14035", 
      "documents": [], 
      "filed_on": "2002-07-10T00:00:00", 
      "id": 14035, 
      "nice_text": "Response by Sandisk Corporation to [91-1] motion to disqualify McKool Smith PC (kjr) (Entered: 07/15/2002)", 
      "number": 117, 
      "tags": []
    }, 
    {
      "@id": "http://lexmachina.com/data/docket-entry/14036", 
      "documents": [], 
      "filed_on": "2002-07-11T00:00:00", 
      "id": 14036, 
      "nice_text": "Motion by Samsung Electronics, Samsung Electronics for Patrick Muir to appear pro hac vice (fnt) (Entered: 07/11/2002)", 
      "number": 102, 
      "tags": []
    }, 
    {
      "@id": "http://lexmachina.com/data/docket-entry/14037", 
      "documents": [], 
      "filed_on": "2002-07-11T00:00:00", 
      "id": 14037, 
      "nice_text": "Notice of attorney appearance for Samsung Electronics, Samsung Electronics by Patrick Muir, patent counsel for Samsung Electronics (fnt) (Entered: 07/11/2002)", 
      "number": 103, 
      "tags": []
    }, 
    {
      "@id": "http://lexmachina.com/data/docket-entry/14038", 
      "documents": [], 
      "filed_on": "2002-07-11T00:00:00", 
      "id": 14038, 
      "nice_text": "Motion by Samsung Electronics, Samsung Electronics for Charles Donohoe to appear pro hac vice (fnt) (Entered: 07/11/2002)", 
      "number": 104, 
      "tags": []
    }, 
    {
      "@id": "http://lexmachina.com/data/docket-entry/14040", 
      "documents": [], 
      "filed_on": "2002-07-11T00:00:00", 
      "id": 14040, 
      "nice_text": "PHV Filing Fee paid by atty Patrick Muir and Charles Donohoe; PHV FILING FEE $ 25.00 each, totaling $50.00, RECEIPT # 618911 (fnt) (Entered: 07/11/2002)", 
      "number": null, 
      "tags": []
    }, 
    {
      "@id": "http://lexmachina.com/data/docket-entry/14041", 
      "documents": [], 
      "filed_on": "2002-07-11T00:00:00", 
      "id": 14041, 
      "nice_text": "MOTION by Sandisk Corporation to compel Samsung to answer SankDisk's Interrogatory No. 10 and provide a claim construction for each asserted claim of the patents in suit (djh) (Entered: 07/11/2002)", 
      "number": 107, 
      "tags": []
    }, 
    {
      "@id": "http://lexmachina.com/data/docket-entry/14043", 
      "documents": [], 
      "filed_on": "2002-07-11T00:00:00", 
      "id": 14043, 
      "nice_text": "Minutes Re: [0-0] motion hearing & tutorial by Judge John Hannah Jr. on 7/11/02 (Ct rep/ECRO: Jan Mason) (pad) (Entered: 07/12/2002)", 
      "number": 108, 
      "tags": []
    }, 
    {
      "@id": "http://lexmachina.com/data/docket-entry/14044", 
      "documents": [], 
      "filed_on": "2002-07-11T00:00:00", 
      "id": 14044, 
      "nice_text": "MOTION by Toshiba to quash subbpoena issued by pla for production of documents (kjr) (Entered: 07/12/2002)", 
      "number": 110, 
      "tags": []
    }, 
    {
      "@id": "http://lexmachina.com/data/docket-entry/14045", 
      "documents": [], 
      "filed_on": "2002-07-12T00:00:00", 
      "id": 14045, 
      "nice_text": "Letter to the Court from David Healey. (pad) (Entered: 07/12/2002)", 
      "number": 109, 
      "tags": []
    }, 
    {
      "@id": "http://lexmachina.com/data/docket-entry/14046", 
      "documents": [], 
      "filed_on": "2002-07-12T00:00:00", 
      "id": 14046, 
      "nice_text": "7/12/02 Letter to the Court from Tracy Crawford (pad) (Entered: 07/12/2002)", 
      "number": 111, 
      "tags": []
    }, 
    {
      "@id": "http://lexmachina.com/data/docket-entry/14047", 
      "documents": [], 
      "filed_on": "2002-07-12T00:00:00", 
      "id": 14047, 
      "nice_text": "MOTION by Sandisk Corporation to exceed page limitation of Sandisk's reply to Samsung Electronics Co Response to their Motion to disqualify Weil, Gotshal & Manges, LLP (fnt) Modified on 08/22/2002 (Entered: 07/15/2002)", 
      "number": 112, 
      "tags": []
    }, 
    {
      "@id": "http://lexmachina.com/data/docket-entry/14048", 
      "documents": [], 
      "filed_on": "2002-07-12T00:00:00", 
      "id": 14048, 
      "nice_text": "MOTION by Sandisk Corporation to extend time to file its reply to Samsung Electronics Response to Sandisk's Motion to Disqualify Weil, Gotshal & Manges, LLP (fnt) (Entered: 07/15/2002)", 
      "number": 113, 
      "tags": []
    }, 
    {
      "@id": "http://lexmachina.com/data/docket-entry/14049", 
      "documents": [], 
      "filed_on": "2002-07-15T00:00:00", 
      "id": 14049, 
      "nice_text": "Scheduling order setting following deadlines: Depositions of witnesses limited to 20 per side; depositions limited to total of 120 hrs, but no more than 10 hrs per witness; venue hearing: 7/17/02; pla to submit opening claim construction brief, response due 9/19/02: 8/19/02; dft to identify invalidity and/or unenforceability contentions: 8/19/02, response due 9/19/02; joint report on claim construction: 9/27/02; expert reports due 9/27/02; rebuttal expert reports due 10/18/02; fact & expert discovery closes 10/31/02; dispositive motions due 11/8/02; responses to dispositive motions due 11/18/02; joint pretrial order due 11/30/02; trial to commence in Tyler on 1/6/03 ( signed by Judge John Hannah Jr. ) cc JH, parties 7/15/02 (kjr) (Entered: 07/15/2002)", 
      "number": 114, 
      "tags": [
        {
          "@id": "http://lexmachina.com/vocab/tags#2", 
          "id": 2, 
          "name": "Order", 
          "visible": 1
        }
      ]
    }, 
    {
      "@id": "http://lexmachina.com/data/docket-entry/14050", 
      "documents": [], 
      "filed_on": "2002-07-15T00:00:00", 
      "id": 14050, 
      "nice_text": "ORDER granting [104-1] motion for Charles Donohoe to appear pro hac vice ( signed by Judge John Hannah Jr. ) cc JH, parties 7/15/02 (kjr) (Entered: 07/15/2002)", 
      "number": 115, 
      "tags": [
        {
          "@id": "http://lexmachina.com/vocab/tags#2", 
          "id": 2, 
          "name": "Order", 
          "visible": 1
        }
      ]
    }, 
    {
      "@id": "http://lexmachina.com/data/docket-entry/14051", 
      "documents": [], 
      "filed_on": "2002-07-15T00:00:00", 
      "id": 14051, 
      "nice_text": "ORDER granting [102-1] motion for Patrick Muir to appear pro hac vice ( signed by Judge John Hannah Jr. ) cc JH, parties 7/15/02 (kjr) (Entered: 07/15/2002)", 
      "number": 116, 
      "tags": [
        {
          "@id": "http://lexmachina.com/vocab/tags#2", 
          "id": 2, 
          "name": "Order", 
          "visible": 1
        }
      ]
    }, 
    {
      "@id": "http://lexmachina.com/data/docket-entry/14052", 
      "documents": [], 
      "filed_on": "2002-07-17T00:00:00", 
      "id": 14052, 
      "nice_text": "ORDER granting [113-1] motion to extend time to file its reply to Samsung Electronics Response to Sandisk's Motion to Disqualify Weil, Gotshal & Manges, LLP ( signed by Judge John Hannah Jr) cc; attys, JH 7/17/02 (djh) (Entered: 07/17/2002)", 
      "number": 118, 
      "tags": [
        {
          "@id": "http://lexmachina.com/vocab/tags#2", 
          "id": 2, 
          "name": "Order", 
          "visible": 1
        }
      ]
    }, 
    {
      "@id": "http://lexmachina.com/data/docket-entry/14054", 
      "documents": [], 
      "filed_on": "2002-07-17T00:00:00", 
      "id": 14054, 
      "nice_text": "ORDER granting [112-1] motion to exceed page limitation Sandisk's reply to Samsung Electronics Co Response to their \"Motion to disqualify Weil, Gotshal & Manges, LLP ( signed by Judge John Hannah Jr) cc; attys, JH 7/17/02 (djh) (Entered: 07/17/2002)", 
      "number": null, 
      "tags": [
        {
          "@id": "http://lexmachina.com/vocab/tags#2", 
          "id": 2, 
          "name": "Order", 
          "visible": 1
        }
      ]
    }, 
    {
      "@id": "http://lexmachina.com/data/docket-entry/14057", 
      "documents": [], 
      "filed_on": "2002-07-18T00:00:00", 
      "id": 14057, 
      "nice_text": "Reply by Samsung Electronics to response to [91-1] motion to disqualify McKool Smith PC (djh) (Entered: 07/18/2002)", 
      "number": 122, 
      "tags": []
    }, 
    {
      "@id": "http://lexmachina.com/data/docket-entry/14058", 
      "documents": [], 
      "filed_on": "2002-07-18T00:00:00", 
      "id": 14058, 
      "nice_text": "UNOPPOSED MOTION by Samsung Electronics to extend deadlines for certain briefs (djh) (Entered: 07/18/2002)", 
      "number": 123, 
      "tags": []
    }, 
    {
      "@id": "http://lexmachina.com/data/docket-entry/14059", 
      "documents": [], 
      "filed_on": "2002-07-18T00:00:00", 
      "id": 14059, 
      "nice_text": "Reply by Samsung Electronics in opposition to response to [95-1] motion to strike Sandisk Corp demand for jury trial (djh) (Entered: 07/18/2002)", 
      "number": 124, 
      "tags": []
    }, 
    {
      "@id": "http://lexmachina.com/data/docket-entry/14060", 
      "documents": [
        {
          "@id": "http://lexmachina.com/data/documents/2000014882", 
          "id": 2000014882, 
          "text": "Case 9:O2-cv~OOO58~jH Document 125 F~ed 07/19/2-Q02 Page 1 of 18\n\n\nIN THE UNITED STATES DISTRICT COURT\n- i-~'~ FOR THE EASTERN DISTRICT OF TEXAS\nLUFKIN DIVISION\nJUL 1 9 2002\nSAMSUNG ELECTRONICS CO., \ufffd\nLTD., . \ufffd\n\nPlaintiff, \ufffd\n\ufffd\nv. \ufffd No. 9:02-CV-58\n\ufffd\nSANDISK CORPORATION, \ufffd\n\ufffd\nDefendant. \ufffd\n\nORDER TRANSFERRING VENUE\n\nBefore the Court is the Motion to Transfer Venue to the Northern District of\n\nCalifornia Pursuant to 28 U.S.C. \ufffd 1404(a). After reviewing the written and oral\n\narguments of counsel, as well as the applicable law, it is the opinion of the Court\n\nthat the motion should be GRANTED. For the reasons stated below, the Court\n\nconcludes that this case would be more properly heard in the Northern District of\n\nCalifornia.\n\nBACKGROUND\n\nSamsung Electronic Co., Ltd., (\"Samsung\"), a company organized under the\n\nlaws of South Korea with its principal place of business in Suwon City, Kyungki.-\n\nDo, Korea, brings suit claiming infringement of patents by SanDisk Corporation\nCase 9:O2~cv~OOO58~jH Document 125 HIed 07/19/2002 Page 2 of 1$\n\n\n(\"SanDisk\"), a company organized under the laws of Delaware, with its principal\n\nplace of business in Sunnyvale, California. Samsung seeks injunctive relief for the\n\nalleged infringement of three patents1 dealing flash electrically erasable and\n\nprogrammable read only memory devices, called \"flash EEPROM\" chips. The\n\npatents in question are Patent No. 5,473,563 (\"the `563 patent\") issued to Samsung\n\non December 5, 1995 and entitled \"Nonvolatile Semiconductor Memory;\" Patent\n\nNo. 5,514,889 (\"the `889 patent\"), issued on May 7, 1996, and entitled \"Non-\n\nVolatile Semiconductor Memory Device and Method for Manufacturing the\n\nSame;\" and Patent No. 5,546,341 (\"the `341 patent\"), issued August 13, 1996, and\n\nentitled \"Nonvolatile Semiconductor Memory.\" It is undisputed that these patents\n\ndeal with what is characterized as NAND flash memory.\n\nSanDisk admits that it sells NAND flash memory cards to original\n\nequipment manufactures (\"OEMs\"), and to industrial and consumer markets but\n\nasserts that it has not infringed the subject patents, and/or that the subject patents\n\nare invalid, and that the products being sold are covered by the licensing\n\nagreement between the parties that resulted from previous lawsuits between the\n\nparties in the Northern District of California and in the United States International\nThe suit originally included a fourth patent, No. 5,642,309, which claim has been\nwithdrawn.\nCase 9:02-cv~O0053~jH Document 125 F~ed 07/19/2002 Page 3 of 18\n\n\nTrade Commission (\"ITC\")2. SanDisk asserts its defense plus counterclaims based\n\nupon the above assertions.\n\nSanDisk moves for change of venue to the Northern District of California\n\nboth pursuant to the forum selection clause of the contract executed in August,\n, entitled\"Settlement and Patent Cross License Agreement Between SanDisk\n\nCorporation and Samsung Electronic Co., Ltd.,\" (\"the Agreement.\") and for the\n\nconvenience of the parties pursuant to 28 U.S.C. \ufffd 1404(a). Samsung counters,\n\ngenerally, that the basis of its infringement claims are not covered by the\n\nAgreement, alternatively that the forum selection clause in the Agreement is\n\npermissive, and that the Eastern District of Texas is just as convenient a forum, if\n\nnot more so than the Northern District of California for everyone except SanDisk,\n\nand that justice requires that the case remain in the district where it was filed\n\nbecause Samsung seeks an injunction and transfer would result in a delay.\n\nDISCUSSION\n\nBefore reaching the request for transfer for the convenience of the parties\n\npursuant to 28 U.S.C. \ufffd 1404(a), the Court will address the issues raised by the\nThe pleadings indicate that Samsung sued SanDisk in the Northern District of California\non October 3, 1995 asserting patent infringement. In January, 1996, SanDisk sued Samsung in\nthe ITC alleging patent infringement by Samsung. An administrative law judge found that\nSamsung infringed two SanDisk patents. The ITC affirmed this finding. The result was the\nSettlement Agreement entered into between the parties in August, 1997.\nCase 9:02~cv~0O058~jH Document 125 FUed 07/1 9~'2002 Page 4 of 18\nAgreement between the parties. It is clear that if SanDisk was granted a\n\nlicense to make, use, sell or offer to sell or import the patented inventionls, this is\n\na valid defense to a patent infringement suit. See P.J. Federico, Commentary on\n\nthe New Patent Act, 75 J.Pat. & Trademark Off. Soc'y 161, 215 (1993)(reprinted\n\nfrom 35 U.S.C.A. 1954 ed.) Patent infringement is defined by 35 U.S.C. \ufffd 271(a)\n\nas unauthorized use, sale, etc. of the patented invention.\n\nSanDisk asserts that it has a license under all of the asserted patents because\n\nnone of the patents-in-suit is specifically directed to \"Samsung Patented NAND\n\nFlash Memory Technology,\" as the term is defined in the Agreement. Therefore,\n\nSanDisk argues that the current dispute is covered by this Agreement, including\n\nthe Agreement's venue provisions. Samsung responds that the Agreement\n\nexpressly did not grant SanDisk a license \"for NAND flash memory products.\"\n\nAccordingly, Samsung's position is that the venue provision contained in the\n\nAgreement does not apply in this dispute.\n\nThe 1997 Settlement Agreement between the parties:\n\nThe Court's first task is to determine whether or not the dispute in this case\n\nis covered by the Agreement. The pertinent provisions of the Agreement are as\n\nfollows:\n\nParagraph 5.1 of the Agreement states:\nCase 9:02-cv~00053~jH Document 125 F~ed 07/19/2002 Page 5 of 18\n.1 Samsung hereby grants to SanDisk and its Subsidiaries non-\n\nexclusive, non-transferable, worldwide licenses under [1J Samsung\n\nPatent Claims and [2} Samsung MLC Patent Claims (without the right\n\nto sublicense), except as noted below, to make, to have made, to use,\n\nto sell and offer to sell (either directly or indirectly), and to import {3~\n\nSanDisk Licensed Products. Under the terms of this license, SanDisk\n\nand its Subsidiaries are permitted to use the names of third party\n\noriginal equipment manufacturers (OEMs) or resellers on SanDisk\n\nLicensed Products.\n\nThe scope of this license is determined by three defined terms that, in turn,\n\nincorporate numerous other defined terms.3 For example, the defined term\n\n\"Samsung Patent Claims\" is defined in paragraph 2.36. That definition, in turn,\n\nincorporates the defined term (1) Integrated Circuits, (2) Flash Memory Product,\n\n(3) Samsung MLC Patent Claims, and (4) Samsung Excluded MLC Patent Claims.\n\nThe definitions for \"Samsung MLC Patent Claims\" and \"SanDisk License\n\nProducts\" similarly incorporate yet further defined terms.\n\nAt this point in the litigation, the parties have not described the accused\n\nproducts but appear to assume that SanDisk's products would be otherwise\nThe Agreement has fifty terms which are specifically defined.\nCase 9:02-cv~00058~.jH Document 125 F~ed 07/1912002 Page 6 of 18\n\n\nlicensed under paragraph 5.1 except for the \"carve out\" provision of Paragraph\n.2, which provides:\n.2 Samsung does not grant SanDisk or its Subsidiaries a license to\n\nmake, to have made, to use, to sell and offer to sell (either directly or\n\nindirectly) or to import Flash Memory Product or MLC Flash\n\nMemory Product that uses Samsung Patented NAND Flash Memory\n\nTechnology.\n\nIt is noted that Paragraph 5.2 incorporates the defined term \"Samsung\n\nPatented NAND Flash Memory Technology\" as opposed to the broader term\n\n\"NAND Flash Memory Technology.\" \"Samsung Patented NAND Flash Memory\n\nTechnology\" is defined by Paragraph 2.22 as follows:\n.22 \"Samsung Patented NAND flash Memory Technology\" shall\n\nmean NAND Flash Memory Product or NAND Flash Memory\n\nTechnology covered by Samsung Patent Claims, Samsung MLC\n\nPatent Claims or Samsung Excluded Patent Claims.\n\nSanDisk asserts that none of the patents-in-suit is specifically directed to\n\n\"Samsung Patented NAND flash Memory Technology\" while Samsung claims that\n\nthe patents-in-suit are \"carved out\" of the licensing agreement by the provisions of\n\nParagraph 5.2. It is clear that SanDisk's license defense, whether raised as an\nC 0~o\n~ Document 125 F~ed 07/19/2002 Page 7 of 1$\n\n\naffirmative defense or a counterclaim, will require an interpretation of the\n\nAgreement as well as the patent claims Samsung asserts. Accordingly, it is clear\n\nthat the dispute in this suit is governed to large degree, if not entirely, by the\n\nagreement entered into between the parties in 1997.\n\nThe 1997 Agreement's Venue Provision:\n\nHaving determined that the Agreement governs the dispute in this suit, we\n\nnext look at the venue provision. Paragraph 9.9 of the Agreement provides:\n.9 All disputes arising directly under the express terms of this\n\nAgreement shall be resolved as follows: First, the senior management\n\nof both parties shall engage in good faith negotiations for up to thirty\n\n(30) days in an attempt to resolve such disputes. If the disputes\n\ncannot be resolved by the senior management within the thirty (30)\n\nday good faith negotiation period, either party may initiate litigation\n\nin the Northern District of California.4\nFurther reference to the parties' intent regarding the venue of a suit brought to resolve a\ndispute under the Agreement is found in Paragraph 9.6, which states in relevant part:\n.6 This Agreement shall be governed by the substantive laws of the State of\nCalifornia, all rights and obligations of the parties of this Agreement and the\ninterpretation, construction and enforceability hereof shall also be governed by the\nlaws of the Sate of California. SanDisk and Samsung agree (i) to submit to the\njurisdiction of the Federal Court for the Northern District of California for any\naction properly brought pursuant to this Agreement; (ii) to waive any objection\nthey may have now or hereafter to the venue of any suit brought pursuant to clause\n(i) above....\nCase 9:02~cv~0O058~jH Document 125 FUed 07/1912~02 Page 8 of 18\n\n\nPredictably, SanDisk argues that Paragraph 9.9 constitutes a mandatory\n\nforum selection clause that requires that any suits brought to resolve disputes\n\nunder the Agreement must be filed in Northern California while Samsung argues\n\nthat the venue provision is merely permissive.\n\nSanDisk's argument is based upon the use of the word \"shall\" at the\n\nbeginning of the paragraph which SanDisk asserts applies to the entire paragraph,\n\nwhich therefore sets forth a mandatory procedure for settling disputes under the\n\nAgreement, i.e., first a mandatory good faith negotiation period of thirty days, and\n\nfailing successful negotiations, suit \"may\" be brought in the Northern District of\n\nCalifornia. SanDisk asserts that the \"may be brought\" language, rather than \"shall\n\nbe brought\" shows that the parties intended that the action of bringing suit was\n\npermissive rather than required. In other words, SanDisk asserts that the plain\n\nreading of the paragraph shows a mandatory procedure for resolving disputes\n\nunder the Agreement which includes a permissive step of bringing suit in the\n\nNorthern District of California. SanDisk argues that the use of the word \"may\"\n\nrefers to the initiation of the litigation but not to the location of the litigation,\n\nwhich is clearly intended to be the Northern District of California.\n\nSamsung argues that the \"may be brought\" language is strictly permissive\n\nand does not show that the parties intended venue to be restricted to the Northern\nCase 9:02-cv~00053~jH Document 125 F~ed 07/19/2002 Page 9 of 18\n\n\nDistrict of California. SanDisk counters by saying this interpretation would render\n\nthe \"may be brought in the Northern District of California\" as mere useless\n\nsurplusage, a result which is an anathema in contract law. Neither party argues\n\nthat the subject language creates an ambiguity.\n\nWhether a contract is ambiguous is a question of law that must be decided\n\nby examining the contract as a whole in light of the circumstances present when\n\nthe contract was entered. Columbia Gas Transmission Corp. v. New Ulm Gas.\n\nLtd., 940 S.W.2d 587, 589 (Tex. 1996). A written contract is ambiguous if its\n\nlanguage is subject to two or more reasonable interpretations. It is not ambiguous\n\nif it is so worded that it can be given definite or certain legal meanings. An\n\nambiguity does not arise simply because the parties advance conflicting\n\ninterpretations of the contract. Forbau v. Aetna Life Ins. Co., 876 S.W.2d 132, 134\n\n(Tex.1994); Sun Oil Co. (Delaware) v. Madeley, 626 S.W.2d 726, 727 (Tex.1981).\n\nFor an ambiguity to exist, both interpretations must be reasonable. See National\n\nUnion Fire Ins. Co. v. CBI Industries, Inc., 907 S.W.2d 517, 520 (Tex.1995); see\n\nalso Glover v. National Ins. Underwriters, 545 S.W.2d 755, 761 (Tex.l977). In\n\ndetermining the ambiguity of a contract, the court's primary concern is to ascertain\n\nand give effect to the intentions of the parties as expressed in the contract. GTE\n\nMobilnet of South Texas Ltd. Partnership v. Telecell Cellular, Inc., 955 S.W. 2d\nTh~e 9~09\n$-jH Document 125 F~ed 07/19/2002 Page 10 of 18\n, 289 (Tex. App. - Houston [1St Dist] 1997, writ denied). In determining the\n\nparties' intention, a court must examine the contract in its entirety and all of its\n\nprovisions must be considered and construed together. Esquivel v. Murray Guard,\n\nInc., 992 S.W. 2d 536, 543 (Tex. App. - Houston [14th Dist] 1999, petition\n\ndenied.) The court should strive for a decision that renders no provision\n\nmeaningless. Northern Natural Gas Co. v. Conoco, Inc., 939 S.W. 2d 676, 679\n\n(Tex. App. - El Paso 1996), aff'd 986 S.W. 2d 603 (Tex. 1998).\n\nGiven the foregoing rules of construction, it appears clear that, viewing the\n\ncontract as a whole, the intent of the parties was that any suit brought under its\n\nprovisions would be brought in the Northern District of California. This is\n\nwarranted not only by the language of the Agreement itself, but by the prior\n\ndealings between the parties, which included a patent infringement suit brought in\n\nthe Northern District of California. The Court also notes that Samsung is a\n\nKorean corporation and it is likely that the location of the Northern District of\n\nCalifornia as geographically closer to Korea and therefore easier to reach from\n\nKorea, as well as other factors to be discussed below, played a part in Samsung's\n\nintent to limit litigation to the Northern District of California rather than facing the\n\nprospect of being sued anywhere within the United States. Given the admitted fact\n\nthat the products in question are sold throughout the United States, neither party\nCase 9:02-cv~0OO5$-jH Document 125 F~ed 07/19/2002 Page 11 of 18\n\n\ncould successfully contest personal jurisdiction in a patent infringement suit in\n\nany district in the county, and would be motivated to limit litigation to an agreed\n\nupon, convenient location.\n\nTherefore, the Court finds that the interpretation of the contract's venue\n\nprovision advanced by Samsung as merely permissive as is not a reasonable\n\nconstruction. The Court agrees that such a construction would render the\n\nlanguage \"may be brought in the Northern District of California\" meaningless\n\nsurplusage. See Florida Polk County v. Prison Health Servs., Inc., 170 F.3d 1081,\n(1 1th Cir. 1999). Finding that the venue provision is mandatory, transfer of\n\nvenue to the Northern District of California is warranted pursuant to Paragraph\n.9 of the Agreement's provisions.\n\nThe \ufffd 1404 considerations:\n\nFor the reasons stated below, the Court further finds that SanDisk has\n\nsuccessfully met its burden of showing that considering all relevant factors, the\n\nlitigation would more conveniently proceed and the interests ofjustice would be\n\nbetter served by transfer to the Northern District of California.\nU.S.C. \ufffd 1404(a), provides: \"For the convenience of parties and\n\nwitnesses, in the interest ofjustice, a district court may transfer any civil action to\n\nany other district or division where it might have been brought.\"\nra~ 9~09\nL.I~Uu058~.JH Document 125 F~ed 07/19/2o~ Face 12 of 18\n\n\nThe Supreme Court has noted that \ufffd 1404(a) is intended to place discretion\n\nin the district court to adjudicate motions for transfer according to an\n\n\"individualized, case-by-case consideration of convenience and fairness.\" Stewart\n\nOrg., Inc. v. Ricoh Corp., 487 U.S. 22,29 (1988); Van Dusen v. Barrack, 376 U.S.\n, 622 (1964). Stated another way, the trial court must exercise its discretion in\n\nlight of the particular circumstances of the case. See Radio Santa Fe v. Sena, 687\n\nF.Supp. 284, 287 (E.D.Tex.1988).\n\nIn determining whether to grant a transfer of venue under \ufffd 1404(a), the\n\nCourt must consider all relevant factors to determine whether or not, on balance,\n\nthe litigation would more conveniently proceed and the interests ofjustice be\n\nbetter served by transfer to a different forum. See Peteet v. Dow Chemical Co., 868\n\nF.2d 1428, 1436 (5th Cir. 1989), cert. denied, 493 U.S. 935 (1989).\n\nThe court should balance two categories of interests when determining\n\nwhether to transfer venue: (1) the convenience of the litigants, and (2) the public\n\ninterests in the fair and efficient administration of justice. See International\n\nSoftware Sys., Inc. v. Amplicon, Inc., 77 F.3d 112, 115 (5th Cir.l996); Walter\n\nFuller Aircraft Sales v. The Repub. of the Philippines, 965 F.2d 1375, 1389 (5th\n\nCir. 1992).\n\nConvenience factors include: (1) plaintiffs choice of forum; (2) the\nCase 9:02-cv~0O058-jH Document 125 F~ed 07/19/200.2 Page 13 of 18\n\n\nconvenience of parties and witnesses; (3) the place of the alleged wrong; (4) the\n\nlocation of counsel; (5) the cost of obtaining the attendance of witnesses; (6) the\n\naccessibility and location of sources of proof; and (7) the possibility of delay and\n\nprejudice if transfer is granted. See, e.g., Lindloff v. Schenectady Intern., 950\n\nF.Supp. 183, 185-186. (E.D.Tex.l996) (weighing a combination of factors).\n\nPublic interest factors consist of (1) the administrative difficulties caused by\n\ncourt congestion, (2) the local interest in adjudicating local disputes; (3) the\n\nunfairness of burdening citizens in an unrelated forum with jury duty; and (4) the\n\navoidance of unnecessary problems in conflict of laws. See Walter Fuller Aircraft\n\nSales, 965 F.2d at 1389.\n\nPlaintiff's choice of forum is generally entitled to great weight. However,\n\nunder Piper Aircraft Co. v. Reyno, 454 U.S. 235 (1981), the plaintiffs' choice is\n\nnot given much significance if the forum is not the plaintiff's place of residence,\n\nsee Hanby v. Shell Oil Co., 144 F. Supp. 2d 673, 677 (E.D. Tex. 2001) or when the\n\nplaintiff's chosen forum has no factual nexus to the case. See Robertson v.\n\nKiamichi RR Co., L.L.C., 42 F. Supp.2d 651, 656 (E.D. Tex. 1999). It is\n\nundisputed that Plaintiff is a Korean company and is not a resident of the Eastern\n\nDistrict of Texas. While Plaintiff argues that infringement occurred in the district\n\nand that there is thus a factual nexus to this district, this argument is gravely\nCase 9:02~cv~00o58-JH Document 125 Ffled 07/19/2002 Page 14 of 18\n\n\nundermined by the supposition that the infringement, if any, occurred in every\n\ndistrict within the United States. This fact negates any special factual nexus to this\n\ndistrict. Therefore, the Court finds that the Plaintiff's choice of forum in the\n\npresent case is not entitled to great deference. The presumption in favor of\n\nplaintiff's choice of forum is overcome when the private and public interest\n\nfactors clearly point toward trial in the alternative forum. Schexnider v.\n\nMcDermott Intern., Inc. 817 F.2d 1159, 1163 (5th Cir.), cert. denied, 484 U.S.\n, 108 S.Ct. 488 (1987).\n\nThe next factor is the convenience of the parties and witnesses. It is clear\n\nthat attendance at a trial in the Northern District of California would be more\n\nconvenient for the witnesses in this case. Plaintiff is a Korean company and will\n\nundoubtedly have witnesses attending from Korea. SanDisk may call third party\n\nwitnesses from Tohisba, a electronics firm located in Japan. Northern California\n\nhas major airports with direct flights from both Tokyo, Japan and Seoul, Korea.\n\nTrial in the Eastern District of Texas would require much longer flight times for\n\nthese witnesses plus require taking a commuter flight from the Dallas-Fort Worth\n\nAirport to Pounds Field in Tyler.5 In our present atmosphere of tight security at\nThe Court and the parties earlier agreed to hold hearings in Tyler, Texas rather than\nLulkin, Texas for the convenience of the attorneys in the case due to Lufkin's more remote\nlocation. However, should a jury trial be required, the even more remote location of Lufkin\nTh~e 9~O2\n~L.I~UuO58~JH Document 125 FUed 07/19/20Q2 Faae 15 of 18\n\n\nairports and flight delays, a non-stop flight without the needed extra commuter\n\nflight is clearly preferable. The prospect of missing connecting flights in today's\n\ntravel climate cannot be discounted. This fact also hold true for any witness\n\nneeding to use air transportation, whether from abroad or within the United States.\n\nThe Court also takes into consideration that both Plaintiff and Defendant have\n\nbusiness operations within the Northern District of California in \"Silicon Valley,\"6\n\nand have negotiated various agreements there. It is obvious from the language of\n\nthe Settlement Agreement, discussed above, that the parties do not find the\n\nNorthern District of California an inconvenient forum. Thus the Court finds that\n\nthe convenience of the parties and witnesses weighs heavily toward change of\n\nvenue.\n\nThe Court finds that the place of the alleged wrong is a neutral factor.\n\nBecause the alleged infringement occurred throughout every district in the land,\n\nthis factor does not favor any district.\n\nThe location of counsel is entitled to very slight consideration, but\n\nwhatever consideration it is entitled to weighs in favor of transfer. Local counsel\n\n\nwould be used, which is more inconvenient than Tyler. Lufkin has no commuter air\ntransportation.\nS~j~isk's headquarters and almost all of its employees are in Sunnyvale, California and\nSamsung owns a subsidiary, Samsung Semiconductor, Inc., in San Jose, California.\nCase S:O2~cv~OOO58jH Document 125 FUed 07/19/2002 Page 16 of 18\n\n\nmust be excepted from consideration as local counsel can be obtained in any\n\ndistrict. It is clear that SanDisk's attorneys are located in the Northern District of\n\nCalifornia. Samsung's counsel, Weil, Gotshal & Manges, according to its website,\n\nhas thirteen offices, including a 50 lawyer office in Redwood Shores, California,\n\nwhich it advertises as being in \"Silicon Valley.\" The website notes that the\n\nattorneys in this California office are \"proficient in all aspects of technology,\n\nincluding.., semi-conductors\" and that the attorneys are an \"integral part of the\n\nfirm's 90 lawyer Technology and Proprietary Rights Group....\"\n\nThe cost of obtaining the attendance of witnesses favors transfer for the\n\nsame reason that the Northern District of California is more convenient for\n\nwitnesses. While some witnesses may be geographically closer to the Eastern\n\nDistrict of Texas, the venue provisions of the Agreement clearly show the parties\n\nagree that the Northern District of California was convenient for both sets of\n\nwitnesses in this type of dispute. Because of modern technology, the accessibility\n\nand location of sources of proof is insignificant. With the advent of copying\n\nmachines, faxes, and computer generated displays for demonstrative purposes, this\n\ntype of case could be tried in any district.\n\nThe Court recognizes the possibility of delay if transfer is granted.\n\nHowever, the parties were well aware of the nature of proceeding in the Northern\nCase 9:O2~cv~OOO58JH Document 125 FUed 07/19/2002 Page 17 of 18\n\n\nDistrict of California when they entered into the Settlement Agreement. The\n\nCourt finds this factor, alone, would indicate that neither party considers that\n\ndistrict to be an inconvenient forum. While the possibility of delay weighs against\n\ntransfer, this factor alone, does not defeat the parties' clear intent regarding venue\n\nexpressed in the Agreement, or the convenience and public interest factors.\n\nThe Court finds the public interest factors regarding the local interest in\n\nadjudicating local disputes and the unfairness of burdening citizens in an unrelated\n\nforum with jury duty weigh toward transfer. While it is true that any district's\n\ncitizens may have an interest in nation wide patent infringement, the nexus to the\n\nEastern District of Texas is tenuous. However, both Plaintiff and Defendant have\n\nmajor business operations in the Northern District of California. Therefore, the\n\nnexus to that district is much greater. The citizens of that forum would have an\n\ninterest in the outcome of the suit between two major employers in their district\n\nand would not be inconvenienced by its trial. The avoidance of unnecessary\n\nproblems in conflict of laws is a minor factor, entitled to very little consideration,\n\nbut what weight it does carry adds to the side of the transfer equation. The\n\nSettlement Agreement states that it is to be interpreted according to California law,\n\na task well suited to the court sitting in the Northern District of California.\n\nTherefore the Court finds that SanDisk has met its burden of showing that,\nCase SO2~cv~0OO58JH Document 125 F~ed 07/19,2000 Page 18 of 18\n\n\non balance, this litigation would more conveniently proceed and the interests of\n\njustice would be better served by transfer to the Northern District of California.\n\nCONCLUSION\n\nIT IS THEREFORE ORDERED that SanDisk's Motion to Transfer Venue\n\nunder both the provisions of the Settlement Agreement between the parties entered\n\ninto in August, 1997, and pursuant to 28 U.S.C. \ufffd 1404(a) is GRANTED.\n\nIT IS ORDERED that this action is hereby transferred to the Northern\n\nDistrict of California.\n\nSIGNED this _______________________ day of July, 2002.\n\nSTATES DISTRICT\n"
        }
      ], 
      "filed_on": "2002-07-19T00:00:00", 
      "id": 14060, 
      "nice_text": "ORDER granting [25-1] Sandisk's motion to transfer venue to the Northern District of California under both provisions of the settlement agreement between parties entered into in August, 1997, and pursuant to 28 U S C 1404(a) (signed by Judge John Hannah Jr) cc; attys, JH 7/19/02 (djh) (Entered: 07/19/2002)", 
      "number": 125, 
      "tags": [
        {
          "@id": "http://lexmachina.com/vocab/tags#2", 
          "id": 2, 
          "name": "Order", 
          "visible": 1
        }, 
        {
          "@id": "http://lexmachina.com/vocab/tags#111", 
          "id": 111, 
          "name": "Order re: Transfer", 
          "visible": 1
        }
      ]
    }, 
    {
      "@id": "http://lexmachina.com/data/docket-entry/14061", 
      "documents": [], 
      "filed_on": "2002-07-21T00:00:00", 
      "id": 14061, 
      "nice_text": "EMERGENCY MOTION by Samsung Electronics to stay transfer of case (djh) (Entered: 07/22/2002)", 
      "number": 126, 
      "tags": []
    }, 
    {
      "@id": "http://lexmachina.com/data/docket-entry/14062", 
      "documents": [], 
      "filed_on": "2002-07-21T00:00:00", 
      "id": 14062, 
      "nice_text": "MOTION by Samsung Electronics for reconsideration of [125-1] order granting Sandisk motion to transfer venue to California (djh) (Entered: 07/22/2002)", 
      "number": 127, 
      "tags": []
    }, 
    {
      "@id": "http://lexmachina.com/data/docket-entry/14063", 
      "documents": [], 
      "filed_on": "2002-07-22T00:00:00", 
      "id": 14063, 
      "nice_text": "Reply by Samsung Electronics to response to [110-1] motion to quash subbpoena issued by pla for production of documents (djh) (Entered: 07/22/2002)", 
      "number": 128, 
      "tags": []
    }, 
    {
      "@id": "http://lexmachina.com/data/docket-entry/14064", 
      "documents": [], 
      "filed_on": "2002-07-22T00:00:00", 
      "id": 14064, 
      "nice_text": "ORDER granting [112-1] motion to exceed page limitation Sandisk's reply to Samsung Electronics Co Response to their Motion to disqualify Weil, Gotshal & Manges, LLP, set notice of compliance due for 7/18/02 for Samsung Electronics (signed by Judge John Hannah Jr) cc; attys, JH 7/17/02 (djh) Modified on 07/25/2002 (Entered: 07/22/2002)", 
      "number": 129, 
      "tags": [
        {
          "@id": "http://lexmachina.com/vocab/tags#2", 
          "id": 2, 
          "name": "Order", 
          "visible": 1
        }
      ]
    }, 
    {
      "@id": "http://lexmachina.com/data/docket-entry/14065", 
      "documents": [], 
      "filed_on": "2002-07-23T00:00:00", 
      "id": 14065, 
      "nice_text": "Response by Sandisk Corporation to [127-1] motion for reconsideration of [125-1] order granting Sandisk motion to transfer venue to California (fnt) Modified on 07/25/2002 (Entered: 07/24/2002)", 
      "number": 130, 
      "tags": []
    }, 
    {
      "@id": "http://lexmachina.com/data/docket-entry/14067", 
      "documents": [], 
      "filed_on": "2002-07-24T00:00:00", 
      "id": 14067, 
      "nice_text": "Reply by Samsung Electronics to response to [127-1] motion for reconsideration of [125-1] order granting Sandisk motion to transfer venue to California (djh) Modified on 07/25/2002 (Entered: 07/24/2002)", 
      "number": 132, 
      "tags": []
    }, 
    {
      "@id": "http://lexmachina.com/data/docket-entry/14069", 
      "documents": [], 
      "filed_on": "2002-07-25T00:00:00", 
      "id": 14069, 
      "nice_text": "Response by Samsung Electronics to [107-1] motion to compel Samsung to answer SankDisk's Interrogatory No. 10 and provide a claim construction for each asserted claim of the patents in suit (djh) (Entered: 07/25/2002)", 
      "number": 134, 
      "tags": []
    }, 
    {
      "@id": "http://lexmachina.com/data/docket-entry/14070", 
      "documents": [
        {
          "@id": "http://lexmachina.com/data/documents/5846", 
          "id": 5846, 
          "text": "     Case 9:02~cv~~00058~JH\n                          Document 135                      F~ed\n                                                               07/30/2002        Page 1 of 8\n\n\n\n                                                                                  FILED CLER~(\n                                                                                         -\n\n\n                          IN THE UNITED STATES DISTRICT COURT                   US. ~LIflCT COURT\n                           FOR THE EASTERN DISTRICT OF TEXAS                             ~     ri\n                                                                                               ~     ~.\n                                                                                                       ~.\n                                                                                                            L\n                                                                                                            ~\n\n                                     LUFKIN DIVISION\n                                                                                TX   EsT\u2019~     \u2014    LUF~U~\nSAMSUNG ELECTRONICS CO., LTD.,                          \u00a7\n                                                        \u00a7\n                                    Plaintiff           \u00a7\n                                    Counterdefendant,   \u00a7\n                                                        \u00a7\nV.                                                      \u00a7   CIVIL ACTION NO.9:02cv58\n                                                        \u00a7   Judge John Hannah, Jr.\nSANDISK CORPORATION,                                    \u00a7\n                                                        \u00a7\n                                    Defendant           \u00a7\n                                    Counterclaimant.    \u00a7\n         PLAINTIFF SAMSUNG ELECTRONICS CO., LTD.\u2019S ANSWER TO\n                 DEFENDANT SANDISK\u2019S COUNTERCLAIMS\n\n         Plaintiff Samsung Electronics Co. Ltd. (\u201cSanisung\u201d) previously filed a Motion for\n\nMore Definite Statement on May 16, 2002 as to Defendant SanDisk Corp.\u2019s (\u201cSanDisk\u201d)\n\nCounterclaims. Since that time, SanDisk has answered and supplemented its\n\ninterrogatory answers, and there has been a hearing and additional briefing and a\n\nmemorandum opinion on the contract issues. Samsung no longer wishes to press for a\n\nmore definite statement, but rather to expedite this case will not re-urge the motion after\n\ntransfer, but instead files this answer to SanDisk\u2019s April 26, 2002 Amended\n\nCounterclaims (which Amended Counterclaims begin at Paragraph 71 of SanDisk\u2019s\n\nAnswer to the Amended Complaint and Amended Counterclaims):\n\n          1. As to Paragraph 71, although Samsung denies that its patent infringement\n\n              claims arise under the 1997 Settlement Patent Cross License Agreement (the\n\n              \u201c1997 Agreement\u201d) between Samsung and SanDisk, Samsung admits the\n\n              Court hasjurisdiction over all counterclaims, otherwise denied.\n\n\n\n\nHOl :\\255235M11\\5GXVO1 !.DOC\\7186S.0008\n     Case 9:02~cv~~0005fi~JH\n                          Document 135                    F~ed\n                                                             07/30/2002         Page 2 of 8\n\n\n\n         2. As to Paragraph 72, although Samsung denies that its patent infringement\n\n              claims arise under the 1997 Settlement Patent Cross License Agreement (the\n\n              \u201c1997 Agreement\u201d) between Samsung and SanDisk, Samsung believes that\n\n              venue is proper in the Eastern District of Texas, continues to object to the\n\n              Court\u2019s July 19, 2002 Order Transferring Venue, and admits venue is\n\n              permissible in the Northern District of California.\n\n         3. As to Paragraph 73, admitted.\n\n         4. As to Paragraph 74, Samsung admits there is a controversy between Samsung\n\n              and SanDisk over the \u2018563 patent, but denies the remaining allegations\n\n              herein.\n\n         5. As to Paragraph 75, admitted.\n\n         6. As to Paragraph 76, Samsung admits there is a controversy between Samsung\n\n              and SanDisk over the \u2018889 patent, but denies the remaining allegations\n\n              herein.\n\n         7. As to Paragraph 77, admitted.\n\n         8. As to Paragraph 78, Samsung admits there is a controversy between Samsung\n\n              and SanDisk over the \u2018341 patent, but denies the remaining allegations\n\n              herein.\n\n         9. As to Paragraph 79, admitted.\n\n         10. As to Paragraph 80, Samsung has dismissed all claims regarding the \u2018309\n\n              patent as to SanDisk only with prejudice, and accordingly, denies the\n\n              allegations of this paragraph.\n\n         11. As to Paragraph 81, admitted.\n\n\n\n\nHO1:\\255235\u2019ffl\u20195GXVO1!.DOC\\71868.0008          2\n  Case 9:02~cv-0005a~JH Document 135                   F~ed\n                                                          07/30/2002          Page 3 of 8\n\n\n\n        12. As to Paragraph 82, admitted.\n\n        13. As to Paragraph 83, admitted.\n\n        14. As to Paragraph 84, admitted.\n\n        15. As to Paragraph 85, admitted.\n\n        16. As to Paragraph 86, Samsung admits that the 1997 Agreement was entered\n\n             into by Samsung and SanDisk on August 14, 1997 and that the 1997\n\n             Agreement contains certain licenses and speaks for itself. Samsung, however,\n\n             denies that the 1997 Agreement provides SanDisk any license for any patent\n\n             rights forNAND Flash Memory Products or Technology.\n\n        17. As to Paragraph 87, Samsung admits that the 1997 Agreement is governed by\n\n             the laws of California, and admits that the 1997 Agreement contains a\n\n             provision consenting to jurisdiction and waiving objections to venue in the\n\n             Northern District of California, otherwise denied.\n\n         18. As to Paragraph 88, admitted.\n\n         19. As to Paragraph 89, Samsung admits that on March 5, 2002, Samsung filed\n\n             this lawsuit in the Eastern District of Texas, Lufldn Division on the \u2018563,\n\n             \u2018341,\u2019889 and \u2018309 patents alleging that NAND Flash Memory Products sold\n\n             by SanDisk infringed those patents, otherwise denied.\n\n         20. As to Paragraph 90, denied.\n\n         21. As to Paragraph 91, no response is required other than the responses above to\n\n             paragraphs 7 1-90, which are incorporated by reference.\n\n         22. As to Paragraph 92, admitted.\n\n\n\n\nHO! :\\255235\u2019O1\\5GXVOI !.DOC\\71868.0008         3\n    Case 9:02~cv~~0005~JH\n                       Document 135                     F~ed\n                                                           07/30/2002          Paqe 4 of 8\n\n\n\n         23. As to Paragraph 93, Sanisung is without sufficient information to admit or\n\n              deny the allegations in this paragraph.\n\n         24. As to Paragraph 94, Samsung admits that it filed this lawsuit on March 5,\n\n              2002 in the Eastern District of Texas, Lufkin Division, otherwise denied.\n\n         25. As to Paragraph 95, demed.\n\n         26. As to Paragraph 96, no further answer is required except to the extent ofthe\n\n              answers to Paragraphs 7 1-95, which are incorporated herein by reference.\n\n         27. As to Paragraph 97, admitted.\n\n         28. As to Paragraph 98, Samsung admits that its Original Complaint and its First\n\n              Amended Complaint are limited to NAND Flash Memory Products, otherwise\n\n              denied.\n\n         29. As to Paragraph 99, Samsung admits that the 1997 Agreement contains certain\n\n              licenses and speaks for itself Samsung admits that SanDisk is not licensed\n\n              under the 1997 Agreement to \u201cSamsung\u2019s NAND Flash Memory\n\n              Technology\u201d, among other rights withheld or excluded by Samsung under the\n\n              1997 Agreement.\n\n         30. As to Paragraph 100, denied.\n\n         31. As to Paragraph 101, Samsung admits there is a controversy between\n\n              Samsung and SanDisk, otherwise denied.\n\n         32. As to the Prayer for Relief, Samsung denies that SariDisk is entitled to any\n\n              relief on any of its counterclaims.\n\n\n\n\nHO1 :\\255235\u2019D1\u20195GXVOI !.DOC\\71868.0008             4\n     Case 9:02~cv-0005&~JH Document 135                  F~ed07/30/2002         Page 5 of 8\n\n\n\n         33. As to the demand for Jury Trial, Samsung denies that SanDisk is entitled to a\n\n              jury trial on its declaratoryjudgment claims based on any of the patents-in-\n\n              suit.\n\n         34. By way of affirmative defense, Sanisung pleads as to the SanDisk\n\n              Counterclaim for a Declaratory Judgment on the \u2018309 patent that this claim\n\n              was dismissed with prejudice by SanDisk and is barred.\n\n         35. By way of affirmative defense, Samsung pleads as to the SanDisk\n\n              counterclaims for breach ofthe 1997 Agreement for filing a lawsuit in a venue\n\n              other than the Northern District of California, that SanDisk waived that claim\n\n              by filing its own counterclaim in the Eastern District of Texas under the 1997\n\n              Agreement.\n\n         36. By way of affirmative defense, Samsung pleads as to the SanDisk\n\n              counterclaims for breach of the 1997 Agreement that SanDisk has failed to\n\n              fulfill conditions precedent to filing ofthose claims in not completing the\n\n              dispute resolution procedures necessary before filing suit for breach as set\n\n              forth in Section 9.9 of the 1997 Agreement.\n\n\n\n\nHOl :\\255235\u2019O1\\5GXVO1 .DOC\\7! 868.0008         5\n     Case 9:02~cv~0005a-JH Document 135           F~ed\n                                                     07/30/2002      Page 6 of 8\n\n\n\nDated: July 29, 2002\n\n                                          Respectfully submitted,\n\n\n\n                                          ~\n                                          George Chandler\n                                                 ~.\n\n\n                                          Attorney-In-Charge for Plaintiff\n                                          Samsung Electronics Co., Ltd.\n                                          State Bar No. 04094000\n                                          The Law Offices of George Chandler\n                                          207 E. Frank Poland Professional Building\n                                          P.O. Box 340\n                                          Lufldn, Texas 75902\n                                          Telephone: (936) 632-7778\n                                          Facsimile: (936) 632-1304\n                                          E-mail: gchandler~chandler1awoffices.com\n\n\n\n\nHO! :\\255235\u2019OI\\5GXVO1 .DOC\\7 1868.0008   6\n     Case 9:02~cv~~0005a-JH\n                          Document 135          F~ed\n                                                   07/30/2002   Page 7 of 8\n\n\n\nOF COUNSEL:\n\nTHE LAW OFFICES OF CLAYTON E. DARK, JR.\nClayton E. Dark, Jr.\nState Bar No. 05384500\nP.O. Box 2207\nLufkin,, Texas 75902\nTelephone: (936) 637-1733\nFacsimile: (936) 637-2897\n\nTHE RICHARDS LAW FIRM\nR.W. (\u201cRicky\u201d) Richards\nState Bar No. 16854100\nP.O. Box 1309\nJacksonvifie, Texas 75766\nTelephone: (903) 586-2544\nFacsimile: (903) 586-6529\n\nTHE LAW OFFICES OF CLAUDE E. WELCH\nClaude E. Welch\nState Bar No. 21120500\nP.O. Box 1574\nLufkin, Texas 75902\nTelephone: (936) 639-3311\nFacsimile: (936) 639-3049\n\nWElL, GOTSHAL & MANGES LLP\nDavid J. Healey\nState Bar No. 09327980\nAnita E. Kadala\nState Bar No. 00786007\n700 Louisiana, Suite 1600\nHouston, Texas 77002\nTelephone: (713) 546-5000\nFacsimile: (713) 224-9511\nE-mail: david.healey@weil.com\nE-mail: anita.kadala@weil.com\n\n\n\n\nHO! :\\255235\u2019ffl\\SGXVO 1 \u2018.DOC\\71868.0008   7\n    Case 9:02~cv-0005a~JH Document 135              F~ed07/30/2002       Page 8 of 8\n\n\n\n\n                                   CERTIFICATE OF SERVICE\n\n                A true and correct copy of the above and foregoing Answer was delivered,\npursuant to the Federal Rules of Civil Procedure upon all counsel of record on the\n                                                                                 _____\n\n\nday of July, 2002.\n\n\n\n\nHOI :\\255235\u2019~1\\5GXV01.DOC\\71868.0008        8\n"
        }
      ], 
      "filed_on": "2002-07-30T00:00:00", 
      "id": 14070, 
      "nice_text": "Answer to SanDisk's Counterclaims by Samsung Electronics (djh) (Entered: 07/30/2002)", 
      "number": 135, 
      "tags": [
        {
          "@id": "http://lexmachina.com/vocab/tags#15", 
          "id": 15, 
          "name": "Answer", 
          "visible": 1
        }, 
        {
          "@id": "http://lexmachina.com/vocab/tags#74", 
          "id": 74, 
          "name": "Pleading", 
          "visible": 1
        }
      ]
    }, 
    {
      "@id": "http://lexmachina.com/data/docket-entry/14072", 
      "documents": [], 
      "filed_on": "2002-08-12T00:00:00", 
      "id": 14072, 
      "nice_text": "Received acknowledgement from Northern District of California of receipt of original file (#C 02 3806 JL) (djh) (Entered: 08/12/2002)", 
      "number": null, 
      "tags": []
    }, 
    {
      "@id": "http://lexmachina.com/data/docket-entry/14073", 
      "documents": [], 
      "filed_on": "2003-06-10T00:00:00", 
      "id": 14073, 
      "nice_text": "Shipped to FRC on 06/02/03 Accession number: 021-03-0211, Location 1-42-202-3-4 Box 30 of 32 (djh) (Entered: 06/10/2003)", 
      "number": null, 
      "tags": []
    }, 
    {
      "@id": "http://lexmachina.com/data/docket-entry/13971", 
      "documents": [
        {
          "@id": "http://lexmachina.com/data/documents/4000078554", 
          "id": 4000078554, 
          "text": "DEFENDANT SANDISK CORPORATION'S\nANSWER To AMENDED COMPLAINT AND\nAMENDED COUNTERCLAIMS\n\n\ufffd\n\ufffd\n\ufffd\n\ufffd\n\ufffd\n\ufffd\n\ufffd\n\ufffd\n\ufffd\n\ufffd\n\ufffd\n\ufffd\n\ufffd\n\ufffd\n\ufffd\n\ufffd\n\ufffd\n\ufffd\n\ufffd\n\ufffd\n~n\n~:_\n\nIN THE UNITED STATES DISTRICT COURT\nFOR THE EASTERN DISTRICT OF TEXAS\nLUFKIN DIVISION\n\n\nSAMSUNG ELECTRONICS CO., LTD.,\n\nPlaintiff,\n\nV.\n\nSANDISK CORPORATION,\n\nDefendant\n\n\nCIVIL ACTION NO. 9:02cv58\nJudge Hannah\nJURY\n\n\nSANDISK CORPORATION,\n\nCounterclaimant,\n\nV.\n\nSAMSUNG ELECTRONICS CO., LTD.,\n\nCounterdefendant.\n\nDEFENDANT SANDISK CORPORATION'S\nANSWER TO AMENDED COMPLAINT AND AMENDED COUNTERCLAIMS\n\n\nDefendant SanDisk Corporation (\"SanDisk\") answers the Complaint of Samsung\n\nElectronics, Co., Ltd. (\"Samsung\") as follows:\n. SanDisk lacks sufficient knowledge or information to form a belief as to the truth\n\nof the averments contained in Paragraph 1.\n. SanDisk admits that it is organized under the laws of Delaware and that its\n\nprincipal place of business is in Sunnyvale, California. SanDisk also admits that it has appeared\n\nin this action. SanDisk denies the remaining averments contained in Paragraph 2.\n\nPage 1\n. In answer to Paragraph 3 of the Complaint, SanDisk states as follows: SanDisk\n\nadmits that this Court has subject matter jurisdiction, but denies that SanDisk infringes\n\nSamsung's patents.\n. SanDisk denies the averments contained in Paragraph 4 of the Complaint.\n. SanDisk lacks sufficient knowledge or information to form a belief as to the truth\n\nof the averments contained in Paragraph 5.\n. In answer to Paragraph 6 of the Complaint, SanDisk states as follows: SanDisk\n\nadmits that NAND flash memory products can be removable memory cards that can be found in\n\ndigital cameras, digital music players, digital camcorders, handheld PCs, eBooks, and newer\n\ncellular phone technology, as well as other emerging products but denies the remaining\n\naverments of Paragraph 6.\n. In answer to Paragraph 7 of the Complaint, SanDisk states as follows: SanDisk\n\nadmits that it manufactures and supplies NAND flash memory cards in consumer, original\n\nequipment manufacturers (\"OEMs\"), and industrial markets. SanDisk also admits that one of its\n\nproducts is CompactFlashTM and that some of its CompactFlashTM products include NAND flash\n\nmemory, but denies that its CompactFlashTM products or any other product distributed by\n\nSanDisk, infringe any Samsung patents.\n. SanDisk admits that it sells NAND flash memory products through\n\nintermediaries, including wholesalers, distributors, value-added resellers, and retailers. SanDisk\n\nadmits that the retailers that sell its NAND flash memory cards are located throughout the United\n\nStates and that some of these retailers may reside in the Eastern District of Texas. SanDisk\n\nadmits that retailers that sell its NAND flash memory cards may include Circuit City, K-Mart,\n\nOffice Depot, Target, Sears, Office Max, Staples, Eckerd drug stores, and Walgreen. SanDisk\n\ndenies the remaining averments contained in paragraph 8.\nDEFENDANT SANDISK CoRPoRATIoN's 2 ::ODMA\\PCDOCS\\TYLEROI\\I 3 1370\\1\nANSWER To AMENDED COMPLAINT AND\nAMENDED COUNTERCLAIMS\n. SanDisk admits that it has sold NAND flash memory cards to OEMs, which may\n\ninclude Cannon, Hewlett-Packard, Fujitsu, Motorola, Kodak, Panasonic, and Polaroid. SanDisk\n\nadmits that it sells NAND flash memory cards to private label partners that re-brand the SanDisk\n\nproducts under a different trade name. SanDisk lacks sufficient knowledge or information to\n\nform a belief as to the truth of the remaining averments in paragraph 9.\n. In answer to Paragraph 10 of the Complaint, SanDisk states as follows: SanDisk\n\nadmits that it markets, promotes, sells and offers for sale certain types of flash memory products\n\nin Texas. SanDisk admits that it uses distributors and manufacturer representatives to sell its\n\nflash memory products in Texas. However, SanDisk specifically denies that it has a direct sales\n\noffice in Texas, and denies the remaining allegations of paragraph 10.\n. In answer to Paragraph 11 of the Complaint, SanDisk states as follows: SanDisk\n\nadmits that it sells its flash memory products on Amazon.com's website. SanDisk lacks\n\nsufficient knowledge or information to form a belief as to the truth of the other averments\n\ncontained in Paragraph 11.\n. In answer to Paragraph 12 of the Complaint, SanDisk states as follows: SanDisk\n\nadmits that it markets, promotes, sells, offers for sale, or leases its flash memory products\n\nthroughout the United States, possibly including the Lufkin Division. However, SanDisk denies\n\nthat it \"directly\" markets, promotes, sells, offers for sale, or lease its NAND flash memory\n\nproducts in the Lulkin Division. SanDisk admits that it employs wholesalers, distributors, value-\n\nadded resellers and retailers to market, promote, sell, offer for sale, or lease its flash memory\n\ncards. Sanflisk lacks sufficient knowledge or information to form a belief as to the truth of the\n\nremaining averments contained in Paragraph 12.\n\n\nDEFENDANT SANDISK CORPORATION'S 3 ::ODMA\\PCDOCS\\TYLERO1\\13 1370\\1\nANSWER To AMENDED COMPLAINT AND\nAMENDED COUNTERCLAIMS\n\nincluding the CompactFlashTM product line. SanDisk also admits consumers can obtain warranty\n\ninformation and warranty registration material for SanDisk products at retail outlets in the United\n\nStates that sell SanDisk flash memory products, including the CompactFlashTM product line.\n\nSanDisk also admits that warranty information and warranty registration materials for SanDisk\n\nflash memory products are included within the package of each retail SanDisk flash memory\n\nproduct sold. SanDisk also admits that warranty information and warranty registration materials\n\nfor SanDisk flash memory products can be obtained from its website. SanDisk lacks sufficient\n\nknowledge or information to form a belief as to the truth of the remaining averments contained in\n\nParagraph 20.\n. SanDisk admits that it offers a five-year warranty on some of its flash memory\n\nproducts, including products in the CompactFlashTM product line. SanDisk admits that the\n\nwarranty for some of its products includes the language, SanDisk \"will repair or replace a flash\n\nmemory card free of charge if it ever fails within 5 years from the date of purchase, subject to the\n\nconditions set forth below,\" and \"SanDisk will inspect the product and at its option, repair or\n\nreplace the product. SanDisk will ship out a product with equal or greater capacity.\" SanDisk\n\ndenies the remaining averments in paragraph 21.\n. SanDisk admits that the packaging containing its flash memory cards includes\n\nwarranty registration materials. SanDisk admits that the warranty registration material includes a\n\nreference to the website TJRL for a SanDisk website. SanDisk denies the remaining averments in\n\nparagraph 22.\n. In answer to Paragraph 23 of the Complaint, SanDisk states as follows: SanDisk\n\nadmits that any consumer for its products who has access to the Internet has access to SanDisk's\n\nwebsite, which is located at http://www.sandisk.comlmain.htm. SanDisk lacks sufficient\n\n\nDEFENDANT SANDISK CORPORATION'S 6 : :ODMA\\PCDOCS\\TYLEROI\\13 1370\\1\nANSWER To AMENDED COMPLAINT AND\nAMENDED COUNTERCLAIMS\n\nknowledge or information to form a belief as to the truth of the remaining averments contained in\n\nParagraph 23.\n. In answer to Paragraph 24 of the Complaint, SanDisk states as follows: SanDisk\n\nadmits that it has a website, run by a distributor, that allows any consumer with access to the\n\nInternet to shop for, order and purchase a full range of SanDisk's flash memory products.\n\nSanDisk also admits that no consumer with access to the Internet, including those located in the\n\nLufkin Division, is prevented from accessing its website. SanDisk lacks sufficient knowledge or\n\ninformation to form a belief as to the truth of the remaining averments contained in\n\nParagraph 24.\n. SanDisk admits that it has shipped flash memory products, including products\n\nfrom the CompactFlashTM product line, purchased through SanDisk's website, to consumers\n\nresiding in the Lufkin Division. SanDisk lacks sufficient knowledge or information to form a\n\nbelief as to the truth of the remaining averments contained in Paragraph 25.\n. SanDisk admits that its website, run by a distributor, provides warranty\n\ninformation related to SanDisk flash memory cards. SanDisk admits that no consumer with\n\naccess to the Internet, including those located in the Lufkin Division, is prevented from accessing\n\nwarranty information. SanDisk denies the remaining averments contained in paragraph 26.\n. SanDisk admits that its website, run by a distributor, allows consumers to register\n\nwarranty information for its flash memory cards, including products from the CompactFlashTM\n\nproduct line. SanDisk admits that no consumer with access to the Internet, including those\n\nlocated in the Lufkin Division, is prevented from accessing this information. SanDisk admits\n\nthat registration of a flash memory card for warranty purposes requires an individual to complete\n\nseveral fields of inquiry and provide information to SanDisk, including the consumer's residence\n\n\nDEFENDANT SANDISK CORPORATION'S 7 ::ODMA\\PCDOCS\\TYLERO1\\13 1370\\1\nANSWER To AMENDED COMPLAINT AND\nAMENDED COUNTERCLAIMS\n\nand where the SanDisk product was purchased. SanDisk denies the remaining averments\n\ncontained in paragraph 27.\n. In answer to Paragraph 28 of the Complaint, SanDisk states as follows: SanDisk\n\nadmits that its website provides any consumer with access to the Internet, cash rebates and cash\n\nrebate information on its flash memory products, and does not restrict access to any consumers,\n\nincluding those residing in the Lufkin Division. SanDisk also admits that the content of the\n\nURLs set forth in Paragraph 28 include the information set forth in Paragraph 28. SanDisk lacks\n\nsufficient knowledge or information to form a belief as to the truth of the remaining averments\n\ncontained in Paragraph 28.\n. In answer to Paragraph 29 of the Complaint, SanDisk states as follows: SanDisk\n\nadmits that the website referred to in Paragraph 29 provides any consumer with access to the\n\nInternet the information necessary to contact technical support staff via e-mail or telephone with\n\nquestions regarding customer service or technical support relating to all of its products. SanDisk\n\nalso admits that no consumer with access to the Internet, including those located in the Lufkin\n\nDivision, is prevented from accessing this information.\n. In answer to Paragraph 30 of the Complaint, SanDisk states as follows: SanDisk\n\nadmits that the website located at the referenced URL includes the language, \"design products\n\nwhich use SanDisk cards, flash memory chips and other SanDisk technology,\" and does not\n\nrestrict any consumer with access to the Internet from accessing the website. SanDisk lacks\n\nsufficient knowledge or information to form a belief as to the truth of the remaining averments\n\ncontained in Paragraph 30.\n. In answer to Paragraph 31 of the Complaint, SanDisk states as follows: SanDisk\n\ndenies that consumers can download software upgrades for its flash memory cards. SanDisk\n\nadmits that it does not restrict or otherwise prevent individuals residing in the Lufkin Division\nDEFENDANT SANDISK CORPORATION'S 8 ;ODMA\\PCDOCSVFYLEROI\\1 3 1370\\l\nANSWER To AMENDED COMPLAINT AND\nAMENDED COUNTERCLAIMS\n\nfrom accessing the website run by SanDisk's distributor. The remaining portion of paragraph 31\n\nis ambiguous and, therefore, SanDisk does not possess sufficient information to respond to the\n\nremaining averments of the paragraph.\n. In answer to Paragraph 32 of the Complaint, SanDisk states as follows: SanDisk\n\nadmits that it allows any consumer with access to the Internet the option to enroll in the quarterly\n\nproduct e-mail list distributed by SanDisk. SanDisk also admits that no consumer with access to\n\nInternet is prevented from receiving this list if he or she chooses to.\n. Except as specifically admitted in the preceding paragraphs, SanDisk denies the\n\nallegations of Paragraph 33 of the Complaint.\n. SanDisk realleges and incorporates herein its responses to Paragraphs 1-33 of the\n\nComplaint.\n. In answer to Paragraph 35 of the Complaint, SanDisk states as follows: SanDisk\n\nadmits that Exhibit A to the Complaint appears to be a copy of United States Patent No.\n,473,563 (\"the `563 patent\") issued December 5, 1995 and assigned to Samsung Electronics,\n\nInc. SanDisk lacks sufficient knowledge or information to form a belief as to the truth of the\n\nremaining averments contained in Paragraph 35.\n. SanDisk denies the averments contained in Paragraph 36 of the Complaint.\n. SanDisk denies the averments contained in Paragraph 37 of the Complaint.\n. SanDisk denies the averments contained in Paragraph 38 of the Complaint.\n. SanDisk denies the averments contained in Paragraph 39 of the Complaint.\n. SanDisk realleges and incorporates herein its responses to Paragraphs 1-39 of the\n\nComplaint.\n. In answer to Paragraph 41 of the Complaint, SanDisk states as follows: SanDisk\n\nadmits that Exhibit B to the Complaint appears to be a copy of United States Patent No.\nDEFENDANT SANDISK CORPORATION'S 9 ::ODMA\\PCDOCS\\TYLERO 1\\13 I 370\\I\nANSWER To AMENDED COMPLAINT AND\nAMENDED COUNTERCLAIMS\n,514,889 (\"the `889 patent\") issued May 7, 1996 and assigned to Samsung Electronics, Inc.\n\nSanDisk lacks sufficient knowledge or information to form a belief as to the truth of the\n\nremaining averments contained in Paragraph 41.\n. SanDisk denies the averments contained in Paragraph 42 of the Complaint.\n. SanDisk denies the averments contained in Paragraph 43 of the Complaint.\n. SanDisk denies the averments contained in Paragraph 44 of the Complaint.\n. SanDisk denies the averments contained in Paragraph 45 of the Complaint.\n. SanDisk realleges and incorporates herein its responses to Paragraphs 1-45 of the\n\nComplaint.\n. In answer to Paragraph 47 of the Complaint, SanDisk states as follows: SanDisk\n\nadmits that Exhibit C to the Complaint appears to be a copy of United States Patent No.\n,546,341 (\"the `341 patent\") issued August 13, 1996 and assigned to Samsung Electronics, Inc.\n\nSanDisk lacks sufficient knowledge or information to form a belief as to the truth of the\n\nremaining averments contained in Paragraph 47.\n. SanDisk denies the averments contained in Paragraph 48 of the Complaint.\n. SanDisk denies the averments contained in Paragraph 49 of the Complaint.\n. SanDisk denies the averments contained in Paragraph 50 of the Complaint.\n. SanDisk denies the averments contained in Paragraph 51 of the Complaint.\n. SanDisk realleges and incorporates herein its responses to Paragraphs 1-51 of the\n\nComplaint.\n. In answer to Paragraph 53 of the Complaint, SanDisk states as follows: SanDisk\n\nadmits that Exhibit D to the Complaint appears to be a copy of United States Patent No.\n,642,309 (\"the `309 patent\") issued June 24, 1997 and assigned to Samsung Electronics, Inc.\n\n\nDEFENDANT SANDISK CORPORATION'S 10 ::ODMA\\PCDOCS\\TYLERO1\\13 1370\\I\nANSWER To AMENDED COMPLAINT AND\nAMENDED COUNTERCLAIMS\n\nSanDisk lacks sufficient knowledge or information to form a belief as to the truth of the\n\nremaining averments contained in Paragraph 53.\n. SanDisk denies the averments contained in Paragraph 54 of the Complaint.\n. SanDisk denies the averments contained in Paragraph 55 of the Complaint.\n. SanDisk denies the averments contained in Paragraph 56 of the Complaint.\n. SanDisk denies the averments contained in Paragraph 57 of the Complaint.\n. SanDisk realleges and incorporates herein its responses to Paragraphs 1-57 of the\n\nComplaint.\n. SanDisk denies the averments contained in Paragraph 59 of the Complaint.\n. SanDisk admits that Samsung has alleged that it is only seeking relief against\n\nSanDisk's NAND flash memory products.\n\nAFFIRMATIVE DEFENSES\n\nFIRST AFFIRMATIVE DEFENSE\n. As a first and separate affirmative defense, SanDisk alleges that it has not\n\ninfringed, directly or indirectly, literally or by the doctrine of equivalents, any valid claims of the\n\n`563, `889, `341 or `309 patents.\n\nSECOND AFFIRMATIVE DEFENSE\n. As a second and separate affirmative defense, SanDisk alleges that the `563, the\n\n`889, `341 or `309 patents are invalid under 35 U.S.C. \ufffd~ 102, 103 andlor 112.\n\nTHIRD AFFIRMATIVE DEFENSE\n. As a third and separate affirmative defense, SanDisk alleges that Samsung's claim\n\nis barred by the doctrine of estoppel.\n\n\nDEFENDANT SANDISK CORPORATION'S 11 ::ODMA\\PCDOCS\\TYLERO1\\1 3 1370\\1\nANSWER To AMENDED COMPLAINT AND\nAMENDED COUNTERCLAIMS\n\nFOURTH AFFIRMATIVE DEFENSE\n. As a fourth and separate affirmative defense, SanDisk alleges that Samsung has\n\nwaived the claim it asserts in this Action.\n\nFIFTH AFFIRMATIVE DEFENSE\n. As a fifth and separate affirmative defense, SanDisk alleges that Samsung's\n\nclaims are barred by its unclean hands.\n\nSIXTH AFFIRMATIVE DEFENSE\n. As a sixth and separate affirmative defense, SanDisk alleges that Samsung's\n\nclaims for patent infringement are barred in that SanDisk has license and/or sublicense rights\n\n(whether express or implied) to the `563, `889, `341 and `309 patents.\n\nSEVENTH AFFIRMATIVE DEFENSE\n. As a seventh and separate affirmative defense, SanDisk alleges that Samsung's\n\nclaims for patent infringement are barred by the doctrine of patent exhaustion.\n\nEIGHTH AFFIRMATIVE DEFENSE\n. As an eighth and separate affirmative defense, SanDisk alleges that Samsung has\n\nreleased any claim for infringement of the `563, `889,'341, and `309 patents.\n\nAMENDED COUNTERCLAIMS\n\nTHE PARTIES\n. SanDisk is a Delaware corporation with its principal place of business in\n\nSunnyvale, California.\n. On information and belief Samsung is a company duly organized under the laws\n\nof South Korea with its principal place of business located at 416 Maetan-3 Dong, Paldal-Gu,\n\nSuwon City, Kyungi-Do, Korea.\n\n\nDEFENDANT SANDISK CORPORATION'S 12 ::ODMA\\PCDOCS\\TYLERO1\\13 1370\\1\nANSWER To AMENDED COMPLAINT AND\nAMENDED COUNTERCLAIMS\n\nJURISDICTION AND VENUE\n. This Court has subject matter jurisdiction over SanDisk's patent counterclaims\n\n(First through Fourth) pursuant to 28 U.S.C. \ufffd~ 1338(a) and 2201, because those counterclaims\n\narise under the patent laws of the United States, 35 U.S.C. \ufffd 1, et seq. This Court has\n\njurisdiction over SanDisk' s counterclaims for breach of contract and for a declaration of rights\n\nand obligations under a contract (Fifth and Sixth Counterclaims) pursuant to 28 U.S.C. \ufffd~ 1367\n\nand 2201, because those claims arise from the same occurrences or transactions as Samsung's\n\npatent claims such that they form part of the same case or controversy under Article III of the\n\nUnited States Constitution.\n. As alleged above in Paragraph 4, SanDisk contends that venue is improper in this\n\nDistrict for Samsung's claims of patent infringement against SanDisk. Accordingly, on April 9,\n, SanDisk filed a motion for transfer of venue to the Northern District of California pursuant\n\nto 28 U.S.C. \ufffd 1404(a). Nevertheless, and in the event that the Court denies SanDisk's motion\n\nfor transfer of venue (currently set for hearing on August 26, 2002), venue is proper for\n\nSanDisk's counterclaims because they are unquestionably compulsory. In that event, venue is\n\nproper in this District for SanDisk's declaratory judgment patent counterclaims (First through\n\nFourth) pursuant to 28 U.S.C. \ufffd 1391(b) and 1400(b). SanDisk's contract counterclaims (Fifth\n\nand Sixth) are proper in this District under 28 U.S.C. 1391(a)(2), in that a substantial part of the\n\nevents giving rise to those counterclaims occurred in this District through Samsung's improper\n\nfiling of a patent infringement action in this District in breach of its contractual obligations to\n\nSanDisk.\n\n\nDEFENDANT SANDISK CORPORATION'S 13 ::ODMA\\PCDOCS\\TYLEROI\\I 3 1370\\1\nANSWER To AMENDED COMPLAINT AND\nAMENDED COUNTERCLAIMS\n\nFIRST COUNTERCLAIM\nDeclaration of Noninfringement and Invalidity of the `563 Patent\n. Samsung claims that it is the owner of the `563 patent; that the patent is valid; and\n\nthat SanDisk infringes the patent.\n. SanDisk contends that the `563 patent is not valid and/or is not infringed.\n\nAccordingly, a valid and justiciable controversy has arisen and exists between Samsung and\n\nSanDisk. SanDisk desires a judicial determination - by jury trial - and declaration of the\n\nrespective rights and duties of the parties herein. Such a determination and declaration is\n\nnecessary and appropriate at this time in order that the parties may ascertain their respective\n\nrights and duties.\n\nSECOND COUNTERCLAIM\nDeclaration of Noninfringement and Invalidity of the `889 Patent\n. Samsung claims that it is the owner of the `889 patent; that the patent is valid; and\n\nthat SanDisk infringes the patent.\n. SanDisk contends that the `889 patent is not valid and/or is not infringed.\n\nAccordingly, a valid and justiciable controversy has arisen and exists between Samsung and\n\nSanDisk. SanDisk desires a judicial determination - by jury trial - and declaration of the\n\nrespective rights and duties of the parties herein. Such a determination and declaration is\n\nnecessary and appropriate at this time in order that the parties may ascertain their respective\n\nrights and duties.\n\nTHIRD COUNTERCLAIM\nDeclaration of Noninfringement and Invalidity of the `341 Patent\n. Samsung claims that it is the owner of the `341 patent; that the patent is valid; and\n\nthat SanDisk infringes the patent.\n\n\nDEFENDANT SANDISK CORPORATION'S 14 ::ODMA\\PCDOCS\\TYLEROI\\13 I 370\\1\nANSWER To AMENDED COMPLAINT AND\nAMENDED COUNTERCLAIMS\n. SanDisk contends that the `341 patent is not valid and/or is not infringed.\n\nAccordingly, a valid and justiciable controversy has arisen and exists between Samsung and\n\nSanDisk. SanDisk desires a judicial determination - by jury trial - and declaration of the\n\nrespective rights and duties of the parties herein. Such a determination and declaration is\n\nnecessary and appropriate at this time in order that the parties may ascertain their respective\n\nrights and duties.\n\nFOURTH COUNTERCLAIM\nDeclaration of Noninfringement and Invalidity of the `309 Patent\n. Samsung claims that it is the owner of the `309 patent; that the patent is valid; and\n\nthat SanDisk infringes the patent.\n. SanDisk contends that the `309 patent is not valid and/or is not infringed.\n\nAccordingly, a valid and justiciable controversy has arisen and exists between Samsung and\n\nSanDisk. SanDisk desires a judicial determination - by jury trial - and declaration of the\n\nrespective rights and duties of the parties herein. Such a determination and declaration is\n\nnecessary and appropriate at this time in order that the parties may ascertain their respective\n\nrights and duties.\n\nFIFTH COUNTERCLAIM\nBreach of Contract\n. On October 3, 1995, Samsung sued SanDisk in the Northern District of\n\nCalifornia, asserting that SaniDisk's products infringed two Samsung patents, and seeking a\n\ndeclaration of invalidity and noninfringement as to five SanDisk patents, including SanDisk's\n\nU.S. Patent Nos. 5,172,338 and 5,418,752 (\"the `338 patent\" and \"the `752 patent,\"\n\nrespectively).\n. In January 1996, SanDisk sued Samsung in the United States International Trade\n\nCommission (\"ITC\") alleging that Samsung infringed the `338 and `752 patents.\nDEFENDANT SANDISK CORPORATION'S 15 :ODMA\\PCDOCS\\TYLEROI\\13 1370\\I\nANSWER To AMENDED COMPLAINT AND\nAMENDED COUNTERCLAIMS\n. The litigation in the Northern District of California was stayed pending resolution\n\nof the ITC litigation.\n. On April 15, 1997, the ITC affirmed an administrative law judge's finding that\n\ncertain Samsung flash memory devices infringed the `338 and `752 patents.\n. Following the ITC ruling in SanDisk's favor, the parties negotiated a Settlement\n\nand Patent Cross License Agreement (the \"Agreement\"). The Agreement resolved both the ITC\n\ncase and the district court case filed by Samsung in the Northern District of California.\n. The Agreement, executed on August 14, 1997, provided SanDisk with a license to\n\nmanufacture various types of flash memory products under Samsung's patents. In particular,\n\nSanDisk received a license under \"Samsung Patent Claims\" for all flash memory products except\n\nthose that use \"Samsung Patented NAND Flash Memory Technology.\" In other words, the only\n\nSanDisk flash memory products not licensed under the Agreement are those that infringe certain\n\nSamsung NAND patents.\n. The parties agreed that the Agreement would be governed by the laws of the State\n\nof California, and agreed to jurisdiction and venue in the Northern District of California for any\n\naction brought pursuant to the Agreement.\n. The Agreement has not been modified, rescinded or revoked by the parties since\n\nits effective date of August 14, 1997.\n. On March 5, 2002, Samsung filed suit against SanDisk in the Eastern District of\n\nTexas, Lufkin Division, alleging that certain flash memory products made, used, sold, offered for\n\nsale, leased or imported by SanDisk infringe four United States patents assigned to Samsung. At\n\nleast two of Samsung's asserted patents - the `309 and `889 patents - are not specific to NAND,\n\nand thus cannot even be included in the definition of \"Samsung Patented NAND Flash Memory\n\nTechnology.\"\nDEFENDANT SANDISK CORPORATION'S 16 ::ODMA\\PCDOCS\\TYLERQI\\I 3 1370\\1\nANSWER To AMENDED COMPLAINT AND\nAMENDED COUNTERCLAIMS\n. For the first time, Samsung's First Amended Complaint attempted to exclude\n\nSanDisk's non-NAND flash memory products from the scope of the Complaint.\n. The Agreement excludes from SanDisk's license any SanDisk flash memory\n\nproducts that use \"Samsung Patented NAND Flash Memory Technology.\"\n. The accused SanDisk NAND flash memory products are not covered by\n\n\"Samsung Patented NAND Flash Memory Technology\" and, as a result, are licensed under the\n\nAgreement.\n. Accordingly, a valid and justiciable controversy has arisen and exists between\n\nSamsung and SanDisk. SanDisk desires a judicial determination and declaration that the\n\naccused SanDisk NAND flash memory products are licensed under the Agreement.\n\nPRAYER FOR RELIEF\n\nWHEREFORE, SanDisk requests that the Court enter judgment in their favor and against\n\nSamsung as follows:\n\n(a) Denying the relief requested by Samsung's Complaint;\n\n(b) For a declaration that the `563, `889, `341 and `309 patents are invalid and not\n\ninfringed by SanDisk;\n\n(c) For a declaration that SanDisk's rights under the Settlement and Patent Cross\n\nLicense Agreement between SanDisk and Samsung dated August 14, 1997 are valid and\n\nsubsisting;\n\n(d) For a declaration that Samsung has breached the express terms of the Settlement\n\nand Patent Cross License Agreement between SanDisk and Samsung dated August 14, 1997;\n\n(e) For a declaration that the accused SanDisk NAND flash memory products are\n\nlicensed under the Settlement and Patent Cross License Agreement between SanDisk and\n\nSamsung dated August 14, 1997;\n\n\nDEFENDANT SANDISK CORPORATION'S 18 ::ODMA\\PCDOCS\\TYLERO1\\13 I 370\\I\nANSWER To AMENDED COMPLAINT AND\nAMENDED COUNTERCLAIMS\n\n(f) A preliminary and permanent injunction enjoining Samsung, its officers, agents,\n\nservants, employees, attorneys and those persons on active concert or participation with any of\n\nthem from any further breach of either the express or implied terms of the Settlement and Patent\n\nCross License Agreement between SanDisk and Samsung dated August 14, 1997;\n\n(g) A dismissal of Samsung's claims based on Samsung's improper selection of\n\nvenue pursuant to the express terms of the Settlement and Patent Cross License Agreement\n\nbetween SanDisk and Samsung dated August 14, 1997;\n\n(h) An award to SanDisk of damages in an amount adequate to compensate SanDisk\n\nfor any and all damages resulting from Samsung's breach of the express and/or implied terms of\n\nthe Settlement and Patent Cross License Agreement between SanDisk and Samsung dated\n\nAugust 14, 1997, and interest on that amount;\n\n(i) An award to SanDisk of its attorney fees and costs; and\n\n(j) Such other relief as the Court deems proper.\n\nJURY DEMAND\n\nSanDisk demands a trial by jury as to all issues so triable.\n\n\nDated: April 26, 2002 Respe tfully sub itted,\n\n\nTracy Cra ford 7/\nAttorney-In-Charg~for Defendant\nState Bar No. 05024000\nEric H. Findlay\nState Bar No. 00789886\nRAMEY & FLOCK, P.C.\nB. Ferguson Street\nFirst Place\nTyler, TX 75702\nTelephone: (903) 597-3301\nFacsimile: (903) 597-2413\n\nDEFENDANT SANDISK CORPORATION'S 19 ::ODMA\\PCDOCS\\TYLEROI\\13 1370\\1\nANSWER To AMENDED COMPLAINT AND\nAMENDED COUNTERCLAIMS\n\nOF COUNSEL:\nMichael A. Ladra\nJames C. Otteson\nJames C. Yoon\nWILSON SONSINI GOODRICH & ROSATI\nProfessional Corporation\nPage Mill Road\nPalo Alto, CA 94304-1050\nTelephone: (650) 493-9300\nFacsimile: (650) 565-5100\n\n\nDEFENDANT SANDISK CORPORATION'S 20 ::ODMA\\PCDOCS\\TYLEROI\\I 3 1370\\1\nANSWER To AMENDED COMPLAINT AND\nAMENDED COUNTERCLAIMS\n\nCERTIFICATE OF SERVICE\n\nI hereby certify that on April 26, 2002, copies of the foregoing DEFENDANT\nSANDISK CORPORATION'S ANSWER TO AMENDED COMPLAINT AND\nAMENDED COUNTERCLAIMS were served upon the following parties as indicated:\n\nGeorge E. Chandler, Esq.\nTHE LAW OFFICES OF GEORGE CHANDLER\nE. Frank Poland Professional Building\nPost Office Box 340\nLufkin, Texas 75902\nBus: (936) 632-7778\nFax: (936)632-1304\n\n\nClayton B. Dark, Jr., Bsq.\nTHE LAW OFFICES OF CLAYTON E. DARK JR.\nPost Office Box 2207\nLufkin, Texas 75902\nBus: (936) 637-1733\nFax: (936) 637-2897\n\n\nR. W. (\"Ricky\") Richards, Esq.\nTHE RICHARDS LAW FIRM\nPost Office Box 1309\nJacksonville, Texas 75766\nBus: (903) 586-2544\nFax: (903) 586-6529\n\nVia First Class Mail\nVia Hand Delivery\nVia Overnight Courier\nVia Facsimile\n\n\n( /) Via First Class Mail\n( ) Via Hand Delivery\n( ) Via Overnight Courier\n( .v) Via Facsimile\n\n\n( ~. ) Via First Class Mail\n( ) Via Hand Delivery\n( ) Via Overnight Courier\n( ~.-2J Via Facsimile\n\nClaude E. Welch, Bsq.\nTHE LAW OFFICES OF CLAUDE B. WELCH\nPost Office Box 1574\nLufkin, Texas 75902\nBus: (936) 639-3311\nFax: (936) 639-3049\n\n\nDEFENDANT SANDISK CORPORATION'S\nANSWER To AMENDED COMPLAINT AND\nAMENDED COUNTERCLAIMS\n( 4 Via First Class Mail\n( ) Via Hand Delivery\n( ) ViaOvernightCourier\n( .v~) Via Facsimile\n\n\n::ODMA\\PCDOCS\\TYLERO1\\13 1370\\1\n\n(Z)\n( )\n( )\n(/)\n\nDavid J. Healey, Bsq.\nAnita E. Kadala, Esq.\nWElL, GOTSHAL & MANAGS LLP\nLouisiana, Suite 1600\nHouston, Texas 77002\nBus: (713) 546-5000\nFax: (713) 224-9511\n\n\nDEFENDANT SANDISK CORPORATION'S\nANSWER TO AMENDED COMPLAINT AND\nAMENDED COUNTERCLAIMS\n( u-') Via First Class Mail\n( ) Via Hand Delivery\n( ) Via Overnight Courier\n( .,-) Via Facsimile\n\n\nJIE~%2\nCY~RAWFO~\n\n\n::ODMA\\PCDOCS\\TYLERO1\\13 1370\\I\n\n"
        }
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      "filed_on": "2002-04-26T00:00:00", 
      "id": 13971, 
      "nice_text": "(Amended) Counterclaim by Samsung Electronics against Sandisk Corporation (fnt) (Entered: 04/26/2002)", 
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      "id": 13930, 
      "nice_text": "Motion by Sandisk Corporation for Julie M. Holloway to appear pro hac vice (djh) (Entered: 03/22/2002)", 
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      "id": 13926, 
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    {
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    }, 
    {
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    {
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      "nice_text": "Unopposed MOTION by Samsung Electronics for leave to file 1st amended complaint (djh) (Entered: 04/02/2002)", 
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      "tags": []
    }, 
    {
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    }, 
    {
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      "filed_on": "2002-04-15T00:00:00", 
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      "filed_on": "2002-04-26T00:00:00", 
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      "number": 41, 
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    {
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      "documents": [], 
      "filed_on": "2002-06-05T00:00:00", 
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    {
      "@id": "http://lexmachina.com/data/docket-entry/14007", 
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      "filed_on": "2002-06-10T00:00:00", 
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      "nice_text": "Acknowledgement from Gale Peterson ofc of receiving a copy of the file (djh) (Entered: 06/10/2002)", 
      "number": 76, 
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    {
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      "filed_on": "2002-06-26T00:00:00", 
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      "number": null, 
      "tags": []
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    {
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      "filed_on": "2002-07-09T00:00:00", 
      "id": 14033, 
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      "number": 101, 
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    {
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      "number": 106, 
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    }, 
    {
      "@id": "http://lexmachina.com/data/docket-entry/14039", 
      "documents": [], 
      "filed_on": "2002-07-11T00:00:00", 
      "id": 14039, 
      "nice_text": "Notice of attorney appearance for Samsung Electronics, Samsung Electronics by Charles Donohoe (fnt) (Entered: 07/11/2002)", 
      "number": 105, 
      "tags": []
    }, 
    {
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      "filed_on": "2002-07-11T00:00:00", 
      "id": 14042, 
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      "number": null, 
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    {
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      "documents": [], 
      "filed_on": "2002-07-17T00:00:00", 
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      "nice_text": "Reply by Sandisk Corporation to response to [79-1] motion to disqualify Weil, Gotshal & Manges, LLP (djh) (Entered: 07/17/2002)", 
      "number": 119, 
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    {
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      "filed_on": "2002-07-17T00:00:00", 
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      "nice_text": "Motion hearing re: [25-1] motion to transfer venue before Judge John Hannah Jr. (pad) (Entered: 07/17/2002)", 
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      "nice_text": "Minutes Re: [0-0] motion hearing by Judge John Hannah Jr. on 7/17/02 (Ct rep/ECRO: Shea Sloan) (pad) (Entered: 07/17/2002)", 
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      "filed_on": "2002-07-31T00:00:00", 
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      "filed_on": "2002-03-05T00:00:00", 
      "id": 13924, 
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      "filed_on": "2002-07-25T00:00:00", 
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      "nice_text": "ORDER denying [127-1] motion for reconsideration of [125-1] order granting Sandisk motion to transfer venue to California (signed by Judge John Hannah Jr) cc: attys, JH 7/25/02 (djh) Modified on 07/25/2002 (Entered: 07/25/2002)", 
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      "number": 131, 
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  "filed_on": "2002-03-05T00:00:00", 
  "id": 88, 
  "judges": [
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  "last_docket_date": "2003-06-10T00:00:00", 
  "tags": [
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      "id": 27, 
      "name": "Patent", 
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  "terminated_on": "2002-07-31T00:00:00", 
  "title": "Samsung Electronics v. Sandisk Corporation", 
  "trial_date": null
}