Verilog Module Declaration

mux.v

// Our input and output signals are all one bit.
// We could make them more than one bit; the only
// thing that would change is we would have to write
//  e.g "input [0:N] a" instead of "input a".
module mux(input a, input b, input select, output out);
    // Verilog code goes here
endmodule