Verilog Multiplexer Testbench

mux_test.v

module mux_test;

reg a, b, s;
wire out;

mux my_mux(a, b, s, out);

initial begin
    a <= 0;
    b <= 1;
    s <= 0;
    #1;
    $display("In: %b, %b select %b. Out %b.", a, b, s, out);
    #1;
    s <= 1;
    #1;
    $display("In: %b, %b select %b. Out %b.", a, b, s, out);
    #1;
    a <= 1;
    b <= 0;
    #1;
    $display("In: %b, %b select %b. Out %b.", a, b, s, out);
end
endmodule