Verilog Fibonacci Module

fib.v

module fib(input clock, reset, input [5:0] n, output reg ready, output [31:0] value)

reg [31:0] previous, current;
reg [5:0] counter;

// Reset the circuit
always @(posedge reset)
    begin
        previous <= 32'd0;
        current <= 32'd1;
        counter <= 32'd1;
    end

// Compute next Fibonacci number
always @(posedge clock)
    begin
        // Increment current index
        counter <= counter + 1;

        // Efficient adders are automatically inferred
        current <= current + previous;
        previous <= current;

       if (counter == n)
           ready <= 1;
    end

// Read the value of the nth fibonacci number from the internal register
assign value = current;

endmodule

This will have multiple driver issues while synthesizing.

This will have multiple driver issues while synthesizing.

Where exactly would the error may occur?

sorry, but the code has an error:

Error (10161): Verilog HDL error at fibonacci.v(21): object "ready" is not declared. Verify the object name is correct. If the name is correct, declare the object.
Error: Quartus Prime Analysis & Synthesis was unsuccessful. 1 error, 2 warnings
Error: Peak virtual memory: 4752 megabytes
Error: Processing ended: Sat Oct 09 14:56:34 2021
Error: Elapsed time: 00:00:06
Error: Total CPU time (on all processors): 00:00:14
Error (293001): Quartus Prime Full Compilation was unsuccessful. 3 errors, 2 warnings

This will have multiple driver issues while synthesizing