aml usb boot

gistfile1.txt

G12B:BL:6e7c85:2a3b91;FEAT:E0F97180:402000;POC:D;RCY:0;USB:0;0.�!,K��х��}���с0x01
bl2_stage_init 0x81
hw id: 0x0000 - pwm id 0x01
bl2_stage_init 0xc1
bl2_stage_init 0x02

L0:00000000
L1:20000700
L2:00008067
L3:14000000
B2:00402000
B1:e0f97180

TE: 4197558

BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz

Board ID = 4
Set A53 clk to 24M
Set A73 clk to 24M
Set clk81 to 24M
A53 clk: 1200 MHz
A73 clk: 1200 MHz
CLK81: 166.6M
smccc: 004054eb
DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
board id: 4
Cfg max: 3, cur: 1. Board id: 255. Force loop cfg
DATA transfer complete...
fw parse done
DATA transfer complete...
AML DDR FW load done
DATA transfer complete...
PIEI prepare done
DDR4 probe
ddr clk to 1320MHz
DATA transfer complete...

dmc_version 0001
Check phy result
INFO : End of initialization
INFO : End of read enable training
INFO : End of fine write leveling
INFO : End of read dq deskew training
INFO : End of MPR read delay center optimization
INFO : End of Write leveling coarse delay
INFO : End of write delay center optimization
INFO : End of read delay center optimization
INFO : End of max read latency training
INFO : Training has run successfully!
1D init succeed
DATA transfer complete...
Check phy result
INFO : End of initialization
INFO : End of 2D read delay Voltage center optimization
INFO : End of 2D write delay Voltage center optimization
INFO : Training has run successfully!

R0_RxClkDly_Margin==106 ps 9
R0_TxDqDly_Margi==130 ps 11


R1_RxClkDly_Margin==0 ps 0
R1_TxDqDly_Margi==0 ps 0

 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0001 

soc_vref_reg_value 0x 0000002d 0000002f 00000031 0000002e 0000002c 0000002b 0000002b 0000002a 0000002e 0000002d 0000002d 0000002b 00000031 0000002e 0000002b 0000002a 00000031 0000002f 0000003
0 0000002e 0000002e 00000031 00000032 0000002d 0000002b 00000030 00000030 0000002b 0000002f 0000002f 0000002b 0000002b dram_vref_reg_value 0x 00000017
2D init succeed
ddr init done, boot next stage
result report
aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
auto size-- 65535DDR cs0 size: 2048MB
DDR cs1 size: 0MB
DMC_DDR_CTRL: 0050002cDDR size: 2048MB
cs0 DataBus test pass
cs0 AddrBus test pass
DATA transfer complete...
DATA transfer complete...
Data req end
DATA transfer complete...
RUN bl2 usb boot
0.0;M3 CHK:0;cm4_sp_mode 0
MVN_1=0x00000000
MVN_2=0x00000000
[Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
OPS=0x10
ring efuse init
chipver efuse init
29 0b 10 00 01 08 11 00 00 07 37 30 4e 42 4e 50 
[0.018961 Inits done]
secure task start!
high task start!
low task start!
run into bl31
NOTICE:  BL31: v1.3(release):4fc40b1
NOTICE:  BL31: Built : 15:58:17, May 22 2019
NOTICE:  BL31: G12A normal boot!
NOTICE:  BL31: BL33 decompress pass
ERROR:   Error initializing runtime service opteed_fast


U-Boot 2015.01-g41f895ab07-dirty (Feb 22 2021 - 16:23:10)

DRAM:  2 GiB
Relocation Offset is: 76e2d000
spi_post_bind(spicc): req_seq = 0
spi_post_bind(spifc): req_seq = 1
[MSG]MMC init in usb
aml_priv->desc_buf = 0x0000000073e1db10
aml_priv->desc_buf = 0x0000000073e1fe50
SDIO Port B: 0, SDIO Port C: 1
InUsbBurn
[MSG]sof
Set Addr 14
Get DT cfg
Get DT cfg
set CFG