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JJRC H31 LT8910 spi dump
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| 1.1792 0 WRITE 10_OSC_XTAL_EN (0A) | |
| DATA: 50 61 01 90 11 00 50 0d 5f 0a f0 57 42 b8 15 b0 ad 05 64 2b 01 57 0a b0 55 42 a8 15 30 a9 05 44 2a 01 4f 0a 70 53 42 98 14 b0 a5 05 24 29 01 47 0a 30 51 42 88 14 30 a1 05 04 29 99 4d 5a c5 55 8a a8 55 f5 a7 | |
| STATUS: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff | |
| 1.5468 1 WRITE REG 0 (00) DATA: 6F E0 STATUS: 01 01 | |
| 1.5469 2 WRITE REG 1 (01) DATA: 56 81 STATUS: 01 01 | |
| 1.5469 3 WRITE REG 2 (02) DATA: 66 17 STATUS: 01 01 | |
| 1.5470 4 WRITE REG 4 (04) DATA: 9C C9 STATUS: 01 01 | |
| 1.5470 5 WRITE REG 5 (05) DATA: 66 37 STATUS: 01 01 | |
| 1.5471 6 WRITE REG 8 (08) DATA: 6C 90 STATUS: 01 01 | |
| 1.5472 7 WRITE 9_PA_CTRL (09) DATA: 48 00 STATUS: 01 01 | |
| 1.5472 8 WRITE 10_OSC_XTAL_EN (0A) DATA: 7F FD STATUS: 01 01 | |
| 1.5473 9 WRITE 11_RSSI_PDN (0B) DATA: 00 08 STATUS: 01 01 | |
| 1.5473 10 WRITE REG 12 (0C) DATA: 00 00 STATUS: 01 01 | |
| 1.5474 11 WRITE REG 13 (0D) DATA: 48 BD STATUS: 01 01 | |
| 1.5475 12 WRITE REG 22 (16) DATA: 00 FF STATUS: 01 01 | |
| 1.5475 13 WRITE 23_VCO_CAL_EN (17) DATA: 80 05 STATUS: 01 01 | |
| 1.5476 14 WRITE REG 24 (18) DATA: 00 67 STATUS: 01 01 | |
| 1.5476 15 WRITE REG 25 (19) DATA: 16 59 STATUS: 01 01 | |
| 1.5477 16 WRITE REG 26 (1A) DATA: 19 E0 STATUS: 01 01 | |
| 1.5478 17 WRITE REG 27 (1B) DATA: 13 00 STATUS: 01 01 | |
| 1.5478 18 WRITE REG 28 (1C) DATA: 18 00 STATUS: 01 01 | |
| 1.5479 19 WRITE 32_AIRFMT (20) DATA: 48 00 STATUS: 01 01 | |
| 1.5479 20 WRITE REG 33 (21) DATA: 3F C7 STATUS: 01 01 | |
| 1.5480 21 WRITE REG 34 (22) DATA: 20 00 STATUS: 01 01 | |
| 1.5481 22 WRITE 35_PWRCONFIG (23) DATA: 03 00 STATUS: 01 01 | |
| 1.5481 23 WRITE 36_SYNCWORD0 (24) DATA: 03 80 STATUS: 01 01 | |
| 1.5482 24 WRITE 37_SYNCWORD1 (25) DATA: 47 43 STATUS: 01 01 | |
| 1.5482 25 WRITE 38_SYNCWORD2 (26) DATA: 46 44 STATUS: 01 01 | |
| 1.5483 26 WRITE 39_SYNCWORD3 (27) DATA: 30 30 STATUS: 01 01 | |
| 1.5484 27 WRITE 40_THRESH (28) DATA: 44 01 STATUS: 01 01 | |
| 1.5484 28 WRITE 41_PKTCONF (29) DATA: B0 00 STATUS: 01 01 | |
| 1.5485 29 WRITE REG 42 (2A) DATA: FD B0 STATUS: 01 01 | |
| 1.5486 30 WRITE 43_RSSI (2B) DATA: 00 0F STATUS: 01 01 | |
| 1.5486 31 WRITE 44_DATARATE (2C) DATA: 10 00 STATUS: 01 01 | |
| 1.5487 32 WRITE REG 45 (2D) DATA: 05 52 STATUS: 01 01 | |
| 1.5487 33 WRITE 52_TXRX_RWPTRS (34) DATA: 80 80 STATUS: 01 01 | |
| 1.5488 34 WRITE REG 0 (00) DATA: 6F E0 STATUS: 01 01 | |
| 1.5489 35 WRITE REG 1 (01) DATA: 56 81 STATUS: 01 01 | |
| 1.5489 36 WRITE REG 2 (02) DATA: 66 17 STATUS: 01 01 | |
| 1.5490 37 WRITE REG 4 (04) DATA: 9C C9 STATUS: 01 01 | |
| 1.5490 38 WRITE REG 5 (05) DATA: 66 37 STATUS: 01 01 | |
| 1.5491 39 WRITE REG 8 (08) DATA: 6C 90 STATUS: 01 01 | |
| 1.5492 40 WRITE 9_PA_CTRL (09) DATA: 48 00 STATUS: 01 01 | |
| 1.5492 41 WRITE 10_OSC_XTAL_EN (0A) DATA: 7F FD STATUS: 01 01 | |
| 1.5493 42 WRITE 11_RSSI_PDN (0B) DATA: 00 08 STATUS: 01 01 | |
| 1.5493 43 WRITE REG 12 (0C) DATA: 00 00 STATUS: 01 01 | |
| 1.5494 44 WRITE REG 13 (0D) DATA: 48 BD STATUS: 01 01 | |
| 1.5495 45 WRITE REG 22 (16) DATA: 00 FF STATUS: 01 01 | |
| 1.5495 46 WRITE 23_VCO_CAL_EN (17) DATA: 80 05 STATUS: 01 01 | |
| 1.5496 47 WRITE REG 24 (18) DATA: 00 67 STATUS: 01 01 | |
| 1.5496 48 WRITE REG 25 (19) DATA: 16 59 STATUS: 01 01 | |
| 1.5497 49 WRITE REG 26 (1A) DATA: 19 E0 STATUS: 01 01 | |
| 1.5498 50 WRITE REG 27 (1B) DATA: 13 00 STATUS: 01 01 | |
| 1.5498 51 WRITE REG 28 (1C) DATA: 18 00 STATUS: 01 01 | |
| 1.5499 52 WRITE 32_AIRFMT (20) DATA: 48 00 STATUS: 01 01 | |
| 1.5499 53 WRITE REG 33 (21) DATA: 3F C7 STATUS: 01 01 | |
| 1.5500 54 WRITE REG 34 (22) DATA: 20 00 STATUS: 01 01 | |
| 1.5501 55 WRITE 35_PWRCONFIG (23) DATA: 03 00 STATUS: 01 01 | |
| 1.5501 56 WRITE 36_SYNCWORD0 (24) DATA: 03 80 STATUS: 01 01 | |
| 1.5502 57 WRITE 37_SYNCWORD1 (25) DATA: 47 43 STATUS: 01 01 | |
| 1.5502 58 WRITE 38_SYNCWORD2 (26) DATA: 46 44 STATUS: 01 01 | |
| 1.5503 59 WRITE 39_SYNCWORD3 (27) DATA: 30 30 STATUS: 01 01 | |
| 1.5504 60 WRITE 40_THRESH (28) DATA: 44 01 STATUS: 01 01 | |
| 1.5504 61 WRITE 41_PKTCONF (29) DATA: B0 00 STATUS: 01 01 | |
| 1.5505 62 WRITE REG 42 (2A) DATA: FD B0 STATUS: 01 01 | |
| 1.5506 63 WRITE 43_RSSI (2B) DATA: 00 0F STATUS: 01 01 | |
| 1.5506 64 WRITE 44_DATARATE (2C) DATA: 10 00 STATUS: 01 01 | |
| 1.5507 65 WRITE REG 45 (2D) DATA: 05 52 STATUS: 01 01 | |
| 1.5507 66 WRITE 52_TXRX_RWPTRS (34) DATA: 80 80 STATUS: 01 01 | |
| 1.5508 67 WRITE REG 0 (00) DATA: 6F E0 STATUS: 01 01 | |
| 1.5509 68 WRITE REG 1 (01) DATA: 56 81 STATUS: 01 01 | |
| 1.5509 69 WRITE REG 2 (02) DATA: 66 17 STATUS: 01 01 | |
| 1.5510 70 WRITE REG 4 (04) DATA: 9C C9 STATUS: 01 01 | |
| 1.5510 71 WRITE REG 5 (05) DATA: 66 37 STATUS: 01 01 | |
| 1.5511 72 WRITE REG 8 (08) DATA: 6C 90 STATUS: 01 01 | |
| 1.5512 73 WRITE 9_PA_CTRL (09) DATA: 48 00 STATUS: 01 01 | |
| 1.5512 74 WRITE 10_OSC_XTAL_EN (0A) DATA: 7F FD STATUS: 01 01 | |
| 1.5513 75 WRITE 11_RSSI_PDN (0B) DATA: 00 08 STATUS: 01 01 | |
| 1.5513 76 WRITE REG 12 (0C) DATA: 00 00 STATUS: 01 01 | |
| 1.5514 77 WRITE REG 13 (0D) DATA: 48 BD STATUS: 01 01 | |
| 1.5515 78 WRITE REG 22 (16) DATA: 00 FF STATUS: 01 01 | |
| 1.5515 79 WRITE 23_VCO_CAL_EN (17) DATA: 80 05 STATUS: 01 01 | |
| 1.5516 80 WRITE REG 24 (18) DATA: 00 67 STATUS: 01 01 | |
| 1.5516 81 WRITE REG 25 (19) DATA: 16 59 STATUS: 01 01 | |
| 1.5517 82 WRITE REG 26 (1A) DATA: 19 E0 STATUS: 01 01 | |
| 1.5518 83 WRITE REG 27 (1B) DATA: 13 00 STATUS: 01 01 | |
| 1.5518 84 WRITE REG 28 (1C) DATA: 18 00 STATUS: 01 01 | |
| 1.5519 85 WRITE 32_AIRFMT (20) DATA: 48 00 STATUS: 01 01 | |
| 1.5519 86 WRITE REG 33 (21) DATA: 3F C7 STATUS: 01 01 | |
| 1.5520 87 WRITE REG 34 (22) DATA: 20 00 STATUS: 01 01 | |
| 1.5521 88 WRITE 35_PWRCONFIG (23) DATA: 03 00 STATUS: 01 01 | |
| 1.5521 89 WRITE 36_SYNCWORD0 (24) DATA: 03 80 STATUS: 01 01 | |
| 1.5522 90 WRITE 37_SYNCWORD1 (25) DATA: 47 43 STATUS: 01 01 | |
| 1.5522 91 WRITE 38_SYNCWORD2 (26) DATA: 46 44 STATUS: 01 01 | |
| 1.5523 92 WRITE 39_SYNCWORD3 (27) DATA: 30 30 STATUS: 01 01 | |
| 1.5524 93 WRITE 40_THRESH (28) DATA: 44 01 STATUS: 01 01 | |
| 1.5524 94 WRITE 41_PKTCONF (29) DATA: B0 00 STATUS: 01 01 | |
| 1.5525 95 WRITE REG 42 (2A) DATA: FD B0 STATUS: 01 01 | |
| 1.5526 96 WRITE 43_RSSI (2B) DATA: 00 0F STATUS: 01 01 | |
| 1.5526 97 WRITE 44_DATARATE (2C) DATA: 10 00 STATUS: 01 01 | |
| 1.5527 98 WRITE REG 45 (2D) DATA: 05 52 STATUS: 01 01 | |
| 1.5527 99 WRITE 52_TXRX_RWPTRS (34) DATA: 80 80 STATUS: 01 01 | |
| 1.5528 100 WRITE REG 0 (00) DATA: 6F E0 STATUS: 01 01 | |
| 1.5529 101 WRITE REG 1 (01) DATA: 56 81 STATUS: 01 01 | |
| 1.5529 102 WRITE REG 2 (02) DATA: 66 17 STATUS: 01 01 | |
| 1.5530 103 WRITE REG 4 (04) DATA: 9C C9 STATUS: 01 01 | |
| 1.5530 104 WRITE REG 5 (05) DATA: 66 37 STATUS: 01 01 | |
| 1.5531 105 WRITE REG 8 (08) DATA: 6C 90 STATUS: 01 01 | |
| 1.5532 106 WRITE 9_PA_CTRL (09) DATA: 48 00 STATUS: 01 01 | |
| 1.5532 107 WRITE 10_OSC_XTAL_EN (0A) DATA: 7F FD STATUS: 01 01 | |
| 1.5533 108 WRITE 11_RSSI_PDN (0B) DATA: 00 08 STATUS: 01 01 | |
| 1.5533 109 WRITE REG 12 (0C) DATA: 00 00 STATUS: 01 01 | |
| 1.5534 110 WRITE REG 13 (0D) DATA: 48 BD STATUS: 01 01 | |
| 1.5535 111 WRITE REG 22 (16) DATA: 00 FF STATUS: 01 01 | |
| 1.5535 112 WRITE 23_VCO_CAL_EN (17) DATA: 80 05 STATUS: 01 01 | |
| 1.5536 113 WRITE REG 24 (18) DATA: 00 67 STATUS: 01 01 | |
| 1.5536 114 WRITE REG 25 (19) DATA: 16 59 STATUS: 01 01 | |
| 1.5537 115 WRITE REG 26 (1A) DATA: 19 E0 STATUS: 01 01 | |
| 1.5538 116 WRITE REG 27 (1B) DATA: 13 00 STATUS: 01 01 | |
| 1.5538 117 WRITE REG 28 (1C) DATA: 18 00 STATUS: 01 01 | |
| 1.5539 118 WRITE 32_AIRFMT (20) DATA: 48 00 STATUS: 01 01 | |
| 1.5539 119 WRITE REG 33 (21) DATA: 3F C7 STATUS: 01 01 | |
| 1.5540 120 WRITE REG 34 (22) DATA: 20 00 STATUS: 01 01 | |
| 1.5541 121 WRITE 35_PWRCONFIG (23) DATA: 03 00 STATUS: 01 01 | |
| 1.5541 122 WRITE 36_SYNCWORD0 (24) DATA: 03 80 STATUS: 01 01 | |
| 1.5542 123 WRITE 37_SYNCWORD1 (25) DATA: 47 43 STATUS: 01 01 | |
| 1.5542 124 WRITE 38_SYNCWORD2 (26) DATA: 46 44 STATUS: 01 01 | |
| 1.5543 125 WRITE 39_SYNCWORD3 (27) DATA: 30 30 STATUS: 01 01 | |
| 1.5544 126 WRITE 40_THRESH (28) DATA: 44 01 STATUS: 01 01 | |
| 1.5544 127 WRITE 41_PKTCONF (29) DATA: B0 00 STATUS: 01 01 | |
| 1.5545 128 WRITE REG 42 (2A) DATA: FD B0 STATUS: 01 01 | |
| 1.5546 129 WRITE 43_RSSI (2B) DATA: 00 0F STATUS: 01 01 | |
| 1.5546 130 WRITE 44_DATARATE (2C) DATA: 10 00 STATUS: 01 01 | |
| 1.5547 131 WRITE REG 45 (2D) DATA: 05 52 STATUS: 01 01 | |
| 1.5547 132 WRITE 52_TXRX_RWPTRS (34) DATA: 80 80 STATUS: 01 01 | |
| 1.5548 133 WRITE REG 0 (00) DATA: 6F E0 STATUS: 01 01 | |
| 1.5549 134 WRITE REG 1 (01) DATA: 56 81 STATUS: 01 01 | |
| 1.5549 135 WRITE REG 2 (02) DATA: 66 17 STATUS: 01 01 | |
| 1.5550 136 WRITE REG 4 (04) DATA: 9C C9 STATUS: 01 01 | |
| 1.5550 137 WRITE REG 5 (05) DATA: 66 37 STATUS: 01 01 | |
| 1.5551 138 WRITE REG 8 (08) DATA: 6C 90 STATUS: 01 01 | |
| 1.5552 139 WRITE 9_PA_CTRL (09) DATA: 48 00 STATUS: 01 01 | |
| 1.5552 140 WRITE 10_OSC_XTAL_EN (0A) DATA: 7F FD STATUS: 01 01 | |
| 1.5553 141 WRITE 11_RSSI_PDN (0B) DATA: 00 08 STATUS: 01 01 | |
| 1.5553 142 WRITE REG 12 (0C) DATA: 00 00 STATUS: 01 01 | |
| 1.5554 143 WRITE REG 13 (0D) DATA: 48 BD STATUS: 01 01 | |
| 1.5555 144 WRITE REG 22 (16) DATA: 00 FF STATUS: 01 01 | |
| 1.5555 145 WRITE 23_VCO_CAL_EN (17) DATA: 80 05 STATUS: 01 01 | |
| 1.5556 146 WRITE REG 24 (18) DATA: 00 67 STATUS: 01 01 | |
| 1.5556 147 WRITE REG 25 (19) DATA: 16 59 STATUS: 01 01 | |
| 1.5557 148 WRITE REG 26 (1A) DATA: 19 E0 STATUS: 01 01 | |
| 1.5558 149 WRITE REG 27 (1B) DATA: 13 00 STATUS: 01 01 | |
| 1.5558 150 WRITE REG 28 (1C) DATA: 18 00 STATUS: 01 01 | |
| 1.5559 151 WRITE 32_AIRFMT (20) DATA: 48 00 STATUS: 01 01 | |
| 1.5559 152 WRITE REG 33 (21) DATA: 3F C7 STATUS: 01 01 | |
| 1.5560 153 WRITE REG 34 (22) DATA: 20 00 STATUS: 01 01 | |
| 1.5561 154 WRITE 35_PWRCONFIG (23) DATA: 03 00 STATUS: 01 01 | |
| 1.5561 155 WRITE 36_SYNCWORD0 (24) DATA: 03 80 STATUS: 01 01 | |
| 1.5562 156 WRITE 37_SYNCWORD1 (25) DATA: 47 43 STATUS: 01 01 | |
| 1.5562 157 WRITE 38_SYNCWORD2 (26) DATA: 46 44 STATUS: 01 01 | |
| 1.5563 158 WRITE 39_SYNCWORD3 (27) DATA: 30 30 STATUS: 01 01 | |
| 1.5564 159 WRITE 40_THRESH (28) DATA: 44 01 STATUS: 01 01 | |
| 1.5564 160 WRITE 41_PKTCONF (29) DATA: B0 00 STATUS: 01 01 | |
| 1.5565 161 WRITE REG 42 (2A) DATA: FD B0 STATUS: 01 01 | |
| 1.5566 162 WRITE 43_RSSI (2B) DATA: 00 0F STATUS: 01 01 | |
| 1.5566 163 WRITE 44_DATARATE (2C) DATA: 10 00 STATUS: 01 01 | |
| 1.5567 164 WRITE REG 45 (2D) DATA: 05 52 STATUS: 01 01 | |
| 1.5567 165 WRITE 52_TXRX_RWPTRS (34) DATA: 80 80 STATUS: 01 01 | |
| 1.5568 166 WRITE REG 0 (00) DATA: 6F E0 STATUS: 01 01 | |
| 1.5569 167 WRITE REG 1 (01) DATA: 56 81 STATUS: 01 01 | |
| 1.5569 168 WRITE REG 2 (02) DATA: 66 17 STATUS: 01 01 | |
| 1.5570 169 WRITE REG 4 (04) DATA: 9C C9 STATUS: 01 01 | |
| 1.5570 170 WRITE REG 5 (05) DATA: 66 37 STATUS: 01 01 | |
| 1.5571 171 WRITE REG 8 (08) DATA: 6C 90 STATUS: 01 01 | |
| 1.5572 172 WRITE 9_PA_CTRL (09) DATA: 48 00 STATUS: 01 01 | |
| 1.5572 173 WRITE 10_OSC_XTAL_EN (0A) DATA: 7F FD STATUS: 01 01 | |
| 1.5573 174 WRITE 11_RSSI_PDN (0B) DATA: 00 08 STATUS: 01 01 | |
| 1.5573 175 WRITE REG 12 (0C) DATA: 00 00 STATUS: 01 01 | |
| 1.5574 176 WRITE REG 13 (0D) DATA: 48 BD STATUS: 01 01 | |
| 1.5575 177 WRITE REG 22 (16) DATA: 00 FF STATUS: 01 01 | |
| 1.5575 178 WRITE 23_VCO_CAL_EN (17) DATA: 80 05 STATUS: 01 01 | |
| 1.5576 179 WRITE REG 24 (18) DATA: 00 67 STATUS: 01 01 | |
| 1.5576 180 WRITE REG 25 (19) DATA: 16 59 STATUS: 01 01 | |
| 1.5577 181 WRITE REG 26 (1A) DATA: 19 E0 STATUS: 01 01 | |
| 1.5578 182 WRITE REG 27 (1B) DATA: 13 00 STATUS: 01 01 | |
| 1.5578 183 WRITE REG 28 (1C) DATA: 18 00 STATUS: 01 01 | |
| 1.5579 184 WRITE 32_AIRFMT (20) DATA: 48 00 STATUS: 01 01 // 3 byte preamble, 32 bit syncword, 4 bit trailer, nrz, no fec, packet length set by 1st byte of payload | |
| 1.5579 185 WRITE REG 33 (21) DATA: 3F C7 STATUS: 01 01 | |
| 1.5580 186 WRITE REG 34 (22) DATA: 20 00 STATUS: 01 01 | |
| 1.5581 187 WRITE 35_PWRCONFIG (23) DATA: 03 00 STATUS: 01 01 | |
| 1.5581 188 WRITE 36_SYNCWORD0 (24) DATA: 03 80 STATUS: 01 01 // syncword [0:15] | |
| 1.5582 189 WRITE 37_SYNCWORD1 (25) DATA: 47 43 STATUS: 01 01 // syncword [16:31] | |
| 1.5582 190 WRITE 38_SYNCWORD2 (26) DATA: 46 44 STATUS: 01 01 // syncword [32:47] (unused) | |
| 1.5583 191 WRITE 39_SYNCWORD3 (27) DATA: 30 30 STATUS: 01 01 // syncword [48:63] (unused) | |
| 1.5584 192 WRITE 40_THRESH (28) DATA: 44 01 STATUS: 01 01 // no error bit allowed in syncword | |
| 1.5584 193 WRITE 41_PKTCONF (29) DATA: B0 00 STATUS: 01 01 // CRC on (init = 00), scramble off, no auto-ack | |
| 1.5585 194 WRITE REG 42 (2A) DATA: FD B0 STATUS: 01 01 | |
| 1.5586 195 WRITE 43_RSSI (2B) DATA: 00 0F STATUS: 01 01 | |
| 1.5586 196 WRITE 44_DATARATE (2C) DATA: 10 00 STATUS: 01 01 // 62.5 kbps datarate | |
| 1.5587 197 WRITE REG 45 (2D) DATA: 05 52 STATUS: 01 01 | |
| 1.5587 198 WRITE 52_TXRX_RWPTRS (34) DATA: 80 80 STATUS: 01 01 // reset FIFO pointers | |
| 1.5588 199 READ 9_PA_CTRL (89) DATA: 00 00 STATUS: 48 00 | |
| 1.7591 200 WRITE 7_RXTX_CHNL (07) DATA: 00 00 STATUS: 01 01 | |
| 1.7591 201 WRITE REG 18 (52) DATA: 80 80 STATUS: 01 01 | |
| 1.7592 202 WRITE 50_TXRX_FIFO (32) | |
| DATA: 0f 1d 55 3f 45 49 50 11 20 00 00 57 00 00 aa e4 // bind packet | |
| STATUS: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 | |
| 1.7595 203 WRITE 7_RXTX_CHNL (07) DATA: 01 32 STATUS: 01 01 // transmit, ch 0x32 (2452 MHz) | |
| 1.7647 204 READ 48_STATUS (B0) DATA: 00 00 STATUS: 01 40 | |
| 1.7648 205 READ 50_TXRX_FIFO (B2) DATA: 00 00 STATUS: 00 00 | |
| 1.7649 206 WRITE 7_RXTX_CHNL (07) DATA: 00 00 STATUS: 01 01 | |
| 1.7649 207 WRITE 52_TXRX_RWPTRS (34) DATA: 80 80 STATUS: 01 01 | |
| 1.7650 208 WRITE 7_RXTX_CHNL (07) DATA: 00 B2 STATUS: 01 01 // rx mode, ch 32 | |
| 1.7656 209 READ 48_STATUS (B0) DATA: 00 00 STATUS: 12 04 | |
| 1.7663 210 READ 48_STATUS (B0) DATA: 00 00 STATUS: 12 04 | |
| 1.7669 211 READ 48_STATUS (B0) DATA: 00 00 STATUS: 12 04 | |
| 1.7676 212 READ 48_STATUS (B0) DATA: 00 00 STATUS: 12 04 | |
| 1.7682 213 READ 48_STATUS (B0) DATA: 00 00 STATUS: 12 04 | |
| 1.7689 214 READ 48_STATUS (B0) DATA: 00 00 STATUS: 12 04 | |
| 1.7695 215 READ 48_STATUS (B0) DATA: 00 00 STATUS: 12 04 | |
| 1.7702 216 READ 48_STATUS (B0) DATA: 00 00 STATUS: 12 04 | |
| 1.7708 217 READ 48_STATUS (B0) DATA: 00 00 STATUS: 12 04 | |
| 1.7715 218 READ 48_STATUS (B0) DATA: 00 00 STATUS: 12 04 | |
| 1.7721 219 READ 48_STATUS (B0) DATA: 00 00 STATUS: 12 04 | |
| 1.7727 220 READ 48_STATUS (B0) DATA: 00 00 STATUS: 12 04 | |
| 1.7734 221 READ 48_STATUS (B0) DATA: 00 00 STATUS: 12 04 | |
| 1.7740 222 READ 48_STATUS (B0) DATA: 00 00 STATUS: 12 04 | |
| 1.7747 223 READ 48_STATUS (B0) DATA: 00 00 STATUS: 12 04 | |
| 1.7753 224 READ 48_STATUS (B0) DATA: 00 00 STATUS: 12 04 | |
| 1.7760 225 READ 48_STATUS (B0) DATA: 00 00 STATUS: 12 04 | |
| 1.7766 226 READ 48_STATUS (B0) DATA: 00 00 STATUS: 12 04 | |
| 1.7773 227 READ 48_STATUS (B0) DATA: 00 00 STATUS: 12 04 | |
| 1.7779 228 WRITE 7_RXTX_CHNL (07) DATA: 00 00 STATUS: 12 12 | |
| 1.7780 229 WRITE REG 18 (52) DATA: 80 80 STATUS: 01 01 | |
| 1.7780 230 WRITE 50_TXRX_FIFO (32) | |
| DATA: 0f 1d 55 3f 45 49 50 11 20 00 00 57 00 00 aa e4 // bind packet | |
| STATUS: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 | |
| 1.7784 231 WRITE 7_RXTX_CHNL (07) DATA: 01 32 STATUS: 01 01 // tx, ch 32 | |
| 1.7836 232 READ 48_STATUS (B0) DATA: 00 00 STATUS: 01 40 | |
| 1.7837 233 READ 50_TXRX_FIFO (B2) DATA: 00 00 STATUS: 00 00 | |
| 1.7837 234 WRITE 7_RXTX_CHNL (07) DATA: 00 00 STATUS: 01 01 | |
| 1.7838 235 WRITE 52_TXRX_RWPTRS (34) DATA: 80 80 STATUS: 01 01 | |
| 1.7838 236 WRITE 7_RXTX_CHNL (07) DATA: 00 B2 STATUS: 01 01 // rx mode, ch 32 | |
| 1.7845 237 READ 48_STATUS (B0) DATA: 00 00 STATUS: 12 04 | |
| 1.7851 238 READ 48_STATUS (B0) DATA: 00 00 STATUS: 12 04 | |
| 1.7858 239 READ 48_STATUS (B0) DATA: 00 00 STATUS: 12 04 | |
| 1.7864 240 READ 48_STATUS (B0) DATA: 00 00 STATUS: 12 04 | |
| 1.7871 241 READ 48_STATUS (B0) DATA: 00 00 STATUS: 12 04 | |
| 1.7877 242 READ 48_STATUS (B0) DATA: 00 00 STATUS: 12 04 | |
| 1.7884 243 READ 48_STATUS (B0) DATA: 00 00 STATUS: 12 04 | |
| 1.7890 244 READ 48_STATUS (B0) DATA: 00 00 STATUS: 12 04 | |
| 1.7896 245 READ 48_STATUS (B0) DATA: 00 00 STATUS: 12 04 | |
| 1.7903 246 READ 48_STATUS (B0) DATA: 00 00 STATUS: 12 04 | |
| 1.7909 247 READ 48_STATUS (B0) DATA: 00 00 STATUS: 12 04 | |
| 1.7916 248 READ 48_STATUS (B0) DATA: 00 00 STATUS: 12 04 | |
| 1.7922 249 READ 48_STATUS (B0) DATA: 00 00 STATUS: 12 04 | |
| 1.7929 250 READ 48_STATUS (B0) DATA: 00 00 STATUS: 12 04 | |
| 1.7935 251 READ 48_STATUS (B0) DATA: 00 00 STATUS: 12 04 | |
| 1.7942 252 READ 48_STATUS (B0) DATA: 00 00 STATUS: 12 04 | |
| 1.7948 253 READ 48_STATUS (B0) DATA: 00 00 STATUS: 12 04 | |
| 1.7955 254 READ 48_STATUS (B0) DATA: 00 00 STATUS: 12 04 | |
| 1.7961 255 READ 48_STATUS (B0) DATA: 00 00 STATUS: 12 04 | |
| 1.7968 256 WRITE 7_RXTX_CHNL (07) DATA: 00 00 STATUS: 12 12 | |
| 1.7968 257 WRITE REG 18 (52) DATA: 80 80 STATUS: 01 01 | |
| 1.7969 258 WRITE 50_TXRX_FIFO (32) | |
| DATA: 0f 1d 55 3f 45 49 50 11 20 00 00 57 00 00 aa e4 // bind packet | |
| STATUS: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 | |
| 1.7972 259 WRITE 7_RXTX_CHNL (07) DATA: 01 32 STATUS: 01 01 // tx, ch 32 | |
| 1.8024 260 READ 48_STATUS (B0) DATA: 00 00 STATUS: 01 40 | |
| 1.8025 261 READ 50_TXRX_FIFO (B2) DATA: 00 00 STATUS: 00 00 | |
| 1.8026 262 WRITE 7_RXTX_CHNL (07) DATA: 00 00 STATUS: 01 01 | |
| 1.8026 263 WRITE 52_TXRX_RWPTRS (34) DATA: 80 80 STATUS: 01 01 | |
| 1.8027 264 WRITE 7_RXTX_CHNL (07) DATA: 00 B2 STATUS: 01 01 // rx mode, ch 32 | |
| 1.8033 265 READ 48_STATUS (B0) DATA: 00 00 STATUS: 12 04 | |
| 1.8040 266 READ 48_STATUS (B0) DATA: 00 00 STATUS: 12 04 | |
| 1.8046 267 READ 48_STATUS (B0) DATA: 00 00 STATUS: 12 04 | |
| 1.8053 268 READ 48_STATUS (B0) DATA: 00 00 STATUS: 12 04 | |
| 1.8059 269 READ 48_STATUS (B0) DATA: 00 00 STATUS: 12 04 | |
| 1.8066 270 READ 48_STATUS (B0) DATA: 00 00 STATUS: 12 04 | |
| 1.8072 271 READ 48_STATUS (B0) DATA: 00 00 STATUS: 12 04 | |
| 1.8078 272 READ 48_STATUS (B0) DATA: 00 00 STATUS: 12 04 | |
| 1.8085 273 READ 48_STATUS (B0) DATA: 00 00 STATUS: 12 04 | |
| 1.8091 274 READ 48_STATUS (B0) DATA: 00 00 STATUS: 12 04 | |
| 1.8098 275 READ 48_STATUS (B0) DATA: 00 00 STATUS: 12 04 | |
| 1.8104 276 READ 48_STATUS (B0) DATA: 00 00 STATUS: 12 04 | |
| 1.8111 277 READ 48_STATUS (B0) DATA: 00 00 STATUS: 12 04 | |
| 1.8117 278 READ 48_STATUS (B0) DATA: 00 00 STATUS: 12 04 | |
| 1.8124 279 READ 48_STATUS (B0) DATA: 00 00 STATUS: 12 04 | |
| 1.8130 280 READ 48_STATUS (B0) DATA: 00 00 STATUS: 12 04 | |
| 1.8137 281 READ 48_STATUS (B0) DATA: 00 00 STATUS: 12 04 | |
| 1.8143 282 READ 48_STATUS (B0) DATA: 00 00 STATUS: 12 04 | |
| 1.8150 283 READ 48_STATUS (B0) DATA: 00 00 STATUS: 12 04 | |
| 1.8156 284 WRITE 7_RXTX_CHNL (07) DATA: 00 00 STATUS: 12 12 | |
| 1.8157 285 WRITE REG 18 (52) DATA: 80 80 STATUS: 01 01 | |
| 1.8157 286 WRITE 50_TXRX_FIFO (32) | |
| DATA: 0f 1d 55 3f 45 49 50 11 20 00 00 57 00 00 aa e4 // bind packet | |
| STATUS: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 | |
| 1.8161 287 WRITE 7_RXTX_CHNL (07) DATA: 01 32 STATUS: 01 01 // tx, ch 32 | |
| 1.8213 288 READ 48_STATUS (B0) DATA: 00 00 STATUS: 01 40 | |
| 1.8213 289 READ 50_TXRX_FIFO (B2) DATA: 00 00 STATUS: 00 00 | |
| 1.8214 290 WRITE 7_RXTX_CHNL (07) DATA: 00 00 STATUS: 01 01 | |
| 1.8215 291 WRITE 52_TXRX_RWPTRS (34) DATA: 80 80 STATUS: 01 01 | |
| 1.8215 292 WRITE 7_RXTX_CHNL (07) DATA: 00 B2 STATUS: 01 01 // rx mode, ch 32 | |
| 1.8222 293 READ 48_STATUS (B0) DATA: 00 00 STATUS: 12 04 | |
| 1.8228 294 READ 48_STATUS (B0) DATA: 00 00 STATUS: 12 04 | |
| 1.8235 295 READ 48_STATUS (B0) DATA: 00 00 STATUS: 12 04 | |
| 1.8241 296 READ 48_STATUS (B0) DATA: 00 00 STATUS: 12 04 | |
| 1.8247 297 READ 48_STATUS (B0) DATA: 00 00 STATUS: 12 04 | |
| 1.8254 298 READ 48_STATUS (B0) DATA: 00 00 STATUS: 12 04 | |
| 1.8260 299 READ 48_STATUS (B0) DATA: 00 00 STATUS: 12 04 | |
| 1.8267 300 READ 48_STATUS (B0) DATA: 00 00 STATUS: 12 04 | |
| 1.8273 301 READ 48_STATUS (B0) DATA: 00 00 STATUS: 12 04 | |
| 1.8280 302 READ 48_STATUS (B0) DATA: 00 00 STATUS: 12 04 | |
| 1.8286 303 READ 48_STATUS (B0) DATA: 00 00 STATUS: 12 04 | |
| 1.8293 304 READ 48_STATUS (B0) DATA: 00 00 STATUS: 11 84 | |
| 1.8299 305 READ 48_STATUS (B0) DATA: 00 00 STATUS: 11 84 | |
| 1.8306 306 READ 48_STATUS (B0) DATA: 00 00 STATUS: 11 84 | |
| 1.8312 307 READ 48_STATUS (B0) DATA: 00 00 STATUS: 10 84 | |
| 1.8319 308 READ 48_STATUS (B0) DATA: 00 00 STATUS: 01 40 // packet received (PKT_FLAG) | |
| 1.8319 309 READ 50_TXRX_FIFO (B2) DATA: 00 00 STATUS: 0F 1D // bind response (sent by rx) | |
| 1.8320 310 READ 50_TXRX_FIFO (B2) DATA: 00 00 STATUS: 55 AA // 1D 55 AA BB CC DD 11 20 00 00 57 00 00 85 E4 | |
| 1.8321 311 READ 50_TXRX_FIFO (B2) DATA: 00 00 STATUS: BB CC | |
| 1.8321 312 READ 50_TXRX_FIFO (B2) DATA: 00 00 STATUS: DD 11 | |
| 1.8322 313 READ 50_TXRX_FIFO (B2) DATA: 00 00 STATUS: 20 00 | |
| 1.8323 314 READ 50_TXRX_FIFO (B2) DATA: 00 00 STATUS: 00 57 | |
| 1.8323 315 READ 50_TXRX_FIFO (B2) DATA: 00 00 STATUS: 00 00 | |
| 1.8324 316 READ 50_TXRX_FIFO (B2) DATA: 00 00 STATUS: 85 E4 | |
| 1.8325 317 WRITE 7_RXTX_CHNL (07) DATA: 00 00 STATUS: 01 01 | |
| 1.8325 318 WRITE 52_TXRX_RWPTRS (34) DATA: 80 80 STATUS: 01 01 | |
| 1.8326 319 WRITE 7_RXTX_CHNL (07) DATA: 00 B2 STATUS: 01 01 // rx mode, ch 32 | |
| 1.8332 320 WRITE 36_SYNCWORD0 (24) DATA: 1D E4 STATUS: 12 12 // data syncword (2 first bytes) = first & last byte of bind packet | |
| 1.8353 321 WRITE 7_RXTX_CHNL (07) DATA: 00 00 STATUS: 12 12 | |
| 1.8353 322 WRITE REG 18 (52) DATA: 80 80 STATUS: 01 01 | |
| 1.8354 323 WRITE 50_TXRX_FIFO (32) | |
| DATA: 0f 1d 01 64 64 64 00 aa 00 00 00 00 00 00 85 e4 // data | |
| STATUS: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 | |
| 1.8357 324 WRITE 7_RXTX_CHNL (07) DATA: 01 32 STATUS: 01 01 // tx, ch 32 | |
| 1.8410 325 WRITE 7_RXTX_CHNL (07) DATA: 00 00 STATUS: 01 01 | |
| 1.8411 326 WRITE REG 18 (52) DATA: 80 80 STATUS: 01 01 | |
| 1.8411 327 WRITE 50_TXRX_FIFO (32) | |
| DATA: 0f 1d 01 64 64 64 00 aa 00 00 00 00 00 00 85 e4 | |
| STATUS: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 | |
| 1.8415 328 WRITE 7_RXTX_CHNL (07) DATA: 01 35 STATUS: 01 01 // tx, ch 35 | |
| 1.8468 329 WRITE 7_RXTX_CHNL (07) DATA: 00 00 STATUS: 01 01 | |
| 1.8469 330 WRITE REG 18 (52) DATA: 80 80 STATUS: 01 01 | |
| 1.8469 331 WRITE 50_TXRX_FIFO (32) | |
| DATA: 0f 1d 01 64 64 64 00 aa 00 00 00 00 00 00 85 e4 | |
| STATUS: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 | |
| 1.8472 332 WRITE 7_RXTX_CHNL (07) DATA: 01 3C STATUS: 01 01 // tx, ch 3c | |
| 1.8525 333 WRITE 7_RXTX_CHNL (07) DATA: 00 00 STATUS: 01 01 | |
| 1.8526 334 WRITE REG 18 (52) DATA: 80 80 STATUS: 01 01 | |
| 1.8526 335 WRITE 50_TXRX_FIFO (32) | |
| DATA: 0f 1d 01 64 64 64 00 aa 00 00 00 00 00 00 85 e4 | |
| STATUS: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 | |
| 1.8530 336 WRITE 7_RXTX_CHNL (07) DATA: 01 46 STATUS: 01 01 // tx, ch 46 | |
| 1.8583 337 WRITE 7_RXTX_CHNL (07) DATA: 00 00 STATUS: 01 01 | |
| 1.8583 338 WRITE REG 18 (52) DATA: 80 80 STATUS: 01 01 | |
| 1.8584 339 WRITE 50_TXRX_FIFO (32) | |
| DATA: 0f 1d 01 64 64 64 00 aa 00 00 00 00 00 00 85 e4 | |
| STATUS: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 | |
| 1.8587 340 WRITE 7_RXTX_CHNL (07) DATA: 01 2D STATUS: 01 01 // tx, ch 2d | |
| 1.8640 341 WRITE 7_RXTX_CHNL (07) DATA: 00 00 STATUS: 01 01 | |
| 1.8641 342 WRITE REG 18 (52) DATA: 80 80 STATUS: 01 01 | |
| 1.8641 343 WRITE 50_TXRX_FIFO (32) | |
| DATA: 0f 1d 01 64 64 64 00 aa 00 00 00 00 00 00 85 e4 | |
| STATUS: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 | |
| 1.8645 344 WRITE 7_RXTX_CHNL (07) DATA: 01 35 STATUS: 01 01 // tx, ch 35 | |
| 1.8698 345 WRITE 7_RXTX_CHNL (07) DATA: 00 00 STATUS: 01 01 | |
| 1.8698 346 WRITE REG 18 (52) DATA: 80 80 STATUS: 01 01 | |
| 1.8699 347 WRITE 50_TXRX_FIFO (32) | |
| DATA: 0f 1d 01 64 64 64 00 aa 00 00 00 00 00 00 85 e4 | |
| STATUS: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 | |
| 1.8702 348 WRITE 7_RXTX_CHNL (07) DATA: 01 3C STATUS: 01 01 // tx, ch 3c | |
| 1.8755 349 WRITE 7_RXTX_CHNL (07) DATA: 00 00 STATUS: 01 01 | |
| 1.8756 350 WRITE REG 18 (52) DATA: 80 80 STATUS: 01 01 | |
| 1.8756 351 WRITE 50_TXRX_FIFO (32) | |
| DATA: 0f 1d 01 64 64 64 00 aa 00 00 00 00 00 00 85 e4 | |
| STATUS: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 | |
| 1.8759 352 WRITE 7_RXTX_CHNL (07) DATA: 01 46 STATUS: 01 01 // tx, ch 46 | |
| 1.8813 353 WRITE 7_RXTX_CHNL (07) DATA: 00 00 STATUS: 01 01 | |
| 1.8813 354 WRITE REG 18 (52) DATA: 80 80 STATUS: 01 01 | |
| 1.8814 355 WRITE 50_TXRX_FIFO (32) | |
| DATA: 0f 1d 01 64 64 64 00 aa 00 00 00 00 00 00 85 e4 | |
| STATUS: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 | |
| 1.8817 356 WRITE 7_RXTX_CHNL (07) DATA: 01 2D STATUS: 01 01 // tx, ch 2d ... | |
| 1.8870 357 WRITE 7_RXTX_CHNL (07) DATA: 00 00 STATUS: 01 01 | |
| 1.8871 358 WRITE REG 18 (52) DATA: 80 80 STATUS: 01 01 | |
| 1.8871 359 WRITE 50_TXRX_FIFO (32) | |
| DATA: 0f 1d 01 64 64 64 00 aa 00 00 00 00 00 00 85 e4 | |
| STATUS: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 | |
| 1.8874 360 WRITE 7_RXTX_CHNL (07) DATA: 01 35 STATUS: 01 01 | |
| 1.8928 361 WRITE 7_RXTX_CHNL (07) DATA: 00 00 STATUS: 01 01 | |
| 1.8928 362 WRITE REG 18 (52) DATA: 80 80 STATUS: 01 01 | |
| 1.8929 363 WRITE 50_TXRX_FIFO (32) | |
| DATA: 0f 1d 01 64 64 64 00 aa 00 00 00 00 00 00 85 e4 | |
| STATUS: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 | |
| 1.8932 364 WRITE 7_RXTX_CHNL (07) DATA: 01 3C STATUS: 01 01 | |
| 1.8985 365 WRITE 7_RXTX_CHNL (07) DATA: 00 00 STATUS: 01 01 | |
| 1.8985 366 WRITE REG 18 (52) DATA: 80 80 STATUS: 01 01 | |
| 1.8986 367 WRITE 50_TXRX_FIFO (32) | |
| DATA: 0f 1d 01 64 64 64 00 aa 00 00 00 00 00 00 85 e4 | |
| STATUS: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 | |
| 1.8989 368 WRITE 7_RXTX_CHNL (07) DATA: 01 46 STATUS: 01 01 | |
| 1.9043 369 WRITE 7_RXTX_CHNL (07) DATA: 00 00 STATUS: 01 01 | |
| 1.9043 370 WRITE REG 18 (52) DATA: 80 80 STATUS: 01 01 | |
| 1.9044 371 WRITE 50_TXRX_FIFO (32) | |
| DATA: 0f 1d 01 64 64 64 00 aa 00 00 00 00 00 00 85 e4 | |
| STATUS: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 | |
| 1.9047 372 WRITE 7_RXTX_CHNL (07) DATA: 01 2D STATUS: 01 01 | |
| 1.9100 373 WRITE 7_RXTX_CHNL (07) DATA: 00 00 STATUS: 01 01 | |
| 1.9100 374 WRITE REG 18 (52) DATA: 80 80 STATUS: 01 01 | |
| 1.9101 375 WRITE 50_TXRX_FIFO (32) | |
| DATA: 0f 1d 01 64 64 64 00 aa 00 00 00 00 00 00 85 e4 | |
| STATUS: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 | |
| 1.9104 376 WRITE 7_RXTX_CHNL (07) DATA: 01 35 STATUS: 01 01 | |
| 1.9157 377 WRITE 7_RXTX_CHNL (07) DATA: 00 00 STATUS: 01 01 | |
| 1.9158 378 WRITE REG 18 (52) DATA: 80 80 STATUS: 01 01 | |
| 1.9159 379 WRITE 50_TXRX_FIFO (32) | |
| DATA: 0f 1d 01 64 64 64 00 aa 00 00 00 00 00 00 85 e4 | |
| STATUS: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 | |
| 1.9162 380 WRITE 7_RXTX_CHNL (07) DATA: 01 3C STATUS: 01 01 | |
| 1.9215 381 WRITE 7_RXTX_CHNL (07) DATA: 00 00 STATUS: 01 01 | |
| 1.9215 382 WRITE REG 18 (52) DATA: 80 80 STATUS: 01 01 | |
| 1.9216 383 WRITE 50_TXRX_FIFO (32) | |
| DATA: 0f 1d 01 64 64 64 00 aa 00 00 00 00 00 00 85 e4 | |
| STATUS: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 | |
| 1.9219 384 WRITE 7_RXTX_CHNL (07) DATA: 01 46 STATUS: 01 01 | |
| 1.9272 385 WRITE 7_RXTX_CHNL (07) DATA: 00 00 STATUS: 01 01 | |
| 1.9273 386 WRITE REG 18 (52) DATA: 80 80 STATUS: 01 01 | |
| 1.9273 387 WRITE 50_TXRX_FIFO (32) | |
| DATA: 0f 1d 01 64 64 64 00 aa 00 00 00 00 00 00 85 e4 | |
| STATUS: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 | |
| 1.9277 388 WRITE 7_RXTX_CHNL (07) DATA: 01 2D STATUS: 01 01 | |
| 1.9330 389 WRITE 7_RXTX_CHNL (07) DATA: 00 00 STATUS: 01 01 | |
| 1.9330 390 WRITE REG 18 (52) DATA: 80 80 STATUS: 01 01 | |
| 1.9331 391 WRITE 50_TXRX_FIFO (32) | |
| DATA: 0f 1d 01 64 64 64 00 aa 00 00 00 00 00 00 85 e4 | |
| STATUS: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 | |
| 1.9334 392 WRITE 7_RXTX_CHNL (07) DATA: 01 35 STATUS: 01 01 | |
| 1.9387 393 WRITE 7_RXTX_CHNL (07) DATA: 00 00 STATUS: 01 01 | |
| 1.9388 394 WRITE REG 18 (52) DATA: 80 80 STATUS: 01 01 | |
| 1.9388 395 WRITE 50_TXRX_FIFO (32) | |
| DATA: 0f 1d 01 64 64 64 00 aa 00 00 00 00 00 00 85 e4 | |
| STATUS: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 | |
| 1.9392 396 WRITE 7_RXTX_CHNL (07) DATA: 01 3C STATUS: 01 01 | |
| 1.9445 397 WRITE 7_RXTX_CHNL (07) DATA: 00 00 STATUS: 01 01 | |
| 1.9445 398 WRITE REG 18 (52) DATA: 80 80 STATUS: 01 01 | |
| 1.9446 399 WRITE 50_TXRX_FIFO (32) | |
| DATA: 0f 1d 01 64 64 64 00 aa 00 00 00 00 00 00 85 e4 | |
| STATUS: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 | |
| 1.9449 400 WRITE 7_RXTX_CHNL (07) DATA: 01 46 STATUS: 01 01 | |
| 1.9502 401 WRITE 7_RXTX_CHNL (07) DATA: 00 00 STATUS: 01 01 | |
| 1.9503 402 WRITE REG 18 (52) DATA: 80 80 STATUS: 01 01 | |
| 1.9503 403 WRITE 50_TXRX_FIFO (32) | |
| DATA: 0f 1d 01 64 64 64 00 aa 00 00 00 00 00 00 85 e4 | |
| STATUS: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 | |
| 1.9507 404 WRITE 7_RXTX_CHNL (07) DATA: 01 2D STATUS: 01 01 | |
| 1.9559 405 WRITE 7_RXTX_CHNL (07) DATA: 00 00 STATUS: 01 01 | |
| 1.9560 406 WRITE REG 18 (52) DATA: 80 80 STATUS: 01 01 | |
| 1.9561 407 WRITE 50_TXRX_FIFO (32) | |
| DATA: 0f 1d 01 64 64 64 00 aa 00 00 00 00 00 00 85 e4 | |
| STATUS: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 | |
| 1.9564 408 WRITE 7_RXTX_CHNL (07) DATA: 01 35 STATUS: 01 01 | |
| 1.9617 409 WRITE 7_RXTX_CHNL (07) DATA: 00 00 STATUS: 01 01 | |
| 1.9618 410 WRITE REG 18 (52) DATA: 80 80 STATUS: 01 01 | |
| 1.9618 411 WRITE 50_TXRX_FIFO (32) | |
| DATA: 0f 1d 01 64 64 64 00 aa 00 00 00 00 00 00 85 e4 | |
| STATUS: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 | |
| 1.9622 412 WRITE 7_RXTX_CHNL (07) DATA: 01 3C STATUS: 01 01 | |
| 1.9674 413 WRITE 7_RXTX_CHNL (07) DATA: 00 00 STATUS: 01 01 | |
| 1.9675 414 WRITE REG 18 (52) DATA: 80 80 STATUS: 01 01 | |
| 1.9675 415 WRITE 50_TXRX_FIFO (32) | |
| DATA: 0f 1d 01 64 64 64 00 aa 00 00 00 00 00 00 85 e4 | |
| STATUS: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 | |
| 1.9679 416 WRITE 7_RXTX_CHNL (07) DATA: 01 46 STATUS: 01 01 | |
| 1.9732 417 WRITE 7_RXTX_CHNL (07) DATA: 00 00 STATUS: 01 01 | |
| 1.9733 418 WRITE REG 18 (52) DATA: 80 80 STATUS: 01 01 | |
| 1.9733 419 WRITE 50_TXRX_FIFO (32) | |
| DATA: 0f 1d 01 64 64 64 00 aa 00 00 00 00 00 00 85 e4 | |
| STATUS: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 | |
| 1.9736 420 WRITE 7_RXTX_CHNL (07) DATA: 01 2D STATUS: 01 01 | |
| 1.9789 421 WRITE 7_RXTX_CHNL (07) DATA: 00 00 STATUS: 01 01 | |
| 1.9790 422 WRITE REG 18 (52) DATA: 80 80 STATUS: 01 01 | |
| 1.9790 423 WRITE 50_TXRX_FIFO (32) | |
| DATA: 0f 1d 01 64 64 64 00 aa 00 00 00 00 00 00 85 e4 | |
| STATUS: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 | |
| 1.9793 424 WRITE 7_RXTX_CHNL (07) DATA: 01 35 STATUS: 01 01 | |
| 1.9843 425 WRITE 7_RXTX_CHNL (07) DATA: 00 00 STATUS: 01 01 | |
| 1.9843 426 WRITE REG 18 (52) DATA: 80 80 STATUS: 01 01 | |
| 1.9844 427 WRITE 50_TXRX_FIFO (32) | |
| DATA: 0f 1d 01 64 64 64 00 aa 00 00 00 00 00 00 85 e4 | |
| STATUS: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 | |
| 1.9847 428 WRITE 7_RXTX_CHNL (07) DATA: 01 3C STATUS: 01 01 | |
| 1.9897 429 WRITE 7_RXTX_CHNL (07) DATA: 00 00 STATUS: 01 01 | |
| 1.9897 430 WRITE REG 18 (52) DATA: 80 80 STATUS: 01 01 | |
| 1.9898 431 WRITE 50_TXRX_FIFO (32) | |
| DATA: 0f 1d 01 64 64 64 00 aa 00 00 00 00 00 00 85 e4 | |
| STATUS: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 | |
| 1.9901 432 WRITE 7_RXTX_CHNL (07) DATA: 01 46 STATUS: 01 01 | |
| 1.9951 433 WRITE 7_RXTX_CHNL (07) DATA: 00 00 STATUS: 01 01 | |
| 1.9951 434 WRITE REG 18 (52) DATA: 80 80 STATUS: 01 01 | |
| 1.9952 435 WRITE 50_TXRX_FIFO (32) | |
| DATA: 0f 1d 01 64 64 64 00 aa 00 00 00 00 00 00 85 e4 | |
| STATUS: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 | |
| 1.9955 436 WRITE 7_RXTX_CHNL (07) DATA: 01 2D STATUS: 01 01 | |
| 2.0004 437 WRITE 7_RXTX_CHNL (07) DATA: 00 00 STATUS: 01 01 | |
| 2.0005 438 WRITE REG 18 (52) DATA: 80 80 STATUS: 01 01 | |
| 2.0005 439 WRITE 50_TXRX_FIFO (32) | |
| DATA: 0f 1d 01 64 64 64 00 aa 00 00 00 00 00 00 85 e4 | |
| STATUS: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 | |
| 2.0009 440 WRITE 7_RXTX_CHNL (07) DATA: 01 35 STATUS: 01 01 | |
| 2.0058 441 WRITE 7_RXTX_CHNL (07) DATA: 00 00 STATUS: 01 01 | |
| 2.0059 442 WRITE REG 18 (52) DATA: 80 80 STATUS: 01 01 | |
| 2.0059 443 WRITE 50_TXRX_FIFO (32) | |
| DATA: 0f 1d 01 64 64 64 00 aa 00 00 00 00 00 00 85 e4 | |
| STATUS: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 | |
| 2.0062 444 WRITE 7_RXTX_CHNL (07) DATA: 01 3C STATUS: 01 01 | |
| 2.0112 445 WRITE 7_RXTX_CHNL (07) DATA: 00 00 STATUS: 01 01 | |
| 2.0113 446 WRITE REG 18 (52) DATA: 80 80 STATUS: 01 01 | |
| 2.0113 447 WRITE 50_TXRX_FIFO (32) | |
| DATA: 0f 1d 01 64 64 64 00 aa 00 00 00 00 00 00 85 e4 | |
| STATUS: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 | |
| 2.0116 448 WRITE 7_RXTX_CHNL (07) DATA: 01 46 STATUS: 01 01 | |
| 2.0166 449 WRITE 7_RXTX_CHNL (07) DATA: 00 00 STATUS: 01 01 | |
| 2.0166 450 WRITE REG 18 (52) DATA: 80 80 STATUS: 01 01 | |
| 2.0167 451 WRITE 50_TXRX_FIFO (32) | |
| DATA: 0f 1d 01 64 64 64 00 aa 00 00 00 00 00 00 85 e4 | |
| STATUS: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 | |
| 2.0170 452 WRITE 7_RXTX_CHNL (07) DATA: 01 2D STATUS: 01 01 |
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