cyrf6936_gfsk.ino

#include "iface_cyrf6936.h"
#include <util/atomic.h>

// !!!!! 3.3V Vcc & IOs !!!!!

// ############ Wiring ################
#define PPM_pin     2  // PPM in
//SPI Comm.pins with nRF24L01
#define MOSI_pin    3  // MOSI - D3
#define SCK_pin     4  // SCK  - D4
#define RST_pin     5  // CE   - D5
#define MISO_pin    A0 // MISO - A0
#define CS_pin      A1 // CS   - A1 --> /SS

// for PA+LNA module
#define TXEN_pin    A2
#define RXEN_pin    A3
#define PACTL_pin   A4

#define ledPin    13 // LED  - D13

// SPI outputs
#define MOSI_on PORTD |= _BV(3)  // PD3
#define MOSI_off PORTD &= ~_BV(3)// PD3
#define SCK_on PORTD |= _BV(4)   // PD4
#define SCK_off PORTD &= ~_BV(4) // PD4
#define RST_on PORTD |= _BV(5)    // PD5
#define RST_off PORTD &= ~_BV(5)  // PD5
#define CS_on PORTC |= _BV(1)    // PC1
#define CS_off PORTC &= ~_BV(1)  // PC1
// SPI input
#define  MISO_on (PINC & _BV(0)) // PC0

// PA+LNA control
#define TXEN_on     PORTC |= _BV(2)
#define TXEN_off    PORTC &= ~_BV(2)
#define RXEN_on     PORTC |= _BV(3)
#define RXEN_off    PORTC &= ~_BV(3)
#define PACTL_on    PORTC |= _BV(4)
#define PACTL_off   PORTC &= ~_BV(4)


#define CHANNEL 0x3c // 2460 MHz 

// DSM init values
/*
static const u8 init_vals[][2] = {
    {CYRF_02_TX_CTRL, 0x00}, // transmit err & complete interrupts disabled
    {CYRF_05_RX_CTRL, 0x00}, // receive err & complete interrupts disabled
    {CYRF_28_CLK_EN, 0x02}, // Force Receive Clock Enable, MUST be set
    {CYRF_32_AUTO_CAL_TIME, 0x3c}, // must be set to 3C
    {CYRF_35_AUTOCAL_OFFSET, 0x14}, // must be  set to 14
    {CYRF_06_RX_CFG, 0x48}, // LNA manual control, Rx Fast Turn Mode Enable 
    {CYRF_1B_TX_OFFSET_LSB, 0x55}, // Tx frequency offset LSB 
    {CYRF_1C_TX_OFFSET_MSB, 0x05}, // Tx frequency offset MSB (0x555 = +1 Mbps)
    {CYRF_0F_XACT_CFG, 0x24}, // Force End State, transaction end state = idle
    {CYRF_03_TX_CFG, 0x38 | 7}, // 64 chip codes, SDR mode, PA = +4 dBm
    {CYRF_12_DATA64_THOLD, 0x0a}, // 64 Chip Data PN Code Correlator Threshold = 10 
    {CYRF_0F_XACT_CFG, 0x04}, // Transaction End State = idle
    {CYRF_39_ANALOG_CTRL, 0x01}, // synth setting time for all channels is the same as for slow channels
    {CYRF_0F_XACT_CFG, 0x24}, //Force IDLE
    {CYRF_29_RX_ABORT, 0x00}, //Clear RX abort
    {CYRF_12_DATA64_THOLD, 0x0a}, //set pn correlation threshold
    {CYRF_10_FRAMING_CFG, 0x4a}, //set sop len and threshold
    {CYRF_29_RX_ABORT, 0x0f}, //Clear RX abort?
    {CYRF_03_TX_CFG, 0x38 | 7}, //Set 64chip, SDE mode, max-power
    {CYRF_10_FRAMING_CFG, 0x4a}, //set sop len and threshold
    {CYRF_1F_TX_OVERRIDE, 0x04}, //disable tx CRC
    {CYRF_1E_RX_OVERRIDE, 0x14}, //disable rx crc
    {CYRF_14_EOP_CTRL, 0x02}, //set EOP sync == 2
    {CYRF_01_TX_LENGTH, 0x10}, //16byte packet
};
*/

// init values for 1 Mbps GFSK
static const u8 init_vals[][2] = {
    {CYRF_02_TX_CTRL, 0x00}, // transmit err & complete interrupts disabled
    {CYRF_05_RX_CTRL, 0x00}, // receive err & complete interrupts disabled
    {CYRF_28_CLK_EN, 0x02}, // Force Receive Clock Enable, MUST be set
    {CYRF_32_AUTO_CAL_TIME, 0x3c}, // must be set to 3C
    {CYRF_35_AUTOCAL_OFFSET, 0x14}, // must be  set to 14
    {CYRF_06_RX_CFG, 0x48}, // LNA manual control, Rx Fast Turn Mode Enable
    {CYRF_1B_TX_OFFSET_LSB, 0x00}, // Tx frequency offset LSB
    {CYRF_1C_TX_OFFSET_MSB, 0x00}, // Tx frequency offset MSB
    {CYRF_0F_XACT_CFG, 0x24}, // Force End State, transaction end state = idle
    {CYRF_03_TX_CFG, 0x00 | 7}, // GFSK mode, PA = +4 dBm
    {CYRF_12_DATA64_THOLD, 0x0a}, // 64 Chip Data PN Code Correlator Threshold = 10
    {CYRF_0F_XACT_CFG, 0x04}, // Transaction End State = idle
    {CYRF_39_ANALOG_CTRL, 0x01}, // synth setting time for all channels is the same as for slow channels
    {CYRF_0F_XACT_CFG, 0x24}, //Force IDLE
    {CYRF_29_RX_ABORT, 0x00}, //Clear RX abort
    {CYRF_12_DATA64_THOLD, 0x0a}, //set pn correlation threshold
    {CYRF_10_FRAMING_CFG, 0x4a}, //set sop len and threshold
    {CYRF_29_RX_ABORT, 0x0f}, //Clear RX abort?
    {CYRF_03_TX_CFG, 0x00 | 4}, // GFSK mode, set power (0-7)
    {CYRF_10_FRAMING_CFG, 0x4a}, // 0b11000000 //set sop len and threshold
    {CYRF_1F_TX_OVERRIDE, 0x04}, //disable tx CRC
    {CYRF_1E_RX_OVERRIDE, 0x14}, //disable rx crc
    {CYRF_14_EOP_CTRL, 0x00}, //set EOP sync == 0
    {CYRF_01_TX_LENGTH, 0x10}, // payload length
};

u8 packet[40];

void setup()
{
    pinMode(ledPin, OUTPUT);
    digitalWrite(ledPin, LOW); //start LED off
    pinMode(PPM_pin, INPUT);
    pinMode(MOSI_pin, OUTPUT);
    pinMode(SCK_pin, OUTPUT);
    pinMode(CS_pin, OUTPUT);
    pinMode(RST_pin, OUTPUT);
    pinMode(MISO_pin, INPUT);
    
    pinMode(TXEN_pin, OUTPUT);
    pinMode(RXEN_pin, OUTPUT);
    pinMode(PACTL_pin, OUTPUT);

    delay(200);
    if(CYRF_Reset())
        digitalWrite(ledPin, HIGH);
        
    for(uint32_t i = 0; i < sizeof(init_vals) / 2; i++)
        CYRF_WriteRegister(init_vals[i][0], init_vals[i][1]);
    
    CYRF_WritePreamble(0x55aa01); // 55aa preamble, not repeated (01)
    CYRF_ConfigRFChannel(0x3c); // 2460 MHz
    
    CYRF_SetTxRxMode(TX_EN);
    delay(10);
}

void loop()
{
  u8 pos=0;
  static u8 tryout = 0;
  
  static u8 inc_time = millis()+1000;
  static u8 count = 0;
  
  if(millis()>= inc_time)
  {
      count++;
      inc_time = millis()+1000;
  }
  
  int16_t offset = map(analogRead(A5),0,1023,-500, 500);
  CYRF_WriteRegister(0x1b, offset & 0xff);
  CYRF_WriteRegister(0x1c, abs(offset) >> 8 | offset < 0 ? _BV(3) : 0);
  
  /*if(tryout++ % 2) {
      CYRF_WritePreamble(0xaac901); // aac9, once
      packet[pos++] = 0x8f;
      packet[pos++] = 0x9c;
      packet[pos++] = 0x42;
      packet[pos++] = 0x55;
  }
  else*/ {   
      CYRF_WritePreamble(0x555501); // aa55, once   
      packet[pos++] = 0xaa;
      packet[pos++] = 0x80;
      packet[pos++] = 0x80;
      packet[pos++] = 0x80;
      packet[pos++] = 0x80;
      packet[pos++] = count;
      /*packet[pos++] = 0x00;
      packet[pos++] = 0x80;
      packet[pos++] = 0x02;
      packet[pos++] = 0x03;
      packet[pos++] = 0x04;
      packet[pos++] = 0x05;
      packet[pos++] = 0x06;
      packet[pos++] = 0x07;
      packet[pos++] = 0x08;
      packet[pos++] = 0x09;
      packet[pos++] = 0x0a;*/
 }  
  
  for(u8 i=pos; i<16+4; i++)
    packet[i] = i%2?255:0; //i;
  
  CYRF_WriteDataPacketLen(packet, 16);
  
  delay(2);
  
}