ULX3S_BB3_SPI_test.v

module top_vgatest_640x480
(
  input clk_25mhz,
//  input clk_stm32,
//  output clk_eth,
  output [3:0] gpdi_dp,
  input [7:3] R_in,
  output [7:3] R_out,
  input [7:2] G_in, 
  output [7:2] G_out,
  input [7:3] B_in, 
  output [7:3] B_out,
  input lcd_clk_in,
  input lcd_HSYNC_in,
  input lcd_VSYNC_in,
  input lcd_DE_in,
  output lcd_clk_out,
  output lcd_HSYNC_out,
  output lcd_VSYNC_out,
  output lcd_DE_out,

  // CLK goes from STM32 to FPGA
  input spi2_in_clk, spi4_in_clk, spi5_in_clk,
  output spi2_out_clk, spi4_out_clk, spi5_out_clk,
  // MISO and IRQ goes from slaves to STM32
  output spi2_in_miso,spi4_in_miso,spi5_in_miso,spi2_in_irq,spi4_in_irq,spi5_in_irq,
  input spi2_out_miso, spi4_out_miso, spi5_out_miso,spi2_out_irq,spi4_out_irq,spi5_out_irq,
  // ALL other pins direction is from STM32 to slaves
  input spi2_in_mosi,spi2_in_csa,spi2_in_csb,
  output spi2_out_mosi,spi2_out_csa,spi2_out_csb,
  input spi4_in_mosi,spi4_in_csa,spi4_in_csb,
  output spi4_out_mosi,spi4_out_csa,spi4_out_csb,
  input spi5_in_mosi,spi5_in_csa,spi5_in_csb,
  output spi5_out_mosi,spi5_out_csa,spi5_out_csb,

  input sd_clk,sd_cmd,sd_d0,
  output sd_detect,
  input stm32_sda,stm32_scl,gpdi_sda,gpdi_scl,
  output gpdi_sda,gpdi_scl

);
    parameter C_ddr = 1'b0; // 0:SDR 1:DDR
    wire lcd_blank;
    wire [7:0] R,G,B;
    wire SD_command,SD_clock,SD_data0,SD_dtct, sda, scl;

    assign SD_clock = sd_clk;
    assign SD_command = sd_cmd;
    assign SD_data0 = sd_d0;
    assign sd_detect = 1'b0;
    //assign scl = stm32_scl;
    //assign sda = stm32_sda;
    assign gpdi_sda = stm32_sda;
    assign gpdi_scl = stm32_scl;
    assign R = { R_in[7], R_in[6], R_in[5], R_in[4], R_in[3], 1'b0, 1'b0, 1'b0 };
    assign B = { B_in[7], B_in[6], B_in[5], B_in[4], B_in[3], 1'b0, 1'b0, 1'b0 };
    assign G = { G_in[7], G_in[6], G_in[5], G_in[4], G_in[3], G_in[2], 1'b0, 1'b0 };
    assign lcd_clk_out = lcd_clk_in;
    assign lcd_HSYNC_out = lcd_HSYNC_in;
    assign lcd_VSYNC_out = ~lcd_VSYNC_in;
    assign R_out = R_in;
    assign G_out = G_in;
    assign B_out = B_in;
    assign lcd_DE_out = lcd_DE_in;
    assign lcd_blank = ~lcd_DE_in;

always @ (posedge clk_25mhz) begin
    spi2_out_clk <= spi2_in_clk;
    spi4_out_clk <= spi4_in_clk;
    spi5_out_clk <= spi5_in_clk;

    spi2_in_miso <= spi2_out_miso;
    spi2_out_mosi <= spi2_in_mosi;
    spi2_out_csa <= spi2_in_csa;
    spi2_out_csb <= spi2_in_csb;
    spi2_in_irq <= spi2_out_irq;

    spi4_in_miso <= spi4_out_miso;
    spi4_out_mosi <= spi4_in_mosi;
    spi4_out_csa <= spi4_in_csa;
    spi4_out_csb <= spi4_in_csb;
    spi4_in_irq <= spi4_out_irq;

    spi5_in_miso <= spi5_out_miso;
    spi5_out_mosi <= spi5_in_mosi;
    spi5_out_csa <= spi5_in_csa;
    spi5_out_csb <= spi5_in_csb;
    spi5_in_irq <= spi5_out_irq;   
end
/*
    assign spi2_out_clk = spi2_in_clk;
    assign spi4_out_clk = spi4_in_clk;
    assign spi5_out_clk = spi5_in_clk;

    assign spi2_in_miso = spi2_out_miso;
    assign spi2_out_mosi = spi2_in_mosi;
    assign spi2_out_csa = spi2_in_csa;
    assign spi2_out_csb = spi2_in_csb;
    assign spi2_out_irq = spi2_in_irq;

    assign spi4_in_miso = spi4_out_miso;
    assign spi4_out_mosi = spi4_in_mosi;
    assign spi4_out_csa = spi4_in_csa;
    assign spi4_out_csb = spi4_in_csb;
    assign spi4_out_irq = spi4_in_irq;

    assign spi5_in_miso = spi5_out_miso;
    assign spi5_out_mosi = spi5_in_mosi;
    assign spi5_out_csa = spi5_in_csa;
    assign spi5_out_csb = spi5_in_csb;
    assign spi5_out_irq = spi5_in_irq;    
*/
    // clock generator
    wire clk_250MHz, clk_125MHz, clk_25MHz, clk_locked;

   assign clk_eth = ~clk_25MHz;

//   clk_25_25
//   clk_25_25_instance(
//     .clk_in(sd_clk),
//     .clk_out(spi5_out_clk)
//   );



//   clk_25_25
//   clk_25_25_instance(
//     .clk_in(clk_25mhz),
//     .clk_out(clk_stm32)
//   );


//    clk_25_250_125_25
//    clock_instance
//    (
//      .clki(clk_25mhz),
//      .clko(clk_250MHz),
//      .clks1(clk_125MHz),
//      .clks2(clk_25MHz),
//      .locked(clk_locked)
//    );
    
    // shift clock choice SDR/DDR
    wire clk_pixel, clk_shift;
    assign clk_pixel = clk_25mhz;
    generate
      if(C_ddr == 1'b1)
        assign clk_shift = clk_125MHz;
      else
        assign clk_shift = clk_250MHz;
    endgenerate

    // VGA signal generator
    wire [7:0] vga_r, vga_g, vga_b;
    wire vga_hsync, vga_vsync, vga_blank;
    vga
    vga_instance
    (
      .clk_pixel(clk_pixel),
      .clk_pixel_ena(1'b1),
      .test_picture(1'b1), // enable test picture generation
      .vga_r(vga_r),
      .vga_g(vga_g),
      .vga_b(vga_b),
      .vga_hsync(vga_hsync),
      .vga_vsync(vga_vsync),
      .vga_blank(vga_blank)
);

    // VGA to digital video converter
    wire [1:0] tmds[3:0];
    vga2dvid
    #(
      .C_depth(8),
      .C_ddr(C_ddr),
      .C_shift_clock_synchronizer(1'b1)
    )
    vga2dvid_instance
    (
      .clk_pixel(clk_pixel),
      .clk_shift(clk_shift),
      .in_red(R),
      .in_green(G),
      .in_blue(B),
      .in_hsync(lcd_HSYNC_in),
      .in_vsync(lcd_VSYNC_in),  
      .in_blank(~lcd_DE_in),
//      .in_hsync(vga_hsync),
//      .in_vsync(vga_vsync),
//      .in_blank(vga_blank),
      .out_clock(tmds[3]),
      .out_red(tmds[2]),
      .out_green(tmds[1]),
      .out_blue(tmds[0])
    );

    // output TMDS SDR/DDR data to fake differential lanes
    fake_differential
    #(
      .C_ddr(C_ddr)
    )
    fake_differential_instance
    (
      .clk_shift(clk_shift),
      .in_clock(tmds[3]),
      .in_red(tmds[2]),
      .in_green(tmds[1]),
      .in_blue(tmds[0]),
      .out_p(gpdi_dp)
      //.out_n(gpdi_dn)
    );

endmodule