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gort818/hang_report

Created July 17, 2019 02:43
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hang_report
GPU hang report:
Device name: Radeon RX Vega (AMD RADV/ACO VEGA10 (LLVM 8.0.0) DRM 3.32.0 / 5.2.0-arch2-1-ARCH, LLVM 8.0.0)
Enabled debug options: allbos, vmfaults, syncshaders,
Enabled perftest options: llvm,
Last 60 lines of dmesg:
[ 4.464811] [drm] vram apper at 0xE0000000
[ 4.464812] [drm] size 14745600
[ 4.464812] [drm] fb depth is 24
[ 4.464812] [drm] pitch is 10240
[ 4.464932] fbcon: amdgpudrmfb (fb0) is primary device
[ 4.483316] ieee80211 phy0: rt2x00lib_request_firmware: Info - Loading firmware file 'rt2870.bin'
[ 4.483618] ieee80211 phy0: rt2x00lib_request_firmware: Info - Firmware detected - version: 0.36
[ 4.508030] Console: switching to colour frame buffer device 320x90
[ 4.521555] amdgpu 0000:03:00.0: fb0: amdgpudrmfb frame buffer device
[ 4.548941] amdgpu 0000:03:00.0: ring gfx uses VM inv eng 0 on hub 0
[ 4.548942] amdgpu 0000:03:00.0: ring comp_1.0.0 uses VM inv eng 1 on hub 0
[ 4.548943] amdgpu 0000:03:00.0: ring comp_1.1.0 uses VM inv eng 4 on hub 0
[ 4.548943] amdgpu 0000:03:00.0: ring comp_1.2.0 uses VM inv eng 5 on hub 0
[ 4.548944] amdgpu 0000:03:00.0: ring comp_1.3.0 uses VM inv eng 6 on hub 0
[ 4.548945] amdgpu 0000:03:00.0: ring comp_1.0.1 uses VM inv eng 7 on hub 0
[ 4.548945] amdgpu 0000:03:00.0: ring comp_1.1.1 uses VM inv eng 8 on hub 0
[ 4.548946] amdgpu 0000:03:00.0: ring comp_1.2.1 uses VM inv eng 9 on hub 0
[ 4.548947] amdgpu 0000:03:00.0: ring comp_1.3.1 uses VM inv eng 10 on hub 0
[ 4.548947] amdgpu 0000:03:00.0: ring kiq_2.1.0 uses VM inv eng 11 on hub 0
[ 4.548948] amdgpu 0000:03:00.0: ring sdma0 uses VM inv eng 0 on hub 1
[ 4.548949] amdgpu 0000:03:00.0: ring sdma1 uses VM inv eng 1 on hub 1
[ 4.548950] amdgpu 0000:03:00.0: ring uvd_0 uses VM inv eng 4 on hub 1
[ 4.548951] amdgpu 0000:03:00.0: ring uvd_enc_0.0 uses VM inv eng 5 on hub 1
[ 4.548951] amdgpu 0000:03:00.0: ring uvd_enc_0.1 uses VM inv eng 6 on hub 1
[ 4.548952] amdgpu 0000:03:00.0: ring vce0 uses VM inv eng 7 on hub 1
[ 4.548953] amdgpu 0000:03:00.0: ring vce1 uses VM inv eng 8 on hub 1
[ 4.548953] amdgpu 0000:03:00.0: ring vce2 uses VM inv eng 9 on hub 1
[ 4.548954] [drm] ECC is not present.
[ 4.548955] [drm] SRAM ECC is not present.
[ 4.549445] [drm] Initialized amdgpu 3.32.0 20150101 for 0000:03:00.0 on minor 0
[ 5.856617] kauditd_printk_skb: 24 callbacks suppressed
[ 5.856618] audit: type=1130 audit(1563328565.662:35): pid=1 uid=0 auid=4294967295 ses=4294967295 msg='unit=user-runtime-dir@973 comm="systemd" exe="/usr/lib/systemd/systemd" hostname=? addr=? terminal=? res=success'
[ 5.865092] audit: type=1006 audit(1563328565.669:36): pid=814 uid=0 old-auid=4294967295 auid=973 tty=(none) old-ses=4294967295 ses=1 res=1
[ 5.931992] audit: type=1130 audit(1563328565.736:37): pid=1 uid=0 auid=4294967295 ses=4294967295 msg='unit=user@973 comm="systemd" exe="/usr/lib/systemd/systemd" hostname=? addr=? terminal=? res=success'
[ 6.649816] audit: type=1130 audit(1563328566.456:38): pid=1 uid=0 auid=4294967295 ses=4294967295 msg='unit=udisks2 comm="systemd" exe="/usr/lib/systemd/systemd" hostname=? addr=? terminal=? res=success'
[ 6.738249] audit: type=1130 audit(1563328566.542:39): pid=1 uid=0 auid=4294967295 ses=4294967295 msg='unit=upower comm="systemd" exe="/usr/lib/systemd/systemd" hostname=? addr=? terminal=? res=success'
[ 7.363413] wlp0s20u2: authenticate with e0:b7:0a:56:6e:90
[ 7.435208] wlp0s20u2: send auth to e0:b7:0a:56:6e:90 (try 1/3)
[ 7.440026] wlp0s20u2: authenticated
[ 7.442166] wlp0s20u2: associate with e0:b7:0a:56:6e:90 (try 1/3)
[ 7.445670] wlp0s20u2: RX AssocResp from e0:b7:0a:56:6e:90 (capab=0x1411 status=0 aid=5)
[ 7.449310] wlp0s20u2: associated
[ 7.479076] IPv6: ADDRCONF(NETDEV_CHANGE): wlp0s20u2: link becomes ready
[ 9.413015] audit: type=1131 audit(1563328569.219:40): pid=1 uid=0 auid=4294967295 ses=4294967295 msg='unit=systemd-rfkill comm="systemd" exe="/usr/lib/systemd/systemd" hostname=? addr=? terminal=? res=success'
[ 14.007220] audit: type=1131 audit(1563328573.812:41): pid=1 uid=0 auid=4294967295 ses=4294967295 msg='unit=NetworkManager-dispatcher comm="systemd" exe="/usr/lib/systemd/systemd" hostname=? addr=? terminal=? res=success'
[ 14.433058] audit: type=1006 audit(1563328574.239:42): pid=916 uid=0 old-auid=4294967295 auid=1000 tty=(none) old-ses=4294967295 ses=2 res=1
[ 14.446679] audit: type=1130 audit(1563328574.252:43): pid=1 uid=0 auid=4294967295 ses=4294967295 msg='unit=user-runtime-dir@1000 comm="systemd" exe="/usr/lib/systemd/systemd" hostname=? addr=? terminal=? res=success'
[ 14.451036] audit: type=1006 audit(1563328574.256:44): pid=920 uid=0 old-auid=4294967295 auid=1000 tty=(none) old-ses=4294967295 ses=3 res=1
[ 14.500340] audit: type=1130 audit(1563328574.306:45): pid=1 uid=0 auid=4294967295 ses=4294967295 msg='unit=user@1000 comm="systemd" exe="/usr/lib/systemd/systemd" hostname=? addr=? terminal=? res=success'
[ 16.431397] input: GaminggearUhidKeyboard as /devices/virtual/misc/uhid/0003:1E7D:FFFF.0005/input/input23
[ 16.431519] hid-generic 0003:1E7D:FFFF.0005: input,hidraw4: USB HID v0.01 Keyboard [GaminggearUhidKeyboard] on
[ 16.431694] input: GaminggearUhidMouse as /devices/virtual/misc/uhid/0003:1E7D:FFFF.0006/input/input24
[ 16.431764] hid-generic 0003:1E7D:FFFF.0006: input,hidraw5: USB HID v0.01 Mouse [GaminggearUhidMouse] on
[ 16.431947] input: GaminggearUhidMultimedia as /devices/virtual/misc/uhid/0003:1E7D:FFFF.0007/input/input25
[ 16.431996] hid-generic 0003:1E7D:FFFF.0007: input,hidraw6: USB HID v0.01 Device [GaminggearUhidMultimedia] on
[ 16.582374] audit: type=1130 audit(1563328576.389:46): pid=1 uid=0 auid=4294967295 ses=4294967295 msg='unit=rtkit-daemon comm="systemd" exe="/usr/lib/systemd/systemd" hostname=? addr=? terminal=? res=success'
[ 24.804445] audit: type=1131 audit(1563328584.609:47): pid=1 uid=0 auid=4294967295 ses=4294967295 msg='unit=user@973 comm="systemd" exe="/usr/lib/systemd/systemd" hostname=? addr=? terminal=? res=success'
[ 24.810994] audit: type=1131 audit(1563328584.616:48): pid=1 uid=0 auid=4294967295 ses=4294967295 msg='unit=user-runtime-dir@973 comm="systemd" exe="/usr/lib/systemd/systemd" hostname=? addr=? terminal=? res=success'
[ 34.119390] audit: type=1131 audit(1563328593.926:49): pid=1 uid=0 auid=4294967295 ses=4294967295 msg='unit=systemd-hostnamed comm="systemd" exe="/usr/lib/systemd/systemd" hostname=? addr=? terminal=? res=success'
[ 46.093421] fuse: init (API version 7.31)
Memory-mapped registers:
GRBM_STATUS <- ME0PIPE0_CMDFIFO_AVAIL = 8
RSMU_RQ_PENDING = 1
ME0PIPE0_CF_RQ_PENDING = 0
ME0PIPE0_PF_RQ_PENDING = 0
GDS_DMA_RQ_PENDING = 0
DB_CLEAN = 1
CB_CLEAN = 1
TA_BUSY = 0
GDS_BUSY = 0
WD_BUSY_NO_DMA = 0
VGT_BUSY = 0
IA_BUSY_NO_DMA = 0
IA_BUSY = 0
SX_BUSY = 0
WD_BUSY = 0
SPI_BUSY = 1
BCI_BUSY = 0
SC_BUSY = 0
PA_BUSY = 0
DB_BUSY = 0
CP_COHERENCY_BUSY = 0
CP_BUSY = 1
CB_BUSY = 0
GUI_ACTIVE = 1
GRBM_STATUS2 <- ME0PIPE1_CMDFIFO_AVAIL = 8
ME0PIPE1_CF_RQ_PENDING = 0
ME0PIPE1_PF_RQ_PENDING = 0
ME1PIPE0_RQ_PENDING = 0
ME1PIPE1_RQ_PENDING = 0
ME1PIPE2_RQ_PENDING = 0
ME1PIPE3_RQ_PENDING = 0
ME2PIPE0_RQ_PENDING = 0
ME2PIPE1_RQ_PENDING = 0
ME2PIPE2_RQ_PENDING = 0
ME2PIPE3_RQ_PENDING = 0
RLC_RQ_PENDING = 0
UTCL2_BUSY = 0
EA_BUSY = 0
RMI_BUSY = 0
UTCL2_RQ_PENDING = 0
CPF_RQ_PENDING = 0
EA_LINK_BUSY = 0
RLC_BUSY = 0
TC_BUSY = 0
TCC_CC_RESIDENT = 0
CPF_BUSY = 1
CPC_BUSY = 0
CPG_BUSY = 1
CPAXI_BUSY = 0
GRBM_STATUS_SE0 <- DB_CLEAN = 1
CB_CLEAN = 1
RMI_BUSY = 0
BCI_BUSY = 0
VGT_BUSY = 0
PA_BUSY = 0
TA_BUSY = 0
SX_BUSY = 0
SPI_BUSY = 1
SC_BUSY = 0
DB_BUSY = 0
CB_BUSY = 0
GRBM_STATUS_SE1 <- DB_CLEAN = 1
CB_CLEAN = 1
RMI_BUSY = 0
BCI_BUSY = 0
VGT_BUSY = 0
PA_BUSY = 0
TA_BUSY = 0
SX_BUSY = 0
SPI_BUSY = 1
SC_BUSY = 0
DB_BUSY = 0
CB_BUSY = 0
GRBM_STATUS_SE2 <- DB_CLEAN = 1
CB_CLEAN = 1
RMI_BUSY = 0
BCI_BUSY = 0
VGT_BUSY = 0
PA_BUSY = 0
TA_BUSY = 0
SX_BUSY = 0
SPI_BUSY = 1
SC_BUSY = 0
DB_BUSY = 0
CB_BUSY = 0
GRBM_STATUS_SE3 <- DB_CLEAN = 1
CB_CLEAN = 1
RMI_BUSY = 0
BCI_BUSY = 0
VGT_BUSY = 0
PA_BUSY = 0
TA_BUSY = 0
SX_BUSY = 0
SPI_BUSY = 1
SC_BUSY = 0
DB_BUSY = 0
CB_BUSY = 0
CP_STAT <- ROQ_RING_BUSY = 1
ROQ_INDIRECT1_BUSY = 1
ROQ_INDIRECT2_BUSY = 0
ROQ_STATE_BUSY = 0
DC_BUSY = 0
UTCL2IU_BUSY = 0
PFP_BUSY = 1
MEQ_BUSY = 1
ME_BUSY = 1
QUERY_BUSY = 0
SEMAPHORE_BUSY = 0
INTERRUPT_BUSY = 0
SURFACE_SYNC_BUSY = 0
DMA_BUSY = 0
RCIU_BUSY = 0
SCRATCH_RAM_BUSY = 1
CE_BUSY = 0
TCIU_BUSY = 0
ROQ_CE_RING_BUSY = 0
ROQ_CE_INDIRECT1_BUSY = 0
ROQ_CE_INDIRECT2_BUSY = 0
CP_BUSY = 1
CP_STALLED_STAT1 <- RBIU_TO_DMA_NOT_RDY_TO_RCV = 0
RBIU_TO_SEM_NOT_RDY_TO_RCV = 0
RBIU_TO_MEMWR_NOT_RDY_TO_RCV = 0
ME_HAS_ACTIVE_CE_BUFFER_FLAG = 1
ME_HAS_ACTIVE_DE_BUFFER_FLAG = 1
ME_STALLED_ON_TC_WR_CONFIRM = 0
ME_STALLED_ON_ATOMIC_RTN_DATA = 0
ME_WAITING_ON_TC_READ_DATA = 0
ME_WAITING_ON_REG_READ_DATA = 0
RCIU_WAITING_ON_GDS_FREE = 0
RCIU_WAITING_ON_GRBM_FREE = 0
RCIU_WAITING_ON_VGT_FREE = 0
RCIU_STALLED_ON_ME_READ = 0
RCIU_STALLED_ON_DMA_READ = 0
RCIU_STALLED_ON_APPEND_READ = 0
RCIU_HALTED_BY_REG_VIOLATION = 0
CP_STALLED_STAT2 <- PFP_TO_CSF_NOT_RDY_TO_RCV = 0
PFP_TO_MEQ_NOT_RDY_TO_RCV = 0
PFP_TO_RCIU_NOT_RDY_TO_RCV = 0
PFP_TO_VGT_WRITES_PENDING = 0
PFP_RCIU_READ_PENDING = 0
PFP_WAITING_ON_BUFFER_DATA = 0
ME_WAIT_ON_CE_COUNTER = 0
ME_WAIT_ON_AVAIL_BUFFER = 0
GFX_CNTX_NOT_AVAIL_TO_ME = 0
ME_RCIU_NOT_RDY_TO_RCV = 0
ME_TO_CONST_NOT_RDY_TO_RCV = 0
ME_WAITING_DATA_FROM_PFP = 0
ME_WAITING_ON_PARTIAL_FLUSH = 1
MEQ_TO_ME_NOT_RDY_TO_RCV = 1
STQ_TO_ME_NOT_RDY_TO_RCV = 0
ME_WAITING_DATA_FROM_STQ = 0
PFP_STALLED_ON_TC_WR_CONFIRM = 0
PFP_STALLED_ON_ATOMIC_RTN_DATA = 0
EOPD_FIFO_NEEDS_SC_EOP_DONE = 0
EOPD_FIFO_NEEDS_WR_CONFIRM = 0
STRMO_WR_OF_PRIM_DATA_PENDING = 0
PIPE_STATS_WR_DATA_PENDING = 0
APPEND_RDY_WAIT_ON_CS_DONE = 0
APPEND_RDY_WAIT_ON_PS_DONE = 0
APPEND_WAIT_ON_WR_CONFIRM = 0
APPEND_ACTIVE_PARTITION = 0
APPEND_WAITING_TO_SEND_MEMWRITE = 0
SURF_SYNC_NEEDS_IDLE_CNTXS = 0
SURF_SYNC_NEEDS_ALL_CLEAN = 0
CP_STALLED_STAT3 <- CE_TO_CSF_NOT_RDY_TO_RCV = 0
CE_TO_RAM_INIT_FETCHER_NOT_RDY_TO_RCV = 0
CE_WAITING_ON_DATA_FROM_RAM_INIT_FETCHER = 0
CE_TO_RAM_INIT_NOT_RDY = 0
CE_TO_RAM_DUMP_NOT_RDY = 0
CE_TO_RAM_WRITE_NOT_RDY = 0
CE_TO_INC_FIFO_NOT_RDY_TO_RCV = 0
CE_TO_WR_FIFO_NOT_RDY_TO_RCV = 0
CE_WAITING_ON_BUFFER_DATA = 0
CE_WAITING_ON_CE_BUFFER_FLAG = 0
CE_WAITING_ON_DE_COUNTER = 0
CE_WAITING_ON_DE_COUNTER_UNDERFLOW = 0
TCIU_WAITING_ON_FREE = 0
TCIU_WAITING_ON_TAGS = 0
CE_STALLED_ON_TC_WR_CONFIRM = 0
CE_STALLED_ON_ATOMIC_RTN_DATA = 0
UTCL2IU_WAITING_ON_FREE = 0
UTCL2IU_WAITING_ON_TAGS = 0
UTCL1_WAITING_ON_TRANS = 0
CP_CPC_STATUS <- MEC1_BUSY = 0
MEC2_BUSY = 0
DC0_BUSY = 0
DC1_BUSY = 0
RCIU1_BUSY = 0
RCIU2_BUSY = 0
ROQ1_BUSY = 0
ROQ2_BUSY = 0
TCIU_BUSY = 0
SCRATCH_RAM_BUSY = 0
QU_BUSY = 0
UTCL2IU_BUSY = 0
SAVE_RESTORE_BUSY = 0
CPG_CPC_BUSY = 0
CPF_CPC_BUSY = 0
CPC_BUSY = 0
CP_CPC_STALLED_STAT1 <- RCIU_TX_FREE_STALL = 0
RCIU_PRIV_VIOLATION = 0
TCIU_TX_FREE_STALL = 0
MEC1_DECODING_PACKET = 0
MEC1_WAIT_ON_RCIU = 0
MEC1_WAIT_ON_RCIU_READ = 0
MEC1_WAIT_ON_ROQ_DATA = 0
MEC2_DECODING_PACKET = 0
MEC2_WAIT_ON_RCIU = 0
MEC2_WAIT_ON_RCIU_READ = 0
MEC2_WAIT_ON_ROQ_DATA = 0
UTCL2IU_WAITING_ON_FREE = 0
UTCL2IU_WAITING_ON_TAGS = 0
UTCL1_WAITING_ON_TRANS = 0
CP_CPF_STATUS <- POST_WPTR_GFX_BUSY = 1
CSF_BUSY = 1
ROQ_ALIGN_BUSY = 0
ROQ_RING_BUSY = 1
ROQ_INDIRECT1_BUSY = 1
ROQ_INDIRECT2_BUSY = 0
ROQ_STATE_BUSY = 0
ROQ_CE_RING_BUSY = 0
ROQ_CE_INDIRECT1_BUSY = 0
ROQ_CE_INDIRECT2_BUSY = 0
SEMAPHORE_BUSY = 0
INTERRUPT_BUSY = 0
TCIU_BUSY = 0
HQD_BUSY = 0
PRT_BUSY = 0
UTCL2IU_BUSY = 0
CPF_GFX_BUSY = 1
CPF_CMP_BUSY = 0
GRBM_CPF_STAT_BUSY = 3
CPC_CPF_BUSY = 0
CPF_BUSY = 1
CP_CPF_BUSY_STAT <- REG_BUS_FIFO_BUSY = 0
CSF_RING_BUSY = 1
CSF_INDIRECT1_BUSY = 1
CSF_INDIRECT2_BUSY = 0
CSF_STATE_BUSY = 0
CSF_CE_INDR1_BUSY = 0
CSF_CE_INDR2_BUSY = 0
CSF_ARBITER_BUSY = 0
CSF_INPUT_BUSY = 0
OUTSTANDING_READ_TAGS = 0
HPD_PROCESSING_EOP_BUSY = 0
HQD_DISPATCH_BUSY = 0
HQD_IQ_TIMER_BUSY = 0
HQD_DMA_OFFLOAD_BUSY = 0
HQD_WAIT_SEMAPHORE_BUSY = 0
HQD_SIGNAL_SEMAPHORE_BUSY = 0
HQD_MESSAGE_BUSY = 0
HQD_PQ_FETCHER_BUSY = 0
HQD_IB_FETCHER_BUSY = 0
HQD_IQ_FETCHER_BUSY = 0
HQD_EOP_FETCHER_BUSY = 0
HQD_CONSUMED_RPTR_BUSY = 0
HQD_FETCHER_ARB_BUSY = 0
HQD_ROQ_ALIGN_BUSY = 0
HQD_ROQ_EOP_BUSY = 0
HQD_ROQ_IQ_BUSY = 0
HQD_ROQ_PQ_BUSY = 0
HQD_ROQ_IB_BUSY = 0
HQD_WPTR_POLL_BUSY = 0
HQD_PQ_BUSY = 0
HQD_IB_BUSY = 0
CP_CPF_STALLED_STAT1 <- RING_FETCHING_DATA = 1
INDR1_FETCHING_DATA = 1
INDR2_FETCHING_DATA = 0
STATE_FETCHING_DATA = 0
TCIU_WAITING_ON_FREE = 0
TCIU_WAITING_ON_TAGS = 0
UTCL2IU_WAITING_ON_FREE = 0
UTCL2IU_WAITING_ON_TAGS = 0
GFX_UTCL1_WAITING_ON_TRANS = 0
CMP_UTCL1_WAITING_ON_TRANS = 0
RCIU_WAITING_ON_FREE = 0
Vertex Shader as VS:
LLVM IR:
; ModuleID = 'mesa-shader'
source_filename = "mesa-shader"
target datalayout = "e-p:64:64-p1:64:64-p2:32:32-p3:32:32-p4:64:64-p5:32:32-p6:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-S32-A5"
target triple = "amdgcn-mesa-mesa3d"
define amdgpu_vs void @main(i32 inreg, i32 inreg, i32, i32, i32, i32) #0 {
main_body:
%6 = icmp eq i32 %2, 2
%7 = icmp eq i32 %2, 1
%8 = select i1 %6, i32 1065353216, i32 -1082130432
%9 = select i1 %7, i32 1065353216, i32 -1082130432
%10 = bitcast i32 %8 to float
%11 = bitcast i32 %9 to float
call void @llvm.amdgcn.exp.f32(i32 12, i32 15, float %10, float %11, float 0.000000e+00, float 1.000000e+00, i1 true, i1 false) #2
ret void
}
; Function Attrs: nounwind readnone speculatable
declare i8 addrspace(4)* @llvm.amdgcn.implicit.buffer.ptr() #1
; Function Attrs: nounwind
declare void @llvm.amdgcn.exp.f32(i32, i32, float, float, float, float, i1, i1) #2
attributes #0 = { "amdgpu-32bit-address-high-bits"="0xffff8000" }
attributes #1 = { nounwind readnone speculatable }
attributes #2 = { nounwind }
DISASM:
main:
BB4_0:
v_cmp_eq_u32_e32 vcc, 2, v0 ; 7D940082
v_cndmask_b32_e64 v1, -1.0, 1.0, vcc ; D1000001 01A9E4F3
v_cmp_eq_u32_e32 vcc, 1, v0 ; 7D940081
v_cndmask_b32_e64 v0, -1.0, 1.0, vcc ; D1000000 01A9E4F3
v_mov_b32_e32 v2, 1.0 ; 7E0402F2
v_mov_b32_e32 v3, 0 ; 7E060280
exp pos0 v1, v0, v3, v2 done ; C40008CF 02030001
s_endpgm ; BF810000
Vertex Shader as VS:
*** SHADER STATS ***
SGPRS: 8
VGPRS: 4
Spilled SGPRs: 0
Spilled VGPRs: 0
PrivMem VGPRS: 0
Code Size: 64 bytes
LDS: 0 blocks
Scratch: 0 bytes per wave
Max Waves: 10
********************
Pixel Shader:
LLVM IR:
(null)
DISASM:
(null)
Pixel Shader:
*** SHADER CONFIG ***
SPI_PS_INPUT_ADDR = 0x0000
SPI_PS_INPUT_ENA = 0x0002
*** SHADER STATS ***
SGPRS: 8
VGPRS: 4
Spilled SGPRs: 0
Spilled VGPRs: 0
PrivMem VGPRS: 0
Code Size: 32 bytes
LDS: 0 blocks
Scratch: 0 bytes per wave
Max Waves: 10
********************
sh: umr: command not found
The number of active waves = 0
List of descriptors:
** descriptor set (0) **
va: 0xffff8000003f0400
size: 32
mapped_ptr:
[0x0] = 0x49c00000
[0x1] = 0x00028001
[0x2] = 0x00120000
[0x3] = 0x00014204
[0x4] = 0x106b0000
[0x5] = 0x00018001
[0x6] = 0x00001200
[0x7] = 0x0000c204
*** layout ***
binding_count: 7
size: 32
shader_stages: 20
dynamic_shader_stages: 20
buffer_count: 7
dynamic_offset_count: 5
**** binding layout (0) ****
type: UNIFORM_BUFFER_DYNAMIC
array_size: 1
offset: 0
buffer_offset: 0
dynamic_offset_offset: 0
dynamic_offset_count: 1
size: 0
immutable_samplers_offset: 0
immutable_samplers_equal: 0
**** binding layout (1) ****
type: UNIFORM_BUFFER_DYNAMIC
array_size: 1
offset: 0
buffer_offset: 1
dynamic_offset_offset: 1
dynamic_offset_count: 1
size: 0
immutable_samplers_offset: 0
immutable_samplers_equal: 0
**** binding layout (2) ****
type: UNIFORM_BUFFER_DYNAMIC
array_size: 1
offset: 0
buffer_offset: 2
dynamic_offset_offset: 2
dynamic_offset_count: 1
size: 0
immutable_samplers_offset: 0
immutable_samplers_equal: 0
**** binding layout (3) ****
type: UNIFORM_BUFFER_DYNAMIC
array_size: 1
offset: 0
buffer_offset: 3
dynamic_offset_offset: 3
dynamic_offset_count: 1
size: 0
immutable_samplers_offset: 0
immutable_samplers_equal: 0
**** binding layout (4) ****
type: STORAGE_BUFFER_DYNAMIC
array_size: 1
offset: 0
buffer_offset: 4
dynamic_offset_offset: 4
dynamic_offset_count: 1
size: 0
immutable_samplers_offset: 0
immutable_samplers_equal: 0
**** binding layout (5) ****
type: STORAGE_TEXEL_BUFFER
array_size: 1
offset: 0
buffer_offset: 5
dynamic_offset_offset: 5
dynamic_offset_count: 0
size: 16
immutable_samplers_offset: 0
immutable_samplers_equal: 0
 Buffer:
SQ_BUF_RSRC_WORD0 <- 0x49c00000
SQ_BUF_RSRC_WORD1 <- BASE_ADDRESS_HI = 0x8001
STRIDE = 2
CACHE_SWIZZLE = 0
SWIZZLE_ENABLE = 0
SQ_BUF_RSRC_WORD2 <- 0x00120000
SQ_BUF_RSRC_WORD3 <- DST_SEL_X = SQ_SEL_X
DST_SEL_Y = SQ_SEL_0
DST_SEL_Z = SQ_SEL_0
DST_SEL_W = SQ_SEL_1
NUM_FORMAT = BUF_NUM_FORMAT_UINT
DATA_FORMAT = BUF_DATA_FORMAT_16
USER_VM_ENABLE = 0
USER_VM_MODE = 0
INDEX_STRIDE = 0
ADD_TID_ENABLE = 0
NV = 0
TYPE = SQ_RSRC_BUF
**** binding layout (6) ****
type: STORAGE_TEXEL_BUFFER
array_size: 1
offset: 16
buffer_offset: 6
dynamic_offset_offset: 5
dynamic_offset_count: 0
size: 16
immutable_samplers_offset: 0
immutable_samplers_equal: 0
 Buffer:
SQ_BUF_RSRC_WORD0 <- 0x106b0000
SQ_BUF_RSRC_WORD1 <- BASE_ADDRESS_HI = 0x8001
STRIDE = 1
CACHE_SWIZZLE = 0
SWIZZLE_ENABLE = 0
SQ_BUF_RSRC_WORD2 <- 4608 (0x00001200)
SQ_BUF_RSRC_WORD3 <- DST_SEL_X = SQ_SEL_X
DST_SEL_Y = SQ_SEL_0
DST_SEL_Z = SQ_SEL_0
DST_SEL_W = SQ_SEL_1
NUM_FORMAT = BUF_NUM_FORMAT_UINT
DATA_FORMAT = BUF_DATA_FORMAT_8
USER_VM_ENABLE = 0
USER_VM_MODE = 0
INDEX_STRIDE = 0
ADD_TID_ENABLE = 0
NV = 0
TYPE = SQ_RSRC_BUF
Compute Shader:
SPIRV (sha1: 8ae4eb62531d145f7ec2007f8b73d39b1760bac0):
gamemodeauto:
error: Invalid SPIR-V magic number '122838e0'.
NIR:
shader: MESA_SHADER_COMPUTE
local-size: 4, 4, 4
shared-size: 1
inputs: 0
outputs: 0
uniforms: 0
shared: 0
decl_var ubo INTERP_MODE_NONE cb0_t cb0 (429, 0, 0)
decl_var ubo INTERP_MODE_NONE cb4_t cb4 (429, 0, 1)
decl_var ubo INTERP_MODE_NONE cb7_t cb7 (429, 0, 2)
decl_var ssbo INTERP_MODE_NONE readonly t0_t t0 (429, 0, 3)
decl_var ssbo INTERP_MODE_NONE readonly t1_t t1 (429, 0, 4)
decl_var uniform INTERP_MODE_NONE sampler2D t2 (429, 0, 5)
decl_var uniform INTERP_MODE_NONE writeonly uimage3D u0 (429, 0, 6)
decl_function main (0 params)
impl main {
decl_var INTERP_MODE_NONE vec4 r6
decl_var INTERP_MODE_NONE vec4 r1
decl_var INTERP_MODE_NONE vec4 r2
decl_var INTERP_MODE_NONE vec4 r0
decl_var INTERP_MODE_NONE vec4 r3
decl_var INTERP_MODE_NONE vec4 r5
decl_var INTERP_MODE_NONE vec4 r4
block block_0:
/* preds: */
vec1 32 ssa_0 = load_const (0x00000000 /* 0.000000 */)
vec1 32 ssa_1 = load_const (0x00000002 /* 0.000000 */)
vec1 32 ssa_2 = load_const (0x3f800000 /* 1.000000 */)
vec1 32 ssa_3 = load_const (0xbf000000 /* -0.500000 */)
vec1 32 ssa_4 = load_const (0xbfc00000 /* -1.500000 */)
vec1 32 ssa_5 = load_const (0x4253ee82 /* 52.982918 */)
vec1 32 ssa_6 = load_const (0x3d897143 /* 0.067111 */)
vec1 32 ssa_7 = load_const (0x3bbf4590 /* 0.005837 */)
vec1 32 ssa_8 = load_const (0x3f000000 /* 0.500000 */)
vec1 32 ssa_9 = load_const (0x3fc00000 /* 1.500000 */)
vec1 32 ssa_10 = load_const (0x43000000 /* 128.000000 */)
vec3 32 ssa_11 = intrinsic load_work_group_id () ()
vec3 32 ssa_12 = intrinsic load_local_invocation_id () ()
vec1 32 ssa_13 = ishl ssa_11.x, ssa_1
vec1 32 ssa_14 = ishl ssa_11.y, ssa_1
vec1 32 ssa_15 = ishl ssa_11.z, ssa_1
vec1 32 ssa_16 = iadd ssa_13, ssa_12.x
vec1 32 ssa_17 = iadd ssa_14, ssa_12.y
vec1 32 ssa_18 = iadd ssa_15, ssa_12.z
vec1 32 ssa_19 = u2f32 ssa_16
vec1 32 ssa_20 = u2f32 ssa_17
vec1 32 ssa_21 = u2f32 ssa_18
vec1 32 ssa_22 = fadd ssa_19, ssa_8
vec1 32 ssa_23 = fadd ssa_20, ssa_8
vec1 32 ssa_24 = intrinsic vulkan_resource_index (ssa_0) (0, 1, 6) /* desc-set=0 */ /* binding=1 */ /* desc_type=UBO */
vec1 32 ssa_25 = load_const (0x00000010 /* 0.000000 */)
vec2 32 ssa_26 = intrinsic load_ubo (ssa_24, ssa_25) (0, 4, 0) /* access=0 */ /* align_mul=4 */ /* align_offset=0 */
vec1 32 ssa_27 = fmul ssa_22, ssa_26.x
vec1 32 ssa_28 = fmul ssa_23, ssa_26.y
vec1 32 ssa_29 = fneg ssa_27
vec1 32 ssa_30 = fadd ssa_29, ssa_2
vec1 32 ssa_31 = fneg ssa_28
vec1 32 ssa_32 = fadd ssa_31, ssa_30
vec1 32 ssa_33 = load_const (0x00000050 /* 0.000000 */)
vec3 32 ssa_34 = intrinsic load_ubo (ssa_24, ssa_33) (0, 4, 0) /* access=0 */ /* align_mul=4 */ /* align_offset=0 */
vec1 32 ssa_35 = fmul ssa_28, ssa_34.x
vec1 32 ssa_36 = fmul ssa_28, ssa_34.y
vec1 32 ssa_37 = fmul ssa_28, ssa_34.z
vec1 32 ssa_38 = load_const (0x00000040 /* 0.000000 */)
vec3 32 ssa_39 = intrinsic load_ubo (ssa_24, ssa_38) (0, 4, 0) /* access=0 */ /* align_mul=4 */ /* align_offset=0 */
vec1 32 ssa_40 = fmul ssa_27, ssa_39.x
vec1 32 ssa_41 = fadd ssa_40, ssa_35
vec1 32 ssa_42 = fmul ssa_27, ssa_39.y
vec1 32 ssa_43 = fadd ssa_42, ssa_36
vec1 32 ssa_44 = fmul ssa_27, ssa_39.z
vec1 32 ssa_45 = fadd ssa_44, ssa_37
vec1 32 ssa_46 = load_const (0x00000030 /* 0.000000 */)
vec3 32 ssa_47 = intrinsic load_ubo (ssa_24, ssa_46) (0, 4, 0) /* access=0 */ /* align_mul=4 */ /* align_offset=0 */
vec1 32 ssa_48 = fmul ssa_32, ssa_47.x
vec1 32 ssa_49 = fadd ssa_48, ssa_41
vec1 32 ssa_50 = fmul ssa_32, ssa_47.y
vec1 32 ssa_51 = fadd ssa_50, ssa_43
vec1 32 ssa_52 = fmul ssa_32, ssa_47.z
vec1 32 ssa_53 = fadd ssa_52, ssa_45
vec1 32 ssa_54 = load_const (0x000000e0 /* 0.000000 */)
vec3 32 ssa_55 = intrinsic load_ubo (ssa_24, ssa_54) (0, 4, 0) /* access=0 */ /* align_mul=4 */ /* align_offset=0 */
vec1 32 ssa_56 = fmul ssa_55.x, ssa_49
vec1 32 ssa_57 = fmul ssa_55.y, ssa_51
vec1 32 ssa_58 = fadd ssa_56, ssa_57
vec1 32 ssa_59 = fmul ssa_55.z, ssa_53
vec1 32 ssa_60 = fadd ssa_58, ssa_59
vec1 32 ssa_61 = frcp ssa_60
vec1 32 ssa_62 = fmul ssa_49, ssa_61
vec1 32 ssa_63 = fmul ssa_51, ssa_61
vec1 32 ssa_64 = fmul ssa_53, ssa_61
vec1 32 ssa_65 = fmul ssa_19, ssa_10
vec1 32 ssa_66 = fmul ssa_20, ssa_10
vec1 32 ssa_67 = f2u32 ssa_65
vec1 32 ssa_68 = f2u32 ssa_66
vec1 32 ssa_69 = u2f32 ssa_67
vec1 32 ssa_70 = u2f32 ssa_68
vec1 32 ssa_71 = fadd ssa_69, ssa_8
vec1 32 ssa_72 = fadd ssa_70, ssa_9
vec1 32 ssa_73 = fmul ssa_71, ssa_6
vec1 32 ssa_74 = fmul ssa_72, ssa_7
vec1 32 ssa_75 = fadd ssa_73, ssa_74
vec1 32 ssa_76 = ffract ssa_75
vec1 32 ssa_77 = fmul ssa_76, ssa_5
vec1 32 ssa_78 = ffract ssa_77
vec1 32 ssa_79 = fneg ssa_78
vec1 32 ssa_80 = fadd ssa_79, ssa_21
vec1 32 ssa_81 = fadd ssa_80, ssa_3
vec1 32 ssa_82 = fadd ssa_80, ssa_4
vec1 32 ssa_83 = intrinsic vulkan_resource_index (ssa_0) (0, 0, 6) /* desc-set=0 */ /* binding=0 */ /* desc_type=UBO */
vec3 32 ssa_84 = intrinsic load_ubo (ssa_83, ssa_0) (0, 4, 0) /* access=0 */ /* align_mul=4 */ /* align_offset=0 */
vec1 32 ssa_85 = fmul ssa_81, ssa_84.z
vec1 32 ssa_86 = fmul ssa_82, ssa_84.z
vec1 32 ssa_87 = fsat ssa_85
vec1 32 ssa_88 = fsat ssa_86
vec1 32 ssa_89 = fmul ssa_87, ssa_87
vec1 32 ssa_90 = fmul ssa_88, ssa_88
vec1 32 ssa_91 = fmul ssa_89, ssa_87
vec1 32 ssa_92 = fmul ssa_90, ssa_88
vec1 32 ssa_93 = fmul ssa_84.y, ssa_91
vec1 32 ssa_94 = fadd ssa_93, ssa_84.x
vec1 32 ssa_95 = fmul ssa_84.y, ssa_92
vec1 32 ssa_96 = fadd ssa_95, ssa_84.x
vec1 32 ssa_97 = fmul ssa_62, ssa_94
vec1 32 ssa_98 = fmul ssa_63, ssa_94
vec1 32 ssa_99 = fmul ssa_64, ssa_94
vec1 32 ssa_100 = fadd ssa_84.x, ssa_84.y
vec2 32 ssa_101 = vec2 ssa_16, ssa_17
vec1 32 ssa_102 = deref_var &t2 (uniform sampler2D)
vec4 32 ssa_103 = txf ssa_102 (texture_deref), ssa_101 (coord), ssa_0 (lod), 0 (sampler)
vec1 32 ssa_104 = fmul ssa_103.x, ssa_100
vec1 1 ssa_105 = flt ssa_96, ssa_104
vec1 32 ssa_106 = b2i32 ssa_105
vec1 32 ssa_107 = ineg ssa_106
vec1 32 ssa_108 = intrinsic vulkan_resource_index (ssa_0) (0, 2, 6) /* desc-set=0 */ /* binding=2 */ /* desc_type=UBO */
vec1 32 ssa_109 = intrinsic load_ubo (ssa_108, ssa_0) (0, 4, 0) /* access=0 */ /* align_mul=4 */ /* align_offset=0 */
vec1 32 ssa_110 = iand ssa_107, ssa_109
/* succs: block_1 */
loop {
block block_1:
/* preds: block_0 block_29 */
vec1 32 ssa_111 = phi block_0: ssa_0, block_29: ssa_265
vec1 1 ssa_112 = uge ssa_111, ssa_110
/* succs: block_2 block_3 */
if ssa_112 {
block block_2:
/* preds: block_1 */
break
/* succs: block_30 */
} else {
block block_3:
/* preds: block_1 */
/* succs: block_4 */
}
block block_4:
/* preds: block_3 */
vec1 32 ssa_113 = load_const (0x00000001 /* 0.000000 */)
vec1 32 ssa_114 = load_const (0x00000060 /* 0.000000 */)
vec1 32 ssa_115 = imul ssa_111, ssa_114
vec1 32 ssa_116 = iadd ssa_115, ssa_38
vec4 32 ssa_117 = intrinsic load_ubo (ssa_108, ssa_116) (0, 4, 0) /* access=0 */ /* align_mul=4 */ /* align_offset=0 */
vec1 32 ssa_118 = fmul ssa_117.x, ssa_97
vec1 32 ssa_119 = fmul ssa_117.y, ssa_98
vec1 32 ssa_120 = fadd ssa_118, ssa_119
vec1 32 ssa_121 = fmul ssa_117.z, ssa_99
vec1 32 ssa_122 = fadd ssa_120, ssa_121
vec1 32 ssa_123 = fadd ssa_122, ssa_117.w
vec1 32 ssa_124 = iadd ssa_115, ssa_33
vec4 32 ssa_125 = intrinsic load_ubo (ssa_108, ssa_124) (0, 4, 0) /* access=0 */ /* align_mul=4 */ /* align_offset=0 */
vec1 32 ssa_126 = fmul ssa_125.x, ssa_97
vec1 32 ssa_127 = fmul ssa_125.y, ssa_98
vec1 32 ssa_128 = fadd ssa_126, ssa_127
vec1 32 ssa_129 = fmul ssa_125.z, ssa_99
vec1 32 ssa_130 = fadd ssa_128, ssa_129
vec1 32 ssa_131 = fadd ssa_130, ssa_125.w
vec1 32 ssa_132 = iadd ssa_115, ssa_114
vec4 32 ssa_133 = intrinsic load_ubo (ssa_108, ssa_132) (0, 4, 0) /* access=0 */ /* align_mul=4 */ /* align_offset=0 */
vec1 32 ssa_134 = fmul ssa_133.x, ssa_97
vec1 32 ssa_135 = fmul ssa_133.y, ssa_98
vec1 32 ssa_136 = fadd ssa_134, ssa_135
vec1 32 ssa_137 = fmul ssa_133.z, ssa_99
vec1 32 ssa_138 = fadd ssa_136, ssa_137
vec1 32 ssa_139 = fadd ssa_138, ssa_133.w
vec1 32 ssa_140 = load_const (0x00000020 /* 0.000000 */)
vec1 32 ssa_141 = iadd ssa_115, ssa_140
vec3 32 ssa_142 = intrinsic load_ubo (ssa_108, ssa_141) (0, 4, 0) /* access=0 */ /* align_mul=4 */ /* align_offset=0 */
vec1 1 ssa_143 = fge ssa_123, ssa_142.x
vec1 1 ssa_144 = fge ssa_131, ssa_142.y
vec1 1 ssa_145 = fge ssa_139, ssa_142.z
vec1 1 ssa_146 = iand ssa_144, ssa_143
vec1 1 ssa_147 = iand ssa_145, ssa_146
vec1 32 ssa_148 = iadd ssa_115, ssa_46
vec3 32 ssa_149 = intrinsic load_ubo (ssa_108, ssa_148) (0, 4, 0) /* access=0 */ /* align_mul=4 */ /* align_offset=0 */
vec1 1 ssa_150 = fge ssa_149.x, ssa_123
vec1 1 ssa_151 = fge ssa_149.y, ssa_131
vec1 1 ssa_152 = fge ssa_149.z, ssa_139
vec1 1 ssa_153 = iand ssa_147, ssa_150
vec1 1 ssa_154 = iand ssa_151, ssa_153
vec1 1 ssa_155 = iand ssa_152, ssa_154
/* succs: block_5 block_28 */
if ssa_155 {
block block_5:
/* preds: block_4 */
vec1 32 ssa_156 = load_const (0x00000014 /* 0.000000 */)
vec1 32 ssa_157 = iadd ssa_115, ssa_25
vec1 32 ssa_158 = intrinsic load_ubo (ssa_108, ssa_157) (0, 4, 0) /* access=0 */ /* align_mul=4 */ /* align_offset=0 */
vec1 1 ssa_159 = ine ssa_158, ssa_0
/* succs: block_6 block_18 */
if ssa_159 {
block block_6:
/* preds: block_5 */
vec1 32 ssa_160 = load_const (0x00000018 /* 0.000000 */)
vec1 32 ssa_161 = iadd ssa_160, ssa_115
vec1 32 ssa_162 = intrinsic load_ubo (ssa_108, ssa_161) (0, 4, 0) /* access=0 */ /* align_mul=4 */ /* align_offset=0 */
/* succs: block_7 */
loop {
block block_7:
/* preds: block_6 block_13 */
vec1 32 ssa_163 = phi block_6: ssa_162, block_13: ssa_184
vec1 32 ssa_164 = phi block_6: ssa_0, block_13: ssa_182
vec1 32 ssa_165 = load_const (0x0000001c /* 0.000000 */)
vec1 32 ssa_166 = iadd ssa_165, ssa_115
vec1 32 ssa_167 = intrinsic load_ubo (ssa_108, ssa_166) (0, 4, 0) /* access=0 */ /* align_mul=4 */ /* align_offset=0 */
vec1 1 ssa_168 = ult ssa_167, ssa_163
/* succs: block_8 block_9 */
if ssa_168 {
block block_8:
/* preds: block_7 */
break
/* succs: block_14 */
} else {
block block_9:
/* preds: block_7 */
/* succs: block_10 */
}
block block_10:
/* preds: block_9 */
vec1 32 ssa_169 = ishl ssa_163, ssa_1
vec1 32 ssa_170 = intrinsic vulkan_resource_index (ssa_0) (0, 4, 7) /* desc-set=0 */ /* binding=4 */ /* desc_type=SSBO */
vec1 32 ssa_171 = ishl ssa_169, ssa_1
vec4 32 ssa_172 = intrinsic load_ssbo (ssa_170, ssa_171) (0, 4, 0) /* access=0 */ /* align_mul=4 */ /* align_offset=0 */
vec1 32 ssa_173 = fmul ssa_172.x, ssa_123
vec1 32 ssa_174 = fmul ssa_172.y, ssa_131
vec1 32 ssa_175 = fadd ssa_173, ssa_174
vec1 32 ssa_176 = fmul ssa_172.z, ssa_139
vec1 32 ssa_177 = fadd ssa_175, ssa_176
vec1 32 ssa_178 = fneg ssa_172.w
vec1 32 ssa_179 = fadd ssa_178, ssa_177
vec1 1 ssa_180 = flt ssa_0, ssa_179
vec1 32 ssa_181 = b2i32 ssa_180
vec1 32 ssa_182 = ineg ssa_181
/* succs: block_11 block_12 */
if ssa_180 {
block block_11:
/* preds: block_10 */
vec1 32 ssa_183 = load_const (0xffffffff /* -nan */)
break
/* succs: block_14 */
} else {
block block_12:
/* preds: block_10 */
/* succs: block_13 */
}
block block_13:
/* preds: block_12 */
vec1 32 ssa_184 = iadd ssa_163, ssa_113
/* succs: block_7 */
}
block block_14:
/* preds: block_8 block_11 */
vec1 32 ssa_185 = phi block_8: ssa_164, block_11: ssa_183
vec1 1 ssa_186 = ieq ssa_185, ssa_0
/* succs: block_15 block_16 */
if ssa_186 {
block block_15:
/* preds: block_14 */
vec1 32 ssa_187 = iadd ssa_156, ssa_115
vec1 32 ssa_188 = intrinsic load_ubo (ssa_108, ssa_187) (0, 4, 0) /* access=0 */ /* align_mul=4 */ /* align_offset=0 */
break
/* succs: block_30 */
} else {
block block_16:
/* preds: block_14 */
/* succs: block_17 */
}
block block_17:
/* preds: block_16 */
/* succs: block_27 */
} else {
block block_18:
/* preds: block_5 */
vec1 32 ssa_189 = load_const (0x00000018 /* 0.000000 */)
vec1 32 ssa_190 = iadd ssa_189, ssa_115
vec2 32 ssa_191 = intrinsic load_ubo (ssa_108, ssa_190) (0, 4, 0) /* access=0 */ /* align_mul=4 */ /* align_offset=0 */
vec1 32 ssa_192 = ishl ssa_191.x, ssa_113
vec1 32 ssa_193 = intrinsic vulkan_resource_index (ssa_0) (0, 3, 7) /* desc-set=0 */ /* binding=3 */ /* desc_type=SSBO */
vec1 32 ssa_194 = ishl ssa_192, ssa_1
vec2 32 ssa_195 = intrinsic load_ssbo (ssa_193, ssa_194) (0, 4, 0) /* access=0 */ /* align_mul=4 */ /* align_offset=0 */
vec1 32 ssa_196 = mov ssa_195.x
vec1 32 ssa_197 = mov ssa_195.y
vec1 32 ssa_198 = iadd ssa_113, ssa_191.y
vec1 32 ssa_199 = iadd ssa_113, ssa_191.x
/* succs: block_19 */
loop {
block block_19:
/* preds: block_18 block_22 */
vec1 32 ssa_200 = phi block_18: ssa_196, block_22: ssa_228
vec1 32 ssa_201 = phi block_18: ssa_197, block_22: ssa_229
vec1 32 ssa_202 = phi block_18: ssa_199, block_22: ssa_259
vec1 32 ssa_203 = phi block_18: ssa_0, block_22: ssa_258
vec1 1 ssa_204 = ult ssa_198, ssa_202
/* succs: block_20 block_21 */
if ssa_204 {
block block_20:
/* preds: block_19 */
break
/* succs: block_23 */
} else {
block block_21:
/* preds: block_19 */
/* succs: block_22 */
}
block block_22:
/* preds: block_21 */
vec1 32 ssa_205 = urcp ssa_198
vec1 32 ssa_206 = imul ssa_205, ssa_198
vec1 32 ssa_207 = umul_high ssa_205, ssa_198
vec1 1 ssa_208 = ine ssa_207, ssa_0
vec1 32 ssa_209 = ineg ssa_206
vec1 32 ssa_210 = bcsel ssa_208, ssa_206, ssa_209
vec1 32 ssa_211 = umul_high ssa_210, ssa_205
vec1 32 ssa_212 = iadd ssa_205, ssa_211
vec1 32 ssa_213 = isub ssa_205, ssa_211
vec1 32 ssa_214 = bcsel ssa_208, ssa_213, ssa_212
vec1 32 ssa_215 = umul_high ssa_214, ssa_202
vec1 32 ssa_216 = imul ssa_215, ssa_198
vec1 32 ssa_217 = isub ssa_202, ssa_216
vec1 1 ssa_218 = uge ssa_217, ssa_198
vec1 1 ssa_219 = uge ssa_202, ssa_216
vec1 1 ssa_220 = iand ssa_218, ssa_219
vec1 32 ssa_221 = isub ssa_217, ssa_198
vec1 32 ssa_222 = iadd ssa_217, ssa_198
vec1 32 ssa_223 = bcsel ssa_220, ssa_221, ssa_217
vec1 32 ssa_224 = bcsel ssa_219, ssa_223, ssa_222
vec1 32 ssa_225 = ishl ssa_224, ssa_113
vec1 32 ssa_226 = ishl ssa_225, ssa_1
vec2 32 ssa_227 = intrinsic load_ssbo (ssa_193, ssa_226) (0, 4, 0) /* access=0 */ /* align_mul=4 */ /* align_offset=0 */
vec1 32 ssa_228 = mov ssa_227.x
vec1 32 ssa_229 = mov ssa_227.y
vec1 32 ssa_230 = fmin ssa_201, ssa_227.y
vec1 1 ssa_231 = fge ssa_131, ssa_230
vec1 32 ssa_232 = fmax ssa_201, ssa_227.y
vec1 32 ssa_233 = fmax ssa_200, ssa_227.x
vec1 1 ssa_234 = flt ssa_131, ssa_232
vec1 1 ssa_235 = flt ssa_123, ssa_233
vec1 1 ssa_236 = feq ssa_227.y, ssa_227.y
vec1 1 ssa_237 = feq ssa_201, ssa_201
vec1 1 ssa_238 = iand ssa_237, ssa_236
vec1 1 ssa_239 = fne ssa_201, ssa_227.y
vec1 1 ssa_240 = iand ssa_239, ssa_238
vec1 32 ssa_241 = fneg ssa_201
vec1 32 ssa_242 = fadd ssa_131, ssa_241
vec1 32 ssa_243 = fneg ssa_200
vec1 32 ssa_244 = fadd ssa_243, ssa_227.x
vec1 32 ssa_245 = fadd ssa_241, ssa_227.y
vec1 32 ssa_246 = fmul ssa_244, ssa_242
vec1 32 ssa_247 = frcp ssa_245
vec1 32 ssa_248 = fmul ssa_246, ssa_247
vec1 32 ssa_249 = fadd ssa_200, ssa_248
vec1 1 ssa_250 = feq ssa_200, ssa_227.x
vec1 1 ssa_251 = fge ssa_249, ssa_123
vec1 1 ssa_252 = ior ssa_251, ssa_250
vec1 32 ssa_253 = b2i32 ssa_252
vec1 32 ssa_254 = iadd ssa_203, ssa_253
vec1 32 ssa_255 = bcsel ssa_240, ssa_254, ssa_203
vec1 32 ssa_256 = bcsel ssa_235, ssa_255, ssa_203
vec1 32 ssa_257 = bcsel ssa_234, ssa_256, ssa_203
vec1 32 ssa_258 = bcsel ssa_231, ssa_257, ssa_203
vec1 32 ssa_259 = iadd ssa_202, ssa_113
/* succs: block_19 */
}
block block_23:
/* preds: block_20 */
/* LCSSA-phi */ vec1 32 ssa_260 = phi block_20: ssa_203
vec1 32 ssa_261 = iand /* LCSSA-phi */ ssa_260, ssa_113
vec1 1 ssa_262 = ine ssa_261, ssa_0
/* succs: block_24 block_25 */
if ssa_262 {
block block_24:
/* preds: block_23 */
vec1 32 ssa_263 = iadd ssa_156, ssa_115
vec1 32 ssa_264 = intrinsic load_ubo (ssa_108, ssa_263) (0, 4, 0) /* access=0 */ /* align_mul=4 */ /* align_offset=0 */
break
/* succs: block_30 */
} else {
block block_25:
/* preds: block_23 */
/* succs: block_26 */
}
block block_26:
/* preds: block_25 */
/* succs: block_27 */
}
block block_27:
/* preds: block_17 block_26 */
/* succs: block_29 */
} else {
block block_28:
/* preds: block_4 */
/* succs: block_29 */
}
block block_29:
/* preds: block_27 block_28 */
vec1 32 ssa_265 = iadd ssa_111, ssa_113
/* succs: block_1 */
}
block block_30:
/* preds: block_2 block_15 block_24 */
vec1 32 ssa_266 = phi block_2: ssa_0, block_15: ssa_188, block_24: ssa_264
vec1 32 ssa_267 = undefined
vec4 32 ssa_268 = vec4 ssa_266, ssa_266, ssa_266, ssa_266
vec4 32 ssa_269 = vec4 ssa_16, ssa_17, ssa_18, ssa_18
vec1 32 ssa_270 = deref_var &u0 (uniform uimage3D)
intrinsic image_deref_store (ssa_270, ssa_269, ssa_267, ssa_268) (0) /* access=0 */
/* succs: block_31 */
block block_31:
}
LLVM IR:
(null)
DISASM:
(null)
Compute Shader:
*** SHADER STATS ***
SGPRS: 40
VGPRS: 16
Spilled SGPRs: 0
Spilled VGPRs: 0
PrivMem VGPRS: 0
Code Size: 1420 bytes
LDS: 0 blocks
Scratch: 0 bytes per wave
Max Waves: 10
********************
sh: umr: command not found
The number of active waves = 0
List of descriptors:
** descriptor set (0) **
va: 0xffff8000003f0400
size: 32
mapped_ptr:
[0x0] = 0x49c00000
[0x1] = 0x00028001
[0x2] = 0x00120000
[0x3] = 0x00014204
[0x4] = 0x106b0000
[0x5] = 0x00018001
[0x6] = 0x00001200
[0x7] = 0x0000c204
*** layout ***
binding_count: 7
size: 32
shader_stages: 20
dynamic_shader_stages: 20
buffer_count: 7
dynamic_offset_count: 5
**** binding layout (0) ****
type: UNIFORM_BUFFER_DYNAMIC
array_size: 1
offset: 0
buffer_offset: 0
dynamic_offset_offset: 0
dynamic_offset_count: 1
size: 0
immutable_samplers_offset: 0
immutable_samplers_equal: 0
**** binding layout (1) ****
type: UNIFORM_BUFFER_DYNAMIC
array_size: 1
offset: 0
buffer_offset: 1
dynamic_offset_offset: 1
dynamic_offset_count: 1
size: 0
immutable_samplers_offset: 0
immutable_samplers_equal: 0
**** binding layout (2) ****
type: UNIFORM_BUFFER_DYNAMIC
array_size: 1
offset: 0
buffer_offset: 2
dynamic_offset_offset: 2
dynamic_offset_count: 1
size: 0
immutable_samplers_offset: 0
immutable_samplers_equal: 0
**** binding layout (3) ****
type: UNIFORM_BUFFER_DYNAMIC
array_size: 1
offset: 0
buffer_offset: 3
dynamic_offset_offset: 3
dynamic_offset_count: 1
size: 0
immutable_samplers_offset: 0
immutable_samplers_equal: 0
**** binding layout (4) ****
type: STORAGE_BUFFER_DYNAMIC
array_size: 1
offset: 0
buffer_offset: 4
dynamic_offset_offset: 4
dynamic_offset_count: 1
size: 0
immutable_samplers_offset: 0
immutable_samplers_equal: 0
**** binding layout (5) ****
type: STORAGE_TEXEL_BUFFER
array_size: 1
offset: 0
buffer_offset: 5
dynamic_offset_offset: 5
dynamic_offset_count: 0
size: 16
immutable_samplers_offset: 0
immutable_samplers_equal: 0
 Buffer:
SQ_BUF_RSRC_WORD0 <- 0x49c00000
SQ_BUF_RSRC_WORD1 <- BASE_ADDRESS_HI = 0x8001
STRIDE = 2
CACHE_SWIZZLE = 0
SWIZZLE_ENABLE = 0
SQ_BUF_RSRC_WORD2 <- 0x00120000
SQ_BUF_RSRC_WORD3 <- DST_SEL_X = SQ_SEL_X
DST_SEL_Y = SQ_SEL_0
DST_SEL_Z = SQ_SEL_0
DST_SEL_W = SQ_SEL_1
NUM_FORMAT = BUF_NUM_FORMAT_UINT
DATA_FORMAT = BUF_DATA_FORMAT_16
USER_VM_ENABLE = 0
USER_VM_MODE = 0
INDEX_STRIDE = 0
ADD_TID_ENABLE = 0
NV = 0
TYPE = SQ_RSRC_BUF
**** binding layout (6) ****
type: STORAGE_TEXEL_BUFFER
array_size: 1
offset: 16
buffer_offset: 6
dynamic_offset_offset: 5
dynamic_offset_count: 0
size: 16
immutable_samplers_offset: 0
immutable_samplers_equal: 0
 Buffer:
SQ_BUF_RSRC_WORD0 <- 0x106b0000
SQ_BUF_RSRC_WORD1 <- BASE_ADDRESS_HI = 0x8001
STRIDE = 1
CACHE_SWIZZLE = 0
SWIZZLE_ENABLE = 0
SQ_BUF_RSRC_WORD2 <- 4608 (0x00001200)
SQ_BUF_RSRC_WORD3 <- DST_SEL_X = SQ_SEL_X
DST_SEL_Y = SQ_SEL_0
DST_SEL_Z = SQ_SEL_0
DST_SEL_W = SQ_SEL_1
NUM_FORMAT = BUF_NUM_FORMAT_UINT
DATA_FORMAT = BUF_DATA_FORMAT_8
USER_VM_ENABLE = 0
USER_VM_MODE = 0
INDEX_STRIDE = 0
ADD_TID_ENABLE = 0
NV = 0
TYPE = SQ_RSRC_BUF
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