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arachne-pnr problem
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| ramtest.bin: ramtest.v ramtest.pcf | |
| yosys -q -p "synth_ice40 -blif ramtest.blif" ramtest.v | |
| arachne-pnr -p ramtest.pcf ramtest.blif -o ramtest.txt | |
| icebox_explain ramtest.txt > ramtest.ex | |
| icepack ramtest.txt ramtest.bin | |
| clean: | |
| rm -f ramtest.blif ramtest.txt ramtest.ex ramtest.bin |
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| # Generated by Yosys 0.5+ 286 (git sha1 eb38722, clang 6.1.0 -fPIC -Os) | |
| .model top | |
| .inputs clk | |
| .outputs D1 | |
| .names $false | |
| .names $true | |
| 1 | |
| .names $undef | |
| .gate SB_RAM40_4K MASK[0]=$false MASK[1]=$false MASK[2]=$false MASK[3]=$false MASK[4]=$false MASK[5]=$false MASK[6]=$false MASK[7]=$false MASK[8]=$false MASK[9]=$false MASK[10]=$false MASK[11]=$false MASK[12]=$false MASK[13]=$false MASK[14]=$false MASK[15]=$false RADDR[0]=$false RADDR[1]=$false RADDR[2]=$false RADDR[3]=$false RADDR[4]=$false RADDR[5]=$false RADDR[6]=$false RADDR[7]=$false RCLK=$false RCLKE=$false RDATA[0]=rdata[0] RDATA[1]=rdata[1] RDATA[2]=rdata[2] RDATA[3]=rdata[3] RDATA[4]=rdata[4] RDATA[5]=rdata[5] RDATA[6]=rdata[6] RDATA[7]=rdata[7] RDATA[8]=rdata[8] RDATA[9]=rdata[9] RDATA[10]=rdata[10] RDATA[11]=rdata[11] RDATA[12]=rdata[12] RDATA[13]=rdata[13] RDATA[14]=rdata[14] RDATA[15]=rdata[15] RE=$false WADDR[0]=$false WADDR[1]=$false WADDR[2]=$false WADDR[3]=$false WADDR[4]=$false WADDR[5]=$false WADDR[6]=$false WADDR[7]=$false WCLK=$false WCLKE=$false WDATA[0]=$false WDATA[1]=$false WDATA[2]=$false WDATA[3]=$false WDATA[4]=$false WDATA[5]=$false WDATA[6]=$false WDATA[7]=$false WDATA[8]=$false WDATA[9]=$false WDATA[10]=$false WDATA[11]=$false WDATA[12]=$false WDATA[13]=$false WDATA[14]=$false WDATA[15]=$false WE=$false | |
| .attr src "ramtest.v:10" | |
| .param READ_MODE 00000000000000000000000000000000 | |
| .param WRITE_MODE 00000000000000000000000000000000 | |
| .names rdata[0] D1 | |
| 1 1 | |
| .end |
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| set_io clk 21 | |
| set_io D1 99 |
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| module top( | |
| input clk, | |
| output D1 | |
| ); | |
| wire [15:0] rdata; | |
| wire [7:0] raddr; | |
| reg out; | |
| SB_RAM40_4K #( | |
| .WRITE_MODE(0), | |
| .READ_MODE(0) | |
| ) ram ( | |
| .RDATA(rdata), | |
| .RCLK(1'b0), | |
| .RCLKE(1'b0), | |
| .RE(1'b0), | |
| .RADDR(raddr), | |
| .WCLK(1'b0), | |
| .WCLKE(1'b0), | |
| .WE(1'b0), | |
| .WADDR(8'h00), | |
| .MASK(16'h0000), | |
| .WDATA(16'h0000) | |
| ); | |
| always @(posedge clk) begin | |
| raddr <= 0; | |
| end | |
| assign D1 = rdata[0]; | |
| endmodule |
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