vhdl_vector.sch

<Qucs Schematic 0.0.18>
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  <Grid=10,10,1>
  <DataSet=vhdl_vector.dat>
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  <Script=vhdl_vector.m>
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<Symbol>
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  <DigiSource S1 1 230 190 -35 16 0 0 "1" 1 "low" 0 "1ns; 1ns" 0 "1 V" 0>
  <.Digi Digi1 1 520 170 0 51 0 0 "TimeList" 1 "10 ns" 0 "VHDL" 0>
  <VHDL X1 1 290 190 -26 21 0 0 "vhdl_vector.vhdl" 1>
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<Diagrams>
  <Time 80 350 791 70 3 #c0c0c0 1 00 1 0 1 10 1 0 1 1 1 0 1 11 315 0 225 "" "" "">
	<"x1.aff.X" #0000ff 0 3 0 0 0>
	<"x1.clk.X" #ff0000 0 3 0 0 0>
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vhdl_vector.vhdl

Library IEEE;
USE ieee.std_logic_1164.all;
Entity Serpent is Port(
	clk : IN std_logic;
	aff : OUT std_logic_vector(6 downto 0));
End Entity Serpent;

Architecture arch_Serpent of Serpent is
	Signal D : std_logic_vector(2 downto 0):="000";
	Signal Q : std_logic_vector(2 downto 0):="000";

Begin
------- COPIE DE D DANS Q A CHAQUE FLANC MONTANT D'HORLOGE
	FF_Q : process(clk) is
	begin
		if rising_edge(clk) then
			Q <= D;
		end if;
	End process FF_Q;

------- CALCULS DES ENTREES ET DE L'AFFICHAGE
	FF_D_Aff : process(Q) is
	begin
		case Q is
		when "000" =>
			aff <= "0000100";
			D <= "001";
		when "001" =>
			aff <= "0000010";
			D <= "010";
		when "010" =>
			aff <= "1000000";
			D <= "011";
		when "011" =>
			aff <= "0100000";
			D <= "100";
		when "100" =>
			aff <= "0010000";
			D <= "101";
		when "101" =>
			aff <= "0001000";
			D <= "110";
		when "110" =>
			aff <= "0000100";
			D <= "111";
		when "111" =>
			aff <= "0000001";
			D <= "000";
		when others => D <= "000";

		end case;

	End Process FF_D_Aff;
End Architecture arch_Serpent;