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Created January 23, 2017 19:29
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Modelsim ASE 10.4b transcript of "vsim -do compile.do" revision fcd775f
# do compile.do
# Model Technology ModelSim ALTERA vcom 10.4b Compiler 2015.05 May 27 2015
# Start time: 20:23:08 on Jan 23,2017
# vcom -reportprogress 300 -work nuand -2008 ../../../ip/nuand/../altera/tx_fifo/tx_fifo.vhd
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Compiling entity tx_fifo
# -- Compiling architecture SYN of tx_fifo
# End time: 20:23:08 on Jan 23,2017, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Model Technology ModelSim ALTERA vcom 10.4b Compiler 2015.05 May 27 2015
# Start time: 20:23:08 on Jan 23,2017
# vcom -reportprogress 300 -work nuand -2008 ../../../ip/nuand/./synthesis/constellation_mapper.vhd
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Loading package NUMERIC_STD
# -- Loading package MATH_REAL
# -- Loading package MATH_COMPLEX
# -- Compiling package constellation_mapper_p
# -- Loading package constellation_mapper_p
# -- Compiling entity constellation_mapper
# -- Compiling architecture arch of constellation_mapper
# End time: 20:23:08 on Jan 23,2017, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Model Technology ModelSim ALTERA vcom 10.4b Compiler 2015.05 May 27 2015
# Start time: 20:23:08 on Jan 23,2017
# vcom -reportprogress 300 -work nuand -2008 ../../../ip/nuand/./synthesis/sync_fifo.vhd
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Loading package NUMERIC_STD
# -- Compiling entity sync_fifo
# -- Compiling architecture arch of sync_fifo
# End time: 20:23:08 on Jan 23,2017, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Model Technology ModelSim ALTERA vcom 10.4b Compiler 2015.05 May 27 2015
# Start time: 20:23:08 on Jan 23,2017
# vcom -reportprogress 300 -work nuand -2008 ../../../ip/nuand/./synthesis/uart.vhd
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Loading package NUMERIC_STD
# -- Compiling entity uart
# -- Compiling architecture arch of uart
# End time: 20:23:08 on Jan 23,2017, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Model Technology ModelSim ALTERA vcom 10.4b Compiler 2015.05 May 27 2015
# Start time: 20:23:08 on Jan 23,2017
# vcom -reportprogress 300 -work nuand -2008 ../../../ip/nuand/./synthesis/cordic.vhd
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Loading package NUMERIC_STD
# -- Compiling package cordic_p
# -- Loading package MATH_REAL
# -- Loading package cordic_p
# -- Compiling entity cordic
# -- Compiling architecture arch of cordic
# End time: 20:23:08 on Jan 23,2017, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Model Technology ModelSim ALTERA vcom 10.4b Compiler 2015.05 May 27 2015
# Start time: 20:23:08 on Jan 23,2017
# vcom -reportprogress 300 -work nuand -2008 ../../../ip/nuand/./synthesis/nco.vhd
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Loading package NUMERIC_STD
# -- Compiling package nco_p
# -- Loading package cordic_p
# -- Loading package nco_p
# -- Compiling entity nco
# -- Compiling architecture arch of nco
# -- Loading package MATH_REAL
# -- Loading entity cordic
# End time: 20:23:08 on Jan 23,2017, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Model Technology ModelSim ALTERA vcom 10.4b Compiler 2015.05 May 27 2015
# Start time: 20:23:08 on Jan 23,2017
# vcom -reportprogress 300 -work nuand -2008 ../../../ip/nuand/./synthesis/fsk_modulator.vhd
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Loading package NUMERIC_STD
# -- Loading package MATH_REAL
# -- Loading package nco_p
# -- Compiling entity fsk_modulator
# -- Compiling architecture arch of fsk_modulator
# -- Loading package cordic_p
# -- Loading entity nco
# End time: 20:23:08 on Jan 23,2017, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Model Technology ModelSim ALTERA vcom 10.4b Compiler 2015.05 May 27 2015
# Start time: 20:23:08 on Jan 23,2017
# vcom -reportprogress 300 -work nuand -2008 ../../../ip/nuand/./synthesis/fsk_demodulator.vhd
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Loading package NUMERIC_STD
# -- Loading package cordic_p
# -- Compiling entity fsk_demodulator
# -- Compiling architecture arch of fsk_demodulator
# -- Loading package MATH_REAL
# -- Loading entity cordic
# End time: 20:23:08 on Jan 23,2017, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Model Technology ModelSim ALTERA vcom 10.4b Compiler 2015.05 May 27 2015
# Start time: 20:23:08 on Jan 23,2017
# vcom -reportprogress 300 -work nuand -2008 ../../../ip/nuand/./synthesis/uart.vhd
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Loading package NUMERIC_STD
# -- Compiling entity uart
# -- Compiling architecture arch of uart
# End time: 20:23:08 on Jan 23,2017, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Model Technology ModelSim ALTERA vcom 10.4b Compiler 2015.05 May 27 2015
# Start time: 20:23:08 on Jan 23,2017
# vcom -reportprogress 300 -work nuand -2008 ../../../ip/nuand/./synthesis/tan_table.vhd
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Loading package NUMERIC_STD
# -- Loading package MATH_REAL
# -- Compiling entity tan_table
# -- Compiling architecture arch of tan_table
# End time: 20:23:08 on Jan 23,2017, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Model Technology ModelSim ALTERA vcom 10.4b Compiler 2015.05 May 27 2015
# Start time: 20:23:08 on Jan 23,2017
# vcom -reportprogress 300 -work nuand -2008 ../../../ip/nuand/./synthesis/iq_correction.vhd
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Loading package NUMERIC_STD
# -- Loading package MATH_REAL
# -- Compiling entity iq_correction
# -- Compiling architecture rx of iq_correction
# -- Loading entity tan_table
# -- Compiling architecture tx of iq_correction
# -- Loading entity iq_correction
# End time: 20:23:08 on Jan 23,2017, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Model Technology ModelSim ALTERA vcom 10.4b Compiler 2015.05 May 27 2015
# Start time: 20:23:08 on Jan 23,2017
# vcom -reportprogress 300 -work nuand -2008 ../../../ip/nuand/./synthesis/synchronizer.vhd
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Compiling entity synchronizer
# -- Compiling architecture arch of synchronizer
# End time: 20:23:08 on Jan 23,2017, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Model Technology ModelSim ALTERA vcom 10.4b Compiler 2015.05 May 27 2015
# Start time: 20:23:08 on Jan 23,2017
# vcom -reportprogress 300 -work nuand -2008 ../../../ip/nuand/./synthesis/handshake.vhd
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Compiling entity handshake
# -- Compiling architecture arch of handshake
# -- Loading entity synchronizer
# End time: 20:23:08 on Jan 23,2017, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Model Technology ModelSim ALTERA vcom 10.4b Compiler 2015.05 May 27 2015
# Start time: 20:23:08 on Jan 23,2017
# vcom -reportprogress 300 -work nuand -2008 ../../../ip/nuand/./synthesis/tb/handshake_tb.vhd
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Loading package NUMERIC_STD
# -- Compiling entity handshake_tb
# -- Compiling architecture arch of handshake_tb
# -- Loading entity handshake
# End time: 20:23:08 on Jan 23,2017, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Model Technology ModelSim ALTERA vcom 10.4b Compiler 2015.05 May 27 2015
# Start time: 20:23:08 on Jan 23,2017
# vcom -reportprogress 300 -work nuand -2008 ../../../ip/nuand/./synthesis/signal_processing_p.vhd
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Loading package NUMERIC_STD
# -- Compiling package signal_processing_p
# -- Compiling package body signal_processing_p
# -- Loading package signal_processing_p
# End time: 20:23:08 on Jan 23,2017, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Model Technology ModelSim ALTERA vcom 10.4b Compiler 2015.05 May 27 2015
# Start time: 20:23:08 on Jan 23,2017
# vcom -reportprogress 300 -work nuand -2008 ../../../ip/nuand/./synthesis/bit_stripper.vhd
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Loading package NUMERIC_STD
# -- Compiling entity bit_stripper
# -- Compiling architecture arch of bit_stripper
# End time: 20:23:08 on Jan 23,2017, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Model Technology ModelSim ALTERA vcom 10.4b Compiler 2015.05 May 27 2015
# Start time: 20:23:08 on Jan 23,2017
# vcom -reportprogress 300 -work nuand -2008 ../../../ip/nuand/./synthesis/fir_filter.vhd
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Loading package NUMERIC_STD
# -- Loading package MATH_REAL
# -- Loading package MATH_COMPLEX
# -- Loading package constellation_mapper_p
# -- Compiling entity fir_filter
# -- Compiling architecture systolic of fir_filter
# End time: 20:23:08 on Jan 23,2017, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Model Technology ModelSim ALTERA vcom 10.4b Compiler 2015.05 May 27 2015
# Start time: 20:23:08 on Jan 23,2017
# vcom -reportprogress 300 -work nuand -2008 ../../../ip/nuand/./synthesis/atsc_tx.vhd
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Loading package NUMERIC_STD
# -- Loading package MATH_REAL
# -- Loading package MATH_COMPLEX
# -- Loading package constellation_mapper_p
# -- Compiling entity atsc_tx
# -- Compiling architecture arch of atsc_tx
# -- Loading entity bit_stripper
# -- Loading entity constellation_mapper
# -- Loading entity fir_filter
# End time: 20:23:08 on Jan 23,2017, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Model Technology ModelSim ALTERA vcom 10.4b Compiler 2015.05 May 27 2015
# Start time: 20:23:08 on Jan 23,2017
# vcom -reportprogress 300 -work nuand -2008 ../../../ip/nuand/./simulation/util.vhd
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Compiling package util
# -- Compiling package body util
# -- Loading package util
# -- Loading package NUMERIC_STD
# -- Compiling entity data_saver
# -- Compiling architecture arch of data_saver
# -- Compiling entity signed_saver
# -- Compiling architecture arch of signed_saver
# -- Compiling entity data_reader
# -- Compiling architecture arch of data_reader
# End time: 20:23:09 on Jan 23,2017, Elapsed time: 0:00:01
# Errors: 0, Warnings: 0
# Model Technology ModelSim ALTERA vcom 10.4b Compiler 2015.05 May 27 2015
# Start time: 20:23:09 on Jan 23,2017
# vcom -reportprogress 300 -work nuand -2008 ../../../ip/nuand/./synthesis/tb/fir_filter_tb.vhd
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Loading package NUMERIC_STD
# -- Loading package MATH_REAL
# -- Loading package MATH_COMPLEX
# -- Loading package ENV
# -- Loading package nco_p
# -- Loading package util
# -- Loading package constellation_mapper_p
# -- Compiling entity fir_filter_tb
# -- Compiling architecture arch of fir_filter_tb
# -- Loading entity tx_fifo
# -- Loading entity bit_stripper
# -- Loading entity constellation_mapper
# -- Loading entity fir_filter
# -- Loading entity signed_saver
# End time: 20:23:09 on Jan 23,2017, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Model Technology ModelSim ALTERA vcom 10.4b Compiler 2015.05 May 27 2015
# Start time: 20:23:09 on Jan 23,2017
# vcom -reportprogress 300 -work nuand -2008 ../../../ip/nuand/./synthesis/tb/atsc_tx_tb.vhd
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Loading package NUMERIC_STD
# -- Loading package MATH_REAL
# -- Loading package MATH_COMPLEX
# -- Loading package ENV
# -- Loading package nco_p
# -- Loading package util
# -- Loading package constellation_mapper_p
# -- Compiling entity atsc_tx_tb
# -- Compiling architecture arch of atsc_tx_tb
# -- Loading entity data_reader
# -- Loading entity tx_fifo
# -- Loading entity atsc_tx
# -- Loading entity signed_saver
# End time: 20:23:09 on Jan 23,2017, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Model Technology ModelSim ALTERA vcom 10.4b Compiler 2015.05 May 27 2015
# Start time: 20:23:09 on Jan 23,2017
# vcom -reportprogress 300 -work nuand -2008 ../../../ip/nuand/./simulation/fx3_model.vhd
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Loading package NUMERIC_STD
# -- Loading package MATH_REAL
# -- Loading package MATH_COMPLEX
# -- Loading package util
# -- Compiling entity fx3_model
# -- Compiling architecture dma of fx3_model
# -- Compiling architecture inband_scheduler of fx3_model
# -- Loading entity fx3_model
# End time: 20:23:09 on Jan 23,2017, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Model Technology ModelSim ALTERA vcom 10.4b Compiler 2015.05 May 27 2015
# Start time: 20:23:09 on Jan 23,2017
# vcom -reportprogress 300 -work nuand -2008 ../../../ip/nuand/./simulation/lms6002d_model.vhd
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Loading package NUMERIC_STD
# -- Loading package MATH_REAL
# -- Loading package MATH_COMPLEX
# -- Compiling entity lms6002d_model
# -- Compiling architecture arch of lms6002d_model
# End time: 20:23:09 on Jan 23,2017, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Model Technology ModelSim ALTERA vcom 10.4b Compiler 2015.05 May 27 2015
# Start time: 20:23:09 on Jan 23,2017
# vcom -reportprogress 300 -work nuand -2008 ../../../ip/nuand/./synthesis/lms6002d/vhdl/lms6002d.vhd
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Loading package NUMERIC_STD
# -- Compiling entity lms6002d
# -- Compiling architecture arch of lms6002d
# End time: 20:23:09 on Jan 23,2017, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Model Technology ModelSim ALTERA vcom 10.4b Compiler 2015.05 May 27 2015
# Start time: 20:23:09 on Jan 23,2017
# vcom -reportprogress 300 -work nuand -2008 ../../../ip/nuand/./synthesis/lms6002d/vhdl/tb/lms6002d_tb.vhd
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Loading package NUMERIC_STD
# -- Loading package MATH_REAL
# -- Loading package ENV
# -- Loading package util
# -- Compiling entity lms6002d_tb
# -- Compiling architecture arch of lms6002d_tb
# -- Loading entity lms6002d
# -- Loading package MATH_COMPLEX
# -- Loading entity lms6002d_model
# End time: 20:23:09 on Jan 23,2017, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Model Technology ModelSim ALTERA vcom 10.4b Compiler 2015.05 May 27 2015
# Start time: 20:23:09 on Jan 23,2017
# vcom -reportprogress 300 -work nuand -2008 ../../../ip/nuand/../altera/rx_fifo/rx_fifo.vhd
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Compiling entity rx_fifo
# -- Compiling architecture SYN of rx_fifo
# End time: 20:23:09 on Jan 23,2017, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Model Technology ModelSim ALTERA vcom 10.4b Compiler 2015.05 May 27 2015
# Start time: 20:23:09 on Jan 23,2017
# vcom -reportprogress 300 -work nuand -2008 ../../../ip/nuand/../altera/tx_fifo/tx_fifo.vhd
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Compiling entity tx_fifo
# -- Compiling architecture SYN of tx_fifo
# End time: 20:23:09 on Jan 23,2017, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Model Technology ModelSim ALTERA vcom 10.4b Compiler 2015.05 May 27 2015
# Start time: 20:23:09 on Jan 23,2017
# vcom -reportprogress 300 -work nuand -2008 ../../../ip/nuand/../altera/rx_meta_fifo/rx_meta_fifo.vhd
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Compiling entity rx_meta_fifo
# -- Compiling architecture SYN of rx_meta_fifo
# End time: 20:23:09 on Jan 23,2017, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Model Technology ModelSim ALTERA vcom 10.4b Compiler 2015.05 May 27 2015
# Start time: 20:23:09 on Jan 23,2017
# vcom -reportprogress 300 -work nuand -2008 ../../../ip/nuand/../altera/tx_meta_fifo/tx_meta_fifo.vhd
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Compiling entity tx_meta_fifo
# -- Compiling architecture SYN of tx_meta_fifo
# End time: 20:23:09 on Jan 23,2017, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Model Technology ModelSim ALTERA vcom 10.4b Compiler 2015.05 May 27 2015
# Start time: 20:23:09 on Jan 23,2017
# vcom -reportprogress 300 -work nuand -2008 ../../../ip/nuand/./synthesis/fifo_reader.vhd
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Loading package NUMERIC_STD
# -- Compiling entity fifo_reader
# -- Compiling architecture simple of fifo_reader
# End time: 20:23:09 on Jan 23,2017, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Model Technology ModelSim ALTERA vcom 10.4b Compiler 2015.05 May 27 2015
# Start time: 20:23:09 on Jan 23,2017
# vcom -reportprogress 300 -work nuand -2008 ../../../ip/nuand/./synthesis/fifo_writer.vhd
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Loading package NUMERIC_STD
# -- Compiling entity fifo_writer
# -- Compiling architecture simple of fifo_writer
# End time: 20:23:09 on Jan 23,2017, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Model Technology ModelSim ALTERA vcom 10.4b Compiler 2015.05 May 27 2015
# Start time: 20:23:09 on Jan 23,2017
# vcom -reportprogress 300 -work nuand -2008 ../../../ip/nuand/./simulation/sample_stream_tb.vhd
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Loading package NUMERIC_STD
# -- Loading package MATH_REAL
# -- Loading package util
# -- Loading package ENV
# -- Compiling entity sample_stream_tb
# -- Compiling architecture arch of sample_stream_tb
# -- Loading entity tx_fifo
# -- Loading entity tx_meta_fifo
# -- Loading entity rx_fifo
# -- Loading entity rx_meta_fifo
# -- Loading entity fifo_reader
# -- Loading entity fifo_writer
# -- Loading entity lms6002d
# -- Loading package MATH_COMPLEX
# -- Loading entity lms6002d_model
# End time: 20:23:09 on Jan 23,2017, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Model Technology ModelSim ALTERA vcom 10.4b Compiler 2015.05 May 27 2015
# Start time: 20:23:09 on Jan 23,2017
# vcom -reportprogress 300 -work nuand -2008 ../../../ip/altera/pll/pll.vhd
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Compiling entity pll
# -- Compiling architecture SYN of pll
# End time: 20:23:09 on Jan 23,2017, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Model Technology ModelSim ALTERA vcom 10.4b Compiler 2015.05 May 27 2015
# Start time: 20:23:09 on Jan 23,2017
# vcom -reportprogress 300 -work nuand -2008 ../../../ip/altera/fx3_pll/fx3_pll.vhd
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Compiling entity fx3_pll
# -- Compiling architecture SYN of fx3_pll
# End time: 20:23:09 on Jan 23,2017, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Model Technology ModelSim ALTERA vcom 10.4b Compiler 2015.05 May 27 2015
# Start time: 20:23:09 on Jan 23,2017
# vcom -reportprogress 300 -work nuand -2008 ../../../ip/altera/rx_fifo/rx_fifo.vhd
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Compiling entity rx_fifo
# -- Compiling architecture SYN of rx_fifo
# End time: 20:23:09 on Jan 23,2017, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Model Technology ModelSim ALTERA vcom 10.4b Compiler 2015.05 May 27 2015
# Start time: 20:23:09 on Jan 23,2017
# vcom -reportprogress 300 -work nuand -2008 ../../../ip/altera/tx_fifo/tx_fifo.vhd
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Compiling entity tx_fifo
# -- Compiling architecture SYN of tx_fifo
# End time: 20:23:09 on Jan 23,2017, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Model Technology ModelSim ALTERA vcom 10.4b Compiler 2015.05 May 27 2015
# Start time: 20:23:09 on Jan 23,2017
# vcom -reportprogress 300 -work nuand -2008 ../../../ip/altera/tx_meta_fifo/tx_meta_fifo.vhd
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Compiling entity tx_meta_fifo
# -- Compiling architecture SYN of tx_meta_fifo
# End time: 20:23:09 on Jan 23,2017, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Model Technology ModelSim ALTERA vcom 10.4b Compiler 2015.05 May 27 2015
# Start time: 20:23:09 on Jan 23,2017
# vcom -reportprogress 300 -work nuand -2008 ../../../ip/altera/rx_meta_fifo/rx_meta_fifo.vhd
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Compiling entity rx_meta_fifo
# -- Compiling architecture SYN of rx_meta_fifo
# End time: 20:23:09 on Jan 23,2017, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Model Technology ModelSim ALTERA vcom 10.4b Compiler 2015.05 May 27 2015
# Start time: 20:23:09 on Jan 23,2017
# vcom -reportprogress 300 -work nuand -2008 ../../../ip/altera/nios_system/simulation/nios_system.vhd
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Compiling entity nios_system
# -- Compiling architecture sim of nios_system
# End time: 20:23:09 on Jan 23,2017, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Model Technology ModelSim ALTERA vcom 10.4b Compiler 2015.05 May 27 2015
# Start time: 20:23:09 on Jan 23,2017
# vcom -reportprogress 300 -work nuand -2008 ../vhdl/fx3_gpif.vhd
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Loading package NUMERIC_STD
# -- Compiling entity fx3_gpif
# -- Compiling architecture sample_shuffler of fx3_gpif
# End time: 20:23:10 on Jan 23,2017, Elapsed time: 0:00:01
# Errors: 0, Warnings: 0
# Model Technology ModelSim ALTERA vcom 10.4b Compiler 2015.05 May 27 2015
# Start time: 20:23:10 on Jan 23,2017
# vcom -reportprogress 300 -work nuand -2008 ../vhdl/bladerf.vhd
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Loading package NUMERIC_STD
# -- Loading package MATH_REAL
# -- Loading package MATH_COMPLEX
# -- Compiling entity bladerf
# End time: 20:23:10 on Jan 23,2017, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Model Technology ModelSim ALTERA vcom 10.4b Compiler 2015.05 May 27 2015
# Start time: 20:23:10 on Jan 23,2017
# vcom -reportprogress 300 -work nuand -2008 ../vhdl/bladerf-hosted.vhd
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Loading package NUMERIC_STD
# -- Loading package MATH_REAL
# -- Loading package MATH_COMPLEX
# -- Compiling architecture hosted_bladerf of bladerf
# -- Loading entity bladerf
# -- Loading entity pll
# -- Loading entity fx3_pll
# -- Loading entity synchronizer
# ** Error: (vcom-11) Could not find work.reset_synchronizer.
# ** Error (suppressible): ../vhdl/bladerf-hosted.vhd(413): (vcom-1195) Cannot find expanded name "work.reset_synchronizer".
# ** Error: ../vhdl/bladerf-hosted.vhd(413): Unknown expanded name.
# ** Error: (vcom-11) Could not find work.reset_synchronizer.
# ** Error (suppressible): ../vhdl/bladerf-hosted.vhd(423): (vcom-1195) Cannot find expanded name "work.reset_synchronizer".
# ** Error: ../vhdl/bladerf-hosted.vhd(423): Unknown expanded name.
# ** Error: (vcom-11) Could not find work.reset_synchronizer.
# ** Error (suppressible): ../vhdl/bladerf-hosted.vhd(433): (vcom-1195) Cannot find expanded name "work.reset_synchronizer".
# ** Error: ../vhdl/bladerf-hosted.vhd(433): Unknown expanded name.
# ** Error: (vcom-11) Could not find work.reset_synchronizer.
# ** Error (suppressible): ../vhdl/bladerf-hosted.vhd(443): (vcom-1195) Cannot find expanded name "work.reset_synchronizer".
# ** Error: ../vhdl/bladerf-hosted.vhd(443): Unknown expanded name.
# -- Loading entity tx_fifo
# -- Loading entity tx_meta_fifo
# -- Loading entity rx_fifo
# -- Loading entity rx_meta_fifo
# ** Error: (vcom-11) Could not find work.reset_synchronizer.
# ** Error (suppressible): ../vhdl/bladerf-hosted.vhd(584): (vcom-1195) Cannot find expanded name "work.reset_synchronizer".
# ** Error: ../vhdl/bladerf-hosted.vhd(584): Unknown expanded name.
# -- Loading entity fx3_gpif
# -- Loading entity fifo_writer
# -- Loading entity iq_correction
# -- Loading entity fifo_reader
# ** Error: (vcom-11) Could not find work.trigger.
# ** Error (suppressible): ../vhdl/bladerf-hosted.vhd(763): (vcom-1195) Cannot find expanded name "work.trigger".
# ** Error: ../vhdl/bladerf-hosted.vhd(763): Unknown expanded name.
# ** Error: (vcom-11) Could not find work.reset_synchronizer.
# ** Error (suppressible): ../vhdl/bladerf-hosted.vhd(782): (vcom-1195) Cannot find expanded name "work.reset_synchronizer".
# ** Error: ../vhdl/bladerf-hosted.vhd(782): Unknown expanded name.
# ** Error: (vcom-11) Could not find work.trigger.
# ** Error (suppressible): ../vhdl/bladerf-hosted.vhd(792): (vcom-1195) Cannot find expanded name "work.trigger".
# ** Error: ../vhdl/bladerf-hosted.vhd(792): Unknown expanded name.
# -- Loading entity lms6002d
# ** Error: (vcom-11) Could not find work.signal_generator.
# ** Error (suppressible): ../vhdl/bladerf-hosted.vhd(840): (vcom-1195) Cannot find expanded name "work.signal_generator".
# ** Error: ../vhdl/bladerf-hosted.vhd(840): Unknown expanded name.
# -- Loading entity handshake
# ** Error: ../vhdl/bladerf-hosted.vhd(1120): VHDL Compiler exiting
# End time: 20:23:10 on Jan 23,2017, Elapsed time: 0:00:00
# Errors: 28, Warnings: 0
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