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@gzxu
Last active June 25, 2018 16:13
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3×3 SISO State Space in LTspice
.subckt siso33ss U Y
G11 0 X1 X1 0 {a11}
G12 0 X1 X2 0 {a12}
G13 0 X1 X3 0 {a13}
G21 0 X2 X1 0 {a21}
G22 0 X2 X2 0 {a22}
G23 0 X2 X3 0 {a23}
G31 0 X3 X1 0 {a31}
G32 0 X3 X2 0 {a32}
G33 0 X3 X3 0 {a33}
G1 0 X1 U 0 {b1}
G2 0 X2 U 0 {b2}
G3 0 X3 U 0 {b3}
C1 X1 0 1
C2 X2 0 1
C3 X3 0 1
E1 Y AUX12 X1 0 {c1}
E2 AUX12 AUX23 X2 0 {c2}
E3 AUX23 0 X3 0 {c3}
.ends siso33ss
Version 4
SHEET 1 2444 1588
WIRE 304 320 288 320
WIRE 336 320 304 320
WIRE 496 320 416 320
WIRE 576 320 496 320
WIRE 736 320 576 320
WIRE 896 320 736 320
WIRE 992 320 896 320
WIRE 1040 320 992 320
WIRE 1136 320 1088 320
WIRE 1152 320 1136 320
WIRE 416 336 416 320
WIRE 576 336 576 320
WIRE 736 336 736 320
WIRE 896 336 896 320
WIRE 992 336 992 320
WIRE 1088 336 1088 320
WIRE 336 352 336 320
WIRE 368 352 336 352
WIRE 496 352 496 320
WIRE 528 352 496 352
WIRE 688 352 656 352
WIRE 848 352 816 352
WIRE 1040 352 1040 320
WIRE 1088 448 1088 416
WIRE 576 464 416 464
WIRE 656 464 656 352
WIRE 656 464 576 464
WIRE 736 464 656 464
WIRE 896 464 736 464
WIRE 992 464 896 464
WIRE 1040 464 992 464
WIRE 416 480 416 464
WIRE 576 480 576 464
WIRE 736 480 736 464
WIRE 896 480 896 464
WIRE 992 480 992 464
WIRE 1088 480 1088 448
WIRE 336 496 336 352
WIRE 368 496 336 496
WIRE 496 496 496 352
WIRE 528 496 496 496
WIRE 656 496 656 464
WIRE 688 496 656 496
WIRE 816 496 816 352
WIRE 848 496 816 496
WIRE 1040 496 1040 464
WIRE 1088 592 1088 560
WIRE 576 608 416 608
WIRE 736 608 576 608
WIRE 816 608 816 496
WIRE 816 608 736 608
WIRE 896 608 816 608
WIRE 992 608 896 608
WIRE 1040 608 992 608
WIRE 416 624 416 608
WIRE 576 624 576 608
WIRE 736 624 736 608
WIRE 896 624 896 608
WIRE 992 624 992 608
WIRE 1088 624 1088 592
WIRE 336 640 336 496
WIRE 368 640 336 640
WIRE 496 640 496 496
WIRE 528 640 496 640
WIRE 656 640 656 496
WIRE 688 640 656 640
WIRE 816 640 816 608
WIRE 848 640 816 640
WIRE 1040 640 1040 608
FLAG 992 400 0
FLAG 992 544 0
FLAG 992 688 0
FLAG 528 400 0
FLAG 688 400 0
FLAG 848 400 0
FLAG 848 544 0
FLAG 688 544 0
FLAG 528 544 0
FLAG 528 688 0
FLAG 688 688 0
FLAG 848 688 0
FLAG 576 416 0
FLAG 736 416 0
FLAG 896 416 0
FLAG 576 560 0
FLAG 736 560 0
FLAG 896 560 0
FLAG 576 704 0
FLAG 736 704 0
FLAG 896 704 0
FLAG 416 416 0
FLAG 416 560 0
FLAG 416 704 0
FLAG 368 688 0
FLAG 368 544 0
FLAG 368 400 0
FLAG 1088 704 0
FLAG 1040 400 0
FLAG 1040 544 0
FLAG 1040 688 0
FLAG 304 320 U
FLAG 1136 320 Y
FLAG 992 320 X1
FLAG 992 464 X2
FLAG 992 608 X3
FLAG 1088 448 AUX12
FLAG 1088 592 AUX23
SYMBOL g 576 320 R0
SYMATTR InstName G11
SYMATTR Value {a11}
SYMBOL g 736 320 R0
SYMATTR InstName G12
SYMATTR Value {a12}
SYMBOL g 896 320 R0
SYMATTR InstName G13
SYMATTR Value {a13}
SYMBOL g 576 464 R0
SYMATTR InstName G21
SYMATTR Value {a21}
SYMBOL g 736 464 R0
SYMATTR InstName G22
SYMATTR Value {a22}
SYMBOL g 896 464 R0
SYMATTR InstName G23
SYMATTR Value {a23}
SYMBOL g 576 608 R0
SYMATTR InstName G31
SYMATTR Value {a31}
SYMBOL g 736 608 R0
SYMATTR InstName G32
SYMATTR Value {a32}
SYMBOL g 896 608 R0
SYMATTR InstName G33
SYMATTR Value {a33}
SYMBOL g 416 320 R0
SYMATTR InstName G1
SYMATTR Value {b1}
SYMBOL g 416 464 R0
SYMATTR InstName G2
SYMATTR Value {b2}
SYMBOL g 416 608 R0
SYMATTR InstName G3
SYMATTR Value {b3}
SYMBOL cap 976 336 R0
SYMATTR InstName C1
SYMATTR Value 1
SYMBOL cap 976 480 R0
SYMATTR InstName C2
SYMATTR Value 1
SYMBOL cap 976 624 R0
SYMATTR InstName C3
SYMATTR Value 1
SYMBOL e 1088 320 R0
SYMATTR InstName E1
SYMATTR Value {c1}
SYMBOL e 1088 464 R0
SYMATTR InstName E2
SYMATTR Value {c2}
SYMBOL e 1088 608 R0
SYMATTR InstName E3
SYMATTR Value {c3}
.subckt albe_dq ALPHA BETA D Q
V1 SIN 0 SINE(0 1 {f} 0 0 0)
V2 COS 0 SINE(0 1 {f} 0 0 90)
B1 D 0 V=V(ALPHA)*V(SIN)-V(BETA)*V(COS)
B2 Q 0 V=V(ALPHA)*V(COS)+V(BETA)*V(SIN)
.ends albe_dq
Version 4
SHEET 1 2444 1588
FLAG 784 16 0
FLAG 784 144 0
FLAG 864 16 SIN
IOPIN 864 16 Out
FLAG 864 144 COS
IOPIN 864 144 Out
FLAG 752 272 ALPHA
IOPIN 752 272 In
FLAG 752 400 BETA
IOPIN 752 400 In
FLAG 864 272 D
IOPIN 864 272 Out
FLAG 864 400 Q
IOPIN 864 400 Out
FLAG 784 272 0
FLAG 784 400 0
SYMBOL voltage 880 16 R90
WINDOW 0 -32 56 VBottom 2
WINDOW 3 32 56 VTop 2
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR InstName V1
SYMATTR Value SINE(0 1 {f} 0 0 0)
SYMBOL voltage 880 144 R90
WINDOW 0 -32 56 VBottom 2
WINDOW 3 32 56 VTop 2
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR InstName V2
SYMATTR Value SINE(0 1 {f} 0 0 90)
SYMBOL bv 880 272 R90
WINDOW 0 -32 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName B1
SYMATTR Value V=V(ALPHA)*V(SIN)-V(BETA)*V(COS)
SYMBOL bv 880 400 R90
WINDOW 0 -32 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName B2
SYMATTR Value V=V(ALPHA)*V(COS)+V(BETA)*V(SIN)
.subckt dq_albe D Q ALPHA BETA
V1 SIN 0 SINE(0 1 {f} 0 0 0)
V2 COS 0 SINE(0 1 {f} 0 0 90)
B1 ALPHA 0 V=V(D)*V(SIN)+V(Q)*V(COS)
B2 BETA 0 V=-V(D)*V(COS)+V(Q)*V(SIN)
.ends dq_albe
Version 4
SHEET 1 2444 1588
FLAG 784 16 0
FLAG 784 144 0
FLAG 864 16 SIN
IOPIN 864 16 Out
FLAG 864 144 COS
IOPIN 864 144 Out
FLAG 752 272 D
IOPIN 752 272 In
FLAG 752 400 Q
IOPIN 752 400 In
FLAG 864 272 ALPHA
IOPIN 864 272 Out
FLAG 864 400 BETA
IOPIN 864 400 Out
FLAG 784 272 0
FLAG 784 400 0
SYMBOL voltage 880 16 R90
WINDOW 0 -32 56 VBottom 2
WINDOW 3 32 56 VTop 2
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR InstName V1
SYMATTR Value SINE(0 1 {f} 0 0 0)
SYMBOL voltage 880 144 R90
WINDOW 0 -32 56 VBottom 2
WINDOW 3 32 56 VTop 2
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR InstName V2
SYMATTR Value SINE(0 1 {f} 0 0 90)
SYMBOL bv 880 272 R90
WINDOW 0 -32 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName B1
SYMATTR Value V=V(D)*V(SIN)+V(Q)*V(COS)
SYMBOL bv 880 400 R90
WINDOW 0 -32 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName B2
SYMATTR Value V=-V(D)*V(COS)+V(Q)*V(SIN)
.subckt virt_beta ALPHA BETA
C1 1 0 {1/(2*pi*f)}
C2 BETA 0 {1/(2*pi*f)}
G1 0 1 0 1 1
G2 0 1 0 BETA 1
G3 0 1 ALPHA 0 1
G5 0 BETA 1 0 1
.ends virt_beta
Version 4
SHEET 1 2444 1588
WIRE 592 352 480 352
WIRE 704 352 592 352
WIRE 768 352 704 352
WIRE 896 352 768 352
WIRE 928 352 896 352
WIRE 1040 352 976 352
WIRE 1168 352 1040 352
WIRE 1200 352 1168 352
WIRE 480 368 480 352
WIRE 592 368 592 352
WIRE 704 368 704 352
WIRE 768 368 768 352
WIRE 976 368 976 352
WIRE 1040 368 1040 352
WIRE 928 384 928 352
WIRE 656 480 656 432
WIRE 896 480 896 352
WIRE 896 480 656 480
WIRE 544 496 544 432
WIRE 1168 496 1168 352
WIRE 1168 496 544 496
FLAG 432 384 ALPHA
IOPIN 432 384 In
FLAG 1200 352 BETA
IOPIN 1200 352 In
FLAG 592 448 0
FLAG 704 448 0
FLAG 976 448 0
FLAG 1040 432 0
FLAG 928 432 0
FLAG 480 448 0
FLAG 432 432 0
FLAG 768 432 0
FLAG 656 384 0
FLAG 544 384 0
SYMBOL cap 752 368 R0
SYMATTR InstName C1
SYMATTR Value {1/(2*pi*f)}
SYMBOL cap 1024 368 R0
SYMATTR InstName C2
SYMATTR Value {1/(2*pi*f)}
SYMBOL g 704 352 R0
SYMATTR InstName G1
SYMATTR Value 1
SYMBOL g 592 352 R0
SYMATTR InstName G2
SYMATTR Value 1
SYMBOL g 480 352 R0
SYMATTR InstName G3
SYMATTR Value 1
SYMBOL g 976 352 R0
SYMATTR InstName G5
SYMATTR Value 1
* f Vmin Vmax Von Voff
.subckt PWM_GENERATOR IN PWM1 PWM2
V1 1 0 PULSE({Vmin} {Vmax} 0 {.5/f} {.5/f} 0 {1/f})
B2 PWM1 0 V=if(V(IN)>V(1),Von,Voff)
B3 PWM2 0 V=if(V(IN)<V(1),Von,Voff)
.ends
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