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October 18, 2022 06:30
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ESP32-S3 efuse summary
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| $ espefuse.py summary | |
| Connecting.... | |
| Detecting chip type... ESP32-S3 | |
| espefuse.py v3.3.2-dev | |
| === Run "summary" command === | |
| EFUSE_NAME (Block) Description = [Meaningful Value] [Readable/Writeable] (Hex Value) | |
| ---------------------------------------------------------------------------------------- | |
| Config fuses: | |
| DIS_ICACHE (BLOCK0) Disables ICache = False R/W (0b0) | |
| DIS_DCACHE (BLOCK0) Disables DCache = False R/W (0b0) | |
| DIS_DOWNLOAD_ICACHE (BLOCK0) Disables Icache when SoC is in Download mode = False R/W (0b0) | |
| DIS_DOWNLOAD_DCACHE (BLOCK0) Disables Dcache when SoC is in Download mode = False R/W (0b0) | |
| DIS_FORCE_DOWNLOAD (BLOCK0) Disables forcing chip into Download mode = False R/W (0b0) | |
| DIS_CAN (BLOCK0) Disables the TWAI Controller hardware = False R/W (0b0) | |
| DIS_APP_CPU (BLOCK0) Disables APP CPU = False R/W (0b0) | |
| FLASH_TPUW (BLOCK0) Configures flash startup delay after SoC power-up, = 0 R/W (0x0) | |
| unit is (ms/2). When the value is 15, delay is 7. | |
| 5 ms | |
| DIS_DIRECT_BOOT (BLOCK0) Disables direct boot mode = False R/W (0b0) | |
| DIS_USB_SERIAL_JTAG_ROM_PRINT (BLOCK0) Disables USB-Serial-JTAG ROM printing = False R/W (0b0) | |
| FLASH_ECC_MODE (BLOCK0) Configures the ECC mode for SPI flash | |
| = 16-byte to 18-byte mode R/W (0b0) | |
| DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE (BLOCK0) Disables USB-Serial-JTAG download feature in UART = False R/W (0b0) | |
| download boot mode | |
| UART_PRINT_CONTROL (BLOCK0) Sets the default UART boot message output mode = Enabled R/W (0b00) | |
| FLASH_TYPE (BLOCK0) Selects SPI flash type = 4 data lines R/W (0b0) | |
| FLASH_PAGE_SIZE (BLOCK0) Sets the size of flash page = 0 R/W (0b00) | |
| FLASH_ECC_EN (BLOCK0) Enables ECC in Flash boot mode = False R/W (0b0) | |
| FORCE_SEND_RESUME (BLOCK0) Forces ROM code to send an SPI flash resume comman = False R/W (0b0) | |
| d during SPI boot | |
| DIS_USB_OTG_DOWNLOAD_MODE (BLOCK0) Disables USB-OTG download feature in UART download = True R/W (0b1) | |
| boot mode | |
| BLOCK_USR_DATA (BLOCK3) User data | |
| = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W | |
| Efuse fuses: | |
| WR_DIS (BLOCK0) Disables programming of individual eFuses = 0 R/W (0x00000000) | |
| RD_DIS (BLOCK0) Disables software reading from BLOCK4-10 = 0 R/W (0b0000000) | |
| Identity fuses: | |
| SECURE_VERSION (BLOCK0) Secure version (used by ESP-IDF anti-rollback feat = 0 R/W (0x0000) | |
| ure) | |
| MAC (BLOCK1) Factory MAC Address | |
| = 7c:df:a1:e3:6c:5c (OK) R/W | |
| WAFER_VERSION (BLOCK1) WAFER version = 1 R/W (0b001) | |
| PKG_VERSION (BLOCK1) ??? Package version = ESP32-S3 R/W (0x0) | |
| BLOCK1_VERSION (BLOCK1) ??? BLOCK1 efuse version = 1 R/W (0b001) | |
| OPTIONAL_UNIQUE_ID (BLOCK2) ??? Optional unique 128-bit ID | |
| = cb 5b 81 59 16 d2 cb c1 c7 fb a2 fc f6 e1 fe de R/W | |
| BLOCK2_VERSION (BLOCK2) ??? Version of BLOCK2 = No calibration R/W (0b000) | |
| CUSTOM_MAC (BLOCK3) Custom MAC Address | |
| = 00:00:00:00:00:00 (OK) R/W | |
| Security fuses: | |
| SOFT_DIS_JTAG (BLOCK0) Software disables JTAG by programming odd number o = 0 R/W (0b000) | |
| f 1 bit(s). JTAG c |
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