Shit bifting part 1

myhdl_shifting.ipynb

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   "cell_type": "markdown",
   "id": "83813a70-aa01-4341-926e-31d97d6d3023",
   "metadata": {},
   "source": [
    "### MyHDL quick installation"
   ]
  },
  {
   "cell_type": "code",
   "execution_count": 1,
   "id": "f1d3f212-3904-4e48-9631-b4ab600422f5",
   "metadata": {},
   "outputs": [
    {
     "name": "stdout",
     "output_type": "stream",
     "text": [
      "Requirement already satisfied: myhdl in /home/testing/.local/lib/python3.9/site-packages (0.11)\n"
     ]
    }
   ],
   "source": [
    "!pip install myhdl --user"
   ]
  },
  {
   "cell_type": "markdown",
   "id": "e6fa3e8b-41f2-4610-8b01-e6389416daf3",
   "metadata": {},
   "source": [
    "You may need to restart your notebook after installation in order to import myhdl."
   ]
  },
  {
   "cell_type": "code",
   "execution_count": 2,
   "id": "fb7ff462-5a74-4ad7-a2a6-a9f1fb25e32d",
   "metadata": {},
   "outputs": [],
   "source": [
    "from myhdl import *"
   ]
  },
  {
   "cell_type": "markdown",
   "id": "0f4db19c-dbf5-4ae0-82ad-ebfd404c9cea",
   "metadata": {},
   "source": [
    "## Left shifts"
   ]
  },
  {
   "cell_type": "code",
   "execution_count": 3,
   "id": "52d971ab-83fd-4022-b89e-a7b747ee5d1c",
   "metadata": {},
   "outputs": [],
   "source": [
    "MODE_WRAP, MODE_NORMAL = range(2)\n",
    "\n",
    "@block\n",
    "def tb_left(MODE):\n",
    "    a = Signal(intbv()[8:])\n",
    "    if MODE == MODE_WRAP:\n",
    "        b = Signal(modbv(min=0, max=65535))\n",
    "    else:\n",
    "        b = Signal(modbv()[16:])\n",
    "\n",
    "    @instance\n",
    "    def main():\n",
    "        a.next = 0x81\n",
    "        yield delay(1)\n",
    "        for i in range(0, 16):\n",
    "            b.next = a << i\n",
    "            yield delay(1)\n",
    "            print(i, b)\n",
    "            \n",
    "        b.next = 65535\n",
    "        yield delay(1)\n",
    "        if MODE == MODE_WRAP:\n",
    "            assert b == 0x0\n",
    "        else:\n",
    "            assert b == 0xffff\n",
    "        print(b)\n",
    "        \n",
    "    return instances()"
   ]
  },
  {
   "cell_type": "code",
   "execution_count": 4,
   "id": "d9fdf97f-4bf4-4c59-9952-435df2e9de2e",
   "metadata": {},
   "outputs": [
    {
     "name": "stdout",
     "output_type": "stream",
     "text": [
      "0 0081\n",
      "1 0102\n",
      "2 0204\n",
      "3 0408\n",
      "4 0810\n",
      "5 1020\n",
      "6 2040\n",
      "7 4080\n",
      "8 8100\n",
      "9 0201\n",
      "10 0402\n",
      "11 0804\n",
      "12 1008\n",
      "13 2010\n",
      "14 4020\n",
      "15 8040\n",
      "0000\n"
     ]
    },
    {
     "name": "stderr",
     "output_type": "stream",
     "text": [
      "<class 'myhdl.StopSimulation'>: No more events\n"
     ]
    }
   ],
   "source": [
    "t = tb_left(MODE_WRAP)\n",
    "t.config_sim(trace = True)\n",
    "t.run_sim(20)"
   ]
  },
  {
   "cell_type": "markdown",
   "id": "fb2da425-22f9-4db7-aea1-160088d6dc3e",
   "metadata": {},
   "source": [
    "### VHDL simulation\n",
    "\n"
   ]
  },
  {
   "cell_type": "code",
   "execution_count": 5,
   "id": "7fe7049d-9608-4ecf-9f56-1bd92379b892",
   "metadata": {},
   "outputs": [
    {
     "data": {
      "text/plain": [
       "<myhdl._block._Block at 0x7fbfd06cc1c0>"
      ]
     },
     "execution_count": 5,
     "metadata": {},
     "output_type": "execute_result"
    }
   ],
   "source": [
    "u = tb_left(MODE_NORMAL) # Mode MODE_WRAP would fail in conversion\n",
    "u.convert('VHDL')"
   ]
  },
  {
   "cell_type": "code",
   "execution_count": 6,
   "id": "7d3e2d83-0dea-434f-96a5-c23bf62f2e5a",
   "metadata": {},
   "outputs": [],
   "source": [
    "!ghdl -i --std=\"08\" tb_left.vhd pck_myhdl_011.vhd"
   ]
  },
  {
   "cell_type": "code",
   "execution_count": 7,
   "id": "4d6662c8-c0d8-4c97-8424-9db2831280b7",
   "metadata": {},
   "outputs": [
    {
     "name": "stdout",
     "output_type": "stream",
     "text": [
      "analyze pck_myhdl_011.vhd\n",
      "analyze tb_left.vhd\n",
      "elaborate tb_left\n"
     ]
    }
   ],
   "source": [
    "!ghdl -m --std=\"08\" tb_left"
   ]
  },
  {
   "cell_type": "code",
   "execution_count": 8,
   "id": "cccd1bcf-bbdb-4403-93dd-20c9f574bffd",
   "metadata": {},
   "outputs": [
    {
     "name": "stdout",
     "output_type": "stream",
     "text": [
      "0 0081\n",
      "1 0102\n",
      "2 0204\n",
      "3 0408\n",
      "4 0810\n",
      "5 1020\n",
      "6 2040\n",
      "7 4080\n",
      "8 8100\n",
      "9 0200\n",
      "10 0400\n",
      "11 0800\n",
      "12 1000\n",
      "13 2000\n",
      "14 4000\n",
      "15 8000\n",
      "FFFF\n"
     ]
    }
   ],
   "source": [
    "!./tb_left --stop-time=10us"
   ]
  },
  {
   "cell_type": "markdown",
   "id": "70ebb79d-c2df-4213-aa09-93266f1dba54",
   "metadata": {},
   "source": [
    "## Right shifts\n",
    "\n",
    "Keep in mind: Python, unlike Verilog, knows only *arithmetic* shifts."
   ]
  },
  {
   "cell_type": "code",
   "execution_count": 9,
   "id": "97313c67-2a88-4b54-92a4-0baa712392fc",
   "metadata": {},
   "outputs": [],
   "source": [
    "v = -0x10 >> 4\n",
    "assert v == -1"
   ]
  },
  {
   "cell_type": "markdown",
   "id": "930c25fd-3b31-4a29-8d8e-56358d776f85",
   "metadata": {},
   "source": [
    "With a bit vector of specific value, we mimic the length constraint using the `&` operator:"
   ]
  },
  {
   "cell_type": "code",
   "execution_count": 10,
   "id": "bb183825-0143-4dc2-b2de-b41fafaaa90e",
   "metadata": {},
   "outputs": [
    {
     "data": {
      "text/plain": [
       "'0x3ff'"
      ]
     },
     "execution_count": 10,
     "metadata": {},
     "output_type": "execute_result"
    }
   ],
   "source": [
    "NBITS = 10\n",
    "mask = (1 << NBITS) - 1\n",
    "bv = v & mask\n",
    "assert bv == 0x3ff\n",
    "hex(bv)"
   ]
  },
  {
   "cell_type": "code",
   "execution_count": 11,
   "id": "04e87b4f-457e-4e13-b8c0-faff10f0362c",
   "metadata": {},
   "outputs": [],
   "source": [
    "MODE_WRAP, MODE_NORMAL, MODE_SIGNED = range(3)\n",
    "\n",
    "@block\n",
    "def tb_right(MODE):\n",
    "    \n",
    "    M = 8\n",
    "    N = 16\n",
    "\n",
    "    if MODE == MODE_SIGNED:\n",
    "        a = Signal(intbv()[M:].signed())\n",
    "        start = -(2** (M-1)) + 1\n",
    "    else:\n",
    "        a = Signal(intbv()[M:])\n",
    "        start = 2 ** M - 4\n",
    "    if MODE == MODE_WRAP:\n",
    "        b = Signal(modbv(min=0, max=2 ** N -1))\n",
    "    else:\n",
    "        b = Signal(modbv()[N:])\n",
    "\n",
    "    @instance\n",
    "    def main():\n",
    "        a.next = start\n",
    "        yield delay(1)\n",
    "        for i in range(0, M):\n",
    "            b.next = a >> i\n",
    "            yield delay(1)\n",
    "            print(i, b)\n",
    "            \n",
    "        b.next = 65535\n",
    "        yield delay(1)\n",
    "        if MODE == MODE_WRAP:\n",
    "            assert b == 0x0\n",
    "        else:\n",
    "            assert b == 0xffff\n",
    "        print(b)\n",
    "        \n",
    "    return instances()"
   ]
  },
  {
   "cell_type": "code",
   "execution_count": 12,
   "id": "50133702-65b7-4893-9061-835576a7d844",
   "metadata": {},
   "outputs": [
    {
     "name": "stdout",
     "output_type": "stream",
     "text": [
      "0 ff81\n",
      "1 ffc0\n",
      "2 ffe0\n",
      "3 fff0\n",
      "4 fff8\n",
      "5 fffc\n",
      "6 fffe\n",
      "7 ffff\n",
      "ffff\n"
     ]
    },
    {
     "name": "stderr",
     "output_type": "stream",
     "text": [
      "<class 'myhdl.StopSimulation'>: No more events\n"
     ]
    }
   ],
   "source": [
    "tb = tb_right(MODE_SIGNED)\n",
    "tb.config_sim(trace = True)\n",
    "tb.run_sim(20)"
   ]
  }
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