Patch to binutils-2.24 for Lexra processors (LX4180/RLX4181/...)

0001-binutils-2.24-add-lexra-support.patch

--- binutils-2.24.orig/bfd/bfd-in2.h
+++ binutils-2.24/bfd/bfd-in2.h
@@ -1938,6 +1938,12 @@ enum bfd_architecture
 #define bfd_mach_mipsisa64             64
 #define bfd_mach_mipsisa64r2           65
 #define bfd_mach_mips_micromips        96
+#define bfd_mach_mips4180              4180
+#define bfd_mach_mips4181              4181
+#define bfd_mach_mips4281              4281
+#define bfd_mach_mips5181              5181
+#define bfd_mach_mips5280              5280
+#define bfd_mach_mips5281              5281
   bfd_arch_i386,      /* Intel 386 */
 #define bfd_mach_i386_intel_syntax     (1 << 0)
 #define bfd_mach_i386_i8086            (1 << 1)
@@ -2329,7 +2335,9 @@ typedef enum bfd_reloc_status
      generated only when linking i960 coff files with i960 b.out
      symbols.  If this type is returned, the error_message argument
      to bfd_perform_relocation will be set.  */
-  bfd_reloc_dangerous
+  bfd_reloc_dangerous,
+
+  bfd_reloc_notmultipleof8_ltw
  }
  bfd_reloc_status_type;
 
@@ -5762,6 +5770,8 @@ assembler and not (currently) written to
 
 /* Adapteva EPIPHANY - 8 bit immediate for 16 bit mov instruction.  */
   BFD_RELOC_EPIPHANY_IMM8,
+
+  BFD_RELOC_OFF6A,
   BFD_RELOC_UNUSED };
 typedef enum bfd_reloc_code_real bfd_reloc_code_real_type;
 reloc_howto_type *bfd_reloc_type_lookup
--- binutils-2.24.orig/bfd/cpu-mips.c
+++ binutils-2.24/bfd/cpu-mips.c
@@ -99,7 +99,13 @@ enum
   I_mipsocteonp,
   I_mipsocteon2,
   I_xlr,
-  I_micromips
+  I_mips4180,
+  I_mips4181,
+  I_mips4281,
+  I_mips5181,
+  I_mips5280,
+  I_mips5281,
+  I_micromips,
 };
 
 #define NN(index) (&arch_info_struct[(index) + 1])
@@ -143,6 +149,12 @@ static const bfd_arch_info_type arch_inf
   N (64, 64, bfd_mach_mips_octeonp,"mips:octeon+",  FALSE, NN(I_mipsocteonp)),
   N (64, 64, bfd_mach_mips_octeon2,"mips:octeon2",  FALSE, NN(I_mipsocteon2)),
   N (64, 64, bfd_mach_mips_xlr, "mips:xlr",       FALSE, NN(I_xlr)),
+  N (32, 32, bfd_mach_mips4180, "mips:4180",      FALSE, NN(I_mips4180)),
+  N (32, 32, bfd_mach_mips4181, "mips:4181",      FALSE, NN(I_mips4181)),
+  N (32, 32, bfd_mach_mips4281, "mips:4281",      FALSE, NN(I_mips4281)),
+  N (32, 32, bfd_mach_mips5181, "mips:5181",      FALSE, NN(I_mips5181)),
+  N (32, 32, bfd_mach_mips5280, "mips:5280",      FALSE, NN(I_mips5280)),
+  N (32, 32, bfd_mach_mips5281, "mips:5281",      FALSE, NN(I_mips5281)),
   N (64, 64, bfd_mach_mips_micromips,"mips:micromips",FALSE,0)
 };
 
--- binutils-2.24.orig/bfd/elf32-mips.c
+++ binutils-2.24/bfd/elf32-mips.c
@@ -717,6 +717,21 @@ static reloc_howto_type elf_mips_howto_t
 	 0x0,			/* src_mask */
 	 0xffffffff,		/* dst_mask */
 	 FALSE),		/* pcrel_offset */
+
+  /* relocation added by dbb */
+  HOWTO (R_RELOC_OFF6A,         /* type */
+	 3,                     /* rightshift */
+	 2,                     /* size (0 = byte, 1 = short, 2 = long) */
+	 10,                    /* bitsize */
+	 FALSE,                 /* pc_relative */
+	 6,                     /* bitpos */
+	 complain_overflow_dont, /* complain_on_overflow */
+	 NULL,                  /* special_function */
+	 "R_RELOC_OFF6A",       /* name */
+	 TRUE,                  /* partial_inplace */
+	 0x0000FFC0,            /* src_mask */
+	 0x0000FFC0,            /* dst_mask */
+	 FALSE),                /* pcrel_offset */
 };
 
 /* The reloc used for BFD_RELOC_CTOR when doing a 64 bit link.  This
@@ -1906,7 +1921,8 @@ static const struct elf_reloc_map mips_r
   { BFD_RELOC_MIPS_TLS_TPREL32, R_MIPS_TLS_TPREL32 },
   { BFD_RELOC_MIPS_TLS_TPREL64, R_MIPS_TLS_TPREL64 },
   { BFD_RELOC_MIPS_TLS_TPREL_HI16, R_MIPS_TLS_TPREL_HI16 },
-  { BFD_RELOC_MIPS_TLS_TPREL_LO16, R_MIPS_TLS_TPREL_LO16 }
+  { BFD_RELOC_MIPS_TLS_TPREL_LO16, R_MIPS_TLS_TPREL_LO16 },
+  { BFD_RELOC_OFF6A, R_RELOC_OFF6A}
 };
 
 static const struct elf_reloc_map mips16_reloc_map[] =
--- binutils-2.24.orig/bfd/elfxx-mips.c
+++ binutils-2.24/bfd/elfxx-mips.c
@@ -5784,6 +5784,13 @@ mips_elf_calculate_relocation (bfd *abfd
 	}
       break;
 
+    case R_RELOC_OFF6A:
+      value = (symbol + ((addend >> 6) << 3));
+      if ((value % 8) != 0)
+	return bfd_reloc_notmultipleof8_ltw;
+      value = ((value >> 3) << 6) & howto->dst_mask;
+      break;
+
     case R_MIPS_LITERAL:
     case R_MICROMIPS_LITERAL:
       /* Because we don't merge literal sections, we can handle this
@@ -10008,6 +10015,12 @@ _bfd_mips_elf_relocate_section (bfd *out
 	    }
 	  break;
 
+	case bfd_reloc_notmultipleof8_ltw:
+	  msg = _("offset in ltw instruction is not multiple of 8");
+	  info->callbacks->warning
+	    (info, msg, name, input_bfd, input_section, rel->r_offset);
+	  return FALSE;
+
 	case bfd_reloc_ok:
 	  break;
 
--- binutils-2.24.orig/bfd/libbfd.h
+++ binutils-2.24/bfd/libbfd.h
@@ -2809,6 +2809,7 @@ static const char *const bfd_reloc_code_
   "BFD_RELOC_EPIPHANY_SIMM11",
   "BFD_RELOC_EPIPHANY_IMM11",
   "BFD_RELOC_EPIPHANY_IMM8",
+  "BFD_RELOC_OFF6A",
  "@@overflow: BFD_RELOC_UNUSED@@",
 };
 #endif
--- binutils-2.24.orig/bfd/reloc.c
+++ binutils-2.24/bfd/reloc.c
@@ -50,6 +50,7 @@ SECTION
 #include "bfd.h"
 #include "bfdlink.h"
 #include "libbfd.h"
+#include "elf/mips.h"
 /*
 DOCDD
 INODE
@@ -831,6 +832,15 @@ space consuming.  For each target:
      }
      */
 
+  /* TODO: should not be there? */
+  switch (howto->type)
+    {
+    case R_RELOC_OFF6A:
+      if ((relocation % 8) != 0)
+        return bfd_reloc_notmultipleof8_ltw;
+      break;
+    }
+
   relocation >>= (bfd_vma) howto->rightshift;
 
   /* Shift everything up to where it's going to be used.  */
@@ -1210,6 +1220,14 @@ space consuming.  For each target:
      }
      */
 
+  switch (howto->type)
+    {
+    case R_RELOC_OFF6A:
+      if ((relocation % 8) != 0)
+        return bfd_reloc_notmultipleof8_ltw;
+      break;
+    }
+
   relocation >>= (bfd_vma) howto->rightshift;
 
   /* Shift everything up to where it's going to be used.  */
--- binutils-2.24.orig/gas/config/tc-mips.c
+++ binutils-2.24/gas/config/tc-mips.c
@@ -103,6 +103,32 @@ static char *mips_regmask_frag;
 #define FP  30
 #define RA  31
 
+#define M0L      1
+#define M0H      2
+#define M0       3
+#define M1L      5
+#define M1H      6
+#define M1       7
+#define M2L      9
+#define M2H     10
+#define M2      11
+#define M3L     13
+#define M3H     14
+#define M3      15
+#define ESTATUS  0
+#define ECAUSE   1
+#define INTVEC   2
+#define CBS0     0
+#define CBS1     1
+#define CBS2     2
+#define CBE0     4
+#define CBE1     5
+#define CBE2     6
+#define LPS0    16
+#define LPE0    17
+#define LPC0    18
+#define MMD     24
+
 #define ILLEGAL_REG (32)
 
 #define AT  mips_opts.at
@@ -294,6 +320,8 @@ static unsigned int file_ase;
 /* Which bits of file_ase were explicitly set or cleared by ASE options.  */
 static unsigned int file_ase_explicit;
 
+static const struct mips_opcode dummy_opcode = { NULL, NULL, 0, 0, 0, 0, 0, 0, 0 };
+
 /* These variables are filled in with the masks of registers used.
    The object format code reads them and puts them in the appropriate
    place.  */
@@ -498,6 +526,9 @@ static int mips_32bitmode = 0;
    || mips_opts.arch == CPU_R3900                     \
    || mips_opts.arch == CPU_R5900                     \
    || mips_opts.micromips                             \
+   || mips_opts.arch == CPU_RLX4281                   \
+   || mips_opts.arch == CPU_LX5280                    \
+   || mips_opts.arch == CPU_RLX5281                   \
    )
 
 /* Whether the processor uses hardware interlocks to avoid delays
@@ -1282,6 +1313,10 @@ static bfd_boolean pic_need_relax (symbo
 static int relaxed_branch_length (fragS *, asection *, int);
 static int relaxed_micromips_16bit_branch_length (fragS *, asection *, int);
 static int relaxed_micromips_32bit_branch_length (fragS *, asection *, int);
+static inline int rlx_nops_for_new_insn (const struct mips_cl_insn *, const struct mips_cl_insn *);
+static inline int rlx_is_insn_lt (const struct mips_cl_insn *, const struct mips_cl_insn *);
+static inline int rlx_is_insn_st (const struct mips_cl_insn *, const struct mips_cl_insn *);
+static inline int rlx_is_insn_swappable (const struct mips_cl_insn *, const struct mips_cl_insn *);
 
 /* Table and functions used to map between CPU/ISA names, and
    ISA levels, and CPU numbers.  */
@@ -2515,6 +2550,33 @@ struct regname {
 #define MIPS16_SPECIAL_REGISTER_NAMES \
     {"$pc",	RTYPE_PC | 0}
 
+#define RLX_REGISTER_ALIAS_NAMES \
+    {"$m0l",	RTYPE_GP | 1},  \
+    {"$m0h",	RTYPE_GP | 2},  \
+    {"$m0",	RTYPE_GP | 3},  \
+    {"$m1l",	RTYPE_GP | 5},  \
+    {"$m1h",	RTYPE_GP | 6},  \
+    {"$m1",	RTYPE_GP | 7},  \
+    {"$m2l",	RTYPE_GP | 9}, \
+    {"$m2h",	RTYPE_GP | 10}, \
+    {"$m2",	RTYPE_GP | 11}, \
+    {"$m3l",	RTYPE_GP | 13}, \
+    {"$m3l",	RTYPE_GP | 14}, \
+    {"$m3",	RTYPE_GP | 15}, \
+    {"$estatus",	RTYPE_GP | 0}, \
+    {"$ecause",	RTYPE_GP | 1}, \
+    {"$intvec",	RTYPE_GP | 2}, \
+    {"$mmd",	RTYPE_GP | 24}, \
+    {"$cbs0",	RTYPE_GP | 0}, \
+    {"$cbs1",	RTYPE_GP | 1}, \
+    {"$cbs2",	RTYPE_GP | 2}, \
+    {"$cbe0",	RTYPE_GP | 4}, \
+    {"$cbe1",	RTYPE_GP | 5}, \
+    {"$cbe2",	RTYPE_GP | 6}, \
+    {"$lps0",	RTYPE_GP | 16}, \
+    {"$lpe0",	RTYPE_GP | 17}, \
+    {"$lpc0",	RTYPE_GP | 18}
+
 #define MDMX_VECTOR_REGISTER_NAMES \
     /* {"$v0",	RTYPE_VEC | 0},  clash with REG 2 above */ \
     /* {"$v1",	RTYPE_VEC | 1},  clash with REG 3 above */ \
@@ -2580,6 +2642,7 @@ static const struct regname reg_names[]
   SYMBOLIC_REGISTER_NAMES,
 
   MIPS16_SPECIAL_REGISTER_NAMES,
+  RLX_REGISTER_ALIAS_NAMES,
   MDMX_VECTOR_REGISTER_NAMES,
   R5900_I_NAMES,
   R5900_Q_NAMES,
@@ -3185,10 +3248,13 @@ validate_mips_insn (const struct mips_op
       case '(':
       case ')':
 	break;
-
+ 
       case '#':
-	s++;
-	break;
+        if (s[1] == '+' || s[1] == '-')
+          {
+	  s++;
+	  break;
+          }
 
       default:
 	if (!decode_operand)
@@ -3216,6 +3282,15 @@ validate_mips_insn (const struct mips_op
 	/* Skip prefix characters.  */
 	if (decode_operand && (*s == '+' || *s == 'm'))
 	  ++s;
+
+	if (decode_operand && *s == '#')
+          {
+          if (s[1] == 'd' || s[1] == 's' || s[1] == 't')
+            s += 2;
+          else if (s[1] != '+' && s[1] != '-')
+            s++;
+          }
+
 	opno += 1;
 	break;
       }
@@ -3994,6 +4069,7 @@ operand_reg_mask (const struct mips_cl_i
   switch (operand->type)
     {
     case OP_INT:
+    case OP_INT_LX:
     case OP_MAPPED_INT:
     case OP_MSB:
     case OP_PCREL:
@@ -4408,6 +4484,18 @@ convert_reg_type (const struct mips_opco
 
     case OP_REG_R5900_ACC:
       return RTYPE_R5900_ACC;
+
+    case OP_REG_LX_EVEN_REG:
+      return RTYPE_NUM | RTYPE_GP;
+
+    case OP_REG_LX_COPRO:
+    case OP_REG_LX_DST_REG_1:
+    case OP_REG_LX_DST_REG_2:
+    case OP_REG_LX_DST_REG_3:
+      return RTYPE_NUM;
+
+    case OP_REG_LX_DST_REG_4:
+      return RTYPE_NUM | RTYPE_CP0;
     }
   abort ();
 }
@@ -4445,6 +4533,49 @@ check_regno (struct mips_arg_info *arg,
 	as_warn (_("condition code register should be 0 or 4 for %s, was %d"),
 		 name, regno);
     }
+
+  if (type == OP_REG_LX_EVEN_REG)
+    {
+    if (regno > 31)
+      as_bad (_("invalid register number (%d)"), regno);
+
+    if (regno % 2 != 0)
+      as_bad (_("not an even register number(%d) "), regno);
+    }
+
+  if (type == OP_REG_LX_COPRO)
+    {
+    if (regno > 63)
+      as_bad (_("invalid coprocessor stype value (0-63)"));
+    }
+
+  if (type == OP_REG_LX_DST_REG_1)
+    {
+    if (regno <= 0 || regno > 15 || (regno & 3) != 3)
+      as_bad (_("RADIAX: illegal register (%d) in %s type d1"),
+              regno, arg->insn->insn_mo->name);
+    }
+
+  if (type == OP_REG_LX_DST_REG_2)
+    {
+    if (regno <= 0 || regno > 15 || (regno & 3) == 0)
+      as_bad (_("RADIAX: illegal register (%d) in %s type d2"),
+              regno, arg->insn->insn_mo->name);
+    }
+
+  if (type == OP_REG_LX_DST_REG_3)
+    {
+    if (regno <= 0 || regno > 15 || (regno & 3) == 0 || (regno & 3) == 3)
+      as_bad (_("RADIAX: illegal register (%d) in %s type d3"),
+              regno, arg->insn->insn_mo->name);
+    }
+
+  if (type == OP_REG_LX_DST_REG_4)
+    {
+    if (regno > 31)
+      as_bad (_("RLX: illegal register (%d) in %s type d4"),
+              regno, arg->insn->insn_mo->name);
+    }
 }
 
 /* ARG is a register with symbol value SYMVAL.  Try to interpret it as
@@ -4608,6 +4739,64 @@ match_int_operand (struct mips_arg_info
   return TRUE;
 }
 
+/* OP_INT_LX matcher.  */
+
+static bfd_boolean
+match_int_rlx_operand (struct mips_arg_info *arg,
+		   const struct mips_operand *operand_base)
+{
+  const struct mips_int_operand *operand;
+  unsigned int uval;
+  int min_val, max_val, factor;
+  offsetT sval;
+
+  struct mips_int_operand real_operand = { \
+    { OP_INT_LX, 8, 8 }, 0x3ff, 0, 3, FALSE \
+  };
+
+  if (!strncmp(arg->insn->insn_mo->name, "lbp", 3) ||
+      !strncmp(arg->insn->insn_mo->name, "sbp", 3))
+    {
+    real_operand.shift = 0;
+    real_operand.max_val = 0x7f;
+    }
+
+  if (!strncmp(arg->insn->insn_mo->name, "lhp", 3) ||
+      !strncmp(arg->insn->insn_mo->name, "shp", 3))
+    {
+    real_operand.shift = 1;
+    real_operand.max_val = 0xff;
+    }
+
+  if (!strncmp(arg->insn->insn_mo->name, "lwp", 3) ||
+      !strncmp(arg->insn->insn_mo->name, "swp", 3))
+    {
+    real_operand.shift = 2;
+    real_operand.max_val = 0x1ff;
+    }
+
+  operand = &real_operand;
+  factor = 1 << operand->shift;
+  min_val = mips_int_operand_min (operand);
+  max_val = mips_int_operand_max (operand);
+
+  if (!match_const_int (arg, &sval))
+    return FALSE;
+
+  arg->last_op_int = sval;
+
+  if (sval < min_val || sval > max_val || sval % factor)
+    {
+      match_out_of_range (arg);
+      return FALSE;
+    }
+
+  uval = (unsigned int) sval >> operand->shift;
+
+  insn_insert_operand (arg->insn, operand_base, uval);
+  return TRUE;
+}
+
 /* OP_MAPPED_INT matcher.  */
 
 static bfd_boolean
@@ -5375,6 +5564,9 @@ match_operand (struct mips_arg_info *arg
     case OP_INT:
       return match_int_operand (arg, operand);
 
+    case OP_INT_LX:
+      return match_int_rlx_operand (arg, operand);
+
     case OP_MAPPED_INT:
       return match_mapped_int_operand (arg, operand);
 
@@ -5561,6 +5753,12 @@ insns_between (const struct mips_cl_insn
       if ((!gpr_interlocks && (pinfo1 & INSN_LOAD_MEMORY_DELAY))
 	  || (!cop_interlocks && (pinfo1 & INSN_LOAD_COPROC_DELAY)))
 	{
+	  /* 2006-01-06 tonywu: insn2 == NULL => mips_optimize = 0 */
+	  /* 2006-10-16 tonywu: fix lt nop bug */
+	  if (rlx_is_insn_lt (insn1, insn2) || rlx_is_insn_st (insn1, insn2))
+	    return 1;
+	  /* 2006-10-16 tonywu: fix lt nop bug */
+
 	  if (insn2 == NULL || (gpr_read_mask (insn2) & gpr_write_mask (insn1)))
 	    return 1;
 	}
@@ -5612,7 +5810,7 @@ insns_between (const struct mips_cl_insn
 	return 1;
     }
 
-  return 0;
+  return rlx_nops_for_new_insn (insn1, insn2);
 }
 
 /* Return the number of nops that would be needed to work around the
@@ -5884,6 +6082,35 @@ nops_for_insn (int ignore, const struct
   return nops;
 }
 
+/* 2006-01-09 tonywu: fix branch delay slot filling bug */
+static inline int
+rlx_is_insn_swappable (const struct mips_cl_insn *hist,
+                       const struct mips_cl_insn *insn)
+{
+
+  unsigned long pinfo1, pinfo2;
+
+  pinfo1 = hist[0].insn_mo->pinfo;
+  pinfo2 = hist[1].insn_mo->pinfo;
+
+  if (pinfo1 & INSN_LOAD_MEMORY_DELAY || gpr_write_mask(&hist[0]))
+    {
+      if (gpr_read_mask (insn) & (1 << EXTRACT_OPERAND (mips_opts.micromips, RT, hist[0])))
+        {
+          return 1;
+        }
+    }
+
+  if (pinfo2 & INSN_LOAD_MEMORY_DELAY || gpr_write_mask(&hist[0]))
+    {
+      if (gpr_read_mask (insn) & (1 << EXTRACT_OPERAND (mips_opts.micromips, RT, hist[1])))
+        {
+          return 1;
+        }
+    }
+  return 0;
+}
+
 /* The variable arguments provide NUM_INSNS extra instructions that
    might be added to HIST.  Return the largest number of nops that
    would be needed after the extended sequence, ignoring hazards
@@ -6064,6 +6291,9 @@ can_swap_branch_p (struct mips_cl_insn *
   if (nops_for_sequence (2, 0, history + 1, ip, history) > 0)
     return FALSE;
 
+  if (rlx_is_insn_swappable (history, ip) > 0)
+    return FALSE;
+
   /* If the branch reads a register that the previous
      instruction sets, we can not swap.  */
   gpr_read = gpr_read_mask (ip);
@@ -6071,6 +6301,9 @@ can_swap_branch_p (struct mips_cl_insn *
   if (gpr_read & prev_gpr_write)
     return FALSE;
 
+  if (rlx_is_insn_lt (history, ip))
+    return FALSE;
+
   /* If the branch writes a register that the previous
      instruction sets, we can not swap.  */
   gpr_write = gpr_write_mask (ip);
@@ -7119,7 +7352,6 @@ match_insn (struct mips_cl_insn *insn, c
 	      ++arg.token;
 	      continue;
 	    }
-	  return FALSE;
 	}
 
       /* Handle special macro operands.  Work out the properties of
@@ -7221,6 +7453,14 @@ match_insn (struct mips_cl_insn *insn, c
       if (*args == '+' || *args == 'm')
 	args++;
 
+      if (*args == '#')
+        {
+        if (args[1] == 'd' || args[1] == 's' || args[1] == 't')
+          args += 2;
+        else if (args[1] != '+' && args[1] != '-')
+          args++;
+        }
+
       if (mips_optional_operand_p (operand)
 	  && args[1] == ','
 	  && (arg.token[0].type != OT_REG
@@ -7871,6 +8111,14 @@ macro_build (expressionS *ep, const char
 
 	  if (*fmt == '+' || *fmt == 'm')
 	    ++fmt;
+
+	  if (*fmt == '#')
+            {
+            if (fmt[1] == 'd' || fmt[1] == 's' || fmt[1] == 't')
+              fmt += 2;
+            else if (fmt[1] != '+' && fmt[1] != '-')
+              fmt++;
+            }
 	  break;
 	}
     }
@@ -13783,6 +14031,9 @@ mips_after_parse_args (void)
   if (mips_arch_string != 0)
     arch_info = mips_parse_cpu ("-march", mips_arch_string);
 
+  if (mips_tune_string != 0)
+    mips_set_architecture (mips_parse_cpu ("-mtune", mips_tune_string));
+
   if (file_mips_isa != ISA_UNKNOWN)
     {
       /* Handle -mipsN.  At this point, file_mips_isa contains the
@@ -14411,6 +14662,39 @@ md_apply_fix (fixS *fixP, valueT *valP,
       fixP->fx_done = 0;
       break;
 
+    case BFD_RELOC_OFF6A:
+      if (fixP->fx_done)
+        {
+          valueT tmp_value;
+          valueT org_value;
+
+          buf = (char *) (fixP->fx_frag->fr_literal + fixP->fx_where);
+          tmp_value =
+            *(valueT *) (fixP->fx_frag->fr_literal + fixP->fx_where);
+          org_value = *valP;
+
+          if (target_big_endian)
+            {
+              tmp_value =
+                (((tmp_value & 0xff) << 24) |
+                 ((tmp_value & 0xff00) << 8) |
+                 (((tmp_value & 0xff0000) >> 8)) |
+                 (((tmp_value & 0xff000000) >> 24)));
+            }
+
+          if ((org_value % 8) != 0)
+            as_bad (_("(%d) is not multiple of 8"), (int) org_value);
+
+          if ((org_value & ~0x1FFF) != 0)
+            as_bad (_("(%d) is too large to stay in 13 bits"),
+                    (int) org_value);
+
+          tmp_value |=
+            (((org_value >> 3) & OP_MASK_OFFSET6A) << OP_SH_OFFSET6A);
+          md_number_to_chars ((char *) buf, tmp_value, 4);
+        }
+      break;
+
     default:
       abort ();
     }
@@ -17666,6 +17950,14 @@ static const struct mips_cpu_info mips_c
   { "mips64",         MIPS_CPU_IS_ISA, 0,	ISA_MIPS64,   CPU_MIPS64 },
   { "mips64r2",       MIPS_CPU_IS_ISA, 0,	ISA_MIPS64R2, CPU_MIPS64R2 },
 
+  /* Lexra processors */
+  { "lx4180",	      0, 0,			ISA_MIPS1,    CPU_LX4180 },
+  { "rlx4181",	      0, 0,			ISA_MIPS1,    CPU_RLX4181 },
+  { "rlx4281",	      0, 0,			ISA_MIPS1,    CPU_RLX4281 },
+  { "rlx5181",	      0, 0,			ISA_MIPS1,    CPU_RLX5181 },
+  { "lx5280",	      0, 0,			ISA_MIPS1,    CPU_LX5280 },
+  { "rlx5281",	      0, 0,			ISA_MIPS1,    CPU_RLX5281 },
+
   /* MIPS I */
   { "r3000",          0, 0,			ISA_MIPS1,    CPU_R3000 },
   { "r2000",          0, 0,			ISA_MIPS1,    CPU_R3000 },
@@ -17832,14 +18124,27 @@ mips_matching_cpu_name_p (const char *ca
 
   /* If not, try comparing based on numerical designation alone.
      See if GIVEN is an unadorned number, or 'r' followed by a number.  */
-  if (TOLOWER (*given) == 'r')
+  /* 2006-01-19 tonywu: add to parse LX/RLX CPUs */
+  if (TOLOWER (given[0]) == 'l' && TOLOWER (given[1]) == 'x')
+    given += 2;
+  else if (TOLOWER (given[0]) == 'r' &&
+           TOLOWER (given[1]) == 'l' && TOLOWER (given[2]) == 'x')
+    given += 3;
+  else if (TOLOWER (*given) == 'r')
     given++;
+
   if (!ISDIGIT (*given))
     return FALSE;
 
   /* Skip over some well-known prefixes in the canonical name,
      hoping to find a number there too.  */
-  if (TOLOWER (canonical[0]) == 'v' && TOLOWER (canonical[1]) == 'r')
+  /* 2006-01-19 tonywu: add to parse LX/RLX CPUs */
+  if (TOLOWER (canonical[0]) == 'l' && TOLOWER (canonical[1]) == 'x')
+    canonical += 2;
+  else if (TOLOWER (canonical[0]) == 'r' &&
+           TOLOWER (canonical[1]) == 'l' && TOLOWER (canonical[2]) == 'x')
+    canonical += 3;
+  else if (TOLOWER (canonical[0]) == 'v' && TOLOWER (canonical[1]) == 'r')
     canonical += 2;
   else if (TOLOWER (canonical[0]) == 'r' && TOLOWER (canonical[1]) == 'm')
     canonical += 2;
@@ -18121,3 +18426,84 @@ tc_mips_regname_to_dw2regnum (char *regn
 
   return regnum;
 }
+
+static inline int
+rlx_is_insn_lt (const struct mips_cl_insn *insn1,
+                const struct mips_cl_insn *insn2)
+{
+  int is_lt = 0;
+
+  if (insn1 == NULL || insn2 == NULL)
+    return 0;
+
+  if (strncmp (insn1->insn_mo->name, "lt", 2) == 0)
+    is_lt = 1;
+  else if (strncmp (insn1->insn_mo->name, "ltw", 3) == 0)
+    is_lt = 1;
+
+  if (is_lt == 0)
+    return 0;
+
+  int regno_mask1 = 1 << (EXTRACT_OPERAND (mips_opts.micromips, RT, *insn1));
+  int regno_mask2 = regno_mask1 << 1;
+
+  if (gpr_read_mask(insn2) & (regno_mask1 | regno_mask2))
+    return 1;
+
+  return 0;
+}
+
+static inline int
+rlx_is_insn_st (const struct mips_cl_insn *insn1,
+                const struct mips_cl_insn *insn2)
+{
+  int is_st = 0;
+
+  if (insn1 == NULL || insn2 == NULL)
+    return 0;
+
+  if (strncmp (insn2->insn_mo->name, "st", 2) == 0)
+    is_st = 1;
+
+  if (is_st == 0)
+    return 0;
+
+  int regno1 = EXTRACT_OPERAND (mips_opts.micromips, RT, *insn1);
+  int regno2 = 0;
+
+  if (regno1 % 2 == 0)
+    regno2 = regno1 + 1;
+  else
+    regno2 = regno1 - 1;
+
+  int regno_mask1 = 1 << regno1;
+  int regno_mask2 = 1 << regno2;
+
+  if (gpr_read_mask(insn2) & (regno_mask1 | regno_mask2))
+    return 1;
+
+  return 0;
+}
+
+/* 2006-01-05 tonywu: merged from 2.14 */
+static inline int
+rlx_nops_for_new_insn (const struct mips_cl_insn *pre,
+                       const struct mips_cl_insn *now)
+{
+  if ((pre == NULL) || (now == NULL))
+    return 0;
+
+  if ((pre->insn_mo->match == 0 && pre->insn_mo->mask == 0xffffffff) ||
+      (now->insn_mo->match == 0 && now->insn_mo->mask == 0xffffffff))
+    return 0;
+
+  if (pre->insn_mo == &dummy_opcode || now->insn_mo == &dummy_opcode)
+    return 0;
+
+  if (strcmp (pre->insn_mo->name, "madda") == 0 &&
+      strcmp (now->insn_mo->name, "mfa") == 0 &&
+      EXTRACT_OPERAND (0, RD, *pre) == EXTRACT_OPERAND (0, RT, *now))
+    return 2;
+
+  return 0;
+}
--- binutils-2.24.orig/gas/write.c
+++ binutils-2.24/gas/write.c
@@ -1162,6 +1162,9 @@ install_reloc (asection *sec, arelent *r
     case bfd_reloc_outofrange:
       as_bad_where (file, line, _("relocation out of range"));
       break;
+    case bfd_reloc_notmultipleof8_ltw:
+      as_bad_where (file, line, _("offset in ltw instruction is not multiple of 8"));
+      break;
     default:
       as_fatal (_("%s:%u: bad return from bfd_install_relocation: %x"),
 		file, line, s);
--- binutils-2.24.orig/include/elf/mips.h
+++ binutils-2.24/include/elf/mips.h
@@ -89,7 +89,8 @@ START_RELOC_NUMBERS (elf_mips_reloc_type
   RELOC_NUMBER (R_MIPS_TLS_TPREL_HI16, 49)
   RELOC_NUMBER (R_MIPS_TLS_TPREL_LO16, 50)
   RELOC_NUMBER (R_MIPS_GLOB_DAT, 51)
-  FAKE_RELOC (R_MIPS_max, 52)
+  RELOC_NUMBER (R_RELOC_OFF6A, 52)
+  FAKE_RELOC (R_MIPS_max, 53)
   /* These relocs are used for the mips16.  */
   FAKE_RELOC (R_MIPS16_min, 100)
   RELOC_NUMBER (R_MIPS16_26, 100)
--- binutils-2.24.orig/include/opcode/mips.h
+++ binutils-2.24/include/opcode/mips.h
@@ -331,6 +331,22 @@
 /* Enhanced VA Scheme */
 #define OP_SH_EVAOFFSET		7
 #define OP_MASK_EVAOFFSET	0x1ff
+ 
+#define OP_MASK_IMMIDATE74	0xf		/* used in MFA,MFA2,RNDA2 */
+#define OP_SH_IMMIDATE74	7		/* used in MFA,MFA2,RNDA2 */
+#define OP_MASK_IMMIDATE6b	0x7ff		/* used in lt,st */
+#define OP_SH_IMMIDATE6b	6		/* used in lt,st */
+#define OP_MASK_IMMIDATE88	0xff		/* used in lbp,stp,etc */
+#define OP_SH_IMMIDATE88	8		/* used in lbp,stp,etc */
+#define OP_MASK_EVENREG		0x1f		/* used in lt,st,ltp,stp */
+#define OP_SH_EVENREG		16		/* used in lt,st,ltp,stp */
+#define OP_MASK_OFFSET6A	0x3ff		/* used in ltw */
+#define OP_SH_OFFSET6A		6		/* used in ltw */
+
+#define OP_MASK_RLX_SEL		0x3f
+#define OP_SH_RLX_SEL		0
+#define OP_MASK_RLX_STYPE	0x3f
+#define OP_SH_RLX_STYPE		6
 
 /* Enumerates the various types of MIPS operand.  */
 enum mips_operand_type {
@@ -413,7 +429,10 @@ enum mips_operand_type {
 
   /* Like OP_VU0_SUFFIX, but used when the operand's value has already
      been set.  Any suffix used here must match the previous value.  */
-  OP_VU0_MATCH_SUFFIX
+  OP_VU0_MATCH_SUFFIX,
+
+  /* Immediate operand used in lbp, stp, etc in Lexra processors. */
+  OP_INT_LX
 };
 
 /* Enumerates the types of MIPS register.  */
@@ -454,7 +473,19 @@ enum mips_reg_operand_type {
   OP_REG_R5900_I,
   OP_REG_R5900_Q,
   OP_REG_R5900_R,
-  OP_REG_R5900_ACC
+  OP_REG_R5900_ACC,
+
+  /* Lexra registers for lt,st,ltp,stp */
+  OP_REG_LX_EVEN_REG,
+
+  /* Lexra registers for lx coprocessors */
+  OP_REG_LX_COPRO,
+
+  /* Lexra registers for #d, #s, #t */
+  OP_REG_LX_DST_REG_1,
+  OP_REG_LX_DST_REG_2,
+  OP_REG_LX_DST_REG_3,
+  OP_REG_LX_DST_REG_4,
 };
 
 /* Base class for all operands.  */
@@ -896,6 +927,14 @@ struct mips_opcode
    ","  separates operands
    "+"  Start of extension sequence.
 
+*********************** dbb  modified for supporting radiax instructions **************************
+   "@"  11 bits immediate used in lt,st (OP_*_IMMIDATE6b),in fact it is 14 bits,mutiple of 8;
+   "#"  4 bits immediate from 0 to 8,used in MFA,MFA2,RNDA2 (OP_*_IMMIDATE74)
+   "~"  8 bits immediate ,used in lbp,stp,etc(OP_*_IMMIDATE88)
+   "`"  even register,used in lt,st,ltp,stp (OP_*_EVENREG)
+   "-"  10 bits offset,used in ltw(OP_*_OFFSET6A)
+*********************** dbb  modified for supporting radiax instructions **************************
+
    Characters used so far, for quick reference when adding more:
    "1234567890"
    "%[]<>(),+:'@!#$*&\~"
@@ -1055,7 +1094,7 @@ static const unsigned int mips_isa_table
   { 0x0001, 0x0003, 0x0607, 0x1e0f, 0x3e1f, 0x0a23, 0x3e63, 0x3ebf, 0x3fff };
 
 /* Masks used for Chip specific instructions.  */
-#define INSN_CHIP_MASK		  0xc3ff0f20
+#define INSN_CHIP_MASK		  0xffff0fe0
 
 /* Cavium Networks Octeon instructions.  */
 #define INSN_OCTEON		  0x00000800
@@ -1095,6 +1134,14 @@ static const unsigned int mips_isa_table
 /* RMI Xlr instruction */
 #define INSN_XLR                 0x00000020
 
+/* Lexra LX/RLX instructions */
+#define INSN_4180                 0x20000000
+#define INSN_4181                 0x10000000
+#define INSN_4281                 0x0c000000
+#define INSN_5181                 0x08000000
+#define INSN_5280                 0x00000080
+#define INSN_5281                 0x00000040
+
 /* DSP ASE */
 #define ASE_DSP			0x00000001
 #define ASE_DSP64		0x00000002
@@ -1172,6 +1219,12 @@ static const unsigned int mips_isa_table
 #define CPU_OCTEONP	6601
 #define CPU_OCTEON2	6502
 #define CPU_XLR     	887682   	/* decimal 'XLR'   */
+#define CPU_LX4180      4180    /*  LX4180 */
+#define CPU_RLX4181     4181    /* RLX4181 */
+#define CPU_RLX4281     4281    /* RLX4281 */
+#define CPU_RLX5181     5181    /* RLX5181 */
+#define CPU_RLX5281     5281    /* RLX5281 */
+#define CPU_LX5280      5280    /*  LX5280 */
 
 /* Return true if the given CPU is included in INSN_* mask MASK.  */
 
@@ -1239,6 +1292,24 @@ cpu_is_member (int cpu, unsigned int mas
     case CPU_XLR:
       return (mask & INSN_XLR) != 0;
 
+    case CPU_LX4180:
+      return (mask & INSN_4180) != 0;
+
+    case CPU_RLX4181:
+      return (mask & INSN_4181) != 0;
+
+    case CPU_RLX4281:
+      return (mask & INSN_4281) != 0;
+
+    case CPU_RLX5181:
+      return (mask & INSN_5181) != 0;
+
+    case CPU_LX5280:
+      return (mask & INSN_5280) != 0;
+
+    case CPU_RLX5281:
+      return (mask & INSN_5281) != 0;
+
     default:
       return FALSE;
     }
--- binutils-2.24.orig/opcodes/mips16-opc.c
+++ binutils-2.24/opcodes/mips16-opc.c
@@ -180,6 +180,11 @@ decode_mips16_operand (char type, bfd_bo
 #define I64	INSN_ISA64
 #define T3	INSN_3900
 
+#define RLX1	(INSN_4180 | INSN_4181 | INSN_4281 | INSN_5181 | INSN_5280 | INSN_5281)
+#define RLX2	(INSN_4181 | INSN_4281 | INSN_5181 | INSN_5280 | INSN_5281)
+#define RLX3	(INSN_4181 | INSN_4281 | INSN_5181 | INSN_5281)
+#define RLX4	(INSN_5181 | INSN_5280 | INSN_5281)
+
 const struct mips_opcode mips16_opcodes[] =
 {
 /* name,    args,	match,	mask,		pinfo,	         	pinfo2, membership */
@@ -224,6 +229,7 @@ const struct mips_opcode mips16_opcodes[
 {"bne",     "x,I,p",	0, (int) M_BNE_I,	INSN_MACRO,		0,		I1,	0,	0 },
 {"bnez",    "x,p",	0x2800, 0xf800,		RD_1,			CBR,		I1,	0,	0 },
 {"break",   "6",	0xe805, 0xf81f,		TRAP,			0,		I1,	0,	0 },
+{"break",   "",		0xe805, 0xffff,		TRAP,			0,		RLX1,	0,	0 },
 {"bteqz",   "p",	0x6000, 0xff00,		RD_T,			CBR,		I1,	0,	0 },
 {"btnez",   "p",	0x6100, 0xff00,		RD_T,			CBR,		I1,	0,	0 },
 {"cmpi",    "x,U",	0x7000, 0xf800,		RD_1|WR_T,		0,		I1,	0,	0 },
@@ -308,10 +314,18 @@ const struct mips_opcode mips16_opcodes[
 {"lw",	    "x,V(P)",	0xb000, 0xf800,		WR_1,			RD_PC,		I1,	0,	0 },
 {"lw",	    "x,V(S)",	0x9000, 0xf800,		WR_1,			RD_SP,		I1,	0,	0 },
 {"lwu",     "y,W(x)",	0xb800, 0xf800,		WR_1|RD_3, 		0,		I3,	0,	0 },
+{"madh",    "x,y",	0xf800, 0xf81f,		RD_1|RD_2|WR_HI|WR_LO,	0,		RLX1,	0,	0 },
+{"madl",    "x,y",	0xf802, 0xf81f,		RD_1|RD_2|WR_HI|WR_LO,	0,		RLX1,	0,	0 },
+{"mazh",    "x,y",	0xf804, 0xf81f,		RD_1|RD_2|WR_HI|WR_LO,	0,		RLX1,	0,	0 },
+{"mazl",    "x,y",	0xf806, 0xf81f,		RD_1|RD_2|WR_HI|WR_LO,	0,		RLX1,	0,	0 },
 {"mfhi",    "x",	0xe810, 0xf8ff,		WR_1|RD_HI,		0,		I1,	0,	0 },
 {"mflo",    "x",	0xe812, 0xf8ff,		WR_1|RD_LO,		0,		I1,	0,	0 },
 {"move",    "y,X",	0x6700, 0xff00,		WR_1|RD_2, 		0,		I1,	0,	0 },
 {"move",    "Y,Z",	0x6500, 0xff00,		WR_1|RD_2,		0,		I1,	0,	0 },
+{"msbh",    "x,y",	0xf810, 0xf81f,		RD_1|RD_2|WR_HI|WR_LO,	0,		RLX1,	0,	0 },
+{"msbl",    "x,y",	0xf812, 0xf81f,		RD_1|RD_2|WR_HI|WR_LO,	0,		RLX1,	0,	0 },
+{"mszh",    "x,y",	0xf814, 0xf81f,		RD_1|RD_2|WR_HI|WR_LO,	0,		RLX1,	0,	0 },
+{"mszl",    "x,y",	0xf816, 0xf81f,		RD_1|RD_2|WR_HI|WR_LO,	0,		RLX1,	0,	0 },
 {"mul",     "z,v,y",	0, (int) M_MUL, 	INSN_MACRO,		0,		I1,	0,	0 },
 {"mult",    "x,y",	0xe818, 0xf81f,		RD_1|RD_2|WR_HI|WR_LO,	0,		I1,	0,	0 },
 {"multu",   "x,y",	0xe819, 0xf81f,		RD_1|RD_2|WR_HI|WR_LO,	0,		I1,	0,	0 },
--- binutils-2.24.orig/opcodes/mips-dis.c
+++ binutils-2.24/opcodes/mips-dis.c
@@ -75,6 +75,27 @@ static const char * const mips_gpr_names
   "t8",   "t9",   "k0",   "k1",   "gp",   "sp",   "s8",   "ra"
 };
 
+static const char *const mips_accumulator_names_alias[16] =
+{
+  "reserve", "m0l", "m0h", "m0", "reserve", "m1l", "m1h", "m1",
+  "reserve", "m2l", "m2h", "m2", "reserve", "m3l", "m3h", "m3"
+};
+
+/* extend to from 14 to 32 to prevent
+ * undefined pattern from crashing objdump
+ */
+static const char *const mips_cplxc0_names_alias[32] =
+{
+  "estatus",  "ecause",   "intvec",   "cvstag",
+  "bpctl", "wmpctl", "wmpstatus", "wmpvaddr",
+  "tlptr", "reserved", "reserved", "reserved",
+  "reserved", "reserved", "reserved", "reserved",
+  "reserved", "reserved", "reserved", "wmpextramask",
+  "reserved", "reserved", "reserved", "reserved",
+  "reserved", "reserved", "reserved", "reserved",
+  "reserved", "reserved", "reserved", "reserved"
+};
+
 static const char * const mips_fpr_names_numeric[32] =
 {
   "$f0",  "$f1",  "$f2",  "$f3",  "$f4",  "$f5",  "$f6",  "$f7",
@@ -550,6 +571,20 @@ const struct mips_arch_choice mips_arch_
     mips_cp0sel_names_xlr, ARRAY_SIZE (mips_cp0sel_names_xlr),
     mips_hwr_names_numeric },
 
+  /* Lexra processors */
+  { "4180",	1, bfd_mach_mips4180, CPU_LX4180, ISA_MIPS1, 0,
+    mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric},
+  { "4181",	1, bfd_mach_mips4181, CPU_RLX4181, ISA_MIPS1, 0,
+    mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric},
+  { "4281",	1, bfd_mach_mips4281, CPU_RLX4281, ISA_MIPS1, 0,
+    mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric},
+  { "5181", 	1, bfd_mach_mips5181, CPU_RLX5181, ISA_MIPS1, 0,
+    mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric},
+  { "5280", 	1, bfd_mach_mips5280, CPU_LX5280, ISA_MIPS1, 0,
+    mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric},
+  { "5281", 	1, bfd_mach_mips5281, CPU_RLX5281, ISA_MIPS1, 0,
+    mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric},
+
   /* This entry, mips16, is here only for ISA/processor selection; do
      not print its name.  */
   { "",		1, bfd_mach_mips16, CPU_MIPS16, ISA_MIPS3, 0,
@@ -929,6 +964,28 @@ print_reg (struct disassemble_info *info
     case OP_REG_R5900_ACC:
       info->fprintf_func (info->stream, "$ACC");
       break;
+
+    case OP_REG_LX_EVEN_REG:
+      info->fprintf_func (info->stream, "%s", mips_gpr_names[regno & 0xfe]);
+      break;
+
+    case OP_REG_LX_COPRO:
+      info->fprintf_func (info->stream, "$%d", regno);
+      break;
+
+    case OP_REG_LX_DST_REG_1:
+    case OP_REG_LX_DST_REG_2:
+    case OP_REG_LX_DST_REG_3:
+      if (regno >= 14 || regno < 0)
+        info->fprintf_func (info->stream, "$%d", regno);
+      else
+        info->fprintf_func (info->stream, "%s",
+                            mips_accumulator_names_alias[regno]);
+      break;
+
+    case OP_REG_LX_DST_REG_4:
+      info->fprintf_func (info->stream, "%s", mips_cplxc0_names_alias[regno]);
+      break;
     }
 }
 
@@ -990,6 +1047,7 @@ print_insn_arg (struct disassemble_info
   switch (operand->type)
     {
     case OP_INT:
+    case OP_INT_LX:
       {
 	const struct mips_int_operand *int_op;
 
--- binutils-2.24.orig/opcodes/mips-formats.h
+++ binutils-2.24/opcodes/mips-formats.h
@@ -35,6 +35,14 @@
 #define HINT(SIZE, LSB) \
   INT_ADJ(SIZE, LSB, (1 << (SIZE)) - 1, 0, TRUE)
 
+#define INT_LX(SIZE, LSB) \
+  { \
+    static const struct mips_int_operand op = { \
+      { OP_INT_LX, SIZE, LSB }, 0x3FF, 0, 3, FALSE \
+    }; \
+    return &op.root; \
+  }
+
 #define BIT(SIZE, LSB, BIAS) \
   { \
     static const struct mips_int_operand op = { \
--- binutils-2.24.orig/opcodes/mips-opc.c
+++ binutils-2.24/opcodes/mips-opc.c
@@ -93,6 +93,63 @@ decode_mips_operand (const char *p)
 	}
       break;
 
+    /* 2006-01-04 tonywu: merged from 2.14 to 2.16 */
+    case '#':
+      switch (p[1])
+        {
+          /* dbb: new instructions support */
+        case '`': REG (5, 16, LX_EVEN_REG);
+        case '~': INT_LX (8, 8);
+        case '#': INT_ADJ (4, 7, 8, 0, FALSE);
+        case '@': INT_ADJ (11, 6, 0x1fff, 3, FALSE);
+        case '=': INT_ADJ (10, 6, 0x0fff, 3, FALSE);
+          /* dbb: new instructions support */
+          /* 2008-07-08 tonywu: add for taroko processor */
+        case 'H': REG (6, 0, LX_COPRO);
+        case 'I': REG (5, 6, LX_COPRO);
+        case 'd':
+        case 's':
+        case 't':
+          {
+          switch (p[1])
+            {
+            case 'd':
+              switch (p[2])
+              {
+              case '1': REG(5, 11, LX_DST_REG_1);
+              case '2': REG(5, 11, LX_DST_REG_2);
+              case '3': REG(5, 11, LX_DST_REG_3);
+              case '4': REG(5, 11, LX_DST_REG_4);
+              }
+              break;
+
+            case 's':
+              switch (p[2])
+                {
+                case '1': REG(5, 21, LX_DST_REG_1);
+                case '2': REG(5, 21, LX_DST_REG_2);
+                case '3': REG(5, 21, LX_DST_REG_3);
+                case '4': REG(5, 21, LX_DST_REG_4);
+                }
+              break;
+
+            case 't':
+              switch (p[2])
+                {
+                case '1': REG(5, 16, LX_DST_REG_1);
+                case '2': REG(5, 16, LX_DST_REG_2);
+                case '3': REG(5, 16, LX_DST_REG_3);
+                case '4': REG(5, 16, LX_DST_REG_4);
+                }
+              break;
+            }
+          break;
+          }
+        case 'u': REG (5, 11, GP);
+        case 'k': REG (5, 11, GP);
+        }
+      break;
+
     case '<': BIT (5, 6, 0);			/* (0 .. 31) */
     case '>': BIT (5, 6, 32);			/* (32 .. 63) */
     case '%': UINT (3, 21);
@@ -332,6 +389,18 @@ decode_mips_operand (const char *p)
 /* TLB invalidate instruction support.  */
 #define TLBINV	ASE_EVA
 
+/* Lexra instructions */
+#define RLX0 INSN_4180
+#define RLX1 INSN_5280
+#define RLX2 (INSN_4181 | INSN_5181)
+#define RLX3 (INSN_4281 | INSN_5281)
+
+#define RLXA (RLX0 | RLX1 | RLX2 | RLX3)
+#define RLXB (RLX1 | RLX2 | RLX3)
+
+#define RAD1 (INSN_5181 | INSN_5280 | INSN_5281)
+#define RAD2 (INSN_5281)
+
 /* The order of overloaded instructions matters.  Label arguments and
    register arguments look the same. Instructions that can have either
    for arguments must apear in the correct order in this table for the
@@ -355,7 +424,7 @@ const struct mips_opcode mips_builtin_op
 {"pref",		"k,A(b)",	0,    (int) M_PREF_AB,	INSN_MACRO,		0,		I4_32|G3,	0,	0 },
 {"prefx",		"h,t(b)",	0x4c00000f, 0xfc0007ff, RD_2|RD_3|FP_S,		0,		I4_33,		0,	0 },
 {"nop",			"",		0x00000000, 0xffffffff, 0,              	INSN2_ALIAS,	I1,		0,	0 }, /* sll */
-{"ssnop",		"",		0x00000040, 0xffffffff, 0,              	INSN2_ALIAS,	I1,		0,	0 }, /* sll */
+{"ssnop",		"",		0x00000040, 0xffffffff, 0,              	INSN2_ALIAS,	I1|RLX3,	0,	0 }, /* sll */
 {"ehb",			"",		0x000000c0, 0xffffffff, 0,              	INSN2_ALIAS,	I1,		0,	0 }, /* sll */
 {"li",			"t,j",		0x24000000, 0xffe00000, WR_1,			INSN2_ALIAS,	I1,		0,	0 }, /* addiu */
 {"li",			"t,i",		0x34000000, 0xffe00000, WR_1,			INSN2_ALIAS,	I1,		0,	0 }, /* ori */
@@ -862,14 +931,16 @@ const struct mips_opcode mips_builtin_op
 {"flushd",		"",		0xbc020000, 0xffffffff, 0, 			0,		L1,		0,	0 },
 {"flushid",		"",		0xbc030000, 0xffffffff, 0, 			0,		L1,		0,	0 },
 {"wb",			"o(b)",		0xbc040000, 0xfc1f0000, RD_2|SM,		0,		L1,		0,	0 },
-{"cache",		"k,o(b)",	0xbc000000, 0xfc000000, RD_3,           	0,		I3_32|T3,	0,	0},
+{"cache",		"k,o(b)",	0xbc000000, 0xfc000000, RD_3,           	0,		I3_32|T3|RLXB,	0,	0},
 {"cache",		"k,A(b)",	0,    (int) M_CACHE_AB, INSN_MACRO,		0,		I3_32|T3,	0,	0},
 {"ceil.l.d",		"D,S",		0x4620000a, 0xffff003f, WR_1|RD_2|FP_D,		0,		I3_33,		0,	0 },
 {"ceil.l.s",		"D,S",		0x4600000a, 0xffff003f, WR_1|RD_2|FP_S|FP_D,	0,		I3_33,		0,	0 },
 {"ceil.w.d",		"D,S",		0x4620000e, 0xffff003f, WR_1|RD_2|FP_S|FP_D,	0,		I2,		0,	SF },
 {"ceil.w.s",		"D,S",		0x4600000e, 0xffff003f, WR_1|RD_2|FP_S,		0,		I2,		0,	EE },
 {"cfc0",		"t,G",		0x40400000, 0xffe007ff,	WR_1|RD_C0|LCD,		0,		I1,		0,	IOCT|IOCTP|IOCT2 },
+{"cfc0",		"t,G,#H",	0x40400000, 0xffe007c0, WR_1|RD_C0|LCD, 	0, 		RLX3,		0,	0 },
 {"cfc1",		"t,G",		0x44400000, 0xffe007ff,	WR_1|RD_C1|LCD|FP_S,	0,		I1,		0,	0 },
+{"cfc1",		"t,G,#H",	0x44400000, 0xffe007c0, WR_1|RD_C1|LCD|FP_S, 	0,  		RLX3,		0,	0 },
 {"cfc1",		"t,S",		0x44400000, 0xffe007ff,	WR_1|RD_C1|LCD|FP_S,	0,		I1,		0,	0 },
 /* cfc2 is at the bottom of the table.  */
 /* cfc3 is at the bottom of the table.  */
@@ -882,7 +953,9 @@ const struct mips_opcode mips_builtin_op
 {"clo",			"U,s",		0x70000021, 0xfc0007ff, WR_1|RD_2, 	0,		I32|N55,	0,	0 },
 {"clz",			"U,s",		0x70000020, 0xfc0007ff, WR_1|RD_2, 	0,		I32|N55,	0,	0 },
 {"ctc0",		"t,G",		0x40c00000, 0xffe007ff,	RD_1|WR_CC|COD,		0,		I1,		0,	IOCT|IOCTP|IOCT2 },
+{"ctc0",		"t,G,#H",	0x40c00000, 0xffe007c0, RD_1|WR_CC|COD, 	0, 		RLX3,		0,	0 },
 {"ctc1",		"t,G",		0x44c00000, 0xffe007ff,	RD_1|WR_CC|COD|FP_S,	0,		I1,		0,	0 },
+{"ctc1",		"t,G,#H",	0x44c00000, 0xffe007c0, RD_1|WR_CC|COD|FP_S, 	0,		RLX3,		0,	0 },
 {"ctc1",		"t,S",		0x44c00000, 0xffe007ff,	RD_1|WR_CC|COD|FP_S,	0,		I1,		0,	0 },
 /* ctc2 is at the bottom of the table.  */
 /* ctc3 is at the bottom of the table.  */
@@ -920,7 +993,7 @@ const struct mips_opcode mips_builtin_op
 /* dctr and dctw are used on the r5000.  */
 {"dctr",		"o(b)",	 	0xbc050000, 0xfc1f0000, RD_2,			0,		I3,		0,	0 },
 {"dctw",		"o(b)",		0xbc090000, 0xfc1f0000, RD_2,			0,		I3,		0,	0 },
-{"deret",		"",		0x4200001f, 0xffffffff, NODS, 			0,		I32|G2,		0,	0 },
+{"deret",		"",		0x4200001f, 0xffffffff, NODS, 			0,		I32|G2|RLXA,	0,	0 },
 {"dext",		"t,r,+A,+H",	0x7c000003, 0xfc00003f, WR_1|RD_2,    		0,		I65,		0,	0 },
 {"dext",		"t,r,+A,+G",	0x7c000001, 0xfc00003f, WR_1|RD_2,    		0,		I65,		0,	0 }, /* dextm */
 {"dext",		"t,r,+E,+H",	0x7c000002, 0xfc00003f, WR_1|RD_2,    		0,		I65,		0,	0 }, /* dextu */
@@ -1161,8 +1234,8 @@ const struct mips_opcode mips_builtin_op
 {"li.d",		"T,L",		0,    (int) M_LI_DD,	INSN_MACRO,		INSN2_M_FP_D,	I1,		0,	SF },
 {"li.s",		"t,f",		0,    (int) M_LI_S,	INSN_MACRO,		INSN2_M_FP_S,	I1,		0,	0 },
 {"li.s",		"T,l",		0,    (int) M_LI_SS,	INSN_MACRO,		INSN2_M_FP_S,	I1,		0,	0 },
-{"ll",			"t,o(b)",	0xc0000000, 0xfc000000, WR_1|RD_3|LDD,		0,		I2,		0,	EE },
-{"ll",			"t,A(b)",	0,    (int) M_LL_AB,	INSN_MACRO,		0,		I2,		0,	EE },
+{"ll",			"t,o(b)",	0xc0000000, 0xfc000000, WR_1|RD_3|LDD,		0,		I2|RLX2|RLX3,	0,	EE },
+{"ll",			"t,A(b)",	0,    (int) M_LL_AB,	INSN_MACRO,		0,		I2|RLX2|RLX3,	0,	EE },
 {"lld",			"t,o(b)",	0xd0000000, 0xfc000000, WR_1|RD_3|LDD,		0,		I3,		0,	EE },
 {"lld",			"t,A(b)",	0,    (int) M_LLD_AB,	INSN_MACRO,		0,		I3,		0,	EE },
 {"lq",			"t,o(b)",	0x78000000, 0xfc000000, WR_1|RD_3,		0,		MMI,		0,	0 },
@@ -1210,8 +1283,8 @@ const struct mips_opcode mips_builtin_op
 {"maccu",		"d,s,t",	0x00000068, 0xfc0007ff,	WR_1|RD_2|RD_3|WR_HILO,	     0,		N412,		0,	0 },
 {"maccu",		"d,s,t",	0x00000159, 0xfc0007ff, WR_1|RD_2|RD_3|WR_HILO,	     0,		N5,		0,	0 },
 {"maccus",		"d,s,t",	0x00000468, 0xfc0007ff,	WR_1|RD_2|RD_3|WR_HILO,	     0,		N412,		0,	0 },
-{"mad",			"s,t",		0x70000000, 0xfc00ffff, RD_1|RD_2|MOD_HILO,	     0,		P3,		0,	0 },
-{"madu",		"s,t",		0x70000001, 0xfc00ffff, RD_1|RD_2|MOD_HILO,	     0,		P3,		0,	0 },
+{"mad",			"s,t",		0x70000000, 0xfc00ffff, RD_1|RD_2|MOD_HILO,	     0,		P3|RLXA,	0,	0 },
+{"madu",		"s,t",		0x70000001, 0xfc00ffff, RD_1|RD_2|MOD_HILO,	     0,		P3|RLXA,	0,	0 },
 {"madd.d",		"D,R,S,T",	0x4c000021, 0xfc00003f, WR_1|RD_2|RD_3|RD_4|FP_D,    0,		I4_33,		0,	0 },
 {"madd.d",		"D,S,T",	0x46200018, 0xffe0003f,	WR_1|RD_2|RD_3|FP_D,	     0,		IL2E,		0,	0 },
 {"madd.d",		"D,S,T",	0x72200018, 0xffe0003f,	WR_1|RD_2|RD_3|FP_D,	     0,		IL2F,		0,	0 },
@@ -1270,11 +1343,13 @@ const struct mips_opcode mips_builtin_op
 {"mftlo",		"d,*",		0x41000021, 0xfff307ff, WR_1|RD_a|TRAP,		0,		0,		MT32,	0 },
 {"mftr",		"d,t,!,H,$",	0x41000000, 0xffe007c8, WR_1|TRAP,		0,		0,		MT32,	0 },
 {"mfc0",		"t,G",		0x40000000, 0xffe007ff,	WR_1|RD_C0|LCD,		0,		I1,		0,	0 },
+{"mfc0",		"t,G,#H",	0x40000000, 0xffe007c0, WR_1|RD_C0|LCD, 	0, 		RLX3,		0,	0 },
 {"mfc0",		"t,G,H",	0x40000000, 0xffe007f8,	WR_1|RD_C0|LCD,		0,		I32,		0,	0 },
 {"mfgc0",		"t,G",		0x40600000, 0xffe007ff,	WR_1|RD_C0|LCD,		0,		0,		IVIRT,	0 },
 {"mfgc0",		"t,G,H",	0x40600000, 0xffe007f8, WR_1|RD_C0|LCD, 	0,		0,		IVIRT,	0 },
 {"mfc1",		"t,S",		0x44000000, 0xffe007ff,	WR_1|RD_2|LCD|FP_S,	0,		I1,		0,	0 },
 {"mfc1",		"t,G",		0x44000000, 0xffe007ff,	WR_1|RD_2|LCD|FP_S,	0,		I1,		0,	0 },
+{"mfc1",		"t,G,#H",	0x44000000, 0xffe007c0,	WR_1|RD_2|LCD|FP_S, 	0,		RLX3,		0,	0 },
 {"mfhc1",		"t,S",		0x44600000, 0xffe007ff,	WR_1|RD_2|LCD|FP_D,	0,		I33,		0,	0 },
 {"mfhc1",		"t,G",		0x44600000, 0xffe007ff,	WR_1|RD_2|LCD|FP_D,	0,		I33,		0,	0 },
 /* mfc2 is at the bottom of the table.  */
@@ -1304,7 +1379,7 @@ const struct mips_opcode mips_builtin_op
 {"movf.l",		"X,Y,N",	0x46a00011, 0xffe3003f, WR_1|RD_2|RD_CC|FP_D,	0,		SB1,		MX,	0 },
 {"movf.s",		"D,S,N",	0x46000011, 0xffe3003f, WR_1|RD_2|RD_CC|FP_S,   0,		I4_32,		0,	0 },
 {"movf.ps",		"D,S,N",	0x46c00011, 0xffe3003f, WR_1|RD_2|RD_CC|FP_D,	0,		I5_33,		0,	0 },
-{"movn",		"d,v,t",	0x0000000b, 0xfc0007ff, WR_1|RD_2|RD_3, 	0,		I4_32|IL2E|IL2F|EE, 0,	0 },
+{"movn",		"d,v,t",	0x0000000b, 0xfc0007ff, WR_1|RD_2|RD_3, 	0,		I4_32|IL2E|IL2F|EE|RLXB,	0,	0 },
 {"movnz",		"d,v,t",	0x0000000b, 0xfc0007ff, WR_1|RD_2|RD_3, 	0,		IL2E|IL2F|IL3A,	0,	0 },
 {"ffc",			"d,v",		0x0000000b, 0xfc1f07ff,	WR_1|RD_2,		0,		L1,		0,	0 },
 {"movn.d",		"D,S,t",	0x46200013, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,		I4_32,		0,	0 },
@@ -1318,7 +1393,7 @@ const struct mips_opcode mips_builtin_op
 {"movt.l",		"X,Y,N",	0x46a10011, 0xffe3003f, WR_1|RD_2|RD_CC|FP_D,   0,		SB1,		MX,	0 },
 {"movt.s",		"D,S,N",	0x46010011, 0xffe3003f, WR_1|RD_2|RD_CC|FP_S,   0,		I4_32,		0,	0 },
 {"movt.ps",		"D,S,N",	0x46c10011, 0xffe3003f, WR_1|RD_2|RD_CC|FP_D,	0,		I5_33,		0,	0 },
-{"movz",		"d,v,t",	0x0000000a, 0xfc0007ff, WR_1|RD_2|RD_3, 	0,		I4_32|IL2E|IL2F|EE, 0,	0 },
+{"movz",		"d,v,t",	0x0000000a, 0xfc0007ff, WR_1|RD_2|RD_3, 	0,		I4_32|IL2E|IL2F|EE|RLXB,	0,	0 },
 {"ffs",			"d,v",		0x0000000a, 0xfc1f07ff,	WR_1|RD_2,		0,		L1,		0,	0 },
 {"movz.d",		"D,S,t",	0x46200012, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,		I4_32,		0,	0 },
 {"movz.l",		"D,S,t",	0x46a00012, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,		SB1,		MX,	0 },
@@ -1347,11 +1422,11 @@ const struct mips_opcode mips_builtin_op
 {"msub.ps",		"D,S,T",	0x45600019, 0xffe0003f,	WR_1|RD_2|RD_3|FP_D,	0,		IL2E,		0,	0 },
 {"msub.ps",		"D,S,T",	0x72c00019, 0xffe0003f,	WR_1|RD_2|RD_3|FP_D,	0,		IL2F,		0,	0 },
 {"msub",		"s,t",		0x0000001e, 0xfc00ffff, RD_1|RD_2|WR_HILO,	0,		L1,		0,	0 },
-{"msub",		"s,t",		0x70000004, 0xfc00ffff, RD_1|RD_2|MOD_HILO,     0,		I32|N55,	0,	0 },
+{"msub",		"s,t",		0x70000004, 0xfc00ffff, RD_1|RD_2|MOD_HILO,     0,		I32|N55|RLXA,	0,	0 },
 {"msub",		"7,s,t",	0x70000004, 0xfc00e7ff, RD_2|RD_3|MOD_a,        0,              0,		D32,	0 },
 {"msuba.s",		"S,T",		0x4600001f, 0xffe007ff,	RD_1|RD_2|FP_S,		0,		EE,		0,	0 },
 {"msubu",		"s,t",		0x0000001f, 0xfc00ffff, RD_1|RD_2|WR_HILO,	0,		L1,		0,	0 },
-{"msubu",		"s,t",		0x70000005, 0xfc00ffff, RD_1|RD_2|MOD_HILO,     0,		I32|N55,	0,	0 },
+{"msubu",		"s,t",		0x70000005, 0xfc00ffff, RD_1|RD_2|MOD_HILO,     0,		I32|N55|RLXA,	0,	0 },
 {"msubu",		"7,s,t",	0x70000005, 0xfc00e7ff, RD_2|RD_3|MOD_a,        0,              0,		D32,	0 },
 {"mtbpc",		"t",		0x4080c000, 0xffe0ffff,	RD_1|WR_C0|COD,		0,		EE,		0,	0 },
 {"mtdab",		"t",		0x4080c004, 0xffe0ffff,	RD_1|WR_C0|COD,		0,		EE,		0,	0 },
@@ -1363,10 +1438,12 @@ const struct mips_opcode mips_builtin_op
 {"mtpc",		"t,P",		0x4080c801, 0xffe0ffc1,	RD_1|WR_C0|COD,		0,		M1|N5|EE,	0,	0 },
 {"mtps",		"t,P",		0x4080c800, 0xffe0ffc1,	RD_1|WR_C0|COD,		0,		M1|N5|EE,	0,	0 },
 {"mtc0",		"t,G",		0x40800000, 0xffe007ff,	RD_1|WR_C0|WR_CC|COD,	0,		I1,		0,	0 },
+{"mtc0",		"t,G,#H",	0x40800000, 0xffe007c0, RD_1|WR_C0|WR_CC|COD,	0,		RLX3,		0,	0 },
 {"mtc0",		"t,G,H",	0x40800000, 0xffe007f8,	RD_1|WR_C0|WR_CC|COD,	0,		I32,		0,	0 },
 {"mtgc0",		"t,G",		0x40600200, 0xffe007ff,	RD_1|WR_C0|WR_CC|COD,	0,		0,		IVIRT,	0 },
 {"mtgc0",		"t,G,H",	0x40600200, 0xffe007f8, RD_1|WR_C0|WR_CC|COD,   0,		0,		IVIRT,	0 },
 {"mtc1",		"t,S",		0x44800000, 0xffe007ff,	RD_1|WR_2|COD|FP_S,	0,		I1,		0,	0 },
+{"mtc1",		"t,G,#H",	0x44800000, 0xffe007c0, RD_1|WR_2|COD|FP_S,	0,		RLX3,		0,	0 },
 {"mtc1",		"t,G",		0x44800000, 0xffe007ff,	RD_1|WR_2|COD|FP_S,	0,		I1,		0,	0 },
 {"mthc1",		"t,S",		0x44e00000, 0xffe007ff,	RD_1|WR_2|COD|FP_D,	0,		I33,		0,	0 },
 {"mthc1",		"t,G",		0x44e00000, 0xffe007ff,	RD_1|WR_2|COD|FP_D,	0,		I33,		0,	0 },
@@ -1664,8 +1741,8 @@ const struct mips_opcode mips_builtin_op
 {"saad",		"t,(b)",	0x70000019, 0xfc00ffff,	RD_1|RD_2|SM,		0,		IOCTP,		0,	0 },
 {"sb",			"t,o(b)",	0xa0000000, 0xfc000000,	RD_1|RD_3|SM,		0,		I1,		0,	0 },
 {"sb",			"t,A(b)",	0,    (int) M_SB_AB,	INSN_MACRO,		0,		I1,		0,	0 },
-{"sc",			"t,o(b)",	0xe0000000, 0xfc000000, MOD_1|RD_3|SM,		0,		I2,		0,	EE },
-{"sc",			"t,A(b)",	0,    (int) M_SC_AB,	INSN_MACRO,		0,		I2,		0,	EE },
+{"sc",			"t,o(b)",	0xe0000000, 0xfc000000, MOD_1|RD_3|SM,		0,		I2|RLX2|RLX3,	0,	EE },
+{"sc",			"t,A(b)",	0,    (int) M_SC_AB,	INSN_MACRO,		0,		I2|RLX2|RLX3,	0,	EE },
 {"scd",			"t,o(b)",	0xf0000000, 0xfc000000, MOD_1|RD_3|SM,		0,		I3,		0,	EE },
 {"scd",			"t,A(b)",	0,    (int) M_SCD_AB,	INSN_MACRO,		0,		I3,		0,	EE },
 /* The macro has to be first to handle o32 correctly.  */
@@ -1674,8 +1751,8 @@ const struct mips_opcode mips_builtin_op
 {"sdbbp",		"",		0x0000000e, 0xffffffff,	TRAP,           	0,		G2,		0,	0 },
 {"sdbbp",		"c",		0x0000000e, 0xfc00ffff,	TRAP,			0,		G2,		0,	0 },
 {"sdbbp",		"c,q",		0x0000000e, 0xfc00003f,	TRAP,			0,		G2,		0,	0 },
-{"sdbbp",		"",		0x7000003f, 0xffffffff, TRAP,           	0,		I32,		0,	0 },
-{"sdbbp",		"B",		0x7000003f, 0xfc00003f, TRAP,           	0,		I32,		0,	0 },
+{"sdbbp",		"",		0x7000003f, 0xffffffff, TRAP,           	0,		I32|RLXA,	0,	0 },
+{"sdbbp",		"B",		0x7000003f, 0xfc00003f, TRAP,           	0,		I32|RLXA,	0,	0 },
 {"sdc1",		"T,o(b)",	0xf4000000, 0xfc000000, RD_1|RD_3|SM|FP_D,	0,		I2,		0,	SF },
 {"sdc1",		"E,o(b)",	0xf4000000, 0xfc000000, RD_1|RD_3|SM|FP_D,	0,		I2,		0,	SF },
 {"sdc1",		"T,A(b)",	0,    (int) M_SDC1_AB,	INSN_MACRO,		INSN2_M_FP_D,	I2,		0,	SF },
@@ -1835,7 +1912,8 @@ const struct mips_opcode mips_builtin_op
 {"sync_release",	"",		0x0000048f, 0xffffffff,	NODS,			0,		I33,		0,	0 },
 {"sync_rmb",		"",		0x000004cf, 0xffffffff,	NODS,			0,		I33,		0,	0 },
 {"sync_wmb",		"",		0x0000010f, 0xffffffff,	NODS,			0,		I33,		0,	0 },
-{"sync",		"",		0x0000000f, 0xffffffff,	NODS,			0,		I2|G1,		0,	0 },
+{"sync",		"",		0x0000000f, 0xffffffff,	NODS,			0,		I2|G1|RLX3,	0,	0 },
+{"sync",		"#I",		0x0000000f, 0xfffff83f, NODS,			0,		RLX3,		0,	0 },
 {"sync",		"1",		0x0000000f, 0xfffff83f,	NODS,			0,		I32,		0,	0 },
 {"sync.p",		"",		0x0000040f, 0xffffffff,	NODS,			0,		I2,		0,	0 },
 {"sync.l",		"",		0x0000000f, 0xffffffff,	NODS,			0,		I2,		0,	0 },
@@ -1932,26 +2010,32 @@ const struct mips_opcode mips_builtin_op
 {"udi0",		"s,t,+2",	0x70000010, 0xfc00003f,	UDI,			0,		I33,		0,	0 },
 {"udi0",		"s,+3",		0x70000010, 0xfc00003f,	UDI,			0,		I33,		0,	0 },
 {"udi0",		"+4",		0x70000010, 0xfc00003f,	UDI,			0,		I33,		0,	0 },
+{"udi0",		 "d,v,t",	0x00000038, 0xfc0007ff, UDI,			0,		RLXB,		0,	0 },
 {"udi1",		"s,t,d,+1",	0x70000011, 0xfc00003f,	UDI,			0,		I33,		0,	0 },
 {"udi1",		"s,t,+2",	0x70000011, 0xfc00003f,	UDI,			0,		I33,		0,	0 },
 {"udi1",		"s,+3",		0x70000011, 0xfc00003f,	UDI,			0,		I33,		0,	0 },
 {"udi1",		"+4",		0x70000011, 0xfc00003f,	UDI,			0,		I33,		0,	0 },
+{"udi1",		"d,v,t",	0x0000003a, 0xfc0007ff, UDI,			0,		RLXB,		0,	0 },
 {"udi2",		"s,t,d,+1",	0x70000012, 0xfc00003f,	UDI,			0,		I33,		0,	0 },
 {"udi2",		"s,t,+2",	0x70000012, 0xfc00003f,	UDI,			0,		I33,		0,	0 },
 {"udi2",		"s,+3",		0x70000012, 0xfc00003f,	UDI,			0,		I33,		0,	0 },
 {"udi2",		"+4",		0x70000012, 0xfc00003f,	UDI,			0,		I33,		0,	0 },
+{"udi2",		"d,v,t",	0x0000003b, 0xfc0007ff, UDI,			0,		RLXB,		0,	0 },
 {"udi3",		"s,t,d,+1",	0x70000013, 0xfc00003f,	UDI,			0,		I33,		0,	0 },
 {"udi3",		"s,t,+2",	0x70000013, 0xfc00003f,	UDI,			0,		I33,		0,	0 },
 {"udi3",		"s,+3",		0x70000013, 0xfc00003f,	UDI,			0,		I33,		0,	0 },
 {"udi3",		"+4",		0x70000013, 0xfc00003f,	UDI,			0,		I33,		0,	0 },
+{"udi3",		"d,v,t",	0x0000003c, 0xfc0007ff, UDI,			0,		RLXB,		0,	0 },
 {"udi4",		"s,t,d,+1",	0x70000014, 0xfc00003f,	UDI,			0,		I33,		0,	0 },
 {"udi4",		"s,t,+2",	0x70000014, 0xfc00003f,	UDI,			0,		I33,		0,	0 },
 {"udi4",		"s,+3",		0x70000014, 0xfc00003f,	UDI,			0,		I33,		0,	0 },
 {"udi4",		"+4",		0x70000014, 0xfc00003f,	UDI,			0,		I33,		0,	0 },
+{"udi4",		"d,v,t",	0x0000003e, 0xfc0007ff, UDI,			0,		RLXB,		0,	0 },
 {"udi5",		"s,t,d,+1",	0x70000015, 0xfc00003f,	UDI,			0,		I33,		0,	0 },
 {"udi5",		"s,t,+2",	0x70000015, 0xfc00003f,	UDI,			0,		I33,		0,	0 },
 {"udi5",		"s,+3",		0x70000015, 0xfc00003f,	UDI,			0,		I33,		0,	0 },
 {"udi5",		"+4",		0x70000015, 0xfc00003f,	UDI,			0,		I33,		0,	0 },
+{"udi5",		"d,v,t",	0x0000003f, 0xfc0007ff, UDI,			0,		RLXB,		0,	0 },
 {"udi6",		"s,t,d,+1",	0x70000016, 0xfc00003f,	UDI,			0,		I33,		0,	0 },
 {"udi6",		"s,t,+2",	0x70000016, 0xfc00003f,	UDI,			0,		I33,		0,	0 },
 {"udi6",		"s,+3",		0x70000016, 0xfc00003f,	UDI,			0,		I33,		0,	0 },
@@ -2004,10 +2088,12 @@ const struct mips_opcode mips_builtin_op
 {"bc2tl",		"p",		0x49030000, 0xffff0000,	RD_CC|CBL,		0,		I2|T3,		0,	IOCT|IOCTP|IOCT2 },
 {"bc2tl",		"N,p",		0x49030000, 0xffe30000,	RD_CC|CBL,		0,		I32,		0,	IOCT|IOCTP|IOCT2 },
 {"cfc2",		"t,G",		0x48400000, 0xffe007ff,	WR_1|RD_C2|LCD,		0,		I1,		0,	IOCT|IOCTP|IOCT2|EE },
+{"cfc2",		"t,G,#H",	0x48400000, 0xffe007c0, WR_1|RD_C2|LCD,		0,		RLX3,		0,	0 },
 {"cfc2",		"t,+9",		0x48400000, 0xffe007ff,	WR_1|RD_C2|LCD,		0,		EE,		0,	0 },
 {"cfc2.i",		"t,+9",		0x48400001, 0xffe007ff, WR_1|RD_C2|LCD,		0,		EE,		0,	0 },
 {"cfc2.ni",		"t,+9",		0x48400000, 0xffe007ff, WR_1|RD_C2|LCD,		0,		EE,		0,	0 },
 {"ctc2",		"t,G",		0x48c00000, 0xffe007ff,	RD_1|WR_CC|COD,		0,		I1,		0,	IOCT|IOCTP|IOCT2|EE },
+{"ctc2",		"t,G,#H",	0x48c00000, 0xffe007c0, RD_1|WR_CC|COD,		0,		RLX3,		0,	0 },
 {"ctc2",		"t,+9",		0x48c00000, 0xffe007ff,	RD_1|WR_CC|COD,		0,		EE,		0,	0 },
 {"ctc2.i",		"t,+9",		0x48c00001, 0xffe007ff, RD_1|WR_CC|COD,		0,		EE,		0,	0 },
 {"ctc2.ni",		"t,+9",		0x48c00000, 0xffe007ff, RD_1|WR_CC|COD,		0,		EE,		0,	0 },
@@ -2018,11 +2104,13 @@ const struct mips_opcode mips_builtin_op
 {"dmtc2",		"t,G",		0x48a00000, 0xffe007ff,	RD_1|WR_C2|WR_CC|COD,	0,		I3,		0,	IOCT|IOCTP|IOCT2|EE },
 {"dmtc2",		"t,G,H",	0x48a00000, 0xffe007f8,	RD_1|WR_C2|WR_CC|COD,	0,		I64,		0,	IOCT|IOCTP|IOCT2 },
 {"mfc2",		"t,G",		0x48000000, 0xffe007ff,	WR_1|RD_C2|LCD,		0,		I1,		0,	IOCT|IOCTP|IOCT2|EE },
+{"mfc2",		"t,G,#H",	0x48000000, 0xffe007c0, WR_1|RD_C2|LCD,		0,		RLX3,		0,	0 },
 {"mfc2",		"t,G,H",	0x48000000, 0xffe007f8,	WR_1|RD_C2|LCD,		0,		I32,		0,	IOCT|IOCTP|IOCT2 },
 {"mfhc2",		"t,G",		0x48600000, 0xffe007ff,	WR_1|RD_C2|LCD,		0,		I33,		0,	IOCT|IOCTP|IOCT2 },
 {"mfhc2",		"t,G,H",	0x48600000, 0xffe007f8,	WR_1|RD_C2|LCD,		0,		I33,		0,	IOCT|IOCTP|IOCT2 },
 {"mfhc2",		"t,i",		0x48600000, 0xffe00000,	WR_1|RD_C2|LCD,		0,		I33,		0,	IOCT|IOCTP|IOCT2 },
 {"mtc2",		"t,G",		0x48800000, 0xffe007ff,	RD_1|WR_C2|WR_CC|COD,	0,		I1,		0,	IOCT|IOCTP|IOCT2|EE },
+{"mtc2",		"t,G,#H",	0x48800000, 0xffe007c0, RD_1|WR_C2|WR_CC|COD,	0,		RLX3,		0,	0 },
 {"mtc2",		"t,G,H",	0x48800000, 0xffe007f8,	RD_1|WR_C2|WR_CC|COD,	0,		I32,		0,	IOCT|IOCTP|IOCT2 },
 {"mthc2",		"t,G",		0x48e00000, 0xffe007ff,	RD_1|WR_C2|WR_CC|COD,	0,		I33,		0,	IOCT|IOCTP|IOCT2 },
 {"mthc2",		"t,G,H",	0x48e00000, 0xffe007f8,	RD_1|WR_C2|WR_CC|COD,	0,		I33,		0,	IOCT|IOCTP|IOCT2 },
@@ -2040,12 +2128,16 @@ const struct mips_opcode mips_builtin_op
 {"bc3t",		"p",		0x4d010000, 0xffff0000,	RD_CC|CBD,		0,		I1,		0,	IOCT|IOCTP|IOCT2|EE },
 {"bc3tl",		"p",		0x4d030000, 0xffff0000,	RD_CC|CBL,		0,		I2|T3,		0,	IOCT|IOCTP|IOCT2|EE },
 {"cfc3",		"t,G",		0x4c400000, 0xffe007ff,	WR_1|RD_C3|LCD,		0,		I1,		0,	IOCT|IOCTP|IOCT2|EE },
+{"cfc3",		"t,G,#H",	0x4c400000, 0xffe007c0, WR_1|RD_C3|LCD,		0,		RLX3,		0,	0 },
 {"ctc3",		"t,G",		0x4cc00000, 0xffe007ff,	RD_1|WR_CC|COD,		0,		I1,		0,	IOCT|IOCTP|IOCT2|EE },
+{"ctc3",		"t,G,#H",	0x4cc00000, 0xffe007c0, RD_1|WR_CC|COD,		0,		RLX3,		0,	0 },
 {"dmfc3",		"t,G",		0x4c200000, 0xffe007ff,	WR_1|RD_C3|LCD,		0,		I3,		0,	IOCT|IOCTP|IOCT2|EE },
 {"dmtc3",		"t,G",		0x4ca00000, 0xffe007ff,	RD_1|WR_C3|WR_CC|COD,	0,		I3,		0,	IOCT|IOCTP|IOCT2|EE },
 {"mfc3",		"t,G",		0x4c000000, 0xffe007ff,	WR_1|RD_C3|LCD,		0,		I1,		0,	IOCT|IOCTP|IOCT2|EE },
+{"mfc3",		"t,G,#H",	0x4c000000, 0xffe007c0, WR_1|RD_C3|LCD,		0,		RLX3,		0,	0 },
 {"mfc3",		"t,G,H",	0x4c000000, 0xffe007f8,	WR_1|RD_C3|LCD,		0,		I32,		0,	IOCT|IOCTP|IOCT2|EE },
 {"mtc3",		"t,G",		0x4c800000, 0xffe007ff,	RD_1|WR_C3|WR_CC|COD,	0,		I1,		0,	IOCT|IOCTP|IOCT2|EE },
+{"mtc3",		"t,G,#H",	0x4c800000, 0xffe007c0, RD_1|WR_C3|WR_CC|COD,	0,		RLX3,		0,	0 },
 {"mtc3",		"t,G,H",	0x4c800000, 0xffe007f8,	RD_1|WR_C3|WR_CC|COD,	0,		I32,		0,	IOCT|IOCTP|IOCT2|EE },
 
   /* Conflicts with the 4650's "mul" instruction.  Nobody's using the
@@ -2071,6 +2163,7 @@ const struct mips_opcode mips_builtin_op
 {"addu_s.qb",		"d,s,t",	0x7c000110, 0xfc0007ff, WR_1|RD_2|RD_3,		0,		0,		D32,	0 },
 {"addwc",		"d,s,t",	0x7c000450, 0xfc0007ff, WR_1|RD_2|RD_3,		0,		0,		D32,	0 },
 {"bitrev",		"d,t",		0x7c0006d2, 0xffe007ff, WR_1|RD_2,		0,		0,		D32,	0 },
+{"bitrev",		"d,t,s", 	0x7c00000c, 0xFC0007FF, WR_1|RD_2|RD_3,		0,		RAD1,		0,	0 },
 {"bposge32",		"p",		0x041c0000, 0xffff0000, CBD,			0,		0,		D32,	0 },
 {"bposge64",		"p",		0x041d0000, 0xffff0000, CBD,			0,		0,		D64,	0 },
 {"cmp.eq.ph",		"s,t",		0x7c000211, 0xfc00ffff, RD_1|RD_2,		0,		0,		D32,	0 },
@@ -2555,6 +2648,175 @@ const struct mips_opcode mips_builtin_op
 {"cop3",		"C",		0,    (int) M_COP3,	INSN_MACRO,		0,		I1,		0,	IOCT|IOCTP|IOCT2 },
 /* RFE conflicts with the new Virt spec instruction tlbgp. */
 {"rfe",			"",		0x42000010, 0xffffffff,	0,			0,		I1|T3,		0,	0 },
+
+/* dbb: modified for supporting radiax instructions */
+/* 2006-01-19 tonywu: cleanup radiax instructions definition */
+/* 2008-07-12 tonywu: add taroko support */
+/* 2008-08-31 tonywu: add rad type */
+/*   d1: m0(3), m1(7), m2(11), m3(15) */
+/*   d2: m0l, m0h, m0 ~ m3l, m3h, m3 */
+/*   d3: m0l, m0h, ~ m3l, m3h */
+/*   d4: LXC0 */
+{"mta2",		"s,#d2",	0x7C00005D, 0xFC1F07ff, RD_1,			0,		RAD1,		0,	0 },
+{"mta2.g",		"s,#d2",	0x7C00015D, 0xFC1F07ff, RD_1,			0,		RAD1,		0,	0 },
+{"mfa",			"d,#t3",	0x7C00001C, 0xFFE007FF, WR_1,			0,		RAD1,		0,	0 },
+{"mfa",			"d,#t3,##",	0x7C00001C, 0xFFE0007F, WR_1,			0,		RAD1,		0,	0 },
+{"mfa2",		"d,#t1",	0x7C00005C, 0xFFE007FF, WR_1,			0,		RAD1,		0,	0 },
+{"mfa2",		"d,#t1,##",	0x7C00005C, 0xFFE0007F, WR_1,			0,		RAD1,		0,	0 },
+{"diva",		"#d1,s,t",	0x7C00001A, 0xFC0007FF, RD_2|RD_3,		0,		RAD1,		0,	0 },
+{"divau",		"#d1,s,t",	0x7C00021A, 0xFC0007FF, RD_2|RD_3,		0,		RAD1,		0,	0 },
+{"multa",		"#d1,s,t",	0x7C000112, 0xFC0007FF, RD_2|RD_3,		0,		RAD1,		0,	0 },
+{"multau",		"#d1,s,t",	0x7C000312, 0xFC0007FF, RD_2|RD_3,		0,		RAD1,		0,	0 },
+{"imulta",		"#d1,s,t",	0x7C000102, 0xFC0007FF, RD_2|RD_3,		0,		RAD2,		0,	0 },
+{"imultau",		"#d1,s,t",	0x7C000302, 0xFC0007FF, RD_2|RD_3,		0,		RAD2,		0,	0 },
+{"qmulta",		"#d1,s,t",	0x7C000502, 0xFC0007FF, RD_2|RD_3,		0,		RAD2,		0,	0 },
+{"multa2",		"#d2,s,t",	0x7C000152, 0xFC0007FF, RD_2|RD_3,		0,		RAD1,		0,	0 },
+{"imulta2",		"#d2,s,t",	0x7C000142, 0xFC0007FF, RD_2|RD_3,		0,		RAD2,		0,	0 },
+{"qmulta2",		"#d2,s,t",	0x7C000542, 0xFC0007FF, RD_2|RD_3,		0,		RAD2,		0,	0 },
+{"mulna2",		"#d2,s,t",	0x7C000153, 0xFC0007FF, RD_2|RD_3,		0,		RAD1,		0,	0 },
+{"imulna2",		"#d2,s,t",	0x7C000143, 0xFC0007FF, RD_2|RD_3,		0,		RAD2,		0,	0 },
+{"qmulna2",		"#d2,s,t",	0x7C000543, 0xFC0007FF, RD_2|RD_3,		0,		RAD2,		0,	0 },
+{"cmulta",		"#d1,s,t",	0x7C00001B, 0xFC0007FF, RD_2|RD_3,		0,		RAD1,		0,	0 },
+{"icmulta",		"#d1,s,t",	0x7C00011B, 0xFC0007FF, RD_2|RD_3,		0,		RAD2,		0,	0 },
+{"qcmulta",		"#d1,s,t",	0x7C00051B, 0xFC0007FF, RD_2|RD_3,		0,		RAD2,		0,	0 },
+{"madda",		"#d1,s,t",	0x7C000012, 0xFC0007FF, RD_2|RD_3,		0,		RAD1,		0,	0 },
+{"maddau",		"#d1,s,t",	0x7C000212, 0xFC0007FF, RD_2|RD_3,		0,		RAD1,		0,	0 },
+{"imadda",		"#d1,s,t",	0x7C000002, 0xFC0007FF, RD_2|RD_3,		0,		RAD2,		0,	0 },
+{"imaddau",		"#d1,s,t",	0x7C000202, 0xFC0007FF, RD_2|RD_3,		0,		RAD2,		0,	0 },
+{"qmadda",		"#d1,s,t",	0x7C000402, 0xFC0007FF, RD_2|RD_3,		0,		RAD2,		0,	0 },
+{"madda2",		"#d2,s,t",	0x7C000052, 0xFC0007FF, RD_2|RD_3,		0,		RAD1,		0,	0 },
+{"imadda2",		"#d2,s,t",	0x7C000042, 0xFC0007FF, RD_2|RD_3,		0,		RAD2,		0,	0 },
+{"qmadda2",		"#d2,s,t",	0x7C000442, 0xFC0007FF, RD_2|RD_3,		0,		RAD2,		0,	0 },
+{"madda2.s",		"#d2,s,t",	0x7C0000D2, 0xFC0007FF, RD_2|RD_3,		0,		RAD1,		0,	0 },
+{"imadda2.s32",		"#d2,s,t",	0x7C0000C2, 0xFC0007FF, RD_2|RD_3,		0,		RAD2,		0,	0 },
+{"qmadda2.s32",		"#d2,s,t",	0x7C0004C2, 0xFC0007FF, RD_2|RD_3,		0,		RAD2,		0,	0 },
+{"imadda2.s40",		"#d2,s,t",	0x7C0001C2, 0xFC0007FF, RD_2|RD_3,		0,		RAD2,		0,	0 },
+{"qmadda2.s40",		"#d2,s,t",	0x7C0005C2, 0xFC0007FF, RD_2|RD_3,		0,		RAD2,		0,	0 },
+{"msuba",		"#d1,s,t",	0x7C000013, 0xFC0007FF, RD_2|RD_3,		0,		RAD1,		0,	0 },
+{"msubau",		"#d1,s,t",	0x7C000213, 0xFC0007FF, RD_2|RD_3,		0,		RAD1,		0,	0 },
+{"imsuba",		"#d1,s,t",	0x7C000003, 0xFC0007FF, RD_2|RD_3,		0,		RAD2,		0,	0 },
+{"imsubau",		"#d1,s,t",	0x7C000203, 0xFC0007FF, RD_2|RD_3,		0,		RAD2,		0,	0 },
+{"qmsuba",		"#d1,s,t",	0x7C000403, 0xFC0007FF, RD_2|RD_3,		0,		RAD2,		0,	0 },
+{"msuba2",		"#d2,s,t",	0x7C000053, 0xFC0007FF, RD_2|RD_3,		0,		RAD1,		0,	0 },
+{"imsuba2",		"#d2,s,t",	0x7C000043, 0xFC0007FF, RD_2|RD_3,		0,		RAD2,		0,	0 },
+{"qmsuba2",		"#d2,s,t",	0x7C000443, 0xFC0007FF, RD_2|RD_3,		0,		RAD2,		0,	0 },
+{"msuba2.s",		"#d2,s,t",	0x7C0000D3, 0xFC0007FF, RD_2|RD_3,		0,		RAD1,		0,	0 },
+{"imsuba2.s32",		"#d2,s,t",	0x7C0000C3, 0xFC0007FF, RD_2|RD_3,		0,		RAD2,		0,	0 },
+{"qmsuba2.s32",		"#d2,s,t",	0x7C0004C3, 0xFC0007FF, RD_2|RD_3,		0,		RAD2,		0,	0 },
+{"imsuba2.s40",		"#d2,s,t",	0x7C0001C3, 0xFC0007FF, RD_2|RD_3,		0,		RAD2,		0,	0 },
+{"qmsuba2.s40",		"#d2,s,t",	0x7C0005C3, 0xFC0007FF, RD_2|RD_3,		0,		RAD2,		0,	0 },
+{"addma",		"#d3,#s3,#t3",	0x7C00001E, 0xFC0007FF, 0,			0,		RAD1,		0,	0 },
+{"addma.s",		"#d3,#s3,#t3",	0x7C00009E, 0xFC0007FF, 0,			0,		RAD1,		0,	0 },
+{"addma.s32",		"#d3,#s3,#t3",	0x7C00041E, 0xFC0007FF, 0,			0,		RAD2,		0,	0 },
+{"addma.s40",		"#d3,#s3,#t3",	0x7C00049E, 0xFC0007FF, 0,			0,		RAD2,		0,	0 },
+{"subma",		"#d3,#s3,#t3",	0x7C00001F, 0xFC0007FF, 0,			0,		RAD1,		0,	0 },
+{"subma.s",		"#d3,#s3,#t3",	0x7C00009F, 0xFC0007FF, 0,			0,		RAD1,		0,	0 },
+{"subma.s32",		"#d3,#s3,#t3",	0x7C00041F, 0xFC0007FF, 0,			0,		RAD2,		0,	0 },
+{"subma.s40",		"#d3,#s3,#t3",	0x7C00049F, 0xFC0007FF, 0,			0,		RAD2,		0,	0 },
+{"rnda2",		"#t2",		0x7C000056, 0xFFE0FFFF, 0,			0,		RAD1,		0,	0 },
+{"rnda2",		"#t2,##",	0x7C000056, 0xFFE0F87F, 0,			0,		RAD1,		0,	0 },
+{"lt",			"#`,#@(b)",	0x7C000036, 0xFC00003F, WR_1|RD_3|LDD,		0,		RAD1,		0,	0 },
+{"st",			"#`,#@(b)",	0x7C00003E, 0xFC00003F, RD_1|RD_3|SM,		0,		RAD1,		0,	0 },
+{"ltp",			"#`,(b)#~",	0x7C0000f2, 0xFC0000FF, WR_1|RD_2|LDD,		0,		RAD1,		0,	0 },
+{"ltp.c0",		"#`,(b)#~",	0x7C000032, 0xFC0000FF, WR_1|RD_2|LDD,		0,		RAD1,		0,	0 },
+{"ltp.c1",		"#`,(b)#~",	0x7C000072, 0xFC0000FF, WR_1|RD_2|LDD,		0,		RAD1,		0,	0 },
+{"ltp.c2",		"#`,(b)#~",	0x7C0000b2, 0xFC0000FF, WR_1|RD_2|LDD,		0,		RAD1,		0,	0 },
+{"lwp",			"t,(b)#~",	0x7C0000f3, 0xFC0000FF, WR_1|RD_2|LDD,		0,		RAD1,		0,	0 },
+{"lwp.c0",		"t,(b)#~",	0x7C000033, 0xFC0000FF, WR_1|RD_2|LDD,		0,		RAD1,		0,	0 },
+{"lwp.c1",		"t,(b)#~",	0x7C000073, 0xFC0000FF, WR_1|RD_2|LDD,		0,		RAD1,		0,	0 },
+{"lwp.c2",		"t,(b)#~",	0x7C0000b3, 0xFC0000FF, WR_1|RD_2|LDD,		0,		RAD1,		0,	0 },
+{"lhp",			"t,(b)#~",	0x7C0000f1, 0xFC0000FF, WR_1|RD_2|LDD,		0,		RAD1,		0,	0 },
+{"lhp.c0",		"t,(b)#~",	0x7C000031, 0xFC0000FF, WR_1|RD_2|LDD,		0,		RAD1,		0,	0 },
+{"lhp.c1",		"t,(b)#~",	0x7C000071, 0xFC0000FF, WR_1|RD_2|LDD,		0,		RAD1,		0,	0 },
+{"lhp.c2",		"t,(b)#~",	0x7C0000b1, 0xFC0000FF, WR_1|RD_2|LDD,		0,		RAD1,		0,	0 },
+{"lhpu",		"t,(b)#~",	0x7C0000f5, 0xFC0000FF, WR_1|RD_2|LDD,		0,		RAD1,		0,	0 },
+{"lhpu.c0",		"t,(b)#~",	0x7C000035, 0xFC0000FF, WR_1|RD_2|LDD,		0,		RAD1,		0,	0 },
+{"lhpu.c1",		"t,(b)#~",	0x7C000075, 0xFC0000FF, WR_1|RD_2|LDD,		0,		RAD1,		0,	0 },
+{"lhpu.c2",		"t,(b)#~",	0x7C0000b5, 0xFC0000FF, WR_1|RD_2|LDD,		0,		RAD1,		0,	0 },
+{"lbp",			"t,(b)#~",	0x7C0000f0, 0xFC0000FF, WR_1|RD_2|LDD,		0,		RAD1,		0,	0 },
+{"lbp.c0",		"t,(b)#~",	0x7C000030, 0xFC0000FF, WR_1|RD_2|LDD,		0,		RAD1,		0,	0 },
+{"lbp.c1",		"t,(b)#~",	0x7C000070, 0xFC0000FF, WR_1|RD_2|LDD,		0,		RAD1,		0,	0 },
+{"lbp.c2",		"t,(b)#~",	0x7C0000b0, 0xFC0000FF, WR_1|RD_2|LDD,		0,		RAD1,		0,	0 },
+{"lbpu",		"t,(b)#~",	0x7C0000f4, 0xFC0000FF, WR_1|RD_2|LDD,		0,		RAD1,		0,	0 },
+{"lbpu.c0",		"t,(b)#~",	0x7C000034, 0xFC0000FF, WR_1|RD_2|LDD,		0,		RAD1,		0,	0 },
+{"lbpu.c1",		"t,(b)#~",	0x7C000074, 0xFC0000FF, WR_1|RD_2|LDD,		0,		RAD1,		0,	0 },
+{"lbpu.c2",		"t,(b)#~",	0x7C0000b4, 0xFC0000FF, WR_1|RD_2|LDD,		0,		RAD1,		0,	0 },
+{"stp",			"#`,(b)#~",	0x7C0000fa, 0xFC0000FF, WR_1|RD_2,		0,		RAD1,		0,	0 },
+{"stp.c0",		"#`,(b)#~",	0x7C00003a, 0xFC0000FF, WR_1|RD_2,		0,		RAD1,		0,	0 },
+{"stp.c1",		"#`,(b)#~",	0x7C00007a, 0xFC0000FF, WR_1|RD_2,		0,		RAD1,		0,	0 },
+{"stp.c2",		"#`,(b)#~",	0x7C0000ba, 0xFC0000FF, WR_1|RD_2,		0,		RAD1,		0,	0 },
+{"swp",			"t,(b)#~",	0x7C0000fb, 0xFC0000FF, WR_1|RD_2,		0,		RAD1,		0,	0 },
+{"swp.c0",		"t,(b)#~",	0x7C00003b, 0xFC0000FF, WR_1|RD_2,		0,		RAD1,		0,	0 },
+{"swp.c1",		"t,(b)#~",	0x7C00007b, 0xFC0000FF, WR_1|RD_2,		0,		RAD1,		0,	0 },
+{"swp.c2",		"t,(b)#~",	0x7C0000bb, 0xFC0000FF, WR_1|RD_2,		0,		RAD1,		0,	0 },
+{"shp",			"t,(b)#~",	0x7C0000f9, 0xFC0000FF, WR_1|RD_2,		0,		RAD1,		0,	0 },
+{"shp.c0",		"t,(b)#~",	0x7C000039, 0xFC0000FF, WR_1|RD_2,		0,		RAD1,		0,	0 },
+{"shp.c1",		"t,(b)#~",	0x7C000079, 0xFC0000FF, WR_1|RD_2,		0,		RAD1,		0,	0 },
+{"shp.c2",		"t,(b)#~",	0x7C0000b9, 0xFC0000FF, WR_1|RD_2,		0,		RAD1,		0,	0 },
+{"sbp",			"t,(b)#~",	0x7C0000f8, 0xFC0000FF, WR_1|RD_2,		0,		RAD1,		0,	0 },
+{"sbp.c0",		"t,(b)#~",	0x7C000038, 0xFC0000FF, WR_1|RD_2,		0,		RAD1,		0,	0 },
+{"sbp.c1",		"t,(b)#~",	0x7C000078, 0xFC0000FF, WR_1|RD_2,		0,		RAD1,		0,	0 },
+{"sbp.c2",		"t,(b)#~",	0x7C0000b8, 0xFC0000FF, WR_1|RD_2,		0,		RAD1,		0,	0 },
+{"mtru",		"t,#u",		0x7C000025, 0xFFE007FF, RD_1,			0,		RAD1,		0,	0 },
+{"mfru",		"t,#u",		0x7C000024, 0xFFE007FF, RD_1,			0,		RAD1,		0,	0 },
+{"mtrk",		"t,#k",		0x7C0000A5, 0xFFE007FF, RD_1,			0,		RAD1,		0,	0 },
+{"mfrk",		"t,#k",		0x7C0000A4, 0xFFE007FF, RD_1,			0,		RAD1,		0,	0 },
+{"sllv2",		"d,t,s",	0x7C000044, 0xFC0007FF, WR_1|RD_2|RD_3,		0,		RAD1,		0,	0 },
+{"srlv2",		"d,t,s",	0x7C000046, 0xFC0007FF, WR_1|RD_2|RD_3,		0,		RAD1,		0,	0 },
+{"srav2",		"d,t,s",	0x7C000047, 0xFC0007FF, WR_1|RD_2|RD_3,		0,		RAD1,		0,	0 },
+{"addr",		"d,s,t",	0x7C000021, 0xFC0007FF, WR_1|RD_2|RD_3,		0,		RAD1,		0,	0 },
+{"addr.s",		"d,s,t",	0x7C0000A1, 0xFC0007FF, WR_1|RD_2|RD_3,		0,		RAD1,		0,	0 },
+{"addr2",		"d,s,t",	0x7C000061, 0xFC0007FF, WR_1|RD_2|RD_3,		0,		RAD1,		0,	0 },
+{"addr2.s",		"d,s,t",	0x7C0000E1, 0xFC0007FF, WR_1|RD_2|RD_3,		0,		RAD1,		0,	0 },
+{"subr",		"d,s,t",	0x7C000023, 0xFC0007FF, WR_1|RD_2|RD_3,		0,		RAD1,		0,	0 },
+{"subr.s",		"d,s,t",	0x7C0000A3, 0xFC0007FF, WR_1|RD_2|RD_3,		0,		RAD1,		0,	0 },
+{"subr2",		"d,s,t",	0x7C000063, 0xFC0007FF, WR_1|RD_2|RD_3,		0,		RAD1,		0,	0 },
+{"subr2.s",		"d,s,t",	0x7C0000E3, 0xFC0007FF, WR_1|RD_2|RD_3,		0,		RAD1,		0,	0 },
+{"sltr2",		"d,s,t",	0x7C00006A, 0xFC0007FF, WR_1|RD_2|RD_3,		0,		RAD1,		0,	0 },
+{"min",			"d,s,t",	0x7C000028, 0xFC0007FF, WR_1|RD_2|RD_3,		0,		RAD1,		0,	0 },
+{"min2",		"d,s,t",	0x7C000068, 0xFC0007FF, WR_1|RD_2|RD_3,		0,		RAD1,		0,	0 },
+{"max",			"d,s,t",	0x7C000029, 0xFC0007FF, WR_1|RD_2|RD_3,		0,		RAD1,		0,	0 },
+{"max2",		"d,s,t",	0x7C000069, 0xFC0007FF, WR_1|RD_2|RD_3,		0,		RAD1,		0,	0 },
+{"absr",		"d,t",		0x7C00000F, 0xFFE007FF, WR_1|RD_2,		0,		RAD1,		0,	0 },
+{"absr.s",		"d,t",		0x7C00008F, 0xFFE007FF, WR_1|RD_2,		0,		RAD1,		0,	0 },
+{"absr2",		"d,t",		0x7C00004F, 0xFFE007FF, WR_1|RD_2,		0,		RAD1,		0,	0 },
+{"absr2.s",		"d,t",		0x7C0000CF, 0xFFE007FF, WR_1|RD_2,		0,		RAD1,		0,	0 },
+{"mux2.hh",		"d,s,t",	0x7C00064D, 0xFC0007FF, WR_1|RD_2|RD_3,		0,		RAD1,		0,	0 },
+{"mux2.hl",		"d,s,t",	0x7C00044D, 0xFC0007FF, WR_1|RD_2|RD_3,		0,		RAD1,		0,	0 },
+{"mux2.lh",		"d,s,t",	0x7C00024D, 0xFC0007FF, WR_1|RD_2|RD_3,		0,		RAD1,		0,	0 },
+{"mux2.ll",		"d,s,t",	0x7C00004D, 0xFC0007FF, WR_1|RD_2|RD_3,		0,		RAD1,		0,	0 },
+{"cls",			"d,t",		0x7C00000E, 0xFFE007FF, WR_1|RD_2,		0,		RAD1,		0,	0 },
+{"cmveqz",		"d,s,t",	0x7C000001, 0xFC0007FF, WR_1|RD_2|RD_3,		0,		RAD1,		0,	0 },
+{"cmveqz.h",		"d,s,t",	0x7C000081, 0xFC0007FF, WR_1|RD_2|RD_3,		0,		RAD1,		0,	0 },
+{"cmveqz.l",		"d,s,t",	0x7C000101, 0xFC0007FF, WR_1|RD_2|RD_3,		0,		RAD1,		0,	0 },
+{"cmvnez",		"d,s,t",	0x7C000041, 0xFC0007FF, WR_1|RD_2|RD_3,		0,		RAD1,		0,	0 },
+{"cmvnez.h",		"d,s,t",	0x7C0000c1, 0xFC0007FF, WR_1|RD_2|RD_3,		0,		RAD1,		0,	0 },
+{"cmvnez.l",		"d,s,t",	0x7C000141, 0xFC0007FF, WR_1|RD_2|RD_3,		0,		RAD1,		0,	0 },
+
+
+/* Coprocessor 0 operations */
+{"mflxc0",		"t,#d4",	0x40600000, 0xFFE007FF, WR_1|RD_C0|LCD,		0,		RLXB,		0,	0 },
+{"mflxc0",		"t,#d4,#H",	0x40600000, 0xFFE007C0, WR_1|RD_C0|LCD,		0,		RLX3,		0,	0 },
+{"mtlxc0",		"t,#d4",	0x40E00000, 0xFFE007FF, RD_1|WR_C0|WR_CC|COD,	0,		RLXB,		0,	0 },
+{"mtlxc0",		"t,#d4,#H",	0x40E00000, 0xFFE007C0, RD_1|WR_C0|WR_CC|COD,	0,		RLX3,		0,	0 },
+/*MAC-DIV*/
+{"sleep",		"",		0x42000038, 0xffffffff, 0,			0,		RLXA,		0,	0 },
+{"sleep",		"#I",		0x42000038, 0xfffff83f, 0,			0,		RLX3,		0,	0 },
+{"madh",		"s,t",		0xF0000000, 0xFC00FFFF, RD_1|RD_2,		0,		RLXA,		0,	0 },
+{"madl",		"s,t",		0xF0000002, 0xFC00FFFF, RD_1|RD_2,		0,		RLXA,		0,	0 },
+{"mazh",		"s,t",		0xF0000004, 0xFC00FFFF, RD_1|RD_2,		0,		RLXA,		0,	0 },
+{"mazl",		"s,t",		0xF0000006, 0xFC00FFFF, RD_1|RD_2,		0,		RLXA,		0,	0 },
+{"msbh",		"s,t",		0xF0000010, 0xFC00FFFF, RD_1|RD_2,		0,		RLXA,		0,	0 },
+{"msbl",		"s,t",		0xF0000012, 0xFC00FFFF, RD_1|RD_2,		0,		RLXA,		0,	0 },
+{"mszh",		"s,t",		0xF0000014, 0xFC00FFFF, RD_1|RD_2,		0,		RLXA,		0,	0 },
+{"mszl",		"s,t",		0xF0000016, 0xFC00FFFF, RD_1|RD_2,		0,		RLXA,		0,	0 },
+{"ltw",			"#`,#=(b)",	0x7800003C, 0xFC00003F, WR_1|RD_3|LDD,		0,		INSN_4181|INSN_4281,	0,	0 },
+/* Lexra opcode extensions. Register mode */
+/* Lexra opcode extensions. Immediate mode */
+{"udi0i",		"t,r,j",	0x60000000, 0xfc000000, WR_1|RD_2,		0,		RLXB,		0,	0 },
+{"udi1i",		"t,r,j",	0x64000000, 0xfc000000, WR_1|RD_2,		0,		RLXB,		0,	0 },
+{"udi2i",		"t,r,j",	0x68000000, 0xfc000000, WR_1|RD_2,		0,		RLXB,		0,	0 },
+{"udi3i",		"t,r,j",	0x6c000000, 0xfc000000, WR_1|RD_2,		0,		RLXB,		0,	0 },
 };
 
 #define MIPS_NUM_OPCODES \

Nevermind, I found that abdoubied has it all ;)

I would be interested in differences between LX5280 and LX5281. If you have any info on that it is highly appreciated!