Created
March 1, 2022 02:02
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-- Code your design here | |
library IEEE; | |
use IEEE.std_logic_1164.all; | |
-- multiplekser 4/1 | |
entity mux is | |
port ( | |
I: in std_logic_vector(3 downto 0); | |
S: in std_logic_vector(1 downto 0); | |
Y: out std_logic); | |
end mux; | |
architecture mux_arch1 of mux is | |
begin | |
case S is | |
when "00" => Y <= I(0); | |
when "01" => Y <= I(1); | |
when "10" => Y <= I(2); | |
when "11" => Y <= I(3); | |
end case; | |
end mux_arch1; | |
architecture mux_arch2 of mux is | |
begin | |
with S select | |
Y <= I(0) when "00", | |
I(1) when "01", | |
I(2) when "10", | |
I(3) when "11"; | |
end mux_arch2; | |
-- prosti brojevi | |
entity prime is | |
port ( | |
num: in std_logic_vector(8 downto 0); | |
is_prime: out std_logic); | |
end prime; | |
architecture prime_arch of prime is | |
begin | |
with num select | |
is_prime <= '1' when "00000010" | "00000011" | "00000101" | |
| "00000111" | "00001011" | "00001101" | |
| "00010001" | "00010011" | "00010111" | |
| "00011101" | "00011111", | |
'0' when others; | |
end; | |
-- 7seg display | |
-- +--a--+ | |
-- | | | |
-- b c | |
-- | | | |
-- +--d--+ | |
-- | | | |
-- e f | |
-- | | | |
-- +--g--+ | |
entity digit_display is | |
port ( | |
num: in std_logic_vector(3 downto 0); | |
a, b, c, d, e, f, g: out std_logic); | |
end digit_display; | |
architecture display_arch of digit_display is | |
signal leds: std_logic_vector(6 downto 0); | |
begin | |
with nums select | |
leds <= "1110111" when "0000", | |
"0010010" when "0001", | |
"1011101" when "0010", | |
"1011011" when "0011", | |
"0111010" when "0100", | |
"1101011" when "0101", | |
"1101111" when "0110", | |
"1010011" when "0111", | |
"1111111" when "1000", | |
"1111011" when "1001", | |
"1101101" when others; | |
a <= nums(6); | |
b <= nums(5); | |
c <= nums(4); | |
d <= nums(3); | |
e <= nums(2); | |
f <= nums(1); | |
g <= nums(0); | |
end display_arch; | |
-- ALU | |
-- '00' => and, '01' => or, '10' => xor, '11' => add | |
entity alu is | |
port ( | |
a, b: in std_logic_vector(3 downto 0); | |
op: in std_logic_vector(1 downto 0); | |
z: out std_logic_vector(3 downto 0)); | |
end alu; | |
architecture alu_arch of alu is | |
begin | |
with op select | |
z <= (a(3) and b(3)) & (a(2) and b(2)) & (a(1) and b(1)) & (a(0) and b(0)) when "00", | |
(a(3) or b(3)) & (a(2) or b(2)) & (a(1) or b(1)) & (a(0) or b(0)) when "01", | |
(a(3) xor b(3)) & (a(2) xor b(2)) & (a(1) xor b(1)) & (a(0) xor b(0)) when "10", | |
(std_logic_vector(unsigned(a) + unsigned(b))) when "11", | |
end alu_arch; |
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Mozda prvi primer za mux koji koristi
case
bude pravio problem. Ako jeste tako, necemo koristiti case van procesa (primer procesa nema u ovom kodu ali ima u daljim).