hansemro/Makefile

## kc705.xdc
# clk_p_i
set_property LOC AD12 [get_ports {clk_p_i}]
set_property IOSTANDARD LVDS [get_ports {clk_p_i}]

# clk_n_i
set_property LOC AD11 [get_ports {clk_n_i}]
set_property IOSTANDARD LVDS [get_ports {clk_n_i}]

# rst_i
set_property LOC G12 [get_ports {rst_i}]
set_property IOSTANDARD LVCMOS25 [get_ports {rst_i}]

# led[0]
set_property LOC AB8 [get_ports {led_o[0]}]
set_property IOSTANDARD LVCMOS15 [get_ports {led_o[0]}]

# led[1]
set_property LOC AA8 [get_ports {led_o[1]}]
set_property IOSTANDARD LVCMOS15 [get_ports {led_o[1]}]

# led[2]
set_property LOC AC9 [get_ports {led_o[2]}]
set_property IOSTANDARD LVCMOS15 [get_ports {led_o[2]}]

# led[3]
set_property LOC AB9 [get_ports {led_o[3]}]
set_property IOSTANDARD LVCMOS15 [get_ports {led_o[3]}]

# led[4]
set_property LOC AE26 [get_ports {led_o[4]}]
set_property IOSTANDARD LVCMOS25 [get_ports {led_o[4]}]

# led[5]
set_property LOC G19 [get_ports {led_o[5]}]
set_property IOSTANDARD LVCMOS25 [get_ports {led_o[5]}]

# led[6]
set_property LOC E18 [get_ports {led_o[6]}]
set_property IOSTANDARD LVCMOS25 [get_ports {led_o[6]}]

# led[7]
set_property LOC F16 [get_ports {led_o[7]}]
set_property IOSTANDARD LVCMOS25 [get_ports {led_o[7]}]

## Makefile
PROJECT = top
TOP = top
TOP_VERILOG = top.v
ADDITIONAL_SOURCES =

# Target Platform
FAMILY  = kintex7
PART    = xc7k325tffg900-2
BOARD   = kc705
XDC    ?= kc705.xdc
CHIPDB ?= ./chipdb
JTAG_LINK ?=

include ./openXC7.mk

## openXC7.mk
NEXTPNR_XILINX_DIR ?= /snap/openxc7/current/opt/nextpnr-xilinx
NEXTPNR_XILINX_PYTHON_DIR ?= ${NEXTPNR_XILINX_DIR}/python
PRJXRAY_DB_DIR ?= ${NEXTPNR_XILINX_DIR}/external/prjxray-db

DBPART = $(shell echo ${PART} | sed -e 's/-[0-9]//g')
SPEEDGRADE = $(shell echo ${PART} | sed -e 's/.*\-\([0-9]\)/\1/g')

CHIPDB ?= ../chipdb/
PYPY3 ?= pypy3

TOP ?= ${PROJECT}
TOP_MODULE ?= ${TOP}

PNR_DEBUG ?= # --verbose --debug

BOARD ?= UNKNOWN
JTAG_LINK ?= --board ${BOARD}

XDC ?= ${PROJECT}.xdc

.PHONY: all
all: ${PROJECT}.bit

.PHONY: program
program: ${PROJECT}.bit
	openFPGALoader ${JTAG_LINK} --bitstream $<

${PROJECT}.json: ${TOP}.v ${ADDITIONAL_SOURCES}
	yosys ${YOSYS_OPTS} -p "synth_xilinx -flatten -abc9 ${SYNTH_OPTS} -arch xc7 -top ${TOP_MODULE}; write_json ${PROJECT}.json" $< ${ADDITIONAL_SOURCES}

# The chip database only needs to be generated once
# that is why we don't clean it with make clean
${CHIPDB}/${DBPART}.bin:
	${PYPY3} ${NEXTPNR_XILINX_PYTHON_DIR}/bbaexport.py --device ${PART} --bba ${DBPART}.bba
	mkdir -p $(CHIPDB) && bbasm -l ${DBPART}.bba ${CHIPDB}/${DBPART}.bin
	rm -f ${DBPART}.bba

${PROJECT}.pack.json: ${PROJECT}.json ${CHIPDB}/${DBPART}.bin ${XDC}
	nextpnr-xilinx --chipdb ${CHIPDB}/${DBPART}.bin --xdc ${XDC} --json ${PROJECT}.json --pack-only --write $@ ${PNR_ARGS} ${PNR_DEBUG}

${PROJECT}.place.json: ${PROJECT}.pack.json
	nextpnr-xilinx --chipdb ${CHIPDB}/${DBPART}.bin --xdc ${XDC} --no-pack --no-route --json $^ --write $@ ${PNR_ARGS} ${PNR_DEBUG}

${PROJECT}.fasm: ${PROJECT}.place.json
	nextpnr-xilinx --chipdb ${CHIPDB}/${DBPART}.bin --xdc ${XDC} --no-pack --no-place --json $^ --fasm $@ --write ${PROJECT}.route.json ${PNR_ARGS} ${PNR_DEBUG}

${PROJECT}.frames: ${PROJECT}.fasm
	fasm2frames --part ${PART} --db-root ${PRJXRAY_DB_DIR}/${FAMILY} $< > $@

${PROJECT}.bit: ${PROJECT}.frames
	xc7frames2bit --part_file ${PRJXRAY_DB_DIR}/${FAMILY}/${PART}/part.yaml --part_name ${PART} --frm_file $< --output_file $@

.PHONY: clean
clean:
	@rm -f *.bit
	@rm -f *.frames
	@rm -f *.fasm
	@rm -f *.json

.PHONY: pnrclean
pnrclean:
	rm *.fasm *.frames *.bit

## top.fasm
CLBLM_R_X3Y316.SLICEM_X0.ALUT.INIT[63:0] = 64'b1100110011001100110011001100110010101010101010101010101010101010
CLBLM_R_X3Y316.SLICEM_X0.AOUTMUX.XOR
CLBLM_R_X3Y316.SLICEM_X0.BLUT.INIT[63:0] = 64'b1111111111111111000000000000000010101010101010101010101010101010
CLBLM_R_X3Y316.SLICEM_X0.BOUTMUX.XOR
CLBLM_R_X3Y316.SLICEM_X0.CLUT.INIT[63:0] = 64'b1111000011110000111100001111000011001100110011001100110011001100
CLBLM_R_X3Y316.SLICEM_X0.COUTMUX.XOR
CLBLM_R_X3Y316.SLICEM_X0.DLUT.INIT[63:0] = 64'b1111111111111111000000000000000011001100110011001100110011001100
CLBLM_R_X3Y316.SLICEM_X0.DOUTMUX.XOR
CLBLM_R_X3Y316.SLICEL_X1.AOUTMUX.A5Q
CLBLM_R_X3Y316.SLICEM_X0.DFF.ZINI
CLBLM_R_X3Y316.SLICEM_X0.DFF.ZRST
CLBLM_R_X3Y316.SLICEM_X0.DFFMUX.DX
CLBLM_R_X3Y316.SLICEM_X0.NOCLKINV
CLBLM_R_X3Y316.SLICEM_X0.SRUSEDMUX
CLBLM_R_X3Y316.SLICEL_X1.A5FF.ZINI
CLBLM_R_X3Y316.SLICEL_X1.A5FF.ZRST
CLBLM_R_X3Y316.SLICEL_X1.A5FFMUX.IN_B
CLBLM_R_X3Y316.SLICEL_X1.BFF.ZINI
CLBLM_R_X3Y316.SLICEL_X1.BFF.ZRST
CLBLM_R_X3Y316.SLICEL_X1.BFFMUX.BX
CLBLM_R_X3Y316.SLICEL_X1.NOCLKINV
CLBLM_R_X3Y316.SLICEL_X1.SRUSEDMUX
CLBLM_R_X3Y316.SLICEM_X0.PRECYINIT.CIN
CLBLM_R_X3Y316.SLICEM_X0.CARRY4.ACY0
CLBLM_R_X3Y316.SLICEM_X0.CARRY4.BCY0
CLBLM_R_X3Y316.SLICEM_X0.CARRY4.CCY0
CLBLM_R_X3Y316.SLICEM_X0.CARRY4.DCY0

CLBLM_R_X3Y315.SLICEM_X0.ALUT.INIT[63:0] = 64'b1111000011110000111100001111000010101010101010101010101010101010
CLBLM_R_X3Y315.SLICEM_X0.AOUTMUX.XOR
CLBLM_R_X3Y315.SLICEM_X0.BLUT.INIT[63:0] = 64'b1111111111111111000000000000000010101010101010101010101010101010
CLBLM_R_X3Y315.SLICEM_X0.BOUTMUX.XOR
CLBLM_R_X3Y315.SLICEM_X0.CLUT.INIT[63:0] = 64'b1010101010101010101010101010101011001100110011001100110011001100
CLBLM_R_X3Y315.SLICEM_X0.COUTMUX.XOR
CLBLM_R_X3Y315.SLICEM_X0.DLUT.INIT[63:0] = 64'b1111111111111111000000000000000011001100110011001100110011001100
CLBLM_R_X3Y315.SLICEM_X0.DOUTMUX.XOR
CLBLM_R_X3Y315.SLICEL_X1.COUTMUX.C5Q
CLBLM_R_X3Y315.SLICEM_X0.CFF.ZINI
CLBLM_R_X3Y315.SLICEM_X0.CFF.ZRST
CLBLM_R_X3Y315.SLICEM_X0.CFFMUX.CX
CLBLM_R_X3Y315.SLICEM_X0.NOCLKINV
CLBLM_R_X3Y315.SLICEM_X0.SRUSEDMUX
CLBLM_R_X3Y315.SLICEL_X1.AFF.ZINI
CLBLM_R_X3Y315.SLICEL_X1.AFF.ZRST
CLBLM_R_X3Y315.SLICEL_X1.AFFMUX.AX
CLBLM_R_X3Y315.SLICEL_X1.BFF.ZINI
CLBLM_R_X3Y315.SLICEL_X1.BFF.ZRST
CLBLM_R_X3Y315.SLICEL_X1.BFFMUX.BX
CLBLM_R_X3Y315.SLICEL_X1.C5FF.ZINI
CLBLM_R_X3Y315.SLICEL_X1.C5FF.ZRST
CLBLM_R_X3Y315.SLICEL_X1.C5FFMUX.IN_B
CLBLM_R_X3Y315.SLICEL_X1.NOCLKINV
CLBLM_R_X3Y315.SLICEL_X1.SRUSEDMUX
CLBLM_R_X3Y315.SLICEM_X0.PRECYINIT.CIN
CLBLM_R_X3Y315.SLICEM_X0.CARRY4.ACY0
CLBLM_R_X3Y315.SLICEM_X0.CARRY4.BCY0
CLBLM_R_X3Y315.SLICEM_X0.CARRY4.CCY0
CLBLM_R_X3Y315.SLICEM_X0.CARRY4.DCY0

CLBLM_R_X3Y314.SLICEM_X0.ALUT.INIT[63:0] = 64'b1010101010101010101010101010101011001100110011001100110011001100
CLBLM_R_X3Y314.SLICEM_X0.AOUTMUX.XOR
CLBLM_R_X3Y314.SLICEM_X0.BLUT.INIT[63:0] = 64'b1100110011001100110011001100110011110000111100001111000011110000
CLBLM_R_X3Y314.SLICEM_X0.CLUT.INIT[63:0] = 64'b1111000011110000111100001111000010101010101010101010101010101010
CLBLM_R_X3Y314.SLICEM_X0.COUTMUX.XOR
CLBLM_R_X3Y314.SLICEM_X0.DLUT.INIT[63:0] = 64'b1111000011110000111100001111000010101010101010101010101010101010
CLBLM_R_X3Y314.SLICEL_X1.BOUTMUX.B5Q
CLBLM_R_X3Y314.SLICEM_X0.BFF.ZINI
CLBLM_R_X3Y314.SLICEM_X0.BFF.ZRST
CLBLM_R_X3Y314.SLICEM_X0.BFFMUX.XOR
CLBLM_R_X3Y314.SLICEM_X0.DFF.ZINI
CLBLM_R_X3Y314.SLICEM_X0.DFF.ZRST
CLBLM_R_X3Y314.SLICEM_X0.DFFMUX.XOR
CLBLM_R_X3Y314.SLICEM_X0.NOCLKINV
CLBLM_R_X3Y314.SLICEM_X0.SRUSEDMUX
CLBLM_R_X3Y314.SLICEL_X1.B5FF.ZINI
CLBLM_R_X3Y314.SLICEL_X1.B5FF.ZRST
CLBLM_R_X3Y314.SLICEL_X1.B5FFMUX.IN_B
CLBLM_R_X3Y314.SLICEL_X1.DFF.ZINI
CLBLM_R_X3Y314.SLICEL_X1.DFF.ZRST
CLBLM_R_X3Y314.SLICEL_X1.DFFMUX.DX
CLBLM_R_X3Y314.SLICEL_X1.NOCLKINV
CLBLM_R_X3Y314.SLICEL_X1.SRUSEDMUX
CLBLM_R_X3Y314.SLICEM_X0.PRECYINIT.CIN
CLBLM_R_X3Y314.SLICEM_X0.CARRY4.ACY0
CLBLM_R_X3Y314.SLICEM_X0.CARRY4.BCY0
CLBLM_R_X3Y314.SLICEM_X0.CARRY4.CCY0
CLBLM_R_X3Y314.SLICEM_X0.CARRY4.DCY0

CLBLM_R_X3Y313.SLICEM_X0.ALUT.INIT[63:0] = 64'b1111111111111111000000000000000010101010101010101010101010101010
CLBLM_R_X3Y313.SLICEM_X0.AOUTMUX.XOR
CLBLM_R_X3Y313.SLICEM_X0.BLUT.INIT[63:0] = 64'b1111000011110000111100001111000010101010101010101010101010101010
CLBLM_R_X3Y313.SLICEM_X0.BOUTMUX.XOR
CLBLM_R_X3Y313.SLICEM_X0.CLUT.INIT[63:0] = 64'b1111000011110000111100001111000011001100110011001100110011001100
CLBLM_R_X3Y313.SLICEM_X0.COUTMUX.XOR
CLBLM_R_X3Y313.SLICEM_X0.DLUT.INIT[63:0] = 64'b1111000011110000111100001111000011001100110011001100110011001100
CLBLM_R_X3Y313.SLICEM_X0.DOUTMUX.XOR
CLBLM_R_X3Y313.SLICEL_X1.COUTMUX.C5Q
CLBLM_R_X3Y313.SLICEL_X1.DOUTMUX.D5Q
CLBLM_R_X3Y313.SLICEM_X0.CFF.ZINI
CLBLM_R_X3Y313.SLICEM_X0.CFF.ZRST
CLBLM_R_X3Y313.SLICEM_X0.CFFMUX.CX
CLBLM_R_X3Y313.SLICEM_X0.DFF.ZINI
CLBLM_R_X3Y313.SLICEM_X0.DFF.ZRST
CLBLM_R_X3Y313.SLICEM_X0.DFFMUX.DX
CLBLM_R_X3Y313.SLICEM_X0.NOCLKINV
CLBLM_R_X3Y313.SLICEM_X0.SRUSEDMUX
CLBLM_R_X3Y313.SLICEL_X1.C5FF.ZINI
CLBLM_R_X3Y313.SLICEL_X1.C5FF.ZRST
CLBLM_R_X3Y313.SLICEL_X1.C5FFMUX.IN_B
CLBLM_R_X3Y313.SLICEL_X1.D5FF.ZINI
CLBLM_R_X3Y313.SLICEL_X1.D5FF.ZRST
CLBLM_R_X3Y313.SLICEL_X1.D5FFMUX.IN_B
CLBLM_R_X3Y313.SLICEL_X1.NOCLKINV
CLBLM_R_X3Y313.SLICEL_X1.SRUSEDMUX
CLBLM_R_X3Y313.SLICEM_X0.PRECYINIT.CIN
CLBLM_R_X3Y313.SLICEM_X0.CARRY4.ACY0
CLBLM_R_X3Y313.SLICEM_X0.CARRY4.BCY0
CLBLM_R_X3Y313.SLICEM_X0.CARRY4.CCY0
CLBLM_R_X3Y313.SLICEM_X0.CARRY4.DCY0

CLBLM_R_X3Y312.SLICEM_X0.ALUT.INIT[63:0] = 64'b1111000011110000111100001111000010101010101010101010101010101010
CLBLM_R_X3Y312.SLICEM_X0.BLUT.INIT[63:0] = 64'b1100110011001100110011001100110010101010101010101010101010101010
CLBLM_R_X3Y312.SLICEM_X0.BOUTMUX.XOR
CLBLM_R_X3Y312.SLICEM_X0.CLUT.INIT[63:0] = 64'b1100110011001100110011001100110011110000111100001111000011110000
CLBLM_R_X3Y312.SLICEM_X0.DLUT.INIT[63:0] = 64'b1111000011110000111100001111000011001100110011001100110011001100
CLBLM_R_X3Y312.SLICEM_X0.DOUTMUX.XOR
CLBLM_R_X3Y312.SLICEL_X1.BOUTMUX.B5Q
CLBLM_R_X3Y312.SLICEL_X1.DOUTMUX.D5Q
CLBLM_R_X3Y312.SLICEM_X0.AFF.ZINI
CLBLM_R_X3Y312.SLICEM_X0.AFF.ZRST
CLBLM_R_X3Y312.SLICEM_X0.AFFMUX.XOR
CLBLM_R_X3Y312.SLICEM_X0.CFF.ZINI
CLBLM_R_X3Y312.SLICEM_X0.CFF.ZRST
CLBLM_R_X3Y312.SLICEM_X0.CFFMUX.XOR
CLBLM_R_X3Y312.SLICEM_X0.NOCLKINV
CLBLM_R_X3Y312.SLICEM_X0.SRUSEDMUX
CLBLM_R_X3Y312.SLICEL_X1.B5FF.ZINI
CLBLM_R_X3Y312.SLICEL_X1.B5FF.ZRST
CLBLM_R_X3Y312.SLICEL_X1.B5FFMUX.IN_B
CLBLM_R_X3Y312.SLICEL_X1.D5FF.ZINI
CLBLM_R_X3Y312.SLICEL_X1.D5FF.ZRST
CLBLM_R_X3Y312.SLICEL_X1.D5FFMUX.IN_B
CLBLM_R_X3Y312.SLICEL_X1.NOCLKINV
CLBLM_R_X3Y312.SLICEL_X1.SRUSEDMUX
CLBLM_R_X3Y312.SLICEM_X0.PRECYINIT.CIN
CLBLM_R_X3Y312.SLICEM_X0.CARRY4.ACY0
CLBLM_R_X3Y312.SLICEM_X0.CARRY4.BCY0
CLBLM_R_X3Y312.SLICEM_X0.CARRY4.CCY0
CLBLM_R_X3Y312.SLICEM_X0.CARRY4.DCY0

CLBLM_R_X3Y311.SLICEM_X0.ALUT.INIT[63:0] = 64'b1111000011110000111100001111000010101010101010101010101010101010
CLBLM_R_X3Y311.SLICEM_X0.AOUTMUX.XOR
CLBLM_R_X3Y311.SLICEM_X0.BLUT.INIT[63:0] = 64'b1100110011001100110011001100110010101010101010101010101010101010
CLBLM_R_X3Y311.SLICEM_X0.BOUTMUX.XOR
CLBLM_R_X3Y311.SLICEM_X0.CLUT.INIT[63:0] = 64'b1111111111111111000000000000000011001100110011001100110011001100
CLBLM_R_X3Y311.SLICEM_X0.COUTMUX.XOR
CLBLM_R_X3Y311.SLICEM_X0.DLUT.INIT[63:0] = 64'b1111000011110000111100001111000011001100110011001100110011001100
CLBLM_R_X3Y311.SLICEM_X0.DOUTMUX.XOR
CLBLM_R_X3Y311.SLICEL_X1.COUTMUX.C5Q
CLBLM_R_X3Y311.SLICEL_X1.DOUTMUX.D5Q
CLBLM_R_X3Y311.SLICEM_X0.DFF.ZINI
CLBLM_R_X3Y311.SLICEM_X0.DFF.ZRST
CLBLM_R_X3Y311.SLICEM_X0.DFFMUX.DX
CLBLM_R_X3Y311.SLICEM_X0.NOCLKINV
CLBLM_R_X3Y311.SLICEM_X0.SRUSEDMUX
CLBLM_R_X3Y311.SLICEL_X1.BFF.ZINI
CLBLM_R_X3Y311.SLICEL_X1.BFF.ZRST
CLBLM_R_X3Y311.SLICEL_X1.BFFMUX.BX
CLBLM_R_X3Y311.SLICEL_X1.C5FF.ZINI
CLBLM_R_X3Y311.SLICEL_X1.C5FF.ZRST
CLBLM_R_X3Y311.SLICEL_X1.C5FFMUX.IN_B
CLBLM_R_X3Y311.SLICEL_X1.D5FF.ZINI
CLBLM_R_X3Y311.SLICEL_X1.D5FF.ZRST
CLBLM_R_X3Y311.SLICEL_X1.D5FFMUX.IN_B
CLBLM_R_X3Y311.SLICEL_X1.NOCLKINV
CLBLM_R_X3Y311.SLICEL_X1.SRUSEDMUX
CLBLM_R_X3Y311.SLICEM_X0.PRECYINIT.CIN
CLBLM_R_X3Y311.SLICEM_X0.CARRY4.ACY0
CLBLM_R_X3Y311.SLICEM_X0.CARRY4.BCY0
CLBLM_R_X3Y311.SLICEM_X0.CARRY4.CCY0
CLBLM_R_X3Y311.SLICEM_X0.CARRY4.DCY0

CLBLM_R_X3Y310.SLICEM_X0.ALUT.INIT[63:0] = 64'b1010101010101010101010101010101011001100110011001100110011001100
CLBLM_R_X3Y310.SLICEM_X0.BLUT.INIT[63:0] = 64'b1111111111111111000000000000000011001100110011001100110011001100
CLBLM_R_X3Y310.SLICEM_X0.BOUTMUX.XOR
CLBLM_R_X3Y310.SLICEM_X0.CLUT.INIT[63:0] = 64'b1100110011001100110011001100110010101010101010101010101010101010
CLBLM_R_X3Y310.SLICEM_X0.COUTMUX.XOR
CLBLM_R_X3Y310.SLICEM_X0.DLUT.INIT[63:0] = 64'b1111000011110000111100001111000010101010101010101010101010101010
CLBLM_R_X3Y310.SLICEL_X1.AOUTMUX.A5Q
CLBLM_R_X3Y310.SLICEM_X0.CFF.ZINI
CLBLM_R_X3Y310.SLICEM_X0.CFF.ZRST
CLBLM_R_X3Y310.SLICEM_X0.CFFMUX.CX
CLBLM_R_X3Y310.SLICEM_X0.DFF.ZINI
CLBLM_R_X3Y310.SLICEM_X0.DFF.ZRST
CLBLM_R_X3Y310.SLICEM_X0.DFFMUX.XOR
CLBLM_R_X3Y310.SLICEM_X0.NOCLKINV
CLBLM_R_X3Y310.SLICEM_X0.SRUSEDMUX
CLBLM_R_X3Y310.SLICEL_X1.A5FF.ZINI
CLBLM_R_X3Y310.SLICEL_X1.A5FF.ZRST
CLBLM_R_X3Y310.SLICEL_X1.A5FFMUX.IN_B
CLBLM_R_X3Y310.SLICEL_X1.NOCLKINV
CLBLM_R_X3Y310.SLICEL_X1.SRUSEDMUX
CLBLM_R_X3Y310.SLICEM_X0.PRECYINIT.AX
CLBLM_R_X3Y310.SLICEM_X0.CARRY4.ACY0
CLBLM_R_X3Y310.SLICEM_X0.CARRY4.BCY0
CLBLM_R_X3Y310.SLICEM_X0.CARRY4.CCY0
CLBLM_R_X3Y310.SLICEM_X0.CARRY4.DCY0

CLBLM_R_X3Y305.SLICEM_X0.NOCLKINV
CLBLM_R_X3Y305.SLICEL_X1.CFF.ZINI
CLBLM_R_X3Y305.SLICEL_X1.CFF.ZRST
CLBLM_R_X3Y305.SLICEL_X1.CFFMUX.CX
CLBLM_R_X3Y305.SLICEL_X1.DFF.ZINI
CLBLM_R_X3Y305.SLICEL_X1.DFF.ZRST
CLBLM_R_X3Y305.SLICEL_X1.DFFMUX.DX
CLBLM_R_X3Y305.SLICEL_X1.NOCLKINV
CLBLM_R_X3Y305.SLICEL_X1.SRUSEDMUX

CLBLL_L_X2Y299.SLICEL_X0.ALUT.INIT[63:0] = 64'b0000111100001111000011110000111100001111000011110000111100001111
CLBLL_L_X2Y299.SLICEL_X0.AFF.ZINI
CLBLL_L_X2Y299.SLICEL_X0.AFF.ZRST
CLBLL_L_X2Y299.SLICEL_X0.AFFMUX.O6
CLBLL_L_X2Y299.SLICEL_X0.NOCLKINV
CLBLL_L_X2Y299.SLICEL_X0.SRUSEDMUX
CLBLL_L_X2Y299.SLICEL_X1.NOCLKINV

RIOB18_X95Y75.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18_SSTL12_SSTL135_SSTL15.IN_ONLY
RIOB18_X95Y75.IOB_Y1.PULLTYPE.NONE

RIOB18_X95Y75.IOB_Y0.LVDS_SSTL12_SSTL135_SSTL15.IN_DIFF
RIOB18_X95Y75.IOB_Y0.LVDS.IN_USE
RIOB18_X95Y75.IOB_Y0.LVDS.IN_ONLY
RIOB18_X95Y75.IOB_Y0.PULLTYPE.NONE

LIOB33_SING_X0Y349.IOB_Y1.LVCMOS25_LVCMOS33_LVTTL.IN
LIOB33_SING_X0Y349.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVDS_25_LVTTL_SSTL135_SSTL15_TMDS_33.IN_ONLY
LIOB33_SING_X0Y349.IOB_Y1.PULLTYPE.NONE

RIOB18_X95Y95.IOB_Y1.LVCMOS15_LVCMOS18.DRIVE.I12_I16_I2_I4_I6_I8
RIOB18_X95Y95.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18.SLEW.SLOW
RIOB18_X95Y95.IOB_Y1.PULLTYPE.NONE

RIOB18_X95Y95.IOB_Y0.LVCMOS15_LVCMOS18.DRIVE.I12_I16_I2_I4_I6_I8
RIOB18_X95Y95.IOB_Y0.LVCMOS12_LVCMOS15_LVCMOS18.SLEW.SLOW
RIOB18_X95Y95.IOB_Y0.PULLTYPE.NONE

RIOB18_X95Y93.IOB_Y1.LVCMOS15_LVCMOS18.DRIVE.I12_I16_I2_I4_I6_I8
RIOB18_X95Y93.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18.SLEW.SLOW
RIOB18_X95Y93.IOB_Y1.PULLTYPE.NONE

RIOB18_X95Y93.IOB_Y0.LVCMOS15_LVCMOS18.DRIVE.I12_I16_I2_I4_I6_I8
RIOB18_X95Y93.IOB_Y0.LVCMOS12_LVCMOS15_LVCMOS18.SLEW.SLOW
RIOB18_X95Y93.IOB_Y0.PULLTYPE.NONE

LIOB33_SING_X0Y50.IOB_Y0.LVCMOS25.DRIVE.I12
LIOB33_SING_X0Y50.IOB_Y0.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL_SSTL135_SSTL15.SLEW.SLOW
LIOB33_SING_X0Y50.IOB_Y0.PULLTYPE.NONE

LIOB33_SING_X0Y299.IOB_Y1.LVCMOS25.DRIVE.I12
LIOB33_SING_X0Y299.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL_SSTL135_SSTL15.SLEW.SLOW
LIOB33_SING_X0Y299.IOB_Y1.PULLTYPE.NONE

LIOB33_SING_X0Y250.IOB_Y0.LVCMOS25.DRIVE.I12
LIOB33_SING_X0Y250.IOB_Y0.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL_SSTL135_SSTL15.SLEW.SLOW
LIOB33_SING_X0Y250.IOB_Y0.PULLTYPE.NONE

LIOB33_SING_X0Y300.IOB_Y0.LVCMOS25.DRIVE.I12
LIOB33_SING_X0Y300.IOB_Y0.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL_SSTL135_SSTL15.SLEW.SLOW
LIOB33_SING_X0Y300.IOB_Y0.PULLTYPE.NONE

HCLK_IOI_X235Y78.ONLY_DIFF_IN_USE

CLBLL_L_X2Y299.CLBLL_LOGIC_OUTS4.CLBLL_LL_AQ
INT_L_X2Y299.IMUX_L1.LOGIC_OUTS_L4
CLBLL_L_X2Y299.CLBLL_LL_A3.CLBLL_IMUX1

INT_L_X2Y299.NN6BEG0.LOGIC_OUTS_L12
INT_L_X2Y305.NN6BEG0.NN6END0
INT_L_X2Y311.EL1BEG_N3.NN6END0
INT_R_X3Y310.IMUX7.EL1END3
CLBLM_R_X3Y310.CLBLM_M_A1.CLBLM_IMUX7
CLBLL_L_X2Y299.CLBLL_LOGIC_OUTS12.CLBLL_LL_A

CLBLM_R_X3Y310.CLBLM_M_COUT_N.CLBLM_M_COUT

INT_R_X3Y310.FAN_ALT3.LOGIC_OUTS21
INT_R_X3Y310.FAN_BOUNCE3.FAN_ALT3
INT_R_X3Y310.BYP_ALT3.FAN_BOUNCE3
INT_R_X3Y310.BYP3.BYP_ALT3
CLBLM_R_X3Y310.CLBLM_LOGIC_OUTS21.CLBLM_M_BMUX
CLBLM_R_X3Y310.CLBLM_M_CX.CLBLM_BYP3

CLBLM_R_X3Y310.CLBLM_LOGIC_OUTS22.CLBLM_M_CMUX
INT_R_X3Y310.BYP0.BYP_ALT0
CLBLM_R_X3Y310.CLBLM_L_AX.CLBLM_BYP0
INT_R_X3Y310.BYP_ALT0.LOGIC_OUTS22

INT_R_X3Y310.SR1BEG3.LOGIC_OUTS6
INT_R_X3Y310.IMUX24.SR1END_N3_3
CLBLM_R_X3Y310.CLBLM_LOGIC_OUTS6.CLBLM_M_CQ
CLBLM_R_X3Y310.CLBLM_M_B5.CLBLM_IMUX24

INT_R_X3Y310.IMUX29.LOGIC_OUTS16
CLBLM_R_X3Y310.CLBLM_LOGIC_OUTS16.CLBLM_L_AMUX
CLBLM_R_X3Y310.CLBLM_M_C2.CLBLM_IMUX29

CLBLM_R_X3Y310.CLBLM_LOGIC_OUTS7.CLBLM_M_DQ
INT_R_X3Y310.IMUX38.LOGIC_OUTS7
CLBLM_R_X3Y310.CLBLM_M_D3.CLBLM_IMUX38

CLBLM_R_X3Y311.CLBLM_M_COUT_N.CLBLM_M_COUT

INT_R_X3Y311.NL1BEG1.LOGIC_OUTS20
INT_R_X3Y312.FAN_ALT2.NL1END1
CLBLM_R_X3Y311.CLBLM_LOGIC_OUTS20.CLBLM_M_AMUX
INT_R_X3Y312.FAN_BOUNCE2.FAN_ALT2
INT_R_X3Y311.BYP_ALT6.FAN_BOUNCE_S3_2
INT_R_X3Y311.BYP6.BYP_ALT6
CLBLM_R_X3Y311.CLBLM_M_DX.CLBLM_BYP6

CLBLM_R_X3Y311.CLBLM_LOGIC_OUTS21.CLBLM_M_BMUX
INT_R_X3Y311.BYP_ALT7.LOGIC_OUTS21
INT_R_X3Y311.BYP7.BYP_ALT7
CLBLM_R_X3Y311.CLBLM_L_DX.CLBLM_BYP7

INT_R_X3Y311.BYP_ALT0.LOGIC_OUTS22
INT_R_X3Y311.BYP_ALT5.BYP_BOUNCE0
INT_R_X3Y311.BYP5.BYP_ALT5
INT_R_X3Y311.BYP_BOUNCE0.BYP_ALT0
CLBLM_R_X3Y311.CLBLM_L_BX.CLBLM_BYP5
CLBLM_R_X3Y311.CLBLM_LOGIC_OUTS22.CLBLM_M_CMUX

INT_R_X3Y311.NW2BEG1.LOGIC_OUTS23
CLBLM_R_X3Y311.CLBLM_LOGIC_OUTS23.CLBLM_M_DMUX
INT_R_X3Y311.BYP_ALT2.ER1END2
INT_R_X3Y311.BYP2.BYP_ALT2
INT_L_X2Y311.ER1BEG2.SR1END1
CLBLM_R_X3Y311.CLBLM_L_CX.CLBLM_BYP2
INT_L_X2Y312.SR1BEG1.NW2END1

INT_R_X3Y311.SR1BEG_S0.LOGIC_OUTS7
INT_R_X3Y311.IMUX1.SR1BEG_S0
CLBLM_R_X3Y311.CLBLM_M_A3.CLBLM_IMUX1
CLBLM_R_X3Y311.CLBLM_LOGIC_OUTS7.CLBLM_M_DQ

INT_R_X3Y311.IMUX18.LOGIC_OUTS19
CLBLM_R_X3Y311.CLBLM_M_B2.CLBLM_IMUX18
CLBLM_R_X3Y311.CLBLM_LOGIC_OUTS19.CLBLM_L_DMUX

CLBLM_R_X3Y311.CLBLM_LOGIC_OUTS1.CLBLM_L_BQ
INT_R_X3Y311.IMUX31.NL1END_S3_0
INT_R_X3Y311.NL1BEG0.LOGIC_OUTS1
CLBLM_R_X3Y311.CLBLM_M_C5.CLBLM_IMUX31

CLBLM_R_X3Y311.CLBLM_LOGIC_OUTS18.CLBLM_L_CMUX
INT_R_X3Y311.NL1BEG_N3.LOGIC_OUTS18
INT_R_X3Y311.IMUX38.NL1BEG_N3
CLBLM_R_X3Y311.CLBLM_M_D3.CLBLM_IMUX38

CLBLM_R_X3Y312.CLBLM_M_COUT_N.CLBLM_M_COUT

CLBLM_R_X3Y312.CLBLM_LOGIC_OUTS21.CLBLM_M_BMUX
INT_R_X3Y312.BYP7.BYP_ALT7
INT_R_X3Y312.BYP_ALT7.LOGIC_OUTS21
CLBLM_R_X3Y312.CLBLM_L_DX.CLBLM_BYP7

INT_R_X3Y312.BYP_ALT5.LOGIC_OUTS23
CLBLM_R_X3Y312.CLBLM_LOGIC_OUTS23.CLBLM_M_DMUX
INT_R_X3Y312.BYP5.BYP_ALT5
CLBLM_R_X3Y312.CLBLM_L_BX.CLBLM_BYP5

INT_R_X3Y312.IMUX1.LOGIC_OUTS4
CLBLM_R_X3Y312.CLBLM_M_A3.CLBLM_IMUX1
CLBLM_R_X3Y312.CLBLM_LOGIC_OUTS4.CLBLM_M_AQ

CLBLM_R_X3Y312.CLBLM_LOGIC_OUTS19.CLBLM_L_DMUX
INT_R_X3Y312.IMUX18.LOGIC_OUTS19
CLBLM_R_X3Y312.CLBLM_M_B2.CLBLM_IMUX18

CLBLM_R_X3Y312.CLBLM_LOGIC_OUTS6.CLBLM_M_CQ
INT_R_X3Y312.IMUX29.LOGIC_OUTS6
CLBLM_R_X3Y312.CLBLM_M_C2.CLBLM_IMUX29

CLBLM_R_X3Y312.CLBLM_LOGIC_OUTS17.CLBLM_L_BMUX
INT_R_X3Y312.IMUX38.LOGIC_OUTS17
CLBLM_R_X3Y312.CLBLM_M_D3.CLBLM_IMUX38

CLBLM_R_X3Y313.CLBLM_M_COUT_N.CLBLM_M_COUT

CLBLM_R_X3Y313.CLBLM_LOGIC_OUTS20.CLBLM_M_AMUX
INT_R_X3Y314.FAN_BOUNCE4.FAN_ALT4
INT_R_X3Y313.BYP3.BYP_ALT3
CLBLM_R_X3Y313.CLBLM_M_CX.CLBLM_BYP3
INT_R_X3Y314.FAN_ALT4.NL1END1
INT_R_X3Y313.BYP_ALT3.FAN_BOUNCE_S3_4
INT_R_X3Y313.NL1BEG1.LOGIC_OUTS20

INT_R_X3Y313.SR1BEG_S0.LOGIC_OUTS21
CLBLM_R_X3Y313.CLBLM_LOGIC_OUTS21.CLBLM_M_BMUX
INT_R_X3Y313.BYP_ALT2.BYP_BOUNCE1
INT_R_X3Y313.BYP2.BYP_ALT2
CLBLM_R_X3Y313.CLBLM_L_CX.CLBLM_BYP2
INT_R_X3Y313.BYP_ALT1.SR1BEG_S0
INT_R_X3Y313.BYP_BOUNCE1.BYP_ALT1

CLBLM_R_X3Y313.CLBLM_LOGIC_OUTS22.CLBLM_M_CMUX
INT_R_X3Y313.NL1BEG_N3.LOGIC_OUTS22
INT_R_X3Y313.BYP_ALT6.NL1BEG_N3
CLBLM_R_X3Y313.CLBLM_M_DX.CLBLM_BYP6
INT_R_X3Y313.BYP6.BYP_ALT6

CLBLM_R_X3Y313.CLBLM_LOGIC_OUTS23.CLBLM_M_DMUX
INT_R_X3Y313.NL1BEG0.LOGIC_OUTS23
INT_R_X3Y313.BYP_ALT7.NL1END_S3_0
INT_R_X3Y313.BYP7.BYP_ALT7
CLBLM_R_X3Y313.CLBLM_L_DX.CLBLM_BYP7

CLBLM_R_X3Y313.CLBLM_LOGIC_OUTS6.CLBLM_M_CQ
INT_R_X3Y313.SR1BEG3.LOGIC_OUTS6
INT_R_X3Y313.IMUX8.SR1END_N3_3
CLBLM_R_X3Y313.CLBLM_M_A5.CLBLM_IMUX8

CLBLM_R_X3Y313.CLBLM_LOGIC_OUTS18.CLBLM_L_CMUX
INT_R_X3Y313.IMUX17.LOGIC_OUTS18
CLBLM_R_X3Y313.CLBLM_M_B3.CLBLM_IMUX17

CLBLM_R_X3Y313.CLBLM_LOGIC_OUTS7.CLBLM_M_DQ
INT_R_X3Y313.IMUX22.LOGIC_OUTS7
CLBLM_R_X3Y313.CLBLM_M_C3.CLBLM_IMUX22

INT_R_X3Y313.BYP_ALT4.LOGIC_OUTS19
CLBLM_R_X3Y313.CLBLM_LOGIC_OUTS19.CLBLM_L_DMUX
INT_R_X3Y313.BYP_BOUNCE4.BYP_ALT4
INT_R_X3Y313.IMUX38.BYP_BOUNCE4
CLBLM_R_X3Y313.CLBLM_M_D3.CLBLM_IMUX38

CLBLM_R_X3Y314.CLBLM_M_COUT_N.CLBLM_M_COUT

CLBLM_R_X3Y314.CLBLM_LOGIC_OUTS20.CLBLM_M_AMUX
INT_R_X3Y314.BYP_ALT2.LOGIC_OUTS20
INT_R_X3Y314.BYP_BOUNCE2.BYP_ALT2
INT_R_X3Y314.BYP7.BYP_ALT7
CLBLM_R_X3Y314.CLBLM_L_DX.CLBLM_BYP7
INT_R_X3Y314.BYP_ALT7.BYP_BOUNCE2

INT_R_X3Y314.BYP_ALT0.LOGIC_OUTS22
INT_R_X3Y314.BYP_BOUNCE0.BYP_ALT0
CLBLM_R_X3Y314.CLBLM_LOGIC_OUTS22.CLBLM_M_CMUX
INT_R_X3Y314.BYP5.BYP_ALT5
CLBLM_R_X3Y314.CLBLM_L_BX.CLBLM_BYP5
INT_R_X3Y314.BYP_ALT5.BYP_BOUNCE0

CLBLM_R_X3Y314.CLBLM_LOGIC_OUTS3.CLBLM_L_DQ
INT_R_X3Y314.IMUX7.LOGIC_OUTS3
CLBLM_R_X3Y314.CLBLM_M_A1.CLBLM_IMUX7

CLBLM_R_X3Y314.CLBLM_LOGIC_OUTS5.CLBLM_M_BQ
INT_R_X3Y314.IMUX18.LOGIC_OUTS5
CLBLM_R_X3Y314.CLBLM_M_B2.CLBLM_IMUX18

INT_R_X3Y314.IMUX22.LOGIC_OUTS17
CLBLM_R_X3Y314.CLBLM_LOGIC_OUTS17.CLBLM_L_BMUX
CLBLM_R_X3Y314.CLBLM_M_C3.CLBLM_IMUX22

CLBLM_R_X3Y314.CLBLM_LOGIC_OUTS7.CLBLM_M_DQ
INT_R_X3Y314.IMUX38.LOGIC_OUTS7
CLBLM_R_X3Y314.CLBLM_M_D3.CLBLM_IMUX38

CLBLM_R_X3Y315.CLBLM_M_COUT_N.CLBLM_M_COUT

CLBLM_R_X3Y315.CLBLM_LOGIC_OUTS20.CLBLM_M_AMUX
INT_R_X3Y315.BYP_ALT2.LOGIC_OUTS20
INT_R_X3Y315.BYP2.BYP_ALT2
CLBLM_R_X3Y315.CLBLM_L_CX.CLBLM_BYP2

CLBLM_R_X3Y315.CLBLM_LOGIC_OUTS21.CLBLM_M_BMUX
INT_R_X3Y315.FAN_ALT3.LOGIC_OUTS21
INT_R_X3Y315.BYP_ALT3.FAN_BOUNCE3
INT_R_X3Y315.BYP3.BYP_ALT3
CLBLM_R_X3Y315.CLBLM_M_CX.CLBLM_BYP3
INT_R_X3Y315.FAN_BOUNCE3.FAN_ALT3

CLBLM_R_X3Y315.CLBLM_LOGIC_OUTS22.CLBLM_M_CMUX
INT_R_X3Y315.BYP_ALT0.LOGIC_OUTS22
INT_R_X3Y315.BYP0.BYP_ALT0
CLBLM_R_X3Y315.CLBLM_L_AX.CLBLM_BYP0

CLBLM_R_X3Y315.CLBLM_LOGIC_OUTS23.CLBLM_M_DMUX
INT_R_X3Y315.BYP_ALT5.LOGIC_OUTS23
INT_R_X3Y315.BYP5.BYP_ALT5
CLBLM_R_X3Y315.CLBLM_L_BX.CLBLM_BYP5

CLBLM_R_X3Y315.CLBLM_LOGIC_OUTS18.CLBLM_L_CMUX
INT_R_X3Y315.IMUX1.LOGIC_OUTS18
CLBLM_R_X3Y315.CLBLM_M_A3.CLBLM_IMUX1

CLBLM_R_X3Y315.CLBLM_LOGIC_OUTS6.CLBLM_M_CQ
INT_R_X3Y315.SR1BEG3.LOGIC_OUTS6
INT_R_X3Y315.IMUX24.SR1END_N3_3
CLBLM_R_X3Y315.CLBLM_M_B5.CLBLM_IMUX24

CLBLM_R_X3Y315.CLBLM_M_C1.CLBLM_IMUX32
CLBLM_R_X3Y315.CLBLM_LOGIC_OUTS0.CLBLM_L_AQ
INT_R_X3Y315.IMUX32.LOGIC_OUTS0

CLBLM_R_X3Y315.CLBLM_LOGIC_OUTS1.CLBLM_L_BQ
INT_R_X3Y315.NL1BEG0.LOGIC_OUTS1
INT_R_X3Y315.IMUX47.NL1END_S3_0
CLBLM_R_X3Y315.CLBLM_M_D5.CLBLM_IMUX47

CLBLM_R_X3Y316.CLBLM_LOGIC_OUTS20.CLBLM_M_AMUX
INT_R_X3Y316.SS6BEG2.LOGIC_OUTS20
INT_R_X3Y310.SS6BEG2.SS6END2
INT_R_X3Y304.NR1BEG2.SS6END2
INT_R_X3Y305.BYP_ALT2.NR1END2
INT_R_X3Y305.BYP2.BYP_ALT2
CLBLM_R_X3Y305.CLBLM_L_CX.CLBLM_BYP2

INT_R_X3Y316.SW2BEG3.LOGIC_OUTS21
INT_L_X2Y315.ER1BEG_S0.SW2END3
INT_R_X3Y316.BYP0.BYP_ALT0
CLBLM_R_X3Y316.CLBLM_L_AX.CLBLM_BYP0
CLBLM_R_X3Y316.CLBLM_LOGIC_OUTS21.CLBLM_M_BMUX
INT_R_X3Y316.BYP_ALT0.ER1END0

CLBLM_R_X3Y316.CLBLM_LOGIC_OUTS22.CLBLM_M_CMUX
INT_R_X3Y316.BYP_ALT6.NL1BEG_N3
INT_R_X3Y316.BYP6.BYP_ALT6
CLBLM_R_X3Y316.CLBLM_M_DX.CLBLM_BYP6
INT_R_X3Y316.NL1BEG_N3.LOGIC_OUTS22

CLBLM_R_X3Y316.CLBLM_LOGIC_OUTS23.CLBLM_M_DMUX
INT_R_X3Y316.BYP_ALT5.LOGIC_OUTS23
INT_R_X3Y316.BYP5.BYP_ALT5
CLBLM_R_X3Y316.CLBLM_L_BX.CLBLM_BYP5

INT_R_X3Y311.NE6BEG2.NN6END2
INT_R_X3Y316.IMUX2.WL1END0
CLBLM_R_X3Y305.CLBLM_L_DX.CLBLM_BYP7
INT_R_X3Y306.FAN_BOUNCE4.FAN_ALT4
INT_R_X3Y305.NN6BEG2.LOGIC_OUTS2
INT_R_X5Y315.NW2BEG2.NE6END2
INT_R_X3Y306.FAN_ALT4.NL1END1
INT_R_X3Y305.BYP_ALT7.FAN_BOUNCE_S3_4
INT_L_X4Y316.WL1BEG0.NW2END2
INT_R_X3Y305.BYP7.BYP_ALT7
INT_R_X3Y305.NL1BEG1.LOGIC_OUTS2
CLBLM_R_X3Y305.CLBLM_LOGIC_OUTS2.CLBLM_L_CQ
CLBLM_R_X3Y316.CLBLM_M_A2.CLBLM_IMUX2

CLBLM_R_X3Y316.CLBLM_LOGIC_OUTS16.CLBLM_L_AMUX
INT_R_X3Y316.SR1BEG3.LOGIC_OUTS16
INT_R_X3Y316.IMUX24.SR1END_N3_3
CLBLM_R_X3Y316.CLBLM_M_B5.CLBLM_IMUX24

CLBLM_R_X3Y316.CLBLM_LOGIC_OUTS7.CLBLM_M_DQ
INT_R_X3Y316.IMUX22.LOGIC_OUTS7
CLBLM_R_X3Y316.CLBLM_M_C3.CLBLM_IMUX22

CLBLM_R_X3Y316.CLBLM_LOGIC_OUTS1.CLBLM_L_BQ
INT_R_X3Y316.NL1BEG0.LOGIC_OUTS1
INT_R_X3Y316.IMUX47.NL1END_S3_0
CLBLM_R_X3Y316.CLBLM_M_D5.CLBLM_IMUX47

BRAM_L_X6Y290.BRAM_FIFO36_CLKARDCLKU.BRAM_CLK1_3
INT_L_X6Y293.CLK_L0.GCLK_L_B0
INT_R_X7Y293.GCLK_B0_WEST.GCLK_B0
BRAM_L_X74Y95.BRAM_FIFO36_CLKARDCLKU.BRAM_CLK1_3
INT_L_X74Y98.CLK_L1.GCLK_L_B0
BRAM_L_X74Y95.BRAM_FIFO36_CLKARDCLKL.BRAM_CLK0_3
INT_R_X75Y98.GCLK_B0_WEST.GCLK_B0
CLK_HROW_BOT_R_X121Y78.CLK_HROW_CK_BUFHCLK_R0.CLK_HROW_CK_HCLK_OUT_R0
CLK_HROW_BOT_R_X121Y78.BUFHCE.BUFHCE_X1Y0.IN_USE
CLK_HROW_BOT_R_X121Y78.BUFHCE.BUFHCE_X1Y0.ZINV_CE
CLK_HROW_BOT_R_X121Y78.CLK_HROW_CK_MUX_OUT_R0.CLK_HROW_R_CK_GCLK1
CLK_BUFG_REBUF_X121Y90.CLK_BUFG_REBUF_R_CK_GCLK1_BOT.CLK_BUFG_REBUF_R_CK_GCLK1_TOP
HCLK_R_X182Y78.HCLK_LEAF_CLK_B_TOP0.HCLK_CK_BUFHCLK0
CLK_BUFG_REBUF_X121Y142.CLK_BUFG_REBUF_R_CK_GCLK1_BOT.CLK_BUFG_REBUF_R_CK_GCLK1_TOP
INT_R_X3Y316.CLK1.GCLK_B0_EAST
INT_L_X6Y293.CLK_L1.GCLK_L_B0
INT_R_X3Y316.CLK0.GCLK_B0_EAST
INT_R_X3Y316.GCLK_B0_EAST.GCLK_B0
CLBLM_R_X3Y315.CLBLM_M_CLK.CLBLM_CLK1
INT_R_X3Y315.CLK1.GCLK_B0_EAST
HCLK_R_X22Y286.HCLK_LEAF_CLK_B_TOP0.HCLK_CK_BUFHCLK0
CLBLM_R_X3Y315.CLBLM_L_CLK.CLBLM_CLK0
INT_R_X3Y315.CLK0.GCLK_B0_EAST
CLBLM_R_X3Y314.CLBLM_M_CLK.CLBLM_CLK1
INT_R_X3Y314.CLK1.GCLK_B0_EAST
CLBLM_R_X3Y314.CLBLM_L_CLK.CLBLM_CLK0
INT_R_X3Y314.CLK0.GCLK_B0_EAST
INT_R_X3Y314.GCLK_B0_EAST.GCLK_B0
CLBLM_R_X3Y310.CLBLM_M_CLK.CLBLM_CLK1
INT_R_X3Y313.CLK1.GCLK_B0_EAST
HCLK_R_X12Y286.HCLK_LEAF_CLK_B_TOP0.HCLK_CK_BUFHCLK0
CLK_HROW_TOP_R_X121Y286.CLK_HROW_CK_MUX_OUT_L0.CLK_HROW_R_CK_GCLK1
INT_R_X3Y299.GCLK_B0_WEST.GCLK_B0
HCLK_R_X12Y338.HCLK_LEAF_CLK_B_BOT0.HCLK_CK_BUFHCLK0
INT_R_X3Y315.GCLK_B0_EAST.GCLK_B0
CLK_HROW_TOP_R_X121Y338.CLK_HROW_CK_MUX_OUT_L0.CLK_HROW_R_CK_GCLK1
INT_R_X3Y310.GCLK_B0_EAST.GCLK_B0
CLK_BUFG_REBUF_X121Y169.CLK_BUFG_REBUF_R_CK_GCLK1_BOT.CLK_BUFG_REBUF_R_CK_GCLK1_TOP
CLBLL_L_X2Y299.CLBLL_LL_CLK.CLBLL_CLK1
CLBLM_R_X3Y305.CLBLM_L_CLK.CLBLM_CLK0
INT_R_X3Y305.CLK0.GCLK_B0_EAST
CLK_HROW_TOP_R_X121Y286.CLK_HROW_CK_BUFHCLK_L0.CLK_HROW_CK_HCLK_OUT_L0
INT_R_X3Y310.CLK1.GCLK_B0_EAST
CLK_BUFG_REBUF_X121Y194.CLK_BUFG_REBUF_R_CK_GCLK1_BOT.CLK_BUFG_REBUF_R_CK_GCLK1_TOP
INT_R_X3Y311.CLK0.GCLK_B0_EAST
CLBLM_R_X3Y311.CLBLM_L_CLK.CLBLM_CLK0
CLK_BUFG_REBUF_X121Y273.CLK_BUFG_REBUF_R_CK_GCLK1_TOP.CLK_BUFG_REBUF_R_CK_GCLK1_BOT
INT_R_X3Y313.CLK0.GCLK_B0_EAST
CLBLM_R_X3Y316.CLBLM_M_CLK.CLBLM_CLK1
CLK_BUFG_REBUF_X121Y298.CLK_BUFG_REBUF_R_CK_GCLK1_TOP.CLK_BUFG_REBUF_R_CK_GCLK1_BOT
CLBLM_R_X3Y313.CLBLM_L_CLK.CLBLM_CLK0
INT_R_X3Y310.CLK0.GCLK_B0_EAST
INT_L_X2Y299.CLK_L1.GCLK_L_B0
CLK_BUFG_REBUF_X121Y221.CLK_BUFG_REBUF_R_CK_GCLK1_TOP.CLK_BUFG_REBUF_R_CK_GCLK1_BOT
CLK_HROW_TOP_R_X121Y286.BUFHCE.BUFHCE_X0Y0.IN_USE
CLK_HROW_TOP_R_X121Y286.BUFHCE.BUFHCE_X0Y0.ZINV_CE
CLK_BUFG_REBUF_X121Y325.CLK_BUFG_REBUF_R_CK_GCLK1_TOP.CLK_BUFG_REBUF_R_CK_GCLK1_BOT
CLK_BUFG_REBUF_X121Y246.CLK_BUFG_REBUF_R_CK_GCLK1_TOP.CLK_BUFG_REBUF_R_CK_GCLK1_BOT
CLK_HROW_TOP_R_X121Y338.BUFHCE.BUFHCE_X0Y0.IN_USE
CLK_HROW_TOP_R_X121Y338.BUFHCE.BUFHCE_X0Y0.ZINV_CE
CLBLM_R_X3Y310.CLBLM_L_CLK.CLBLM_CLK0
CLBLM_R_X3Y312.CLBLM_L_CLK.CLBLM_CLK0
INT_R_X3Y311.GCLK_B0_EAST.GCLK_B0
INT_R_X3Y311.CLK1.GCLK_B0_EAST
CLBLM_R_X3Y311.CLBLM_M_CLK.CLBLM_CLK1
BRAM_L_X6Y290.BRAM_FIFO36_CLKARDCLKL.BRAM_CLK0_3
CLK_BUFG_BOT_R_X121Y204.CLK_BUFG_CK_GCLK1.CLK_BUFG_BUFGCTRL1_O
CLK_BUFG_REBUF_X121Y117.CLK_BUFG_REBUF_R_CK_GCLK1_BOT.CLK_BUFG_REBUF_R_CK_GCLK1_TOP
CLK_HROW_TOP_R_X121Y338.CLK_HROW_CK_BUFHCLK_L0.CLK_HROW_CK_HCLK_OUT_L0
INT_R_X3Y312.GCLK_B0_EAST.GCLK_B0
INT_R_X3Y312.CLK1.GCLK_B0_EAST
INT_R_X3Y305.GCLK_B0_EAST.GCLK_B0
CLBLM_R_X3Y312.CLBLM_M_CLK.CLBLM_CLK1
INT_L_X74Y98.CLK_L0.GCLK_L_B0
CLBLM_R_X3Y313.CLBLM_M_CLK.CLBLM_CLK1
CLBLM_R_X3Y316.CLBLM_L_CLK.CLBLM_CLK0
INT_R_X3Y312.CLK0.GCLK_B0_EAST
INT_R_X3Y313.GCLK_B0_EAST.GCLK_B0

CLBLM_R_X3Y316.CLBLM_M_SR.CLBLM_CTRL1
INT_R_X3Y315.NR1BEG2.NR1END2
INT_R_X3Y316.CTRL0.NR1END2
CLBLM_R_X3Y316.CLBLM_L_SR.CLBLM_CTRL0
INT_R_X3Y315.CTRL1.NR1END2
INT_R_X3Y314.NR1BEG2.ER1END2
INT_R_X3Y314.CTRL1.ER1END2
CLBLM_R_X3Y314.CLBLM_M_SR.CLBLM_CTRL1
INT_L_X2Y314.ER1BEG2.SR1END1
INT_R_X3Y316.CTRL1.NR1END2
INT_R_X3Y314.CTRL0.ER1END2
CLBLM_R_X3Y314.CLBLM_L_SR.CLBLM_CTRL0
CLBLM_R_X3Y313.CLBLM_L_SR.CLBLM_CTRL0
INT_L_X4Y312.NR1BEG1.NN2END1
INT_L_X4Y313.WR1BEG2.NR1END1
INT_R_X3Y313.CTRL1.WR1END2
CLBLM_R_X3Y313.CLBLM_M_SR.CLBLM_CTRL1
INT_R_X3Y315.CTRL0.NR1END2
CLBLL_L_X2Y299.CLBLL_LL_SR.CLBLL_CTRL1
CLBLM_R_X3Y311.CLBLM_L_SR.CLBLM_CTRL0
LIOI3_SING_X0Y349.LIOI_I0.LIOI_IBUF0
INT_L_X2Y345.SS6BEG0.SE6END0
INT_L_X2Y299.CTRL_L1.GFAN1
LIOI3_SING_X0Y349.IDELAY_Y1.IDELAY_TYPE_FIXED
LIOI3_SING_X0Y349.ILOGIC_Y1.ZINV_D
INT_L_X2Y299.GFAN1.BYP_BOUNCE1
CLBLM_R_X3Y312.CLBLM_M_SR.CLBLM_CTRL1
INT_R_X3Y305.CTRL0.ER1END2
INT_R_X3Y312.CTRL0.WR1END2
INT_L_X2Y327.SS6BEG0.SS6END0
INT_L_X4Y310.NR1BEG1.NE2END1
INT_L_X2Y333.SS6BEG0.SS6END0
INT_L_X2Y309.ER1BEG1.SS6END0
INT_L_X2Y305.ER1BEG2.SR1END1
INT_L_X2Y307.SS6BEG0.SS2END0
INT_L_X2Y306.SR1BEG1.SL1END0
INT_L_X2Y307.SL1BEG0.SS2END0
INT_L_X2Y321.SS6BEG0.SS6END0
LIOI3_SING_X0Y349.IOI_LOGIC_OUTS18_1.IOI_ILOGIC0_O
INT_L_X2Y339.SS6BEG0.SS6END0
CLBLM_R_X3Y305.CLBLM_L_SR.CLBLM_CTRL0
INT_R_X3Y309.NE2BEG1.ER1END1
INT_L_X2Y309.SS2BEG0.SS6END0
INT_L_X4Y311.WR1BEG2.NR1END1
INT_L_X0Y349.SE6BEG0.LOGIC_OUTS_L18
INT_R_X3Y312.CTRL1.WR1END2
INT_L_X2Y315.SS6BEG0.SS6END0
INT_L_X2Y299.BYP_ALT1.SS2END0
INT_L_X2Y301.SS2BEG0.SS6END0
IO_INT_INTERFACE_L_X0Y349.INT_INTERFACE_LOGIC_OUTS_L18.INT_INTERFACE_LOGIC_OUTS_L_B18
INT_L_X4Y312.WR1BEG2.NN2END1
CLBLM_R_X3Y310.CLBLM_M_SR.CLBLM_CTRL1
CLBLM_R_X3Y312.CLBLM_L_SR.CLBLM_CTRL0
INT_R_X3Y310.CTRL1.WR1END2
INT_L_X4Y310.WR1BEG2.NE2END1
INT_L_X2Y299.BYP_BOUNCE1.BYP_ALT1
CLBLM_R_X3Y315.CLBLM_L_SR.CLBLM_CTRL0
CLBLM_R_X3Y310.CLBLM_L_SR.CLBLM_CTRL0
INT_R_X3Y310.CTRL0.WR1END2
INT_L_X2Y315.SR1BEG1.SS6END0
INT_R_X3Y313.CTRL0.WR1END2
CLBLM_R_X3Y311.CLBLM_M_SR.CLBLM_CTRL1
LIOI3_SING_X0Y349.LIOI_ILOGIC0_D.LIOI_I0
INT_R_X3Y311.CTRL1.WR1END2
INT_R_X3Y311.CTRL0.WR1END2
CLBLM_R_X3Y315.CLBLM_M_SR.CLBLM_CTRL1
INT_L_X4Y310.NN2BEG1.NE2END1

INT_L_X6Y293.IMUX_L12.ER1END1
BRAM_L_X6Y290.BRAM_FIFO36_ADDRARDADDRU5.BRAM_ADDRARDADDRU5
INT_R_X5Y293.SR1BEG_S0.SS2END3
INT_R_X3Y299.SE6BEG3.SS6END3
BRAM_L_X6Y290.BRAM_IMUX_ADDRARDADDRL5.BRAM_IMUX20_3
BRAM_L_X74Y95.BRAM_IMUX_ADDRARDADDRU5.BRAM_IMUX12_3
BRAM_L_X74Y95.BRAM_FIFO36_ADDRARDADDRU5.BRAM_ADDRARDADDRU5
BRAM_L_X6Y290.BRAM_ADDRARDADDRU5.BRAM_IMUX_ADDRARDADDRU5
INT_L_X6Y293.IMUX_L20.ER1END1
INT_L_X74Y98.IMUX_L12.ER1END1
INT_R_X3Y305.SS6BEG3.LOGIC_OUTS3
CLBLM_R_X3Y305.CLBLM_LOGIC_OUTS3.CLBLM_L_DQ
INT_R_X3Y299.LH12.SS6END3
INT_R_X15Y281.LV18.LV0
INT_R_X33Y191.LV18.LH0
INT_R_X71Y95.NE6BEG0.EE2END0
INT_R_X5Y293.ER1BEG1.SR1BEG_S0
BRAM_L_X74Y95.BRAM_ADDRARDADDRU5.BRAM_IMUX_ADDRARDADDRU5
INT_R_X15Y263.LV18.LV0
INT_R_X33Y119.LV18.LV0
INT_R_X61Y95.EE4BEG0.EE4END0
INT_R_X73Y99.SL1BEG0.NE6END0
INT_R_X73Y98.ER1BEG1.SL1END0
BRAM_L_X6Y290.BRAM_IMUX_ADDRARDADDRU5.BRAM_IMUX12_3
INT_L_X74Y98.IMUX_L20.ER1END1
BRAM_L_X6Y290.BRAM_ADDRARDADDRL5.BRAM_IMUX_ADDRARDADDRL5
INT_R_X15Y191.LH12.LV0
INT_R_X65Y95.EE4BEG0.EE4END0
BRAM_L_X74Y95.BRAM_IMUX_ADDRARDADDRL5.BRAM_IMUX20_3
INT_R_X15Y245.LV18.LV0
INT_R_X45Y95.EE4BEG0.EE4END0
BRAM_L_X74Y95.BRAM_FIFO36_ADDRARDADDRL5.BRAM_ADDRARDADDRL5
INT_R_X15Y299.LV18.LH0
INT_R_X53Y95.EE4BEG0.EE4END0
INT_R_X5Y295.SS2BEG3.SE6END3
INT_R_X69Y95.EE2BEG0.EE4END0
INT_R_X57Y95.EE4BEG0.EE4END0
INT_R_X49Y95.EE4BEG0.EE4END0
INT_R_X33Y95.EE4BEG0.SS6END0
INT_R_X41Y95.EE4BEG0.EE4END0
BRAM_L_X74Y95.BRAM_ADDRARDADDRL5.BRAM_IMUX_ADDRARDADDRL5
INT_R_X33Y101.SS6BEG0.LV0
INT_R_X33Y137.LV18.LV0
INT_R_X33Y155.LV18.LV0
INT_R_X33Y173.LV18.LV0
INT_R_X15Y209.LV18.LV0
BRAM_L_X6Y290.BRAM_FIFO36_ADDRARDADDRL5.BRAM_ADDRARDADDRL5
INT_R_X37Y95.EE4BEG0.EE4END0
INT_R_X15Y227.LV18.LV0

BRAM_L_X74Y95.BRAM_LOGIC_OUTS_B8_0.BRAM_FIFO36_DOADOL0
BRAM_INT_INTERFACE_L_X74Y95.INT_INTERFACE_LOGIC_OUTS_L8.INT_INTERFACE_LOGIC_OUTS_L_B8
INT_L_X78Y95.EE4BEG0.EE4END0
RIOI_X95Y95.RIOI_O1.RIOI_OLOGIC1_OQ
RIOI_X95Y95.IOI_OLOGIC1_D1.IOI_IMUX34_0
INT_L_X94Y95.ER1BEG1.EE4END0
RIOI_X95Y95.OLOGIC_Y1.OMUX.D1
RIOI_X95Y95.OLOGIC_Y1.OQUSED
RIOI_X95Y95.OLOGIC_Y1.OSERDES.DATA_RATE_TQ.BUF
INT_L_X82Y95.EE4BEG0.EE4END0
INT_R_X95Y95.IMUX34.ER1END1
INT_L_X90Y95.EE4BEG0.EE4END0
INT_L_X86Y95.EE4BEG0.EE4END0
INT_L_X74Y95.EE4BEG0.LOGIC_OUTS_L8

BRAM_INT_INTERFACE_L_X74Y97.INT_INTERFACE_LOGIC_OUTS_L15.INT_INTERFACE_LOGIC_OUTS_L_B15
INT_L_X74Y95.EE4BEG3.SS2END3
RIOI_X95Y95.RIOI_O0.RIOI_OLOGIC0_OQ
RIOI_X95Y95.OLOGIC_Y0.OMUX.D1
RIOI_X95Y95.OLOGIC_Y0.OQUSED
RIOI_X95Y95.OLOGIC_Y0.OSERDES.DATA_RATE_TQ.BUF
RIOI_X95Y95.IOI_OLOGIC0_D1.IOI_IMUX34_1
BRAM_L_X74Y95.BRAM_LOGIC_OUTS_B15_2.BRAM_FIFO36_DOADOU0
INT_R_X95Y96.IMUX34.WR1END1
INT_R_X95Y96.ER1BEG1.ER1END0
INT_L_X74Y97.SS2BEG3.LOGIC_OUTS_L15
INT_L_X94Y95.ER1BEG_S0.EE4END3
INT_L_X90Y95.EE4BEG3.LH0
INT_L_X78Y95.LH12.EE4END3

BRAM_INT_INTERFACE_L_X74Y95.INT_INTERFACE_LOGIC_OUTS_L13.INT_INTERFACE_LOGIC_OUTS_L_B13
INT_L_X86Y93.EE4BEG1.EE4END1
RIOI_TBYTESRC_X95Y93.OLOGIC_Y1.OMUX.D1
RIOI_TBYTESRC_X95Y93.OLOGIC_Y1.OQUSED
RIOI_TBYTESRC_X95Y93.OLOGIC_Y1.OSERDES.DATA_RATE_TQ.BUF
RIOI_TBYTESRC_X95Y93.RIOI_O1.RIOI_OLOGIC1_OQ
BRAM_L_X74Y95.BRAM_LOGIC_OUTS_B13_0.BRAM_FIFO36_DOADOL1
RIOI_TBYTESRC_X95Y93.IOI_OLOGIC1_D1.IOI_IMUX34_0
INT_L_X78Y93.EE4BEG1.EE4END1
INT_L_X74Y95.SS2BEG1.LOGIC_OUTS_L13
INT_R_X95Y93.IMUX34.WL1END1
INT_L_X82Y93.EE4BEG1.EE4END1
INT_L_X74Y93.EE4BEG1.SS2END1
INT_R_X95Y93.EL1BEG1.ER1END2
INT_L_X94Y93.ER1BEG2.EE4END1
INT_L_X90Y93.EE4BEG1.EE4END1

BRAM_L_X74Y95.BRAM_LOGIC_OUTS_B8_3.BRAM_FIFO36_DOADOU1
BRAM_INT_INTERFACE_L_X74Y98.INT_INTERFACE_LOGIC_OUTS_L8.INT_INTERFACE_LOGIC_OUTS_L_B8
INT_L_X74Y98.SE6BEG0.LOGIC_OUTS_L8
INT_L_X84Y94.EE4BEG0.EE4END0
RIOI_TBYTESRC_X95Y93.OLOGIC_Y0.OMUX.D1
RIOI_TBYTESRC_X95Y93.OLOGIC_Y0.OQUSED
RIOI_TBYTESRC_X95Y93.OLOGIC_Y0.OSERDES.DATA_RATE_TQ.BUF
INT_L_X92Y94.EE2BEG0.EE4END0
INT_R_X95Y94.IMUX34.ER1END1
INT_L_X94Y94.ER1BEG1.EE2END0
RIOI_TBYTESRC_X95Y93.IOI_OLOGIC0_D1.IOI_IMUX34_1
RIOI_TBYTESRC_X95Y93.RIOI_O0.RIOI_OLOGIC0_OQ
INT_L_X80Y94.EE4BEG0.EE4END0
INT_L_X76Y94.EE4BEG0.SE6END0
INT_L_X88Y94.EE4BEG0.EE4END0

BRAM_INT_INTERFACE_L_X74Y95.INT_INTERFACE_LOGIC_OUTS_L10.INT_INTERFACE_LOGIC_OUTS_L_B10
INT_L_X74Y95.SW6BEG2.LOGIC_OUTS_L10
INT_L_X72Y91.LVB_L12.SW6END2
INT_R_X13Y50.WW4BEG3.WW4END3
INT_R_X29Y50.WW4BEG3.WW4END3
INT_R_X49Y50.WW4BEG3.WW4END3
INT_R_X5Y50.WW4BEG3.WW4END3
INT_R_X53Y50.WW4BEG3.WW4END3
BRAM_L_X74Y95.BRAM_LOGIC_OUTS_B10_0.BRAM_FIFO36_DOADOL2
INT_R_X21Y50.WW4BEG3.WW4END3
LIOI3_SING_X0Y50.OLOGIC_Y0.OMUX.D1
LIOI3_SING_X0Y50.OLOGIC_Y0.OQUSED
LIOI3_SING_X0Y50.OLOGIC_Y0.OSERDES.DATA_RATE_TQ.BUF
INT_R_X65Y50.WW4BEG3.WW4END3
INT_L_X72Y55.SW6BEG2.LVB_L0
LIOI3_SING_X0Y50.LIOI_O0.LIOI_OLOGIC0_OQ
INT_R_X17Y50.WW4BEG3.WW4END3
INT_R_X41Y50.WW4BEG3.WW4END3
INT_L_X0Y50.IMUX_L34.WL1END1
INT_R_X9Y50.WW4BEG3.WW4END3
INT_R_X25Y50.WW4BEG3.WW4END3
INT_L_X72Y79.LVB_L12.LVB_L0
INT_R_X33Y50.WW4BEG3.WW4END3
INT_R_X1Y50.WL1BEG1.WW4END3
INT_R_X37Y50.WW4BEG3.WW4END3
INT_R_X45Y50.WW4BEG3.WW4END3
INT_L_X70Y51.SW2BEG2.SW6END2
INT_R_X57Y50.WW4BEG3.WW4END3
INT_R_X61Y50.WW4BEG3.WW4END3
INT_R_X69Y50.WW4BEG3.SW2END2
INT_L_X72Y67.LVB_L12.LVB_L0

INT_L_X68Y110.NW6BEG1.NW6END1
INT_L_X52Y142.NW6BEG1.NW6END1
INT_L_X60Y126.NW6BEG1.NW6END1
INT_L_X48Y150.NW6BEG1.NW6END1
INT_L_X46Y154.NW6BEG1.NW6END1
INT_L_X42Y162.NW6BEG1.NW6END1
INT_L_X40Y166.NW6BEG1.NW6END1
INT_L_X38Y176.NW6BEG1.NN6END1
INT_L_X36Y180.NW6BEG1.NW6END1
INT_L_X30Y192.NW6BEG1.NW6END1
INT_L_X54Y138.NW6BEG1.NW6END1
INT_L_X32Y188.NW6BEG1.NW6END1
INT_L_X0Y272.NN6BEG1.NN6END1
INT_L_X0Y278.NN6BEG1.NN6END1
INT_L_X64Y118.NW6BEG1.NW6END1
INT_L_X38Y170.NN6BEG1.NW6END1
INT_L_X28Y196.NW6BEG1.NW6END1
INT_L_X0Y284.NN6BEG1.NN6END1
INT_L_X34Y184.NW6BEG1.NW6END1
INT_L_X62Y122.NW6BEG1.NW6END1
INT_L_X50Y146.NW6BEG1.NW6END1
INT_L_X0Y298.NR1BEG1.NN2END1
INT_L_X58Y130.NW6BEG1.NW6END1
LIOI3_SING_X0Y299.OLOGIC_Y1.OMUX.D1
LIOI3_SING_X0Y299.OLOGIC_Y1.OQUSED
LIOI3_SING_X0Y299.OLOGIC_Y1.OSERDES.DATA_RATE_TQ.BUF
INT_L_X74Y98.NW6BEG1.LOGIC_OUTS_L13
INT_L_X0Y299.IMUX_L34.NR1END1
INT_L_X8Y242.WW4BEG1.NW6END1
INT_L_X0Y296.NN2BEG1.NN6END1
INT_L_X24Y204.NW6BEG1.NW6END1
INT_L_X70Y106.NW6BEG1.NW6END1
INT_L_X66Y114.NW6BEG1.NW6END1
INT_L_X56Y134.NW6BEG1.NW6END1
INT_L_X0Y290.NN6BEG1.NN6END1
INT_L_X0Y266.NN6BEG1.NN6END1
INT_L_X72Y102.NW6BEG1.NW6END1
INT_L_X18Y216.NW6BEG1.NW6END1
INT_L_X16Y226.NW6BEG1.NN6END1
LIOI3_SING_X0Y299.LIOI_O0.LIOI_OLOGIC0_OQ
INT_L_X0Y260.NN6BEG1.NN6END1
INT_L_X0Y254.NN6BEG1.NN6END1
INT_L_X44Y158.NW6BEG1.NW6END1
INT_L_X0Y248.NN6BEG1.NN6END1
INT_L_X0Y242.NN6BEG1.WW4END1
INT_L_X4Y242.WW4BEG1.WW4END1
BRAM_L_X74Y95.BRAM_LOGIC_OUTS_B13_3.BRAM_FIFO36_DOADOU2
INT_L_X16Y220.NN6BEG1.NW6END1
BRAM_INT_INTERFACE_L_X74Y98.INT_INTERFACE_LOGIC_OUTS_L13.INT_INTERFACE_LOGIC_OUTS_L_B13
INT_L_X10Y238.NW6BEG1.NW6END1
INT_L_X12Y234.NW6BEG1.NW6END1
INT_L_X26Y200.NW6BEG1.NW6END1
INT_L_X14Y230.NW6BEG1.NW6END1
INT_L_X20Y212.NW6BEG1.NW6END1
INT_L_X22Y208.NW6BEG1.NW6END1

BRAM_INT_INTERFACE_L_X74Y95.INT_INTERFACE_LOGIC_OUTS_L15.INT_INTERFACE_LOGIC_OUTS_L_B15
INT_L_X74Y95.NW6BEG3.LOGIC_OUTS_L15
INT_L_X72Y111.LVB_L0.LVB_L12
INT_L_X72Y99.LVB_L0.NW6END3
INT_L_X72Y135.LVB_L0.LVB_L12
INT_L_X72Y147.LVB_L0.LVB_L12
INT_L_X72Y159.LVB_L0.LVB_L12
INT_L_X72Y171.LVB_L0.LVB_L12
INT_L_X72Y207.LVB_L0.LVB_L12
INT_L_X72Y219.LVB_L0.LVB_L12
BRAM_L_X74Y95.BRAM_LOGIC_OUTS_B15_0.BRAM_FIFO36_DOADOL3
INT_L_X0Y250.IMUX_L34.EE2END1
INT_R_X35Y250.WW4BEG2.WW4END2
INT_L_X72Y249.NW2BEG2.NN6END2
INT_L_X72Y195.LVB_L0.LVB_L12
INT_R_X43Y250.WW4BEG2.WW4END2
INT_R_X3Y250.WW2BEG1.WW4END2
INT_L_X72Y183.LVB_L0.LVB_L12
INT_R_X67Y250.WW4BEG2.WW4END2
INT_R_X59Y250.WW4BEG2.WW4END2
LIOI3_SING_X0Y250.OLOGIC_Y0.OMUX.D1
LIOI3_SING_X0Y250.OLOGIC_Y0.OQUSED
LIOI3_SING_X0Y250.OLOGIC_Y0.OSERDES.DATA_RATE_TQ.BUF
INT_R_X7Y250.WW4BEG2.WW4END2
LIOI3_SING_X0Y250.LIOI_O0.LIOI_OLOGIC0_OQ
INT_R_X1Y250.WW2BEG1.WW2END1
INT_R_X11Y250.WW4BEG2.WW4END2
INT_L_X72Y243.NN6BEG2.LVB_L12
INT_L_X72Y123.LVB_L0.LVB_L12
INT_R_X23Y250.WW4BEG2.WW4END2
INT_R_X63Y250.WW4BEG2.WW4END2
INT_R_X27Y250.WW4BEG2.WW4END2
INT_R_X31Y250.WW4BEG2.WW4END2
INT_R_X15Y250.WW4BEG2.WW4END2
INT_R_X39Y250.WW4BEG2.WW4END2
INT_R_X47Y250.WW4BEG2.WW4END2
INT_R_X51Y250.WW4BEG2.WW4END2
INT_R_X55Y250.WW4BEG2.WW4END2
INT_R_X19Y250.WW4BEG2.WW4END2
INT_R_X71Y250.WW4BEG2.NW2END2
INT_L_X72Y231.LVB_L0.LVB_L12

BRAM_L_X6Y290.BRAM_LOGIC_OUTS_B8_0.BRAM_FIFO36_DOADOL0
BRAM_INT_INTERFACE_L_X6Y290.INT_INTERFACE_LOGIC_OUTS_L8.INT_INTERFACE_LOGIC_OUTS_L_B8
LIOI3_SING_X0Y300.OLOGIC_Y0.OMUX.D1
LIOI3_SING_X0Y300.OLOGIC_Y0.OQUSED
LIOI3_SING_X0Y300.OLOGIC_Y0.OSERDES.DATA_RATE_TQ.BUF
LIOI3_SING_X0Y300.LIOI_O0.LIOI_OLOGIC0_OQ
INT_L_X0Y300.IMUX_L34.EE2END1
INT_R_X1Y299.NN2BEG1.EE4END1
INT_R_X1Y300.WW2BEG1.SR1END1
INT_L_X2Y290.LV_L0.WW4END0
INT_R_X1Y301.SR1BEG1.NN2END1
INT_L_X2Y299.WW4BEG1.LV_L9
INT_L_X6Y290.WW4BEG0.LOGIC_OUTS_L8

RIOI_X95Y75.RIOI_I0.RIOI_IBUF0
RIOI_X95Y75.RIOI_ILOGIC0_D.RIOI_I0
HCLK_CMT_L_X228Y78.HCLK_CMT_CK_IN12.HCLK_CMT_CCIO0
CLK_HROW_BOT_R_X121Y78.CLK_HROW_BOT_R_CK_BUFG_CASCO2.CLK_HROW_CK_IN_R12
CLK_HROW_BOT_R_X121Y182.CLK_HROW_BOT_R_CK_BUFG_CASCO2.CLK_HROW_BOT_R_CK_BUFG_CASCIN2
CLK_HROW_BOT_R_X121Y130.CLK_HROW_BOT_R_CK_BUFG_CASCO2.CLK_HROW_BOT_R_CK_BUFG_CASCIN2
CLK_BUFG_BOT_R_X121Y204.CLK_BUFG_BUFGCTRL1_I0.CLK_BUFG_BOT_R_CK_MUXED2
RIOI_X95Y75.ILOGIC_Y0.ZINV_D
RIOI_X95Y75.RIOI_I2GCLK_TOP0.IOI_ILOGIC0_O

CLBLM_R_X3Y310.CLBLM_M_C1.CLBLM_IMUX32
CLBLM_R_X3Y311.CLBLM_M_D2.CLBLM_IMUX45
INT_R_X3Y311.GFAN1.GND_WIRE
CLBLM_R_X3Y311.CLBLM_M_A1.CLBLM_IMUX7
CLBLM_R_X3Y312.CLBLM_M_C3.CLBLM_IMUX22
INT_R_X3Y312.IMUX15.GFAN1
CLBLM_R_X3Y312.CLBLM_M_B1.CLBLM_IMUX15
INT_R_X3Y312.IMUX7.GFAN1
CLBLM_R_X3Y313.CLBLM_M_D2.CLBLM_IMUX45
CLBLM_R_X3Y313.CLBLM_M_C2.CLBLM_IMUX29
CLBLM_R_X3Y313.CLBLM_M_B1.CLBLM_IMUX15
INT_R_X3Y314.IMUX40.GFAN0
CLBLM_R_X3Y314.CLBLM_M_D1.CLBLM_IMUX40
INT_R_X3Y314.IMUX17.GFAN0
CLBLM_R_X3Y314.CLBLM_M_B3.CLBLM_IMUX17
INT_R_X3Y314.GFAN0.GND_WIRE
INT_R_X3Y315.IMUX45.GFAN1
CLBLM_R_X3Y315.CLBLM_M_D2.CLBLM_IMUX45
INT_R_X3Y315.IMUX29.GFAN1
CLBLM_R_X3Y315.CLBLM_M_C2.CLBLM_IMUX29
INT_R_X3Y315.IMUX15.GFAN1
CLBLM_R_X3Y315.CLBLM_M_B1.CLBLM_IMUX15
INT_R_X3Y315.IMUX7.GFAN1
CLBLM_R_X3Y315.CLBLM_M_A1.CLBLM_IMUX7
INT_R_X3Y316.IMUX45.GFAN1
CLBLM_R_X3Y316.CLBLM_M_D2.CLBLM_IMUX45
INT_R_X3Y316.IMUX29.GFAN1
CLBLM_R_X3Y316.CLBLM_M_C2.CLBLM_IMUX29
CLBLM_R_X3Y316.CLBLM_M_B1.CLBLM_IMUX15
CLBLM_R_X3Y312.CLBLM_M_A1.CLBLM_IMUX7
INT_R_X3Y316.GFAN1.GND_WIRE
CLBLM_R_X3Y316.CLBLM_M_A1.CLBLM_IMUX7
INT_L_X6Y292.IMUX_L46.GFAN1
BRAM_L_X6Y290.BRAM_FIFO36_WEBWEU7.BRAM_IMUX46_2
INT_R_X3Y310.IMUX32.GFAN0
INT_L_X6Y292.IMUX_L30.GFAN1
BRAM_L_X6Y290.BRAM_FIFO36_WEBWEU6.BRAM_IMUX30_2
BRAM_L_X6Y290.BRAM_FIFO36_WEBWEU5.BRAM_IMUX14_2
INT_L_X6Y292.FAN_L1.FAN_ALT1
INT_L_X6Y292.BYP_ALT6.GFAN1
INT_L_X6Y292.BYP_L6.BYP_ALT6
INT_L_X6Y292.IMUX_L22.GFAN1
BRAM_L_X6Y290.BRAM_FIFO36_WEBWEL5.BRAM_IMUX22_2
INT_L_X6Y292.IMUX_L6.GFAN1
BRAM_L_X6Y290.BRAM_FIFO36_WEBWEL4.BRAM_IMUX6_2
INT_L_X74Y97.IMUX_L46.GFAN1
INT_L_X74Y97.IMUX_L30.GFAN1
INT_L_X74Y97.IMUX_L14.GFAN1
BRAM_L_X74Y95.BRAM_FIFO36_WEBWEU5.BRAM_IMUX14_2
INT_L_X74Y97.BYP_ALT6.GFAN1
INT_L_X74Y97.BYP_L6.BYP_ALT6
INT_R_X3Y313.IMUX15.GFAN1
INT_L_X74Y97.IMUX_L38.GFAN1
BRAM_L_X6Y290.BRAM_FIFO36_WEBWEL6.BRAM_IMUX38_2
BRAM_L_X74Y95.BRAM_FIFO36_WEBWEL6.BRAM_IMUX38_2
INT_L_X74Y97.IMUX_L22.GFAN1
INT_L_X6Y292.IMUX_L25.GFAN0
BRAM_L_X6Y290.BRAM_FIFO36_WEAU3.BRAM_IMUX25_2
BRAM_L_X74Y95.BRAM_FIFO36_WEBWEL4.BRAM_IMUX6_2
INT_L_X6Y292.IMUX_L33.GFAN0
BRAM_L_X6Y290.BRAM_ADDRARDADDRU4.BRAM_IMUX_ADDRARDADDRU4
BRAM_L_X6Y290.BRAM_FIFO36_ADDRARDADDRU4.BRAM_ADDRARDADDRU4
INT_L_X6Y291.IMUX_L21.GFAN1
BRAM_L_X6Y290.BRAM_IMUX_ADDRARDADDRL4.BRAM_IMUX21_1
BRAM_L_X6Y290.BRAM_FIFO36_ADDRARDADDRL4.BRAM_ADDRARDADDRL4
BRAM_L_X6Y290.BRAM_FIFO36_WEAL3.BRAM_IMUX33_2
BRAM_L_X6Y290.BRAM_FIFO36_WEAU2.BRAM_IMUX9_2
BRAM_L_X74Y95.BRAM_FIFO36_WEBWEU6.BRAM_IMUX30_2
BRAM_L_X6Y290.BRAM_FIFO36_WEAL2.BRAM_IMUX17_2
INT_L_X6Y293.IMUX_L10.GFAN0
BRAM_L_X6Y290.BRAM_ADDRARDADDRU3.BRAM_IMUX_ADDRARDADDRU3
BRAM_L_X6Y290.BRAM_FIFO36_ADDRARDADDRU3.BRAM_ADDRARDADDRU3
INT_L_X6Y293.IMUX_L18.GFAN0
BRAM_L_X6Y290.BRAM_IMUX_ADDRARDADDRL3.BRAM_IMUX18_3
BRAM_L_X6Y290.BRAM_FIFO36_ADDRARDADDRL3.BRAM_ADDRARDADDRL3
INT_L_X6Y293.IMUX_L13.GFAN1
BRAM_L_X6Y290.BRAM_IMUX_ADDRARDADDRU12.BRAM_IMUX13_3
BRAM_L_X6Y290.BRAM_ADDRARDADDRU11.BRAM_IMUX_ADDRARDADDRU11
BRAM_L_X6Y290.BRAM_FIFO36_ADDRARDADDRU11.BRAM_ADDRARDADDRU11
BRAM_L_X6Y290.BRAM_IMUX_ADDRARDADDRL11.BRAM_IMUX22_1
BRAM_L_X6Y290.BRAM_ADDRARDADDRL11.BRAM_IMUX_ADDRARDADDRL11
INT_L_X6Y292.IMUX_L12.GFAN1
BRAM_L_X6Y290.BRAM_IMUX_ADDRARDADDRU10.BRAM_IMUX12_2
BRAM_L_X6Y290.BRAM_FIFO36_ADDRARDADDRU10.BRAM_ADDRARDADDRU10
BRAM_L_X6Y290.BRAM_IMUX_ADDRARDADDRL12.BRAM_IMUX21_3
BRAM_L_X6Y290.BRAM_FIFO36_ADDRARDADDRL12.BRAM_ADDRARDADDRL12
BRAM_L_X6Y290.BRAM_IMUX_ADDRARDADDRL10.BRAM_IMUX20_2
BRAM_L_X6Y290.BRAM_FIFO36_ADDRARDADDRL10.BRAM_ADDRARDADDRL10
INT_L_X6Y292.IMUX_L24.GFAN0
BRAM_L_X6Y290.BRAM_FIFO36_WEAU1.BRAM_IMUX24_2
INT_R_X3Y311.IMUX29.GFAN1
INT_L_X6Y292.IMUX_L32.GFAN0
BRAM_L_X6Y290.BRAM_FIFO36_WEAL1.BRAM_IMUX32_2
INT_L_X6Y291.IMUX_L11.GFAN0
BRAM_L_X74Y95.BRAM_FIFO36_WEBWEU4.BRAM_FAN1_2
BRAM_L_X6Y290.BRAM_IMUX_ADDRARDADDRU2.BRAM_IMUX11_1
BRAM_L_X6Y290.BRAM_FIFO36_ADDRARDADDRU2.BRAM_ADDRARDADDRU2
INT_L_X6Y291.IMUX_L19.GFAN0
INT_R_X3Y313.GFAN1.GND_WIRE
BRAM_L_X6Y290.BRAM_ADDRARDADDRL2.BRAM_IMUX_ADDRARDADDRL2
BRAM_L_X6Y290.BRAM_ADDRARDADDRU9.BRAM_IMUX_ADDRARDADDRU9
INT_L_X6Y293.IMUX_L19.GFAN0
BRAM_L_X6Y290.BRAM_FIFO36_ADDRARDADDRL9.BRAM_ADDRARDADDRL9
BRAM_L_X6Y290.BRAM_FIFO36_WEAU0.BRAM_IMUX8_2
INT_L_X6Y292.IMUX_L16.GFAN0
INT_R_X3Y310.IMUX18.GFAN0
BRAM_L_X6Y290.BRAM_FIFO36_WEAL0.BRAM_IMUX16_2
BRAM_L_X74Y95.BRAM_FIFO36_ADDRARDADDRL10.BRAM_ADDRARDADDRL10
BRAM_L_X74Y95.BRAM_FIFO36_ADDRARDADDRL13.BRAM_ADDRARDADDRL13
BRAM_L_X74Y95.BRAM_FIFO36_ADDRARDADDRL14.BRAM_ADDRARDADDRL14
CLBLM_R_X3Y313.CLBLM_M_A1.CLBLM_IMUX7
INT_R_X3Y311.IMUX45.GFAN1
INT_L_X74Y97.GFAN1.GND_WIRE
BRAM_L_X74Y95.BRAM_IMUX_ADDRARDADDRU6.BRAM_IMUX8_3
BRAM_L_X74Y95.BRAM_FIFO36_WEAU1.BRAM_IMUX24_2
INT_L_X74Y96.IMUX_L12.GFAN1
BRAM_L_X6Y290.BRAM_IMUX_ADDRARDADDRU6.BRAM_IMUX8_3
INT_R_X3Y313.IMUX45.GFAN1
BRAM_L_X6Y290.BRAM_FIFO36_ADDRARDADDRL7.BRAM_ADDRARDADDRL7
INT_L_X74Y97.FAN_L1.FAN_ALT1
BRAM_L_X74Y95.BRAM_FIFO36_WEAL1.BRAM_IMUX32_2
BRAM_L_X74Y95.BRAM_FIFO36_ADDRARDADDRL7.BRAM_ADDRARDADDRL7
CLBLM_R_X3Y311.CLBLM_M_B1.CLBLM_IMUX15
INT_L_X74Y98.IMUX_L13.GFAN1
INT_L_X74Y98.IMUX_L19.GFAN0
INT_L_X74Y97.IMUX_L20.GFAN1
BRAM_L_X74Y95.BRAM_FIFO36_ADDRARDADDRU4.BRAM_ADDRARDADDRU4
BRAM_L_X74Y95.BRAM_ADDRARDADDRL6.BRAM_IMUX_ADDRARDADDRL6
BRAM_L_X74Y95.BRAM_ADDRARDADDRL7.BRAM_IMUX_ADDRARDADDRL7
INT_L_X6Y292.IMUX_L17.GFAN0
BRAM_L_X74Y95.BRAM_FIFO36_WEAU0.BRAM_IMUX8_2
INT_L_X74Y96.IMUX_L10.GFAN0
BRAM_L_X74Y95.BRAM_FIFO36_ADDRARDADDRL9.BRAM_ADDRARDADDRL9
BRAM_L_X74Y95.BRAM_FIFO36_ADDRARDADDRU8.BRAM_ADDRARDADDRU8
BRAM_L_X6Y290.BRAM_FIFO36_WEBWEU4.BRAM_FAN1_2
BRAM_L_X6Y290.BRAM_IMUX_ADDRARDADDRU3.BRAM_IMUX10_3
INT_L_X6Y291.IMUX_L22.GFAN1
INT_L_X6Y291.IMUX_L10.GFAN0
BRAM_L_X6Y290.BRAM_FIFO36_ADDRARDADDRU14.BRAM_ADDRARDADDRU14
BRAM_L_X74Y95.BRAM_ADDRARDADDRL2.BRAM_IMUX_ADDRARDADDRL2
INT_R_X3Y311.IMUX15.GFAN1
INT_R_X3Y312.IMUX22.GFAN1
BRAM_L_X74Y95.BRAM_ADDRARDADDRU8.BRAM_IMUX_ADDRARDADDRU8
BRAM_L_X74Y95.BRAM_IMUX_ADDRARDADDRL9.BRAM_IMUX19_3
BRAM_L_X74Y95.BRAM_IMUX_ADDRARDADDRL4.BRAM_IMUX21_1
INT_L_X74Y96.IMUX_L20.GFAN1
BRAM_L_X74Y95.BRAM_ADDRARDADDRL8.BRAM_IMUX_ADDRARDADDRL8
BRAM_L_X6Y290.BRAM_ADDRARDADDRL3.BRAM_IMUX_ADDRARDADDRL3
INT_L_X74Y96.IMUX_L11.GFAN0
BRAM_L_X74Y95.BRAM_FIFO36_ADDRARDADDRL8.BRAM_ADDRARDADDRL8
INT_R_X3Y310.IMUX40.GFAN0
BRAM_L_X74Y95.BRAM_FIFO36_ADDRARDADDRU6.BRAM_ADDRARDADDRU6
INT_L_X74Y98.GFAN0.GND_WIRE
BRAM_L_X6Y290.BRAM_FIFO36_ADDRARDADDRL2.BRAM_ADDRARDADDRL2
BRAM_L_X74Y95.BRAM_ADDRARDADDRL4.BRAM_IMUX_ADDRARDADDRL4
BRAM_L_X74Y95.BRAM_ADDRARDADDRL10.BRAM_IMUX_ADDRARDADDRL10
INT_L_X74Y97.IMUX_L24.GFAN0
BRAM_L_X74Y95.BRAM_IMUX_ADDRARDADDRU1.BRAM_IMUX10_1
INT_L_X74Y98.IMUX_L9.GFAN0
INT_L_X6Y292.FAN_ALT1.GFAN1
INT_L_X6Y293.GFAN1.GND_WIRE
BRAM_L_X6Y290.BRAM_IMUX_ADDRARDADDRL13.BRAM_IMUX23_1
INT_L_X6Y293.IMUX_L11.GFAN0
BRAM_L_X74Y95.BRAM_FIFO36_ADDRARDADDRL1.BRAM_ADDRARDADDRL1
BRAM_L_X6Y290.BRAM_ADDRARDADDRL14.BRAM_IMUX_ADDRARDADDRL14
BRAM_L_X74Y95.BRAM_ADDRARDADDRL9.BRAM_IMUX_ADDRARDADDRL9
INT_L_X74Y98.IMUX_L17.GFAN0
INT_L_X74Y98.GFAN1.GND_WIRE
BRAM_L_X74Y95.BRAM_ADDRARDADDRU13.BRAM_IMUX_ADDRARDADDRU13
INT_L_X74Y97.IMUX_L8.GFAN0
BRAM_L_X74Y95.BRAM_IMUX_ADDRARDADDRU8.BRAM_IMUX12_1
INT_L_X6Y292.IMUX_L14.GFAN1
INT_L_X74Y97.IMUX_L17.GFAN0
INT_L_X6Y291.GFAN1.GND_WIRE
INT_L_X74Y97.IMUX_L16.GFAN0
INT_R_X3Y313.IMUX7.GFAN1
BRAM_L_X74Y95.BRAM_ADDRARDADDRU6.BRAM_IMUX_ADDRARDADDRU6
INT_L_X6Y292.IMUX_L20.GFAN1
CLBLM_R_X3Y314.CLBLM_M_A2.CLBLM_IMUX2
BRAM_L_X6Y290.BRAM_IMUX_ADDRARDADDRL2.BRAM_IMUX19_1
BRAM_L_X74Y95.BRAM_FIFO36_ADDRARDADDRU0.BRAM_ADDRARDADDRU0
BRAM_L_X74Y95.BRAM_FIFO36_WEBWEU7.BRAM_IMUX46_2
BRAM_L_X6Y290.BRAM_ADDRARDADDRL0.BRAM_IMUX_ADDRARDADDRL0
BRAM_L_X6Y290.BRAM_ADDRARDADDRL7.BRAM_IMUX_ADDRARDADDRL7
INT_L_X74Y96.IMUX_L15.GFAN1
BRAM_L_X74Y95.BRAM_IMUX_ADDRARDADDRL10.BRAM_IMUX20_2
BRAM_L_X6Y290.BRAM_FIFO36_ADDRARDADDRU1.BRAM_ADDRARDADDRU1
BRAM_L_X74Y95.BRAM_FIFO36_ADDRARDADDRU10.BRAM_ADDRARDADDRU10
INT_R_X3Y314.IMUX2.GFAN0
INT_L_X74Y97.IMUX_L32.GFAN0
BRAM_L_X74Y95.BRAM_IMUX_ADDRARDADDRU0.BRAM_IMUX9_1
INT_L_X74Y98.IMUX_L14.GFAN1
BRAM_L_X74Y95.BRAM_FIFO36_ADDRARDADDRU2.BRAM_ADDRARDADDRU2
BRAM_L_X74Y95.BRAM_FIFO36_ADDRARDADDRU1.BRAM_ADDRARDADDRU1
BRAM_L_X74Y95.BRAM_FIFO36_ADDRARDADDRU9.BRAM_ADDRARDADDRU9
BRAM_L_X74Y95.BRAM_IMUX_ADDRARDADDRU9.BRAM_IMUX11_3
BRAM_L_X6Y290.BRAM_ADDRARDADDRU6.BRAM_IMUX_ADDRARDADDRU6
BRAM_L_X74Y95.BRAM_ADDRARDADDRU10.BRAM_IMUX_ADDRARDADDRU10
BRAM_L_X74Y95.BRAM_FIFO36_ADDRARDADDRL11.BRAM_ADDRARDADDRL11
BRAM_L_X6Y290.BRAM_ADDRARDADDRL9.BRAM_IMUX_ADDRARDADDRL9
INT_R_X3Y310.GFAN0.GND_WIRE
BRAM_L_X6Y290.BRAM_IMUX_ADDRARDADDRU13.BRAM_IMUX15_1
CLBLM_R_X3Y310.CLBLM_M_B2.CLBLM_IMUX18
BRAM_L_X74Y95.BRAM_FIFO36_WEAL2.BRAM_IMUX17_2
INT_R_X3Y311.IMUX7.GFAN1
BRAM_L_X74Y95.BRAM_IMUX_ADDRARDADDRU7.BRAM_IMUX9_3
BRAM_L_X74Y95.BRAM_IMUX_ADDRARDADDRL1.BRAM_IMUX18_1
BRAM_L_X74Y95.BRAM_ADDRARDADDRU11.BRAM_IMUX_ADDRARDADDRU11
INT_L_X6Y291.IMUX_L20.GFAN1
BRAM_L_X74Y95.BRAM_IMUX_ADDRARDADDRL14.BRAM_IMUX22_3
INT_L_X6Y291.IMUX_L13.GFAN1
INT_L_X74Y98.IMUX_L22.GFAN1
INT_L_X74Y96.IMUX_L18.GFAN0
INT_L_X74Y96.GFAN1.GND_WIRE
INT_L_X6Y293.IMUX_L14.GFAN1
INT_L_X74Y96.IMUX_L17.GFAN0
BRAM_L_X74Y95.BRAM_FIFO36_ADDRARDADDRU12.BRAM_ADDRARDADDRU12
BRAM_L_X6Y290.BRAM_FIFO36_ADDRARDADDRL8.BRAM_ADDRARDADDRL8
CLBLM_R_X3Y311.CLBLM_M_C2.CLBLM_IMUX29
BRAM_L_X74Y95.BRAM_FIFO36_ADDRARDADDRU14.BRAM_ADDRARDADDRU14
CLBLM_R_X3Y310.CLBLM_M_D1.CLBLM_IMUX40
BRAM_L_X74Y95.BRAM_IMUX_ADDRARDADDRL6.BRAM_IMUX16_3
BRAM_L_X6Y290.BRAM_FIFO36_ADDRARDADDRL11.BRAM_ADDRARDADDRL11
BRAM_L_X6Y290.BRAM_FIFO36_ADDRARDADDRU9.BRAM_ADDRARDADDRU9
BRAM_L_X74Y95.BRAM_ADDRARDADDRL0.BRAM_IMUX_ADDRARDADDRL0
BRAM_L_X74Y95.BRAM_IMUX_ADDRARDADDRU2.BRAM_IMUX11_1
BRAM_L_X6Y290.BRAM_IMUX_ADDRARDADDRU11.BRAM_IMUX14_1
INT_L_X74Y98.IMUX_L16.GFAN0
CLBLM_R_X3Y310.CLBLM_M_AX.CLBLM_BYP1
INT_R_X3Y310.BYP_ALT1.GFAN0
BRAM_L_X74Y95.BRAM_FIFO36_ADDRARDADDRL2.BRAM_ADDRARDADDRL2
BRAM_L_X6Y290.BRAM_IMUX_ADDRARDADDRU4.BRAM_IMUX13_1
INT_L_X74Y98.IMUX_L18.GFAN0
BRAM_L_X6Y290.BRAM_FIFO36_ADDRARDADDRU7.BRAM_ADDRARDADDRU7
BRAM_L_X74Y95.BRAM_ADDRARDADDRU0.BRAM_IMUX_ADDRARDADDRU0
BRAM_L_X6Y290.BRAM_FIFO36_ADDRARDADDRL14.BRAM_ADDRARDADDRL14
INT_L_X6Y291.IMUX_L23.GFAN1
BRAM_L_X74Y95.BRAM_IMUX_ADDRARDADDRL0.BRAM_IMUX17_1
BRAM_L_X74Y95.BRAM_FIFO36_WEBWEL5.BRAM_IMUX22_2
BRAM_L_X74Y95.BRAM_FIFO36_ADDRARDADDRU7.BRAM_ADDRARDADDRU7
INT_L_X74Y96.IMUX_L22.GFAN1
BRAM_L_X6Y290.BRAM_ADDRARDADDRU7.BRAM_IMUX_ADDRARDADDRU7
BRAM_L_X6Y290.BRAM_FIFO36_ADDRARDADDRU8.BRAM_ADDRARDADDRU8
INT_R_X3Y316.IMUX7.GFAN1
INT_L_X6Y292.IMUX_L38.GFAN1
BRAM_L_X74Y95.BRAM_IMUX_ADDRARDADDRU14.BRAM_IMUX14_3
BRAM_L_X74Y95.BRAM_IMUX_ADDRARDADDRL7.BRAM_IMUX17_3
BRAM_L_X6Y290.BRAM_ADDRARDADDRL12.BRAM_IMUX_ADDRARDADDRL12
BRAM_L_X74Y95.BRAM_IMUX_ADDRARDADDRL13.BRAM_IMUX23_1
INT_L_X74Y96.IMUX_L23.GFAN1
INT_L_X6Y291.IMUX_L12.GFAN1
BRAM_L_X6Y290.BRAM_IMUX_ADDRARDADDRU8.BRAM_IMUX12_1
BRAM_L_X74Y95.BRAM_ADDRARDADDRU7.BRAM_IMUX_ADDRARDADDRU7
INT_L_X74Y97.IMUX_L6.GFAN1
BRAM_L_X74Y95.BRAM_FIFO36_ADDRARDADDRU13.BRAM_ADDRARDADDRU13
INT_L_X6Y292.GFAN1.GND_WIRE
BRAM_L_X6Y290.BRAM_FIFO36_WEBWEL7.BRAM_BYP6_2
BRAM_L_X74Y95.BRAM_IMUX_ADDRARDADDRU13.BRAM_IMUX15_1
INT_L_X6Y291.IMUX_L15.GFAN1
BRAM_L_X74Y95.BRAM_IMUX_ADDRARDADDRL8.BRAM_IMUX20_1
INT_R_X3Y313.IMUX29.GFAN1
INT_R_X3Y310.BYP1.BYP_ALT1
INT_L_X74Y98.IMUX_L11.GFAN0
BRAM_L_X74Y95.BRAM_ADDRARDADDRU2.BRAM_IMUX_ADDRARDADDRU2
BRAM_L_X74Y95.BRAM_FIFO36_ADDRARDADDRL0.BRAM_ADDRARDADDRL0
INT_L_X6Y291.IMUX_L14.GFAN1
BRAM_L_X74Y95.BRAM_FIFO36_WEAL0.BRAM_IMUX16_2
INT_L_X6Y293.IMUX_L9.GFAN0
INT_L_X74Y97.IMUX_L12.GFAN1
INT_L_X74Y96.GFAN0.GND_WIRE
INT_R_X3Y315.GFAN1.GND_WIRE
INT_R_X3Y316.IMUX15.GFAN1
INT_L_X6Y293.IMUX_L21.GFAN1
BRAM_L_X6Y290.BRAM_ADDRARDADDRL13.BRAM_IMUX_ADDRARDADDRL13
BRAM_L_X74Y95.BRAM_IMUX_ADDRARDADDRL11.BRAM_IMUX22_1
INT_L_X74Y96.IMUX_L19.GFAN0
BRAM_L_X6Y290.BRAM_FIFO36_ADDRARDADDRU12.BRAM_ADDRARDADDRU12
BRAM_L_X6Y290.BRAM_IMUX_ADDRARDADDRU9.BRAM_IMUX11_3
BRAM_L_X6Y290.BRAM_FIFO36_ADDRARDADDRL13.BRAM_ADDRARDADDRL13
CLBLM_R_X3Y314.CLBLM_M_C1.CLBLM_IMUX32
BRAM_L_X74Y95.BRAM_FIFO36_ADDRARDADDRU11.BRAM_ADDRARDADDRU11
BRAM_L_X6Y290.BRAM_IMUX_ADDRARDADDRU7.BRAM_IMUX9_3
BRAM_L_X6Y290.BRAM_IMUX_ADDRARDADDRL1.BRAM_IMUX18_1
BRAM_L_X6Y290.BRAM_IMUX_ADDRARDADDRU1.BRAM_IMUX10_1
BRAM_L_X74Y95.BRAM_IMUX_ADDRARDADDRU11.BRAM_IMUX14_1
BRAM_L_X6Y290.BRAM_ADDRARDADDRU12.BRAM_IMUX_ADDRARDADDRU12
BRAM_L_X6Y290.BRAM_ADDRARDADDRU0.BRAM_IMUX_ADDRARDADDRU0
INT_R_X3Y314.IMUX32.GFAN0
INT_L_X74Y96.IMUX_L14.GFAN1
BRAM_L_X74Y95.BRAM_ADDRARDADDRU14.BRAM_IMUX_ADDRARDADDRU14
BRAM_L_X74Y95.BRAM_FIFO36_ADDRARDADDRL12.BRAM_ADDRARDADDRL12
BRAM_L_X74Y95.BRAM_ADDRARDADDRL1.BRAM_IMUX_ADDRARDADDRL1
BRAM_L_X74Y95.BRAM_IMUX_ADDRARDADDRL12.BRAM_IMUX21_3
INT_R_X3Y312.IMUX45.GFAN1
BRAM_L_X6Y290.BRAM_ADDRARDADDRL4.BRAM_IMUX_ADDRARDADDRL4
INT_L_X74Y98.IMUX_L21.GFAN1
BRAM_L_X74Y95.BRAM_ADDRARDADDRU12.BRAM_IMUX_ADDRARDADDRU12
BRAM_L_X74Y95.BRAM_IMUX_ADDRARDADDRU12.BRAM_IMUX13_3
BRAM_L_X6Y290.BRAM_FIFO36_ADDRARDADDRU0.BRAM_ADDRARDADDRU0
BRAM_L_X74Y95.BRAM_FIFO36_ADDRARDADDRL3.BRAM_ADDRARDADDRL3
BRAM_L_X74Y95.BRAM_ADDRARDADDRL3.BRAM_IMUX_ADDRARDADDRL3
BRAM_L_X74Y95.BRAM_IMUX_ADDRARDADDRU4.BRAM_IMUX13_1
INT_L_X74Y97.IMUX_L33.GFAN0
BRAM_L_X6Y290.BRAM_IMUX_ADDRARDADDRL8.BRAM_IMUX20_1
BRAM_L_X74Y95.BRAM_FIFO36_ADDRARDADDRL6.BRAM_ADDRARDADDRL6
BRAM_L_X74Y95.BRAM_ADDRARDADDRU3.BRAM_IMUX_ADDRARDADDRU3
BRAM_L_X74Y95.BRAM_IMUX_ADDRARDADDRU3.BRAM_IMUX10_3
BRAM_L_X74Y95.BRAM_ADDRARDADDRU9.BRAM_IMUX_ADDRARDADDRU9
BRAM_L_X74Y95.BRAM_FIFO36_WEAU2.BRAM_IMUX9_2
INT_L_X6Y291.GFAN0.GND_WIRE
BRAM_L_X74Y95.BRAM_ADDRARDADDRL14.BRAM_IMUX_ADDRARDADDRL14
INT_L_X74Y97.FAN_ALT1.GFAN1
BRAM_L_X74Y95.BRAM_FIFO36_WEBWEL7.BRAM_BYP6_2
BRAM_L_X74Y95.BRAM_FIFO36_ADDRARDADDRL4.BRAM_ADDRARDADDRL4
INT_L_X6Y292.IMUX_L9.GFAN0
BRAM_L_X6Y290.BRAM_IMUX_ADDRARDADDRL6.BRAM_IMUX16_3
INT_L_X74Y96.IMUX_L21.GFAN1
BRAM_L_X6Y290.BRAM_ADDRARDADDRU10.BRAM_IMUX_ADDRARDADDRU10
BRAM_L_X74Y95.BRAM_ADDRARDADDRU4.BRAM_IMUX_ADDRARDADDRU4
INT_L_X74Y97.GFAN0.GND_WIRE
BRAM_L_X74Y95.BRAM_FIFO36_ADDRARDADDRU3.BRAM_ADDRARDADDRU3
INT_L_X74Y96.IMUX_L13.GFAN1
INT_L_X74Y98.IMUX_L10.GFAN0
BRAM_L_X74Y95.BRAM_FIFO36_WEAL3.BRAM_IMUX33_2
INT_L_X6Y293.IMUX_L17.GFAN0
BRAM_L_X74Y95.BRAM_FIFO36_WEAU3.BRAM_IMUX25_2
BRAM_L_X74Y95.BRAM_ADDRARDADDRL12.BRAM_IMUX_ADDRARDADDRL12
BRAM_L_X6Y290.BRAM_ADDRARDADDRU14.BRAM_IMUX_ADDRARDADDRU14
INT_L_X74Y97.IMUX_L25.GFAN0
BRAM_L_X74Y95.BRAM_ADDRARDADDRU1.BRAM_IMUX_ADDRARDADDRU1
INT_L_X74Y97.IMUX_L9.GFAN0
INT_R_X3Y312.GFAN1.GND_WIRE
BRAM_L_X6Y290.BRAM_FIFO36_ADDRARDADDRL0.BRAM_ADDRARDADDRL0
BRAM_L_X6Y290.BRAM_IMUX_ADDRARDADDRL0.BRAM_IMUX17_1
INT_L_X6Y291.IMUX_L17.GFAN0
BRAM_L_X6Y290.BRAM_IMUX_ADDRARDADDRU0.BRAM_IMUX9_1
BRAM_L_X6Y290.BRAM_ADDRARDADDRU2.BRAM_IMUX_ADDRARDADDRU2
INT_L_X6Y291.IMUX_L9.GFAN0
INT_L_X6Y292.GFAN0.GND_WIRE
BRAM_L_X6Y290.BRAM_IMUX_ADDRARDADDRL14.BRAM_IMUX22_3
BRAM_L_X74Y95.BRAM_IMUX_ADDRARDADDRU10.BRAM_IMUX12_2
INT_L_X6Y293.IMUX_L22.GFAN1
INT_L_X74Y96.IMUX_L9.GFAN0
BRAM_L_X6Y290.BRAM_FIFO36_ADDRARDADDRU13.BRAM_ADDRARDADDRU13
BRAM_L_X6Y290.BRAM_ADDRARDADDRU13.BRAM_IMUX_ADDRARDADDRU13
BRAM_L_X6Y290.BRAM_FIFO36_ADDRARDADDRL6.BRAM_ADDRARDADDRL6
BRAM_L_X6Y290.BRAM_ADDRARDADDRL6.BRAM_IMUX_ADDRARDADDRL6
BRAM_L_X74Y95.BRAM_IMUX_ADDRARDADDRL2.BRAM_IMUX19_1
INT_L_X6Y293.IMUX_L16.GFAN0
INT_L_X6Y293.GFAN0.GND_WIRE
CLBLM_R_X3Y312.CLBLM_M_D2.CLBLM_IMUX45
BRAM_L_X6Y290.BRAM_FIFO36_ADDRARDADDRU6.BRAM_ADDRARDADDRU6
INT_L_X6Y293.IMUX_L8.GFAN0
INT_L_X6Y292.IMUX_L8.GFAN0
INT_L_X74Y98.IMUX_L8.GFAN0
BRAM_L_X6Y290.BRAM_IMUX_ADDRARDADDRL7.BRAM_IMUX17_3
BRAM_L_X6Y290.BRAM_ADDRARDADDRL8.BRAM_IMUX_ADDRARDADDRL8
BRAM_L_X6Y290.BRAM_IMUX_ADDRARDADDRU14.BRAM_IMUX14_3
BRAM_L_X74Y95.BRAM_ADDRARDADDRL13.BRAM_IMUX_ADDRARDADDRL13
BRAM_L_X6Y290.BRAM_ADDRARDADDRU8.BRAM_IMUX_ADDRARDADDRU8
BRAM_L_X74Y95.BRAM_IMUX_ADDRARDADDRL3.BRAM_IMUX18_3
BRAM_L_X6Y290.BRAM_ADDRARDADDRL1.BRAM_IMUX_ADDRARDADDRL1
BRAM_L_X74Y95.BRAM_ADDRARDADDRL11.BRAM_IMUX_ADDRARDADDRL11
BRAM_L_X6Y290.BRAM_IMUX_ADDRARDADDRL9.BRAM_IMUX19_3
BRAM_L_X6Y290.BRAM_FIFO36_ADDRARDADDRL1.BRAM_ADDRARDADDRL1
INT_L_X6Y291.IMUX_L18.GFAN0
BRAM_L_X6Y290.BRAM_ADDRARDADDRL10.BRAM_IMUX_ADDRARDADDRL10
BRAM_L_X6Y290.BRAM_ADDRARDADDRU1.BRAM_IMUX_ADDRARDADDRU1

CLBLM_R_X3Y310.CLBLM_M_D6.CLBLM_IMUX43
CLBLM_R_X3Y310.CLBLM_M_B6.CLBLM_IMUX12
INT_R_X3Y310.IMUX4.VCC_WIRE
CLBLM_R_X3Y310.CLBLM_M_A6.CLBLM_IMUX4
INT_R_X3Y310.IMUX2.VCC_WIRE
CLBLM_R_X3Y310.CLBLM_M_A2.CLBLM_IMUX2
INT_R_X3Y311.IMUX43.VCC_WIRE
INT_R_X3Y311.IMUX4.VCC_WIRE
CLBLM_R_X3Y311.CLBLM_M_A6.CLBLM_IMUX4
CLBLM_R_X3Y312.CLBLM_M_B6.CLBLM_IMUX12
INT_R_X3Y312.IMUX4.VCC_WIRE
CLBLM_R_X3Y312.CLBLM_M_A6.CLBLM_IMUX4
INT_R_X3Y313.IMUX43.VCC_WIRE
CLBLM_R_X3Y313.CLBLM_M_C6.CLBLM_IMUX35
INT_R_X3Y313.IMUX12.VCC_WIRE
CLBLM_R_X3Y313.CLBLM_M_B6.CLBLM_IMUX12
INT_R_X3Y313.IMUX4.VCC_WIRE
CLBLM_R_X3Y314.CLBLM_M_C6.CLBLM_IMUX35
INT_R_X3Y314.IMUX4.VCC_WIRE
CLBLM_R_X3Y314.CLBLM_M_A6.CLBLM_IMUX4
INT_R_X3Y315.IMUX35.VCC_WIRE
CLBLM_R_X3Y315.CLBLM_M_C6.CLBLM_IMUX35
INT_R_X3Y315.IMUX12.VCC_WIRE
CLBLM_R_X3Y315.CLBLM_M_B6.CLBLM_IMUX12
INT_R_X3Y316.IMUX43.VCC_WIRE
CLBLM_R_X3Y316.CLBLM_M_D6.CLBLM_IMUX43
INT_R_X3Y312.IMUX35.VCC_WIRE
INT_R_X3Y316.IMUX4.VCC_WIRE
CLBLM_R_X3Y316.CLBLM_M_A6.CLBLM_IMUX4
INT_L_X6Y293.IMUX_L39.VCC_WIRE
INT_L_X6Y293.IMUX_L31.VCC_WIRE
BRAM_L_X6Y290.BRAM_IMUX_ADDRARDADDRL15.BRAM_IMUX31_3
BRAM_L_X6Y290.BRAM_FIFO36_ADDRARDADDRL15.BRAM_IMUX_ADDRARDADDRL15
INT_L_X74Y98.IMUX_L39.VCC_WIRE
BRAM_L_X74Y95.BRAM_IMUX_ADDRARDADDRL15.BRAM_IMUX31_3
CLBLM_R_X3Y312.CLBLM_M_D6.CLBLM_IMUX43
INT_L_X6Y292.IMUX_L35.VCC_WIRE
BRAM_L_X6Y290.BRAM_FIFO36_ENARDENU.BRAM_IMUX10_2
INT_L_X6Y292.IMUX_L18.VCC_WIRE
BRAM_L_X6Y290.BRAM_FIFO36_ENARDENL.BRAM_IMUX18_2
INT_L_X6Y294.CTRL_L1.BYP_BOUNCE4
INT_R_X3Y316.IMUX35.VCC_WIRE
BRAM_L_X6Y290.BRAM_FIFO36_RSTREGARSTREGU.BRAM_CTRL1_4
INT_L_X6Y294.CTRL_L0.BYP_BOUNCE4
BRAM_L_X6Y290.BRAM_FIFO36_RSTREGARSTREGL.BRAM_CTRL0_4
BRAM_L_X6Y290.BRAM_FIFO36_RSTRAMARSTRAMLRST.BRAM_CTRL0_3
INT_L_X6Y292.IMUX_L26.VCC_WIRE
BRAM_L_X6Y290.BRAM_FIFO36_ENBWRENU.BRAM_IMUX26_2
INT_L_X6Y292.IMUX_L34.VCC_WIRE
BRAM_L_X74Y95.BRAM_IMUX_ADDRBWRADDRL15.BRAM_IMUX39_3
BRAM_L_X6Y290.BRAM_FIFO36_RSTREGBU.BRAM_CTRL1_0
INT_L_X6Y290.BYP_ALT4.VCC_WIRE
BRAM_L_X6Y290.BRAM_FIFO36_REGCEBL.BRAM_IMUX35_2
INT_L_X6Y290.BYP_BOUNCE4.BYP_ALT4
BRAM_L_X6Y290.BRAM_FIFO36_RSTREGBL.BRAM_CTRL0_0
INT_L_X6Y291.CTRL_L1.BYP_BOUNCE4
INT_L_X74Y98.IMUX_L31.VCC_WIRE
INT_L_X6Y291.BYP_ALT4.VCC_WIRE
INT_L_X6Y291.BYP_BOUNCE4.BYP_ALT4
INT_L_X6Y291.CTRL_L0.BYP_BOUNCE4
BRAM_L_X6Y290.BRAM_FIFO36_REGCEBU.BRAM_IMUX27_2
BRAM_L_X6Y290.BRAM_FIFO36_WEBWEU3.BRAM_IMUX45_2
INT_L_X6Y292.BYP_L3.BYP_ALT3
BRAM_L_X6Y290.BRAM_FIFO36_WEBWEL3.BRAM_BYP3_2
INT_L_X6Y292.FAN_ALT5.VCC_WIRE
BRAM_L_X6Y290.BRAM_FIFO36_RSTRAMBU.BRAM_CTRL1_1
INT_L_X6Y292.FAN_L5.FAN_ALT5
BRAM_L_X74Y95.BRAM_FIFO36_WEBWEL2.BRAM_IMUX37_2
INT_L_X74Y97.IMUX_L11.VCC_WIRE
INT_R_X3Y312.FAN6.FAN_ALT6
CLBLL_L_X2Y299.CLBLL_LL_CE.CLBLL_FAN7
INT_L_X6Y293.CTRL_L0.BYP_BOUNCE4
INT_R_X3Y311.FAN_ALT7.VCC_WIRE
INT_L_X6Y293.CTRL_L1.BYP_BOUNCE4
INT_L_X74Y97.IMUX_L29.VCC_WIRE
CLK_BUFG_BOT_R_X121Y204.CLK_BUFG_R_BUFGCTRL1_IGNORE1.CLK_BUFG_IMUX9_0
INT_R_X49Y196.IMUX13.VCC_WIRE
INT_R_X49Y196.IMUX1.VCC_WIRE
INT_R_X49Y196.IMUX5.VCC_WIRE
CLK_BUFG_BOT_R_X121Y204.CLK_BUFG_R_BUFGCTRL1_S0.CLK_BUFG_IMUX5_0
BRAM_L_X74Y95.BRAM_FIFO36_RSTRAMBL.BRAM_CTRL0_1
BRAM_L_X6Y290.BRAM_FIFO36_ADDRBWRADDRL15.BRAM_IMUX_ADDRBWRADDRL15
CLBLM_R_X3Y311.CLBLM_M_D6.CLBLM_IMUX43
CLBLM_R_X3Y311.CLBLM_M_B6.CLBLM_IMUX12
INT_L_X74Y97.IMUX_L19.VCC_WIRE
CLBLM_R_X3Y316.CLBLM_M_CE.CLBLM_FAN7
CLBLM_R_X3Y310.CLBLM_M_C6.CLBLM_IMUX35
BRAM_L_X74Y95.BRAM_FIFO36_WEBWEU2.BRAM_IMUX29_2
CLBLM_R_X3Y316.CLBLM_L_CE.CLBLM_FAN6
CLBLM_R_X3Y314.CLBLM_M_CE.CLBLM_FAN7
INT_R_X49Y196.IMUX9.VCC_WIRE
INT_L_X74Y97.BYP_ALT3.VCC_WIRE
BRAM_L_X74Y95.BRAM_FIFO36_ENBWRENL.BRAM_IMUX34_2
INT_L_X6Y294.BYP_BOUNCE4.BYP_ALT4
CLBLM_R_X3Y315.CLBLM_M_CE.CLBLM_FAN7
INT_R_X3Y315.FAN_ALT6.VCC_WIRE
INT_R_X3Y312.IMUX12.VCC_WIRE
INT_R_X3Y316.IMUX12.VCC_WIRE
BRAM_L_X74Y95.BRAM_FIFO36_RSTREGARSTREGL.BRAM_CTRL0_4
INT_R_X3Y315.FAN6.FAN_ALT6
INT_R_X3Y311.IMUX12.VCC_WIRE
BRAM_L_X6Y290.BRAM_FIFO36_RSTRAMARSTRAMU.BRAM_CTRL1_3
CLBLM_R_X3Y311.CLBLM_M_CE.CLBLM_FAN7
INT_R_X3Y312.FAN7.FAN_ALT7
INT_L_X74Y98.BYP_BOUNCE4.BYP_ALT4
CLK_BUFG_BOT_R_X121Y204.CLK_BUFG_R_BUFGCTRL1_IGNORE0.CLK_BUFG_IMUX13_0
INT_R_X49Y196.IMUX21.VCC_WIRE
INT_R_X3Y310.FAN_ALT7.VCC_WIRE
BRAM_L_X74Y95.BRAM_FIFO36_CLKBWRCLKL.BRAM_CLK0_1
INT_L_X6Y292.BYP_ALT3.VCC_WIRE
INT_R_X3Y310.FAN_ALT6.VCC_WIRE
CLK_BUFG_BOT_R_X121Y204.CLK_BUFG_R_BUFGCTRL1_CE0.CLK_BUFG_IMUX21_0
BRAM_L_X6Y290.BRAM_FIFO36_WEBWEU0.BRAM_FAN5_2
INT_R_X3Y316.FAN_ALT6.VCC_WIRE
CLBLM_R_X3Y310.CLBLM_L_CE.CLBLM_FAN6
INT_L_X74Y97.IMUX_L10.VCC_WIRE
CLBLM_R_X3Y311.CLBLM_L_CE.CLBLM_FAN6
INT_L_X74Y97.IMUX_L37.VCC_WIRE
INT_L_X74Y97.IMUX_L35.VCC_WIRE
CLBLM_R_X3Y315.CLBLM_L_CE.CLBLM_FAN6
INT_L_X74Y97.IMUX_L27.VCC_WIRE
INT_R_X3Y316.FAN_ALT7.VCC_WIRE
INT_L_X74Y96.CLK_L0.FAN_BOUNCE5
BRAM_L_X74Y95.BRAM_FIFO36_WEBWEU0.BRAM_FAN5_2
BRAM_L_X6Y290.BRAM_FIFO36_WEBWEU1.BRAM_IMUX13_2
INT_R_X3Y310.FAN7.FAN_ALT7
CLBLM_R_X3Y316.CLBLM_M_C6.CLBLM_IMUX35
CLBLM_R_X3Y310.CLBLM_M_CE.CLBLM_FAN7
INT_L_X6Y292.IMUX_L5.VCC_WIRE
INT_R_X3Y314.FAN7.FAN_ALT7
INT_R_X3Y312.IMUX43.VCC_WIRE
INT_R_X3Y310.FAN6.FAN_ALT6
INT_R_X3Y311.FAN7.FAN_ALT7
INT_R_X3Y314.IMUX12.VCC_WIRE
INT_R_X3Y315.FAN7.FAN_ALT7
CLBLM_R_X3Y305.CLBLM_L_CE.CLBLM_FAN6
INT_L_X6Y292.IMUX_L11.VCC_WIRE
INT_L_X2Y299.FAN_L7.FAN_ALT7
INT_R_X3Y314.FAN_ALT7.VCC_WIRE
INT_R_X3Y305.FAN_ALT6.VCC_WIRE
INT_R_X3Y315.FAN_ALT7.VCC_WIRE
INT_R_X3Y311.FAN6.FAN_ALT6
CLBLM_R_X3Y314.CLBLM_L_CE.CLBLM_FAN6
CLBLM_R_X3Y316.CLBLM_M_B6.CLBLM_IMUX12
INT_R_X3Y313.FAN6.FAN_ALT6
INT_R_X3Y313.FAN_ALT7.VCC_WIRE
INT_L_X74Y98.CTRL_L1.BYP_BOUNCE4
BRAM_L_X6Y290.BRAM_FIFO36_ENBWRENL.BRAM_IMUX34_2
INT_L_X74Y97.IMUX_L13.VCC_WIRE
INT_R_X3Y314.FAN6.FAN_ALT6
INT_L_X74Y97.IMUX_L5.VCC_WIRE
BRAM_L_X74Y95.BRAM_FIFO36_REGCEAREGCEU.BRAM_IMUX11_2
INT_R_X3Y314.IMUX43.VCC_WIRE
INT_R_X49Y196.IMUX17.VCC_WIRE
INT_L_X6Y292.IMUX_L37.VCC_WIRE
INT_L_X74Y98.BYP_ALT4.VCC_WIRE
INT_L_X6Y292.IMUX_L10.VCC_WIRE
CLK_BUFG_BOT_R_X121Y204.CLK_BUFG_R_BUFGCTRL1_S1.CLK_BUFG_IMUX1_0
CLBLM_R_X3Y312.CLBLM_M_CE.CLBLM_FAN7
INT_R_X3Y315.IMUX4.VCC_WIRE
CLBLM_R_X3Y313.CLBLM_M_A6.CLBLM_IMUX4
CLK_BUFG_BOT_R_X121Y204.CLK_BUFG_R_BUFGCTRL1_CE1.CLK_BUFG_IMUX17_0
INT_R_X3Y312.FAN_ALT7.VCC_WIRE
BRAM_L_X6Y290.BRAM_FIFO36_REGCEAREGCEL.BRAM_IMUX19_2
BRAM_L_X6Y290.BRAM_FIFO36_RSTRAMBL.BRAM_CTRL0_1
CLBLM_R_X3Y312.CLBLM_L_CE.CLBLM_FAN6
INT_R_X3Y316.FAN7.FAN_ALT7
CLBLM_R_X3Y313.CLBLM_M_CE.CLBLM_FAN7
BRAM_L_X74Y95.BRAM_FIFO36_ADDRARDADDRL15.BRAM_IMUX_ADDRARDADDRL15
BRAM_L_X6Y290.BRAM_FIFO36_WEBWEL2.BRAM_IMUX37_2
CLBLM_R_X3Y313.CLBLM_L_CE.CLBLM_FAN6
INT_L_X74Y95.CTRL_L1.BYP_BOUNCE4
BRAM_L_X74Y95.BRAM_FIFO36_REGCEAREGCEL.BRAM_IMUX19_2
INT_L_X74Y97.IMUX_L34.VCC_WIRE
INT_R_X3Y313.FAN_ALT6.VCC_WIRE
BRAM_L_X74Y95.BRAM_FIFO36_WEBWEL1.BRAM_IMUX21_2
BRAM_L_X74Y95.BRAM_FIFO36_WEBWEU1.BRAM_IMUX13_2
INT_L_X74Y96.FAN_ALT5.VCC_WIRE
CLBLM_R_X3Y315.CLBLM_M_A6.CLBLM_IMUX4
BRAM_L_X74Y95.BRAM_FIFO36_WEBWEL0.BRAM_IMUX5_2
INT_L_X74Y99.CTRL_L1.BYP_BOUNCE4
INT_R_X3Y310.IMUX12.VCC_WIRE
INT_L_X74Y99.CTRL_L0.BYP_BOUNCE4
INT_L_X6Y292.IMUX_L21.VCC_WIRE
INT_L_X74Y96.CLK_L1.FAN_BOUNCE5
INT_L_X74Y96.FAN_BOUNCE5.FAN_ALT5
INT_L_X74Y97.FAN_ALT5.VCC_WIRE
INT_R_X3Y305.FAN6.FAN_ALT6
BRAM_L_X74Y95.BRAM_FIFO36_WEBWEL3.BRAM_BYP3_2
INT_L_X74Y97.BYP_L3.BYP_ALT3
BRAM_L_X74Y95.BRAM_FIFO36_WEBWEU3.BRAM_IMUX45_2
INT_L_X74Y97.IMUX_L45.VCC_WIRE
BRAM_L_X6Y290.BRAM_FIFO36_WEBWEU2.BRAM_IMUX29_2
INT_L_X2Y299.FAN_ALT7.VCC_WIRE
INT_L_X74Y97.IMUX_L26.VCC_WIRE
INT_R_X3Y312.FAN_ALT6.VCC_WIRE
INT_L_X74Y96.BYP_ALT4.VCC_WIRE
INT_L_X6Y292.IMUX_L19.VCC_WIRE
BRAM_L_X74Y95.BRAM_FIFO36_RSTREGBL.BRAM_CTRL0_0
BRAM_L_X6Y290.BRAM_FIFO36_CLKBWRCLKU.BRAM_CLK1_1
BRAM_L_X74Y95.BRAM_FIFO36_RSTRAMBU.BRAM_CTRL1_1
INT_L_X74Y96.CTRL_L1.BYP_BOUNCE4
CLBLM_R_X3Y314.CLBLM_M_D6.CLBLM_IMUX43
INT_L_X74Y96.CTRL_L0.BYP_BOUNCE4
CLBLM_R_X3Y314.CLBLM_M_B6.CLBLM_IMUX12
INT_L_X74Y95.BYP_ALT4.VCC_WIRE
INT_L_X6Y292.IMUX_L27.VCC_WIRE
INT_R_X3Y314.IMUX35.VCC_WIRE
CLBLM_R_X3Y311.CLBLM_M_C6.CLBLM_IMUX35
INT_L_X74Y97.FAN_L5.FAN_ALT5
BRAM_L_X6Y290.BRAM_FIFO36_CLKBWRCLKL.BRAM_CLK0_1
BRAM_L_X74Y95.BRAM_FIFO36_RSTREGBU.BRAM_CTRL1_0
INT_L_X6Y293.BYP_ALT4.VCC_WIRE
BRAM_L_X74Y95.BRAM_FIFO36_ENBWRENU.BRAM_IMUX26_2
INT_L_X74Y96.BYP_BOUNCE4.BYP_ALT4
INT_L_X74Y95.CTRL_L0.BYP_BOUNCE4
INT_L_X74Y98.CTRL_L0.BYP_BOUNCE4
BRAM_L_X74Y95.BRAM_FIFO36_RSTRAMARSTRAMLRST.BRAM_CTRL0_3
BRAM_L_X74Y95.BRAM_FIFO36_RSTRAMARSTRAMU.BRAM_CTRL1_3
INT_L_X6Y294.BYP_ALT4.VCC_WIRE
BRAM_L_X74Y95.BRAM_FIFO36_RSTREGARSTREGU.BRAM_CTRL1_4
INT_L_X74Y99.BYP_BOUNCE4.BYP_ALT4
INT_R_X3Y311.FAN_ALT6.VCC_WIRE
INT_R_X3Y314.FAN_ALT6.VCC_WIRE
INT_L_X74Y97.IMUX_L21.VCC_WIRE
INT_L_X74Y99.BYP_ALT4.VCC_WIRE
BRAM_L_X6Y290.BRAM_IMUX_ADDRBWRADDRL15.BRAM_IMUX39_3
BRAM_L_X74Y95.BRAM_FIFO36_ENARDENL.BRAM_IMUX18_2
INT_L_X74Y97.IMUX_L18.VCC_WIRE
CLBLM_R_X3Y312.CLBLM_M_C6.CLBLM_IMUX35
BRAM_L_X74Y95.BRAM_FIFO36_ENARDENU.BRAM_IMUX10_2
INT_R_X3Y311.IMUX35.VCC_WIRE
CLBLM_R_X3Y313.CLBLM_M_D6.CLBLM_IMUX43
BRAM_L_X74Y95.BRAM_FIFO36_REGCEBL.BRAM_IMUX35_2
BRAM_L_X74Y95.BRAM_FIFO36_REGCEBU.BRAM_IMUX27_2
BRAM_L_X74Y95.BRAM_FIFO36_ADDRBWRADDRL15.BRAM_IMUX_ADDRBWRADDRL15
INT_L_X6Y293.BYP_BOUNCE4.BYP_ALT4
INT_L_X6Y292.IMUX_L45.VCC_WIRE
INT_R_X3Y310.IMUX35.VCC_WIRE
INT_R_X3Y310.IMUX43.VCC_WIRE
CLBLM_R_X3Y315.CLBLM_M_D6.CLBLM_IMUX43
BRAM_L_X6Y290.BRAM_FIFO36_REGCEAREGCEU.BRAM_IMUX11_2
INT_L_X6Y290.CTRL_L1.BYP_BOUNCE4
INT_L_X6Y292.IMUX_L29.VCC_WIRE
INT_L_X6Y290.CTRL_L0.BYP_BOUNCE4
INT_R_X3Y316.FAN6.FAN_ALT6
INT_R_X3Y313.IMUX35.VCC_WIRE
INT_L_X74Y95.BYP_BOUNCE4.BYP_ALT4
BRAM_L_X6Y290.BRAM_FIFO36_WEBWEL1.BRAM_IMUX21_2
INT_R_X3Y313.FAN7.FAN_ALT7
INT_L_X6Y292.IMUX_L13.VCC_WIRE
INT_L_X6Y291.CLK_L0.FAN_BOUNCE5
INT_L_X6Y291.FAN_BOUNCE5.FAN_ALT5
INT_L_X6Y291.FAN_ALT5.VCC_WIRE
INT_R_X3Y315.IMUX43.VCC_WIRE
INT_L_X6Y291.CLK_L1.FAN_BOUNCE5
BRAM_L_X74Y95.BRAM_FIFO36_CLKBWRCLKU.BRAM_CLK1_1
BRAM_L_X6Y290.BRAM_FIFO36_WEBWEL0.BRAM_IMUX5_2

BRAM_L_X6Y290.RAMB18_Y0.IN_USE
BRAM_L_X6Y290.RAMB18_Y0.READ_WIDTH_A_18
BRAM_L_X6Y290.RAMB18_Y0.ZINV_ENARDEN
BRAM_L_X6Y290.RAMB18_Y0.ZINV_CLKARDCLK
BRAM_L_X6Y290.RAMB18_Y0.ZINIT_A[17:0] = 18'b111111111111111111
BRAM_L_X6Y290.RAMB18_Y0.ZINIT_B[17:0] = 18'b111111111111111111
BRAM_L_X6Y290.RAMB18_Y0.ZSRVAL_A[17:0] = 18'b111111111111111111
BRAM_L_X6Y290.RAMB18_Y0.ZSRVAL_B[17:0] = 18'b111111111111111111
BRAM_L_X6Y290.RAMB18_Y0.INIT_00[255:0] = 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
BRAM_L_X6Y290.RAMB18_Y1.IN_USE
BRAM_L_X6Y290.RAMB18_Y1.READ_WIDTH_A_18
BRAM_L_X6Y290.RAMB18_Y1.ZINV_ENARDEN
BRAM_L_X6Y290.RAMB18_Y1.ZINV_CLKARDCLK
BRAM_L_X6Y290.RAMB18_Y1.ZINIT_A[17:0] = 18'b111111111111111111
BRAM_L_X6Y290.RAMB18_Y1.ZINIT_B[17:0] = 18'b111111111111111111
BRAM_L_X6Y290.RAMB18_Y1.ZSRVAL_A[17:0] = 18'b111111111111111111
BRAM_L_X6Y290.RAMB18_Y1.ZSRVAL_B[17:0] = 18'b111111111111111111
BRAM_L_X6Y290.RAMB18_Y1.INIT_00[255:0] = 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000

BRAM_L_X74Y95.RAMB18_Y0.IN_USE
BRAM_L_X74Y95.RAMB18_Y0.READ_WIDTH_A_18
BRAM_L_X74Y95.RAMB18_Y0.ZINV_ENARDEN
BRAM_L_X74Y95.RAMB18_Y0.ZINV_CLKARDCLK
BRAM_L_X74Y95.RAMB18_Y0.ZINIT_A[17:0] = 18'b111111111111111111
BRAM_L_X74Y95.RAMB18_Y0.ZINIT_B[17:0] = 18'b111111111111111111
BRAM_L_X74Y95.RAMB18_Y0.ZSRVAL_A[17:0] = 18'b111111111111111111
BRAM_L_X74Y95.RAMB18_Y0.ZSRVAL_B[17:0] = 18'b111111111111111111
BRAM_L_X74Y95.RAMB18_Y0.INIT_00[255:0] = 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
BRAM_L_X74Y95.RAMB18_Y1.IN_USE
BRAM_L_X74Y95.RAMB18_Y1.READ_WIDTH_A_18
BRAM_L_X74Y95.RAMB18_Y1.ZINV_ENARDEN
BRAM_L_X74Y95.RAMB18_Y1.ZINV_CLKARDCLK
BRAM_L_X74Y95.RAMB18_Y1.ZINIT_A[17:0] = 18'b111111111111111111
BRAM_L_X74Y95.RAMB18_Y1.ZINIT_B[17:0] = 18'b111111111111111111
BRAM_L_X74Y95.RAMB18_Y1.ZSRVAL_A[17:0] = 18'b111111111111111111
BRAM_L_X74Y95.RAMB18_Y1.ZSRVAL_B[17:0] = 18'b111111111111111111
BRAM_L_X74Y95.RAMB18_Y1.INIT_00[255:0] = 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000

CLK_BUFG_BOT_R_X121Y204.BUFGCTRL.BUFGCTRL_X0Y1.IN_USE
CLK_BUFG_BOT_R_X121Y204.BUFGCTRL.BUFGCTRL_X0Y1.IS_IGNORE1_INVERTED
CLK_BUFG_BOT_R_X121Y204.BUFGCTRL.BUFGCTRL_X0Y1.ZINV_CE0
CLK_BUFG_BOT_R_X121Y204.BUFGCTRL.BUFGCTRL_X0Y1.ZINV_S0

HCLK_R_X12Y338.ENABLE_BUFFER.HCLK_CK_BUFHCLK0

CLK_HROW_TOP_R_X121Y338.CLK_HROW_R_CK_GCLK1_ACTIVE

HCLK_R_X12Y286.ENABLE_BUFFER.HCLK_CK_BUFHCLK0

HCLK_R_X22Y286.ENABLE_BUFFER.HCLK_CK_BUFHCLK0

CLK_HROW_TOP_R_X121Y286.CLK_HROW_R_CK_GCLK1_ACTIVE

CLK_HROW_BOT_R_X121Y78.CLK_HROW_R_CK_GCLK1_ACTIVE
CLK_HROW_BOT_R_X121Y78.CLK_HROW_CK_IN_R12_ACTIVE

HCLK_R_X182Y78.ENABLE_BUFFER.HCLK_CK_BUFHCLK0

HCLK_CMT_L_X228Y78.HCLK_CMT_CCIO0_ACTIVE
HCLK_CMT_L_X228Y78.HCLK_CMT_CCIO0_USED

CLK_BUFG_REBUF_X121Y350.GCLK1_ENABLE_ABOVE
CLK_BUFG_REBUF_X121Y350.GCLK1_ENABLE_BELOW

HCLK_CMT_X8Y338.HCLK_CMT_CK_BUFHCLK0_USED

CLK_BUFG_REBUF_X121Y325.GCLK1_ENABLE_ABOVE
CLK_BUFG_REBUF_X121Y325.GCLK1_ENABLE_BELOW

CLK_BUFG_REBUF_X121Y298.GCLK1_ENABLE_ABOVE
CLK_BUFG_REBUF_X121Y298.GCLK1_ENABLE_BELOW

HCLK_CMT_X8Y286.HCLK_CMT_CK_BUFHCLK0_USED

CLK_BUFG_REBUF_X121Y273.GCLK1_ENABLE_ABOVE
CLK_BUFG_REBUF_X121Y273.GCLK1_ENABLE_BELOW

CLK_BUFG_REBUF_X121Y246.GCLK1_ENABLE_ABOVE
CLK_BUFG_REBUF_X121Y246.GCLK1_ENABLE_BELOW

CLK_BUFG_REBUF_X121Y221.GCLK1_ENABLE_ABOVE
CLK_BUFG_REBUF_X121Y221.GCLK1_ENABLE_BELOW

CLK_BUFG_REBUF_X121Y194.GCLK1_ENABLE_ABOVE
CLK_BUFG_REBUF_X121Y194.GCLK1_ENABLE_BELOW

CLK_BUFG_REBUF_X121Y169.GCLK1_ENABLE_ABOVE
CLK_BUFG_REBUF_X121Y169.GCLK1_ENABLE_BELOW

CLK_BUFG_REBUF_X121Y142.GCLK1_ENABLE_ABOVE
CLK_BUFG_REBUF_X121Y142.GCLK1_ENABLE_BELOW

CLK_BUFG_REBUF_X121Y117.GCLK1_ENABLE_ABOVE
CLK_BUFG_REBUF_X121Y117.GCLK1_ENABLE_BELOW

CLK_BUFG_REBUF_X121Y90.GCLK1_ENABLE_ABOVE
CLK_BUFG_REBUF_X121Y90.GCLK1_ENABLE_BELOW

HCLK_CMT_X8Y78.HCLK_CMT_CK_BUFHCLK0_USED

HCLK_CMT_L_X228Y78.HCLK_CMT_CK_BUFHCLK0_USED

CLK_BUFG_REBUF_X121Y65.GCLK1_ENABLE_ABOVE
CLK_BUFG_REBUF_X121Y65.GCLK1_ENABLE_BELOW

CLK_BUFG_REBUF_X121Y38.GCLK1_ENABLE_ABOVE
CLK_BUFG_REBUF_X121Y38.GCLK1_ENABLE_BELOW

CLK_BUFG_REBUF_X121Y13.GCLK1_ENABLE_ABOVE
CLK_BUFG_REBUF_X121Y13.GCLK1_ENABLE_BELOW


## top.v
// Original source: https://github.com/openXC7/nextpnr-xilinx/commit/ddd2977da08b63e1103#commitcomment-143234414

`define DIFF_CLK

module top(
    input clk_p_i,
    input clk_n_i,
    input rst_i,
    output [7:0] led_o
);

    wire clk;
    wire clk_ibufg;
`ifdef DIFF_CLK
    IBUFDS ibuf_inst (.I(clk_p_i), .IB(clk_n_i), .O(clk_ibufg));
    BUFG bufg_inst (.I(clk_ibufg), .O(clk));
`else
    BUFG bufg_inst (.I(clk_i), .O(clk));
`endif

    reg  [1:0] addr = 0;
    wire [63:0]out;

    reg [27:0] cnt=28'b0;

    assign led_o[6:0] = out[6:0];
    assign led_o[7] = out[32];

    always@(posedge clk or posedge rst_i)begin
        if(rst_i) begin
            cnt <=0;
            addr <=2'b0;
            end
        else begin
            cnt <=cnt+1'b1;
            addr <={0,cnt[24]};
            end
    end

    rom_ip rom_ip_inst(
        .clk(clk),
        .addr(addr),
        .dout(out)
    );

endmodule

module rom_ip(
    input clk,
    input [1:0] addr,
    output [63:0] dout
);

    RAMB36E1 #(
        .READ_WIDTH_A(36),          // 端口A的读取宽度,
        .RAM_MODE("TDP"),
        .WRITE_MODE_A("WRITE_FIRST"),
        .INIT_00(256'h0100000000)
    ) ramb36e1_inst_0 (
        .CLKARDCLK(clk),                // 时钟输入
        .ENARDEN(1'b1),                // 使能信号
        .ADDRARDADDR({9'b0,addr,5'b0}),              // 地址输入
        .DOADO(dout[31:0]),             // 数据输出
        .WEA(4'b0)                // 写使能，不写入
    );

    RAMB36E1 #(
        .READ_WIDTH_A(36),          // 端口A的读取宽度,
        .RAM_MODE("TDP"),
        .WRITE_MODE_A("WRITE_FIRST"),
        .INIT_00(256'h00000001)
    ) ramb36e1_inst_1 (
        .CLKARDCLK(clk),                // 时钟输入
        .ENARDEN(1'b1),                // 使能信号
        .ADDRARDADDR({9'b0,addr,5'b0}),              // 地址输入
        .DOADO(dout[63:32]),             // 数据输出
        .WEA(4'b0)                // 写使能，不写入
    );

endmodule
	# clk_p_i
	set_property LOC AD12 [get_ports {clk_p_i}]
	set_property IOSTANDARD LVDS [get_ports {clk_p_i}]

	# clk_n_i
	set_property LOC AD11 [get_ports {clk_n_i}]
	set_property IOSTANDARD LVDS [get_ports {clk_n_i}]

	# rst_i
	set_property LOC G12 [get_ports {rst_i}]
	set_property IOSTANDARD LVCMOS25 [get_ports {rst_i}]

	# led[0]
	set_property LOC AB8 [get_ports {led_o[0]}]
	set_property IOSTANDARD LVCMOS15 [get_ports {led_o[0]}]

	# led[1]
	set_property LOC AA8 [get_ports {led_o[1]}]
	set_property IOSTANDARD LVCMOS15 [get_ports {led_o[1]}]

	# led[2]
	set_property LOC AC9 [get_ports {led_o[2]}]
	set_property IOSTANDARD LVCMOS15 [get_ports {led_o[2]}]

	# led[3]
	set_property LOC AB9 [get_ports {led_o[3]}]
	set_property IOSTANDARD LVCMOS15 [get_ports {led_o[3]}]

	# led[4]
	set_property LOC AE26 [get_ports {led_o[4]}]
	set_property IOSTANDARD LVCMOS25 [get_ports {led_o[4]}]

	# led[5]
	set_property LOC G19 [get_ports {led_o[5]}]
	set_property IOSTANDARD LVCMOS25 [get_ports {led_o[5]}]

	# led[6]
	set_property LOC E18 [get_ports {led_o[6]}]
	set_property IOSTANDARD LVCMOS25 [get_ports {led_o[6]}]

	# led[7]
	set_property LOC F16 [get_ports {led_o[7]}]
	set_property IOSTANDARD LVCMOS25 [get_ports {led_o[7]}]
	PROJECT = top
	TOP = top
	TOP_VERILOG = top.v
	ADDITIONAL_SOURCES =

	# Target Platform
	FAMILY = kintex7
	PART = xc7k325tffg900-2
	BOARD = kc705
	XDC ?= kc705.xdc
	CHIPDB ?= ./chipdb
	JTAG_LINK ?=

	include ./openXC7.mk
	NEXTPNR_XILINX_DIR ?= /snap/openxc7/current/opt/nextpnr-xilinx
	NEXTPNR_XILINX_PYTHON_DIR ?= ${NEXTPNR_XILINX_DIR}/python
	PRJXRAY_DB_DIR ?= ${NEXTPNR_XILINX_DIR}/external/prjxray-db

	DBPART = $(shell echo ${PART} \| sed -e 's/-[0-9]//g')
	SPEEDGRADE = $(shell echo ${PART} \| sed -e 's/.*\-\([0-9]\)/\1/g')

	CHIPDB ?= ../chipdb/
	PYPY3 ?= pypy3

	TOP ?= ${PROJECT}
	TOP_MODULE ?= ${TOP}

	PNR_DEBUG ?= # --verbose --debug

	BOARD ?= UNKNOWN
	JTAG_LINK ?= --board ${BOARD}

	XDC ?= ${PROJECT}.xdc

	.PHONY: all
	all: ${PROJECT}.bit

	.PHONY: program
	program: ${PROJECT}.bit
	openFPGALoader ${JTAG_LINK} --bitstream $<

	${PROJECT}.json: ${TOP}.v ${ADDITIONAL_SOURCES}
	yosys ${YOSYS_OPTS} -p "synth_xilinx -flatten -abc9 ${SYNTH_OPTS} -arch xc7 -top ${TOP_MODULE}; write_json ${PROJECT}.json" $< ${ADDITIONAL_SOURCES}

	# The chip database only needs to be generated once
	# that is why we don't clean it with make clean
	${CHIPDB}/${DBPART}.bin:
	${PYPY3} ${NEXTPNR_XILINX_PYTHON_DIR}/bbaexport.py --device ${PART} --bba ${DBPART}.bba
	mkdir -p $(CHIPDB) && bbasm -l ${DBPART}.bba ${CHIPDB}/${DBPART}.bin
	rm -f ${DBPART}.bba

	${PROJECT}.pack.json: ${PROJECT}.json ${CHIPDB}/${DBPART}.bin ${XDC}
	nextpnr-xilinx --chipdb ${CHIPDB}/${DBPART}.bin --xdc ${XDC} --json ${PROJECT}.json --pack-only --write $@ ${PNR_ARGS} ${PNR_DEBUG}

	${PROJECT}.place.json: ${PROJECT}.pack.json
	nextpnr-xilinx --chipdb ${CHIPDB}/${DBPART}.bin --xdc ${XDC} --no-pack --no-route --json $^ --write $@ ${PNR_ARGS} ${PNR_DEBUG}

	${PROJECT}.fasm: ${PROJECT}.place.json
	nextpnr-xilinx --chipdb ${CHIPDB}/${DBPART}.bin --xdc ${XDC} --no-pack --no-place --json $^ --fasm $@ --write ${PROJECT}.route.json ${PNR_ARGS} ${PNR_DEBUG}

	${PROJECT}.frames: ${PROJECT}.fasm
	fasm2frames --part ${PART} --db-root ${PRJXRAY_DB_DIR}/${FAMILY} $< > $@

	${PROJECT}.bit: ${PROJECT}.frames
	xc7frames2bit --part_file ${PRJXRAY_DB_DIR}/${FAMILY}/${PART}/part.yaml --part_name ${PART} --frm_file $< --output_file $@

	.PHONY: clean
	clean:
	@rm -f *.bit
	@rm -f *.frames
	@rm -f *.fasm
	@rm -f *.json

	.PHONY: pnrclean
	pnrclean:
	rm .fasm .frames *.bit
	// Original source: https://github.com/openXC7/nextpnr-xilinx/commit/ddd2977da08b63e1103#commitcomment-143234414

	`define DIFF_CLK

	module top(
	input clk_p_i,
	input clk_n_i,
	input rst_i,
	output [7:0] led_o
	);

	wire clk;
	wire clk_ibufg;
	`ifdef DIFF_CLK
	IBUFDS ibuf_inst (.I(clk_p_i), .IB(clk_n_i), .O(clk_ibufg));
	BUFG bufg_inst (.I(clk_ibufg), .O(clk));
	`else
	BUFG bufg_inst (.I(clk_i), .O(clk));
	`endif

	reg [1:0] addr = 0;
	wire [63:0]out;

	reg [27:0] cnt=28'b0;

	assign led_o[6:0] = out[6:0];
	assign led_o[7] = out[32];

	always@(posedge clk or posedge rst_i)begin
	if(rst_i) begin
	cnt <=0;
	addr <=2'b0;
	end
	else begin
	cnt <=cnt+1'b1;
	addr <={0,cnt[24]};
	end
	end

	rom_ip rom_ip_inst(
	.clk(clk),
	.addr(addr),
	.dout(out)
	);

	endmodule

	module rom_ip(
	input clk,
	input [1:0] addr,
	output [63:0] dout
	);

	RAMB36E1 #(
	.READ_WIDTH_A(36), // 端口A的读取宽度,
	.RAM_MODE("TDP"),
	.WRITE_MODE_A("WRITE_FIRST"),
	.INIT_00(256'h0100000000)
	) ramb36e1_inst_0 (
	.CLKARDCLK(clk), // 时钟输入
	.ENARDEN(1'b1), // 使能信号
	.ADDRARDADDR({9'b0,addr,5'b0}), // 地址输入
	.DOADO(dout[31:0]), // 数据输出
	.WEA(4'b0) // 写使能，不写入
	);

	RAMB36E1 #(
	.READ_WIDTH_A(36), // 端口A的读取宽度,
	.RAM_MODE("TDP"),
	.WRITE_MODE_A("WRITE_FIRST"),
	.INIT_00(256'h00000001)
	) ramb36e1_inst_1 (
	.CLKARDCLK(clk), // 时钟输入
	.ENARDEN(1'b1), // 使能信号
	.ADDRARDADDR({9'b0,addr,5'b0}), // 地址输入
	.DOADO(dout[63:32]), // 数据输出
	.WEA(4'b0) // 写使能，不写入
	);

	endmodule