XC7K420T DDR constraint file

xc7k420t_constraints.xdc

#NET "clk" LOC = U24;
#NET "clk" IOSTANDARD = LVCMOS25;

#set_property SLEW FAST [get_ports {clk}]
set_property IOSTANDARD LVCMOS25 [get_ports clk]
set_property PACKAGE_PIN U24 [get_ports clk]

#NET "led" LOC = A27;
#NET "led" IOSTANDARD = LVCMOS15;

set_property IOSTANDARD LVCMOS15 [get_ports led]
set_property PACKAGE_PIN A27 [get_ports led]

#NET "led2" LOC = H21;
#NET "led2" IOSTANDARD = LVCMOS15;

set_property IOSTANDARD LVCMOS15 [get_ports led2]
set_property PACKAGE_PIN H21 [get_ports led2]


#NET "rst" LOC = J24;
#NET "rst" IOSTANDARD = LVCMOS15;

set_property IOSTANDARD LVCMOS15 [get_ports rst]
set_property PACKAGE_PIN J24 [get_ports rst]


#NET "led1" LOC = H25;
#NET "led1" IOSTANDARD = LVCMOS15;

set_property IOSTANDARD LVCMOS15 [get_ports led1]
set_property PACKAGE_PIN H25 [get_ports led1]


#NET "led3" LOC = H26;
#NET "led3" IOSTANDARD = LVCMOS15;

set_property IOSTANDARD LVCMOS15 [get_ports led3]
set_property PACKAGE_PIN H26 [get_ports led3]



##################################################################################################
## Controller 0
## Memory Device: DDR3_SDRAM->SODIMMs->MT8JSF25664HZ-1G1
## Data Width: 64
## Time Period: 2500
## Data Mask: 1
##################################################################################################

#create_clock -name sys_clk_i -period 5 [get_ports sys_clk_i]
#set_propagated_clock sys_clk_i

############## NET - IOSTANDARD ##################


# PadFunction: IO_L22N_T3_17
set_property SLEW FAST [get_ports {ddr3_dq[0]}]
set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dq[0]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[0]}]
set_property PACKAGE_PIN W29 [get_ports {ddr3_dq[0]}]

# PadFunction: IO_L24P_T3_17
set_property SLEW FAST [get_ports {ddr3_dq[1]}]
set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dq[1]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[1]}]
set_property PACKAGE_PIN Y29 [get_ports {ddr3_dq[1]}]

# PadFunction: IO_L24N_T3_17
set_property SLEW FAST [get_ports {ddr3_dq[2]}]
set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dq[2]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[2]}]
set_property PACKAGE_PIN AB30 [get_ports {ddr3_dq[2]}]

# PadFunction: IO_L23N_T3_17
set_property SLEW FAST [get_ports {ddr3_dq[3]}]
set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dq[3]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[3]}]
set_property PACKAGE_PIN AB29 [get_ports {ddr3_dq[3]}]

# PadFunction: IO_L20P_T3_17
set_property SLEW FAST [get_ports {ddr3_dq[4]}]
set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dq[4]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[4]}]
set_property PACKAGE_PIN W28 [get_ports {ddr3_dq[4]}]

# PadFunction: IO_L19P_T3_17
set_property SLEW FAST [get_ports {ddr3_dq[5]}]
set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dq[5]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[5]}]
set_property PACKAGE_PIN W26 [get_ports {ddr3_dq[5]}]

# PadFunction: IO_L22P_T3_17
set_property SLEW FAST [get_ports {ddr3_dq[6]}]
set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dq[6]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[6]}]
set_property PACKAGE_PIN Y28 [get_ports {ddr3_dq[6]}]

# PadFunction: IO_L20N_T3_17
set_property SLEW FAST [get_ports {ddr3_dq[7]}]
set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dq[7]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[7]}]
set_property PACKAGE_PIN AB28 [get_ports {ddr3_dq[7]}]

# PadFunction: IO_L16P_T2_17
set_property SLEW FAST [get_ports {ddr3_dq[8]}]
set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dq[8]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[8]}]
set_property PACKAGE_PIN AA25 [get_ports {ddr3_dq[8]}]

# PadFunction: IO_L14P_T2_SRCC_17
set_property SLEW FAST [get_ports {ddr3_dq[9]}]
set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dq[9]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[9]}]
set_property PACKAGE_PIN AD27 [get_ports {ddr3_dq[9]}]

# PadFunction: IO_L16N_T2_17
set_property SLEW FAST [get_ports {ddr3_dq[10]}]
set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dq[10]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[10]}]
set_property PACKAGE_PIN AB24 [get_ports {ddr3_dq[10]}]

# PadFunction: IO_L14N_T2_SRCC_17
set_property SLEW FAST [get_ports {ddr3_dq[11]}]
set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dq[11]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[11]}]
set_property PACKAGE_PIN AC24 [get_ports {ddr3_dq[11]}]

# PadFunction: IO_L17P_T2_17
set_property SLEW FAST [get_ports {ddr3_dq[12]}]
set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dq[12]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[12]}]
set_property PACKAGE_PIN Y26 [get_ports {ddr3_dq[12]}]

# PadFunction: IO_L18P_T2_17
set_property SLEW FAST [get_ports {ddr3_dq[13]}]
set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dq[13]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[13]}]
set_property PACKAGE_PIN Y25 [get_ports {ddr3_dq[13]}]

# PadFunction: IO_L13P_T2_MRCC_17
set_property SLEW FAST [get_ports {ddr3_dq[14]}]
set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dq[14]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[14]}]
set_property PACKAGE_PIN AA26 [get_ports {ddr3_dq[14]}]

# PadFunction: IO_L13N_T2_MRCC_17
set_property SLEW FAST [get_ports {ddr3_dq[15]}]
set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dq[15]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[15]}]
set_property PACKAGE_PIN AC26 [get_ports {ddr3_dq[15]}]

# PadFunction: IO_L10P_T1_17
set_property SLEW FAST [get_ports {ddr3_dq[16]}]
set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dq[16]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[16]}]
set_property PACKAGE_PIN AD29 [get_ports {ddr3_dq[16]}]

# PadFunction: IO_L10N_T1_17
set_property SLEW FAST [get_ports {ddr3_dq[17]}]
set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dq[17]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[17]}]
set_property PACKAGE_PIN AE30 [get_ports {ddr3_dq[17]}]

# PadFunction: IO_L8N_T1_17
set_property SLEW FAST [get_ports {ddr3_dq[18]}]
set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dq[18]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[18]}]
set_property PACKAGE_PIN AE29 [get_ports {ddr3_dq[18]}]

# PadFunction: IO_L12P_T1_MRCC_17
set_property SLEW FAST [get_ports {ddr3_dq[19]}]
set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dq[19]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[19]}]
set_property PACKAGE_PIN AF30 [get_ports {ddr3_dq[19]}]

# PadFunction: IO_L8P_T1_17
set_property SLEW FAST [get_ports {ddr3_dq[20]}]
set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dq[20]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[20]}]
set_property PACKAGE_PIN AD28 [get_ports {ddr3_dq[20]}]

# PadFunction: IO_L11P_T1_SRCC_17
set_property SLEW FAST [get_ports {ddr3_dq[21]}]
set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dq[21]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[21]}]
set_property PACKAGE_PIN AC27 [get_ports {ddr3_dq[21]}]

# PadFunction: IO_L7P_T1_17
set_property SLEW FAST [get_ports {ddr3_dq[22]}]
set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dq[22]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[22]}]
set_property PACKAGE_PIN AF28 [get_ports {ddr3_dq[22]}]

# PadFunction: IO_L7N_T1_17
set_property SLEW FAST [get_ports {ddr3_dq[23]}]
set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dq[23]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[23]}]
set_property PACKAGE_PIN AF27 [get_ports {ddr3_dq[23]}]

# PadFunction: IO_L6P_T0_17
set_property SLEW FAST [get_ports {ddr3_dq[24]}]
set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dq[24]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[24]}]
set_property PACKAGE_PIN AG30 [get_ports {ddr3_dq[24]}]

# PadFunction: IO_L5P_T0_17
set_property SLEW FAST [get_ports {ddr3_dq[25]}]
set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dq[25]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[25]}]
set_property PACKAGE_PIN AG29 [get_ports {ddr3_dq[25]}]

# PadFunction: IO_L5N_T0_17
set_property SLEW FAST [get_ports {ddr3_dq[26]}]
set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dq[26]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[26]}]
set_property PACKAGE_PIN AH29 [get_ports {ddr3_dq[26]}]

# PadFunction: IO_L4N_T0_17
set_property SLEW FAST [get_ports {ddr3_dq[27]}]
set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dq[27]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[27]}]
set_property PACKAGE_PIN AJ29 [get_ports {ddr3_dq[27]}]

# PadFunction: IO_L2P_T0_17
set_property SLEW FAST [get_ports {ddr3_dq[28]}]
set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dq[28]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[28]}]
set_property PACKAGE_PIN AK30 [get_ports {ddr3_dq[28]}]

# PadFunction: IO_L2N_T0_17
set_property SLEW FAST [get_ports {ddr3_dq[29]}]
set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dq[29]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[29]}]
set_property PACKAGE_PIN AK29 [get_ports {ddr3_dq[29]}]

# PadFunction: IO_L1P_T0_17
set_property SLEW FAST [get_ports {ddr3_dq[30]}]
set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dq[30]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[30]}]
set_property PACKAGE_PIN AK28 [get_ports {ddr3_dq[30]}]

# PadFunction: IO_L1N_T0_17
set_property SLEW FAST [get_ports {ddr3_dq[31]}]
set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dq[31]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[31]}]
set_property PACKAGE_PIN AG27 [get_ports {ddr3_dq[31]}]

# PadFunction: IO_L14P_T2_SRCC_15
set_property SLEW FAST [get_ports {ddr3_dq[32]}]
set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dq[32]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[32]}]
set_property PACKAGE_PIN AD18 [get_ports {ddr3_dq[32]}]

# PadFunction: IO_L16P_T2_A28_15
set_property SLEW FAST [get_ports {ddr3_dq[33]}]
set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dq[33]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[33]}]
set_property PACKAGE_PIN AD19 [get_ports {ddr3_dq[33]}]

# PadFunction: IO_L17N_T2_A25_15
set_property SLEW FAST [get_ports {ddr3_dq[34]}]
set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dq[34]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[34]}]
set_property PACKAGE_PIN AA18 [get_ports {ddr3_dq[34]}]

# PadFunction: IO_L17P_T2_A26_15
set_property SLEW FAST [get_ports {ddr3_dq[35]}]
set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dq[35]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[35]}]
set_property PACKAGE_PIN Y18 [get_ports {ddr3_dq[35]}]

# PadFunction: IO_L18P_T2_A24_15
set_property SLEW FAST [get_ports {ddr3_dq[36]}]
set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dq[36]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[36]}]
set_property PACKAGE_PIN AE18 [get_ports {ddr3_dq[36]}]

# PadFunction: IO_L16N_T2_A27_15
set_property SLEW FAST [get_ports {ddr3_dq[37]}]
set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dq[37]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[37]}]
set_property PACKAGE_PIN Y19 [get_ports {ddr3_dq[37]}]

# PadFunction: IO_L13N_T2_MRCC_15
set_property SLEW FAST [get_ports {ddr3_dq[38]}]
set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dq[38]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[38]}]
set_property PACKAGE_PIN AB17 [get_ports {ddr3_dq[38]}]

# PadFunction: IO_L14N_T2_SRCC_15
set_property SLEW FAST [get_ports {ddr3_dq[39]}]
set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dq[39]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[39]}]
set_property PACKAGE_PIN AA17 [get_ports {ddr3_dq[39]}]

# PadFunction: IO_L23N_T3_FWE_B_15
set_property SLEW FAST [get_ports {ddr3_dq[40]}]
set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dq[40]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[40]}]
set_property PACKAGE_PIN AH20 [get_ports {ddr3_dq[40]}]

# PadFunction: IO_L22N_T3_A16_15
set_property SLEW FAST [get_ports {ddr3_dq[41]}]
set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dq[41]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[41]}]
set_property PACKAGE_PIN AH19 [get_ports {ddr3_dq[41]}]

# PadFunction: IO_L23P_T3_FOE_B_15
set_property SLEW FAST [get_ports {ddr3_dq[42]}]
set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dq[42]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[42]}]
set_property PACKAGE_PIN AG19 [get_ports {ddr3_dq[42]}]

# PadFunction: IO_L24P_T3_RS1_15
set_property SLEW FAST [get_ports {ddr3_dq[43]}]
set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dq[43]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[43]}]
set_property PACKAGE_PIN AF18 [get_ports {ddr3_dq[43]}]

# PadFunction: IO_L19P_T3_A22_15
set_property SLEW FAST [get_ports {ddr3_dq[44]}]
set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dq[44]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[44]}]
set_property PACKAGE_PIN AJ18 [get_ports {ddr3_dq[44]}]

# PadFunction: IO_L20N_T3_A19_15
set_property SLEW FAST [get_ports {ddr3_dq[45]}]
set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dq[45]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[45]}]
set_property PACKAGE_PIN AK18 [get_ports {ddr3_dq[45]}]

# PadFunction: IO_L20P_T3_A20_15
set_property SLEW FAST [get_ports {ddr3_dq[46]}]
set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dq[46]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[46]}]
set_property PACKAGE_PIN AJ17 [get_ports {ddr3_dq[46]}]

# PadFunction: IO_L22P_T3_A17_15
set_property SLEW FAST [get_ports {ddr3_dq[47]}]
set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dq[47]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[47]}]
set_property PACKAGE_PIN AJ16 [get_ports {ddr3_dq[47]}]

# PadFunction: IO_L7N_T1_AD10N_15
set_property SLEW FAST [get_ports {ddr3_dq[48]}]
set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dq[48]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[48]}]
set_property PACKAGE_PIN AF16 [get_ports {ddr3_dq[48]}]

# PadFunction: IO_L7P_T1_AD10P_15
set_property SLEW FAST [get_ports {ddr3_dq[49]}]
set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dq[49]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[49]}]
set_property PACKAGE_PIN AE16 [get_ports {ddr3_dq[49]}]

# PadFunction: IO_L12P_T1_MRCC_AD5P_15
set_property SLEW FAST [get_ports {ddr3_dq[50]}]
set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dq[50]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[50]}]
set_property PACKAGE_PIN AE15 [get_ports {ddr3_dq[50]}]

# PadFunction: IO_L11N_T1_SRCC_AD12N_15
set_property SLEW FAST [get_ports {ddr3_dq[51]}]
set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dq[51]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[51]}]
set_property PACKAGE_PIN AF15 [get_ports {ddr3_dq[51]}]

# PadFunction: IO_L11P_T1_SRCC_AD12P_15
set_property SLEW FAST [get_ports {ddr3_dq[52]}]
set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dq[52]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[52]}]
set_property PACKAGE_PIN AC15 [get_ports {ddr3_dq[52]}]

# PadFunction: IO_L8N_T1_AD3N_15
set_property SLEW FAST [get_ports {ddr3_dq[53]}]
set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dq[53]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[53]}]
set_property PACKAGE_PIN AB15 [get_ports {ddr3_dq[53]}]

# PadFunction: IO_L10N_T1_AD4N_15
set_property SLEW FAST [get_ports {ddr3_dq[54]}]
set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dq[54]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[54]}]
set_property PACKAGE_PIN AC14 [get_ports {ddr3_dq[54]}]

# PadFunction: IO_L10P_T1_AD4P_15
set_property SLEW FAST [get_ports {ddr3_dq[55]}]
set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dq[55]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[55]}]
set_property PACKAGE_PIN AB14 [get_ports {ddr3_dq[55]}]

# PadFunction: IO_L2P_T0_AD8P_15
set_property SLEW FAST [get_ports {ddr3_dq[56]}]
set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dq[56]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[56]}]
set_property PACKAGE_PIN AH17 [get_ports {ddr3_dq[56]}]

# PadFunction: IO_L4N_T0_AD9N_15
set_property SLEW FAST [get_ports {ddr3_dq[57]}]
set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dq[57]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[57]}]
set_property PACKAGE_PIN AH16 [get_ports {ddr3_dq[57]}]

# PadFunction: IO_L5N_T0_AD2N_15
set_property SLEW FAST [get_ports {ddr3_dq[58]}]
set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dq[58]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[58]}]
set_property PACKAGE_PIN AK14 [get_ports {ddr3_dq[58]}]

# PadFunction: IO_L5P_T0_AD2P_15
set_property SLEW FAST [get_ports {ddr3_dq[59]}]
set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dq[59]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[59]}]
set_property PACKAGE_PIN AJ14 [get_ports {ddr3_dq[59]}]

# PadFunction: IO_L1P_T0_AD0P_15
set_property SLEW FAST [get_ports {ddr3_dq[60]}]
set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dq[60]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[60]}]
set_property PACKAGE_PIN AF17 [get_ports {ddr3_dq[60]}]

# PadFunction: IO_L1N_T0_AD0N_15
set_property SLEW FAST [get_ports {ddr3_dq[61]}]
set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dq[61]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[61]}]
set_property PACKAGE_PIN AG17 [get_ports {ddr3_dq[61]}]

# PadFunction: IO_L2N_T0_AD8N_15
set_property SLEW FAST [get_ports {ddr3_dq[62]}]
set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dq[62]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[62]}]
set_property PACKAGE_PIN AH15 [get_ports {ddr3_dq[62]}]

# PadFunction: IO_L6P_T0_15
set_property SLEW FAST [get_ports {ddr3_dq[63]}]
set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dq[63]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[63]}]
set_property PACKAGE_PIN AH14 [get_ports {ddr3_dq[63]}]

# PadFunction: IO_L11P_T1_SRCC_16
set_property SLEW FAST [get_ports {ddr3_addr[14]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[14]}]
set_property PACKAGE_PIN AK24 [get_ports {ddr3_addr[14]}]

# PadFunction: IO_L15P_T2_DQS_16
set_property SLEW FAST [get_ports {ddr3_addr[13]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[13]}]
set_property PACKAGE_PIN AD22 [get_ports {ddr3_addr[13]}]

# PadFunction: IO_L24N_T3_16
set_property SLEW FAST [get_ports {ddr3_addr[12]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[12]}]
set_property PACKAGE_PIN AD21 [get_ports {ddr3_addr[12]}]

# PadFunction: IO_L12N_T1_MRCC_16
set_property SLEW FAST [get_ports {ddr3_addr[11]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[11]}]
set_property PACKAGE_PIN AK25 [get_ports {ddr3_addr[11]}]

# PadFunction: IO_L16N_T2_16
set_property SLEW FAST [get_ports {ddr3_addr[10]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[10]}]
set_property PACKAGE_PIN AJ22 [get_ports {ddr3_addr[10]}]

# PadFunction: IO_L23P_T3_16
set_property SLEW FAST [get_ports {ddr3_addr[9]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[9]}]
set_property PACKAGE_PIN AB23 [get_ports {ddr3_addr[9]}]

# PadFunction: IO_L21P_T3_DQS_16
set_property SLEW FAST [get_ports {ddr3_addr[8]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[8]}]
set_property PACKAGE_PIN AE23 [get_ports {ddr3_addr[8]}]

# PadFunction: IO_L22P_T3_16
set_property SLEW FAST [get_ports {ddr3_addr[7]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[7]}]
set_property PACKAGE_PIN AJ24 [get_ports {ddr3_addr[7]}]

# PadFunction: IO_L23N_T3_16
set_property SLEW FAST [get_ports {ddr3_addr[6]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[6]}]
set_property PACKAGE_PIN AF23 [get_ports {ddr3_addr[6]}]

# PadFunction: IO_L21N_T3_DQS_16
set_property SLEW FAST [get_ports {ddr3_addr[5]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[5]}]
set_property PACKAGE_PIN AD23 [get_ports {ddr3_addr[5]}]

# PadFunction: IO_L22N_T3_16
set_property SLEW FAST [get_ports {ddr3_addr[4]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[4]}]
set_property PACKAGE_PIN AG23 [get_ports {ddr3_addr[4]}]

# PadFunction: IO_L20N_T3_16
set_property SLEW FAST [get_ports {ddr3_addr[3]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[3]}]
set_property PACKAGE_PIN AJ26 [get_ports {ddr3_addr[3]}]

# PadFunction: IO_L11N_T1_SRCC_16
set_property SLEW FAST [get_ports {ddr3_addr[2]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[2]}]
set_property PACKAGE_PIN AF22 [get_ports {ddr3_addr[2]}]

# PadFunction: IO_L20P_T3_16
set_property SLEW FAST [get_ports {ddr3_addr[1]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[1]}]
set_property PACKAGE_PIN AJ23 [get_ports {ddr3_addr[1]}]

# PadFunction: IO_L14N_T2_SRCC_16
set_property SLEW FAST [get_ports {ddr3_addr[0]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[0]}]
set_property PACKAGE_PIN AG22 [get_ports {ddr3_addr[0]}]

# PadFunction: IO_L19P_T3_16
set_property SLEW FAST [get_ports {ddr3_ba[2]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_ba[2]}]
set_property PACKAGE_PIN AC21 [get_ports {ddr3_ba[2]}]

# PadFunction: IO_L14P_T2_SRCC_16
set_property SLEW FAST [get_ports {ddr3_ba[1]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_ba[1]}]
set_property PACKAGE_PIN AF21 [get_ports {ddr3_ba[1]}]

# PadFunction: IO_L16P_T2_16
set_property SLEW FAST [get_ports {ddr3_ba[0]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_ba[0]}]
set_property PACKAGE_PIN AK23 [get_ports {ddr3_ba[0]}]

# PadFunction: IO_L10N_T1_16
set_property SLEW FAST [get_ports ddr3_ras_n]
set_property IOSTANDARD SSTL15 [get_ports ddr3_ras_n]
set_property PACKAGE_PIN AF20 [get_ports ddr3_ras_n]

# PadFunction: IO_L17N_T2_16
set_property SLEW FAST [get_ports ddr3_cas_n]
set_property IOSTANDARD SSTL15 [get_ports ddr3_cas_n]
set_property PACKAGE_PIN AK21 [get_ports ddr3_cas_n]

# PadFunction: IO_L15N_T2_DQS_16
set_property SLEW FAST [get_ports ddr3_we_n]
set_property IOSTANDARD SSTL15 [get_ports ddr3_we_n]
set_property PACKAGE_PIN AJ21 [get_ports ddr3_we_n]

# PadFunction: IO_L13N_T2_MRCC_16
set_property SLEW FAST [get_ports ddr3_reset_n]
set_property IOSTANDARD LVCMOS15 [get_ports ddr3_reset_n]
set_property PACKAGE_PIN Y21 [get_ports ddr3_reset_n]

# PadFunction: IO_L8N_T1_16
set_property SLEW FAST [get_ports {ddr3_cke[0]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_cke[0]}]
set_property PACKAGE_PIN AB22 [get_ports {ddr3_cke[0]}]

# PadFunction: IO_L18P_T2_16
set_property SLEW FAST [get_ports {ddr3_odt[0]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_odt[0]}]
set_property PACKAGE_PIN AG20 [get_ports {ddr3_odt[0]}]

# PadFunction: IO_L17P_T2_16
set_property SLEW FAST [get_ports {ddr3_cs_n[0]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_cs_n[0]}]
set_property PACKAGE_PIN AG24 [get_ports {ddr3_cs_n[0]}]

# PadFunction: IO_L23P_T3_17
set_property SLEW FAST [get_ports {ddr3_dm[0]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dm[0]}]
set_property PACKAGE_PIN AA28 [get_ports {ddr3_dm[0]}]

# PadFunction: IO_L17N_T2_17
set_property SLEW FAST [get_ports {ddr3_dm[1]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dm[1]}]
set_property PACKAGE_PIN AA27 [get_ports {ddr3_dm[1]}]

# PadFunction: IO_L11N_T1_SRCC_17
set_property SLEW FAST [get_ports {ddr3_dm[2]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dm[2]}]
set_property PACKAGE_PIN AE28 [get_ports {ddr3_dm[2]}]

# PadFunction: IO_L4P_T0_17
set_property SLEW FAST [get_ports {ddr3_dm[3]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dm[3]}]
set_property PACKAGE_PIN AH30 [get_ports {ddr3_dm[3]}]

# PadFunction: IO_L13P_T2_MRCC_15
set_property SLEW FAST [get_ports {ddr3_dm[4]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dm[4]}]
set_property PACKAGE_PIN AB18 [get_ports {ddr3_dm[4]}]

# PadFunction: IO_L24N_T3_RS0_15
set_property SLEW FAST [get_ports {ddr3_dm[5]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dm[5]}]
set_property PACKAGE_PIN AJ19 [get_ports {ddr3_dm[5]}]

# PadFunction: IO_L8P_T1_AD3P_15
set_property SLEW FAST [get_ports {ddr3_dm[6]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dm[6]}]
set_property PACKAGE_PIN AD14 [get_ports {ddr3_dm[6]}]

# PadFunction: IO_L4P_T0_AD9P_15
set_property SLEW FAST [get_ports {ddr3_dm[7]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dm[7]}]
set_property PACKAGE_PIN AK16 [get_ports {ddr3_dm[7]}]

# PadFunction: IO_L21P_T3_DQS_17
set_property SLEW FAST [get_ports {ddr3_dqs_p[0]}]
set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dqs_p[0]}]
set_property IOSTANDARD DIFF_SSTL15 [get_ports {ddr3_dqs_p[0]}]

# PadFunction: IO_L21N_T3_DQS_17
set_property SLEW FAST [get_ports {ddr3_dqs_n[0]}]
set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dqs_n[0]}]
set_property IOSTANDARD DIFF_SSTL15 [get_ports {ddr3_dqs_n[0]}]
set_property PACKAGE_PIN Y30 [get_ports {ddr3_dqs_p[0]}]
set_property PACKAGE_PIN AA30 [get_ports {ddr3_dqs_n[0]}]

# PadFunction: IO_L15P_T2_DQS_17
set_property SLEW FAST [get_ports {ddr3_dqs_p[1]}]
set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dqs_p[1]}]
set_property IOSTANDARD DIFF_SSTL15 [get_ports {ddr3_dqs_p[1]}]

# PadFunction: IO_L15N_T2_DQS_17
set_property SLEW FAST [get_ports {ddr3_dqs_n[1]}]
set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dqs_n[1]}]
set_property IOSTANDARD DIFF_SSTL15 [get_ports {ddr3_dqs_n[1]}]
set_property PACKAGE_PIN AB25 [get_ports {ddr3_dqs_p[1]}]
set_property PACKAGE_PIN AC25 [get_ports {ddr3_dqs_n[1]}]

# PadFunction: IO_L9P_T1_DQS_17
set_property SLEW FAST [get_ports {ddr3_dqs_p[2]}]
set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dqs_p[2]}]
set_property IOSTANDARD DIFF_SSTL15 [get_ports {ddr3_dqs_p[2]}]

# PadFunction: IO_L9N_T1_DQS_17
set_property SLEW FAST [get_ports {ddr3_dqs_n[2]}]
set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dqs_n[2]}]
set_property IOSTANDARD DIFF_SSTL15 [get_ports {ddr3_dqs_n[2]}]
set_property PACKAGE_PIN AC29 [get_ports {ddr3_dqs_p[2]}]
set_property PACKAGE_PIN AC30 [get_ports {ddr3_dqs_n[2]}]

# PadFunction: IO_L3P_T0_DQS_17
set_property SLEW FAST [get_ports {ddr3_dqs_p[3]}]
set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dqs_p[3]}]
set_property IOSTANDARD DIFF_SSTL15 [get_ports {ddr3_dqs_p[3]}]

# PadFunction: IO_L3N_T0_DQS_17
set_property SLEW FAST [get_ports {ddr3_dqs_n[3]}]
set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dqs_n[3]}]
set_property IOSTANDARD DIFF_SSTL15 [get_ports {ddr3_dqs_n[3]}]
set_property PACKAGE_PIN AJ27 [get_ports {ddr3_dqs_p[3]}]
set_property PACKAGE_PIN AJ28 [get_ports {ddr3_dqs_n[3]}]

# PadFunction: IO_L15P_T2_DQS_15
set_property SLEW FAST [get_ports {ddr3_dqs_p[4]}]
set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dqs_p[4]}]
set_property IOSTANDARD DIFF_SSTL15 [get_ports {ddr3_dqs_p[4]}]

# PadFunction: IO_L15N_T2_DQS_ADV_B_15
set_property SLEW FAST [get_ports {ddr3_dqs_n[4]}]
set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dqs_n[4]}]
set_property IOSTANDARD DIFF_SSTL15 [get_ports {ddr3_dqs_n[4]}]
set_property PACKAGE_PIN AC17 [get_ports {ddr3_dqs_p[4]}]
set_property PACKAGE_PIN AD17 [get_ports {ddr3_dqs_n[4]}]

# PadFunction: IO_L21P_T3_DQS_15
set_property SLEW FAST [get_ports {ddr3_dqs_p[5]}]
set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dqs_p[5]}]
set_property IOSTANDARD DIFF_SSTL15 [get_ports {ddr3_dqs_p[5]}]

# PadFunction: IO_L21N_T3_DQS_A18_15
set_property SLEW FAST [get_ports {ddr3_dqs_n[5]}]
set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dqs_n[5]}]
set_property IOSTANDARD DIFF_SSTL15 [get_ports {ddr3_dqs_n[5]}]
set_property PACKAGE_PIN AK19 [get_ports {ddr3_dqs_p[5]}]
set_property PACKAGE_PIN AK20 [get_ports {ddr3_dqs_n[5]}]

# PadFunction: IO_L9P_T1_DQS_AD11P_15
set_property SLEW FAST [get_ports {ddr3_dqs_p[6]}]
set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dqs_p[6]}]
set_property IOSTANDARD DIFF_SSTL15 [get_ports {ddr3_dqs_p[6]}]

# PadFunction: IO_L9N_T1_DQS_AD11N_15
set_property SLEW FAST [get_ports {ddr3_dqs_n[6]}]
set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dqs_n[6]}]
set_property IOSTANDARD DIFF_SSTL15 [get_ports {ddr3_dqs_n[6]}]
set_property PACKAGE_PIN AC16 [get_ports {ddr3_dqs_p[6]}]
set_property PACKAGE_PIN AD16 [get_ports {ddr3_dqs_n[6]}]

# PadFunction: IO_L3P_T0_DQS_AD1P_15
set_property SLEW FAST [get_ports {ddr3_dqs_p[7]}]
set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dqs_p[7]}]
set_property IOSTANDARD DIFF_SSTL15 [get_ports {ddr3_dqs_p[7]}]

# PadFunction: IO_L3N_T0_DQS_AD1N_15
set_property SLEW FAST [get_ports {ddr3_dqs_n[7]}]
set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dqs_n[7]}]
set_property IOSTANDARD DIFF_SSTL15 [get_ports {ddr3_dqs_n[7]}]
set_property PACKAGE_PIN AG14 [get_ports {ddr3_dqs_p[7]}]
set_property PACKAGE_PIN AG15 [get_ports {ddr3_dqs_n[7]}]

# PadFunction: IO_L9P_T1_DQS_16
set_property SLEW FAST [get_ports {ddr3_ck_p[0]}]
set_property IOSTANDARD DIFF_SSTL15 [get_ports {ddr3_ck_p[0]}]

# PadFunction: IO_L9N_T1_DQS_16
set_property SLEW FAST [get_ports {ddr3_ck_n[0]}]
set_property IOSTANDARD DIFF_SSTL15 [get_ports {ddr3_ck_n[0]}]
set_property PACKAGE_PIN AA22 [get_ports {ddr3_ck_p[0]}]
set_property PACKAGE_PIN AA23 [get_ports {ddr3_ck_n[0]}]


set_property LOC PHASER_OUT_PHY_X0Y3 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out}]
set_property LOC PHASER_OUT_PHY_X0Y2 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out}]
set_property LOC PHASER_OUT_PHY_X0Y1 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_out}]
set_property LOC PHASER_OUT_PHY_X0Y0 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_out}]
set_property LOC PHASER_OUT_PHY_X0Y7 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out}]
set_property LOC PHASER_OUT_PHY_X0Y5 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_out}]
set_property LOC PHASER_OUT_PHY_X0Y4 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_out}]
set_property LOC PHASER_OUT_PHY_X0Y11 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out}]
set_property LOC PHASER_OUT_PHY_X0Y10 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out}]
set_property LOC PHASER_OUT_PHY_X0Y9 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_out}]
set_property LOC PHASER_OUT_PHY_X0Y8 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_out}]

set_property LOC PHASER_IN_PHY_X0Y3 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_in_gen.phaser_in}]
set_property LOC PHASER_IN_PHY_X0Y2 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_in_gen.phaser_in}]
set_property LOC PHASER_IN_PHY_X0Y1 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_in_gen.phaser_in}]
set_property LOC PHASER_IN_PHY_X0Y0 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_in_gen.phaser_in}]
## set_property LOC PHASER_IN_PHY_X0Y7 [get_cells  -hier -filter {NAME =~ */ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_in_gen.phaser_in}]
## set_property LOC PHASER_IN_PHY_X0Y5 [get_cells  -hier -filter {NAME =~ */ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_in_gen.phaser_in}]
## set_property LOC PHASER_IN_PHY_X0Y4 [get_cells  -hier -filter {NAME =~ */ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_in_gen.phaser_in}]
set_property LOC PHASER_IN_PHY_X0Y11 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_in_gen.phaser_in}]
set_property LOC PHASER_IN_PHY_X0Y10 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_in_gen.phaser_in}]
set_property LOC PHASER_IN_PHY_X0Y9 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_in_gen.phaser_in}]
set_property LOC PHASER_IN_PHY_X0Y8 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_in_gen.phaser_in}]



set_property LOC OUT_FIFO_X0Y3 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/out_fifo}]
set_property LOC OUT_FIFO_X0Y2 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/out_fifo}]
set_property LOC OUT_FIFO_X0Y1 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/out_fifo}]
set_property LOC OUT_FIFO_X0Y0 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/out_fifo}]
set_property LOC OUT_FIFO_X0Y7 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/out_fifo}]
set_property LOC OUT_FIFO_X0Y5 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/out_fifo}]
set_property LOC OUT_FIFO_X0Y4 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/out_fifo}]
set_property LOC OUT_FIFO_X0Y11 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/out_fifo}]
set_property LOC OUT_FIFO_X0Y10 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/out_fifo}]
set_property LOC OUT_FIFO_X0Y9 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/out_fifo}]
set_property LOC OUT_FIFO_X0Y8 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/out_fifo}]

set_property LOC IN_FIFO_X0Y3 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/in_fifo_gen.in_fifo}]
set_property LOC IN_FIFO_X0Y2 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/in_fifo_gen.in_fifo}]
set_property LOC IN_FIFO_X0Y1 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/in_fifo_gen.in_fifo}]
set_property LOC IN_FIFO_X0Y0 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/in_fifo_gen.in_fifo}]
set_property LOC IN_FIFO_X0Y11 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/in_fifo_gen.in_fifo}]
set_property LOC IN_FIFO_X0Y10 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/in_fifo_gen.in_fifo}]
set_property LOC IN_FIFO_X0Y9 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/in_fifo_gen.in_fifo}]
set_property LOC IN_FIFO_X0Y8 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/in_fifo_gen.in_fifo}]

set_property LOC PHY_CONTROL_X0Y0 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_2.u_ddr_phy_4lanes/phy_control_i}]
set_property LOC PHY_CONTROL_X0Y1 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_1.u_ddr_phy_4lanes/phy_control_i}]
set_property LOC PHY_CONTROL_X0Y2 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/phy_control_i}]

set_property LOC PHASER_REF_X0Y0 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_2.u_ddr_phy_4lanes/phaser_ref_i}]
set_property LOC PHASER_REF_X0Y1 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_1.u_ddr_phy_4lanes/phaser_ref_i}]
set_property LOC PHASER_REF_X0Y2 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/phaser_ref_i}]

set_property LOC OLOGIC_X0Y43 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/*slave_ts}]
set_property LOC OLOGIC_X0Y31 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/*slave_ts}]
set_property LOC OLOGIC_X0Y19 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/ddr_byte_group_io/*slave_ts}]
set_property LOC OLOGIC_X0Y7 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/ddr_byte_group_io/*slave_ts}]
set_property LOC OLOGIC_X0Y143 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/*slave_ts}]
set_property LOC OLOGIC_X0Y131 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/*slave_ts}]
set_property LOC OLOGIC_X0Y119 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/ddr_byte_group_io/*slave_ts}]
set_property LOC OLOGIC_X0Y107 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/ddr_byte_group_io/*slave_ts}]

set_property LOC PLLE2_ADV_X0Y1 [get_cells -hier -filter {NAME =~ */u_ddr3_infrastructure/plle2_i}]
set_property LOC MMCME2_ADV_X0Y1 [get_cells -hier -filter {NAME =~ */u_ddr3_infrastructure/gen_mmcm.mmcm_i}]


set_multicycle_path -setup -from [get_cells -hier -filter {NAME =~ */mc0/mc_read_idle_r_reg}] -to [get_cells -hier -filter {NAME =~ */input_[?].iserdes_dq_.iserdesdq}] 6

set_multicycle_path -hold -from [get_cells -hier -filter {NAME =~ */mc0/mc_read_idle_r_reg}] -to [get_cells -hier -filter {NAME =~ */input_[?].iserdes_dq_.iserdesdq}] 5

set_false_path -through [get_pins -filter {NAME =~ */DQSFOUND} -of [get_cells -hier -filter {REF_NAME == PHASER_IN_PHY}]]

set_multicycle_path -setup -start -through [get_pins -filter {NAME =~ */OSERDESRST} -of [get_cells -hier -filter {REF_NAME == PHASER_OUT_PHY}]] 2
set_multicycle_path -hold -start -through [get_pins -filter {NAME =~ */OSERDESRST} -of [get_cells -hier -filter {REF_NAME == PHASER_OUT_PHY}]] 1

set_max_delay -datapath_only -from [get_cells -hier -filter {NAME =~ *temp_mon_enabled.u_tempmon/* && IS_SEQUENTIAL}] -to [get_cells -hier -filter {NAME =~ *temp_mon_enabled.u_tempmon/device_temp_sync_r1*}] 20.000
set_max_delay -datapath_only -from [get_cells -hier *rstdiv0_sync_r1_reg*] -to [get_pins -filter {NAME =~ */RESET} -of [get_cells -hier -filter {REF_NAME == PHY_CONTROL}]] 5.000
set_false_path -through [get_pins -hier -filter {NAME =~ */u_iodelay_ctrl/sys_rst}]

set_max_delay -datapath_only -from [get_cells -hier -filter {NAME =~ *ddr3_infrastructure/rstdiv0_sync_r1_reg*}] -to [get_cells -hier -filter {NAME =~ *temp_mon_enabled.u_tempmon/xadc_supplied_temperature.rst_r1*}] 20.000

set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
set_property BITSTREAM.CONFIG.CCLK_TRISTATE TRUE [current_design]
set_property BITSTREAM.CONFIG.CONFIGRATE 50 [current_design]
set_property CONFIG_VOLTAGE 3.3 [current_design]
set_property CFGBVS VCCO [current_design]
set_property BITSTREAM.CONFIG.SPI_32BIT_ADDR YES [current_design]
set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]
set_property BITSTREAM.CONFIG.SPI_FALL_EDGE YES [current_design]
set_property BITSTREAM.CONFIG.UNUSEDPIN PULLUP [current_design]