Skip to content

Instantly share code, notes, and snippets.

@heijligen

heijligen/blink2.dump

Last active January 13, 2020 13:22
Show Gist options
  • Star 0 You must be signed in to star a gist
  • Fork 0 You must be signed in to fork a gist
  • Save heijligen/ff7a64b1f559de43a2509d503b99edb2 to your computer and use it in GitHub Desktop.
Save heijligen/ff7a64b1f559de43a2509d503b99edb2 to your computer and use it in GitHub Desktop.
Download ZIP
Raw
blink2.dump
This file has been truncated, but you can view the full file.
autoidx 262
attribute \blackbox 1
attribute \cells_not_processed 1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_sim.v:635"
module \AND2B1L
parameter \IS_SRI_INVERTED
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_sim.v:637"
wire input 2 \DI
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_sim.v:636"
wire output 1 \O
attribute \invertible_pin "IS_SRI_INVERTED"
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_sim.v:639"
wire input 3 \SRI
end
attribute \blackbox 1
attribute \keep 1
attribute \cells_not_processed 1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:6761"
module \BITSLICE_CONTROL
parameter \CTRL_CLK
parameter \DIV_MODE
parameter \EN_CLK_TO_EXT_NORTH
parameter \EN_CLK_TO_EXT_SOUTH
parameter \EN_DYN_ODLY_MODE
parameter \EN_OTHER_NCLK
parameter \EN_OTHER_PCLK
parameter \IDLY_VT_TRACK
parameter \INV_RXCLK
parameter \ODLY_VT_TRACK
parameter \QDLY_VT_TRACK
parameter \READ_IDLE_COUNT
parameter \REFCLK_SRC
parameter \ROUNDING_FACTOR
parameter \RXGATE_EXTEND
parameter \RX_CLK_PHASE_N
parameter \RX_CLK_PHASE_P
parameter \RX_GATING
parameter \SELF_CALIBRATE
parameter \SERIAL_MODE
parameter \SIM_DEVICE
parameter \SIM_SPEEDUP
parameter \SIM_VERSION
parameter \TX_GATING
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:6810"
wire input 25 \CLK_FROM_EXT
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:6786"
wire output 1 \CLK_TO_EXT_NORTH
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:6787"
wire output 2 \CLK_TO_EXT_SOUTH
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:6788"
wire output 3 \DLY_RDY
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:6789"
wire width 7 output 4 \DYN_DCI
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:6811"
wire input 26 \EN_VTC
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:6812"
wire input 27 \NCLK_NIBBLE_IN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:6790"
wire output 5 \NCLK_NIBBLE_OUT
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:6813"
wire input 28 \PCLK_NIBBLE_IN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:6791"
wire output 6 \PCLK_NIBBLE_OUT
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:6814"
wire width 4 input 29 \PHY_RDCS0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:6815"
wire width 4 input 30 \PHY_RDCS1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:6816"
wire width 4 input 31 \PHY_RDEN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:6817"
wire width 4 input 32 \PHY_WRCS0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:6818"
wire width 4 input 33 \PHY_WRCS1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:6819"
wire input 34 \PLL_CLK
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:6820"
wire input 35 \REFCLK
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:6821"
wire width 6 input 36 \RIU_ADDR
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:6822"
wire input 37 \RIU_CLK
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:6823"
wire input 38 \RIU_NIBBLE_SEL
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:6792"
wire width 16 output 7 \RIU_RD_DATA
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:6793"
wire output 8 \RIU_VALID
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:6824"
wire width 16 input 39 \RIU_WR_DATA
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:6825"
wire input 40 \RIU_WR_EN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:6826"
wire input 41 \RST
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:6827"
wire width 40 input 42 \RX_BIT_CTRL_IN0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:6828"
wire width 40 input 43 \RX_BIT_CTRL_IN1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:6829"
wire width 40 input 44 \RX_BIT_CTRL_IN2
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:6830"
wire width 40 input 45 \RX_BIT_CTRL_IN3
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:6831"
wire width 40 input 46 \RX_BIT_CTRL_IN4
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:6832"
wire width 40 input 47 \RX_BIT_CTRL_IN5
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:6833"
wire width 40 input 48 \RX_BIT_CTRL_IN6
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:6794"
wire width 40 output 9 \RX_BIT_CTRL_OUT0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:6795"
wire width 40 output 10 \RX_BIT_CTRL_OUT1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:6796"
wire width 40 output 11 \RX_BIT_CTRL_OUT2
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:6797"
wire width 40 output 12 \RX_BIT_CTRL_OUT3
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:6798"
wire width 40 output 13 \RX_BIT_CTRL_OUT4
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:6799"
wire width 40 output 14 \RX_BIT_CTRL_OUT5
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:6800"
wire width 40 output 15 \RX_BIT_CTRL_OUT6
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:6834"
wire width 4 input 49 \TBYTE_IN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:6835"
wire width 40 input 50 \TX_BIT_CTRL_IN0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:6836"
wire width 40 input 51 \TX_BIT_CTRL_IN1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:6837"
wire width 40 input 52 \TX_BIT_CTRL_IN2
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:6838"
wire width 40 input 53 \TX_BIT_CTRL_IN3
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:6839"
wire width 40 input 54 \TX_BIT_CTRL_IN4
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:6840"
wire width 40 input 55 \TX_BIT_CTRL_IN5
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:6841"
wire width 40 input 56 \TX_BIT_CTRL_IN6
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:6842"
wire width 40 input 57 \TX_BIT_CTRL_IN_TRI
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:6801"
wire width 40 output 16 \TX_BIT_CTRL_OUT0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:6802"
wire width 40 output 17 \TX_BIT_CTRL_OUT1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:6803"
wire width 40 output 18 \TX_BIT_CTRL_OUT2
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:6804"
wire width 40 output 19 \TX_BIT_CTRL_OUT3
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:6805"
wire width 40 output 20 \TX_BIT_CTRL_OUT4
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:6806"
wire width 40 output 21 \TX_BIT_CTRL_OUT5
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:6807"
wire width 40 output 22 \TX_BIT_CTRL_OUT6
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:6808"
wire width 40 output 23 \TX_BIT_CTRL_OUT_TRI
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:6809"
wire output 24 \VTC_RDY
end
attribute \blackbox 1
attribute \keep 1
attribute \cells_not_processed 1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:9519"
module \BSCANE2
parameter \DISABLE_JTAG
parameter \JTAG_CHAIN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:9522"
wire output 1 \CAPTURE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:9523"
wire output 2 \DRCK
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:9524"
wire output 3 \RESET
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:9525"
wire output 4 \RUNTEST
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:9526"
wire output 5 \SEL
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:9527"
wire output 6 \SHIFT
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:9528"
wire output 7 \TCK
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:9529"
wire output 8 \TDI
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:9532"
wire input 11 \TDO
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:9530"
wire output 9 \TMS
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:9531"
wire output 10 \UPDATE
end
attribute \blackbox 1
attribute \keep 1
attribute \cells_not_processed 1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:9428"
module \BSCAN_SPARTAN3
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:9429"
wire output 1 \CAPTURE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:9430"
wire output 2 \DRCK1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:9431"
wire output 3 \DRCK2
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:9432"
wire output 4 \RESET
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:9433"
wire output 5 \SEL1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:9434"
wire output 6 \SEL2
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:9435"
wire output 7 \SHIFT
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:9436"
wire output 8 \TDI
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:9438"
wire input 10 \TDO1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:9439"
wire input 11 \TDO2
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:9437"
wire output 9 \UPDATE
end
attribute \blackbox 1
attribute \keep 1
attribute \cells_not_processed 1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:9443"
module \BSCAN_SPARTAN3A
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:9444"
wire output 1 \CAPTURE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:9445"
wire output 2 \DRCK1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:9446"
wire output 3 \DRCK2
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:9447"
wire output 4 \RESET
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:9448"
wire output 5 \SEL1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:9449"
wire output 6 \SEL2
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:9450"
wire output 7 \SHIFT
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:9451"
wire output 8 \TCK
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:9452"
wire output 9 \TDI
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:9455"
wire input 12 \TDO1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:9456"
wire input 13 \TDO2
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:9453"
wire output 10 \TMS
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:9454"
wire output 11 \UPDATE
end
attribute \blackbox 1
attribute \keep 1
attribute \cells_not_processed 1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:9460"
module \BSCAN_SPARTAN6
parameter \JTAG_CHAIN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:9462"
wire output 1 \CAPTURE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:9463"
wire output 2 \DRCK
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:9464"
wire output 3 \RESET
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:9465"
wire output 4 \RUNTEST
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:9466"
wire output 5 \SEL
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:9467"
wire output 6 \SHIFT
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:9468"
wire output 7 \TCK
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:9469"
wire output 8 \TDI
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:9472"
wire input 11 \TDO
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:9470"
wire output 9 \TMS
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:9471"
wire output 10 \UPDATE
end
attribute \blackbox 1
attribute \keep 1
attribute \cells_not_processed 1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:9476"
module \BSCAN_VIRTEX4
parameter \JTAG_CHAIN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:9478"
wire output 1 \CAPTURE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:9479"
wire output 2 \DRCK
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:9480"
wire output 3 \RESET
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:9481"
wire output 4 \SEL
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:9482"
wire output 5 \SHIFT
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:9483"
wire output 6 \TDI
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:9485"
wire input 8 \TDO
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:9484"
wire output 7 \UPDATE
end
attribute \blackbox 1
attribute \keep 1
attribute \cells_not_processed 1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:9489"
module \BSCAN_VIRTEX5
parameter \JTAG_CHAIN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:9491"
wire output 1 \CAPTURE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:9492"
wire output 2 \DRCK
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:9493"
wire output 3 \RESET
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:9494"
wire output 4 \SEL
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:9495"
wire output 5 \SHIFT
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:9496"
wire output 6 \TDI
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:9498"
wire input 8 \TDO
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:9497"
wire output 7 \UPDATE
end
attribute \blackbox 1
attribute \keep 1
attribute \cells_not_processed 1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:9502"
module \BSCAN_VIRTEX6
parameter \DISABLE_JTAG
parameter \JTAG_CHAIN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:9505"
wire output 1 \CAPTURE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:9506"
wire output 2 \DRCK
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:9507"
wire output 3 \RESET
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:9508"
wire output 4 \RUNTEST
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:9509"
wire output 5 \SEL
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:9510"
wire output 6 \SHIFT
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:9511"
wire output 7 \TCK
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:9512"
wire output 8 \TDI
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:9515"
wire input 11 \TDO
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:9513"
wire output 9 \TMS
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:9514"
wire output 10 \UPDATE
end
attribute \blackbox 1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_sim.v:90"
module \BUFG
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_sim.v:93"
wire input 2 \I
attribute \clkbuf_driver 1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_sim.v:92"
wire output 1 \O
end
attribute \blackbox 1
attribute \cells_not_processed 1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7658"
module \BUFGCE
parameter \CE_TYPE
parameter \IS_CE_INVERTED
parameter \IS_I_INVERTED
attribute \invertible_pin "IS_CE_INVERTED"
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7665"
wire input 2 \CE
attribute \invertible_pin "IS_I_INVERTED"
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7667"
wire input 3 \I
attribute \clkbuf_driver 1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7663"
wire output 1 \O
end
attribute \blackbox 1
attribute \cells_not_processed 1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7670"
module \BUFGCE_1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7673"
wire input 2 \CE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7674"
wire input 3 \I
attribute \clkbuf_driver 1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7672"
wire output 1 \O
end
attribute \blackbox 1
attribute \cells_not_processed 1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7736"
module \BUFGCE_DIV
parameter \BUFGCE_DIVIDE
parameter \IS_CE_INVERTED
parameter \IS_CLR_INVERTED
parameter \IS_I_INVERTED
attribute \invertible_pin "IS_CE_INVERTED"
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7744"
wire input 2 \CE
attribute \invertible_pin "IS_CLR_INVERTED"
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7746"
wire input 3 \CLR
attribute \invertible_pin "IS_I_INVERTED"
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7748"
wire input 4 \I
attribute \clkbuf_driver 1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7742"
wire output 1 \O
end
attribute \blackbox 1
attribute \cells_not_processed 1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_sim.v:98"
module \BUFGCTRL
parameter \INIT_OUT
parameter \IS_CE0_INVERTED
parameter \IS_CE1_INVERTED
parameter \IS_IGNORE0_INVERTED
parameter \IS_IGNORE1_INVERTED
parameter \IS_S0_INVERTED
parameter \IS_S1_INVERTED
parameter \PRESELECT_I0
parameter \PRESELECT_I1
attribute \invertible_pin "IS_CE0_INVERTED"
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_sim.v:107"
wire input 6 \CE0
attribute \invertible_pin "IS_CE1_INVERTED"
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_sim.v:109"
wire input 7 \CE1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_sim.v:101"
wire input 2 \I0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_sim.v:101"
wire input 3 \I1
attribute \invertible_pin "IS_IGNORE0_INVERTED"
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_sim.v:111"
wire input 8 \IGNORE0
attribute \invertible_pin "IS_IGNORE1_INVERTED"
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_sim.v:113"
wire input 9 \IGNORE1
attribute \clkbuf_driver 1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_sim.v:100"
wire output 1 \O
attribute \invertible_pin "IS_S0_INVERTED"
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_sim.v:103"
wire input 4 \S0
attribute \invertible_pin "IS_S1_INVERTED"
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_sim.v:105"
wire input 5 \S1
end
attribute \blackbox 1
attribute \cells_not_processed 1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7677"
module \BUFGMUX
parameter \CLK_SEL_TYPE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7681"
wire input 2 \I0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7682"
wire input 3 \I1
attribute \clkbuf_driver 1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7680"
wire output 1 \O
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7683"
wire input 4 \S
end
attribute \blackbox 1
attribute \cells_not_processed 1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7686"
module \BUFGMUX_1
parameter \CLK_SEL_TYPE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7690"
wire input 2 \I0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7691"
wire input 3 \I1
attribute \clkbuf_driver 1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7689"
wire output 1 \O
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7692"
wire input 4 \S
end
attribute \blackbox 1
attribute \cells_not_processed 1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7695"
module \BUFGMUX_CTRL
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7698"
wire input 2 \I0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7699"
wire input 3 \I1
attribute \clkbuf_driver 1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7697"
wire output 1 \O
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7700"
wire input 4 \S
end
attribute \blackbox 1
attribute \cells_not_processed 1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7703"
module \BUFGMUX_VIRTEX4
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7706"
wire input 2 \I0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7707"
wire input 3 \I1
attribute \clkbuf_driver 1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7705"
wire output 1 \O
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7708"
wire input 4 \S
end
attribute \blackbox 1
attribute \cells_not_processed 1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7711"
module \BUFG_GT
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7714"
wire input 2 \CE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7715"
wire input 3 \CEMASK
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7716"
wire input 4 \CLR
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7717"
wire input 5 \CLRMASK
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7718"
wire width 3 input 6 \DIV
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7719"
wire input 7 \I
attribute \clkbuf_driver 1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7713"
wire output 1 \O
end
attribute \blackbox 1
attribute \cells_not_processed 1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7722"
module \BUFG_GT_SYNC
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7725"
wire input 3 \CE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7723"
wire output 1 \CESYNC
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7726"
wire input 4 \CLK
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7727"
wire input 5 \CLR
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7724"
wire output 2 \CLRSYNC
end
attribute \blackbox 1
attribute \cells_not_processed 1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7730"
module \BUFG_PS
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7733"
wire input 2 \I
attribute \clkbuf_driver 1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7732"
wire output 1 \O
end
attribute \blackbox 1
attribute \cells_not_processed 1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7751"
module \BUFH
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7754"
wire input 2 \I
attribute \clkbuf_driver 1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7753"
wire output 1 \O
end
attribute \blackbox 1
attribute \cells_not_processed 1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_sim.v:134"
module \BUFHCE
parameter \CE_TYPE
parameter \INIT_OUT
parameter \IS_CE_INVERTED
attribute \invertible_pin "IS_CE_INVERTED"
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_sim.v:139"
wire input 3 \CE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_sim.v:137"
wire input 2 \I
attribute \clkbuf_driver 1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_sim.v:136"
wire output 1 \O
end
attribute \blackbox 1
attribute \cells_not_processed 1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7816"
module \BUFIO
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7819"
wire input 2 \I
attribute \clkbuf_driver 1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7818"
wire output 1 \O
end
attribute \blackbox 1
attribute \cells_not_processed 1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7757"
module \BUFIO2
parameter \DIVIDE
parameter \DIVIDE_BYPASS
parameter \I_INVERT
parameter \USE_DOUBLER
attribute \clkbuf_driver 1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7763"
wire output 1 \DIVCLK
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7767"
wire input 4 \I
attribute \clkbuf_driver 1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7765"
wire output 2 \IOCLK
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7766"
wire output 3 \SERDESSTROBE
end
attribute \blackbox 1
attribute \cells_not_processed 1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7781"
module \BUFIO2FB
parameter \DIVIDE_BYPASS
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7785"
wire input 2 \I
attribute \clkbuf_driver 1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7784"
wire output 1 \O
end
attribute \blackbox 1
attribute \cells_not_processed 1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7770"
module \BUFIO2_2CLK
parameter \DIVIDE
attribute \clkbuf_driver 1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7773"
wire output 1 \DIVCLK
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7777"
wire input 4 \I
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7778"
wire input 5 \IB
attribute \clkbuf_driver 1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7775"
wire output 2 \IOCLK
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7776"
wire output 3 \SERDESSTROBE
end
attribute \blackbox 1
attribute \cells_not_processed 1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7822"
module \BUFIODQS
parameter \DQSMASK_ENABLE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7826"
wire input 2 \DQSMASK
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7827"
wire input 3 \I
attribute \clkbuf_driver 1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7825"
wire output 1 \O
end
attribute \blackbox 1
attribute \cells_not_processed 1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7840"
module \BUFMR
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7843"
wire input 2 \I
attribute \clkbuf_driver 1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7842"
wire output 1 \O
end
attribute \blackbox 1
attribute \cells_not_processed 1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7846"
module \BUFMRCE
parameter \CE_TYPE
parameter \INIT_OUT
parameter \IS_CE_INVERTED
attribute \invertible_pin "IS_CE_INVERTED"
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7853"
wire input 2 \CE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7854"
wire input 3 \I
attribute \clkbuf_driver 1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7851"
wire output 1 \O
end
attribute \blackbox 1
attribute \cells_not_processed 1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7788"
module \BUFPLL
parameter \DIVIDE
parameter \ENABLE_SYNC
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7795"
wire input 4 \GCLK
attribute \clkbuf_driver 1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7792"
wire output 1 \IOCLK
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7793"
wire output 2 \LOCK
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7796"
wire input 5 \LOCKED
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7797"
wire input 6 \PLLIN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7794"
wire output 3 \SERDESSTROBE
end
attribute \blackbox 1
attribute \cells_not_processed 1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7800"
module \BUFPLL_MCB
parameter \DIVIDE
parameter \LOCK_SRC
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7810"
wire input 6 \GCLK
attribute \clkbuf_driver 1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7804"
wire output 1 \IOCLK0
attribute \clkbuf_driver 1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7806"
wire output 2 \IOCLK1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7807"
wire output 3 \LOCK
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7811"
wire input 7 \LOCKED
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7812"
wire input 8 \PLLIN0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7813"
wire input 9 \PLLIN1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7808"
wire output 4 \SERDESSTROBE0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7809"
wire output 5 \SERDESSTROBE1
end
attribute \blackbox 1
attribute \cells_not_processed 1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7830"
module \BUFR
parameter \BUFR_DIVIDE
parameter \SIM_DEVICE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7835"
wire input 2 \CE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7836"
wire input 3 \CLR
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7837"
wire input 4 \I
attribute \clkbuf_driver 1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7834"
wire output 1 \O
end
attribute \blackbox 1
attribute \cells_not_processed 1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:9084"
module \BUFT
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:9086"
wire input 2 \I
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:9085"
wire output 1 \O
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:9087"
wire input 3 \T
end
attribute \blackbox 1
attribute \keep 1
attribute \cells_not_processed 1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:9337"
module \CAPTUREE2
parameter \ONESHOT
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:9339"
wire input 1 \CAP
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:9340"
wire input 2 \CLK
end
attribute \blackbox 1
attribute \keep 1
attribute \cells_not_processed 1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:9302"
module \CAPTURE_SPARTAN3
parameter \ONESHOT
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:9304"
wire input 1 \CAP
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:9305"
wire input 2 \CLK
end
attribute \blackbox 1
attribute \keep 1
attribute \cells_not_processed 1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:9309"
module \CAPTURE_SPARTAN3A
parameter \ONESHOT
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:9311"
wire input 1 \CAP
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:9312"
wire input 2 \CLK
end
attribute \blackbox 1
attribute \keep 1
attribute \cells_not_processed 1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:9316"
module \CAPTURE_VIRTEX4
parameter \ONESHOT
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:9318"
wire input 1 \CAP
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:9319"
wire input 2 \CLK
end
attribute \blackbox 1
attribute \keep 1
attribute \cells_not_processed 1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:9323"
module \CAPTURE_VIRTEX5
parameter \ONESHOT
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:9325"
wire input 1 \CAP
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:9326"
wire input 2 \CLK
end
attribute \blackbox 1
attribute \keep 1
attribute \cells_not_processed 1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:9330"
module \CAPTURE_VIRTEX6
parameter \ONESHOT
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:9332"
wire input 1 \CAP
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:9333"
wire input 2 \CLK
end
attribute \abc9_box_id 4
attribute \whitebox 1
attribute \cells_not_processed 1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_sim.v:257"
module \CARRY4
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_sim.v:266"
wire $or$/usr/local/bin/../share/yosys/xilinx/cells_sim.v:266$36_Y
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_sim.v:267"
wire $or$/usr/local/bin/../share/yosys/xilinx/cells_sim.v:267$38_Y
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_sim.v:267"
wire $ternary$/usr/local/bin/../share/yosys/xilinx/cells_sim.v:267$39_Y
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_sim.v:268"
wire $ternary$/usr/local/bin/../share/yosys/xilinx/cells_sim.v:268$40_Y
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_sim.v:269"
wire $ternary$/usr/local/bin/../share/yosys/xilinx/cells_sim.v:269$41_Y
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_sim.v:270"
wire $ternary$/usr/local/bin/../share/yosys/xilinx/cells_sim.v:270$42_Y
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_sim.v:266"
wire width 4 $xor$/usr/local/bin/../share/yosys/xilinx/cells_sim.v:266$37_Y
attribute \abc9_carry 1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_sim.v:262"
wire input 3 \CI
attribute \abc9_carry 1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_sim.v:259"
wire width 4 output 1 \CO
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_sim.v:263"
wire input 4 \CYINIT
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_sim.v:264"
wire width 4 input 5 \DI
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_sim.v:260"
wire width 4 output 2 \O
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_sim.v:264"
wire width 4 input 6 \S
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_sim.v:266"
cell $or $or$/usr/local/bin/../share/yosys/xilinx/cells_sim.v:266$36
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \CI
connect \B \CYINIT
connect \Y $or$/usr/local/bin/../share/yosys/xilinx/cells_sim.v:266$36_Y
end
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_sim.v:267"
cell $or $or$/usr/local/bin/../share/yosys/xilinx/cells_sim.v:267$38
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \CI
connect \B \CYINIT
connect \Y $or$/usr/local/bin/../share/yosys/xilinx/cells_sim.v:267$38_Y
end
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_sim.v:267"
cell $mux $ternary$/usr/local/bin/../share/yosys/xilinx/cells_sim.v:267$39
parameter \WIDTH 1
connect \A \DI [0]
connect \B $or$/usr/local/bin/../share/yosys/xilinx/cells_sim.v:267$38_Y
connect \S \S [0]
connect \Y $ternary$/usr/local/bin/../share/yosys/xilinx/cells_sim.v:267$39_Y
end
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_sim.v:268"
cell $mux $ternary$/usr/local/bin/../share/yosys/xilinx/cells_sim.v:268$40
parameter \WIDTH 1
connect \A \DI [1]
connect \B \CO [0]
connect \S \S [1]
connect \Y $ternary$/usr/local/bin/../share/yosys/xilinx/cells_sim.v:268$40_Y
end
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_sim.v:269"
cell $mux $ternary$/usr/local/bin/../share/yosys/xilinx/cells_sim.v:269$41
parameter \WIDTH 1
connect \A \DI [2]
connect \B \CO [1]
connect \S \S [2]
connect \Y $ternary$/usr/local/bin/../share/yosys/xilinx/cells_sim.v:269$41_Y
end
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_sim.v:270"
cell $mux $ternary$/usr/local/bin/../share/yosys/xilinx/cells_sim.v:270$42
parameter \WIDTH 1
connect \A \DI [3]
connect \B \CO [2]
connect \S \S [3]
connect \Y $ternary$/usr/local/bin/../share/yosys/xilinx/cells_sim.v:270$42_Y
end
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_sim.v:266"
cell $xor $xor$/usr/local/bin/../share/yosys/xilinx/cells_sim.v:266$37
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \B_WIDTH 4
parameter \Y_WIDTH 4
connect \A \S
connect \B { \CO [2:0] $or$/usr/local/bin/../share/yosys/xilinx/cells_sim.v:266$36_Y }
connect \Y $xor$/usr/local/bin/../share/yosys/xilinx/cells_sim.v:266$37_Y
end
connect \O $xor$/usr/local/bin/../share/yosys/xilinx/cells_sim.v:266$37_Y
connect \CO [0] $ternary$/usr/local/bin/../share/yosys/xilinx/cells_sim.v:267$39_Y
connect \CO [1] $ternary$/usr/local/bin/../share/yosys/xilinx/cells_sim.v:268$40_Y
connect \CO [2] $ternary$/usr/local/bin/../share/yosys/xilinx/cells_sim.v:269$41_Y
connect \CO [3] $ternary$/usr/local/bin/../share/yosys/xilinx/cells_sim.v:270$42_Y
end
attribute \blackbox 1
attribute \cells_not_processed 1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_sim.v:273"
module \CARRY8
parameter \CARRY_TYPE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_sim.v:276"
wire input 3 \CI
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_sim.v:277"
wire input 4 \CI_TOP
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_sim.v:274"
wire width 8 output 1 \CO
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_sim.v:278"
wire width 8 input 5 \DI
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_sim.v:275"
wire width 8 output 2 \O
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_sim.v:278"
wire width 8 input 6 \S
end
attribute \blackbox 1
attribute \cells_not_processed 1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_sim.v:1630"
module \CFGLUT5
parameter \INIT
parameter \IS_CLK_INVERTED
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_sim.v:1639"
wire input 9 \CDI
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_sim.v:1631"
wire output 1 \CDO
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_sim.v:1640"
wire input 10 \CE
attribute \clkbuf_sink 1
attribute \invertible_pin "IS_CLK_INVERTED"
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_sim.v:1643"
wire input 11 \CLK
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_sim.v:1638"
wire input 8 \I0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_sim.v:1637"
wire input 7 \I1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_sim.v:1636"
wire input 6 \I2
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_sim.v:1635"
wire input 5 \I3
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_sim.v:1634"
wire input 4 \I4
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_sim.v:1632"
wire output 2 \O5
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_sim.v:1633"
wire output 3 \O6
end
attribute \blackbox 1
attribute \cells_not_processed 1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24524"
module \CMAC
parameter \CTL_PTP_TRANSPCLK_MODE
parameter \CTL_RX_CHECK_ACK
parameter \CTL_RX_CHECK_PREAMBLE
parameter \CTL_RX_CHECK_SFD
parameter \CTL_RX_DELETE_FCS
parameter \CTL_RX_ETYPE_GCP
parameter \CTL_RX_ETYPE_GPP
parameter \CTL_RX_ETYPE_PCP
parameter \CTL_RX_ETYPE_PPP
parameter \CTL_RX_FORWARD_CONTROL
parameter \CTL_RX_IGNORE_FCS
parameter \CTL_RX_MAX_PACKET_LEN
parameter \CTL_RX_MIN_PACKET_LEN
parameter \CTL_RX_OPCODE_GPP
parameter \CTL_RX_OPCODE_MAX_GCP
parameter \CTL_RX_OPCODE_MAX_PCP
parameter \CTL_RX_OPCODE_MIN_GCP
parameter \CTL_RX_OPCODE_MIN_PCP
parameter \CTL_RX_OPCODE_PPP
parameter \CTL_RX_PAUSE_DA_MCAST
parameter \CTL_RX_PAUSE_DA_UCAST
parameter \CTL_RX_PAUSE_SA
parameter \CTL_RX_PROCESS_LFI
parameter \CTL_RX_VL_LENGTH_MINUS1
parameter \CTL_RX_VL_MARKER_ID0
parameter \CTL_RX_VL_MARKER_ID1
parameter \CTL_RX_VL_MARKER_ID10
parameter \CTL_RX_VL_MARKER_ID11
parameter \CTL_RX_VL_MARKER_ID12
parameter \CTL_RX_VL_MARKER_ID13
parameter \CTL_RX_VL_MARKER_ID14
parameter \CTL_RX_VL_MARKER_ID15
parameter \CTL_RX_VL_MARKER_ID16
parameter \CTL_RX_VL_MARKER_ID17
parameter \CTL_RX_VL_MARKER_ID18
parameter \CTL_RX_VL_MARKER_ID19
parameter \CTL_RX_VL_MARKER_ID2
parameter \CTL_RX_VL_MARKER_ID3
parameter \CTL_RX_VL_MARKER_ID4
parameter \CTL_RX_VL_MARKER_ID5
parameter \CTL_RX_VL_MARKER_ID6
parameter \CTL_RX_VL_MARKER_ID7
parameter \CTL_RX_VL_MARKER_ID8
parameter \CTL_RX_VL_MARKER_ID9
parameter \CTL_TEST_MODE_PIN_CHAR
parameter \CTL_TX_DA_GPP
parameter \CTL_TX_DA_PPP
parameter \CTL_TX_ETHERTYPE_GPP
parameter \CTL_TX_ETHERTYPE_PPP
parameter \CTL_TX_FCS_INS_ENABLE
parameter \CTL_TX_IGNORE_FCS
parameter \CTL_TX_OPCODE_GPP
parameter \CTL_TX_OPCODE_PPP
parameter \CTL_TX_PTP_1STEP_ENABLE
parameter \CTL_TX_PTP_LATENCY_ADJUST
parameter \CTL_TX_SA_GPP
parameter \CTL_TX_SA_PPP
parameter \CTL_TX_VL_LENGTH_MINUS1
parameter \CTL_TX_VL_MARKER_ID0
parameter \CTL_TX_VL_MARKER_ID1
parameter \CTL_TX_VL_MARKER_ID10
parameter \CTL_TX_VL_MARKER_ID11
parameter \CTL_TX_VL_MARKER_ID12
parameter \CTL_TX_VL_MARKER_ID13
parameter \CTL_TX_VL_MARKER_ID14
parameter \CTL_TX_VL_MARKER_ID15
parameter \CTL_TX_VL_MARKER_ID16
parameter \CTL_TX_VL_MARKER_ID17
parameter \CTL_TX_VL_MARKER_ID18
parameter \CTL_TX_VL_MARKER_ID19
parameter \CTL_TX_VL_MARKER_ID2
parameter \CTL_TX_VL_MARKER_ID3
parameter \CTL_TX_VL_MARKER_ID4
parameter \CTL_TX_VL_MARKER_ID5
parameter \CTL_TX_VL_MARKER_ID6
parameter \CTL_TX_VL_MARKER_ID7
parameter \CTL_TX_VL_MARKER_ID8
parameter \CTL_TX_VL_MARKER_ID9
parameter \SIM_VERSION
parameter \TEST_MODE_PIN_CHAR
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24852"
wire input 248 \CTL_CAUI4_MODE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24853"
wire input 249 \CTL_RX_CHECK_ETYPE_GCP
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24854"
wire input 250 \CTL_RX_CHECK_ETYPE_GPP
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24855"
wire input 251 \CTL_RX_CHECK_ETYPE_PCP
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24856"
wire input 252 \CTL_RX_CHECK_ETYPE_PPP
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24857"
wire input 253 \CTL_RX_CHECK_MCAST_GCP
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24858"
wire input 254 \CTL_RX_CHECK_MCAST_GPP
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24859"
wire input 255 \CTL_RX_CHECK_MCAST_PCP
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24860"
wire input 256 \CTL_RX_CHECK_MCAST_PPP
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24861"
wire input 257 \CTL_RX_CHECK_OPCODE_GCP
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24862"
wire input 258 \CTL_RX_CHECK_OPCODE_GPP
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24863"
wire input 259 \CTL_RX_CHECK_OPCODE_PCP
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24864"
wire input 260 \CTL_RX_CHECK_OPCODE_PPP
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24865"
wire input 261 \CTL_RX_CHECK_SA_GCP
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24866"
wire input 262 \CTL_RX_CHECK_SA_GPP
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24867"
wire input 263 \CTL_RX_CHECK_SA_PCP
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24868"
wire input 264 \CTL_RX_CHECK_SA_PPP
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24869"
wire input 265 \CTL_RX_CHECK_UCAST_GCP
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24870"
wire input 266 \CTL_RX_CHECK_UCAST_GPP
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24871"
wire input 267 \CTL_RX_CHECK_UCAST_PCP
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24872"
wire input 268 \CTL_RX_CHECK_UCAST_PPP
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24873"
wire input 269 \CTL_RX_ENABLE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24874"
wire input 270 \CTL_RX_ENABLE_GCP
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24875"
wire input 271 \CTL_RX_ENABLE_GPP
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24876"
wire input 272 \CTL_RX_ENABLE_PCP
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24877"
wire input 273 \CTL_RX_ENABLE_PPP
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24878"
wire input 274 \CTL_RX_FORCE_RESYNC
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24879"
wire width 9 input 275 \CTL_RX_PAUSE_ACK
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24880"
wire width 9 input 276 \CTL_RX_PAUSE_ENABLE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24881"
wire width 80 input 277 \CTL_RX_SYSTEMTIMERIN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24882"
wire input 278 \CTL_RX_TEST_PATTERN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24883"
wire input 279 \CTL_TX_ENABLE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24884"
wire input 280 \CTL_TX_LANE0_VLM_BIP7_OVERRIDE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24885"
wire width 8 input 281 \CTL_TX_LANE0_VLM_BIP7_OVERRIDE_VALUE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24886"
wire width 9 input 282 \CTL_TX_PAUSE_ENABLE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24887"
wire width 16 input 283 \CTL_TX_PAUSE_QUANTA0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24888"
wire width 16 input 284 \CTL_TX_PAUSE_QUANTA1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24889"
wire width 16 input 285 \CTL_TX_PAUSE_QUANTA2
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24890"
wire width 16 input 286 \CTL_TX_PAUSE_QUANTA3
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24891"
wire width 16 input 287 \CTL_TX_PAUSE_QUANTA4
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24892"
wire width 16 input 288 \CTL_TX_PAUSE_QUANTA5
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24893"
wire width 16 input 289 \CTL_TX_PAUSE_QUANTA6
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24894"
wire width 16 input 290 \CTL_TX_PAUSE_QUANTA7
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24895"
wire width 16 input 291 \CTL_TX_PAUSE_QUANTA8
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24896"
wire width 16 input 292 \CTL_TX_PAUSE_REFRESH_TIMER0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24897"
wire width 16 input 293 \CTL_TX_PAUSE_REFRESH_TIMER1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24898"
wire width 16 input 294 \CTL_TX_PAUSE_REFRESH_TIMER2
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24899"
wire width 16 input 295 \CTL_TX_PAUSE_REFRESH_TIMER3
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24900"
wire width 16 input 296 \CTL_TX_PAUSE_REFRESH_TIMER4
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24901"
wire width 16 input 297 \CTL_TX_PAUSE_REFRESH_TIMER5
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24902"
wire width 16 input 298 \CTL_TX_PAUSE_REFRESH_TIMER6
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24903"
wire width 16 input 299 \CTL_TX_PAUSE_REFRESH_TIMER7
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24904"
wire width 16 input 300 \CTL_TX_PAUSE_REFRESH_TIMER8
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24905"
wire width 9 input 301 \CTL_TX_PAUSE_REQ
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24906"
wire input 302 \CTL_TX_PTP_VLANE_ADJUST_MODE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24907"
wire input 303 \CTL_TX_RESEND_PAUSE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24908"
wire input 304 \CTL_TX_SEND_IDLE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24909"
wire input 305 \CTL_TX_SEND_RFI
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24910"
wire width 80 input 306 \CTL_TX_SYSTEMTIMERIN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24911"
wire input 307 \CTL_TX_TEST_PATTERN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24912"
wire width 10 input 308 \DRP_ADDR
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24913"
wire input 309 \DRP_CLK
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24914"
wire width 16 input 310 \DRP_DI
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24605"
wire width 16 output 1 \DRP_DO
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24915"
wire input 311 \DRP_EN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24606"
wire output 2 \DRP_RDY
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24916"
wire input 312 \DRP_WE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24917"
wire input 313 \RX_CLK
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24607"
wire width 128 output 3 \RX_DATAOUT0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24608"
wire width 128 output 4 \RX_DATAOUT1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24609"
wire width 128 output 5 \RX_DATAOUT2
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24610"
wire width 128 output 6 \RX_DATAOUT3
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24611"
wire output 7 \RX_ENAOUT0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24612"
wire output 8 \RX_ENAOUT1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24613"
wire output 9 \RX_ENAOUT2
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24614"
wire output 10 \RX_ENAOUT3
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24615"
wire output 11 \RX_EOPOUT0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24616"
wire output 12 \RX_EOPOUT1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24617"
wire output 13 \RX_EOPOUT2
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24618"
wire output 14 \RX_EOPOUT3
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24619"
wire output 15 \RX_ERROUT0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24620"
wire output 16 \RX_ERROUT1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24621"
wire output 17 \RX_ERROUT2
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24622"
wire output 18 \RX_ERROUT3
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24623"
wire width 7 output 19 \RX_LANE_ALIGNER_FILL_0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24624"
wire width 7 output 20 \RX_LANE_ALIGNER_FILL_1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24625"
wire width 7 output 21 \RX_LANE_ALIGNER_FILL_10
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24626"
wire width 7 output 22 \RX_LANE_ALIGNER_FILL_11
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24627"
wire width 7 output 23 \RX_LANE_ALIGNER_FILL_12
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24628"
wire width 7 output 24 \RX_LANE_ALIGNER_FILL_13
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24629"
wire width 7 output 25 \RX_LANE_ALIGNER_FILL_14
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24630"
wire width 7 output 26 \RX_LANE_ALIGNER_FILL_15
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24631"
wire width 7 output 27 \RX_LANE_ALIGNER_FILL_16
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24632"
wire width 7 output 28 \RX_LANE_ALIGNER_FILL_17
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24633"
wire width 7 output 29 \RX_LANE_ALIGNER_FILL_18
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24634"
wire width 7 output 30 \RX_LANE_ALIGNER_FILL_19
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24635"
wire width 7 output 31 \RX_LANE_ALIGNER_FILL_2
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24636"
wire width 7 output 32 \RX_LANE_ALIGNER_FILL_3
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24637"
wire width 7 output 33 \RX_LANE_ALIGNER_FILL_4
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24638"
wire width 7 output 34 \RX_LANE_ALIGNER_FILL_5
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24639"
wire width 7 output 35 \RX_LANE_ALIGNER_FILL_6
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24640"
wire width 7 output 36 \RX_LANE_ALIGNER_FILL_7
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24641"
wire width 7 output 37 \RX_LANE_ALIGNER_FILL_8
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24642"
wire width 7 output 38 \RX_LANE_ALIGNER_FILL_9
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24643"
wire width 4 output 39 \RX_MTYOUT0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24644"
wire width 4 output 40 \RX_MTYOUT1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24645"
wire width 4 output 41 \RX_MTYOUT2
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24646"
wire width 4 output 42 \RX_MTYOUT3
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24647"
wire width 5 output 43 \RX_PTP_PCSLANE_OUT
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24648"
wire width 80 output 44 \RX_PTP_TSTAMP_OUT
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24918"
wire input 314 \RX_RESET
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24919"
wire width 16 input 315 \RX_SERDES_ALT_DATA0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24920"
wire width 16 input 316 \RX_SERDES_ALT_DATA1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24921"
wire width 16 input 317 \RX_SERDES_ALT_DATA2
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24922"
wire width 16 input 318 \RX_SERDES_ALT_DATA3
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24923"
wire width 10 input 319 \RX_SERDES_CLK
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24924"
wire width 64 input 320 \RX_SERDES_DATA0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24925"
wire width 64 input 321 \RX_SERDES_DATA1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24926"
wire width 64 input 322 \RX_SERDES_DATA2
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24927"
wire width 64 input 323 \RX_SERDES_DATA3
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24928"
wire width 32 input 324 \RX_SERDES_DATA4
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24929"
wire width 32 input 325 \RX_SERDES_DATA5
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24930"
wire width 32 input 326 \RX_SERDES_DATA6
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24931"
wire width 32 input 327 \RX_SERDES_DATA7
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24932"
wire width 32 input 328 \RX_SERDES_DATA8
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24933"
wire width 32 input 329 \RX_SERDES_DATA9
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24934"
wire width 10 input 330 \RX_SERDES_RESET
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24649"
wire output 45 \RX_SOPOUT0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24650"
wire output 46 \RX_SOPOUT1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24651"
wire output 47 \RX_SOPOUT2
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24652"
wire output 48 \RX_SOPOUT3
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24653"
wire output 49 \STAT_RX_ALIGNED
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24654"
wire output 50 \STAT_RX_ALIGNED_ERR
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24655"
wire width 7 output 51 \STAT_RX_BAD_CODE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24656"
wire width 4 output 52 \STAT_RX_BAD_FCS
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24657"
wire output 53 \STAT_RX_BAD_PREAMBLE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24658"
wire output 54 \STAT_RX_BAD_SFD
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24659"
wire output 55 \STAT_RX_BIP_ERR_0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24660"
wire output 56 \STAT_RX_BIP_ERR_1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24661"
wire output 57 \STAT_RX_BIP_ERR_10
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24662"
wire output 58 \STAT_RX_BIP_ERR_11
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24663"
wire output 59 \STAT_RX_BIP_ERR_12
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24664"
wire output 60 \STAT_RX_BIP_ERR_13
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24665"
wire output 61 \STAT_RX_BIP_ERR_14
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24666"
wire output 62 \STAT_RX_BIP_ERR_15
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24667"
wire output 63 \STAT_RX_BIP_ERR_16
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24668"
wire output 64 \STAT_RX_BIP_ERR_17
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24669"
wire output 65 \STAT_RX_BIP_ERR_18
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24670"
wire output 66 \STAT_RX_BIP_ERR_19
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24671"
wire output 67 \STAT_RX_BIP_ERR_2
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24672"
wire output 68 \STAT_RX_BIP_ERR_3
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24673"
wire output 69 \STAT_RX_BIP_ERR_4
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24674"
wire output 70 \STAT_RX_BIP_ERR_5
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24675"
wire output 71 \STAT_RX_BIP_ERR_6
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24676"
wire output 72 \STAT_RX_BIP_ERR_7
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24677"
wire output 73 \STAT_RX_BIP_ERR_8
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24678"
wire output 74 \STAT_RX_BIP_ERR_9
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24679"
wire width 20 output 75 \STAT_RX_BLOCK_LOCK
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24680"
wire output 76 \STAT_RX_BROADCAST
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24681"
wire width 4 output 77 \STAT_RX_FRAGMENT
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24682"
wire width 4 output 78 \STAT_RX_FRAMING_ERR_0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24683"
wire width 4 output 79 \STAT_RX_FRAMING_ERR_1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24684"
wire width 4 output 80 \STAT_RX_FRAMING_ERR_10
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24685"
wire width 4 output 81 \STAT_RX_FRAMING_ERR_11
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24686"
wire width 4 output 82 \STAT_RX_FRAMING_ERR_12
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24687"
wire width 4 output 83 \STAT_RX_FRAMING_ERR_13
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24688"
wire width 4 output 84 \STAT_RX_FRAMING_ERR_14
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24689"
wire width 4 output 85 \STAT_RX_FRAMING_ERR_15
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24690"
wire width 4 output 86 \STAT_RX_FRAMING_ERR_16
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24691"
wire width 4 output 87 \STAT_RX_FRAMING_ERR_17
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24692"
wire width 4 output 88 \STAT_RX_FRAMING_ERR_18
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24693"
wire width 4 output 89 \STAT_RX_FRAMING_ERR_19
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24694"
wire width 4 output 90 \STAT_RX_FRAMING_ERR_2
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24695"
wire width 4 output 91 \STAT_RX_FRAMING_ERR_3
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24696"
wire width 4 output 92 \STAT_RX_FRAMING_ERR_4
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24697"
wire width 4 output 93 \STAT_RX_FRAMING_ERR_5
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24698"
wire width 4 output 94 \STAT_RX_FRAMING_ERR_6
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24699"
wire width 4 output 95 \STAT_RX_FRAMING_ERR_7
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24700"
wire width 4 output 96 \STAT_RX_FRAMING_ERR_8
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24701"
wire width 4 output 97 \STAT_RX_FRAMING_ERR_9
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24702"
wire output 98 \STAT_RX_FRAMING_ERR_VALID_0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24703"
wire output 99 \STAT_RX_FRAMING_ERR_VALID_1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24704"
wire output 100 \STAT_RX_FRAMING_ERR_VALID_10
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24705"
wire output 101 \STAT_RX_FRAMING_ERR_VALID_11
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24706"
wire output 102 \STAT_RX_FRAMING_ERR_VALID_12
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24707"
wire output 103 \STAT_RX_FRAMING_ERR_VALID_13
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24708"
wire output 104 \STAT_RX_FRAMING_ERR_VALID_14
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24709"
wire output 105 \STAT_RX_FRAMING_ERR_VALID_15
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24710"
wire output 106 \STAT_RX_FRAMING_ERR_VALID_16
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24711"
wire output 107 \STAT_RX_FRAMING_ERR_VALID_17
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24712"
wire output 108 \STAT_RX_FRAMING_ERR_VALID_18
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24713"
wire output 109 \STAT_RX_FRAMING_ERR_VALID_19
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24714"
wire output 110 \STAT_RX_FRAMING_ERR_VALID_2
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24715"
wire output 111 \STAT_RX_FRAMING_ERR_VALID_3
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24716"
wire output 112 \STAT_RX_FRAMING_ERR_VALID_4
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24717"
wire output 113 \STAT_RX_FRAMING_ERR_VALID_5
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24718"
wire output 114 \STAT_RX_FRAMING_ERR_VALID_6
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24719"
wire output 115 \STAT_RX_FRAMING_ERR_VALID_7
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24720"
wire output 116 \STAT_RX_FRAMING_ERR_VALID_8
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24721"
wire output 117 \STAT_RX_FRAMING_ERR_VALID_9
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24722"
wire output 118 \STAT_RX_GOT_SIGNAL_OS
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24723"
wire output 119 \STAT_RX_HI_BER
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24724"
wire output 120 \STAT_RX_INRANGEERR
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24725"
wire output 121 \STAT_RX_INTERNAL_LOCAL_FAULT
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24726"
wire output 122 \STAT_RX_JABBER
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24727"
wire width 8 output 123 \STAT_RX_LANE0_VLM_BIP7
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24728"
wire output 124 \STAT_RX_LANE0_VLM_BIP7_VALID
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24729"
wire output 125 \STAT_RX_LOCAL_FAULT
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24730"
wire width 20 output 126 \STAT_RX_MF_ERR
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24731"
wire width 20 output 127 \STAT_RX_MF_LEN_ERR
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24732"
wire width 20 output 128 \STAT_RX_MF_REPEAT_ERR
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24733"
wire output 129 \STAT_RX_MISALIGNED
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24734"
wire output 130 \STAT_RX_MULTICAST
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24735"
wire output 131 \STAT_RX_OVERSIZE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24736"
wire output 132 \STAT_RX_PACKET_1024_1518_BYTES
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24737"
wire output 133 \STAT_RX_PACKET_128_255_BYTES
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24738"
wire output 134 \STAT_RX_PACKET_1519_1522_BYTES
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24739"
wire output 135 \STAT_RX_PACKET_1523_1548_BYTES
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24740"
wire output 136 \STAT_RX_PACKET_1549_2047_BYTES
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24741"
wire output 137 \STAT_RX_PACKET_2048_4095_BYTES
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24742"
wire output 138 \STAT_RX_PACKET_256_511_BYTES
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24743"
wire output 139 \STAT_RX_PACKET_4096_8191_BYTES
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24744"
wire output 140 \STAT_RX_PACKET_512_1023_BYTES
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24745"
wire output 141 \STAT_RX_PACKET_64_BYTES
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24746"
wire output 142 \STAT_RX_PACKET_65_127_BYTES
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24747"
wire output 143 \STAT_RX_PACKET_8192_9215_BYTES
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24748"
wire output 144 \STAT_RX_PACKET_BAD_FCS
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24749"
wire output 145 \STAT_RX_PACKET_LARGE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24750"
wire width 4 output 146 \STAT_RX_PACKET_SMALL
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24751"
wire output 147 \STAT_RX_PAUSE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24752"
wire width 16 output 148 \STAT_RX_PAUSE_QUANTA0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24753"
wire width 16 output 149 \STAT_RX_PAUSE_QUANTA1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24754"
wire width 16 output 150 \STAT_RX_PAUSE_QUANTA2
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24755"
wire width 16 output 151 \STAT_RX_PAUSE_QUANTA3
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24756"
wire width 16 output 152 \STAT_RX_PAUSE_QUANTA4
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24757"
wire width 16 output 153 \STAT_RX_PAUSE_QUANTA5
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24758"
wire width 16 output 154 \STAT_RX_PAUSE_QUANTA6
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24759"
wire width 16 output 155 \STAT_RX_PAUSE_QUANTA7
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24760"
wire width 16 output 156 \STAT_RX_PAUSE_QUANTA8
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24761"
wire width 9 output 157 \STAT_RX_PAUSE_REQ
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24762"
wire width 9 output 158 \STAT_RX_PAUSE_VALID
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24763"
wire output 159 \STAT_RX_RECEIVED_LOCAL_FAULT
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24764"
wire output 160 \STAT_RX_REMOTE_FAULT
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24765"
wire output 161 \STAT_RX_STATUS
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24766"
wire width 4 output 162 \STAT_RX_STOMPED_FCS
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24767"
wire width 20 output 163 \STAT_RX_SYNCED
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24768"
wire width 20 output 164 \STAT_RX_SYNCED_ERR
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24769"
wire width 3 output 165 \STAT_RX_TEST_PATTERN_MISMATCH
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24770"
wire output 166 \STAT_RX_TOOLONG
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24771"
wire width 8 output 167 \STAT_RX_TOTAL_BYTES
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24772"
wire width 14 output 168 \STAT_RX_TOTAL_GOOD_BYTES
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24773"
wire output 169 \STAT_RX_TOTAL_GOOD_PACKETS
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24774"
wire width 4 output 170 \STAT_RX_TOTAL_PACKETS
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24775"
wire output 171 \STAT_RX_TRUNCATED
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24776"
wire width 4 output 172 \STAT_RX_UNDERSIZE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24777"
wire output 173 \STAT_RX_UNICAST
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24778"
wire output 174 \STAT_RX_USER_PAUSE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24779"
wire output 175 \STAT_RX_VLAN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24780"
wire width 20 output 176 \STAT_RX_VL_DEMUXED
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24781"
wire width 5 output 177 \STAT_RX_VL_NUMBER_0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24782"
wire width 5 output 178 \STAT_RX_VL_NUMBER_1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24783"
wire width 5 output 179 \STAT_RX_VL_NUMBER_10
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24784"
wire width 5 output 180 \STAT_RX_VL_NUMBER_11
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24785"
wire width 5 output 181 \STAT_RX_VL_NUMBER_12
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24786"
wire width 5 output 182 \STAT_RX_VL_NUMBER_13
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24787"
wire width 5 output 183 \STAT_RX_VL_NUMBER_14
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24788"
wire width 5 output 184 \STAT_RX_VL_NUMBER_15
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24789"
wire width 5 output 185 \STAT_RX_VL_NUMBER_16
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24790"
wire width 5 output 186 \STAT_RX_VL_NUMBER_17
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24791"
wire width 5 output 187 \STAT_RX_VL_NUMBER_18
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24792"
wire width 5 output 188 \STAT_RX_VL_NUMBER_19
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24793"
wire width 5 output 189 \STAT_RX_VL_NUMBER_2
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24794"
wire width 5 output 190 \STAT_RX_VL_NUMBER_3
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24795"
wire width 5 output 191 \STAT_RX_VL_NUMBER_4
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24796"
wire width 5 output 192 \STAT_RX_VL_NUMBER_5
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24797"
wire width 5 output 193 \STAT_RX_VL_NUMBER_6
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24798"
wire width 5 output 194 \STAT_RX_VL_NUMBER_7
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24799"
wire width 5 output 195 \STAT_RX_VL_NUMBER_8
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24800"
wire width 5 output 196 \STAT_RX_VL_NUMBER_9
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24801"
wire output 197 \STAT_TX_BAD_FCS
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24802"
wire output 198 \STAT_TX_BROADCAST
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24803"
wire output 199 \STAT_TX_FRAME_ERROR
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24804"
wire output 200 \STAT_TX_LOCAL_FAULT
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24805"
wire output 201 \STAT_TX_MULTICAST
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24806"
wire output 202 \STAT_TX_PACKET_1024_1518_BYTES
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24807"
wire output 203 \STAT_TX_PACKET_128_255_BYTES
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24808"
wire output 204 \STAT_TX_PACKET_1519_1522_BYTES
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24809"
wire output 205 \STAT_TX_PACKET_1523_1548_BYTES
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24810"
wire output 206 \STAT_TX_PACKET_1549_2047_BYTES
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24811"
wire output 207 \STAT_TX_PACKET_2048_4095_BYTES
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24812"
wire output 208 \STAT_TX_PACKET_256_511_BYTES
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24813"
wire output 209 \STAT_TX_PACKET_4096_8191_BYTES
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24814"
wire output 210 \STAT_TX_PACKET_512_1023_BYTES
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24815"
wire output 211 \STAT_TX_PACKET_64_BYTES
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24816"
wire output 212 \STAT_TX_PACKET_65_127_BYTES
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24817"
wire output 213 \STAT_TX_PACKET_8192_9215_BYTES
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24818"
wire output 214 \STAT_TX_PACKET_LARGE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24819"
wire output 215 \STAT_TX_PACKET_SMALL
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24820"
wire output 216 \STAT_TX_PAUSE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24821"
wire width 9 output 217 \STAT_TX_PAUSE_VALID
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24822"
wire output 218 \STAT_TX_PTP_FIFO_READ_ERROR
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24823"
wire output 219 \STAT_TX_PTP_FIFO_WRITE_ERROR
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24824"
wire width 7 output 220 \STAT_TX_TOTAL_BYTES
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24825"
wire width 14 output 221 \STAT_TX_TOTAL_GOOD_BYTES
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24826"
wire output 222 \STAT_TX_TOTAL_GOOD_PACKETS
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24827"
wire output 223 \STAT_TX_TOTAL_PACKETS
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24828"
wire output 224 \STAT_TX_UNICAST
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24829"
wire output 225 \STAT_TX_USER_PAUSE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24830"
wire output 226 \STAT_TX_VLAN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24935"
wire input 331 \TX_CLK
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24936"
wire width 128 input 332 \TX_DATAIN0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24937"
wire width 128 input 333 \TX_DATAIN1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24938"
wire width 128 input 334 \TX_DATAIN2
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24939"
wire width 128 input 335 \TX_DATAIN3
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24940"
wire input 336 \TX_ENAIN0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24941"
wire input 337 \TX_ENAIN1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24942"
wire input 338 \TX_ENAIN2
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24943"
wire input 339 \TX_ENAIN3
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24944"
wire input 340 \TX_EOPIN0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24945"
wire input 341 \TX_EOPIN1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24946"
wire input 342 \TX_EOPIN2
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24947"
wire input 343 \TX_EOPIN3
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24948"
wire input 344 \TX_ERRIN0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24949"
wire input 345 \TX_ERRIN1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24950"
wire input 346 \TX_ERRIN2
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24951"
wire input 347 \TX_ERRIN3
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24952"
wire width 4 input 348 \TX_MTYIN0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24953"
wire width 4 input 349 \TX_MTYIN1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24954"
wire width 4 input 350 \TX_MTYIN2
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24955"
wire width 4 input 351 \TX_MTYIN3
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24831"
wire output 227 \TX_OVFOUT
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24956"
wire width 2 input 352 \TX_PTP_1588OP_IN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24957"
wire width 16 input 353 \TX_PTP_CHKSUM_OFFSET_IN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24832"
wire width 5 output 228 \TX_PTP_PCSLANE_OUT
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24958"
wire width 64 input 354 \TX_PTP_RXTSTAMP_IN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24959"
wire width 16 input 355 \TX_PTP_TAG_FIELD_IN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24960"
wire width 16 input 356 \TX_PTP_TSTAMP_OFFSET_IN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24833"
wire width 80 output 229 \TX_PTP_TSTAMP_OUT
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24834"
wire width 16 output 230 \TX_PTP_TSTAMP_TAG_OUT
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24835"
wire output 231 \TX_PTP_TSTAMP_VALID_OUT
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24961"
wire input 357 \TX_PTP_UPD_CHKSUM_IN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24836"
wire output 232 \TX_RDYOUT
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24962"
wire input 358 \TX_RESET
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24837"
wire width 16 output 233 \TX_SERDES_ALT_DATA0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24838"
wire width 16 output 234 \TX_SERDES_ALT_DATA1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24839"
wire width 16 output 235 \TX_SERDES_ALT_DATA2
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24840"
wire width 16 output 236 \TX_SERDES_ALT_DATA3
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24841"
wire width 64 output 237 \TX_SERDES_DATA0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24842"
wire width 64 output 238 \TX_SERDES_DATA1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24843"
wire width 64 output 239 \TX_SERDES_DATA2
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24844"
wire width 64 output 240 \TX_SERDES_DATA3
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24845"
wire width 32 output 241 \TX_SERDES_DATA4
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24846"
wire width 32 output 242 \TX_SERDES_DATA5
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24847"
wire width 32 output 243 \TX_SERDES_DATA6
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24848"
wire width 32 output 244 \TX_SERDES_DATA7
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24849"
wire width 32 output 245 \TX_SERDES_DATA8
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24850"
wire width 32 output 246 \TX_SERDES_DATA9
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24963"
wire input 359 \TX_SOPIN0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24964"
wire input 360 \TX_SOPIN1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24965"
wire input 361 \TX_SOPIN2
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24966"
wire input 362 \TX_SOPIN3
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24851"
wire output 247 \TX_UNFOUT
end
attribute \blackbox 1
attribute \cells_not_processed 1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24969"
module \CMACE4
parameter \CTL_PTP_TRANSPCLK_MODE
parameter \CTL_RX_CHECK_ACK
parameter \CTL_RX_CHECK_PREAMBLE
parameter \CTL_RX_CHECK_SFD
parameter \CTL_RX_DELETE_FCS
parameter \CTL_RX_ETYPE_GCP
parameter \CTL_RX_ETYPE_GPP
parameter \CTL_RX_ETYPE_PCP
parameter \CTL_RX_ETYPE_PPP
parameter \CTL_RX_FORWARD_CONTROL
parameter \CTL_RX_IGNORE_FCS
parameter \CTL_RX_MAX_PACKET_LEN
parameter \CTL_RX_MIN_PACKET_LEN
parameter \CTL_RX_OPCODE_GPP
parameter \CTL_RX_OPCODE_MAX_GCP
parameter \CTL_RX_OPCODE_MAX_PCP
parameter \CTL_RX_OPCODE_MIN_GCP
parameter \CTL_RX_OPCODE_MIN_PCP
parameter \CTL_RX_OPCODE_PPP
parameter \CTL_RX_PAUSE_DA_MCAST
parameter \CTL_RX_PAUSE_DA_UCAST
parameter \CTL_RX_PAUSE_SA
parameter \CTL_RX_PROCESS_LFI
parameter \CTL_RX_RSFEC_AM_THRESHOLD
parameter \CTL_RX_RSFEC_FILL_ADJUST
parameter \CTL_RX_VL_LENGTH_MINUS1
parameter \CTL_RX_VL_MARKER_ID0
parameter \CTL_RX_VL_MARKER_ID1
parameter \CTL_RX_VL_MARKER_ID10
parameter \CTL_RX_VL_MARKER_ID11
parameter \CTL_RX_VL_MARKER_ID12
parameter \CTL_RX_VL_MARKER_ID13
parameter \CTL_RX_VL_MARKER_ID14
parameter \CTL_RX_VL_MARKER_ID15
parameter \CTL_RX_VL_MARKER_ID16
parameter \CTL_RX_VL_MARKER_ID17
parameter \CTL_RX_VL_MARKER_ID18
parameter \CTL_RX_VL_MARKER_ID19
parameter \CTL_RX_VL_MARKER_ID2
parameter \CTL_RX_VL_MARKER_ID3
parameter \CTL_RX_VL_MARKER_ID4
parameter \CTL_RX_VL_MARKER_ID5
parameter \CTL_RX_VL_MARKER_ID6
parameter \CTL_RX_VL_MARKER_ID7
parameter \CTL_RX_VL_MARKER_ID8
parameter \CTL_RX_VL_MARKER_ID9
parameter \CTL_TEST_MODE_PIN_CHAR
parameter \CTL_TX_CUSTOM_PREAMBLE_ENABLE
parameter \CTL_TX_DA_GPP
parameter \CTL_TX_DA_PPP
parameter \CTL_TX_ETHERTYPE_GPP
parameter \CTL_TX_ETHERTYPE_PPP
parameter \CTL_TX_FCS_INS_ENABLE
parameter \CTL_TX_IGNORE_FCS
parameter \CTL_TX_IPG_VALUE
parameter \CTL_TX_OPCODE_GPP
parameter \CTL_TX_OPCODE_PPP
parameter \CTL_TX_PTP_1STEP_ENABLE
parameter \CTL_TX_PTP_LATENCY_ADJUST
parameter \CTL_TX_SA_GPP
parameter \CTL_TX_SA_PPP
parameter \CTL_TX_VL_LENGTH_MINUS1
parameter \CTL_TX_VL_MARKER_ID0
parameter \CTL_TX_VL_MARKER_ID1
parameter \CTL_TX_VL_MARKER_ID10
parameter \CTL_TX_VL_MARKER_ID11
parameter \CTL_TX_VL_MARKER_ID12
parameter \CTL_TX_VL_MARKER_ID13
parameter \CTL_TX_VL_MARKER_ID14
parameter \CTL_TX_VL_MARKER_ID15
parameter \CTL_TX_VL_MARKER_ID16
parameter \CTL_TX_VL_MARKER_ID17
parameter \CTL_TX_VL_MARKER_ID18
parameter \CTL_TX_VL_MARKER_ID19
parameter \CTL_TX_VL_MARKER_ID2
parameter \CTL_TX_VL_MARKER_ID3
parameter \CTL_TX_VL_MARKER_ID4
parameter \CTL_TX_VL_MARKER_ID5
parameter \CTL_TX_VL_MARKER_ID6
parameter \CTL_TX_VL_MARKER_ID7
parameter \CTL_TX_VL_MARKER_ID8
parameter \CTL_TX_VL_MARKER_ID9
parameter \SIM_DEVICE
parameter \TEST_MODE_PIN_CHAR
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:25340"
wire input 287 \CTL_CAUI4_MODE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:25341"
wire input 288 \CTL_RSFEC_ENABLE_TRANSCODER_BYPASS_MODE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:25342"
wire input 289 \CTL_RSFEC_IEEE_ERROR_INDICATION_MODE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:25343"
wire input 290 \CTL_RX_CHECK_ETYPE_GCP
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:25344"
wire input 291 \CTL_RX_CHECK_ETYPE_GPP
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:25345"
wire input 292 \CTL_RX_CHECK_ETYPE_PCP
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:25346"
wire input 293 \CTL_RX_CHECK_ETYPE_PPP
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:25347"
wire input 294 \CTL_RX_CHECK_MCAST_GCP
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:25348"
wire input 295 \CTL_RX_CHECK_MCAST_GPP
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:25349"
wire input 296 \CTL_RX_CHECK_MCAST_PCP
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:25350"
wire input 297 \CTL_RX_CHECK_MCAST_PPP
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:25351"
wire input 298 \CTL_RX_CHECK_OPCODE_GCP
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:25352"
wire input 299 \CTL_RX_CHECK_OPCODE_GPP
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:25353"
wire input 300 \CTL_RX_CHECK_OPCODE_PCP
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:25354"
wire input 301 \CTL_RX_CHECK_OPCODE_PPP
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:25355"
wire input 302 \CTL_RX_CHECK_SA_GCP
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:25356"
wire input 303 \CTL_RX_CHECK_SA_GPP
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:25357"
wire input 304 \CTL_RX_CHECK_SA_PCP
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:25358"
wire input 305 \CTL_RX_CHECK_SA_PPP
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:25359"
wire input 306 \CTL_RX_CHECK_UCAST_GCP
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:25360"
wire input 307 \CTL_RX_CHECK_UCAST_GPP
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:25361"
wire input 308 \CTL_RX_CHECK_UCAST_PCP
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:25362"
wire input 309 \CTL_RX_CHECK_UCAST_PPP
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:25363"
wire input 310 \CTL_RX_ENABLE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:25364"
wire input 311 \CTL_RX_ENABLE_GCP
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:25365"
wire input 312 \CTL_RX_ENABLE_GPP
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:25366"
wire input 313 \CTL_RX_ENABLE_PCP
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:25367"
wire input 314 \CTL_RX_ENABLE_PPP
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:25368"
wire input 315 \CTL_RX_FORCE_RESYNC
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:25369"
wire width 9 input 316 \CTL_RX_PAUSE_ACK
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:25370"
wire width 9 input 317 \CTL_RX_PAUSE_ENABLE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:25371"
wire input 318 \CTL_RX_RSFEC_ENABLE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:25372"
wire input 319 \CTL_RX_RSFEC_ENABLE_CORRECTION
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:25373"
wire input 320 \CTL_RX_RSFEC_ENABLE_INDICATION
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:25374"
wire width 80 input 321 \CTL_RX_SYSTEMTIMERIN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:25375"
wire input 322 \CTL_RX_TEST_PATTERN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:25376"
wire input 323 \CTL_TX_ENABLE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:25377"
wire input 324 \CTL_TX_LANE0_VLM_BIP7_OVERRIDE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:25378"
wire width 8 input 325 \CTL_TX_LANE0_VLM_BIP7_OVERRIDE_VALUE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:25379"
wire width 9 input 326 \CTL_TX_PAUSE_ENABLE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:25380"
wire width 16 input 327 \CTL_TX_PAUSE_QUANTA0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:25381"
wire width 16 input 328 \CTL_TX_PAUSE_QUANTA1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:25382"
wire width 16 input 329 \CTL_TX_PAUSE_QUANTA2
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:25383"
wire width 16 input 330 \CTL_TX_PAUSE_QUANTA3
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:25384"
wire width 16 input 331 \CTL_TX_PAUSE_QUANTA4
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:25385"
wire width 16 input 332 \CTL_TX_PAUSE_QUANTA5
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:25386"
wire width 16 input 333 \CTL_TX_PAUSE_QUANTA6
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:25387"
wire width 16 input 334 \CTL_TX_PAUSE_QUANTA7
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:25388"
wire width 16 input 335 \CTL_TX_PAUSE_QUANTA8
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:25389"
wire width 16 input 336 \CTL_TX_PAUSE_REFRESH_TIMER0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:25390"
wire width 16 input 337 \CTL_TX_PAUSE_REFRESH_TIMER1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:25391"
wire width 16 input 338 \CTL_TX_PAUSE_REFRESH_TIMER2
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:25392"
wire width 16 input 339 \CTL_TX_PAUSE_REFRESH_TIMER3
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:25393"
wire width 16 input 340 \CTL_TX_PAUSE_REFRESH_TIMER4
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:25394"
wire width 16 input 341 \CTL_TX_PAUSE_REFRESH_TIMER5
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:25395"
wire width 16 input 342 \CTL_TX_PAUSE_REFRESH_TIMER6
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:25396"
wire width 16 input 343 \CTL_TX_PAUSE_REFRESH_TIMER7
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:25397"
wire width 16 input 344 \CTL_TX_PAUSE_REFRESH_TIMER8
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:25398"
wire width 9 input 345 \CTL_TX_PAUSE_REQ
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:25399"
wire input 346 \CTL_TX_PTP_VLANE_ADJUST_MODE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:25400"
wire input 347 \CTL_TX_RESEND_PAUSE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:25401"
wire input 348 \CTL_TX_RSFEC_ENABLE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:25402"
wire input 349 \CTL_TX_SEND_IDLE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:25403"
wire input 350 \CTL_TX_SEND_LFI
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:25404"
wire input 351 \CTL_TX_SEND_RFI
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:25405"
wire width 80 input 352 \CTL_TX_SYSTEMTIMERIN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:25406"
wire input 353 \CTL_TX_TEST_PATTERN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:25407"
wire width 10 input 354 \DRP_ADDR
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:25408"
wire input 355 \DRP_CLK
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:25409"
wire width 16 input 356 \DRP_DI
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:25054"
wire width 16 output 1 \DRP_DO
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:25410"
wire input 357 \DRP_EN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:25055"
wire output 2 \DRP_RDY
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:25411"
wire input 358 \DRP_WE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:25412"
wire width 330 input 359 \RSFEC_BYPASS_RX_DIN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:25413"
wire input 360 \RSFEC_BYPASS_RX_DIN_CW_START
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:25056"
wire width 330 output 3 \RSFEC_BYPASS_RX_DOUT
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:25057"
wire output 4 \RSFEC_BYPASS_RX_DOUT_CW_START
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:25058"
wire output 5 \RSFEC_BYPASS_RX_DOUT_VALID
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:25414"
wire width 330 input 361 \RSFEC_BYPASS_TX_DIN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:25415"
wire input 362 \RSFEC_BYPASS_TX_DIN_CW_START
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:25059"
wire width 330 output 6 \RSFEC_BYPASS_TX_DOUT
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:25060"
wire output 7 \RSFEC_BYPASS_TX_DOUT_CW_START
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:25061"
wire output 8 \RSFEC_BYPASS_TX_DOUT_VALID
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:25416"
wire input 363 \RX_CLK
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:25062"
wire width 128 output 9 \RX_DATAOUT0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:25063"
wire width 128 output 10 \RX_DATAOUT1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:25064"
wire width 128 output 11 \RX_DATAOUT2
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:25065"
wire width 128 output 12 \RX_DATAOUT3
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:25066"
wire output 13 \RX_ENAOUT0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:25067"
wire output 14 \RX_ENAOUT1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:25068"
wire output 15 \RX_ENAOUT2
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:25069"
wire output 16 \RX_ENAOUT3
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:25070"
wire output 17 \RX_EOPOUT0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:25071"
wire output 18 \RX_EOPOUT1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:25072"
wire output 19 \RX_EOPOUT2
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:25073"
wire output 20 \RX_EOPOUT3
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:25074"
wire output 21 \RX_ERROUT0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:25075"
wire output 22 \RX_ERROUT1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:25076"
wire output 23 \RX_ERROUT2
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:25077"
wire output 24 \RX_ERROUT3
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:25078"
wire width 7 output 25 \RX_LANE_ALIGNER_FILL_0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:25079"
wire width 7 output 26 \RX_LANE_ALIGNER_FILL_1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:25080"
wire width 7 output 27 \RX_LANE_ALIGNER_FILL_10
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:25081"
wire width 7 output 28 \RX_LANE_ALIGNER_FILL_11
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:25082"
wire width 7 output 29 \RX_LANE_ALIGNER_FILL_12
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:25083"
wire width 7 output 30 \RX_LANE_ALIGNER_FILL_13
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:25084"
wire width 7 output 31 \RX_LANE_ALIGNER_FILL_14
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:25085"
wire width 7 output 32 \RX_LANE_ALIGNER_FILL_15
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:25086"
wire width 7 output 33 \RX_LANE_ALIGNER_FILL_16
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:25087"
wire width 7 output 34 \RX_LANE_ALIGNER_FILL_17
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:25088"
wire width 7 output 35 \RX_LANE_ALIGNER_FILL_18
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:25089"
wire width 7 output 36 \RX_LANE_ALIGNER_FILL_19
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:25090"
wire width 7 output 37 \RX_LANE_ALIGNER_FILL_2
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:25091"
wire width 7 output 38 \RX_LANE_ALIGNER_FILL_3
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:25092"
wire width 7 output 39 \RX_LANE_ALIGNER_FILL_4
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:25093"
wire width 7 output 40 \RX_LANE_ALIGNER_FILL_5
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:25094"
wire width 7 output 41 \RX_LANE_ALIGNER_FILL_6
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:25095"
wire width 7 output 42 \RX_LANE_ALIGNER_FILL_7
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:25096"
wire width 7 output 43 \RX_LANE_ALIGNER_FILL_8
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:25097"
wire width 7 output 44 \RX_LANE_ALIGNER_FILL_9
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:25098"
wire width 4 output 45 \RX_MTYOUT0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:25099"
wire width 4 output 46 \RX_MTYOUT1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:25100"
wire width 4 output 47 \RX_MTYOUT2
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:25101"
wire width 4 output 48 \RX_MTYOUT3
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:25102"
wire width 8 output 49 \RX_OTN_BIP8_0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:25103"
wire width 8 output 50 \RX_OTN_BIP8_1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:25104"
wire width 8 output 51 \RX_OTN_BIP8_2
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:25105"
wire width 8 output 52 \RX_OTN_BIP8_3
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:25106"
wire width 8 output 53 \RX_OTN_BIP8_4
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:25107"
wire width 66 output 54 \RX_OTN_DATA_0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:25108"
wire width 66 output 55 \RX_OTN_DATA_1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:25109"
wire width 66 output 56 \RX_OTN_DATA_2
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:25110"
wire width 66 output 57 \RX_OTN_DATA_3
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:25111"
wire width 66 output 58 \RX_OTN_DATA_4
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:25112"
wire output 59 \RX_OTN_ENA
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:25113"
wire output 60 \RX_OTN_LANE0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:25114"
wire output 61 \RX_OTN_VLMARKER
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:25115"
wire width 56 output 62 \RX_PREOUT
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:25116"
wire width 5 output 63 \RX_PTP_PCSLANE_OUT
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:25117"
wire width 80 output 64 \RX_PTP_TSTAMP_OUT
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:25417"
wire input 364 \RX_RESET
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:25418"
wire width 16 input 365 \RX_SERDES_ALT_DATA0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:25419"
wire width 16 input 366 \RX_SERDES_ALT_DATA1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:25420"
wire width 16 input 367 \RX_SERDES_ALT_DATA2
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:25421"
wire width 16 input 368 \RX_SERDES_ALT_DATA3
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:25422"
wire width 10 input 369 \RX_SERDES_CLK
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:25423"
wire width 64 input 370 \RX_SERDES_DATA0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:25424"
wire width 64 input 371 \RX_SERDES_DATA1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:25425"
wire width 64 input 372 \RX_SERDES_DATA2
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:25426"
wire width 64 input 373 \RX_SERDES_DATA3
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:25427"
wire width 32 input 374 \RX_SERDES_DATA4
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:25428"
wire width 32 input 375 \RX_SERDES_DATA5
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:25429"
wire width 32 input 376 \RX_SERDES_DATA6
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:25430"
wire width 32 input 377 \RX_SERDES_DATA7
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:25431"
wire width 32 input 378 \RX_SERDES_DATA8
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:25432"
wire width 32 input 379 \RX_SERDES_DATA9
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:25433"
wire width 10 input 380 \RX_SERDES_RESET
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:25118"
wire output 65 \RX_SOPOUT0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:25119"
wire output 66 \RX_SOPOUT1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:25120"
wire output 67 \RX_SOPOUT2
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:25121"
wire output 68 \RX_SOPOUT3
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:25122"
wire output 69 \STAT_RX_ALIGNED
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:25123"
wire output 70 \STAT_RX_ALIGNED_ERR
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:25124"
wire width 3 output 71 \STAT_RX_BAD_CODE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:25125"
wire width 3 output 72 \STAT_RX_BAD_FCS
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:25126"
wire output 73 \STAT_RX_BAD_PREAMBLE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:25127"
wire output 74 \STAT_RX_BAD_SFD
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:25128"
wire output 75 \STAT_RX_BIP_ERR_0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:25129"
wire output 76 \STAT_RX_BIP_ERR_1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:25130"
wire output 77 \STAT_RX_BIP_ERR_10
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:25131"
wire output 78 \STAT_RX_BIP_ERR_11
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:25132"
wire output 79 \STAT_RX_BIP_ERR_12
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:25133"
wire output 80 \STAT_RX_BIP_ERR_13
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:25134"
wire output 81 \STAT_RX_BIP_ERR_14
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:25135"
wire output 82 \STAT_RX_BIP_ERR_15
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:25136"
wire output 83 \STAT_RX_BIP_ERR_16
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:25137"
wire output 84 \STAT_RX_BIP_ERR_17
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:25138"
wire output 85 \STAT_RX_BIP_ERR_18
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:25139"
wire output 86 \STAT_RX_BIP_ERR_19
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:25140"
wire output 87 \STAT_RX_BIP_ERR_2
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:25141"
wire output 88 \STAT_RX_BIP_ERR_3
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:25142"
wire output 89 \STAT_RX_BIP_ERR_4
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:25143"
wire output 90 \STAT_RX_BIP_ERR_5
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:25144"
wire output 91 \STAT_RX_BIP_ERR_6
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:25145"
wire output 92 \STAT_RX_BIP_ERR_7
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:25146"
wire output 93 \STAT_RX_BIP_ERR_8
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:25147"
wire output 94 \STAT_RX_BIP_ERR_9
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:25148"
wire width 20 output 95 \STAT_RX_BLOCK_LOCK
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:25149"
wire output 96 \STAT_RX_BROADCAST
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:25150"
wire width 3 output 97 \STAT_RX_FRAGMENT
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:25151"
wire width 2 output 98 \STAT_RX_FRAMING_ERR_0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:25152"
wire width 2 output 99 \STAT_RX_FRAMING_ERR_1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:25153"
wire width 2 output 100 \STAT_RX_FRAMING_ERR_10
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:25154"
wire width 2 output 101 \STAT_RX_FRAMING_ERR_11
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:25155"
wire width 2 output 102 \STAT_RX_FRAMING_ERR_12
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:25156"
wire width 2 output 103 \STAT_RX_FRAMING_ERR_13
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:25157"
wire width 2 output 104 \STAT_RX_FRAMING_ERR_14
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:25158"
wire width 2 output 105 \STAT_RX_FRAMING_ERR_15
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:25159"
wire width 2 output 106 \STAT_RX_FRAMING_ERR_16
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:25160"
wire width 2 output 107 \STAT_RX_FRAMING_ERR_17
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:25161"
wire width 2 output 108 \STAT_RX_FRAMING_ERR_18
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:25162"
wire width 2 output 109 \STAT_RX_FRAMING_ERR_19
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:25163"
wire width 2 output 110 \STAT_RX_FRAMING_ERR_2
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:25164"
wire width 2 output 111 \STAT_RX_FRAMING_ERR_3
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:25165"
wire width 2 output 112 \STAT_RX_FRAMING_ERR_4
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:25166"
wire width 2 output 113 \STAT_RX_FRAMING_ERR_5
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:25167"
wire width 2 output 114 \STAT_RX_FRAMING_ERR_6
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:25168"
wire width 2 output 115 \STAT_RX_FRAMING_ERR_7
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:25169"
wire width 2 output 116 \STAT_RX_FRAMING_ERR_8
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:25170"
wire width 2 output 117 \STAT_RX_FRAMING_ERR_9
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:25171"
wire output 118 \STAT_RX_FRAMING_ERR_VALID_0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:25172"
wire output 119 \STAT_RX_FRAMING_ERR_VALID_1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:25173"
wire output 120 \STAT_RX_FRAMING_ERR_VALID_10
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:25174"
wire output 121 \STAT_RX_FRAMING_ERR_VALID_11
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:25175"
wire output 122 \STAT_RX_FRAMING_ERR_VALID_12
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:25176"
wire output 123 \STAT_RX_FRAMING_ERR_VALID_13
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:25177"
wire output 124 \STAT_RX_FRAMING_ERR_VALID_14
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:25178"
wire output 125 \STAT_RX_FRAMING_ERR_VALID_15
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:25179"
wire output 126 \STAT_RX_FRAMING_ERR_VALID_16
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:25180"
wire output 127 \STAT_RX_FRAMING_ERR_VALID_17
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:25181"
wire output 128 \STAT_RX_FRAMING_ERR_VALID_18
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:25182"
wire output 129 \STAT_RX_FRAMING_ERR_VALID_19
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:25183"
wire output 130 \STAT_RX_FRAMING_ERR_VALID_2
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:25184"
wire output 131 \STAT_RX_FRAMING_ERR_VALID_3
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:25185"
wire output 132 \STAT_RX_FRAMING_ERR_VALID_4
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:25186"
wire output 133 \STAT_RX_FRAMING_ERR_VALID_5
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:25187"
wire output 134 \STAT_RX_FRAMING_ERR_VALID_6
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:25188"
wire output 135 \STAT_RX_FRAMING_ERR_VALID_7
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:25189"
wire output 136 \STAT_RX_FRAMING_ERR_VALID_8
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:25190"
wire output 137 \STAT_RX_FRAMING_ERR_VALID_9
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:25191"
wire output 138 \STAT_RX_GOT_SIGNAL_OS
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:25192"
wire output 139 \STAT_RX_HI_BER
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:25193"
wire output 140 \STAT_RX_INRANGEERR
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:25194"
wire output 141 \STAT_RX_INTERNAL_LOCAL_FAULT
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:25195"
wire output 142 \STAT_RX_JABBER
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:25196"
wire width 8 output 143 \STAT_RX_LANE0_VLM_BIP7
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:25197"
wire output 144 \STAT_RX_LANE0_VLM_BIP7_VALID
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:25198"
wire output 145 \STAT_RX_LOCAL_FAULT
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:25199"
wire width 20 output 146 \STAT_RX_MF_ERR
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:25200"
wire width 20 output 147 \STAT_RX_MF_LEN_ERR
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:25201"
wire width 20 output 148 \STAT_RX_MF_REPEAT_ERR
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:25202"
wire output 149 \STAT_RX_MISALIGNED
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:25203"
wire output 150 \STAT_RX_MULTICAST
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:25204"
wire output 151 \STAT_RX_OVERSIZE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:25205"
wire output 152 \STAT_RX_PACKET_1024_1518_BYTES
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:25206"
wire output 153 \STAT_RX_PACKET_128_255_BYTES
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:25207"
wire output 154 \STAT_RX_PACKET_1519_1522_BYTES
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:25208"
wire output 155 \STAT_RX_PACKET_1523_1548_BYTES
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:25209"
wire output 156 \STAT_RX_PACKET_1549_2047_BYTES
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:25210"
wire output 157 \STAT_RX_PACKET_2048_4095_BYTES
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:25211"
wire output 158 \STAT_RX_PACKET_256_511_BYTES
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:25212"
wire output 159 \STAT_RX_PACKET_4096_8191_BYTES
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:25213"
wire output 160 \STAT_RX_PACKET_512_1023_BYTES
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:25214"
wire output 161 \STAT_RX_PACKET_64_BYTES
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:25215"
wire output 162 \STAT_RX_PACKET_65_127_BYTES
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:25216"
wire output 163 \STAT_RX_PACKET_8192_9215_BYTES
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:25217"
wire output 164 \STAT_RX_PACKET_BAD_FCS
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:25218"
wire output 165 \STAT_RX_PACKET_LARGE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:25219"
wire width 3 output 166 \STAT_RX_PACKET_SMALL
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:25220"
wire output 167 \STAT_RX_PAUSE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:25221"
wire width 16 output 168 \STAT_RX_PAUSE_QUANTA0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:25222"
wire width 16 output 169 \STAT_RX_PAUSE_QUANTA1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:25223"
wire width 16 output 170 \STAT_RX_PAUSE_QUANTA2
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:25224"
wire width 16 output 171 \STAT_RX_PAUSE_QUANTA3
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:25225"
wire width 16 output 172 \STAT_RX_PAUSE_QUANTA4
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:25226"
wire width 16 output 173 \STAT_RX_PAUSE_QUANTA5
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:25227"
wire width 16 output 174 \STAT_RX_PAUSE_QUANTA6
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:25228"
wire width 16 output 175 \STAT_RX_PAUSE_QUANTA7
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:25229"
wire width 16 output 176 \STAT_RX_PAUSE_QUANTA8
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:25230"
wire width 9 output 177 \STAT_RX_PAUSE_REQ
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:25231"
wire width 9 output 178 \STAT_RX_PAUSE_VALID
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:25232"
wire output 179 \STAT_RX_RECEIVED_LOCAL_FAULT
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:25233"
wire output 180 \STAT_RX_REMOTE_FAULT
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:25234"
wire output 181 \STAT_RX_RSFEC_AM_LOCK0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:25235"
wire output 182 \STAT_RX_RSFEC_AM_LOCK1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:25236"
wire output 183 \STAT_RX_RSFEC_AM_LOCK2
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:25237"
wire output 184 \STAT_RX_RSFEC_AM_LOCK3
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:25238"
wire output 185 \STAT_RX_RSFEC_CORRECTED_CW_INC
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:25239"
wire output 186 \STAT_RX_RSFEC_CW_INC
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:25240"
wire width 3 output 187 \STAT_RX_RSFEC_ERR_COUNT0_INC
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:25241"
wire width 3 output 188 \STAT_RX_RSFEC_ERR_COUNT1_INC
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:25242"
wire width 3 output 189 \STAT_RX_RSFEC_ERR_COUNT2_INC
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:25243"
wire width 3 output 190 \STAT_RX_RSFEC_ERR_COUNT3_INC
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:25244"
wire output 191 \STAT_RX_RSFEC_HI_SER
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:25245"
wire output 192 \STAT_RX_RSFEC_LANE_ALIGNMENT_STATUS
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:25246"
wire width 14 output 193 \STAT_RX_RSFEC_LANE_FILL_0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:25247"
wire width 14 output 194 \STAT_RX_RSFEC_LANE_FILL_1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:25248"
wire width 14 output 195 \STAT_RX_RSFEC_LANE_FILL_2
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:25249"
wire width 14 output 196 \STAT_RX_RSFEC_LANE_FILL_3
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:25250"
wire width 8 output 197 \STAT_RX_RSFEC_LANE_MAPPING
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:25251"
wire width 32 output 198 \STAT_RX_RSFEC_RSVD
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:25252"
wire output 199 \STAT_RX_RSFEC_UNCORRECTED_CW_INC
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:25253"
wire output 200 \STAT_RX_STATUS
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:25254"
wire width 3 output 201 \STAT_RX_STOMPED_FCS
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:25255"
wire width 20 output 202 \STAT_RX_SYNCED
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:25256"
wire width 20 output 203 \STAT_RX_SYNCED_ERR
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:25257"
wire width 3 output 204 \STAT_RX_TEST_PATTERN_MISMATCH
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:25258"
wire output 205 \STAT_RX_TOOLONG
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:25259"
wire width 7 output 206 \STAT_RX_TOTAL_BYTES
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:25260"
wire width 14 output 207 \STAT_RX_TOTAL_GOOD_BYTES
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:25261"
wire output 208 \STAT_RX_TOTAL_GOOD_PACKETS
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:25262"
wire width 3 output 209 \STAT_RX_TOTAL_PACKETS
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:25263"
wire output 210 \STAT_RX_TRUNCATED
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:25264"
wire width 3 output 211 \STAT_RX_UNDERSIZE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:25265"
wire output 212 \STAT_RX_UNICAST
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:25266"
wire output 213 \STAT_RX_USER_PAUSE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:25267"
wire output 214 \STAT_RX_VLAN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:25268"
wire width 20 output 215 \STAT_RX_VL_DEMUXED
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:25269"
wire width 5 output 216 \STAT_RX_VL_NUMBER_0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:25270"
wire width 5 output 217 \STAT_RX_VL_NUMBER_1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:25271"
wire width 5 output 218 \STAT_RX_VL_NUMBER_10
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:25272"
wire width 5 output 219 \STAT_RX_VL_NUMBER_11
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:25273"
wire width 5 output 220 \STAT_RX_VL_NUMBER_12
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:25274"
wire width 5 output 221 \STAT_RX_VL_NUMBER_13
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:25275"
wire width 5 output 222 \STAT_RX_VL_NUMBER_14
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:25276"
wire width 5 output 223 \STAT_RX_VL_NUMBER_15
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:25277"
wire width 5 output 224 \STAT_RX_VL_NUMBER_16
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:25278"
wire width 5 output 225 \STAT_RX_VL_NUMBER_17
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:25279"
wire width 5 output 226 \STAT_RX_VL_NUMBER_18
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:25280"
wire width 5 output 227 \STAT_RX_VL_NUMBER_19
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:25281"
wire width 5 output 228 \STAT_RX_VL_NUMBER_2
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:25282"
wire width 5 output 229 \STAT_RX_VL_NUMBER_3
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:25283"
wire width 5 output 230 \STAT_RX_VL_NUMBER_4
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:25284"
wire width 5 output 231 \STAT_RX_VL_NUMBER_5
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:25285"
wire width 5 output 232 \STAT_RX_VL_NUMBER_6
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:25286"
wire width 5 output 233 \STAT_RX_VL_NUMBER_7
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:25287"
wire width 5 output 234 \STAT_RX_VL_NUMBER_8
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:25288"
wire width 5 output 235 \STAT_RX_VL_NUMBER_9
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:25289"
wire output 236 \STAT_TX_BAD_FCS
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:25290"
wire output 237 \STAT_TX_BROADCAST
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:25291"
wire output 238 \STAT_TX_FRAME_ERROR
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:25292"
wire output 239 \STAT_TX_LOCAL_FAULT
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:25293"
wire output 240 \STAT_TX_MULTICAST
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:25294"
wire output 241 \STAT_TX_PACKET_1024_1518_BYTES
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:25295"
wire output 242 \STAT_TX_PACKET_128_255_BYTES
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:25296"
wire output 243 \STAT_TX_PACKET_1519_1522_BYTES
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:25297"
wire output 244 \STAT_TX_PACKET_1523_1548_BYTES
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:25298"
wire output 245 \STAT_TX_PACKET_1549_2047_BYTES
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:25299"
wire output 246 \STAT_TX_PACKET_2048_4095_BYTES
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:25300"
wire output 247 \STAT_TX_PACKET_256_511_BYTES
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:25301"
wire output 248 \STAT_TX_PACKET_4096_8191_BYTES
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:25302"
wire output 249 \STAT_TX_PACKET_512_1023_BYTES
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:25303"
wire output 250 \STAT_TX_PACKET_64_BYTES
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:25304"
wire output 251 \STAT_TX_PACKET_65_127_BYTES
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:25305"
wire output 252 \STAT_TX_PACKET_8192_9215_BYTES
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:25306"
wire output 253 \STAT_TX_PACKET_LARGE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:25307"
wire output 254 \STAT_TX_PACKET_SMALL
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:25308"
wire output 255 \STAT_TX_PAUSE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:25309"
wire width 9 output 256 \STAT_TX_PAUSE_VALID
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:25310"
wire output 257 \STAT_TX_PTP_FIFO_READ_ERROR
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:25311"
wire output 258 \STAT_TX_PTP_FIFO_WRITE_ERROR
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:25312"
wire width 6 output 259 \STAT_TX_TOTAL_BYTES
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:25313"
wire width 14 output 260 \STAT_TX_TOTAL_GOOD_BYTES
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:25314"
wire output 261 \STAT_TX_TOTAL_GOOD_PACKETS
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:25315"
wire output 262 \STAT_TX_TOTAL_PACKETS
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:25316"
wire output 263 \STAT_TX_UNICAST
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:25317"
wire output 264 \STAT_TX_USER_PAUSE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:25318"
wire output 265 \STAT_TX_VLAN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:25434"
wire input 381 \TX_CLK
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:25435"
wire width 128 input 382 \TX_DATAIN0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:25436"
wire width 128 input 383 \TX_DATAIN1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:25437"
wire width 128 input 384 \TX_DATAIN2
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:25438"
wire width 128 input 385 \TX_DATAIN3
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:25439"
wire input 386 \TX_ENAIN0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:25440"
wire input 387 \TX_ENAIN1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:25441"
wire input 388 \TX_ENAIN2
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:25442"
wire input 389 \TX_ENAIN3
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:25443"
wire input 390 \TX_EOPIN0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:25444"
wire input 391 \TX_EOPIN1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:25445"
wire input 392 \TX_EOPIN2
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:25446"
wire input 393 \TX_EOPIN3
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:25447"
wire input 394 \TX_ERRIN0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:25448"
wire input 395 \TX_ERRIN1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:25449"
wire input 396 \TX_ERRIN2
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:25450"
wire input 397 \TX_ERRIN3
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:25451"
wire width 4 input 398 \TX_MTYIN0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:25452"
wire width 4 input 399 \TX_MTYIN1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:25453"
wire width 4 input 400 \TX_MTYIN2
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:25454"
wire width 4 input 401 \TX_MTYIN3
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:25319"
wire output 266 \TX_OVFOUT
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:25455"
wire width 56 input 402 \TX_PREIN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:25456"
wire width 2 input 403 \TX_PTP_1588OP_IN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:25457"
wire width 16 input 404 \TX_PTP_CHKSUM_OFFSET_IN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:25320"
wire width 5 output 267 \TX_PTP_PCSLANE_OUT
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:25458"
wire width 64 input 405 \TX_PTP_RXTSTAMP_IN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:25459"
wire width 16 input 406 \TX_PTP_TAG_FIELD_IN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:25460"
wire width 16 input 407 \TX_PTP_TSTAMP_OFFSET_IN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:25321"
wire width 80 output 268 \TX_PTP_TSTAMP_OUT
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:25322"
wire width 16 output 269 \TX_PTP_TSTAMP_TAG_OUT
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:25323"
wire output 270 \TX_PTP_TSTAMP_VALID_OUT
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:25461"
wire input 408 \TX_PTP_UPD_CHKSUM_IN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:25324"
wire output 271 \TX_RDYOUT
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:25462"
wire input 409 \TX_RESET
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:25325"
wire width 16 output 272 \TX_SERDES_ALT_DATA0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:25326"
wire width 16 output 273 \TX_SERDES_ALT_DATA1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:25327"
wire width 16 output 274 \TX_SERDES_ALT_DATA2
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:25328"
wire width 16 output 275 \TX_SERDES_ALT_DATA3
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:25329"
wire width 64 output 276 \TX_SERDES_DATA0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:25330"
wire width 64 output 277 \TX_SERDES_DATA1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:25331"
wire width 64 output 278 \TX_SERDES_DATA2
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:25332"
wire width 64 output 279 \TX_SERDES_DATA3
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:25333"
wire width 32 output 280 \TX_SERDES_DATA4
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:25334"
wire width 32 output 281 \TX_SERDES_DATA5
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:25335"
wire width 32 output 282 \TX_SERDES_DATA6
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:25336"
wire width 32 output 283 \TX_SERDES_DATA7
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:25337"
wire width 32 output 284 \TX_SERDES_DATA8
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:25338"
wire width 32 output 285 \TX_SERDES_DATA9
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:25463"
wire input 410 \TX_SOPIN0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:25464"
wire input 411 \TX_SOPIN1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:25465"
wire input 412 \TX_SOPIN2
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:25466"
wire input 413 \TX_SOPIN3
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:25339"
wire output 286 \TX_UNFOUT
end
attribute \blackbox 1
attribute \cells_not_processed 1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12087"
module \CRC32
parameter \CRC_INIT
attribute \clkbuf_sink 1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12091"
wire input 2 \CRCCLK
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12092"
wire input 3 \CRCDATAVALID
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12093"
wire width 3 input 4 \CRCDATAWIDTH
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12094"
wire width 32 input 5 \CRCIN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12089"
wire width 32 output 1 \CRCOUT
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12095"
wire input 6 \CRCRESET
end
attribute \blackbox 1
attribute \cells_not_processed 1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12098"
module \CRC64
parameter \CRC_INIT
attribute \clkbuf_sink 1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12102"
wire input 2 \CRCCLK
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12103"
wire input 3 \CRCDATAVALID
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12104"
wire width 3 input 4 \CRCDATAWIDTH
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12105"
wire width 64 input 5 \CRCIN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12100"
wire width 32 output 1 \CRCOUT
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12106"
wire input 6 \CRCRESET
end
attribute \blackbox 1
attribute \keep 1
attribute \cells_not_processed 1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7647"
module \DCIRESET
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7648"
wire output 1 \LOCKED
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7649"
wire input 2 \RST
end
attribute \blackbox 1
attribute \cells_not_processed 1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7857"
module \DCM
parameter \CLKDV_DIVIDE
parameter \CLKFX_DIVIDE
parameter \CLKFX_MULTIPLY
parameter \CLKIN_DIVIDE_BY_2
parameter \CLKIN_PERIOD
parameter \CLKOUT_PHASE_SHIFT
parameter \CLK_FEEDBACK
parameter \DESKEW_ADJUST
parameter \DFS_FREQUENCY_MODE
parameter \DLL_FREQUENCY_MODE
parameter \DSS_MODE
parameter \DUTY_CYCLE_CORRECTION
parameter \FACTORY_JF
parameter \PHASE_SHIFT
parameter \SIM_MODE
parameter \STARTUP_WAIT
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7881"
wire output 8 \CLK0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7882"
wire output 9 \CLK180
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7883"
wire output 10 \CLK270
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7884"
wire output 11 \CLK2X
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7885"
wire output 12 \CLK2X180
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7886"
wire output 13 \CLK90
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7887"
wire output 14 \CLKDV
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7874"
wire input 1 \CLKFB
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7888"
wire output 15 \CLKFX
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7889"
wire output 16 \CLKFX180
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7875"
wire input 2 \CLKIN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7876"
wire input 3 \DSSEN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7890"
wire output 17 \LOCKED
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7877"
wire input 4 \PSCLK
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7891"
wire output 18 \PSDONE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7878"
wire input 5 \PSEN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7879"
wire input 6 \PSINCDEC
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7880"
wire input 7 \RST
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7892"
wire width 8 output 19 \STATUS
end
attribute \blackbox 1
attribute \cells_not_processed 1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7954"
module \DCM_ADV
parameter \CLKDV_DIVIDE
parameter \CLKFX_DIVIDE
parameter \CLKFX_MULTIPLY
parameter \CLKIN_DIVIDE_BY_2
parameter \CLKIN_PERIOD
parameter \CLKOUT_PHASE_SHIFT
parameter \CLK_FEEDBACK
parameter \DCM_AUTOCALIBRATION
parameter \DCM_PERFORMANCE_MODE
parameter \DESKEW_ADJUST
parameter \DFS_FREQUENCY_MODE
parameter \DLL_FREQUENCY_MODE
parameter \DUTY_CYCLE_CORRECTION
parameter \FACTORY_JF
parameter \PHASE_SHIFT
parameter \SIM_DEVICE
parameter \STARTUP_WAIT
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7972"
wire output 1 \CLK0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7973"
wire output 2 \CLK180
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7974"
wire output 3 \CLK270
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7976"
wire output 5 \CLK2X
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7975"
wire output 4 \CLK2X180
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7977"
wire output 6 \CLK90
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7978"
wire output 7 \CLKDV
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7985"
wire input 14 \CLKFB
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7980"
wire output 9 \CLKFX
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7979"
wire output 8 \CLKFX180
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7986"
wire input 15 \CLKIN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7995"
wire width 7 input 24 \DADDR
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7987"
wire input 16 \DCLK
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7988"
wire input 17 \DEN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7994"
wire width 16 input 23 \DI
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7984"
wire width 16 output 13 \DO
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7981"
wire output 10 \DRDY
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7989"
wire input 18 \DWE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7982"
wire output 11 \LOCKED
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7990"
wire input 19 \PSCLK
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7983"
wire output 12 \PSDONE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7991"
wire input 20 \PSEN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7992"
wire input 21 \PSINCDEC
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7993"
wire input 22 \RST
end
attribute \blackbox 1
attribute \cells_not_processed 1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7998"
module \DCM_BASE
parameter \CLKDV_DIVIDE
parameter \CLKFX_DIVIDE
parameter \CLKFX_MULTIPLY
parameter \CLKIN_DIVIDE_BY_2
parameter \CLKIN_PERIOD
parameter \CLKOUT_PHASE_SHIFT
parameter \CLK_FEEDBACK
parameter \DCM_AUTOCALIBRATION
parameter \DCM_PERFORMANCE_MODE
parameter \DESKEW_ADJUST
parameter \DFS_FREQUENCY_MODE
parameter \DLL_FREQUENCY_MODE
parameter \DUTY_CYCLE_CORRECTION
parameter \FACTORY_JF
parameter \PHASE_SHIFT
parameter \STARTUP_WAIT
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:8015"
wire output 1 \CLK0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:8016"
wire output 2 \CLK180
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:8017"
wire output 3 \CLK270
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:8019"
wire output 5 \CLK2X
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:8018"
wire output 4 \CLK2X180
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:8020"
wire output 6 \CLK90
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:8021"
wire output 7 \CLKDV
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:8025"
wire input 11 \CLKFB
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:8023"
wire output 9 \CLKFX
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:8022"
wire output 8 \CLKFX180
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:8026"
wire input 12 \CLKIN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:8024"
wire output 10 \LOCKED
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:8027"
wire input 13 \RST
end
attribute \blackbox 1
attribute \cells_not_processed 1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7932"
module \DCM_CLKGEN
parameter \CLKFXDV_DIVIDE
parameter \CLKFX_DIVIDE
parameter \CLKFX_MD_MAX
parameter \CLKFX_MULTIPLY
parameter \CLKIN_PERIOD
parameter \SPREAD_SPECTRUM
parameter \STARTUP_WAIT
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7941"
wire output 2 \CLKFX
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7940"
wire output 1 \CLKFX180
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7942"
wire output 3 \CLKFXDV
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7946"
wire input 7 \CLKIN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7947"
wire input 8 \FREEZEDCM
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7943"
wire output 4 \LOCKED
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7948"
wire input 9 \PROGCLK
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7949"
wire input 10 \PROGDATA
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7944"
wire output 5 \PROGDONE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7950"
wire input 11 \PROGEN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7951"
wire input 12 \RST
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7945"
wire width 2 offset 1 output 6 \STATUS
end
attribute \blackbox 1
attribute \cells_not_processed 1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:8030"
module \DCM_PS
parameter \CLKDV_DIVIDE
parameter \CLKFX_DIVIDE
parameter \CLKFX_MULTIPLY
parameter \CLKIN_DIVIDE_BY_2
parameter \CLKIN_PERIOD
parameter \CLKOUT_PHASE_SHIFT
parameter \CLK_FEEDBACK
parameter \DCM_AUTOCALIBRATION
parameter \DCM_PERFORMANCE_MODE
parameter \DESKEW_ADJUST
parameter \DFS_FREQUENCY_MODE
parameter \DLL_FREQUENCY_MODE
parameter \DUTY_CYCLE_CORRECTION
parameter \FACTORY_JF
parameter \PHASE_SHIFT
parameter \STARTUP_WAIT
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:8047"
wire output 1 \CLK0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:8048"
wire output 2 \CLK180
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:8049"
wire output 3 \CLK270
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:8051"
wire output 5 \CLK2X
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:8050"
wire output 4 \CLK2X180
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:8052"
wire output 6 \CLK90
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:8053"
wire output 7 \CLKDV
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:8059"
wire input 13 \CLKFB
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:8055"
wire output 9 \CLKFX
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:8054"
wire output 8 \CLKFX180
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:8060"
wire input 14 \CLKIN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:8058"
wire width 16 output 12 \DO
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:8056"
wire output 10 \LOCKED
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:8061"
wire input 15 \PSCLK
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:8057"
wire output 11 \PSDONE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:8062"
wire input 16 \PSEN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:8063"
wire input 17 \PSINCDEC
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:8064"
wire input 18 \RST
end
attribute \blackbox 1
attribute \cells_not_processed 1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7895"
module \DCM_SP
parameter \CLKDV_DIVIDE
parameter \CLKFX_DIVIDE
parameter \CLKFX_MULTIPLY
parameter \CLKIN_DIVIDE_BY_2
parameter \CLKIN_PERIOD
parameter \CLKOUT_PHASE_SHIFT
parameter \CLK_FEEDBACK
parameter \DESKEW_ADJUST
parameter \DFS_FREQUENCY_MODE
parameter \DLL_FREQUENCY_MODE
parameter \DSS_MODE
parameter \DUTY_CYCLE_CORRECTION
parameter \FACTORY_JF
parameter \PHASE_SHIFT
parameter \STARTUP_WAIT
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7918"
wire output 8 \CLK0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7919"
wire output 9 \CLK180
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7920"
wire output 10 \CLK270
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7921"
wire output 11 \CLK2X
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7922"
wire output 12 \CLK2X180
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7923"
wire output 13 \CLK90
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7924"
wire output 14 \CLKDV
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7911"
wire input 1 \CLKFB
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7925"
wire output 15 \CLKFX
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7926"
wire output 16 \CLKFX180
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7912"
wire input 2 \CLKIN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7913"
wire input 3 \DSSEN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7927"
wire output 17 \LOCKED
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7914"
wire input 4 \PSCLK
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7928"
wire output 18 \PSDONE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7915"
wire input 5 \PSEN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7916"
wire input 6 \PSINCDEC
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7917"
wire input 7 \RST
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7929"
wire width 8 output 19 \STATUS
end
attribute \blackbox 1
attribute \cells_not_processed 1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:9535"
module \DNA_PORT
parameter \SIM_DNA_VALUE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:9538"
wire input 2 \CLK
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:9539"
wire input 3 \DIN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:9537"
wire output 1 \DOUT
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:9540"
wire input 4 \READ
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:9541"
wire input 5 \SHIFT
end
attribute \blackbox 1
attribute \cells_not_processed 1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:9544"
module \DNA_PORTE2
parameter \SIM_DNA_VALUE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:9547"
wire input 2 \CLK
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:9548"
wire input 3 \DIN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:9546"
wire output 1 \DOUT
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:9549"
wire input 4 \READ
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:9550"
wire input 5 \SHIFT
end
attribute \blackbox 1
attribute \cells_not_processed 1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:5479"
module \DSP48
parameter \AREG
parameter \BREG
parameter \B_INPUT
parameter \CARRYINREG
parameter \CARRYINSELREG
parameter \CREG
parameter \LEGACY_MODE
parameter \MREG
parameter \OPMODEREG
parameter \PREG
parameter \SUBTRACTREG
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:5494"
wire width 18 input 4 \A
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:5495"
wire width 18 input 5 \B
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:5496"
wire width 18 input 6 \BCIN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:5491"
wire width 18 output 1 \BCOUT
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:5497"
wire width 48 input 7 \C
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:5498"
wire input 8 \CARRYIN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:5499"
wire width 2 input 9 \CARRYINSEL
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:5500"
wire input 10 \CEA
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:5501"
wire input 11 \CEB
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:5502"
wire input 12 \CEC
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:5503"
wire input 13 \CECARRYIN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:5504"
wire input 14 \CECINSUB
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:5505"
wire input 15 \CECTRL
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:5506"
wire input 16 \CEM
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:5507"
wire input 17 \CEP
attribute \clkbuf_sink 1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:5509"
wire input 18 \CLK
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:5510"
wire width 7 input 19 \OPMODE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:5492"
wire width 48 output 2 \P
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:5511"
wire width 48 input 20 \PCIN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:5493"
wire width 48 output 3 \PCOUT
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:5512"
wire input 21 \RSTA
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:5513"
wire input 22 \RSTB
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:5514"
wire input 23 \RSTC
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:5515"
wire input 24 \RSTCARRYIN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:5516"
wire input 25 \RSTCTRL
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:5517"
wire input 26 \RSTM
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:5518"
wire input 27 \RSTP
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:5519"
wire input 28 \SUBTRACT
end
attribute \blackbox 1
attribute \cells_not_processed 1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_sim.v:1764"
module \DSP48A
parameter \A0REG
parameter \A1REG
parameter \B0REG
parameter \B1REG
parameter \CARRYINREG
parameter \CARRYINSEL
parameter \CREG
parameter \DREG
parameter \MREG
parameter \OPMODEREG
parameter \PREG
parameter \RSTTYPE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_sim.v:1765"
wire width 18 input 1 \A
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_sim.v:1766"
wire width 18 input 2 \B
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_sim.v:1773"
wire width 18 output 9 \BCOUT
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_sim.v:1767"
wire width 48 input 3 \C
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_sim.v:1770"
wire input 6 \CARRYIN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_sim.v:1775"
wire output 11 \CARRYOUT
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_sim.v:1778"
wire input 13 \CEA
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_sim.v:1779"
wire input 14 \CEB
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_sim.v:1780"
wire input 15 \CEC
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_sim.v:1783"
wire input 18 \CECARRYIN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_sim.v:1781"
wire input 16 \CED
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_sim.v:1782"
wire input 17 \CEM
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_sim.v:1784"
wire input 19 \CEOPMODE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_sim.v:1785"
wire input 20 \CEP
attribute \clkbuf_sink 1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_sim.v:1777"
wire input 12 \CLK
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_sim.v:1768"
wire width 18 input 4 \D
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_sim.v:1771"
wire width 8 input 7 \OPMODE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_sim.v:1772"
wire width 48 output 8 \P
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_sim.v:1769"
wire width 48 input 5 \PCIN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_sim.v:1774"
wire width 48 output 10 \PCOUT
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_sim.v:1786"
wire input 21 \RSTA
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_sim.v:1787"
wire input 22 \RSTB
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_sim.v:1788"
wire input 23 \RSTC
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_sim.v:1791"
wire input 26 \RSTCARRYIN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_sim.v:1789"
wire input 24 \RSTD
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_sim.v:1790"
wire input 25 \RSTM
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_sim.v:1792"
wire input 27 \RSTOPMODE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_sim.v:1793"
wire input 28 \RSTP
end
attribute \blackbox 1
attribute \cells_not_processed 1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_sim.v:1862"
module \DSP48A1
parameter \A0REG
parameter \A1REG
parameter \B0REG
parameter \B1REG
parameter \CARRYINREG
parameter \CARRYINSEL
parameter \CARRYOUTREG
parameter \CREG
parameter \DREG
parameter \MREG
parameter \OPMODEREG
parameter \PREG
parameter \RSTTYPE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_sim.v:1863"
wire width 18 input 1 \A
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_sim.v:1864"
wire width 18 input 2 \B
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_sim.v:1872"
wire width 18 output 10 \BCOUT
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_sim.v:1865"
wire width 48 input 3 \C
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_sim.v:1868"
wire input 6 \CARRYIN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_sim.v:1874"
wire output 12 \CARRYOUT
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_sim.v:1875"
wire output 13 \CARRYOUTF
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_sim.v:1878"
wire input 15 \CEA
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_sim.v:1879"
wire input 16 \CEB
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_sim.v:1880"
wire input 17 \CEC
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_sim.v:1883"
wire input 20 \CECARRYIN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_sim.v:1881"
wire input 18 \CED
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_sim.v:1882"
wire input 19 \CEM
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_sim.v:1884"
wire input 21 \CEOPMODE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_sim.v:1885"
wire input 22 \CEP
attribute \clkbuf_sink 1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_sim.v:1877"
wire input 14 \CLK
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_sim.v:1866"
wire width 18 input 4 \D
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_sim.v:1870"
wire width 36 output 8 \M
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_sim.v:1869"
wire width 8 input 7 \OPMODE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_sim.v:1871"
wire width 48 output 9 \P
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_sim.v:1867"
wire width 48 input 5 \PCIN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_sim.v:1873"
wire width 48 output 11 \PCOUT
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_sim.v:1886"
wire input 23 \RSTA
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_sim.v:1887"
wire input 24 \RSTB
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_sim.v:1888"
wire input 25 \RSTC
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_sim.v:1891"
wire input 28 \RSTCARRYIN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_sim.v:1889"
wire input 26 \RSTD
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_sim.v:1890"
wire input 27 \RSTM
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_sim.v:1892"
wire input 29 \RSTOPMODE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_sim.v:1893"
wire input 30 \RSTP
end
attribute \blackbox 1
attribute \cells_not_processed 1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:5522"
module \DSP48E
parameter \ACASCREG
parameter \ALUMODEREG
parameter \AREG
parameter \AUTORESET_PATTERN_DETECT
parameter \AUTORESET_PATTERN_DETECT_OPTINV
parameter \A_INPUT
parameter \BCASCREG
parameter \BREG
parameter \B_INPUT
parameter \CARRYINREG
parameter \CARRYINSELREG
parameter \CREG
parameter \MASK
parameter \MREG
parameter \MULTCARRYINREG
parameter \OPMODEREG
parameter \PATTERN
parameter \PREG
parameter \SEL_MASK
parameter \SEL_PATTERN
parameter \SEL_ROUNDING_MASK
parameter \SIM_MODE
parameter \USE_MULT
parameter \USE_PATTERN_DETECT
parameter \USE_SIMD
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:5559"
wire width 30 input 12 \A
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:5560"
wire width 30 input 13 \ACIN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:5548"
wire width 30 output 1 \ACOUT
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:5561"
wire width 4 input 14 \ALUMODE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:5562"
wire width 18 input 15 \B
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:5563"
wire width 18 input 16 \BCIN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:5549"
wire width 18 output 2 \BCOUT
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:5564"
wire width 48 input 17 \C
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:5565"
wire input 18 \CARRYCASCIN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:5550"
wire output 3 \CARRYCASCOUT
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:5566"
wire input 19 \CARRYIN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:5567"
wire width 3 input 20 \CARRYINSEL
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:5551"
wire width 4 output 4 \CARRYOUT
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:5568"
wire input 21 \CEA1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:5569"
wire input 22 \CEA2
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:5570"
wire input 23 \CEALUMODE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:5571"
wire input 24 \CEB1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:5572"
wire input 25 \CEB2
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:5573"
wire input 26 \CEC
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:5574"
wire input 27 \CECARRYIN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:5575"
wire input 28 \CECTRL
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:5576"
wire input 29 \CEM
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:5577"
wire input 30 \CEMULTCARRYIN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:5578"
wire input 31 \CEP
attribute \clkbuf_sink 1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:5580"
wire input 32 \CLK
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:5581"
wire input 33 \MULTSIGNIN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:5552"
wire output 5 \MULTSIGNOUT
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:5582"
wire width 7 input 34 \OPMODE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:5553"
wire output 6 \OVERFLOW
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:5554"
wire width 48 output 7 \P
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:5555"
wire output 8 \PATTERNBDETECT
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:5556"
wire output 9 \PATTERNDETECT
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:5583"
wire width 48 input 35 \PCIN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:5557"
wire width 48 output 10 \PCOUT
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:5584"
wire input 36 \RSTA
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:5585"
wire input 37 \RSTALLCARRYIN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:5586"
wire input 38 \RSTALUMODE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:5587"
wire input 39 \RSTB
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:5588"
wire input 40 \RSTC
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:5589"
wire input 41 \RSTCTRL
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:5590"
wire input 42 \RSTM
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:5591"
wire input 43 \RSTP
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:5558"
wire output 11 \UNDERFLOW
end
attribute \blackbox 1
attribute \cells_not_processed 1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_sim.v:2164"
module \DSP48E1
parameter \ACASCREG
parameter \ADREG
parameter \ALUMODEREG
parameter \AREG
parameter \AUTORESET_PATDET
parameter \A_INPUT
parameter \BCASCREG
parameter \BREG
parameter \B_INPUT
parameter \CARRYINREG
parameter \CARRYINSELREG
parameter \CREG
parameter \DREG
parameter \INMODEREG
parameter \IS_ALUMODE_INVERTED
parameter \IS_CARRYIN_INVERTED
parameter \IS_CLK_INVERTED
parameter \IS_INMODE_INVERTED
parameter \IS_OPMODE_INVERTED
parameter \MASK
parameter \MREG
parameter \OPMODEREG
parameter \PATTERN
parameter \PREG
parameter \SEL_MASK
parameter \SEL_PATTERN
parameter \USE_DPORT
parameter \USE_MULT
parameter \USE_PATTERN_DETECT
parameter \USE_SIMD
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_sim.v:2182"
wire width 30 input 12 \A
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_sim.v:2183"
wire width 30 input 13 \ACIN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_sim.v:2165"
wire width 30 output 1 \ACOUT
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_sim.v:2184"
wire width 4 input 14 \ALUMODE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_sim.v:2185"
wire width 18 input 15 \B
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_sim.v:2186"
wire width 18 input 16 \BCIN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_sim.v:2166"
wire width 18 output 2 \BCOUT
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_sim.v:2187"
wire width 48 input 17 \C
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_sim.v:2188"
wire input 18 \CARRYCASCIN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_sim.v:2167"
wire output 3 \CARRYCASCOUT
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_sim.v:2189"
wire input 19 \CARRYIN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_sim.v:2190"
wire width 3 input 20 \CARRYINSEL
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_sim.v:2168"
wire width 4 output 4 \CARRYOUT
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_sim.v:2191"
wire input 21 \CEA1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_sim.v:2192"
wire input 22 \CEA2
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_sim.v:2193"
wire input 23 \CEAD
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_sim.v:2194"
wire input 24 \CEALUMODE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_sim.v:2195"
wire input 25 \CEB1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_sim.v:2196"
wire input 26 \CEB2
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_sim.v:2197"
wire input 27 \CEC
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_sim.v:2198"
wire input 28 \CECARRYIN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_sim.v:2199"
wire input 29 \CECTRL
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_sim.v:2200"
wire input 30 \CED
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_sim.v:2201"
wire input 31 \CEINMODE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_sim.v:2202"
wire input 32 \CEM
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_sim.v:2203"
wire input 33 \CEP
attribute \clkbuf_sink 1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_sim.v:2204"
wire input 34 \CLK
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_sim.v:2205"
wire width 25 input 35 \D
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_sim.v:2206"
wire width 5 input 36 \INMODE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_sim.v:2207"
wire input 37 \MULTSIGNIN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_sim.v:2169"
wire output 5 \MULTSIGNOUT
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_sim.v:2208"
wire width 7 input 38 \OPMODE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_sim.v:2170"
wire output 6 \OVERFLOW
attribute \abc9_arrival 329
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_sim.v:2174"
wire width 48 output 7 \P
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_sim.v:2175"
wire output 8 \PATTERNBDETECT
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_sim.v:2176"
wire output 9 \PATTERNDETECT
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_sim.v:2209"
wire width 48 input 39 \PCIN
attribute \abc9_arrival 435
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_sim.v:2180"
wire width 48 output 10 \PCOUT
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_sim.v:2210"
wire input 40 \RSTA
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_sim.v:2211"
wire input 41 \RSTALLCARRYIN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_sim.v:2212"
wire input 42 \RSTALUMODE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_sim.v:2213"
wire input 43 \RSTB
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_sim.v:2214"
wire input 44 \RSTC
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_sim.v:2215"
wire input 45 \RSTCTRL
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_sim.v:2216"
wire input 46 \RSTD
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_sim.v:2217"
wire input 47 \RSTINMODE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_sim.v:2218"
wire input 48 \RSTM
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_sim.v:2219"
wire input 49 \RSTP
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_sim.v:2181"
wire output 11 \UNDERFLOW
end
attribute \blackbox 1
attribute \cells_not_processed 1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:5594"
module \DSP48E2
parameter \ACASCREG
parameter \ADREG
parameter \ALUMODEREG
parameter \AMULTSEL
parameter \AREG
parameter \AUTORESET_PATDET
parameter \AUTORESET_PRIORITY
parameter \A_INPUT
parameter \BCASCREG
parameter \BMULTSEL
parameter \BREG
parameter \B_INPUT
parameter \CARRYINREG
parameter \CARRYINSELREG
parameter \CREG
parameter \DREG
parameter \INMODEREG
parameter \IS_ALUMODE_INVERTED
parameter \IS_CARRYIN_INVERTED
parameter \IS_CLK_INVERTED
parameter \IS_INMODE_INVERTED
parameter \IS_OPMODE_INVERTED
parameter \IS_RSTALLCARRYIN_INVERTED
parameter \IS_RSTALUMODE_INVERTED
parameter \IS_RSTA_INVERTED
parameter \IS_RSTB_INVERTED
parameter \IS_RSTCTRL_INVERTED
parameter \IS_RSTC_INVERTED
parameter \IS_RSTD_INVERTED
parameter \IS_RSTINMODE_INVERTED
parameter \IS_RSTM_INVERTED
parameter \IS_RSTP_INVERTED
parameter \MASK
parameter \MREG
parameter \OPMODEREG
parameter \PATTERN
parameter \PREADDINSEL
parameter \PREG
parameter \RND
parameter \SEL_MASK
parameter \SEL_PATTERN
parameter \USE_MULT
parameter \USE_PATTERN_DETECT
parameter \USE_SIMD
parameter \USE_WIDEXOR
parameter \XORSIMD
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:5653"
wire width 30 input 13 \A
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:5654"
wire width 30 input 14 \ACIN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:5641"
wire width 30 output 1 \ACOUT
attribute \invertible_pin "IS_ALUMODE_INVERTED"
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:5656"
wire width 4 input 15 \ALUMODE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:5657"
wire width 18 input 16 \B
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:5658"
wire width 18 input 17 \BCIN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:5642"
wire width 18 output 2 \BCOUT
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:5659"
wire width 48 input 18 \C
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:5660"
wire input 19 \CARRYCASCIN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:5643"
wire output 3 \CARRYCASCOUT
attribute \invertible_pin "IS_CARRYIN_INVERTED"
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:5662"
wire input 20 \CARRYIN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:5663"
wire width 3 input 21 \CARRYINSEL
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:5644"
wire width 4 output 4 \CARRYOUT
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:5664"
wire input 22 \CEA1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:5665"
wire input 23 \CEA2
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:5666"
wire input 24 \CEAD
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:5667"
wire input 25 \CEALUMODE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:5668"
wire input 26 \CEB1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:5669"
wire input 27 \CEB2
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:5670"
wire input 28 \CEC
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:5671"
wire input 29 \CECARRYIN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:5672"
wire input 30 \CECTRL
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:5673"
wire input 31 \CED
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:5674"
wire input 32 \CEINMODE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:5675"
wire input 33 \CEM
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:5676"
wire input 34 \CEP
attribute \clkbuf_sink 1
attribute \invertible_pin "IS_CLK_INVERTED"
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:5679"
wire input 35 \CLK
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:5680"
wire width 27 input 36 \D
attribute \invertible_pin "IS_INMODE_INVERTED"
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:5682"
wire width 5 input 37 \INMODE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:5683"
wire input 38 \MULTSIGNIN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:5645"
wire output 5 \MULTSIGNOUT
attribute \invertible_pin "IS_OPMODE_INVERTED"
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:5685"
wire width 9 input 39 \OPMODE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:5646"
wire output 6 \OVERFLOW
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:5647"
wire width 48 output 7 \P
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:5648"
wire output 8 \PATTERNBDETECT
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:5649"
wire output 9 \PATTERNDETECT
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:5686"
wire width 48 input 40 \PCIN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:5650"
wire width 48 output 10 \PCOUT
attribute \invertible_pin "IS_RSTA_INVERTED"
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:5688"
wire input 41 \RSTA
attribute \invertible_pin "IS_RSTALLCARRYIN_INVERTED"
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:5690"
wire input 42 \RSTALLCARRYIN
attribute \invertible_pin "IS_RSTALUMODE_INVERTED"
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:5692"
wire input 43 \RSTALUMODE
attribute \invertible_pin "IS_RSTB_INVERTED"
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:5694"
wire input 44 \RSTB
attribute \invertible_pin "IS_RSTC_INVERTED"
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:5696"
wire input 45 \RSTC
attribute \invertible_pin "IS_RSTCTRL_INVERTED"
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:5698"
wire input 46 \RSTCTRL
attribute \invertible_pin "IS_RSTD_INVERTED"
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:5700"
wire input 47 \RSTD
attribute \invertible_pin "IS_RSTINMODE_INVERTED"
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:5702"
wire input 48 \RSTINMODE
attribute \invertible_pin "IS_RSTM_INVERTED"
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:5704"
wire input 49 \RSTM
attribute \invertible_pin "IS_RSTP_INVERTED"
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:5706"
wire input 50 \RSTP
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:5651"
wire output 11 \UNDERFLOW
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:5652"
wire width 8 output 12 \XOROUT
end
attribute \blackbox 1
attribute \cells_not_processed 1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:9664"
module \EFUSE_USR
parameter \SIM_EFUSE_VALUE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:9666"
wire width 32 output 1 \EFUSEUSR
end
attribute \blackbox 1
attribute \cells_not_processed 1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:23975"
module \EMAC
parameter \EMAC0_MODE
parameter \EMAC1_MODE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24055"
wire input 78 \CLIENTEMAC0DCMLOCKED
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24056"
wire input 79 \CLIENTEMAC0PAUSEREQ
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24121"
wire width 16 input 144 \CLIENTEMAC0PAUSEVAL
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24057"
wire input 80 \CLIENTEMAC0RXCLIENTCLKIN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24058"
wire input 81 \CLIENTEMAC0TXCLIENTCLKIN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24122"
wire width 16 input 145 \CLIENTEMAC0TXD
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24059"
wire input 82 \CLIENTEMAC0TXDVLD
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24060"
wire input 83 \CLIENTEMAC0TXDVLDMSW
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24061"
wire input 84 \CLIENTEMAC0TXFIRSTBYTE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24062"
wire input 85 \CLIENTEMAC0TXGMIIMIICLKIN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24139"
wire width 8 input 162 \CLIENTEMAC0TXIFGDELAY
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24063"
wire input 86 \CLIENTEMAC0TXUNDERRUN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24064"
wire input 87 \CLIENTEMAC1DCMLOCKED
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24065"
wire input 88 \CLIENTEMAC1PAUSEREQ
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24123"
wire width 16 input 146 \CLIENTEMAC1PAUSEVAL
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24066"
wire input 89 \CLIENTEMAC1RXCLIENTCLKIN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24067"
wire input 90 \CLIENTEMAC1TXCLIENTCLKIN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24124"
wire width 16 input 147 \CLIENTEMAC1TXD
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24068"
wire input 91 \CLIENTEMAC1TXDVLD
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24069"
wire input 92 \CLIENTEMAC1TXDVLDMSW
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24070"
wire input 93 \CLIENTEMAC1TXFIRSTBYTE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24071"
wire input 94 \CLIENTEMAC1TXGMIIMIICLKIN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24140"
wire width 8 input 163 \CLIENTEMAC1TXIFGDELAY
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24072"
wire input 95 \CLIENTEMAC1TXUNDERRUN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24143"
wire width 2 upto offset 8 input 166 \DCREMACABUS
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24073"
wire input 96 \DCREMACCLK
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24120"
wire width 32 upto input 143 \DCREMACDBUS
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24074"
wire input 97 \DCREMACENABLE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24075"
wire input 98 \DCREMACREAD
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24076"
wire input 99 \DCREMACWRITE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:23978"
wire output 1 \DCRHOSTDONEIR
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:23979"
wire output 2 \EMAC0CLIENTANINTERRUPT
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:23980"
wire output 3 \EMAC0CLIENTRXBADFRAME
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:23981"
wire output 4 \EMAC0CLIENTRXCLIENTCLKOUT
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24048"
wire width 16 output 71 \EMAC0CLIENTRXD
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:23982"
wire output 5 \EMAC0CLIENTRXDVLD
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:23983"
wire output 6 \EMAC0CLIENTRXDVLDMSW
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:23984"
wire output 7 \EMAC0CLIENTRXDVREG6
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:23985"
wire output 8 \EMAC0CLIENTRXFRAMEDROP
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:23986"
wire output 9 \EMAC0CLIENTRXGOODFRAME
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24051"
wire width 7 output 74 \EMAC0CLIENTRXSTATS
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:23987"
wire output 10 \EMAC0CLIENTRXSTATSBYTEVLD
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:23988"
wire output 11 \EMAC0CLIENTRXSTATSVLD
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:23989"
wire output 12 \EMAC0CLIENTTXACK
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:23990"
wire output 13 \EMAC0CLIENTTXCLIENTCLKOUT
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:23991"
wire output 14 \EMAC0CLIENTTXCOLLISION
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:23992"
wire output 15 \EMAC0CLIENTTXGMIIMIICLKOUT
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:23993"
wire output 16 \EMAC0CLIENTTXRETRANSMIT
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:23994"
wire output 17 \EMAC0CLIENTTXSTATS
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:23995"
wire output 18 \EMAC0CLIENTTXSTATSBYTEVLD
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:23996"
wire output 19 \EMAC0CLIENTTXSTATSVLD
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:23997"
wire output 20 \EMAC0PHYENCOMMAALIGN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:23998"
wire output 21 \EMAC0PHYLOOPBACKMSB
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:23999"
wire output 22 \EMAC0PHYMCLKOUT
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24000"
wire output 23 \EMAC0PHYMDOUT
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24001"
wire output 24 \EMAC0PHYMDTRI
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24002"
wire output 25 \EMAC0PHYMGTRXRESET
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24003"
wire output 26 \EMAC0PHYMGTTXRESET
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24004"
wire output 27 \EMAC0PHYPOWERDOWN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24005"
wire output 28 \EMAC0PHYSYNCACQSTATUS
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24006"
wire output 29 \EMAC0PHYTXCHARDISPMODE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24007"
wire output 30 \EMAC0PHYTXCHARDISPVAL
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24008"
wire output 31 \EMAC0PHYTXCHARISK
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24009"
wire output 32 \EMAC0PHYTXCLK
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24053"
wire width 8 output 76 \EMAC0PHYTXD
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24010"
wire output 33 \EMAC0PHYTXEN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24011"
wire output 34 \EMAC0PHYTXER
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24012"
wire output 35 \EMAC1CLIENTANINTERRUPT
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24013"
wire output 36 \EMAC1CLIENTRXBADFRAME
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24014"
wire output 37 \EMAC1CLIENTRXCLIENTCLKOUT
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24049"
wire width 16 output 72 \EMAC1CLIENTRXD
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24015"
wire output 38 \EMAC1CLIENTRXDVLD
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24016"
wire output 39 \EMAC1CLIENTRXDVLDMSW
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24017"
wire output 40 \EMAC1CLIENTRXDVREG6
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24018"
wire output 41 \EMAC1CLIENTRXFRAMEDROP
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24019"
wire output 42 \EMAC1CLIENTRXGOODFRAME
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24052"
wire width 7 output 75 \EMAC1CLIENTRXSTATS
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24020"
wire output 43 \EMAC1CLIENTRXSTATSBYTEVLD
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24021"
wire output 44 \EMAC1CLIENTRXSTATSVLD
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24022"
wire output 45 \EMAC1CLIENTTXACK
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24023"
wire output 46 \EMAC1CLIENTTXCLIENTCLKOUT
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24024"
wire output 47 \EMAC1CLIENTTXCOLLISION
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24025"
wire output 48 \EMAC1CLIENTTXGMIIMIICLKOUT
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24026"
wire output 49 \EMAC1CLIENTTXRETRANSMIT
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24027"
wire output 50 \EMAC1CLIENTTXSTATS
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24028"
wire output 51 \EMAC1CLIENTTXSTATSBYTEVLD
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24029"
wire output 52 \EMAC1CLIENTTXSTATSVLD
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24030"
wire output 53 \EMAC1PHYENCOMMAALIGN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24031"
wire output 54 \EMAC1PHYLOOPBACKMSB
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24032"
wire output 55 \EMAC1PHYMCLKOUT
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24033"
wire output 56 \EMAC1PHYMDOUT
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24034"
wire output 57 \EMAC1PHYMDTRI
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24035"
wire output 58 \EMAC1PHYMGTRXRESET
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24036"
wire output 59 \EMAC1PHYMGTTXRESET
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24037"
wire output 60 \EMAC1PHYPOWERDOWN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24038"
wire output 61 \EMAC1PHYSYNCACQSTATUS
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24039"
wire output 62 \EMAC1PHYTXCHARDISPMODE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24040"
wire output 63 \EMAC1PHYTXCHARDISPVAL
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24041"
wire output 64 \EMAC1PHYTXCHARISK
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24042"
wire output 65 \EMAC1PHYTXCLK
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24054"
wire width 8 output 77 \EMAC1PHYTXD
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24043"
wire output 66 \EMAC1PHYTXEN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24044"
wire output 67 \EMAC1PHYTXER
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24045"
wire output 68 \EMACDCRACK
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24047"
wire width 32 upto output 70 \EMACDCRDBUS
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24144"
wire width 10 input 167 \HOSTADDR
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24077"
wire input 100 \HOSTCLK
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24078"
wire input 101 \HOSTEMAC1SEL
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24046"
wire output 69 \HOSTMIIMRDY
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24079"
wire input 102 \HOSTMIIMSEL
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24125"
wire width 2 input 148 \HOSTOPCODE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24050"
wire width 32 output 73 \HOSTRDDATA
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24080"
wire input 103 \HOSTREQ
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24132"
wire width 32 input 155 \HOSTWRDATA
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24081"
wire input 104 \PHYEMAC0COL
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24082"
wire input 105 \PHYEMAC0CRS
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24083"
wire input 106 \PHYEMAC0GTXCLK
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24084"
wire input 107 \PHYEMAC0MCLKIN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24085"
wire input 108 \PHYEMAC0MDIN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24086"
wire input 109 \PHYEMAC0MIITXCLK
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24135"
wire width 5 input 158 \PHYEMAC0PHYAD
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24087"
wire input 110 \PHYEMAC0RXBUFERR
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24126"
wire width 2 input 149 \PHYEMAC0RXBUFSTATUS
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24088"
wire input 111 \PHYEMAC0RXCHARISCOMMA
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24089"
wire input 112 \PHYEMAC0RXCHARISK
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24090"
wire input 113 \PHYEMAC0RXCHECKINGCRC
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24091"
wire input 114 \PHYEMAC0RXCLK
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24130"
wire width 3 input 153 \PHYEMAC0RXCLKCORCNT
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24092"
wire input 115 \PHYEMAC0RXCOMMADET
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24141"
wire width 8 input 164 \PHYEMAC0RXD
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24093"
wire input 116 \PHYEMAC0RXDISPERR
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24094"
wire input 117 \PHYEMAC0RXDV
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24095"
wire input 118 \PHYEMAC0RXER
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24127"
wire width 2 input 150 \PHYEMAC0RXLOSSOFSYNC
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24096"
wire input 119 \PHYEMAC0RXNOTINTABLE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24097"
wire input 120 \PHYEMAC0RXRUNDISP
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24098"
wire input 121 \PHYEMAC0SIGNALDET
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24099"
wire input 122 \PHYEMAC0TXBUFERR
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24100"
wire input 123 \PHYEMAC1COL
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24101"
wire input 124 \PHYEMAC1CRS
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24102"
wire input 125 \PHYEMAC1GTXCLK
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24103"
wire input 126 \PHYEMAC1MCLKIN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24104"
wire input 127 \PHYEMAC1MDIN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24105"
wire input 128 \PHYEMAC1MIITXCLK
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24136"
wire width 5 input 159 \PHYEMAC1PHYAD
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24106"
wire input 129 \PHYEMAC1RXBUFERR
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24128"
wire width 2 input 151 \PHYEMAC1RXBUFSTATUS
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24107"
wire input 130 \PHYEMAC1RXCHARISCOMMA
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24108"
wire input 131 \PHYEMAC1RXCHARISK
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24109"
wire input 132 \PHYEMAC1RXCHECKINGCRC
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24110"
wire input 133 \PHYEMAC1RXCLK
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24131"
wire width 3 input 154 \PHYEMAC1RXCLKCORCNT
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24111"
wire input 134 \PHYEMAC1RXCOMMADET
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24142"
wire width 8 input 165 \PHYEMAC1RXD
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24112"
wire input 135 \PHYEMAC1RXDISPERR
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24113"
wire input 136 \PHYEMAC1RXDV
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24114"
wire input 137 \PHYEMAC1RXER
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24129"
wire width 2 input 152 \PHYEMAC1RXLOSSOFSYNC
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24115"
wire input 138 \PHYEMAC1RXNOTINTABLE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24116"
wire input 139 \PHYEMAC1RXRUNDISP
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24117"
wire input 140 \PHYEMAC1SIGNALDET
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24118"
wire input 141 \PHYEMAC1TXBUFERR
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24119"
wire input 142 \RESET
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24137"
wire width 80 input 160 \TIEEMAC0CONFIGVEC
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24133"
wire width 48 input 156 \TIEEMAC0UNICASTADDR
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24138"
wire width 80 input 161 \TIEEMAC1CONFIGVEC
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:24134"
wire width 48 input 157 \TIEEMAC1UNICASTADDR
end
attribute \abc9_flop 1
attribute \abc9_box_id 1104
attribute \whitebox 1
attribute \cells_not_processed 1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_sim.v:438"
module \FDCE
parameter \INIT
parameter \IS_CLR_INVERTED
parameter \IS_C_INVERTED
parameter \IS_D_INVERTED
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_sim.v:456"
wire $0\Q[0:0]
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_sim.v:454"
wire $1\Q[0:0]
wire $procmux$77_Y
wire $procmux$78_CMP
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_sim.v:456"
wire $xor$/usr/local/bin/../share/yosys/xilinx/cells_sim.v:456$56_Y
attribute \clkbuf_sink 1
attribute \invertible_pin "IS_C_INVERTED"
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_sim.v:443"
wire input 2 \C
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_sim.v:444"
wire input 3 \CE
attribute \invertible_pin "IS_CLR_INVERTED"
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_sim.v:446"
wire input 4 \CLR
attribute \invertible_pin "IS_D_INVERTED"
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_sim.v:448"
wire input 5 \D
attribute \abc9_arrival 303
attribute \init 1'0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_sim.v:440"
wire output 1 \Q
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_sim.v:456"
cell $adff $procdff$102
parameter \ARST_POLARITY 1'1
parameter \ARST_VALUE 1'0
parameter \CLK_POLARITY 1'1
parameter \WIDTH 1
connect \ARST \CLR
connect \CLK \C
connect \D $procmux$77_Y
connect \Q \Q
end
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_sim.v:456"
cell $mux $procmux$77
parameter \WIDTH 1
connect \A \Q
connect \B $xor$/usr/local/bin/../share/yosys/xilinx/cells_sim.v:456$56_Y
connect \S $procmux$78_CMP
connect \Y $procmux$77_Y
end
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_sim.v:456"
cell $xor $xor$/usr/local/bin/../share/yosys/xilinx/cells_sim.v:456$56
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \D
connect \B 1'0
connect \Y $xor$/usr/local/bin/../share/yosys/xilinx/cells_sim.v:456$56_Y
end
connect $1\Q[0:0] 1'0
connect $procmux$78_CMP \CE
connect $0\Q[0:0] $procmux$77_Y
end
attribute \abc9_flop 1
attribute \abc9_box_id 1105
attribute \whitebox 1
attribute \cells_not_processed 1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_sim.v:464"
module \FDCE_1
parameter \INIT
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_sim.v:473"
wire $0\Q[0:0]
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_sim.v:472"
wire $1\Q[0:0]
wire $procmux$75_Y
wire $procmux$76_CMP
attribute \clkbuf_sink 1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_sim.v:468"
wire input 2 \C
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_sim.v:469"
wire input 3 \CE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_sim.v:469"
wire input 5 \CLR
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_sim.v:469"
wire input 4 \D
attribute \abc9_arrival 303
attribute \init 1'0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_sim.v:466"
wire output 1 \Q
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_sim.v:473"
cell $adff $procdff$101
parameter \ARST_POLARITY 1'1
parameter \ARST_VALUE 1'0
parameter \CLK_POLARITY 1'0
parameter \WIDTH 1
connect \ARST \CLR
connect \CLK \C
connect \D $procmux$75_Y
connect \Q \Q
end
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_sim.v:473"
cell $mux $procmux$75
parameter \WIDTH 1
connect \A \Q
connect \B \D
connect \S $procmux$76_CMP
connect \Y $procmux$75_Y
end
connect $1\Q[0:0] 1'0
connect $procmux$76_CMP \CE
connect $0\Q[0:0] $procmux$75_Y
end
attribute \blackbox 1
attribute \cells_not_processed 1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_sim.v:515"
module \FDCPE
parameter \INIT
parameter \IS_CLR_INVERTED
parameter \IS_C_INVERTED
parameter \IS_PRE_INVERTED
attribute \clkbuf_sink 1
attribute \invertible_pin "IS_C_INVERTED"
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_sim.v:519"
wire input 2 \C
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_sim.v:520"
wire input 3 \CE
attribute \invertible_pin "IS_CLR_INVERTED"
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_sim.v:522"
wire input 4 \CLR
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_sim.v:523"
wire input 5 \D
attribute \invertible_pin "IS_PRE_INVERTED"
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_sim.v:525"
wire input 6 \PRE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_sim.v:516"
wire output 1 \Q
end
attribute \abc9_flop 1
attribute \abc9_box_id 1106
attribute \whitebox 1
attribute \cells_not_processed 1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_sim.v:477"
module \FDPE
parameter \INIT
parameter \IS_C_INVERTED
parameter \IS_D_INVERTED
parameter \IS_PRE_INVERTED
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_sim.v:495"
wire $0\Q[0:0]
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_sim.v:493"
wire $1\Q[0:0]
wire $procmux$73_Y
wire $procmux$74_CMP
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_sim.v:495"
wire $xor$/usr/local/bin/../share/yosys/xilinx/cells_sim.v:495$61_Y
attribute \clkbuf_sink 1
attribute \invertible_pin "IS_C_INVERTED"
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_sim.v:482"
wire input 2 \C
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_sim.v:483"
wire input 3 \CE
attribute \invertible_pin "IS_D_INVERTED"
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_sim.v:485"
wire input 4 \D
attribute \invertible_pin "IS_PRE_INVERTED"
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_sim.v:487"
wire input 5 \PRE
attribute \abc9_arrival 303
attribute \init 1'1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_sim.v:479"
wire output 1 \Q
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_sim.v:495"
cell $adff $procdff$100
parameter \ARST_POLARITY 1'1
parameter \ARST_VALUE 1'1
parameter \CLK_POLARITY 1'1
parameter \WIDTH 1
connect \ARST \PRE
connect \CLK \C
connect \D $procmux$73_Y
connect \Q \Q
end
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_sim.v:495"
cell $mux $procmux$73
parameter \WIDTH 1
connect \A \Q
connect \B $xor$/usr/local/bin/../share/yosys/xilinx/cells_sim.v:495$61_Y
connect \S $procmux$74_CMP
connect \Y $procmux$73_Y
end
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_sim.v:495"
cell $xor $xor$/usr/local/bin/../share/yosys/xilinx/cells_sim.v:495$61
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \D
connect \B 1'0
connect \Y $xor$/usr/local/bin/../share/yosys/xilinx/cells_sim.v:495$61_Y
end
connect $1\Q[0:0] 1'1
connect $procmux$74_CMP \CE
connect $0\Q[0:0] $procmux$73_Y
end
attribute \abc9_flop 1
attribute \abc9_box_id 1107
attribute \whitebox 1
attribute \cells_not_processed 1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_sim.v:503"
module \FDPE_1
parameter \INIT
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_sim.v:512"
wire $0\Q[0:0]
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_sim.v:511"
wire $1\Q[0:0]
wire $procmux$71_Y
wire $procmux$72_CMP
attribute \clkbuf_sink 1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_sim.v:507"
wire input 2 \C
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_sim.v:508"
wire input 3 \CE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_sim.v:508"
wire input 4 \D
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_sim.v:508"
wire input 5 \PRE
attribute \abc9_arrival 303
attribute \init 1'1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_sim.v:505"
wire output 1 \Q
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_sim.v:512"
cell $adff $procdff$99
parameter \ARST_POLARITY 1'1
parameter \ARST_VALUE 1'1
parameter \CLK_POLARITY 1'0
parameter \WIDTH 1
connect \ARST \PRE
connect \CLK \C
connect \D $procmux$71_Y
connect \Q \Q
end
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_sim.v:512"
cell $mux $procmux$71
parameter \WIDTH 1
connect \A \Q
connect \B \D
connect \S $procmux$72_CMP
connect \Y $procmux$71_Y
end
connect $1\Q[0:0] 1'1
connect $procmux$72_CMP \CE
connect $0\Q[0:0] $procmux$71_Y
end
attribute \abc9_box_id 1100
attribute \whitebox 1
attribute \abc9_flop 1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_sim.v:329"
module \FDRE
parameter \INIT
parameter \IS_C_INVERTED
parameter \IS_D_INVERTED
parameter \IS_R_INVERTED
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_sim.v:347"
wire $0\Q[0:0]
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_sim.v:345"
wire $1\Q[0:0]
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_sim.v:347"
wire $eq$/usr/local/bin/../share/yosys/xilinx/cells_sim.v:347$44_Y
wire $procmux$94_Y
wire $procmux$95_CMP
wire $procmux$97_Y
wire $procmux$98_CMP
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_sim.v:347"
wire $xor$/usr/local/bin/../share/yosys/xilinx/cells_sim.v:347$45_Y
attribute \clkbuf_sink 1
attribute \invertible_pin "IS_C_INVERTED"
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_sim.v:334"
wire input 2 \C
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_sim.v:335"
wire input 3 \CE
attribute \invertible_pin "IS_D_INVERTED"
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_sim.v:337"
wire input 4 \D
attribute \abc9_arrival 303
attribute \init 1'0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_sim.v:331"
wire output 1 \Q
attribute \invertible_pin "IS_R_INVERTED"
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_sim.v:339"
wire input 5 \R
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_sim.v:347"
cell $eq $eq$/usr/local/bin/../share/yosys/xilinx/cells_sim.v:347$44
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \R
connect \B 1'1
connect \Y $eq$/usr/local/bin/../share/yosys/xilinx/cells_sim.v:347$44_Y
end
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_sim.v:347"
cell $dff $procdff$106
parameter \CLK_POLARITY 1'1
parameter \WIDTH 1
connect \CLK \C
connect \D $procmux$97_Y
connect \Q \Q
end
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_sim.v:347"
cell $mux $procmux$94
parameter \WIDTH 1
connect \A \Q
connect \B $xor$/usr/local/bin/../share/yosys/xilinx/cells_sim.v:347$45_Y
connect \S $procmux$95_CMP
connect \Y $procmux$94_Y
end
attribute \full_case 1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_sim.v:347"
cell $mux $procmux$97
parameter \WIDTH 1
connect \A $procmux$94_Y
connect \B 1'0
connect \S $procmux$98_CMP
connect \Y $procmux$97_Y
end
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_sim.v:347"
cell $xor $xor$/usr/local/bin/../share/yosys/xilinx/cells_sim.v:347$45
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \D
connect \B 1'0
connect \Y $xor$/usr/local/bin/../share/yosys/xilinx/cells_sim.v:347$45_Y
end
connect $1\Q[0:0] 1'0
connect $procmux$95_CMP \CE
connect $procmux$98_CMP $eq$/usr/local/bin/../share/yosys/xilinx/cells_sim.v:347$44_Y
connect $0\Q[0:0] $procmux$97_Y
end
attribute \abc9_flop 1
attribute \abc9_box_id 1101
attribute \whitebox 1
attribute \cells_not_processed 1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_sim.v:353"
module \FDRE_1
parameter \INIT
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_sim.v:362"
wire $0\Q[0:0]
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_sim.v:361"
wire $1\Q[0:0]
wire $procmux$89_Y
wire $procmux$90_CMP
wire $procmux$92_Y
wire $procmux$93_CMP
attribute \clkbuf_sink 1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_sim.v:357"
wire input 2 \C
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_sim.v:358"
wire input 3 \CE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_sim.v:358"
wire input 4 \D
attribute \abc9_arrival 303
attribute \init 1'0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_sim.v:355"
wire output 1 \Q
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_sim.v:358"
wire input 5 \R
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_sim.v:362"
cell $dff $procdff$105
parameter \CLK_POLARITY 1'0
parameter \WIDTH 1
connect \CLK \C
connect \D $procmux$92_Y
connect \Q \Q
end
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_sim.v:362"
cell $mux $procmux$89
parameter \WIDTH 1
connect \A \Q
connect \B \D
connect \S $procmux$90_CMP
connect \Y $procmux$89_Y
end
attribute \full_case 1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_sim.v:362"
cell $mux $procmux$92
parameter \WIDTH 1
connect \A $procmux$89_Y
connect \B 1'0
connect \S $procmux$93_CMP
connect \Y $procmux$92_Y
end
connect $1\Q[0:0] 1'0
connect $procmux$90_CMP \CE
connect $procmux$93_CMP \R
connect $0\Q[0:0] $procmux$92_Y
end
attribute \blackbox 1
attribute \cells_not_processed 1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_sim.v:402"
module \FDRSE
parameter \INIT
parameter \IS_CE_INVERTED
parameter \IS_C_INVERTED
parameter \IS_D_INVERTED
parameter \IS_R_INVERTED
parameter \IS_S_INVERTED
attribute \clkbuf_sink 1
attribute \invertible_pin "IS_C_INVERTED"
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_sim.v:406"
wire input 2 \C
attribute \invertible_pin "IS_CE_INVERTED"
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_sim.v:408"
wire input 3 \CE
attribute \invertible_pin "IS_D_INVERTED"
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_sim.v:410"
wire input 4 \D
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_sim.v:403"
wire output 1 \Q
attribute \invertible_pin "IS_R_INVERTED"
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_sim.v:412"
wire input 5 \R
attribute \invertible_pin "IS_S_INVERTED"
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_sim.v:414"
wire input 6 \S
end
attribute \abc9_flop 1
attribute \abc9_box_id 1102
attribute \whitebox 1
attribute \cells_not_processed 1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_sim.v:366"
module \FDSE
parameter \INIT
parameter \IS_C_INVERTED
parameter \IS_D_INVERTED
parameter \IS_S_INVERTED
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_sim.v:384"
wire $0\Q[0:0]
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_sim.v:382"
wire $1\Q[0:0]
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_sim.v:384"
wire $eq$/usr/local/bin/../share/yosys/xilinx/cells_sim.v:384$50_Y
wire $procmux$84_Y
wire $procmux$85_CMP
wire $procmux$87_Y
wire $procmux$88_CMP
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_sim.v:384"
wire $xor$/usr/local/bin/../share/yosys/xilinx/cells_sim.v:384$51_Y
attribute \clkbuf_sink 1
attribute \invertible_pin "IS_C_INVERTED"
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_sim.v:371"
wire input 2 \C
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_sim.v:372"
wire input 3 \CE
attribute \invertible_pin "IS_D_INVERTED"
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_sim.v:374"
wire input 4 \D
attribute \abc9_arrival 303
attribute \init 1'1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_sim.v:368"
wire output 1 \Q
attribute \invertible_pin "IS_S_INVERTED"
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_sim.v:376"
wire input 5 \S
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_sim.v:384"
cell $eq $eq$/usr/local/bin/../share/yosys/xilinx/cells_sim.v:384$50
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \S
connect \B 1'1
connect \Y $eq$/usr/local/bin/../share/yosys/xilinx/cells_sim.v:384$50_Y
end
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_sim.v:384"
cell $dff $procdff$104
parameter \CLK_POLARITY 1'1
parameter \WIDTH 1
connect \CLK \C
connect \D $procmux$87_Y
connect \Q \Q
end
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_sim.v:384"
cell $mux $procmux$84
parameter \WIDTH 1
connect \A \Q
connect \B $xor$/usr/local/bin/../share/yosys/xilinx/cells_sim.v:384$51_Y
connect \S $procmux$85_CMP
connect \Y $procmux$84_Y
end
attribute \full_case 1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_sim.v:384"
cell $mux $procmux$87
parameter \WIDTH 1
connect \A $procmux$84_Y
connect \B 1'1
connect \S $procmux$88_CMP
connect \Y $procmux$87_Y
end
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_sim.v:384"
cell $xor $xor$/usr/local/bin/../share/yosys/xilinx/cells_sim.v:384$51
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \D
connect \B 1'0
connect \Y $xor$/usr/local/bin/../share/yosys/xilinx/cells_sim.v:384$51_Y
end
connect $1\Q[0:0] 1'1
connect $procmux$85_CMP \CE
connect $procmux$88_CMP $eq$/usr/local/bin/../share/yosys/xilinx/cells_sim.v:384$50_Y
connect $0\Q[0:0] $procmux$87_Y
end
attribute \abc9_flop 1
attribute \abc9_box_id 1103
attribute \whitebox 1
attribute \cells_not_processed 1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_sim.v:390"
module \FDSE_1
parameter \INIT
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_sim.v:399"
wire $0\Q[0:0]
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_sim.v:398"
wire $1\Q[0:0]
wire $procmux$79_Y
wire $procmux$80_CMP
wire $procmux$82_Y
wire $procmux$83_CMP
attribute \clkbuf_sink 1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_sim.v:394"
wire input 2 \C
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_sim.v:395"
wire input 3 \CE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_sim.v:395"
wire input 4 \D
attribute \abc9_arrival 303
attribute \init 1'1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_sim.v:392"
wire output 1 \Q
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_sim.v:395"
wire input 5 \S
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_sim.v:399"
cell $dff $procdff$103
parameter \CLK_POLARITY 1'0
parameter \WIDTH 1
connect \CLK \C
connect \D $procmux$82_Y
connect \Q \Q
end
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_sim.v:399"
cell $mux $procmux$79
parameter \WIDTH 1
connect \A \Q
connect \B \D
connect \S $procmux$80_CMP
connect \Y $procmux$79_Y
end
attribute \full_case 1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_sim.v:399"
cell $mux $procmux$82
parameter \WIDTH 1
connect \A $procmux$79_Y
connect \B 1'1
connect \S $procmux$83_CMP
connect \Y $procmux$82_Y
end
connect $1\Q[0:0] 1'1
connect $procmux$80_CMP \CE
connect $procmux$83_CMP \S
connect $0\Q[0:0] $procmux$82_Y
end
attribute \blackbox 1
attribute \cells_not_processed 1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:3437"
module \FIFO16
parameter \ALMOST_EMPTY_OFFSET
parameter \ALMOST_FULL_OFFSET
parameter \DATA_WIDTH
parameter \FIRST_WORD_FALL_THROUGH
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:3442"
wire output 1 \ALMOSTEMPTY
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:3443"
wire output 2 \ALMOSTFULL
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:3452"
wire width 32 input 11 \DI
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:3453"
wire width 4 input 12 \DIP
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:3444"
wire width 32 output 3 \DO
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:3445"
wire width 4 output 4 \DOP
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:3446"
wire output 5 \EMPTY
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:3447"
wire output 6 \FULL
attribute \clkbuf_sink 1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:3455"
wire input 13 \RDCLK
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:3448"
wire width 12 output 7 \RDCOUNT
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:3456"
wire input 14 \RDEN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:3449"
wire output 8 \RDERR
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:3457"
wire input 15 \RST
attribute \clkbuf_sink 1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:3459"
wire input 16 \WRCLK
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:3450"
wire width 12 output 9 \WRCOUNT
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:3460"
wire input 17 \WREN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:3451"
wire output 10 \WRERR
end
attribute \blackbox 1
attribute \cells_not_processed 1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:3599"
module \FIFO18
parameter \ALMOST_EMPTY_OFFSET
parameter \ALMOST_FULL_OFFSET
parameter \DATA_WIDTH
parameter \DO_REG
parameter \EN_SYN
parameter \FIRST_WORD_FALL_THROUGH
parameter \SIM_MODE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:3607"
wire output 1 \ALMOSTEMPTY
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:3608"
wire output 2 \ALMOSTFULL
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:3617"
wire width 16 input 11 \DI
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:3618"
wire width 2 input 12 \DIP
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:3609"
wire width 16 output 3 \DO
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:3610"
wire width 2 output 4 \DOP
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:3611"
wire output 5 \EMPTY
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:3612"
wire output 6 \FULL
attribute \clkbuf_sink 1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:3620"
wire input 13 \RDCLK
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:3613"
wire width 12 output 7 \RDCOUNT
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:3621"
wire input 14 \RDEN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:3614"
wire output 8 \RDERR
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:3622"
wire input 15 \RST
attribute \clkbuf_sink 1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:3624"
wire input 16 \WRCLK
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:3615"
wire width 12 output 9 \WRCOUNT
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:3625"
wire input 17 \WREN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:3616"
wire output 10 \WRERR
end
attribute \blackbox 1
attribute \cells_not_processed 1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:4294"
module \FIFO18E1
parameter \ALMOST_EMPTY_OFFSET
parameter \ALMOST_FULL_OFFSET
parameter \DATA_WIDTH
parameter \DO_REG
parameter \EN_SYN
parameter \FIFO_MODE
parameter \FIRST_WORD_FALL_THROUGH
parameter \INIT
parameter \IS_RDCLK_INVERTED
parameter \IS_RDEN_INVERTED
parameter \IS_RSTREG_INVERTED
parameter \IS_RST_INVERTED
parameter \IS_WRCLK_INVERTED
parameter \IS_WREN_INVERTED
parameter \SIM_DEVICE
parameter \SRVAL
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:4311"
wire output 1 \ALMOSTEMPTY
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:4312"
wire output 2 \ALMOSTFULL
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:4321"
wire width 32 input 11 \DI
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:4322"
wire width 4 input 12 \DIP
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:4313"
wire width 32 output 3 \DO
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:4314"
wire width 4 output 4 \DOP
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:4315"
wire output 5 \EMPTY
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:4316"
wire output 6 \FULL
attribute \clkbuf_sink 1
attribute \invertible_pin "IS_RDCLK_INVERTED"
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:4325"
wire input 13 \RDCLK
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:4317"
wire width 12 output 7 \RDCOUNT
attribute \invertible_pin "IS_RDEN_INVERTED"
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:4327"
wire input 14 \RDEN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:4318"
wire output 8 \RDERR
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:4328"
wire input 15 \REGCE
attribute \invertible_pin "IS_RST_INVERTED"
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:4330"
wire input 16 \RST
attribute \invertible_pin "IS_RSTREG_INVERTED"
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:4332"
wire input 17 \RSTREG
attribute \clkbuf_sink 1
attribute \invertible_pin "IS_WRCLK_INVERTED"
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:4335"
wire input 18 \WRCLK
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:4319"
wire width 12 output 9 \WRCOUNT
attribute \invertible_pin "IS_WREN_INVERTED"
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:4337"
wire input 19 \WREN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:4320"
wire output 10 \WRERR
end
attribute \blackbox 1
attribute \cells_not_processed 1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:4755"
module \FIFO18E2
parameter \CASCADE_ORDER
parameter \CLOCK_DOMAINS
parameter \FIRST_WORD_FALL_THROUGH
parameter \INIT
parameter \IS_RDCLK_INVERTED
parameter \IS_RDEN_INVERTED
parameter \IS_RSTREG_INVERTED
parameter \IS_RST_INVERTED
parameter \IS_WRCLK_INVERTED
parameter \IS_WREN_INVERTED
parameter \PROG_EMPTY_THRESH
parameter \PROG_FULL_THRESH
parameter \RDCOUNT_TYPE
parameter \READ_WIDTH
parameter \REGISTER_MODE
parameter \RSTREG_PRIORITY
parameter \SLEEP_ASYNC
parameter \SRVAL
parameter \WRCOUNT_TYPE
parameter \WRITE_WIDTH
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:4792"
wire width 32 input 17 \CASDIN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:4793"
wire width 4 input 18 \CASDINP
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:4794"
wire input 19 \CASDOMUX
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:4795"
wire input 20 \CASDOMUXEN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:4776"
wire width 32 output 1 \CASDOUT
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:4777"
wire width 4 output 2 \CASDOUTP
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:4778"
wire output 3 \CASNXTEMPTY
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:4796"
wire input 21 \CASNXTRDEN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:4797"
wire input 22 \CASOREGIMUX
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:4798"
wire input 23 \CASOREGIMUXEN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:4799"
wire input 24 \CASPRVEMPTY
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:4779"
wire output 4 \CASPRVRDEN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:4800"
wire width 32 input 25 \DIN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:4801"
wire width 4 input 26 \DINP
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:4780"
wire width 32 output 5 \DOUT
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:4781"
wire width 4 output 6 \DOUTP
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:4782"
wire output 7 \EMPTY
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:4783"
wire output 8 \FULL
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:4784"
wire output 9 \PROGEMPTY
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:4785"
wire output 10 \PROGFULL
attribute \clkbuf_sink 1
attribute \invertible_pin "IS_RDCLK_INVERTED"
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:4804"
wire input 27 \RDCLK
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:4786"
wire width 13 output 11 \RDCOUNT
attribute \invertible_pin "IS_RDEN_INVERTED"
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:4806"
wire input 28 \RDEN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:4787"
wire output 12 \RDERR
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:4788"
wire output 13 \RDRSTBUSY
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:4807"
wire input 29 \REGCE
attribute \invertible_pin "IS_RST_INVERTED"
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:4809"
wire input 30 \RST
attribute \invertible_pin "IS_RSTREG_INVERTED"
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:4811"
wire input 31 \RSTREG
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:4812"
wire input 32 \SLEEP
attribute \clkbuf_sink 1
attribute \invertible_pin "IS_WRCLK_INVERTED"
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:4815"
wire input 33 \WRCLK
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:4789"
wire width 13 output 14 \WRCOUNT
attribute \invertible_pin "IS_WREN_INVERTED"
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:4817"
wire input 34 \WREN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:4790"
wire output 15 \WRERR
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:4791"
wire output 16 \WRRSTBUSY
end
attribute \blackbox 1
attribute \cells_not_processed 1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:3628"
module \FIFO18_36
parameter \ALMOST_EMPTY_OFFSET
parameter \ALMOST_FULL_OFFSET
parameter \DO_REG
parameter \EN_SYN
parameter \FIRST_WORD_FALL_THROUGH
parameter \SIM_MODE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:3635"
wire output 1 \ALMOSTEMPTY
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:3636"
wire output 2 \ALMOSTFULL
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:3645"
wire width 32 input 11 \DI
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:3646"
wire width 4 input 12 \DIP
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:3637"
wire width 32 output 3 \DO
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:3638"
wire width 4 output 4 \DOP
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:3639"
wire output 5 \EMPTY
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:3640"
wire output 6 \FULL
attribute \clkbuf_sink 1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:3648"
wire input 13 \RDCLK
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:3641"
wire width 9 output 7 \RDCOUNT
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:3649"
wire input 14 \RDEN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:3642"
wire output 8 \RDERR
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:3650"
wire input 15 \RST
attribute \clkbuf_sink 1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:3652"
wire input 16 \WRCLK
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:3643"
wire width 9 output 9 \WRCOUNT
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:3653"
wire input 17 \WREN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:3644"
wire output 10 \WRERR
end
attribute \blackbox 1
attribute \cells_not_processed 1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:3656"
module \FIFO36
parameter \ALMOST_EMPTY_OFFSET
parameter \ALMOST_FULL_OFFSET
parameter \DATA_WIDTH
parameter \DO_REG
parameter \EN_SYN
parameter \FIRST_WORD_FALL_THROUGH
parameter \SIM_MODE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:3664"
wire output 1 \ALMOSTEMPTY
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:3665"
wire output 2 \ALMOSTFULL
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:3674"
wire width 32 input 11 \DI
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:3675"
wire width 4 input 12 \DIP
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:3666"
wire width 32 output 3 \DO
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:3667"
wire width 4 output 4 \DOP
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:3668"
wire output 5 \EMPTY
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:3669"
wire output 6 \FULL
attribute \clkbuf_sink 1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:3677"
wire input 13 \RDCLK
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:3670"
wire width 13 output 7 \RDCOUNT
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:3678"
wire input 14 \RDEN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:3671"
wire output 8 \RDERR
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:3679"
wire input 15 \RST
attribute \clkbuf_sink 1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:3681"
wire input 16 \WRCLK
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:3672"
wire width 13 output 9 \WRCOUNT
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:3682"
wire input 17 \WREN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:3673"
wire output 10 \WRERR
end
attribute \blackbox 1
attribute \cells_not_processed 1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:4340"
module \FIFO36E1
parameter \ALMOST_EMPTY_OFFSET
parameter \ALMOST_FULL_OFFSET
parameter \DATA_WIDTH
parameter \DO_REG
parameter \EN_ECC_READ
parameter \EN_ECC_WRITE
parameter \EN_SYN
parameter \FIFO_MODE
parameter \FIRST_WORD_FALL_THROUGH
parameter \INIT
parameter \IS_RDCLK_INVERTED
parameter \IS_RDEN_INVERTED
parameter \IS_RSTREG_INVERTED
parameter \IS_RST_INVERTED
parameter \IS_WRCLK_INVERTED
parameter \IS_WREN_INVERTED
parameter \SIM_DEVICE
parameter \SRVAL
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:4359"
wire output 1 \ALMOSTEMPTY
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:4360"
wire output 2 \ALMOSTFULL
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:4361"
wire output 3 \DBITERR
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:4372"
wire width 64 input 14 \DI
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:4373"
wire width 8 input 15 \DIP
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:4362"
wire width 64 output 4 \DO
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:4363"
wire width 8 output 5 \DOP
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:4364"
wire width 8 output 6 \ECCPARITY
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:4365"
wire output 7 \EMPTY
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:4366"
wire output 8 \FULL
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:4374"
wire input 16 \INJECTDBITERR
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:4375"
wire input 17 \INJECTSBITERR
attribute \clkbuf_sink 1
attribute \invertible_pin "IS_RDCLK_INVERTED"
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:4378"
wire input 18 \RDCLK
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:4367"
wire width 13 output 9 \RDCOUNT
attribute \invertible_pin "IS_RDEN_INVERTED"
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:4380"
wire input 19 \RDEN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:4368"
wire output 10 \RDERR
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:4381"
wire input 20 \REGCE
attribute \invertible_pin "IS_RST_INVERTED"
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:4383"
wire input 21 \RST
attribute \invertible_pin "IS_RSTREG_INVERTED"
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:4385"
wire input 22 \RSTREG
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:4369"
wire output 11 \SBITERR
attribute \clkbuf_sink 1
attribute \invertible_pin "IS_WRCLK_INVERTED"
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:4388"
wire input 23 \WRCLK
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:4370"
wire width 13 output 12 \WRCOUNT
attribute \invertible_pin "IS_WREN_INVERTED"
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:4390"
wire input 24 \WREN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:4371"
wire output 13 \WRERR
end
attribute \blackbox 1
attribute \cells_not_processed 1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:4820"
module \FIFO36E2
parameter \CASCADE_ORDER
parameter \CLOCK_DOMAINS
parameter \EN_ECC_PIPE
parameter \EN_ECC_READ
parameter \EN_ECC_WRITE
parameter \FIRST_WORD_FALL_THROUGH
parameter \INIT
parameter \IS_RDCLK_INVERTED
parameter \IS_RDEN_INVERTED
parameter \IS_RSTREG_INVERTED
parameter \IS_RST_INVERTED
parameter \IS_WRCLK_INVERTED
parameter \IS_WREN_INVERTED
parameter \PROG_EMPTY_THRESH
parameter \PROG_FULL_THRESH
parameter \RDCOUNT_TYPE
parameter \READ_WIDTH
parameter \REGISTER_MODE
parameter \RSTREG_PRIORITY
parameter \SLEEP_ASYNC
parameter \SRVAL
parameter \WRCOUNT_TYPE
parameter \WRITE_WIDTH
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:4863"
wire width 64 input 20 \CASDIN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:4864"
wire width 8 input 21 \CASDINP
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:4865"
wire input 22 \CASDOMUX
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:4866"
wire input 23 \CASDOMUXEN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:4844"
wire width 64 output 1 \CASDOUT
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:4845"
wire width 8 output 2 \CASDOUTP
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:4846"
wire output 3 \CASNXTEMPTY
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:4867"
wire input 24 \CASNXTRDEN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:4868"
wire input 25 \CASOREGIMUX
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:4869"
wire input 26 \CASOREGIMUXEN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:4870"
wire input 27 \CASPRVEMPTY
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:4847"
wire output 4 \CASPRVRDEN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:4848"
wire output 5 \DBITERR
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:4871"
wire width 64 input 28 \DIN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:4872"
wire width 8 input 29 \DINP
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:4849"
wire width 64 output 6 \DOUT
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:4850"
wire width 8 output 7 \DOUTP
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:4851"
wire width 8 output 8 \ECCPARITY
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:4852"
wire output 9 \EMPTY
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:4853"
wire output 10 \FULL
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:4873"
wire input 30 \INJECTDBITERR
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:4874"
wire input 31 \INJECTSBITERR
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:4854"
wire output 11 \PROGEMPTY
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:4855"
wire output 12 \PROGFULL
attribute \clkbuf_sink 1
attribute \invertible_pin "IS_RDCLK_INVERTED"
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:4877"
wire input 32 \RDCLK
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:4856"
wire width 14 output 13 \RDCOUNT
attribute \invertible_pin "IS_RDEN_INVERTED"
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:4879"
wire input 33 \RDEN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:4857"
wire output 14 \RDERR
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:4858"
wire output 15 \RDRSTBUSY
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:4880"
wire input 34 \REGCE
attribute \invertible_pin "IS_RST_INVERTED"
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:4882"
wire input 35 \RST
attribute \invertible_pin "IS_RSTREG_INVERTED"
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:4884"
wire input 36 \RSTREG
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:4859"
wire output 16 \SBITERR
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:4885"
wire input 37 \SLEEP
attribute \clkbuf_sink 1
attribute \invertible_pin "IS_WRCLK_INVERTED"
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:4888"
wire input 38 \WRCLK
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:4860"
wire width 14 output 17 \WRCOUNT
attribute \invertible_pin "IS_WREN_INVERTED"
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:4890"
wire input 39 \WREN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:4861"
wire output 18 \WRERR
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:4862"
wire output 19 \WRRSTBUSY
end
attribute \blackbox 1
attribute \cells_not_processed 1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:3685"
module \FIFO36_72
parameter \ALMOST_EMPTY_OFFSET
parameter \ALMOST_FULL_OFFSET
parameter \DO_REG
parameter \EN_ECC_READ
parameter \EN_ECC_WRITE
parameter \EN_SYN
parameter \FIRST_WORD_FALL_THROUGH
parameter \SIM_MODE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:3694"
wire output 1 \ALMOSTEMPTY
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:3695"
wire output 2 \ALMOSTFULL
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:3696"
wire output 3 \DBITERR
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:3707"
wire width 64 input 14 \DI
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:3708"
wire width 8 input 15 \DIP
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:3697"
wire width 64 output 4 \DO
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:3698"
wire width 8 output 5 \DOP
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:3699"
wire width 8 output 6 \ECCPARITY
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:3700"
wire output 7 \EMPTY
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:3701"
wire output 8 \FULL
attribute \clkbuf_sink 1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:3710"
wire input 16 \RDCLK
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:3702"
wire width 9 output 9 \RDCOUNT
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:3711"
wire input 17 \RDEN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:3703"
wire output 10 \RDERR
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:3712"
wire input 18 \RST
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:3704"
wire output 11 \SBITERR
attribute \clkbuf_sink 1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:3714"
wire input 19 \WRCLK
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:3705"
wire width 9 output 12 \WRCOUNT
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:3715"
wire input 20 \WREN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:3706"
wire output 13 \WRERR
end
attribute \blackbox 1
attribute \cells_not_processed 1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:9579"
module \FRAME_ECCE2
parameter \FARSRC
parameter \FRAME_RBT_IN_FILENAME
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:9582"
wire output 1 \CRCERROR
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:9583"
wire output 2 \ECCERROR
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:9584"
wire output 3 \ECCERRORSINGLE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:9587"
wire width 26 output 6 \FAR
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:9588"
wire width 5 output 7 \SYNBIT
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:9586"
wire width 13 output 5 \SYNDROME
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:9585"
wire output 4 \SYNDROMEVALID
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:9589"
wire width 7 output 8 \SYNWORD
end
attribute \blackbox 1
attribute \cells_not_processed 1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:9592"
module \FRAME_ECCE3
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:9593"
wire output 1 \CRCERROR
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:9594"
wire output 2 \ECCERRORNOTSINGLE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:9595"
wire output 3 \ECCERRORSINGLE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:9596"
wire output 4 \ENDOFFRAME
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:9597"
wire output 5 \ENDOFSCAN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:9598"
wire width 26 output 6 \FAR
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:9599"
wire width 2 input 7 \FARSEL
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:9600"
wire input 8 \ICAPBOTCLK
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:9601"
wire input 9 \ICAPTOPCLK
end
attribute \blackbox 1
attribute \cells_not_processed 1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:9553"
module \FRAME_ECC_VIRTEX4
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:9554"
wire output 1 \ERROR
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:9555"
wire width 12 output 2 \SYNDROME
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:9556"
wire output 3 \SYNDROMEVALID
end
attribute \blackbox 1
attribute \cells_not_processed 1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:9559"
module \FRAME_ECC_VIRTEX5
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:9560"
wire output 1 \CRCERROR
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:9561"
wire output 2 \ECCERROR
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:9563"
wire width 12 output 4 \SYNDROME
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:9562"
wire output 3 \SYNDROMEVALID
end
attribute \blackbox 1
attribute \cells_not_processed 1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:9566"
module \FRAME_ECC_VIRTEX6
parameter \FARSRC
parameter \FRAME_RBT_IN_FILENAME
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:9569"
wire output 1 \CRCERROR
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:9570"
wire output 2 \ECCERROR
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:9571"
wire output 3 \ECCERRORSINGLE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:9574"
wire width 24 output 6 \FAR
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:9575"
wire width 5 output 7 \SYNBIT
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:9573"
wire width 13 output 5 \SYNDROME
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:9572"
wire output 4 \SYNDROMEVALID
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:9576"
wire width 7 output 8 \SYNWORD
end
attribute \blackbox 1
attribute \cells_not_processed 1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_sim.v:28"
module \GND
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_sim.v:28"
wire output 1 \G
end
attribute \blackbox 1
attribute \cells_not_processed 1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11271"
module \GT11CLK
parameter \REFCLKSEL
parameter \SYNCLK1OUTEN
parameter \SYNCLK2OUTEN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11277"
wire input 3 \MGTCLKN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11278"
wire input 4 \MGTCLKP
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11279"
wire input 5 \REFCLK
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11280"
wire input 6 \RXBCLK
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11281"
wire input 7 \SYNCLK1IN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11275"
wire output 1 \SYNCLK1OUT
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11282"
wire input 8 \SYNCLK2IN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11276"
wire output 2 \SYNCLK2OUT
end
attribute \blackbox 1
attribute \cells_not_processed 1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11285"
module \GT11CLK_MGT
parameter \SYNCLK1OUTEN
parameter \SYNCLK2OUTEN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11290"
wire input 3 \MGTCLKN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11291"
wire input 4 \MGTCLKP
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11288"
wire output 1 \SYNCLK1OUT
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11289"
wire output 2 \SYNCLK2OUT
end
attribute \blackbox 1
attribute \cells_not_processed 1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:10458"
module \GT11_CUSTOM
parameter \ALIGN_COMMA_WORD
parameter \BANDGAPSEL
parameter \BIASRESSEL
parameter \CCCB_ARBITRATOR_DISABLE
parameter \CHAN_BOND_LIMIT
parameter \CHAN_BOND_MODE
parameter \CHAN_BOND_ONE_SHOT
parameter \CHAN_BOND_SEQ_1_1
parameter \CHAN_BOND_SEQ_1_2
parameter \CHAN_BOND_SEQ_1_3
parameter \CHAN_BOND_SEQ_1_4
parameter \CHAN_BOND_SEQ_1_MASK
parameter \CHAN_BOND_SEQ_2_1
parameter \CHAN_BOND_SEQ_2_2
parameter \CHAN_BOND_SEQ_2_3
parameter \CHAN_BOND_SEQ_2_4
parameter \CHAN_BOND_SEQ_2_MASK
parameter \CHAN_BOND_SEQ_2_USE
parameter \CHAN_BOND_SEQ_LEN
parameter \CLK_CORRECT_USE
parameter \CLK_COR_8B10B_DE
parameter \CLK_COR_MAX_LAT
parameter \CLK_COR_MIN_LAT
parameter \CLK_COR_SEQ_1_1
parameter \CLK_COR_SEQ_1_2
parameter \CLK_COR_SEQ_1_3
parameter \CLK_COR_SEQ_1_4
parameter \CLK_COR_SEQ_1_MASK
parameter \CLK_COR_SEQ_2_1
parameter \CLK_COR_SEQ_2_2
parameter \CLK_COR_SEQ_2_3
parameter \CLK_COR_SEQ_2_4
parameter \CLK_COR_SEQ_2_MASK
parameter \CLK_COR_SEQ_2_USE
parameter \CLK_COR_SEQ_DROP
parameter \CLK_COR_SEQ_LEN
parameter \COMMA32
parameter \COMMA_10B_MASK
parameter \CYCLE_LIMIT_SEL
parameter \DCDR_FILTER
parameter \DEC_MCOMMA_DETECT
parameter \DEC_PCOMMA_DETECT
parameter \DEC_VALID_COMMA_ONLY
parameter \DIGRX_FWDCLK
parameter \DIGRX_SYNC_MODE
parameter \ENABLE_DCDR
parameter \FDET_HYS_CAL
parameter \FDET_HYS_SEL
parameter \FDET_LCK_CAL
parameter \FDET_LCK_SEL
parameter \GT11_MODE
parameter \IREFBIASMODE
parameter \LOOPCAL_WAIT
parameter \MCOMMA_32B_VALUE
parameter \MCOMMA_DETECT
parameter \OPPOSITE_SELECT
parameter \PCOMMA_32B_VALUE
parameter \PCOMMA_DETECT
parameter \PCS_BIT_SLIP
parameter \PMACLKENABLE
parameter \PMACOREPWRENABLE
parameter \PMAIREFTRIM
parameter \PMAVBGCTRL
parameter \PMAVREFTRIM
parameter \PMA_BIT_SLIP
parameter \REPEATER
parameter \RXACTST
parameter \RXAFEEQ
parameter \RXAFEPD
parameter \RXAFETST
parameter \RXAPD
parameter \RXASYNCDIVIDE
parameter \RXBY_32
parameter \RXCDRLOS
parameter \RXCLK0_FORCE_PMACLK
parameter \RXCLKMODE
parameter \RXCMADJ
parameter \RXCPSEL
parameter \RXCPTST
parameter \RXCRCCLOCKDOUBLE
parameter \RXCRCENABLE
parameter \RXCRCINITVAL
parameter \RXCRCINVERTGEN
parameter \RXCRCSAMECLOCK
parameter \RXCTRL1
parameter \RXCYCLE_LIMIT_SEL
parameter \RXDATA_SEL
parameter \RXDCCOUPLE
parameter \RXDIGRESET
parameter \RXDIGRX
parameter \RXEQ
parameter \RXFDCAL_CLOCK_DIVIDE
parameter \RXFDET_HYS_CAL
parameter \RXFDET_HYS_SEL
parameter \RXFDET_LCK_CAL
parameter \RXFDET_LCK_SEL
parameter \RXFECONTROL1
parameter \RXFECONTROL2
parameter \RXFETUNE
parameter \RXLB
parameter \RXLKADJ
parameter \RXLKAPD
parameter \RXLOOPCAL_WAIT
parameter \RXLOOPFILT
parameter \RXOUTDIV2SEL
parameter \RXPD
parameter \RXPDDTST
parameter \RXPLLNDIVSEL
parameter \RXPMACLKSEL
parameter \RXRCPADJ
parameter \RXRCPPD
parameter \RXRECCLK1_USE_SYNC
parameter \RXRIBADJ
parameter \RXRPDPD
parameter \RXRSDPD
parameter \RXSLOWDOWN_CAL
parameter \RXUSRDIVISOR
parameter \RXVCODAC_INIT
parameter \RXVCO_CTRL_ENABLE
parameter \RX_BUFFER_USE
parameter \RX_CLOCK_DIVIDER
parameter \RX_LOS_INVALID_INCR
parameter \RX_LOS_THRESHOLD
parameter \SAMPLE_8X
parameter \SH_CNT_MAX
parameter \SH_INVALID_CNT_MAX
parameter \SLOWDOWN_CAL
parameter \TXABPMACLKSEL
parameter \TXAPD
parameter \TXAREFBIASSEL
parameter \TXASYNCDIVIDE
parameter \TXCLK0_FORCE_PMACLK
parameter \TXCLKMODE
parameter \TXCPSEL
parameter \TXCRCCLOCKDOUBLE
parameter \TXCRCENABLE
parameter \TXCRCINITVAL
parameter \TXCRCINVERTGEN
parameter \TXCRCSAMECLOCK
parameter \TXCTRL1
parameter \TXDATA_SEL
parameter \TXDAT_PRDRV_DAC
parameter \TXDAT_TAP_DAC
parameter \TXDIGPD
parameter \TXFDCAL_CLOCK_DIVIDE
parameter \TXHIGHSIGNALEN
parameter \TXLOOPFILT
parameter \TXLVLSHFTPD
parameter \TXOUTCLK1_USE_SYNC
parameter \TXOUTDIV2SEL
parameter \TXPD
parameter \TXPHASESEL
parameter \TXPLLNDIVSEL
parameter \TXPOST_PRDRV_DAC
parameter \TXPOST_TAP_DAC
parameter \TXPOST_TAP_PD
parameter \TXPRE_PRDRV_DAC
parameter \TXPRE_TAP_DAC
parameter \TXPRE_TAP_PD
parameter \TXSLEWRATE
parameter \TXTERMTRIM
parameter \TX_BUFFER_USE
parameter \TX_CLOCK_DIVIDER
parameter \VCODAC_INIT
parameter \VCO_CTRL_ENABLE
parameter \VREFBIASMODE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:10719"
wire width 5 input 95 \CHBONDI
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:10650"
wire width 5 output 26 \CHBONDO
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:10723"
wire width 8 input 99 \DADDR
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:10660"
wire input 36 \DCLK
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:10661"
wire input 37 \DEN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:10711"
wire width 16 input 87 \DI
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:10646"
wire width 16 output 22 \DO
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:10625"
wire output 1 \DRDY
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:10662"
wire input 38 \DWE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:10663"
wire input 39 \ENCHANSYNC
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:10664"
wire input 40 \ENMCOMMAALIGN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:10665"
wire input 41 \ENPCOMMAALIGN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:10666"
wire input 42 \GREFCLK
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:10712"
wire width 2 input 88 \LOOPBACK
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:10667"
wire input 43 \POWERDOWN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:10668"
wire input 44 \REFCLK1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:10669"
wire input 45 \REFCLK2
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:10670"
wire input 46 \RX1N
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:10671"
wire input 47 \RX1P
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:10672"
wire input 48 \RXBLOCKSYNC64B66BUSE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:10626"
wire output 2 \RXBUFERR
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:10627"
wire output 3 \RXCALFAIL
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:10653"
wire width 8 output 29 \RXCHARISCOMMA
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:10654"
wire width 8 output 30 \RXCHARISK
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:10673"
wire input 49 \RXCLKSTABLE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:10628"
wire output 4 \RXCOMMADET
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:10674"
wire input 50 \RXCOMMADETUSE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:10675"
wire input 51 \RXCRCCLK
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:10676"
wire input 52 \RXCRCDATAVALID
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:10717"
wire width 3 input 93 \RXCRCDATAWIDTH
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:10720"
wire width 64 input 96 \RXCRCIN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:10677"
wire input 53 \RXCRCINIT
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:10678"
wire input 54 \RXCRCINTCLK
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:10648"
wire width 32 output 24 \RXCRCOUT
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:10679"
wire input 55 \RXCRCPD
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:10680"
wire input 56 \RXCRCRESET
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:10629"
wire output 5 \RXCYCLELIMIT
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:10652"
wire width 64 output 28 \RXDATA
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:10713"
wire width 2 input 89 \RXDATAWIDTH
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:10681"
wire input 57 \RXDEC64B66BUSE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:10682"
wire input 58 \RXDEC8B10BUSE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:10683"
wire input 59 \RXDESCRAM64B66BUSE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:10655"
wire width 8 output 31 \RXDISPERR
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:10684"
wire input 60 \RXIGNOREBTF
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:10714"
wire width 2 input 90 \RXINTDATAWIDTH
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:10630"
wire output 6 \RXLOCK
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:10647"
wire width 2 output 23 \RXLOSSOFSYNC
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:10631"
wire output 7 \RXMCLK
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:10656"
wire width 8 output 32 \RXNOTINTABLE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:10632"
wire output 8 \RXPCSHCLKOUT
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:10685"
wire input 61 \RXPMARESET
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:10686"
wire input 62 \RXPOLARITY
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:10633"
wire output 9 \RXREALIGN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:10634"
wire output 10 \RXRECCLK1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:10635"
wire output 11 \RXRECCLK2
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:10687"
wire input 63 \RXRESET
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:10657"
wire width 8 output 33 \RXRUNDISP
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:10636"
wire output 12 \RXSIGDET
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:10688"
wire input 64 \RXSLIDE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:10651"
wire width 6 output 27 \RXSTATUS
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:10689"
wire input 65 \RXSYNC
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:10691"
wire input 67 \RXUSRCLK
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:10690"
wire input 66 \RXUSRCLK2
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:10637"
wire output 13 \TX1N
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:10638"
wire output 14 \TX1P
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:10639"
wire output 15 \TXBUFERR
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:10724"
wire width 8 input 100 \TXBYPASS8B10B
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:10640"
wire output 16 \TXCALFAIL
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:10725"
wire width 8 input 101 \TXCHARDISPMODE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:10726"
wire width 8 input 102 \TXCHARDISPVAL
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:10727"
wire width 8 input 103 \TXCHARISK
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:10692"
wire input 68 \TXCLKSTABLE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:10693"
wire input 69 \TXCRCCLK
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:10694"
wire input 70 \TXCRCDATAVALID
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:10718"
wire width 3 input 94 \TXCRCDATAWIDTH
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:10721"
wire width 64 input 97 \TXCRCIN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:10695"
wire input 71 \TXCRCINIT
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:10696"
wire input 72 \TXCRCINTCLK
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:10649"
wire width 32 output 25 \TXCRCOUT
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:10697"
wire input 73 \TXCRCPD
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:10698"
wire input 74 \TXCRCRESET
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:10641"
wire output 17 \TXCYCLELIMIT
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:10722"
wire width 64 input 98 \TXDATA
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:10715"
wire width 2 input 91 \TXDATAWIDTH
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:10699"
wire input 75 \TXENC64B66BUSE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:10700"
wire input 76 \TXENC8B10BUSE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:10701"
wire input 77 \TXENOOB
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:10702"
wire input 78 \TXGEARBOX64B66BUSE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:10703"
wire input 79 \TXINHIBIT
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:10716"
wire width 2 input 92 \TXINTDATAWIDTH
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:10658"
wire width 8 output 34 \TXKERR
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:10642"
wire output 18 \TXLOCK
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:10643"
wire output 19 \TXOUTCLK1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:10644"
wire output 20 \TXOUTCLK2
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:10645"
wire output 21 \TXPCSHCLKOUT
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:10704"
wire input 80 \TXPMARESET
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:10705"
wire input 81 \TXPOLARITY
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:10706"
wire input 82 \TXRESET
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:10659"
wire width 8 output 35 \TXRUNDISP
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:10707"
wire input 83 \TXSCRAM64B66BUSE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:10708"
wire input 84 \TXSYNC
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:10710"
wire input 86 \TXUSRCLK
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:10709"
wire input 85 \TXUSRCLK2
end
attribute \blackbox 1
attribute \cells_not_processed 1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:10730"
module \GT11_DUAL
parameter \ALIGN_COMMA_WORD_A
parameter \ALIGN_COMMA_WORD_B
parameter \BANDGAPSEL_A
parameter \BANDGAPSEL_B
parameter \BIASRESSEL_A
parameter \BIASRESSEL_B
parameter \CCCB_ARBITRATOR_DISABLE_A
parameter \CCCB_ARBITRATOR_DISABLE_B
parameter \CHAN_BOND_LIMIT_A
parameter \CHAN_BOND_LIMIT_B
parameter \CHAN_BOND_MODE_A
parameter \CHAN_BOND_MODE_B
parameter \CHAN_BOND_ONE_SHOT_A
parameter \CHAN_BOND_ONE_SHOT_B
parameter \CHAN_BOND_SEQ_1_1_A
parameter \CHAN_BOND_SEQ_1_1_B
parameter \CHAN_BOND_SEQ_1_2_A
parameter \CHAN_BOND_SEQ_1_2_B
parameter \CHAN_BOND_SEQ_1_3_A
parameter \CHAN_BOND_SEQ_1_3_B
parameter \CHAN_BOND_SEQ_1_4_A
parameter \CHAN_BOND_SEQ_1_4_B
parameter \CHAN_BOND_SEQ_1_MASK_A
parameter \CHAN_BOND_SEQ_1_MASK_B
parameter \CHAN_BOND_SEQ_2_1_A
parameter \CHAN_BOND_SEQ_2_1_B
parameter \CHAN_BOND_SEQ_2_2_A
parameter \CHAN_BOND_SEQ_2_2_B
parameter \CHAN_BOND_SEQ_2_3_A
parameter \CHAN_BOND_SEQ_2_3_B
parameter \CHAN_BOND_SEQ_2_4_A
parameter \CHAN_BOND_SEQ_2_4_B
parameter \CHAN_BOND_SEQ_2_MASK_A
parameter \CHAN_BOND_SEQ_2_MASK_B
parameter \CHAN_BOND_SEQ_2_USE_A
parameter \CHAN_BOND_SEQ_2_USE_B
parameter \CHAN_BOND_SEQ_LEN_A
parameter \CHAN_BOND_SEQ_LEN_B
parameter \CLK_CORRECT_USE_A
parameter \CLK_CORRECT_USE_B
parameter \CLK_COR_8B10B_DE_A
parameter \CLK_COR_8B10B_DE_B
parameter \CLK_COR_MAX_LAT_A
parameter \CLK_COR_MAX_LAT_B
parameter \CLK_COR_MIN_LAT_A
parameter \CLK_COR_MIN_LAT_B
parameter \CLK_COR_SEQ_1_1_A
parameter \CLK_COR_SEQ_1_1_B
parameter \CLK_COR_SEQ_1_2_A
parameter \CLK_COR_SEQ_1_2_B
parameter \CLK_COR_SEQ_1_3_A
parameter \CLK_COR_SEQ_1_3_B
parameter \CLK_COR_SEQ_1_4_A
parameter \CLK_COR_SEQ_1_4_B
parameter \CLK_COR_SEQ_1_MASK_A
parameter \CLK_COR_SEQ_1_MASK_B
parameter \CLK_COR_SEQ_2_1_A
parameter \CLK_COR_SEQ_2_1_B
parameter \CLK_COR_SEQ_2_2_A
parameter \CLK_COR_SEQ_2_2_B
parameter \CLK_COR_SEQ_2_3_A
parameter \CLK_COR_SEQ_2_3_B
parameter \CLK_COR_SEQ_2_4_A
parameter \CLK_COR_SEQ_2_4_B
parameter \CLK_COR_SEQ_2_MASK_A
parameter \CLK_COR_SEQ_2_MASK_B
parameter \CLK_COR_SEQ_2_USE_A
parameter \CLK_COR_SEQ_2_USE_B
parameter \CLK_COR_SEQ_DROP_A
parameter \CLK_COR_SEQ_DROP_B
parameter \CLK_COR_SEQ_LEN_A
parameter \CLK_COR_SEQ_LEN_B
parameter \COMMA32_A
parameter \COMMA32_B
parameter \COMMA_10B_MASK_A
parameter \COMMA_10B_MASK_B
parameter \CYCLE_LIMIT_SEL_A
parameter \CYCLE_LIMIT_SEL_B
parameter \DCDR_FILTER_A
parameter \DCDR_FILTER_B
parameter \DEC_MCOMMA_DETECT_A
parameter \DEC_MCOMMA_DETECT_B
parameter \DEC_PCOMMA_DETECT_A
parameter \DEC_PCOMMA_DETECT_B
parameter \DEC_VALID_COMMA_ONLY_A
parameter \DEC_VALID_COMMA_ONLY_B
parameter \DIGRX_FWDCLK_A
parameter \DIGRX_FWDCLK_B
parameter \DIGRX_SYNC_MODE_A
parameter \DIGRX_SYNC_MODE_B
parameter \ENABLE_DCDR_A
parameter \ENABLE_DCDR_B
parameter \FDET_HYS_CAL_A
parameter \FDET_HYS_CAL_B
parameter \FDET_HYS_SEL_A
parameter \FDET_HYS_SEL_B
parameter \FDET_LCK_CAL_A
parameter \FDET_LCK_CAL_B
parameter \FDET_LCK_SEL_A
parameter \FDET_LCK_SEL_B
parameter \IREFBIASMODE_A
parameter \IREFBIASMODE_B
parameter \LOOPCAL_WAIT_A
parameter \LOOPCAL_WAIT_B
parameter \MCOMMA_32B_VALUE_A
parameter \MCOMMA_32B_VALUE_B
parameter \MCOMMA_DETECT_A
parameter \MCOMMA_DETECT_B
parameter \OPPOSITE_SELECT_A
parameter \OPPOSITE_SELECT_B
parameter \PCOMMA_32B_VALUE_A
parameter \PCOMMA_32B_VALUE_B
parameter \PCOMMA_DETECT_A
parameter \PCOMMA_DETECT_B
parameter \PCS_BIT_SLIP_A
parameter \PCS_BIT_SLIP_B
parameter \PMACLKENABLE_A
parameter \PMACLKENABLE_B
parameter \PMACOREPWRENABLE_A
parameter \PMACOREPWRENABLE_B
parameter \PMAIREFTRIM_A
parameter \PMAIREFTRIM_B
parameter \PMAVBGCTRL_A
parameter \PMAVBGCTRL_B
parameter \PMAVREFTRIM_A
parameter \PMAVREFTRIM_B
parameter \PMA_BIT_SLIP_A
parameter \PMA_BIT_SLIP_B
parameter \POWER_ENABLE_A
parameter \POWER_ENABLE_B
parameter \REPEATER_A
parameter \REPEATER_B
parameter \RXACTST_A
parameter \RXACTST_B
parameter \RXAFEEQ_A
parameter \RXAFEEQ_B
parameter \RXAFEPD_A
parameter \RXAFEPD_B
parameter \RXAFETST_A
parameter \RXAFETST_B
parameter \RXAPD_A
parameter \RXAPD_B
parameter \RXASYNCDIVIDE_A
parameter \RXASYNCDIVIDE_B
parameter \RXBY_32_A
parameter \RXBY_32_B
parameter \RXCDRLOS_A
parameter \RXCDRLOS_B
parameter \RXCLK0_FORCE_PMACLK_A
parameter \RXCLK0_FORCE_PMACLK_B
parameter \RXCLKMODE_A
parameter \RXCLKMODE_B
parameter \RXCMADJ_A
parameter \RXCMADJ_B
parameter \RXCPSEL_A
parameter \RXCPSEL_B
parameter \RXCPTST_A
parameter \RXCPTST_B
parameter \RXCRCCLOCKDOUBLE_A
parameter \RXCRCCLOCKDOUBLE_B
parameter \RXCRCENABLE_A
parameter \RXCRCENABLE_B
parameter \RXCRCINITVAL_A
parameter \RXCRCINITVAL_B
parameter \RXCRCINVERTGEN_A
parameter \RXCRCINVERTGEN_B
parameter \RXCRCSAMECLOCK_A
parameter \RXCRCSAMECLOCK_B
parameter \RXCTRL1_A
parameter \RXCTRL1_B
parameter \RXCYCLE_LIMIT_SEL_A
parameter \RXCYCLE_LIMIT_SEL_B
parameter \RXDATA_SEL_A
parameter \RXDATA_SEL_B
parameter \RXDCCOUPLE_A
parameter \RXDCCOUPLE_B
parameter \RXDIGRESET_A
parameter \RXDIGRESET_B
parameter \RXDIGRX_A
parameter \RXDIGRX_B
parameter \RXEQ_A
parameter \RXEQ_B
parameter \RXFDCAL_CLOCK_DIVIDE_A
parameter \RXFDCAL_CLOCK_DIVIDE_B
parameter \RXFDET_HYS_CAL_A
parameter \RXFDET_HYS_CAL_B
parameter \RXFDET_HYS_SEL_A
parameter \RXFDET_HYS_SEL_B
parameter \RXFDET_LCK_CAL_A
parameter \RXFDET_LCK_CAL_B
parameter \RXFDET_LCK_SEL_A
parameter \RXFDET_LCK_SEL_B
parameter \RXFECONTROL1_A
parameter \RXFECONTROL1_B
parameter \RXFECONTROL2_A
parameter \RXFECONTROL2_B
parameter \RXFETUNE_A
parameter \RXFETUNE_B
parameter \RXLB_A
parameter \RXLB_B
parameter \RXLKADJ_A
parameter \RXLKADJ_B
parameter \RXLKAPD_A
parameter \RXLKAPD_B
parameter \RXLOOPCAL_WAIT_A
parameter \RXLOOPCAL_WAIT_B
parameter \RXLOOPFILT_A
parameter \RXLOOPFILT_B
parameter \RXOUTDIV2SEL_A
parameter \RXOUTDIV2SEL_B
parameter \RXPDDTST_A
parameter \RXPDDTST_B
parameter \RXPD_A
parameter \RXPD_B
parameter \RXPLLNDIVSEL_A
parameter \RXPLLNDIVSEL_B
parameter \RXPMACLKSEL_A
parameter \RXPMACLKSEL_B
parameter \RXRCPADJ_A
parameter \RXRCPADJ_B
parameter \RXRCPPD_A
parameter \RXRCPPD_B
parameter \RXRECCLK1_USE_SYNC_A
parameter \RXRECCLK1_USE_SYNC_B
parameter \RXRIBADJ_A
parameter \RXRIBADJ_B
parameter \RXRPDPD_A
parameter \RXRPDPD_B
parameter \RXRSDPD_A
parameter \RXRSDPD_B
parameter \RXSLOWDOWN_CAL_A
parameter \RXSLOWDOWN_CAL_B
parameter \RXUSRDIVISOR_A
parameter \RXUSRDIVISOR_B
parameter \RXVCODAC_INIT_A
parameter \RXVCODAC_INIT_B
parameter \RXVCO_CTRL_ENABLE_A
parameter \RXVCO_CTRL_ENABLE_B
parameter \RX_BUFFER_USE_A
parameter \RX_BUFFER_USE_B
parameter \RX_CLOCK_DIVIDER_A
parameter \RX_CLOCK_DIVIDER_B
parameter \RX_LOS_INVALID_INCR_A
parameter \RX_LOS_INVALID_INCR_B
parameter \RX_LOS_THRESHOLD_A
parameter \RX_LOS_THRESHOLD_B
parameter \SAMPLE_8X_A
parameter \SAMPLE_8X_B
parameter \SH_CNT_MAX_A
parameter \SH_CNT_MAX_B
parameter \SH_INVALID_CNT_MAX_A
parameter \SH_INVALID_CNT_MAX_B
parameter \SLOWDOWN_CAL_A
parameter \SLOWDOWN_CAL_B
parameter \TXABPMACLKSEL_A
parameter \TXABPMACLKSEL_B
parameter \TXAPD_A
parameter \TXAPD_B
parameter \TXAREFBIASSEL_A
parameter \TXAREFBIASSEL_B
parameter \TXASYNCDIVIDE_A
parameter \TXASYNCDIVIDE_B
parameter \TXCLK0_FORCE_PMACLK_A
parameter \TXCLK0_FORCE_PMACLK_B
parameter \TXCLKMODE_A
parameter \TXCLKMODE_B
parameter \TXCPSEL_A
parameter \TXCPSEL_B
parameter \TXCRCCLOCKDOUBLE_A
parameter \TXCRCCLOCKDOUBLE_B
parameter \TXCRCENABLE_A
parameter \TXCRCENABLE_B
parameter \TXCRCINITVAL_A
parameter \TXCRCINITVAL_B
parameter \TXCRCINVERTGEN_A
parameter \TXCRCINVERTGEN_B
parameter \TXCRCSAMECLOCK_A
parameter \TXCRCSAMECLOCK_B
parameter \TXCTRL1_A
parameter \TXCTRL1_B
parameter \TXDATA_SEL_A
parameter \TXDATA_SEL_B
parameter \TXDAT_PRDRV_DAC_A
parameter \TXDAT_PRDRV_DAC_B
parameter \TXDAT_TAP_DAC_A
parameter \TXDAT_TAP_DAC_B
parameter \TXDIGPD_A
parameter \TXDIGPD_B
parameter \TXFDCAL_CLOCK_DIVIDE_A
parameter \TXFDCAL_CLOCK_DIVIDE_B
parameter \TXHIGHSIGNALEN_A
parameter \TXHIGHSIGNALEN_B
parameter \TXLOOPFILT_A
parameter \TXLOOPFILT_B
parameter \TXLVLSHFTPD_A
parameter \TXLVLSHFTPD_B
parameter \TXOUTCLK1_USE_SYNC_A
parameter \TXOUTCLK1_USE_SYNC_B
parameter \TXOUTDIV2SEL_A
parameter \TXOUTDIV2SEL_B
parameter \TXPD_A
parameter \TXPD_B
parameter \TXPHASESEL_A
parameter \TXPHASESEL_B
parameter \TXPLLNDIVSEL_A
parameter \TXPLLNDIVSEL_B
parameter \TXPOST_PRDRV_DAC_A
parameter \TXPOST_PRDRV_DAC_B
parameter \TXPOST_TAP_DAC_A
parameter \TXPOST_TAP_DAC_B
parameter \TXPOST_TAP_PD_A
parameter \TXPOST_TAP_PD_B
parameter \TXPRE_PRDRV_DAC_A
parameter \TXPRE_PRDRV_DAC_B
parameter \TXPRE_TAP_DAC_A
parameter \TXPRE_TAP_DAC_B
parameter \TXPRE_TAP_PD_A
parameter \TXPRE_TAP_PD_B
parameter \TXSLEWRATE_A
parameter \TXSLEWRATE_B
parameter \TXTERMTRIM_A
parameter \TXTERMTRIM_B
parameter \TX_BUFFER_USE_A
parameter \TX_BUFFER_USE_B
parameter \TX_CLOCK_DIVIDER_A
parameter \TX_CLOCK_DIVIDER_B
parameter \VCODAC_INIT_A
parameter \VCODAC_INIT_B
parameter \VCO_CTRL_ENABLE_A
parameter \VCO_CTRL_ENABLE_B
parameter \VREFBIASMODE_A
parameter \VREFBIASMODE_B
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11251"
wire width 5 input 189 \CHBONDIA
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11252"
wire width 5 input 190 \CHBONDIB
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11113"
wire width 5 output 51 \CHBONDOA
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11114"
wire width 5 output 52 \CHBONDOB
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11259"
wire width 8 input 197 \DADDRA
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11260"
wire width 8 input 198 \DADDRB
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11133"
wire input 71 \DCLKA
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11134"
wire input 72 \DCLKB
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11135"
wire input 73 \DENA
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11136"
wire input 74 \DENB
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11235"
wire width 16 input 173 \DIA
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11236"
wire width 16 input 174 \DIB
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11105"
wire width 16 output 43 \DOA
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11106"
wire width 16 output 44 \DOB
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11063"
wire output 1 \DRDYA
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11064"
wire output 2 \DRDYB
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11137"
wire input 75 \DWEA
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11138"
wire input 76 \DWEB
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11139"
wire input 77 \ENCHANSYNCA
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11140"
wire input 78 \ENCHANSYNCB
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11141"
wire input 79 \ENMCOMMAALIGNA
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11142"
wire input 80 \ENMCOMMAALIGNB
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11143"
wire input 81 \ENPCOMMAALIGNA
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11144"
wire input 82 \ENPCOMMAALIGNB
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11145"
wire input 83 \GREFCLKA
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11146"
wire input 84 \GREFCLKB
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11237"
wire width 2 input 175 \LOOPBACKA
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11238"
wire width 2 input 176 \LOOPBACKB
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11147"
wire input 85 \POWERDOWNA
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11148"
wire input 86 \POWERDOWNB
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11149"
wire input 87 \REFCLK1A
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11150"
wire input 88 \REFCLK1B
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11151"
wire input 89 \REFCLK2A
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11152"
wire input 90 \REFCLK2B
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11153"
wire input 91 \RX1NA
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11154"
wire input 92 \RX1NB
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11155"
wire input 93 \RX1PA
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11156"
wire input 94 \RX1PB
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11157"
wire input 95 \RXBLOCKSYNC64B66BUSEA
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11158"
wire input 96 \RXBLOCKSYNC64B66BUSEB
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11065"
wire output 3 \RXBUFERRA
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11066"
wire output 4 \RXBUFERRB
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11067"
wire output 5 \RXCALFAILA
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11068"
wire output 6 \RXCALFAILB
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11119"
wire width 8 output 57 \RXCHARISCOMMAA
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11120"
wire width 8 output 58 \RXCHARISCOMMAB
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11121"
wire width 8 output 59 \RXCHARISKA
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11122"
wire width 8 output 60 \RXCHARISKB
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11159"
wire input 97 \RXCLKSTABLEA
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11160"
wire input 98 \RXCLKSTABLEB
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11069"
wire output 7 \RXCOMMADETA
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11070"
wire output 8 \RXCOMMADETB
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11161"
wire input 99 \RXCOMMADETUSEA
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11162"
wire input 100 \RXCOMMADETUSEB
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11163"
wire input 101 \RXCRCCLKA
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11164"
wire input 102 \RXCRCCLKB
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11165"
wire input 103 \RXCRCDATAVALIDA
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11166"
wire input 104 \RXCRCDATAVALIDB
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11247"
wire width 3 input 185 \RXCRCDATAWIDTHA
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11248"
wire width 3 input 186 \RXCRCDATAWIDTHB
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11253"
wire width 64 input 191 \RXCRCINA
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11254"
wire width 64 input 192 \RXCRCINB
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11167"
wire input 105 \RXCRCINITA
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11168"
wire input 106 \RXCRCINITB
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11169"
wire input 107 \RXCRCINTCLKA
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11170"
wire input 108 \RXCRCINTCLKB
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11109"
wire width 32 output 47 \RXCRCOUTA
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11110"
wire width 32 output 48 \RXCRCOUTB
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11171"
wire input 109 \RXCRCPDA
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11172"
wire input 110 \RXCRCPDB
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11173"
wire input 111 \RXCRCRESETA
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11174"
wire input 112 \RXCRCRESETB
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11071"
wire output 9 \RXCYCLELIMITA
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11072"
wire output 10 \RXCYCLELIMITB
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11117"
wire width 64 output 55 \RXDATAA
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11118"
wire width 64 output 56 \RXDATAB
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11239"
wire width 2 input 177 \RXDATAWIDTHA
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11240"
wire width 2 input 178 \RXDATAWIDTHB
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11175"
wire input 113 \RXDEC64B66BUSEA
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11176"
wire input 114 \RXDEC64B66BUSEB
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11177"
wire input 115 \RXDEC8B10BUSEA
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11178"
wire input 116 \RXDEC8B10BUSEB
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11179"
wire input 117 \RXDESCRAM64B66BUSEA
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11180"
wire input 118 \RXDESCRAM64B66BUSEB
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11123"
wire width 8 output 61 \RXDISPERRA
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11124"
wire width 8 output 62 \RXDISPERRB
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11181"
wire input 119 \RXIGNOREBTFA
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11182"
wire input 120 \RXIGNOREBTFB
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11241"
wire width 2 input 179 \RXINTDATAWIDTHA
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11242"
wire width 2 input 180 \RXINTDATAWIDTHB
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11073"
wire output 11 \RXLOCKA
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11074"
wire output 12 \RXLOCKB
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11107"
wire width 2 output 45 \RXLOSSOFSYNCA
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11108"
wire width 2 output 46 \RXLOSSOFSYNCB
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11075"
wire output 13 \RXMCLKA
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11076"
wire output 14 \RXMCLKB
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11125"
wire width 8 output 63 \RXNOTINTABLEA
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11126"
wire width 8 output 64 \RXNOTINTABLEB
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11077"
wire output 15 \RXPCSHCLKOUTA
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11078"
wire output 16 \RXPCSHCLKOUTB
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11183"
wire input 121 \RXPMARESETA
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11184"
wire input 122 \RXPMARESETB
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11185"
wire input 123 \RXPOLARITYA
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11186"
wire input 124 \RXPOLARITYB
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11079"
wire output 17 \RXREALIGNA
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11080"
wire output 18 \RXREALIGNB
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11081"
wire output 19 \RXRECCLK1A
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11082"
wire output 20 \RXRECCLK1B
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11083"
wire output 21 \RXRECCLK2A
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11084"
wire output 22 \RXRECCLK2B
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11187"
wire input 125 \RXRESETA
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11188"
wire input 126 \RXRESETB
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11127"
wire width 8 output 65 \RXRUNDISPA
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11128"
wire width 8 output 66 \RXRUNDISPB
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11085"
wire output 23 \RXSIGDETA
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11086"
wire output 24 \RXSIGDETB
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11189"
wire input 127 \RXSLIDEA
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11190"
wire input 128 \RXSLIDEB
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11115"
wire width 6 output 53 \RXSTATUSA
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11116"
wire width 6 output 54 \RXSTATUSB
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11191"
wire input 129 \RXSYNCA
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11192"
wire input 130 \RXSYNCB
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11193"
wire input 131 \RXUSRCLK2A
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11194"
wire input 132 \RXUSRCLK2B
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11195"
wire input 133 \RXUSRCLKA
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11196"
wire input 134 \RXUSRCLKB
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11087"
wire output 25 \TX1NA
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11088"
wire output 26 \TX1NB
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11089"
wire output 27 \TX1PA
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11090"
wire output 28 \TX1PB
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11091"
wire output 29 \TXBUFERRA
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11092"
wire output 30 \TXBUFERRB
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11261"
wire width 8 input 199 \TXBYPASS8B10BA
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11262"
wire width 8 input 200 \TXBYPASS8B10BB
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11093"
wire output 31 \TXCALFAILA
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11094"
wire output 32 \TXCALFAILB
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11263"
wire width 8 input 201 \TXCHARDISPMODEA
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11264"
wire width 8 input 202 \TXCHARDISPMODEB
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11265"
wire width 8 input 203 \TXCHARDISPVALA
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11266"
wire width 8 input 204 \TXCHARDISPVALB
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11267"
wire width 8 input 205 \TXCHARISKA
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11268"
wire width 8 input 206 \TXCHARISKB
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11197"
wire input 135 \TXCLKSTABLEA
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11198"
wire input 136 \TXCLKSTABLEB
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11199"
wire input 137 \TXCRCCLKA
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11200"
wire input 138 \TXCRCCLKB
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11201"
wire input 139 \TXCRCDATAVALIDA
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11202"
wire input 140 \TXCRCDATAVALIDB
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11249"
wire width 3 input 187 \TXCRCDATAWIDTHA
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11250"
wire width 3 input 188 \TXCRCDATAWIDTHB
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11255"
wire width 64 input 193 \TXCRCINA
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11256"
wire width 64 input 194 \TXCRCINB
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11203"
wire input 141 \TXCRCINITA
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11204"
wire input 142 \TXCRCINITB
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11205"
wire input 143 \TXCRCINTCLKA
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11206"
wire input 144 \TXCRCINTCLKB
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11111"
wire width 32 output 49 \TXCRCOUTA
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11112"
wire width 32 output 50 \TXCRCOUTB
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11207"
wire input 145 \TXCRCPDA
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11208"
wire input 146 \TXCRCPDB
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11209"
wire input 147 \TXCRCRESETA
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11210"
wire input 148 \TXCRCRESETB
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11095"
wire output 33 \TXCYCLELIMITA
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11096"
wire output 34 \TXCYCLELIMITB
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11257"
wire width 64 input 195 \TXDATAA
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11258"
wire width 64 input 196 \TXDATAB
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11243"
wire width 2 input 181 \TXDATAWIDTHA
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11244"
wire width 2 input 182 \TXDATAWIDTHB
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11211"
wire input 149 \TXENC64B66BUSEA
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11212"
wire input 150 \TXENC64B66BUSEB
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11213"
wire input 151 \TXENC8B10BUSEA
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11214"
wire input 152 \TXENC8B10BUSEB
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11215"
wire input 153 \TXENOOBA
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11216"
wire input 154 \TXENOOBB
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11217"
wire input 155 \TXGEARBOX64B66BUSEA
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11218"
wire input 156 \TXGEARBOX64B66BUSEB
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11219"
wire input 157 \TXINHIBITA
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11220"
wire input 158 \TXINHIBITB
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11245"
wire width 2 input 183 \TXINTDATAWIDTHA
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11246"
wire width 2 input 184 \TXINTDATAWIDTHB
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11129"
wire width 8 output 67 \TXKERRA
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11130"
wire width 8 output 68 \TXKERRB
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11097"
wire output 35 \TXLOCKA
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11098"
wire output 36 \TXLOCKB
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11099"
wire output 37 \TXOUTCLK1A
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11100"
wire output 38 \TXOUTCLK1B
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11101"
wire output 39 \TXOUTCLK2A
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11102"
wire output 40 \TXOUTCLK2B
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11103"
wire output 41 \TXPCSHCLKOUTA
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11104"
wire output 42 \TXPCSHCLKOUTB
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11221"
wire input 159 \TXPMARESETA
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11222"
wire input 160 \TXPMARESETB
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11223"
wire input 161 \TXPOLARITYA
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11224"
wire input 162 \TXPOLARITYB
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11225"
wire input 163 \TXRESETA
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11226"
wire input 164 \TXRESETB
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11131"
wire width 8 output 69 \TXRUNDISPA
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11132"
wire width 8 output 70 \TXRUNDISPB
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11227"
wire input 165 \TXSCRAM64B66BUSEA
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11228"
wire input 166 \TXSCRAM64B66BUSEB
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11229"
wire input 167 \TXSYNCA
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11230"
wire input 168 \TXSYNCB
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11231"
wire input 169 \TXUSRCLK2A
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11232"
wire input 170 \TXUSRCLK2B
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11233"
wire input 171 \TXUSRCLKA
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11234"
wire input 172 \TXUSRCLKB
end
attribute \blackbox 1
attribute \cells_not_processed 1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12109"
module \GTHE1_QUAD
parameter \BER_CONST_PTRN0
parameter \BER_CONST_PTRN1
parameter \BUFFER_CONFIG_LANE0
parameter \BUFFER_CONFIG_LANE1
parameter \BUFFER_CONFIG_LANE2
parameter \BUFFER_CONFIG_LANE3
parameter \DFE_TRAIN_CTRL_LANE0
parameter \DFE_TRAIN_CTRL_LANE1
parameter \DFE_TRAIN_CTRL_LANE2
parameter \DFE_TRAIN_CTRL_LANE3
parameter \DLL_CFG0
parameter \DLL_CFG1
parameter \E10GBASEKR_LD_COEFF_UPD_LANE0
parameter \E10GBASEKR_LD_COEFF_UPD_LANE1
parameter \E10GBASEKR_LD_COEFF_UPD_LANE2
parameter \E10GBASEKR_LD_COEFF_UPD_LANE3
parameter \E10GBASEKR_LP_COEFF_UPD_LANE0
parameter \E10GBASEKR_LP_COEFF_UPD_LANE1
parameter \E10GBASEKR_LP_COEFF_UPD_LANE2
parameter \E10GBASEKR_LP_COEFF_UPD_LANE3
parameter \E10GBASEKR_PMA_CTRL_LANE0
parameter \E10GBASEKR_PMA_CTRL_LANE1
parameter \E10GBASEKR_PMA_CTRL_LANE2
parameter \E10GBASEKR_PMA_CTRL_LANE3
parameter \E10GBASEKX_CTRL_LANE0
parameter \E10GBASEKX_CTRL_LANE1
parameter \E10GBASEKX_CTRL_LANE2
parameter \E10GBASEKX_CTRL_LANE3
parameter \E10GBASER_PCS_CFG_LANE0
parameter \E10GBASER_PCS_CFG_LANE1
parameter \E10GBASER_PCS_CFG_LANE2
parameter \E10GBASER_PCS_CFG_LANE3
parameter \E10GBASER_PCS_SEEDA0_LANE0
parameter \E10GBASER_PCS_SEEDA0_LANE1
parameter \E10GBASER_PCS_SEEDA0_LANE2
parameter \E10GBASER_PCS_SEEDA0_LANE3
parameter \E10GBASER_PCS_SEEDA1_LANE0
parameter \E10GBASER_PCS_SEEDA1_LANE1
parameter \E10GBASER_PCS_SEEDA1_LANE2
parameter \E10GBASER_PCS_SEEDA1_LANE3
parameter \E10GBASER_PCS_SEEDA2_LANE0
parameter \E10GBASER_PCS_SEEDA2_LANE1
parameter \E10GBASER_PCS_SEEDA2_LANE2
parameter \E10GBASER_PCS_SEEDA2_LANE3
parameter \E10GBASER_PCS_SEEDA3_LANE0
parameter \E10GBASER_PCS_SEEDA3_LANE1
parameter \E10GBASER_PCS_SEEDA3_LANE2
parameter \E10GBASER_PCS_SEEDA3_LANE3
parameter \E10GBASER_PCS_SEEDB0_LANE0
parameter \E10GBASER_PCS_SEEDB0_LANE1
parameter \E10GBASER_PCS_SEEDB0_LANE2
parameter \E10GBASER_PCS_SEEDB0_LANE3
parameter \E10GBASER_PCS_SEEDB1_LANE0
parameter \E10GBASER_PCS_SEEDB1_LANE1
parameter \E10GBASER_PCS_SEEDB1_LANE2
parameter \E10GBASER_PCS_SEEDB1_LANE3
parameter \E10GBASER_PCS_SEEDB2_LANE0
parameter \E10GBASER_PCS_SEEDB2_LANE1
parameter \E10GBASER_PCS_SEEDB2_LANE2
parameter \E10GBASER_PCS_SEEDB2_LANE3
parameter \E10GBASER_PCS_SEEDB3_LANE0
parameter \E10GBASER_PCS_SEEDB3_LANE1
parameter \E10GBASER_PCS_SEEDB3_LANE2
parameter \E10GBASER_PCS_SEEDB3_LANE3
parameter \E10GBASER_PCS_TEST_CTRL_LANE0
parameter \E10GBASER_PCS_TEST_CTRL_LANE1
parameter \E10GBASER_PCS_TEST_CTRL_LANE2
parameter \E10GBASER_PCS_TEST_CTRL_LANE3
parameter \E10GBASEX_PCS_TSTCTRL_LANE0
parameter \E10GBASEX_PCS_TSTCTRL_LANE1
parameter \E10GBASEX_PCS_TSTCTRL_LANE2
parameter \E10GBASEX_PCS_TSTCTRL_LANE3
parameter \GLBL0_NOISE_CTRL
parameter \GLBL_AMON_SEL
parameter \GLBL_DMON_SEL
parameter \GLBL_PWR_CTRL
parameter \GTH_CFG_PWRUP_LANE0
parameter \GTH_CFG_PWRUP_LANE1
parameter \GTH_CFG_PWRUP_LANE2
parameter \GTH_CFG_PWRUP_LANE3
parameter \LANE_AMON_SEL
parameter \LANE_DMON_SEL
parameter \LANE_LNK_CFGOVRD
parameter \LANE_PWR_CTRL_LANE0
parameter \LANE_PWR_CTRL_LANE1
parameter \LANE_PWR_CTRL_LANE2
parameter \LANE_PWR_CTRL_LANE3
parameter \LNK_TRN_CFG_LANE0
parameter \LNK_TRN_CFG_LANE1
parameter \LNK_TRN_CFG_LANE2
parameter \LNK_TRN_CFG_LANE3
parameter \LNK_TRN_COEFF_REQ_LANE0
parameter \LNK_TRN_COEFF_REQ_LANE1
parameter \LNK_TRN_COEFF_REQ_LANE2
parameter \LNK_TRN_COEFF_REQ_LANE3
parameter \MISC_CFG
parameter \MODE_CFG1
parameter \MODE_CFG2
parameter \MODE_CFG3
parameter \MODE_CFG4
parameter \MODE_CFG5
parameter \MODE_CFG6
parameter \MODE_CFG7
parameter \PCS_ABILITY_LANE0
parameter \PCS_ABILITY_LANE1
parameter \PCS_ABILITY_LANE2
parameter \PCS_ABILITY_LANE3
parameter \PCS_CTRL1_LANE0
parameter \PCS_CTRL1_LANE1
parameter \PCS_CTRL1_LANE2
parameter \PCS_CTRL1_LANE3
parameter \PCS_CTRL2_LANE0
parameter \PCS_CTRL2_LANE1
parameter \PCS_CTRL2_LANE2
parameter \PCS_CTRL2_LANE3
parameter \PCS_MISC_CFG_0_LANE0
parameter \PCS_MISC_CFG_0_LANE1
parameter \PCS_MISC_CFG_0_LANE2
parameter \PCS_MISC_CFG_0_LANE3
parameter \PCS_MISC_CFG_1_LANE0
parameter \PCS_MISC_CFG_1_LANE1
parameter \PCS_MISC_CFG_1_LANE2
parameter \PCS_MISC_CFG_1_LANE3
parameter \PCS_MODE_LANE0
parameter \PCS_MODE_LANE1
parameter \PCS_MODE_LANE2
parameter \PCS_MODE_LANE3
parameter \PCS_RESET_1_LANE0
parameter \PCS_RESET_1_LANE1
parameter \PCS_RESET_1_LANE2
parameter \PCS_RESET_1_LANE3
parameter \PCS_RESET_LANE0
parameter \PCS_RESET_LANE1
parameter \PCS_RESET_LANE2
parameter \PCS_RESET_LANE3
parameter \PCS_TYPE_LANE0
parameter \PCS_TYPE_LANE1
parameter \PCS_TYPE_LANE2
parameter \PCS_TYPE_LANE3
parameter \PLL_CFG0
parameter \PLL_CFG1
parameter \PLL_CFG2
parameter \PMA_CTRL1_LANE0
parameter \PMA_CTRL1_LANE1
parameter \PMA_CTRL1_LANE2
parameter \PMA_CTRL1_LANE3
parameter \PMA_CTRL2_LANE0
parameter \PMA_CTRL2_LANE1
parameter \PMA_CTRL2_LANE2
parameter \PMA_CTRL2_LANE3
parameter \PMA_LPBK_CTRL_LANE0
parameter \PMA_LPBK_CTRL_LANE1
parameter \PMA_LPBK_CTRL_LANE2
parameter \PMA_LPBK_CTRL_LANE3
parameter \PRBS_BER_CFG0_LANE0
parameter \PRBS_BER_CFG0_LANE1
parameter \PRBS_BER_CFG0_LANE2
parameter \PRBS_BER_CFG0_LANE3
parameter \PRBS_BER_CFG1_LANE0
parameter \PRBS_BER_CFG1_LANE1
parameter \PRBS_BER_CFG1_LANE2
parameter \PRBS_BER_CFG1_LANE3
parameter \PRBS_CFG_LANE0
parameter \PRBS_CFG_LANE1
parameter \PRBS_CFG_LANE2
parameter \PRBS_CFG_LANE3
parameter \PTRN_CFG0_LSB
parameter \PTRN_CFG0_MSB
parameter \PTRN_LEN_CFG
parameter \PWRUP_DLY
parameter \RX_AEQ_VAL0_LANE0
parameter \RX_AEQ_VAL0_LANE1
parameter \RX_AEQ_VAL0_LANE2
parameter \RX_AEQ_VAL0_LANE3
parameter \RX_AEQ_VAL1_LANE0
parameter \RX_AEQ_VAL1_LANE1
parameter \RX_AEQ_VAL1_LANE2
parameter \RX_AEQ_VAL1_LANE3
parameter \RX_AGC_CTRL_LANE0
parameter \RX_AGC_CTRL_LANE1
parameter \RX_AGC_CTRL_LANE2
parameter \RX_AGC_CTRL_LANE3
parameter \RX_CDR_CTRL0_LANE0
parameter \RX_CDR_CTRL0_LANE1
parameter \RX_CDR_CTRL0_LANE2
parameter \RX_CDR_CTRL0_LANE3
parameter \RX_CDR_CTRL1_LANE0
parameter \RX_CDR_CTRL1_LANE1
parameter \RX_CDR_CTRL1_LANE2
parameter \RX_CDR_CTRL1_LANE3
parameter \RX_CDR_CTRL2_LANE0
parameter \RX_CDR_CTRL2_LANE1
parameter \RX_CDR_CTRL2_LANE2
parameter \RX_CDR_CTRL2_LANE3
parameter \RX_CFG0_LANE0
parameter \RX_CFG0_LANE1
parameter \RX_CFG0_LANE2
parameter \RX_CFG0_LANE3
parameter \RX_CFG1_LANE0
parameter \RX_CFG1_LANE1
parameter \RX_CFG1_LANE2
parameter \RX_CFG1_LANE3
parameter \RX_CFG2_LANE0
parameter \RX_CFG2_LANE1
parameter \RX_CFG2_LANE2
parameter \RX_CFG2_LANE3
parameter \RX_CTLE_CTRL_LANE0
parameter \RX_CTLE_CTRL_LANE1
parameter \RX_CTLE_CTRL_LANE2
parameter \RX_CTLE_CTRL_LANE3
parameter \RX_CTRL_OVRD_LANE0
parameter \RX_CTRL_OVRD_LANE1
parameter \RX_CTRL_OVRD_LANE2
parameter \RX_CTRL_OVRD_LANE3
parameter \RX_FABRIC_WIDTH0
parameter \RX_FABRIC_WIDTH1
parameter \RX_FABRIC_WIDTH2
parameter \RX_FABRIC_WIDTH3
parameter \RX_LOOP_CTRL_LANE0
parameter \RX_LOOP_CTRL_LANE1
parameter \RX_LOOP_CTRL_LANE2
parameter \RX_LOOP_CTRL_LANE3
parameter \RX_MVAL0_LANE0
parameter \RX_MVAL0_LANE1
parameter \RX_MVAL0_LANE2
parameter \RX_MVAL0_LANE3
parameter \RX_MVAL1_LANE0
parameter \RX_MVAL1_LANE1
parameter \RX_MVAL1_LANE2
parameter \RX_MVAL1_LANE3
parameter \RX_P0S_CTRL
parameter \RX_P0_CTRL
parameter \RX_P1_CTRL
parameter \RX_P2_CTRL
parameter \RX_PI_CTRL0
parameter \RX_PI_CTRL1
parameter \SIM_GTHRESET_SPEEDUP
parameter \SIM_VERSION
parameter \SLICE_CFG
parameter \SLICE_NOISE_CTRL_0_LANE01
parameter \SLICE_NOISE_CTRL_0_LANE23
parameter \SLICE_NOISE_CTRL_1_LANE01
parameter \SLICE_NOISE_CTRL_1_LANE23
parameter \SLICE_NOISE_CTRL_2_LANE01
parameter \SLICE_NOISE_CTRL_2_LANE23
parameter \SLICE_TX_RESET_LANE01
parameter \SLICE_TX_RESET_LANE23
parameter \TERM_CTRL_LANE0
parameter \TERM_CTRL_LANE1
parameter \TERM_CTRL_LANE2
parameter \TERM_CTRL_LANE3
parameter \TX_CFG0_LANE0
parameter \TX_CFG0_LANE1
parameter \TX_CFG0_LANE2
parameter \TX_CFG0_LANE3
parameter \TX_CFG1_LANE0
parameter \TX_CFG1_LANE1
parameter \TX_CFG1_LANE2
parameter \TX_CFG1_LANE3
parameter \TX_CFG2_LANE0
parameter \TX_CFG2_LANE1
parameter \TX_CFG2_LANE2
parameter \TX_CFG2_LANE3
parameter \TX_CLK_SEL0_LANE0
parameter \TX_CLK_SEL0_LANE1
parameter \TX_CLK_SEL0_LANE2
parameter \TX_CLK_SEL0_LANE3
parameter \TX_CLK_SEL1_LANE0
parameter \TX_CLK_SEL1_LANE1
parameter \TX_CLK_SEL1_LANE2
parameter \TX_CLK_SEL1_LANE3
parameter \TX_DISABLE_LANE0
parameter \TX_DISABLE_LANE1
parameter \TX_DISABLE_LANE2
parameter \TX_DISABLE_LANE3
parameter \TX_FABRIC_WIDTH0
parameter \TX_FABRIC_WIDTH1
parameter \TX_FABRIC_WIDTH2
parameter \TX_FABRIC_WIDTH3
parameter \TX_P0P0S_CTRL
parameter \TX_P1P2_CTRL
parameter \TX_PREEMPH_LANE0
parameter \TX_PREEMPH_LANE1
parameter \TX_PREEMPH_LANE2
parameter \TX_PREEMPH_LANE3
parameter \TX_PWR_RATE_OVRD_LANE0
parameter \TX_PWR_RATE_OVRD_LANE1
parameter \TX_PWR_RATE_OVRD_LANE2
parameter \TX_PWR_RATE_OVRD_LANE3
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12531"
wire width 16 input 133 \DADDR
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12471"
wire input 73 \DCLK
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12472"
wire input 74 \DEN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12473"
wire input 75 \DFETRAINCTRL0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12474"
wire input 76 \DFETRAINCTRL1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12475"
wire input 77 \DFETRAINCTRL2
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12476"
wire input 78 \DFETRAINCTRL3
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12532"
wire width 16 input 134 \DI
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12477"
wire input 79 \DISABLEDRP
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12399"
wire output 1 \DRDY
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12449"
wire width 16 output 51 \DRPDO
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12478"
wire input 80 \DWE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12479"
wire input 81 \GTHINIT
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12400"
wire output 2 \GTHINITDONE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12480"
wire input 82 \GTHRESET
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12481"
wire input 83 \GTHX2LANE01
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12482"
wire input 84 \GTHX2LANE23
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12483"
wire input 85 \GTHX4LANE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12560"
wire width 4 input 162 \MGMTPCSLANESEL
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12561"
wire width 5 input 163 \MGMTPCSMMDADDR
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12401"
wire output 3 \MGMTPCSRDACK
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12450"
wire width 16 output 52 \MGMTPCSRDDATA
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12533"
wire width 16 input 135 \MGMTPCSREGADDR
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12484"
wire input 86 \MGMTPCSREGRD
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12485"
wire input 87 \MGMTPCSREGWR
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12534"
wire width 16 input 136 \MGMTPCSWRDATA
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12562"
wire width 6 input 164 \PLLPCSCLKDIV
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12551"
wire width 3 input 153 \PLLREFCLKSEL
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12486"
wire input 88 \POWERDOWN0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12487"
wire input 89 \POWERDOWN1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12488"
wire input 90 \POWERDOWN2
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12489"
wire input 91 \POWERDOWN3
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12490"
wire input 92 \REFCLK
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12491"
wire input 93 \RXBUFRESET0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12492"
wire input 94 \RXBUFRESET1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12493"
wire input 95 \RXBUFRESET2
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12494"
wire input 96 \RXBUFRESET3
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12455"
wire width 8 output 57 \RXCODEERR0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12456"
wire width 8 output 58 \RXCODEERR1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12457"
wire width 8 output 59 \RXCODEERR2
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12458"
wire width 8 output 60 \RXCODEERR3
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12459"
wire width 8 output 61 \RXCTRL0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12460"
wire width 8 output 62 \RXCTRL1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12461"
wire width 8 output 63 \RXCTRL2
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12462"
wire width 8 output 64 \RXCTRL3
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12402"
wire output 4 \RXCTRLACK0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12403"
wire output 5 \RXCTRLACK1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12404"
wire output 6 \RXCTRLACK2
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12405"
wire output 7 \RXCTRLACK3
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12451"
wire width 64 output 53 \RXDATA0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12452"
wire width 64 output 54 \RXDATA1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12453"
wire width 64 output 55 \RXDATA2
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12454"
wire width 64 output 56 \RXDATA3
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12406"
wire output 8 \RXDATATAP0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12407"
wire output 9 \RXDATATAP1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12408"
wire output 10 \RXDATATAP2
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12409"
wire output 11 \RXDATATAP3
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12463"
wire width 8 output 65 \RXDISPERR0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12464"
wire width 8 output 66 \RXDISPERR1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12465"
wire width 8 output 67 \RXDISPERR2
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12466"
wire width 8 output 68 \RXDISPERR3
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12495"
wire input 97 \RXENCOMMADET0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12496"
wire input 98 \RXENCOMMADET1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12497"
wire input 99 \RXENCOMMADET2
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12498"
wire input 100 \RXENCOMMADET3
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12499"
wire input 101 \RXN0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12500"
wire input 102 \RXN1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12501"
wire input 103 \RXN2
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12502"
wire input 104 \RXN3
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12503"
wire input 105 \RXP0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12504"
wire input 106 \RXP1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12505"
wire input 107 \RXP2
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12506"
wire input 108 \RXP3
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12410"
wire output 12 \RXPCSCLKSMPL0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12411"
wire output 13 \RXPCSCLKSMPL1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12412"
wire output 14 \RXPCSCLKSMPL2
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12413"
wire output 15 \RXPCSCLKSMPL3
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12507"
wire input 109 \RXPOLARITY0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12508"
wire input 110 \RXPOLARITY1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12509"
wire input 111 \RXPOLARITY2
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12510"
wire input 112 \RXPOLARITY3
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12535"
wire width 2 input 137 \RXPOWERDOWN0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12536"
wire width 2 input 138 \RXPOWERDOWN1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12537"
wire width 2 input 139 \RXPOWERDOWN2
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12538"
wire width 2 input 140 \RXPOWERDOWN3
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12539"
wire width 2 input 141 \RXRATE0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12540"
wire width 2 input 142 \RXRATE1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12541"
wire width 2 input 143 \RXRATE2
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12542"
wire width 2 input 144 \RXRATE3
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12511"
wire input 113 \RXSLIP0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12512"
wire input 114 \RXSLIP1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12513"
wire input 115 \RXSLIP2
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12514"
wire input 116 \RXSLIP3
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12515"
wire input 117 \RXUSERCLKIN0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12516"
wire input 118 \RXUSERCLKIN1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12517"
wire input 119 \RXUSERCLKIN2
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12518"
wire input 120 \RXUSERCLKIN3
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12414"
wire output 16 \RXUSERCLKOUT0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12415"
wire output 17 \RXUSERCLKOUT1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12416"
wire output 18 \RXUSERCLKOUT2
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12417"
wire output 19 \RXUSERCLKOUT3
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12467"
wire width 8 output 69 \RXVALID0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12468"
wire width 8 output 70 \RXVALID1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12469"
wire width 8 output 71 \RXVALID2
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12470"
wire width 8 output 72 \RXVALID3
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12552"
wire width 3 input 154 \SAMPLERATE0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12553"
wire width 3 input 155 \SAMPLERATE1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12554"
wire width 3 input 156 \SAMPLERATE2
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12555"
wire width 3 input 157 \SAMPLERATE3
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12418"
wire output 20 \TSTPATH
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12419"
wire output 21 \TSTREFCLKFAB
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12420"
wire output 22 \TSTREFCLKOUT
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12519"
wire input 121 \TXBUFRESET0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12520"
wire input 122 \TXBUFRESET1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12521"
wire input 123 \TXBUFRESET2
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12522"
wire input 124 \TXBUFRESET3
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12567"
wire width 8 input 169 \TXCTRL0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12568"
wire width 8 input 170 \TXCTRL1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12569"
wire width 8 input 171 \TXCTRL2
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12570"
wire width 8 input 172 \TXCTRL3
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12421"
wire output 23 \TXCTRLACK0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12422"
wire output 24 \TXCTRLACK1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12423"
wire output 25 \TXCTRLACK2
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12424"
wire output 26 \TXCTRLACK3
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12563"
wire width 64 input 165 \TXDATA0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12564"
wire width 64 input 166 \TXDATA1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12565"
wire width 64 input 167 \TXDATA2
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12566"
wire width 64 input 168 \TXDATA3
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12571"
wire width 8 input 173 \TXDATAMSB0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12572"
wire width 8 input 174 \TXDATAMSB1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12573"
wire width 8 input 175 \TXDATAMSB2
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12574"
wire width 8 input 176 \TXDATAMSB3
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12425"
wire output 27 \TXDATATAP10
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12426"
wire output 28 \TXDATATAP11
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12427"
wire output 29 \TXDATATAP12
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12428"
wire output 30 \TXDATATAP13
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12429"
wire output 31 \TXDATATAP20
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12430"
wire output 32 \TXDATATAP21
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12431"
wire output 33 \TXDATATAP22
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12432"
wire output 34 \TXDATATAP23
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12523"
wire input 125 \TXDEEMPH0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12524"
wire input 126 \TXDEEMPH1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12525"
wire input 127 \TXDEEMPH2
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12526"
wire input 128 \TXDEEMPH3
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12556"
wire width 3 input 158 \TXMARGIN0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12557"
wire width 3 input 159 \TXMARGIN1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12558"
wire width 3 input 160 \TXMARGIN2
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12559"
wire width 3 input 161 \TXMARGIN3
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12433"
wire output 35 \TXN0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12434"
wire output 36 \TXN1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12435"
wire output 37 \TXN2
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12436"
wire output 38 \TXN3
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12437"
wire output 39 \TXP0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12438"
wire output 40 \TXP1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12439"
wire output 41 \TXP2
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12440"
wire output 42 \TXP3
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12441"
wire output 43 \TXPCSCLKSMPL0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12442"
wire output 44 \TXPCSCLKSMPL1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12443"
wire output 45 \TXPCSCLKSMPL2
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12444"
wire output 46 \TXPCSCLKSMPL3
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12543"
wire width 2 input 145 \TXPOWERDOWN0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12544"
wire width 2 input 146 \TXPOWERDOWN1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12545"
wire width 2 input 147 \TXPOWERDOWN2
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12546"
wire width 2 input 148 \TXPOWERDOWN3
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12547"
wire width 2 input 149 \TXRATE0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12548"
wire width 2 input 150 \TXRATE1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12549"
wire width 2 input 151 \TXRATE2
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12550"
wire width 2 input 152 \TXRATE3
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12527"
wire input 129 \TXUSERCLKIN0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12528"
wire input 130 \TXUSERCLKIN1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12529"
wire input 131 \TXUSERCLKIN2
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12530"
wire input 132 \TXUSERCLKIN3
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12445"
wire output 47 \TXUSERCLKOUT0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12446"
wire output 48 \TXUSERCLKOUT1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12447"
wire output 49 \TXUSERCLKOUT2
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12448"
wire output 50 \TXUSERCLKOUT3
end
attribute \blackbox 1
attribute \cells_not_processed 1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12950"
module \GTHE2_CHANNEL
parameter \ACJTAG_DEBUG_MODE
parameter \ACJTAG_MODE
parameter \ACJTAG_RESET
parameter \ADAPT_CFG0
parameter \ALIGN_COMMA_DOUBLE
parameter \ALIGN_COMMA_ENABLE
parameter \ALIGN_COMMA_WORD
parameter \ALIGN_MCOMMA_DET
parameter \ALIGN_MCOMMA_VALUE
parameter \ALIGN_PCOMMA_DET
parameter \ALIGN_PCOMMA_VALUE
parameter \A_RXOSCALRESET
parameter \CBCC_DATA_SOURCE_SEL
parameter \CFOK_CFG
parameter \CFOK_CFG2
parameter \CFOK_CFG3
parameter \CHAN_BOND_KEEP_ALIGN
parameter \CHAN_BOND_MAX_SKEW
parameter \CHAN_BOND_SEQ_1_1
parameter \CHAN_BOND_SEQ_1_2
parameter \CHAN_BOND_SEQ_1_3
parameter \CHAN_BOND_SEQ_1_4
parameter \CHAN_BOND_SEQ_1_ENABLE
parameter \CHAN_BOND_SEQ_2_1
parameter \CHAN_BOND_SEQ_2_2
parameter \CHAN_BOND_SEQ_2_3
parameter \CHAN_BOND_SEQ_2_4
parameter \CHAN_BOND_SEQ_2_ENABLE
parameter \CHAN_BOND_SEQ_2_USE
parameter \CHAN_BOND_SEQ_LEN
parameter \CLK_CORRECT_USE
parameter \CLK_COR_KEEP_IDLE
parameter \CLK_COR_MAX_LAT
parameter \CLK_COR_MIN_LAT
parameter \CLK_COR_PRECEDENCE
parameter \CLK_COR_REPEAT_WAIT
parameter \CLK_COR_SEQ_1_1
parameter \CLK_COR_SEQ_1_2
parameter \CLK_COR_SEQ_1_3
parameter \CLK_COR_SEQ_1_4
parameter \CLK_COR_SEQ_1_ENABLE
parameter \CLK_COR_SEQ_2_1
parameter \CLK_COR_SEQ_2_2
parameter \CLK_COR_SEQ_2_3
parameter \CLK_COR_SEQ_2_4
parameter \CLK_COR_SEQ_2_ENABLE
parameter \CLK_COR_SEQ_2_USE
parameter \CLK_COR_SEQ_LEN
parameter \CPLL_CFG
parameter \CPLL_FBDIV
parameter \CPLL_FBDIV_45
parameter \CPLL_INIT_CFG
parameter \CPLL_LOCK_CFG
parameter \CPLL_REFCLK_DIV
parameter \DEC_MCOMMA_DETECT
parameter \DEC_PCOMMA_DETECT
parameter \DEC_VALID_COMMA_ONLY
parameter \DMONITOR_CFG
parameter \ES_CLK_PHASE_SEL
parameter \ES_CONTROL
parameter \ES_ERRDET_EN
parameter \ES_EYE_SCAN_EN
parameter \ES_HORZ_OFFSET
parameter \ES_PMA_CFG
parameter \ES_PRESCALE
parameter \ES_QUALIFIER
parameter \ES_QUAL_MASK
parameter \ES_SDATA_MASK
parameter \ES_VERT_OFFSET
parameter \FTS_DESKEW_SEQ_ENABLE
parameter \FTS_LANE_DESKEW_CFG
parameter \FTS_LANE_DESKEW_EN
parameter \GEARBOX_MODE
parameter \IS_CLKRSVD0_INVERTED
parameter \IS_CLKRSVD1_INVERTED
parameter \IS_CPLLLOCKDETCLK_INVERTED
parameter \IS_DMONITORCLK_INVERTED
parameter \IS_DRPCLK_INVERTED
parameter \IS_GTGREFCLK_INVERTED
parameter \IS_RXUSRCLK2_INVERTED
parameter \IS_RXUSRCLK_INVERTED
parameter \IS_SIGVALIDCLK_INVERTED
parameter \IS_TXPHDLYTSTCLK_INVERTED
parameter \IS_TXUSRCLK2_INVERTED
parameter \IS_TXUSRCLK_INVERTED
parameter \LOOPBACK_CFG
parameter \OUTREFCLK_SEL_INV
parameter \PCS_PCIE_EN
parameter \PCS_RSVD_ATTR
parameter \PD_TRANS_TIME_FROM_P2
parameter \PD_TRANS_TIME_NONE_P2
parameter \PD_TRANS_TIME_TO_P2
parameter \PMA_RSV
parameter \PMA_RSV2
parameter \PMA_RSV3
parameter \PMA_RSV4
parameter \PMA_RSV5
parameter \RESET_POWERSAVE_DISABLE
parameter \RXBUFRESET_TIME
parameter \RXBUF_ADDR_MODE
parameter \RXBUF_EIDLE_HI_CNT
parameter \RXBUF_EIDLE_LO_CNT
parameter \RXBUF_EN
parameter \RXBUF_RESET_ON_CB_CHANGE
parameter \RXBUF_RESET_ON_COMMAALIGN
parameter \RXBUF_RESET_ON_EIDLE
parameter \RXBUF_RESET_ON_RATE_CHANGE
parameter \RXBUF_THRESH_OVFLW
parameter \RXBUF_THRESH_OVRD
parameter \RXBUF_THRESH_UNDFLW
parameter \RXCDRFREQRESET_TIME
parameter \RXCDRPHRESET_TIME
parameter \RXCDR_CFG
parameter \RXCDR_FR_RESET_ON_EIDLE
parameter \RXCDR_HOLD_DURING_EIDLE
parameter \RXCDR_LOCK_CFG
parameter \RXCDR_PH_RESET_ON_EIDLE
parameter \RXDFELPMRESET_TIME
parameter \RXDLY_CFG
parameter \RXDLY_LCFG
parameter \RXDLY_TAP_CFG
parameter \RXGEARBOX_EN
parameter \RXISCANRESET_TIME
parameter \RXLPM_HF_CFG
parameter \RXLPM_LF_CFG
parameter \RXOOB_CFG
parameter \RXOOB_CLK_CFG
parameter \RXOSCALRESET_TIME
parameter \RXOSCALRESET_TIMEOUT
parameter \RXOUT_DIV
parameter \RXPCSRESET_TIME
parameter \RXPHDLY_CFG
parameter \RXPH_CFG
parameter \RXPH_MONITOR_SEL
parameter \RXPI_CFG0
parameter \RXPI_CFG1
parameter \RXPI_CFG2
parameter \RXPI_CFG3
parameter \RXPI_CFG4
parameter \RXPI_CFG5
parameter \RXPI_CFG6
parameter \RXPMARESET_TIME
parameter \RXPRBS_ERR_LOOPBACK
parameter \RXSLIDE_AUTO_WAIT
parameter \RXSLIDE_MODE
parameter \RXSYNC_MULTILANE
parameter \RXSYNC_OVRD
parameter \RXSYNC_SKIP_DA
parameter \RX_BIAS_CFG
parameter \RX_BUFFER_CFG
parameter \RX_CLK25_DIV
parameter \RX_CLKMUX_PD
parameter \RX_CM_SEL
parameter \RX_CM_TRIM
parameter \RX_DATA_WIDTH
parameter \RX_DDI_SEL
parameter \RX_DEBUG_CFG
parameter \RX_DEFER_RESET_BUF_EN
parameter \RX_DFELPM_CFG0
parameter \RX_DFELPM_CFG1
parameter \RX_DFELPM_KLKH_AGC_STUP_EN
parameter \RX_DFE_AGC_CFG0
parameter \RX_DFE_AGC_CFG1
parameter \RX_DFE_AGC_CFG2
parameter \RX_DFE_AGC_OVRDEN
parameter \RX_DFE_GAIN_CFG
parameter \RX_DFE_H2_CFG
parameter \RX_DFE_H3_CFG
parameter \RX_DFE_H4_CFG
parameter \RX_DFE_H5_CFG
parameter \RX_DFE_H6_CFG
parameter \RX_DFE_H7_CFG
parameter \RX_DFE_KL_CFG
parameter \RX_DFE_KL_LPM_KH_CFG0
parameter \RX_DFE_KL_LPM_KH_CFG1
parameter \RX_DFE_KL_LPM_KH_CFG2
parameter \RX_DFE_KL_LPM_KH_OVRDEN
parameter \RX_DFE_KL_LPM_KL_CFG0
parameter \RX_DFE_KL_LPM_KL_CFG1
parameter \RX_DFE_KL_LPM_KL_CFG2
parameter \RX_DFE_KL_LPM_KL_OVRDEN
parameter \RX_DFE_LPM_CFG
parameter \RX_DFE_LPM_HOLD_DURING_EIDLE
parameter \RX_DFE_ST_CFG
parameter \RX_DFE_UT_CFG
parameter \RX_DFE_VP_CFG
parameter \RX_DISPERR_SEQ_MATCH
parameter \RX_INT_DATAWIDTH
parameter \RX_OS_CFG
parameter \RX_SIG_VALID_DLY
parameter \RX_XCLK_SEL
parameter \SAS_MAX_COM
parameter \SAS_MIN_COM
parameter \SATA_BURST_SEQ_LEN
parameter \SATA_BURST_VAL
parameter \SATA_CPLL_CFG
parameter \SATA_EIDLE_VAL
parameter \SATA_MAX_BURST
parameter \SATA_MAX_INIT
parameter \SATA_MAX_WAKE
parameter \SATA_MIN_BURST
parameter \SATA_MIN_INIT
parameter \SATA_MIN_WAKE
parameter \SHOW_REALIGN_COMMA
parameter \SIM_CPLLREFCLK_SEL
parameter \SIM_RECEIVER_DETECT_PASS
parameter \SIM_RESET_SPEEDUP
parameter \SIM_TX_EIDLE_DRIVE_LEVEL
parameter \SIM_VERSION
parameter \TERM_RCAL_CFG
parameter \TERM_RCAL_OVRD
parameter \TRANS_TIME_RATE
parameter \TST_RSV
parameter \TXBUF_EN
parameter \TXBUF_RESET_ON_RATE_CHANGE
parameter \TXDLY_CFG
parameter \TXDLY_LCFG
parameter \TXDLY_TAP_CFG
parameter \TXGEARBOX_EN
parameter \TXOOB_CFG
parameter \TXOUT_DIV
parameter \TXPCSRESET_TIME
parameter \TXPHDLY_CFG
parameter \TXPH_CFG
parameter \TXPH_MONITOR_SEL
parameter \TXPI_CFG0
parameter \TXPI_CFG1
parameter \TXPI_CFG2
parameter \TXPI_CFG3
parameter \TXPI_CFG4
parameter \TXPI_CFG5
parameter \TXPI_GREY_SEL
parameter \TXPI_INVSTROBE_SEL
parameter \TXPI_PPMCLK_SEL
parameter \TXPI_PPM_CFG
parameter \TXPI_SYNFREQ_PPM
parameter \TXPMARESET_TIME
parameter \TXSYNC_MULTILANE
parameter \TXSYNC_OVRD
parameter \TXSYNC_SKIP_DA
parameter \TX_CLK25_DIV
parameter \TX_CLKMUX_PD
parameter \TX_DATA_WIDTH
parameter \TX_DEEMPH0
parameter \TX_DEEMPH1
parameter \TX_DRIVE_MODE
parameter \TX_EIDLE_ASSERT_DELAY
parameter \TX_EIDLE_DEASSERT_DELAY
parameter \TX_INT_DATAWIDTH
parameter \TX_LOOPBACK_DRIVE_HIZ
parameter \TX_MAINCURSOR_SEL
parameter \TX_MARGIN_FULL_0
parameter \TX_MARGIN_FULL_1
parameter \TX_MARGIN_FULL_2
parameter \TX_MARGIN_FULL_3
parameter \TX_MARGIN_FULL_4
parameter \TX_MARGIN_LOW_0
parameter \TX_MARGIN_LOW_1
parameter \TX_MARGIN_LOW_2
parameter \TX_MARGIN_LOW_3
parameter \TX_MARGIN_LOW_4
parameter \TX_QPI_STATUS_EN
parameter \TX_RXDETECT_CFG
parameter \TX_RXDETECT_PRECHARGE_TIME
parameter \TX_RXDETECT_REF
parameter \TX_XCLK_SEL
parameter \UCODEER_CLR
parameter \USE_PCS_CLK_PHASE_SEL
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13296"
wire input 78 \CFGRESET
attribute \invertible_pin "IS_CLKRSVD0_INVERTED"
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13298"
wire input 79 \CLKRSVD0
attribute \invertible_pin "IS_CLKRSVD1_INVERTED"
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13300"
wire input 80 \CLKRSVD1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13219"
wire output 1 \CPLLFBCLKLOST
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13220"
wire output 2 \CPLLLOCK
attribute \invertible_pin "IS_CPLLLOCKDETCLK_INVERTED"
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13302"
wire input 81 \CPLLLOCKDETCLK
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13303"
wire input 82 \CPLLLOCKEN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13304"
wire input 83 \CPLLPD
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13221"
wire output 3 \CPLLREFCLKLOST
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13479"
wire width 3 input 249 \CPLLREFCLKSEL
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13305"
wire input 84 \CPLLRESET
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13306"
wire input 85 \DMONFIFORESET
attribute \invertible_pin "IS_DMONITORCLK_INVERTED"
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13308"
wire input 86 \DMONITORCLK
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13276"
wire width 15 output 58 \DMONITOROUT
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13510"
wire width 9 input 280 \DRPADDR
attribute \invertible_pin "IS_DRPCLK_INVERTED"
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13310"
wire input 87 \DRPCLK
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13469"
wire width 16 input 239 \DRPDI
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13277"
wire width 16 output 59 \DRPDO
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13311"
wire input 88 \DRPEN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13222"
wire output 4 \DRPRDY
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13312"
wire input 89 \DRPWE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13223"
wire output 5 \EYESCANDATAERROR
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13313"
wire input 90 \EYESCANMODE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13314"
wire input 91 \EYESCANRESET
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13315"
wire input 92 \EYESCANTRIGGER
attribute \invertible_pin "IS_GTGREFCLK_INVERTED"
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13317"
wire input 93 \GTGREFCLK
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13318"
wire input 94 \GTHRXN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13319"
wire input 95 \GTHRXP
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13224"
wire output 6 \GTHTXN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13225"
wire output 7 \GTHTXP
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13320"
wire input 96 \GTNORTHREFCLK0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13321"
wire input 97 \GTNORTHREFCLK1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13322"
wire input 98 \GTREFCLK0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13323"
wire input 99 \GTREFCLK1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13226"
wire output 8 \GTREFCLKMONITOR
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13324"
wire input 100 \GTRESETSEL
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13470"
wire width 16 input 240 \GTRSVD
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13325"
wire input 101 \GTRXRESET
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13326"
wire input 102 \GTSOUTHREFCLK0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13327"
wire input 103 \GTSOUTHREFCLK1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13328"
wire input 104 \GTTXRESET
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13480"
wire width 3 input 250 \LOOPBACK
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13471"
wire width 16 input 241 \PCSRSVDIN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13494"
wire width 5 input 264 \PCSRSVDIN2
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13278"
wire width 16 output 60 \PCSRSVDOUT
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13227"
wire output 9 \PHYSTATUS
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13495"
wire width 5 input 265 \PMARSVDIN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13329"
wire input 105 \QPLLCLK
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13330"
wire input 106 \QPLLREFCLK
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13331"
wire input 107 \RESETOVRD
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13228"
wire output 10 \RSOSINTDONE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13332"
wire input 108 \RX8B10BEN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13468"
wire width 14 input 238 \RXADAPTSELTEST
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13333"
wire input 109 \RXBUFRESET
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13284"
wire width 3 output 66 \RXBUFSTATUS
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13229"
wire output 11 \RXBYTEISALIGNED
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13230"
wire output 12 \RXBYTEREALIGN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13334"
wire input 110 \RXCDRFREQRESET
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13335"
wire input 111 \RXCDRHOLD
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13231"
wire output 13 \RXCDRLOCK
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13336"
wire input 112 \RXCDROVRDEN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13337"
wire input 113 \RXCDRRESET
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13338"
wire input 114 \RXCDRRESETRSV
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13232"
wire output 14 \RXCHANBONDSEQ
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13233"
wire output 15 \RXCHANISALIGNED
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13234"
wire output 16 \RXCHANREALIGN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13292"
wire width 8 output 74 \RXCHARISCOMMA
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13293"
wire width 8 output 75 \RXCHARISK
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13339"
wire input 115 \RXCHBONDEN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13496"
wire width 5 input 266 \RXCHBONDI
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13481"
wire width 3 input 251 \RXCHBONDLEVEL
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13340"
wire input 116 \RXCHBONDMASTER
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13286"
wire width 5 output 68 \RXCHBONDO
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13341"
wire input 117 \RXCHBONDSLAVE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13279"
wire width 2 output 61 \RXCLKCORCNT
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13235"
wire output 17 \RXCOMINITDET
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13236"
wire output 18 \RXCOMMADET
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13342"
wire input 118 \RXCOMMADETEN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13237"
wire output 19 \RXCOMSASDET
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13238"
wire output 20 \RXCOMWAKEDET
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13290"
wire width 64 output 72 \RXDATA
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13280"
wire width 2 output 62 \RXDATAVALID
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13343"
wire input 119 \RXDDIEN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13344"
wire input 120 \RXDFEAGCHOLD
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13345"
wire input 121 \RXDFEAGCOVRDEN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13497"
wire width 5 input 267 \RXDFEAGCTRL
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13346"
wire input 122 \RXDFECM1EN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13347"
wire input 123 \RXDFELFHOLD
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13348"
wire input 124 \RXDFELFOVRDEN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13349"
wire input 125 \RXDFELPMRESET
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13498"
wire width 5 input 268 \RXDFESLIDETAP
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13350"
wire input 126 \RXDFESLIDETAPADAPTEN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13351"
wire input 127 \RXDFESLIDETAPHOLD
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13502"
wire width 6 input 272 \RXDFESLIDETAPID
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13352"
wire input 128 \RXDFESLIDETAPINITOVRDEN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13353"
wire input 129 \RXDFESLIDETAPONLYADAPTEN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13354"
wire input 130 \RXDFESLIDETAPOVRDEN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13239"
wire output 21 \RXDFESLIDETAPSTARTED
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13355"
wire input 131 \RXDFESLIDETAPSTROBE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13240"
wire output 22 \RXDFESLIDETAPSTROBEDONE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13241"
wire output 23 \RXDFESLIDETAPSTROBESTARTED
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13242"
wire output 24 \RXDFESTADAPTDONE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13356"
wire input 132 \RXDFETAP2HOLD
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13357"
wire input 133 \RXDFETAP2OVRDEN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13358"
wire input 134 \RXDFETAP3HOLD
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13359"
wire input 135 \RXDFETAP3OVRDEN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13360"
wire input 136 \RXDFETAP4HOLD
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13361"
wire input 137 \RXDFETAP4OVRDEN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13362"
wire input 138 \RXDFETAP5HOLD
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13363"
wire input 139 \RXDFETAP5OVRDEN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13364"
wire input 140 \RXDFETAP6HOLD
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13365"
wire input 141 \RXDFETAP6OVRDEN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13366"
wire input 142 \RXDFETAP7HOLD
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13367"
wire input 143 \RXDFETAP7OVRDEN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13368"
wire input 144 \RXDFEUTHOLD
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13369"
wire input 145 \RXDFEUTOVRDEN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13370"
wire input 146 \RXDFEVPHOLD
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13371"
wire input 147 \RXDFEVPOVRDEN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13372"
wire input 148 \RXDFEVSEN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13373"
wire input 149 \RXDFEXYDEN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13294"
wire width 8 output 76 \RXDISPERR
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13374"
wire input 150 \RXDLYBYPASS
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13375"
wire input 151 \RXDLYEN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13376"
wire input 152 \RXDLYOVRDEN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13377"
wire input 153 \RXDLYSRESET
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13243"
wire output 25 \RXDLYSRESETDONE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13244"
wire output 26 \RXELECIDLE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13473"
wire width 2 input 243 \RXELECIDLEMODE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13378"
wire input 154 \RXGEARBOXSLIP
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13289"
wire width 6 output 71 \RXHEADER
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13281"
wire width 2 output 63 \RXHEADERVALID
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13379"
wire input 155 \RXLPMEN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13380"
wire input 156 \RXLPMHFHOLD
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13381"
wire input 157 \RXLPMHFOVRDEN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13382"
wire input 158 \RXLPMLFHOLD
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13383"
wire input 159 \RXLPMLFKLOVRDEN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13384"
wire input 160 \RXMCOMMAALIGNEN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13291"
wire width 7 output 73 \RXMONITOROUT
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13474"
wire width 2 input 244 \RXMONITORSEL
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13295"
wire width 8 output 77 \RXNOTINTABLE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13385"
wire input 161 \RXOOBRESET
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13386"
wire input 162 \RXOSCALRESET
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13387"
wire input 163 \RXOSHOLD
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13491"
wire width 4 input 261 \RXOSINTCFG
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13388"
wire input 164 \RXOSINTEN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13389"
wire input 165 \RXOSINTHOLD
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13492"
wire width 4 input 262 \RXOSINTID0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13390"
wire input 166 \RXOSINTNTRLEN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13391"
wire input 167 \RXOSINTOVRDEN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13245"
wire output 27 \RXOSINTSTARTED
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13392"
wire input 168 \RXOSINTSTROBE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13246"
wire output 28 \RXOSINTSTROBEDONE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13247"
wire output 29 \RXOSINTSTROBESTARTED
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13393"
wire input 169 \RXOSINTTESTOVRDEN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13394"
wire input 170 \RXOSOVRDEN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13248"
wire output 30 \RXOUTCLK
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13249"
wire output 31 \RXOUTCLKFABRIC
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13250"
wire output 32 \RXOUTCLKPCS
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13482"
wire width 3 input 252 \RXOUTCLKSEL
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13395"
wire input 171 \RXPCOMMAALIGNEN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13396"
wire input 172 \RXPCSRESET
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13475"
wire width 2 input 245 \RXPD
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13397"
wire input 173 \RXPHALIGN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13251"
wire output 33 \RXPHALIGNDONE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13398"
wire input 174 \RXPHALIGNEN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13399"
wire input 175 \RXPHDLYPD
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13400"
wire input 176 \RXPHDLYRESET
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13287"
wire width 5 output 69 \RXPHMONITOR
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13401"
wire input 177 \RXPHOVRDEN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13288"
wire width 5 output 70 \RXPHSLIPMONITOR
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13402"
wire input 178 \RXPMARESET
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13252"
wire output 34 \RXPMARESETDONE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13403"
wire input 179 \RXPOLARITY
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13404"
wire input 180 \RXPRBSCNTRESET
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13253"
wire output 35 \RXPRBSERR
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13483"
wire width 3 input 253 \RXPRBSSEL
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13405"
wire input 181 \RXQPIEN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13254"
wire output 36 \RXQPISENN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13255"
wire output 37 \RXQPISENP
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13484"
wire width 3 input 254 \RXRATE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13256"
wire output 38 \RXRATEDONE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13406"
wire input 182 \RXRATEMODE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13257"
wire output 39 \RXRESETDONE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13407"
wire input 183 \RXSLIDE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13282"
wire width 2 output 64 \RXSTARTOFSEQ
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13285"
wire width 3 output 67 \RXSTATUS
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13408"
wire input 184 \RXSYNCALLIN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13258"
wire output 40 \RXSYNCDONE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13409"
wire input 185 \RXSYNCIN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13410"
wire input 186 \RXSYNCMODE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13259"
wire output 41 \RXSYNCOUT
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13476"
wire width 2 input 246 \RXSYSCLKSEL
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13411"
wire input 187 \RXUSERRDY
attribute \invertible_pin "IS_RXUSRCLK_INVERTED"
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13415"
wire input 189 \RXUSRCLK
attribute \invertible_pin "IS_RXUSRCLK2_INVERTED"
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13413"
wire input 188 \RXUSRCLK2
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13260"
wire output 42 \RXVALID
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13416"
wire input 190 \SETERRSTATUS
attribute \invertible_pin "IS_SIGVALIDCLK_INVERTED"
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13418"
wire input 191 \SIGVALIDCLK
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13472"
wire width 20 input 242 \TSTIN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13506"
wire width 8 input 276 \TX8B10BBYPASS
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13419"
wire input 192 \TX8B10BEN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13485"
wire width 3 input 255 \TXBUFDIFFCTRL
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13283"
wire width 2 output 65 \TXBUFSTATUS
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13507"
wire width 8 input 277 \TXCHARDISPMODE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13508"
wire width 8 input 278 \TXCHARDISPVAL
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13509"
wire width 8 input 279 \TXCHARISK
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13261"
wire output 43 \TXCOMFINISH
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13420"
wire input 193 \TXCOMINIT
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13421"
wire input 194 \TXCOMSAS
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13422"
wire input 195 \TXCOMWAKE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13503"
wire width 64 input 273 \TXDATA
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13423"
wire input 196 \TXDEEMPH
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13424"
wire input 197 \TXDETECTRX
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13493"
wire width 4 input 263 \TXDIFFCTRL
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13425"
wire input 198 \TXDIFFPD
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13426"
wire input 199 \TXDLYBYPASS
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13427"
wire input 200 \TXDLYEN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13428"
wire input 201 \TXDLYHOLD
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13429"
wire input 202 \TXDLYOVRDEN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13430"
wire input 203 \TXDLYSRESET
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13262"
wire output 44 \TXDLYSRESETDONE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13431"
wire input 204 \TXDLYUPDOWN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13432"
wire input 205 \TXELECIDLE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13263"
wire output 45 \TXGEARBOXREADY
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13486"
wire width 3 input 256 \TXHEADER
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13433"
wire input 206 \TXINHIBIT
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13504"
wire width 7 input 274 \TXMAINCURSOR
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13487"
wire width 3 input 257 \TXMARGIN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13264"
wire output 46 \TXOUTCLK
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13265"
wire output 47 \TXOUTCLKFABRIC
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13266"
wire output 48 \TXOUTCLKPCS
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13488"
wire width 3 input 258 \TXOUTCLKSEL
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13434"
wire input 207 \TXPCSRESET
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13477"
wire width 2 input 247 \TXPD
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13435"
wire input 208 \TXPDELECIDLEMODE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13436"
wire input 209 \TXPHALIGN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13267"
wire output 49 \TXPHALIGNDONE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13437"
wire input 210 \TXPHALIGNEN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13438"
wire input 211 \TXPHDLYPD
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13439"
wire input 212 \TXPHDLYRESET
attribute \invertible_pin "IS_TXPHDLYTSTCLK_INVERTED"
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13441"
wire input 213 \TXPHDLYTSTCLK
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13442"
wire input 214 \TXPHINIT
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13268"
wire output 50 \TXPHINITDONE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13443"
wire input 215 \TXPHOVRDEN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13444"
wire input 216 \TXPIPPMEN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13445"
wire input 217 \TXPIPPMOVRDEN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13446"
wire input 218 \TXPIPPMPD
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13447"
wire input 219 \TXPIPPMSEL
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13499"
wire width 5 input 269 \TXPIPPMSTEPSIZE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13448"
wire input 220 \TXPISOPD
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13449"
wire input 221 \TXPMARESET
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13269"
wire output 51 \TXPMARESETDONE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13450"
wire input 222 \TXPOLARITY
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13500"
wire width 5 input 270 \TXPOSTCURSOR
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13451"
wire input 223 \TXPOSTCURSORINV
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13452"
wire input 224 \TXPRBSFORCEERR
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13489"
wire width 3 input 259 \TXPRBSSEL
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13501"
wire width 5 input 271 \TXPRECURSOR
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13453"
wire input 225 \TXPRECURSORINV
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13454"
wire input 226 \TXQPIBIASEN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13270"
wire output 52 \TXQPISENN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13271"
wire output 53 \TXQPISENP
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13455"
wire input 227 \TXQPISTRONGPDOWN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13456"
wire input 228 \TXQPIWEAKPUP
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13490"
wire width 3 input 260 \TXRATE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13272"
wire output 54 \TXRATEDONE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13457"
wire input 229 \TXRATEMODE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13273"
wire output 55 \TXRESETDONE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13505"
wire width 7 input 275 \TXSEQUENCE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13458"
wire input 230 \TXSTARTSEQ
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13459"
wire input 231 \TXSWING
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13460"
wire input 232 \TXSYNCALLIN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13274"
wire output 56 \TXSYNCDONE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13461"
wire input 233 \TXSYNCIN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13462"
wire input 234 \TXSYNCMODE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13275"
wire output 57 \TXSYNCOUT
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13478"
wire width 2 input 248 \TXSYSCLKSEL
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13463"
wire input 235 \TXUSERRDY
attribute \invertible_pin "IS_TXUSRCLK_INVERTED"
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13467"
wire input 237 \TXUSRCLK
attribute \invertible_pin "IS_TXUSRCLK2_INVERTED"
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13465"
wire input 236 \TXUSRCLK2
end
attribute \blackbox 1
attribute \cells_not_processed 1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13513"
module \GTHE2_COMMON
parameter \BIAS_CFG
parameter \COMMON_CFG
parameter \IS_DRPCLK_INVERTED
parameter \IS_GTGREFCLK_INVERTED
parameter \IS_QPLLLOCKDETCLK_INVERTED
parameter \QPLL_CFG
parameter \QPLL_CLKOUT_CFG
parameter \QPLL_COARSE_FREQ_OVRD
parameter \QPLL_COARSE_FREQ_OVRD_EN
parameter \QPLL_CP
parameter \QPLL_CP_MONITOR_EN
parameter \QPLL_DMONITOR_SEL
parameter \QPLL_FBDIV
parameter \QPLL_FBDIV_MONITOR_EN
parameter \QPLL_FBDIV_RATIO
parameter \QPLL_INIT_CFG
parameter \QPLL_LOCK_CFG
parameter \QPLL_LPF
parameter \QPLL_REFCLK_DIV
parameter \QPLL_RP_COMP
parameter \QPLL_VTRL_RESET
parameter \RCAL_CFG
parameter \RSVD_ATTR0
parameter \RSVD_ATTR1
parameter \SIM_QPLLREFCLK_SEL
parameter \SIM_RESET_SPEEDUP
parameter \SIM_VERSION
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13551"
wire input 11 \BGBYPASSB
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13552"
wire input 12 \BGMONITORENB
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13553"
wire input 13 \BGPDB
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13577"
wire width 5 input 34 \BGRCALOVRD
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13554"
wire input 14 \BGRCALOVRDENB
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13579"
wire width 8 input 36 \DRPADDR
attribute \invertible_pin "IS_DRPCLK_INVERTED"
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13556"
wire input 15 \DRPCLK
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13574"
wire width 16 input 31 \DRPDI
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13548"
wire width 16 output 8 \DRPDO
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13557"
wire input 16 \DRPEN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13541"
wire output 1 \DRPRDY
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13558"
wire input 17 \DRPWE
attribute \invertible_pin "IS_GTGREFCLK_INVERTED"
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13560"
wire input 18 \GTGREFCLK
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13561"
wire input 19 \GTNORTHREFCLK0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13562"
wire input 20 \GTNORTHREFCLK1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13563"
wire input 21 \GTREFCLK0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13564"
wire input 22 \GTREFCLK1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13565"
wire input 23 \GTSOUTHREFCLK0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13566"
wire input 24 \GTSOUTHREFCLK1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13580"
wire width 8 input 37 \PMARSVD
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13549"
wire width 16 output 9 \PMARSVDOUT
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13550"
wire width 8 output 10 \QPLLDMONITOR
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13542"
wire output 2 \QPLLFBCLKLOST
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13543"
wire output 3 \QPLLLOCK
attribute \invertible_pin "IS_QPLLLOCKDETCLK_INVERTED"
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13568"
wire input 25 \QPLLLOCKDETCLK
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13569"
wire input 26 \QPLLLOCKEN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13544"
wire output 4 \QPLLOUTCLK
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13545"
wire output 5 \QPLLOUTREFCLK
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13570"
wire input 27 \QPLLOUTRESET
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13571"
wire input 28 \QPLLPD
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13546"
wire output 6 \QPLLREFCLKLOST
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13576"
wire width 3 input 33 \QPLLREFCLKSEL
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13572"
wire input 29 \QPLLRESET
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13575"
wire width 16 input 32 \QPLLRSVD1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13578"
wire width 5 input 35 \QPLLRSVD2
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13573"
wire input 30 \RCALENB
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13547"
wire output 7 \REFCLKOUTMONITOR
end
attribute \blackbox 1
attribute \cells_not_processed 1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:14673"
module \GTHE3_CHANNEL
parameter \ACJTAG_DEBUG_MODE
parameter \ACJTAG_MODE
parameter \ACJTAG_RESET
parameter \ADAPT_CFG0
parameter \ADAPT_CFG1
parameter \ALIGN_COMMA_DOUBLE
parameter \ALIGN_COMMA_ENABLE
parameter \ALIGN_COMMA_WORD
parameter \ALIGN_MCOMMA_DET
parameter \ALIGN_MCOMMA_VALUE
parameter \ALIGN_PCOMMA_DET
parameter \ALIGN_PCOMMA_VALUE
parameter \A_RXOSCALRESET
parameter \A_RXPROGDIVRESET
parameter \A_TXPROGDIVRESET
parameter \CBCC_DATA_SOURCE_SEL
parameter \CDR_SWAP_MODE_EN
parameter \CHAN_BOND_KEEP_ALIGN
parameter \CHAN_BOND_MAX_SKEW
parameter \CHAN_BOND_SEQ_1_1
parameter \CHAN_BOND_SEQ_1_2
parameter \CHAN_BOND_SEQ_1_3
parameter \CHAN_BOND_SEQ_1_4
parameter \CHAN_BOND_SEQ_1_ENABLE
parameter \CHAN_BOND_SEQ_2_1
parameter \CHAN_BOND_SEQ_2_2
parameter \CHAN_BOND_SEQ_2_3
parameter \CHAN_BOND_SEQ_2_4
parameter \CHAN_BOND_SEQ_2_ENABLE
parameter \CHAN_BOND_SEQ_2_USE
parameter \CHAN_BOND_SEQ_LEN
parameter \CLK_CORRECT_USE
parameter \CLK_COR_KEEP_IDLE
parameter \CLK_COR_MAX_LAT
parameter \CLK_COR_MIN_LAT
parameter \CLK_COR_PRECEDENCE
parameter \CLK_COR_REPEAT_WAIT
parameter \CLK_COR_SEQ_1_1
parameter \CLK_COR_SEQ_1_2
parameter \CLK_COR_SEQ_1_3
parameter \CLK_COR_SEQ_1_4
parameter \CLK_COR_SEQ_1_ENABLE
parameter \CLK_COR_SEQ_2_1
parameter \CLK_COR_SEQ_2_2
parameter \CLK_COR_SEQ_2_3
parameter \CLK_COR_SEQ_2_4
parameter \CLK_COR_SEQ_2_ENABLE
parameter \CLK_COR_SEQ_2_USE
parameter \CLK_COR_SEQ_LEN
parameter \CPLL_CFG0
parameter \CPLL_CFG1
parameter \CPLL_CFG2
parameter \CPLL_CFG3
parameter \CPLL_FBDIV
parameter \CPLL_FBDIV_45
parameter \CPLL_INIT_CFG0
parameter \CPLL_INIT_CFG1
parameter \CPLL_LOCK_CFG
parameter \CPLL_REFCLK_DIV
parameter \DDI_CTRL
parameter \DDI_REALIGN_WAIT
parameter \DEC_MCOMMA_DETECT
parameter \DEC_PCOMMA_DETECT
parameter \DEC_VALID_COMMA_ONLY
parameter \DFE_D_X_REL_POS
parameter \DFE_VCM_COMP_EN
parameter \DMONITOR_CFG0
parameter \DMONITOR_CFG1
parameter \ES_CLK_PHASE_SEL
parameter \ES_CONTROL
parameter \ES_ERRDET_EN
parameter \ES_EYE_SCAN_EN
parameter \ES_HORZ_OFFSET
parameter \ES_PMA_CFG
parameter \ES_PRESCALE
parameter \ES_QUALIFIER0
parameter \ES_QUALIFIER1
parameter \ES_QUALIFIER2
parameter \ES_QUALIFIER3
parameter \ES_QUALIFIER4
parameter \ES_QUAL_MASK0
parameter \ES_QUAL_MASK1
parameter \ES_QUAL_MASK2
parameter \ES_QUAL_MASK3
parameter \ES_QUAL_MASK4
parameter \ES_SDATA_MASK0
parameter \ES_SDATA_MASK1
parameter \ES_SDATA_MASK2
parameter \ES_SDATA_MASK3
parameter \ES_SDATA_MASK4
parameter \EVODD_PHI_CFG
parameter \EYE_SCAN_SWAP_EN
parameter \FTS_DESKEW_SEQ_ENABLE
parameter \FTS_LANE_DESKEW_CFG
parameter \FTS_LANE_DESKEW_EN
parameter \GEARBOX_MODE
parameter \GM_BIAS_SELECT
parameter \LOCAL_MASTER
parameter \OOBDIVCTL
parameter \OOB_PWRUP
parameter \PCI3_AUTO_REALIGN
parameter \PCI3_PIPE_RX_ELECIDLE
parameter \PCI3_RX_ASYNC_EBUF_BYPASS
parameter \PCI3_RX_ELECIDLE_EI2_ENABLE
parameter \PCI3_RX_ELECIDLE_H2L_COUNT
parameter \PCI3_RX_ELECIDLE_H2L_DISABLE
parameter \PCI3_RX_ELECIDLE_HI_COUNT
parameter \PCI3_RX_ELECIDLE_LP4_DISABLE
parameter \PCI3_RX_FIFO_DISABLE
parameter \PCIE_BUFG_DIV_CTRL
parameter \PCIE_RXPCS_CFG_GEN3
parameter \PCIE_RXPMA_CFG
parameter \PCIE_TXPCS_CFG_GEN3
parameter \PCIE_TXPMA_CFG
parameter \PCS_PCIE_EN
parameter \PCS_RSVD0
parameter \PCS_RSVD1
parameter \PD_TRANS_TIME_FROM_P2
parameter \PD_TRANS_TIME_NONE_P2
parameter \PD_TRANS_TIME_TO_P2
parameter \PLL_SEL_MODE_GEN12
parameter \PLL_SEL_MODE_GEN3
parameter \PMA_RSV1
parameter \PROCESS_PAR
parameter \RATE_SW_USE_DRP
parameter \RESET_POWERSAVE_DISABLE
parameter \RXBUFRESET_TIME
parameter \RXBUF_ADDR_MODE
parameter \RXBUF_EIDLE_HI_CNT
parameter \RXBUF_EIDLE_LO_CNT
parameter \RXBUF_EN
parameter \RXBUF_RESET_ON_CB_CHANGE
parameter \RXBUF_RESET_ON_COMMAALIGN
parameter \RXBUF_RESET_ON_EIDLE
parameter \RXBUF_RESET_ON_RATE_CHANGE
parameter \RXBUF_THRESH_OVFLW
parameter \RXBUF_THRESH_OVRD
parameter \RXBUF_THRESH_UNDFLW
parameter \RXCDRFREQRESET_TIME
parameter \RXCDRPHRESET_TIME
parameter \RXCDR_CFG0
parameter \RXCDR_CFG0_GEN3
parameter \RXCDR_CFG1
parameter \RXCDR_CFG1_GEN3
parameter \RXCDR_CFG2
parameter \RXCDR_CFG2_GEN3
parameter \RXCDR_CFG3
parameter \RXCDR_CFG3_GEN3
parameter \RXCDR_CFG4
parameter \RXCDR_CFG4_GEN3
parameter \RXCDR_CFG5
parameter \RXCDR_CFG5_GEN3
parameter \RXCDR_FR_RESET_ON_EIDLE
parameter \RXCDR_HOLD_DURING_EIDLE
parameter \RXCDR_LOCK_CFG0
parameter \RXCDR_LOCK_CFG1
parameter \RXCDR_LOCK_CFG2
parameter \RXCDR_PH_RESET_ON_EIDLE
parameter \RXCFOK_CFG0
parameter \RXCFOK_CFG1
parameter \RXCFOK_CFG2
parameter \RXDFELPMRESET_TIME
parameter \RXDFELPM_KL_CFG0
parameter \RXDFELPM_KL_CFG1
parameter \RXDFELPM_KL_CFG2
parameter \RXDFE_CFG0
parameter \RXDFE_CFG1
parameter \RXDFE_GC_CFG0
parameter \RXDFE_GC_CFG1
parameter \RXDFE_GC_CFG2
parameter \RXDFE_H2_CFG0
parameter \RXDFE_H2_CFG1
parameter \RXDFE_H3_CFG0
parameter \RXDFE_H3_CFG1
parameter \RXDFE_H4_CFG0
parameter \RXDFE_H4_CFG1
parameter \RXDFE_H5_CFG0
parameter \RXDFE_H5_CFG1
parameter \RXDFE_H6_CFG0
parameter \RXDFE_H6_CFG1
parameter \RXDFE_H7_CFG0
parameter \RXDFE_H7_CFG1
parameter \RXDFE_H8_CFG0
parameter \RXDFE_H8_CFG1
parameter \RXDFE_H9_CFG0
parameter \RXDFE_H9_CFG1
parameter \RXDFE_HA_CFG0
parameter \RXDFE_HA_CFG1
parameter \RXDFE_HB_CFG0
parameter \RXDFE_HB_CFG1
parameter \RXDFE_HC_CFG0
parameter \RXDFE_HC_CFG1
parameter \RXDFE_HD_CFG0
parameter \RXDFE_HD_CFG1
parameter \RXDFE_HE_CFG0
parameter \RXDFE_HE_CFG1
parameter \RXDFE_HF_CFG0
parameter \RXDFE_HF_CFG1
parameter \RXDFE_OS_CFG0
parameter \RXDFE_OS_CFG1
parameter \RXDFE_UT_CFG0
parameter \RXDFE_UT_CFG1
parameter \RXDFE_VP_CFG0
parameter \RXDFE_VP_CFG1
parameter \RXDLY_CFG
parameter \RXDLY_LCFG
parameter \RXELECIDLE_CFG
parameter \RXGBOX_FIFO_INIT_RD_ADDR
parameter \RXGEARBOX_EN
parameter \RXISCANRESET_TIME
parameter \RXLPM_CFG
parameter \RXLPM_GC_CFG
parameter \RXLPM_KH_CFG0
parameter \RXLPM_KH_CFG1
parameter \RXLPM_OS_CFG0
parameter \RXLPM_OS_CFG1
parameter \RXOOB_CFG
parameter \RXOOB_CLK_CFG
parameter \RXOSCALRESET_TIME
parameter \RXOUT_DIV
parameter \RXPCSRESET_TIME
parameter \RXPHBEACON_CFG
parameter \RXPHDLY_CFG
parameter \RXPHSAMP_CFG
parameter \RXPHSLIP_CFG
parameter \RXPH_MONITOR_SEL
parameter \RXPI_CFG0
parameter \RXPI_CFG1
parameter \RXPI_CFG2
parameter \RXPI_CFG3
parameter \RXPI_CFG4
parameter \RXPI_CFG5
parameter \RXPI_CFG6
parameter \RXPI_LPM
parameter \RXPI_VREFSEL
parameter \RXPMACLK_SEL
parameter \RXPMARESET_TIME
parameter \RXPRBS_ERR_LOOPBACK
parameter \RXPRBS_LINKACQ_CNT
parameter \RXSLIDE_AUTO_WAIT
parameter \RXSLIDE_MODE
parameter \RXSYNC_MULTILANE
parameter \RXSYNC_OVRD
parameter \RXSYNC_SKIP_DA
parameter \RX_AFE_CM_EN
parameter \RX_BIAS_CFG0
parameter \RX_BUFFER_CFG
parameter \RX_CAPFF_SARC_ENB
parameter \RX_CLK25_DIV
parameter \RX_CLKMUX_EN
parameter \RX_CLK_SLIP_OVRD
parameter \RX_CM_BUF_CFG
parameter \RX_CM_BUF_PD
parameter \RX_CM_SEL
parameter \RX_CM_TRIM
parameter \RX_CTLE3_LPF
parameter \RX_DATA_WIDTH
parameter \RX_DDI_SEL
parameter \RX_DEFER_RESET_BUF_EN
parameter \RX_DFELPM_CFG0
parameter \RX_DFELPM_CFG1
parameter \RX_DFELPM_KLKH_AGC_STUP_EN
parameter \RX_DFE_AGC_CFG0
parameter \RX_DFE_AGC_CFG1
parameter \RX_DFE_KL_LPM_KH_CFG0
parameter \RX_DFE_KL_LPM_KH_CFG1
parameter \RX_DFE_KL_LPM_KL_CFG0
parameter \RX_DFE_KL_LPM_KL_CFG1
parameter \RX_DFE_LPM_HOLD_DURING_EIDLE
parameter \RX_DISPERR_SEQ_MATCH
parameter \RX_DIVRESET_TIME
parameter \RX_EN_HI_LR
parameter \RX_EYESCAN_VS_CODE
parameter \RX_EYESCAN_VS_NEG_DIR
parameter \RX_EYESCAN_VS_RANGE
parameter \RX_EYESCAN_VS_UT_SIGN
parameter \RX_FABINT_USRCLK_FLOP
parameter \RX_INT_DATAWIDTH
parameter \RX_PMA_POWER_SAVE
parameter \RX_PROGDIV_CFG
parameter \RX_SAMPLE_PERIOD
parameter \RX_SIG_VALID_DLY
parameter \RX_SUM_DFETAPREP_EN
parameter \RX_SUM_IREF_TUNE
parameter \RX_SUM_RES_CTRL
parameter \RX_SUM_VCMTUNE
parameter \RX_SUM_VCM_OVWR
parameter \RX_SUM_VREF_TUNE
parameter \RX_TUNE_AFE_OS
parameter \RX_WIDEMODE_CDR
parameter \RX_XCLK_SEL
parameter \SAS_MAX_COM
parameter \SAS_MIN_COM
parameter \SATA_BURST_SEQ_LEN
parameter \SATA_BURST_VAL
parameter \SATA_CPLL_CFG
parameter \SATA_EIDLE_VAL
parameter \SATA_MAX_BURST
parameter \SATA_MAX_INIT
parameter \SATA_MAX_WAKE
parameter \SATA_MIN_BURST
parameter \SATA_MIN_INIT
parameter \SATA_MIN_WAKE
parameter \SHOW_REALIGN_COMMA
parameter \SIM_MODE
parameter \SIM_RECEIVER_DETECT_PASS
parameter \SIM_RESET_SPEEDUP
parameter \SIM_TX_EIDLE_DRIVE_LEVEL
parameter \SIM_VERSION
parameter \TAPDLY_SET_TX
parameter \TEMPERATUR_PAR
parameter \TERM_RCAL_CFG
parameter \TERM_RCAL_OVRD
parameter \TRANS_TIME_RATE
parameter \TST_RSV0
parameter \TST_RSV1
parameter \TXBUF_EN
parameter \TXBUF_RESET_ON_RATE_CHANGE
parameter \TXDLY_CFG
parameter \TXDLY_LCFG
parameter \TXDRVBIAS_N
parameter \TXDRVBIAS_P
parameter \TXFIFO_ADDR_CFG
parameter \TXGBOX_FIFO_INIT_RD_ADDR
parameter \TXGEARBOX_EN
parameter \TXOUT_DIV
parameter \TXPCSRESET_TIME
parameter \TXPHDLY_CFG0
parameter \TXPHDLY_CFG1
parameter \TXPH_CFG
parameter \TXPH_MONITOR_SEL
parameter \TXPI_CFG0
parameter \TXPI_CFG1
parameter \TXPI_CFG2
parameter \TXPI_CFG3
parameter \TXPI_CFG4
parameter \TXPI_CFG5
parameter \TXPI_GRAY_SEL
parameter \TXPI_INVSTROBE_SEL
parameter \TXPI_LPM
parameter \TXPI_PPMCLK_SEL
parameter \TXPI_PPM_CFG
parameter \TXPI_SYNFREQ_PPM
parameter \TXPI_VREFSEL
parameter \TXPMARESET_TIME
parameter \TXSYNC_MULTILANE
parameter \TXSYNC_OVRD
parameter \TXSYNC_SKIP_DA
parameter \TX_CLK25_DIV
parameter \TX_CLKMUX_EN
parameter \TX_DATA_WIDTH
parameter \TX_DCD_CFG
parameter \TX_DCD_EN
parameter \TX_DEEMPH0
parameter \TX_DEEMPH1
parameter \TX_DIVRESET_TIME
parameter \TX_DRIVE_MODE
parameter \TX_EIDLE_ASSERT_DELAY
parameter \TX_EIDLE_DEASSERT_DELAY
parameter \TX_EML_PHI_TUNE
parameter \TX_FABINT_USRCLK_FLOP
parameter \TX_IDLE_DATA_ZERO
parameter \TX_INT_DATAWIDTH
parameter \TX_LOOPBACK_DRIVE_HIZ
parameter \TX_MAINCURSOR_SEL
parameter \TX_MARGIN_FULL_0
parameter \TX_MARGIN_FULL_1
parameter \TX_MARGIN_FULL_2
parameter \TX_MARGIN_FULL_3
parameter \TX_MARGIN_FULL_4
parameter \TX_MARGIN_LOW_0
parameter \TX_MARGIN_LOW_1
parameter \TX_MARGIN_LOW_2
parameter \TX_MARGIN_LOW_3
parameter \TX_MARGIN_LOW_4
parameter \TX_MODE_SEL
parameter \TX_PMADATA_OPT
parameter \TX_PMA_POWER_SAVE
parameter \TX_PROGCLK_SEL
parameter \TX_PROGDIV_CFG
parameter \TX_QPI_STATUS_EN
parameter \TX_RXDETECT_CFG
parameter \TX_RXDETECT_REF
parameter \TX_SAMPLE_PERIOD
parameter \TX_SARC_LPBK_ENB
parameter \TX_XCLK_SEL
parameter \USE_PCS_CLK_PHASE_SEL
parameter \WB_MODE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:15062"
wire width 3 output 1 \BUFGTCE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:15063"
wire width 3 output 2 \BUFGTCEMASK
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:15064"
wire width 9 output 3 \BUFGTDIV
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:15065"
wire width 3 output 4 \BUFGTRESET
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:15066"
wire width 3 output 5 \BUFGTRSTMASK
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:15159"
wire input 98 \CFGRESET
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:15160"
wire input 99 \CLKRSVD0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:15161"
wire input 100 \CLKRSVD1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:15067"
wire output 6 \CPLLFBCLKLOST
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:15068"
wire output 7 \CPLLLOCK
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:15162"
wire input 101 \CPLLLOCKDETCLK
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:15163"
wire input 102 \CPLLLOCKEN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:15164"
wire input 103 \CPLLPD
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:15069"
wire output 8 \CPLLREFCLKLOST
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:15165"
wire width 3 input 104 \CPLLREFCLKSEL
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:15166"
wire input 105 \CPLLRESET
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:15167"
wire input 106 \DMONFIFORESET
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:15168"
wire input 107 \DMONITORCLK
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:15070"
wire width 17 output 9 \DMONITOROUT
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:15169"
wire width 9 input 108 \DRPADDR
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:15170"
wire input 109 \DRPCLK
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:15171"
wire width 16 input 110 \DRPDI
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:15071"
wire width 16 output 10 \DRPDO
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:15172"
wire input 111 \DRPEN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:15072"
wire output 11 \DRPRDY
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:15173"
wire input 112 \DRPWE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:15174"
wire input 113 \EVODDPHICALDONE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:15175"
wire input 114 \EVODDPHICALSTART
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:15176"
wire input 115 \EVODDPHIDRDEN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:15177"
wire input 116 \EVODDPHIDWREN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:15178"
wire input 117 \EVODDPHIXRDEN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:15179"
wire input 118 \EVODDPHIXWREN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:15073"
wire output 12 \EYESCANDATAERROR
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:15180"
wire input 119 \EYESCANMODE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:15181"
wire input 120 \EYESCANRESET
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:15182"
wire input 121 \EYESCANTRIGGER
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:15183"
wire input 122 \GTGREFCLK
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:15184"
wire input 123 \GTHRXN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:15185"
wire input 124 \GTHRXP
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:15074"
wire output 13 \GTHTXN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:15075"
wire output 14 \GTHTXP
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:15186"
wire input 125 \GTNORTHREFCLK0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:15187"
wire input 126 \GTNORTHREFCLK1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:15076"
wire output 15 \GTPOWERGOOD
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:15188"
wire input 127 \GTREFCLK0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:15189"
wire input 128 \GTREFCLK1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:15077"
wire output 16 \GTREFCLKMONITOR
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:15190"
wire input 129 \GTRESETSEL
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:15191"
wire width 16 input 130 \GTRSVD
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:15192"
wire input 131 \GTRXRESET
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:15193"
wire input 132 \GTSOUTHREFCLK0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:15194"
wire input 133 \GTSOUTHREFCLK1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:15195"
wire input 134 \GTTXRESET
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:15196"
wire width 3 input 135 \LOOPBACK
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:15197"
wire input 136 \LPBKRXTXSEREN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:15198"
wire input 137 \LPBKTXRXSEREN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:15199"
wire input 138 \PCIEEQRXEQADAPTDONE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:15078"
wire output 17 \PCIERATEGEN3
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:15079"
wire output 18 \PCIERATEIDLE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:15080"
wire width 2 output 19 \PCIERATEQPLLPD
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:15081"
wire width 2 output 20 \PCIERATEQPLLRESET
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:15200"
wire input 139 \PCIERSTIDLE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:15201"
wire input 140 \PCIERSTTXSYNCSTART
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:15082"
wire output 21 \PCIESYNCTXSYNCDONE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:15083"
wire output 22 \PCIEUSERGEN3RDY
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:15084"
wire output 23 \PCIEUSERPHYSTATUSRST
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:15202"
wire input 141 \PCIEUSERRATEDONE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:15085"
wire output 24 \PCIEUSERRATESTART
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:15203"
wire width 16 input 142 \PCSRSVDIN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:15204"
wire width 5 input 143 \PCSRSVDIN2
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:15086"
wire width 12 output 25 \PCSRSVDOUT
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:15087"
wire output 26 \PHYSTATUS
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:15088"
wire width 8 output 27 \PINRSRVDAS
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:15205"
wire width 5 input 144 \PMARSVDIN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:15206"
wire input 145 \QPLL0CLK
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:15207"
wire input 146 \QPLL0REFCLK
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:15208"
wire input 147 \QPLL1CLK
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:15209"
wire input 148 \QPLL1REFCLK
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:15089"
wire output 28 \RESETEXCEPTION
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:15210"
wire input 149 \RESETOVRD
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:15211"
wire input 150 \RSTCLKENTX
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:15212"
wire input 151 \RX8B10BEN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:15213"
wire input 152 \RXBUFRESET
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:15090"
wire width 3 output 29 \RXBUFSTATUS
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:15091"
wire output 30 \RXBYTEISALIGNED
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:15092"
wire output 31 \RXBYTEREALIGN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:15214"
wire input 153 \RXCDRFREQRESET
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:15215"
wire input 154 \RXCDRHOLD
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:15093"
wire output 32 \RXCDRLOCK
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:15216"
wire input 155 \RXCDROVRDEN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:15094"
wire output 33 \RXCDRPHDONE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:15217"
wire input 156 \RXCDRRESET
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:15218"
wire input 157 \RXCDRRESETRSV
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:15095"
wire output 34 \RXCHANBONDSEQ
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:15096"
wire output 35 \RXCHANISALIGNED
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:15097"
wire output 36 \RXCHANREALIGN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:15219"
wire input 158 \RXCHBONDEN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:15220"
wire width 5 input 159 \RXCHBONDI
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:15221"
wire width 3 input 160 \RXCHBONDLEVEL
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:15222"
wire input 161 \RXCHBONDMASTER
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:15098"
wire width 5 output 37 \RXCHBONDO
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:15223"
wire input 162 \RXCHBONDSLAVE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:15099"
wire width 2 output 38 \RXCLKCORCNT
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:15100"
wire output 39 \RXCOMINITDET
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:15101"
wire output 40 \RXCOMMADET
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:15224"
wire input 163 \RXCOMMADETEN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:15102"
wire output 41 \RXCOMSASDET
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:15103"
wire output 42 \RXCOMWAKEDET
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:15104"
wire width 16 output 43 \RXCTRL0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:15105"
wire width 16 output 44 \RXCTRL1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:15106"
wire width 8 output 45 \RXCTRL2
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:15107"
wire width 8 output 46 \RXCTRL3
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:15108"
wire width 128 output 47 \RXDATA
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:15109"
wire width 8 output 48 \RXDATAEXTENDRSVD
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:15110"
wire width 2 output 49 \RXDATAVALID
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:15225"
wire width 2 input 164 \RXDFEAGCCTRL
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:15226"
wire input 165 \RXDFEAGCHOLD
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:15227"
wire input 166 \RXDFEAGCOVRDEN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:15228"
wire input 167 \RXDFELFHOLD
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:15229"
wire input 168 \RXDFELFOVRDEN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:15230"
wire input 169 \RXDFELPMRESET
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:15231"
wire input 170 \RXDFETAP10HOLD
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:15232"
wire input 171 \RXDFETAP10OVRDEN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:15233"
wire input 172 \RXDFETAP11HOLD
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:15234"
wire input 173 \RXDFETAP11OVRDEN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:15235"
wire input 174 \RXDFETAP12HOLD
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:15236"
wire input 175 \RXDFETAP12OVRDEN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:15237"
wire input 176 \RXDFETAP13HOLD
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:15238"
wire input 177 \RXDFETAP13OVRDEN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:15239"
wire input 178 \RXDFETAP14HOLD
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:15240"
wire input 179 \RXDFETAP14OVRDEN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:15241"
wire input 180 \RXDFETAP15HOLD
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:15242"
wire input 181 \RXDFETAP15OVRDEN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:15243"
wire input 182 \RXDFETAP2HOLD
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:15244"
wire input 183 \RXDFETAP2OVRDEN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:15245"
wire input 184 \RXDFETAP3HOLD
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:15246"
wire input 185 \RXDFETAP3OVRDEN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:15247"
wire input 186 \RXDFETAP4HOLD
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:15248"
wire input 187 \RXDFETAP4OVRDEN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:15249"
wire input 188 \RXDFETAP5HOLD
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:15250"
wire input 189 \RXDFETAP5OVRDEN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:15251"
wire input 190 \RXDFETAP6HOLD
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:15252"
wire input 191 \RXDFETAP6OVRDEN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:15253"
wire input 192 \RXDFETAP7HOLD
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:15254"
wire input 193 \RXDFETAP7OVRDEN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:15255"
wire input 194 \RXDFETAP8HOLD
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:15256"
wire input 195 \RXDFETAP8OVRDEN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:15257"
wire input 196 \RXDFETAP9HOLD
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:15258"
wire input 197 \RXDFETAP9OVRDEN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:15259"
wire input 198 \RXDFEUTHOLD
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:15260"
wire input 199 \RXDFEUTOVRDEN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:15261"
wire input 200 \RXDFEVPHOLD
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:15262"
wire input 201 \RXDFEVPOVRDEN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:15263"
wire input 202 \RXDFEVSEN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:15264"
wire input 203 \RXDFEXYDEN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:15265"
wire input 204 \RXDLYBYPASS
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:15266"
wire input 205 \RXDLYEN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:15267"
wire input 206 \RXDLYOVRDEN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:15268"
wire input 207 \RXDLYSRESET
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:15111"
wire output 50 \RXDLYSRESETDONE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:15112"
wire output 51 \RXELECIDLE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:15269"
wire width 2 input 208 \RXELECIDLEMODE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:15270"
wire input 209 \RXGEARBOXSLIP
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:15113"
wire width 6 output 52 \RXHEADER
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:15114"
wire width 2 output 53 \RXHEADERVALID
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:15271"
wire input 210 \RXLATCLK
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:15272"
wire input 211 \RXLPMEN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:15273"
wire input 212 \RXLPMGCHOLD
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:15274"
wire input 213 \RXLPMGCOVRDEN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:15275"
wire input 214 \RXLPMHFHOLD
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:15276"
wire input 215 \RXLPMHFOVRDEN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:15277"
wire input 216 \RXLPMLFHOLD
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:15278"
wire input 217 \RXLPMLFKLOVRDEN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:15279"
wire input 218 \RXLPMOSHOLD
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:15280"
wire input 219 \RXLPMOSOVRDEN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:15281"
wire input 220 \RXMCOMMAALIGNEN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:15115"
wire width 7 output 54 \RXMONITOROUT
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:15282"
wire width 2 input 221 \RXMONITORSEL
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:15283"
wire input 222 \RXOOBRESET
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:15284"
wire input 223 \RXOSCALRESET
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:15285"
wire input 224 \RXOSHOLD
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:15286"
wire width 4 input 225 \RXOSINTCFG
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:15116"
wire output 55 \RXOSINTDONE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:15287"
wire input 226 \RXOSINTEN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:15288"
wire input 227 \RXOSINTHOLD
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:15289"
wire input 228 \RXOSINTOVRDEN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:15117"
wire output 56 \RXOSINTSTARTED
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:15290"
wire input 229 \RXOSINTSTROBE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:15118"
wire output 57 \RXOSINTSTROBEDONE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:15119"
wire output 58 \RXOSINTSTROBESTARTED
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:15291"
wire input 230 \RXOSINTTESTOVRDEN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:15292"
wire input 231 \RXOSOVRDEN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:15120"
wire output 59 \RXOUTCLK
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:15121"
wire output 60 \RXOUTCLKFABRIC
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:15122"
wire output 61 \RXOUTCLKPCS
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:15293"
wire width 3 input 232 \RXOUTCLKSEL
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:15294"
wire input 233 \RXPCOMMAALIGNEN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:15295"
wire input 234 \RXPCSRESET
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:15296"
wire width 2 input 235 \RXPD
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:15297"
wire input 236 \RXPHALIGN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:15123"
wire output 62 \RXPHALIGNDONE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:15298"
wire input 237 \RXPHALIGNEN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:15124"
wire output 63 \RXPHALIGNERR
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:15299"
wire input 238 \RXPHDLYPD
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:15300"
wire input 239 \RXPHDLYRESET
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:15301"
wire input 240 \RXPHOVRDEN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:15302"
wire width 2 input 241 \RXPLLCLKSEL
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:15303"
wire input 242 \RXPMARESET
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:15125"
wire output 64 \RXPMARESETDONE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:15304"
wire input 243 \RXPOLARITY
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:15305"
wire input 244 \RXPRBSCNTRESET
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:15126"
wire output 65 \RXPRBSERR
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:15127"
wire output 66 \RXPRBSLOCKED
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:15306"
wire width 4 input 245 \RXPRBSSEL
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:15128"
wire output 67 \RXPRGDIVRESETDONE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:15307"
wire input 246 \RXPROGDIVRESET
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:15308"
wire input 247 \RXQPIEN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:15129"
wire output 68 \RXQPISENN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:15130"
wire output 69 \RXQPISENP
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:15309"
wire width 3 input 248 \RXRATE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:15131"
wire output 70 \RXRATEDONE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:15310"
wire input 249 \RXRATEMODE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:15132"
wire output 71 \RXRECCLKOUT
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:15133"
wire output 72 \RXRESETDONE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:15311"
wire input 250 \RXSLIDE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:15134"
wire output 73 \RXSLIDERDY
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:15135"
wire output 74 \RXSLIPDONE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:15312"
wire input 251 \RXSLIPOUTCLK
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:15136"
wire output 75 \RXSLIPOUTCLKRDY
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:15313"
wire input 252 \RXSLIPPMA
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:15137"
wire output 76 \RXSLIPPMARDY
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:15138"
wire width 2 output 77 \RXSTARTOFSEQ
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:15139"
wire width 3 output 78 \RXSTATUS
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:15314"
wire input 253 \RXSYNCALLIN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:15140"
wire output 79 \RXSYNCDONE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:15315"
wire input 254 \RXSYNCIN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:15316"
wire input 255 \RXSYNCMODE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:15141"
wire output 80 \RXSYNCOUT
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:15317"
wire width 2 input 256 \RXSYSCLKSEL
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:15318"
wire input 257 \RXUSERRDY
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:15319"
wire input 258 \RXUSRCLK
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:15320"
wire input 259 \RXUSRCLK2
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:15142"
wire output 81 \RXVALID
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:15321"
wire input 260 \SIGVALIDCLK
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:15322"
wire width 20 input 261 \TSTIN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:15323"
wire width 8 input 262 \TX8B10BBYPASS
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:15324"
wire input 263 \TX8B10BEN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:15325"
wire width 3 input 264 \TXBUFDIFFCTRL
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:15143"
wire width 2 output 82 \TXBUFSTATUS
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:15144"
wire output 83 \TXCOMFINISH
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:15326"
wire input 265 \TXCOMINIT
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:15327"
wire input 266 \TXCOMSAS
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:15328"
wire input 267 \TXCOMWAKE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:15329"
wire width 16 input 268 \TXCTRL0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:15330"
wire width 16 input 269 \TXCTRL1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:15331"
wire width 8 input 270 \TXCTRL2
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:15332"
wire width 128 input 271 \TXDATA
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:15333"
wire width 8 input 272 \TXDATAEXTENDRSVD
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:15334"
wire input 273 \TXDEEMPH
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:15335"
wire input 274 \TXDETECTRX
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:15336"
wire width 4 input 275 \TXDIFFCTRL
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:15337"
wire input 276 \TXDIFFPD
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:15338"
wire input 277 \TXDLYBYPASS
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:15339"
wire input 278 \TXDLYEN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:15340"
wire input 279 \TXDLYHOLD
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:15341"
wire input 280 \TXDLYOVRDEN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:15342"
wire input 281 \TXDLYSRESET
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:15145"
wire output 84 \TXDLYSRESETDONE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:15343"
wire input 282 \TXDLYUPDOWN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:15344"
wire input 283 \TXELECIDLE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:15345"
wire width 6 input 284 \TXHEADER
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:15346"
wire input 285 \TXINHIBIT
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:15347"
wire input 286 \TXLATCLK
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:15348"
wire width 7 input 287 \TXMAINCURSOR
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:15349"
wire width 3 input 288 \TXMARGIN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:15146"
wire output 85 \TXOUTCLK
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:15147"
wire output 86 \TXOUTCLKFABRIC
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:15148"
wire output 87 \TXOUTCLKPCS
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:15350"
wire width 3 input 289 \TXOUTCLKSEL
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:15351"
wire input 290 \TXPCSRESET
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:15352"
wire width 2 input 291 \TXPD
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:15353"
wire input 292 \TXPDELECIDLEMODE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:15354"
wire input 293 \TXPHALIGN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:15149"
wire output 88 \TXPHALIGNDONE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:15355"
wire input 294 \TXPHALIGNEN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:15356"
wire input 295 \TXPHDLYPD
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:15357"
wire input 296 \TXPHDLYRESET
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:15358"
wire input 297 \TXPHDLYTSTCLK
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:15359"
wire input 298 \TXPHINIT
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:15150"
wire output 89 \TXPHINITDONE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:15360"
wire input 299 \TXPHOVRDEN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:15361"
wire input 300 \TXPIPPMEN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:15362"
wire input 301 \TXPIPPMOVRDEN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:15363"
wire input 302 \TXPIPPMPD
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:15364"
wire input 303 \TXPIPPMSEL
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:15365"
wire width 5 input 304 \TXPIPPMSTEPSIZE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:15366"
wire input 305 \TXPISOPD
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:15367"
wire width 2 input 306 \TXPLLCLKSEL
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:15368"
wire input 307 \TXPMARESET
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:15151"
wire output 90 \TXPMARESETDONE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:15369"
wire input 308 \TXPOLARITY
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:15370"
wire width 5 input 309 \TXPOSTCURSOR
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:15371"
wire input 310 \TXPOSTCURSORINV
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:15372"
wire input 311 \TXPRBSFORCEERR
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:15373"
wire width 4 input 312 \TXPRBSSEL
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:15374"
wire width 5 input 313 \TXPRECURSOR
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:15375"
wire input 314 \TXPRECURSORINV
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:15152"
wire output 91 \TXPRGDIVRESETDONE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:15376"
wire input 315 \TXPROGDIVRESET
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:15377"
wire input 316 \TXQPIBIASEN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:15153"
wire output 92 \TXQPISENN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:15154"
wire output 93 \TXQPISENP
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:15378"
wire input 317 \TXQPISTRONGPDOWN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:15379"
wire input 318 \TXQPIWEAKPUP
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:15380"
wire width 3 input 319 \TXRATE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:15155"
wire output 94 \TXRATEDONE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:15381"
wire input 320 \TXRATEMODE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:15156"
wire output 95 \TXRESETDONE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:15382"
wire width 7 input 321 \TXSEQUENCE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:15383"
wire input 322 \TXSWING
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:15384"
wire input 323 \TXSYNCALLIN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:15157"
wire output 96 \TXSYNCDONE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:15385"
wire input 324 \TXSYNCIN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:15386"
wire input 325 \TXSYNCMODE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:15158"
wire output 97 \TXSYNCOUT
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:15387"
wire width 2 input 326 \TXSYSCLKSEL
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:15388"
wire input 327 \TXUSERRDY
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:15389"
wire input 328 \TXUSRCLK
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:15390"
wire input 329 \TXUSRCLK2
end
attribute \blackbox 1
attribute \cells_not_processed 1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:15393"
module \GTHE3_COMMON
parameter \BIAS_CFG0
parameter \BIAS_CFG1
parameter \BIAS_CFG2
parameter \BIAS_CFG3
parameter \BIAS_CFG4
parameter \BIAS_CFG_RSVD
parameter \COMMON_CFG0
parameter \COMMON_CFG1
parameter \POR_CFG
parameter \QPLL0_CFG0
parameter \QPLL0_CFG1
parameter \QPLL0_CFG1_G3
parameter \QPLL0_CFG2
parameter \QPLL0_CFG2_G3
parameter \QPLL0_CFG3
parameter \QPLL0_CFG4
parameter \QPLL0_CP
parameter \QPLL0_CP_G3
parameter \QPLL0_FBDIV
parameter \QPLL0_FBDIV_G3
parameter \QPLL0_INIT_CFG0
parameter \QPLL0_INIT_CFG1
parameter \QPLL0_LOCK_CFG
parameter \QPLL0_LOCK_CFG_G3
parameter \QPLL0_LPF
parameter \QPLL0_LPF_G3
parameter \QPLL0_REFCLK_DIV
parameter \QPLL0_SDM_CFG0
parameter \QPLL0_SDM_CFG1
parameter \QPLL0_SDM_CFG2
parameter \QPLL1_CFG0
parameter \QPLL1_CFG1
parameter \QPLL1_CFG1_G3
parameter \QPLL1_CFG2
parameter \QPLL1_CFG2_G3
parameter \QPLL1_CFG3
parameter \QPLL1_CFG4
parameter \QPLL1_CP
parameter \QPLL1_CP_G3
parameter \QPLL1_FBDIV
parameter \QPLL1_FBDIV_G3
parameter \QPLL1_INIT_CFG0
parameter \QPLL1_INIT_CFG1
parameter \QPLL1_LOCK_CFG
parameter \QPLL1_LOCK_CFG_G3
parameter \QPLL1_LPF
parameter \QPLL1_LPF_G3
parameter \QPLL1_REFCLK_DIV
parameter \QPLL1_SDM_CFG0
parameter \QPLL1_SDM_CFG1
parameter \QPLL1_SDM_CFG2
parameter \RSVD_ATTR0
parameter \RSVD_ATTR1
parameter \RSVD_ATTR2
parameter \RSVD_ATTR3
parameter \RXRECCLKOUT0_SEL
parameter \RXRECCLKOUT1_SEL
parameter \SARC_EN
parameter \SARC_SEL
parameter \SDM0DATA1_0
parameter \SDM0DATA1_1
parameter \SDM0INITSEED0_0
parameter \SDM0INITSEED0_1
parameter \SDM0_DATA_PIN_SEL
parameter \SDM0_WIDTH_PIN_SEL
parameter \SDM1DATA1_0
parameter \SDM1DATA1_1
parameter \SDM1INITSEED0_0
parameter \SDM1INITSEED0_1
parameter \SDM1_DATA_PIN_SEL
parameter \SDM1_WIDTH_PIN_SEL
parameter \SIM_MODE
parameter \SIM_RESET_SPEEDUP
parameter \SIM_VERSION
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:15488"
wire input 21 \BGBYPASSB
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:15489"
wire input 22 \BGMONITORENB
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:15490"
wire input 23 \BGPDB
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:15491"
wire width 5 input 24 \BGRCALOVRD
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:15492"
wire input 25 \BGRCALOVRDENB
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:15493"
wire width 9 input 26 \DRPADDR
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:15494"
wire input 27 \DRPCLK
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:15495"
wire width 16 input 28 \DRPDI
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:15468"
wire width 16 output 1 \DRPDO
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:15496"
wire input 29 \DRPEN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:15469"
wire output 2 \DRPRDY
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:15497"
wire input 30 \DRPWE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:15498"
wire input 31 \GTGREFCLK0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:15499"
wire input 32 \GTGREFCLK1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:15500"
wire input 33 \GTNORTHREFCLK00
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:15501"
wire input 34 \GTNORTHREFCLK01
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:15502"
wire input 35 \GTNORTHREFCLK10
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:15503"
wire input 36 \GTNORTHREFCLK11
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:15504"
wire input 37 \GTREFCLK00
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:15505"
wire input 38 \GTREFCLK01
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:15506"
wire input 39 \GTREFCLK10
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:15507"
wire input 40 \GTREFCLK11
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:15508"
wire input 41 \GTSOUTHREFCLK00
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:15509"
wire input 42 \GTSOUTHREFCLK01
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:15510"
wire input 43 \GTSOUTHREFCLK10
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:15511"
wire input 44 \GTSOUTHREFCLK11
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:15512"
wire width 8 input 45 \PMARSVD0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:15513"
wire width 8 input 46 \PMARSVD1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:15470"
wire width 8 output 3 \PMARSVDOUT0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:15471"
wire width 8 output 4 \PMARSVDOUT1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:15514"
wire input 47 \QPLL0CLKRSVD0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:15515"
wire input 48 \QPLL0CLKRSVD1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:15472"
wire output 5 \QPLL0FBCLKLOST
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:15473"
wire output 6 \QPLL0LOCK
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:15516"
wire input 49 \QPLL0LOCKDETCLK
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:15517"
wire input 50 \QPLL0LOCKEN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:15474"
wire output 7 \QPLL0OUTCLK
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:15475"
wire output 8 \QPLL0OUTREFCLK
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:15518"
wire input 51 \QPLL0PD
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:15476"
wire output 9 \QPLL0REFCLKLOST
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:15519"
wire width 3 input 52 \QPLL0REFCLKSEL
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:15520"
wire input 53 \QPLL0RESET
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:15521"
wire input 54 \QPLL1CLKRSVD0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:15522"
wire input 55 \QPLL1CLKRSVD1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:15477"
wire output 10 \QPLL1FBCLKLOST
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:15478"
wire output 11 \QPLL1LOCK
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:15523"
wire input 56 \QPLL1LOCKDETCLK
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:15524"
wire input 57 \QPLL1LOCKEN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:15479"
wire output 12 \QPLL1OUTCLK
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:15480"
wire output 13 \QPLL1OUTREFCLK
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:15525"
wire input 58 \QPLL1PD
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:15481"
wire output 14 \QPLL1REFCLKLOST
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:15526"
wire width 3 input 59 \QPLL1REFCLKSEL
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:15527"
wire input 60 \QPLL1RESET
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:15482"
wire width 8 output 15 \QPLLDMONITOR0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:15483"
wire width 8 output 16 \QPLLDMONITOR1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:15528"
wire width 8 input 61 \QPLLRSVD1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:15529"
wire width 5 input 62 \QPLLRSVD2
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:15530"
wire width 5 input 63 \QPLLRSVD3
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:15531"
wire width 8 input 64 \QPLLRSVD4
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:15532"
wire input 65 \RCALENB
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:15484"
wire output 17 \REFCLKOUTMONITOR0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:15485"
wire output 18 \REFCLKOUTMONITOR1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:15486"
wire width 2 output 19 \RXRECCLK0_SEL
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:15487"
wire width 2 output 20 \RXRECCLK1_SEL
end
attribute \blackbox 1
attribute \cells_not_processed 1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:15535"
module \GTHE4_CHANNEL
parameter \ACJTAG_DEBUG_MODE
parameter \ACJTAG_MODE
parameter \ACJTAG_RESET
parameter \ADAPT_CFG0
parameter \ADAPT_CFG1
parameter \ADAPT_CFG2
parameter \ALIGN_COMMA_DOUBLE
parameter \ALIGN_COMMA_ENABLE
parameter \ALIGN_COMMA_WORD
parameter \ALIGN_MCOMMA_DET
parameter \ALIGN_MCOMMA_VALUE
parameter \ALIGN_PCOMMA_DET
parameter \ALIGN_PCOMMA_VALUE
parameter \A_RXOSCALRESET
parameter \A_RXPROGDIVRESET
parameter \A_RXTERMINATION
parameter \A_TXDIFFCTRL
parameter \A_TXPROGDIVRESET
parameter \CAPBYPASS_FORCE
parameter \CBCC_DATA_SOURCE_SEL
parameter \CDR_SWAP_MODE_EN
parameter \CFOK_PWRSVE_EN
parameter \CHAN_BOND_KEEP_ALIGN
parameter \CHAN_BOND_MAX_SKEW
parameter \CHAN_BOND_SEQ_1_1
parameter \CHAN_BOND_SEQ_1_2
parameter \CHAN_BOND_SEQ_1_3
parameter \CHAN_BOND_SEQ_1_4
parameter \CHAN_BOND_SEQ_1_ENABLE
parameter \CHAN_BOND_SEQ_2_1
parameter \CHAN_BOND_SEQ_2_2
parameter \CHAN_BOND_SEQ_2_3
parameter \CHAN_BOND_SEQ_2_4
parameter \CHAN_BOND_SEQ_2_ENABLE
parameter \CHAN_BOND_SEQ_2_USE
parameter \CHAN_BOND_SEQ_LEN
parameter \CH_HSPMUX
parameter \CKCAL1_CFG_0
parameter \CKCAL1_CFG_1
parameter \CKCAL1_CFG_2
parameter \CKCAL1_CFG_3
parameter \CKCAL2_CFG_0
parameter \CKCAL2_CFG_1
parameter \CKCAL2_CFG_2
parameter \CKCAL2_CFG_3
parameter \CKCAL2_CFG_4
parameter \CKCAL_RSVD0
parameter \CKCAL_RSVD1
parameter \CLK_CORRECT_USE
parameter \CLK_COR_KEEP_IDLE
parameter \CLK_COR_MAX_LAT
parameter \CLK_COR_MIN_LAT
parameter \CLK_COR_PRECEDENCE
parameter \CLK_COR_REPEAT_WAIT
parameter \CLK_COR_SEQ_1_1
parameter \CLK_COR_SEQ_1_2
parameter \CLK_COR_SEQ_1_3
parameter \CLK_COR_SEQ_1_4
parameter \CLK_COR_SEQ_1_ENABLE
parameter \CLK_COR_SEQ_2_1
parameter \CLK_COR_SEQ_2_2
parameter \CLK_COR_SEQ_2_3
parameter \CLK_COR_SEQ_2_4
parameter \CLK_COR_SEQ_2_ENABLE
parameter \CLK_COR_SEQ_2_USE
parameter \CLK_COR_SEQ_LEN
parameter \CPLL_CFG0
parameter \CPLL_CFG1
parameter \CPLL_CFG2
parameter \CPLL_CFG3
parameter \CPLL_FBDIV
parameter \CPLL_FBDIV_45
parameter \CPLL_INIT_CFG0
parameter \CPLL_LOCK_CFG
parameter \CPLL_REFCLK_DIV
parameter \CTLE3_OCAP_EXT_CTRL
parameter \CTLE3_OCAP_EXT_EN
parameter \DDI_CTRL
parameter \DDI_REALIGN_WAIT
parameter \DEC_MCOMMA_DETECT
parameter \DEC_PCOMMA_DETECT
parameter \DEC_VALID_COMMA_ONLY
parameter \DELAY_ELEC
parameter \DMONITOR_CFG0
parameter \DMONITOR_CFG1
parameter \ES_CLK_PHASE_SEL
parameter \ES_CONTROL
parameter \ES_ERRDET_EN
parameter \ES_EYE_SCAN_EN
parameter \ES_HORZ_OFFSET
parameter \ES_PRESCALE
parameter \ES_QUALIFIER0
parameter \ES_QUALIFIER1
parameter \ES_QUALIFIER2
parameter \ES_QUALIFIER3
parameter \ES_QUALIFIER4
parameter \ES_QUALIFIER5
parameter \ES_QUALIFIER6
parameter \ES_QUALIFIER7
parameter \ES_QUALIFIER8
parameter \ES_QUALIFIER9
parameter \ES_QUAL_MASK0
parameter \ES_QUAL_MASK1
parameter \ES_QUAL_MASK2
parameter \ES_QUAL_MASK3
parameter \ES_QUAL_MASK4
parameter \ES_QUAL_MASK5
parameter \ES_QUAL_MASK6
parameter \ES_QUAL_MASK7
parameter \ES_QUAL_MASK8
parameter \ES_QUAL_MASK9
parameter \ES_SDATA_MASK0
parameter \ES_SDATA_MASK1
parameter \ES_SDATA_MASK2
parameter \ES_SDATA_MASK3
parameter \ES_SDATA_MASK4
parameter \ES_SDATA_MASK5
parameter \ES_SDATA_MASK6
parameter \ES_SDATA_MASK7
parameter \ES_SDATA_MASK8
parameter \ES_SDATA_MASK9
parameter \EYE_SCAN_SWAP_EN
parameter \FTS_DESKEW_SEQ_ENABLE
parameter \FTS_LANE_DESKEW_CFG
parameter \FTS_LANE_DESKEW_EN
parameter \GEARBOX_MODE
parameter \ISCAN_CK_PH_SEL2
parameter \LOCAL_MASTER
parameter \LPBK_BIAS_CTRL
parameter \LPBK_EN_RCAL_B
parameter \LPBK_EXT_RCAL
parameter \LPBK_IND_CTRL0
parameter \LPBK_IND_CTRL1
parameter \LPBK_IND_CTRL2
parameter \LPBK_RG_CTRL
parameter \OOBDIVCTL
parameter \OOB_PWRUP
parameter \PCI3_AUTO_REALIGN
parameter \PCI3_PIPE_RX_ELECIDLE
parameter \PCI3_RX_ASYNC_EBUF_BYPASS
parameter \PCI3_RX_ELECIDLE_EI2_ENABLE
parameter \PCI3_RX_ELECIDLE_H2L_COUNT
parameter \PCI3_RX_ELECIDLE_H2L_DISABLE
parameter \PCI3_RX_ELECIDLE_HI_COUNT
parameter \PCI3_RX_ELECIDLE_LP4_DISABLE
parameter \PCI3_RX_FIFO_DISABLE
parameter \PCIE3_CLK_COR_EMPTY_THRSH
parameter \PCIE3_CLK_COR_FULL_THRSH
parameter \PCIE3_CLK_COR_MAX_LAT
parameter \PCIE3_CLK_COR_MIN_LAT
parameter \PCIE3_CLK_COR_THRSH_TIMER
parameter \PCIE_BUFG_DIV_CTRL
parameter \PCIE_PLL_SEL_MODE_GEN12
parameter \PCIE_PLL_SEL_MODE_GEN3
parameter \PCIE_PLL_SEL_MODE_GEN4
parameter \PCIE_RXPCS_CFG_GEN3
parameter \PCIE_RXPMA_CFG
parameter \PCIE_TXPCS_CFG_GEN3
parameter \PCIE_TXPMA_CFG
parameter \PCS_PCIE_EN
parameter \PCS_RSVD0
parameter \PD_TRANS_TIME_FROM_P2
parameter \PD_TRANS_TIME_NONE_P2
parameter \PD_TRANS_TIME_TO_P2
parameter \PREIQ_FREQ_BST
parameter \PROCESS_PAR
parameter \RATE_SW_USE_DRP
parameter \RCLK_SIPO_DLY_ENB
parameter \RCLK_SIPO_INV_EN
parameter \RESET_POWERSAVE_DISABLE
parameter \RTX_BUF_CML_CTRL
parameter \RTX_BUF_TERM_CTRL
parameter \RXBUFRESET_TIME
parameter \RXBUF_ADDR_MODE
parameter \RXBUF_EIDLE_HI_CNT
parameter \RXBUF_EIDLE_LO_CNT
parameter \RXBUF_EN
parameter \RXBUF_RESET_ON_CB_CHANGE
parameter \RXBUF_RESET_ON_COMMAALIGN
parameter \RXBUF_RESET_ON_EIDLE
parameter \RXBUF_RESET_ON_RATE_CHANGE
parameter \RXBUF_THRESH_OVFLW
parameter \RXBUF_THRESH_OVRD
parameter \RXBUF_THRESH_UNDFLW
parameter \RXCDRFREQRESET_TIME
parameter \RXCDRPHRESET_TIME
parameter \RXCDR_CFG0
parameter \RXCDR_CFG0_GEN3
parameter \RXCDR_CFG1
parameter \RXCDR_CFG1_GEN3
parameter \RXCDR_CFG2
parameter \RXCDR_CFG2_GEN2
parameter \RXCDR_CFG2_GEN3
parameter \RXCDR_CFG2_GEN4
parameter \RXCDR_CFG3
parameter \RXCDR_CFG3_GEN2
parameter \RXCDR_CFG3_GEN3
parameter \RXCDR_CFG3_GEN4
parameter \RXCDR_CFG4
parameter \RXCDR_CFG4_GEN3
parameter \RXCDR_CFG5
parameter \RXCDR_CFG5_GEN3
parameter \RXCDR_FR_RESET_ON_EIDLE
parameter \RXCDR_HOLD_DURING_EIDLE
parameter \RXCDR_LOCK_CFG0
parameter \RXCDR_LOCK_CFG1
parameter \RXCDR_LOCK_CFG2
parameter \RXCDR_LOCK_CFG3
parameter \RXCDR_LOCK_CFG4
parameter \RXCDR_PH_RESET_ON_EIDLE
parameter \RXCFOK_CFG0
parameter \RXCFOK_CFG1
parameter \RXCFOK_CFG2
parameter \RXCKCAL1_IQ_LOOP_RST_CFG
parameter \RXCKCAL1_I_LOOP_RST_CFG
parameter \RXCKCAL1_Q_LOOP_RST_CFG
parameter \RXCKCAL2_DX_LOOP_RST_CFG
parameter \RXCKCAL2_D_LOOP_RST_CFG
parameter \RXCKCAL2_S_LOOP_RST_CFG
parameter \RXCKCAL2_X_LOOP_RST_CFG
parameter \RXDFELPMRESET_TIME
parameter \RXDFELPM_KL_CFG0
parameter \RXDFELPM_KL_CFG1
parameter \RXDFELPM_KL_CFG2
parameter \RXDFE_CFG0
parameter \RXDFE_CFG1
parameter \RXDFE_GC_CFG0
parameter \RXDFE_GC_CFG1
parameter \RXDFE_GC_CFG2
parameter \RXDFE_H2_CFG0
parameter \RXDFE_H2_CFG1
parameter \RXDFE_H3_CFG0
parameter \RXDFE_H3_CFG1
parameter \RXDFE_H4_CFG0
parameter \RXDFE_H4_CFG1
parameter \RXDFE_H5_CFG0
parameter \RXDFE_H5_CFG1
parameter \RXDFE_H6_CFG0
parameter \RXDFE_H6_CFG1
parameter \RXDFE_H7_CFG0
parameter \RXDFE_H7_CFG1
parameter \RXDFE_H8_CFG0
parameter \RXDFE_H8_CFG1
parameter \RXDFE_H9_CFG0
parameter \RXDFE_H9_CFG1
parameter \RXDFE_HA_CFG0
parameter \RXDFE_HA_CFG1
parameter \RXDFE_HB_CFG0
parameter \RXDFE_HB_CFG1
parameter \RXDFE_HC_CFG0
parameter \RXDFE_HC_CFG1
parameter \RXDFE_HD_CFG0
parameter \RXDFE_HD_CFG1
parameter \RXDFE_HE_CFG0
parameter \RXDFE_HE_CFG1
parameter \RXDFE_HF_CFG0
parameter \RXDFE_HF_CFG1
parameter \RXDFE_KH_CFG0
parameter \RXDFE_KH_CFG1
parameter \RXDFE_KH_CFG2
parameter \RXDFE_KH_CFG3
parameter \RXDFE_OS_CFG0
parameter \RXDFE_OS_CFG1
parameter \RXDFE_PWR_SAVING
parameter \RXDFE_UT_CFG0
parameter \RXDFE_UT_CFG1
parameter \RXDFE_UT_CFG2
parameter \RXDFE_VP_CFG0
parameter \RXDFE_VP_CFG1
parameter \RXDLY_CFG
parameter \RXDLY_LCFG
parameter \RXELECIDLE_CFG
parameter \RXGBOX_FIFO_INIT_RD_ADDR
parameter \RXGEARBOX_EN
parameter \RXISCANRESET_TIME
parameter \RXLPM_CFG
parameter \RXLPM_GC_CFG
parameter \RXLPM_KH_CFG0
parameter \RXLPM_KH_CFG1
parameter \RXLPM_OS_CFG0
parameter \RXLPM_OS_CFG1
parameter \RXOOB_CFG
parameter \RXOOB_CLK_CFG
parameter \RXOSCALRESET_TIME
parameter \RXOUT_DIV
parameter \RXPCSRESET_TIME
parameter \RXPHBEACON_CFG
parameter \RXPHDLY_CFG
parameter \RXPHSAMP_CFG
parameter \RXPHSLIP_CFG
parameter \RXPH_MONITOR_SEL
parameter \RXPI_AUTO_BW_SEL_BYPASS
parameter \RXPI_CFG0
parameter \RXPI_CFG1
parameter \RXPI_LPM
parameter \RXPI_SEL_LC
parameter \RXPI_STARTCODE
parameter \RXPI_VREFSEL
parameter \RXPMACLK_SEL
parameter \RXPMARESET_TIME
parameter \RXPRBS_ERR_LOOPBACK
parameter \RXPRBS_LINKACQ_CNT
parameter \RXREFCLKDIV2_SEL
parameter \RXSLIDE_AUTO_WAIT
parameter \RXSLIDE_MODE
parameter \RXSYNC_MULTILANE
parameter \RXSYNC_OVRD
parameter \RXSYNC_SKIP_DA
parameter \RX_AFE_CM_EN
parameter \RX_BIAS_CFG0
parameter \RX_BUFFER_CFG
parameter \RX_CAPFF_SARC_ENB
parameter \RX_CLK25_DIV
parameter \RX_CLKMUX_EN
parameter \RX_CLK_SLIP_OVRD
parameter \RX_CM_BUF_CFG
parameter \RX_CM_BUF_PD
parameter \RX_CM_SEL
parameter \RX_CM_TRIM
parameter \RX_CTLE3_LPF
parameter \RX_DATA_WIDTH
parameter \RX_DDI_SEL
parameter \RX_DEFER_RESET_BUF_EN
parameter \RX_DEGEN_CTRL
parameter \RX_DFELPM_CFG0
parameter \RX_DFELPM_CFG1
parameter \RX_DFELPM_KLKH_AGC_STUP_EN
parameter \RX_DFE_AGC_CFG0
parameter \RX_DFE_AGC_CFG1
parameter \RX_DFE_KL_LPM_KH_CFG0
parameter \RX_DFE_KL_LPM_KH_CFG1
parameter \RX_DFE_KL_LPM_KL_CFG0
parameter \RX_DFE_KL_LPM_KL_CFG1
parameter \RX_DFE_LPM_HOLD_DURING_EIDLE
parameter \RX_DISPERR_SEQ_MATCH
parameter \RX_DIV2_MODE_B
parameter \RX_DIVRESET_TIME
parameter \RX_EN_CTLE_RCAL_B
parameter \RX_EN_HI_LR
parameter \RX_EXT_RL_CTRL
parameter \RX_EYESCAN_VS_CODE
parameter \RX_EYESCAN_VS_NEG_DIR
parameter \RX_EYESCAN_VS_RANGE
parameter \RX_EYESCAN_VS_UT_SIGN
parameter \RX_FABINT_USRCLK_FLOP
parameter \RX_INT_DATAWIDTH
parameter \RX_PMA_POWER_SAVE
parameter \RX_PMA_RSV0
parameter \RX_PROGDIV_CFG
parameter \RX_PROGDIV_RATE
parameter \RX_RESLOAD_CTRL
parameter \RX_RESLOAD_OVRD
parameter \RX_SAMPLE_PERIOD
parameter \RX_SIG_VALID_DLY
parameter \RX_SUM_DFETAPREP_EN
parameter \RX_SUM_IREF_TUNE
parameter \RX_SUM_RESLOAD_CTRL
parameter \RX_SUM_VCMTUNE
parameter \RX_SUM_VCM_OVWR
parameter \RX_SUM_VREF_TUNE
parameter \RX_TUNE_AFE_OS
parameter \RX_VREG_CTRL
parameter \RX_VREG_PDB
parameter \RX_WIDEMODE_CDR
parameter \RX_WIDEMODE_CDR_GEN3
parameter \RX_WIDEMODE_CDR_GEN4
parameter \RX_XCLK_SEL
parameter \RX_XMODE_SEL
parameter \SAMPLE_CLK_PHASE
parameter \SAS_12G_MODE
parameter \SATA_BURST_SEQ_LEN
parameter \SATA_BURST_VAL
parameter \SATA_CPLL_CFG
parameter \SATA_EIDLE_VAL
parameter \SHOW_REALIGN_COMMA
parameter \SIM_DEVICE
parameter \SIM_MODE
parameter \SIM_RECEIVER_DETECT_PASS
parameter \SIM_RESET_SPEEDUP
parameter \SIM_TX_EIDLE_DRIVE_LEVEL
parameter \SRSTMODE
parameter \TAPDLY_SET_TX
parameter \TEMPERATURE_PAR
parameter \TERM_RCAL_CFG
parameter \TERM_RCAL_OVRD
parameter \TRANS_TIME_RATE
parameter \TST_RSV0
parameter \TST_RSV1
parameter \TXBUF_EN
parameter \TXBUF_RESET_ON_RATE_CHANGE
parameter \TXDLY_CFG
parameter \TXDLY_LCFG
parameter \TXDRVBIAS_N
parameter \TXFIFO_ADDR_CFG
parameter \TXGBOX_FIFO_INIT_RD_ADDR
parameter \TXGEARBOX_EN
parameter \TXOUT_DIV
parameter \TXPCSRESET_TIME
parameter \TXPHDLY_CFG0
parameter \TXPHDLY_CFG1
parameter \TXPH_CFG
parameter \TXPH_CFG2
parameter \TXPH_MONITOR_SEL
parameter \TXPI_CFG
parameter \TXPI_CFG0
parameter \TXPI_CFG1
parameter \TXPI_CFG2
parameter \TXPI_CFG3
parameter \TXPI_CFG4
parameter \TXPI_CFG5
parameter \TXPI_GRAY_SEL
parameter \TXPI_INVSTROBE_SEL
parameter \TXPI_LPM
parameter \TXPI_PPM
parameter \TXPI_PPMCLK_SEL
parameter \TXPI_PPM_CFG
parameter \TXPI_SYNFREQ_PPM
parameter \TXPI_VREFSEL
parameter \TXPMARESET_TIME
parameter \TXREFCLKDIV2_SEL
parameter \TXSYNC_MULTILANE
parameter \TXSYNC_OVRD
parameter \TXSYNC_SKIP_DA
parameter \TX_CLK25_DIV
parameter \TX_CLKMUX_EN
parameter \TX_DATA_WIDTH
parameter \TX_DCC_LOOP_RST_CFG
parameter \TX_DEEMPH0
parameter \TX_DEEMPH1
parameter \TX_DEEMPH2
parameter \TX_DEEMPH3
parameter \TX_DIVRESET_TIME
parameter \TX_DRIVE_MODE
parameter \TX_DRVMUX_CTRL
parameter \TX_EIDLE_ASSERT_DELAY
parameter \TX_EIDLE_DEASSERT_DELAY
parameter \TX_FABINT_USRCLK_FLOP
parameter \TX_FIFO_BYP_EN
parameter \TX_IDLE_DATA_ZERO
parameter \TX_INT_DATAWIDTH
parameter \TX_LOOPBACK_DRIVE_HIZ
parameter \TX_MAINCURSOR_SEL
parameter \TX_MARGIN_FULL_0
parameter \TX_MARGIN_FULL_1
parameter \TX_MARGIN_FULL_2
parameter \TX_MARGIN_FULL_3
parameter \TX_MARGIN_FULL_4
parameter \TX_MARGIN_LOW_0
parameter \TX_MARGIN_LOW_1
parameter \TX_MARGIN_LOW_2
parameter \TX_MARGIN_LOW_3
parameter \TX_MARGIN_LOW_4
parameter \TX_PHICAL_CFG0
parameter \TX_PHICAL_CFG1
parameter \TX_PHICAL_CFG2
parameter \TX_PI_BIASSET
parameter \TX_PI_IBIAS_MID
parameter \TX_PMADATA_OPT
parameter \TX_PMA_POWER_SAVE
parameter \TX_PMA_RSV0
parameter \TX_PREDRV_CTRL
parameter \TX_PROGCLK_SEL
parameter \TX_PROGDIV_CFG
parameter \TX_PROGDIV_RATE
parameter \TX_QPI_STATUS_EN
parameter \TX_RXDETECT_CFG
parameter \TX_RXDETECT_REF
parameter \TX_SAMPLE_PERIOD
parameter \TX_SARC_LPBK_ENB
parameter \TX_SW_MEAS
parameter \TX_VREG_CTRL
parameter \TX_VREG_PDB
parameter \TX_VREG_VREFSEL
parameter \TX_XCLK_SEL
parameter \USB_BOTH_BURST_IDLE
parameter \USB_BURSTMAX_U3WAKE
parameter \USB_BURSTMIN_U3WAKE
parameter \USB_CLK_COR_EQ_EN
parameter \USB_EXT_CNTL
parameter \USB_IDLEMAX_POLLING
parameter \USB_IDLEMIN_POLLING
parameter \USB_LFPSPING_BURST
parameter \USB_LFPSPOLLING_BURST
parameter \USB_LFPSPOLLING_IDLE_MS
parameter \USB_LFPSU1EXIT_BURST
parameter \USB_LFPSU2LPEXIT_BURST_MS
parameter \USB_LFPSU3WAKE_BURST_MS
parameter \USB_LFPS_TPERIOD
parameter \USB_LFPS_TPERIOD_ACCURATE
parameter \USB_MODE
parameter \USB_PCIE_ERR_REP_DIS
parameter \USB_PING_SATA_MAX_INIT
parameter \USB_PING_SATA_MIN_INIT
parameter \USB_POLL_SATA_MAX_BURST
parameter \USB_POLL_SATA_MIN_BURST
parameter \USB_RAW_ELEC
parameter \USB_RXIDLE_P0_CTRL
parameter \USB_TXIDLE_TUNE_ENABLE
parameter \USB_U1_SATA_MAX_WAKE
parameter \USB_U1_SATA_MIN_WAKE
parameter \USB_U2_SAS_MAX_COM
parameter \USB_U2_SAS_MIN_COM
parameter \USE_PCS_CLK_PHASE_SEL
parameter \Y_ALL_MODE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16040"
wire output 1 \BUFGTCE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16041"
wire width 3 output 2 \BUFGTCEMASK
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16042"
wire width 9 output 3 \BUFGTDIV
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16043"
wire output 4 \BUFGTRESET
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16044"
wire width 3 output 5 \BUFGTRSTMASK
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16144"
wire input 105 \CDRSTEPDIR
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16145"
wire input 106 \CDRSTEPSQ
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16146"
wire input 107 \CDRSTEPSX
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16147"
wire input 108 \CFGRESET
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16148"
wire input 109 \CLKRSVD0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16149"
wire input 110 \CLKRSVD1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16045"
wire output 6 \CPLLFBCLKLOST
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16150"
wire input 111 \CPLLFREQLOCK
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16046"
wire output 7 \CPLLLOCK
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16151"
wire input 112 \CPLLLOCKDETCLK
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16152"
wire input 113 \CPLLLOCKEN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16153"
wire input 114 \CPLLPD
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16047"
wire output 8 \CPLLREFCLKLOST
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16154"
wire width 3 input 115 \CPLLREFCLKSEL
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16155"
wire input 116 \CPLLRESET
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16156"
wire input 117 \DMONFIFORESET
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16157"
wire input 118 \DMONITORCLK
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16048"
wire width 16 output 9 \DMONITOROUT
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16049"
wire output 10 \DMONITOROUTCLK
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16158"
wire width 10 input 119 \DRPADDR
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16159"
wire input 120 \DRPCLK
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16160"
wire width 16 input 121 \DRPDI
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16050"
wire width 16 output 11 \DRPDO
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16161"
wire input 122 \DRPEN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16051"
wire output 12 \DRPRDY
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16162"
wire input 123 \DRPRST
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16163"
wire input 124 \DRPWE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16052"
wire output 13 \EYESCANDATAERROR
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16164"
wire input 125 \EYESCANRESET
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16165"
wire input 126 \EYESCANTRIGGER
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16166"
wire input 127 \FREQOS
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16167"
wire input 128 \GTGREFCLK
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16168"
wire input 129 \GTHRXN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16169"
wire input 130 \GTHRXP
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16053"
wire output 14 \GTHTXN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16054"
wire output 15 \GTHTXP
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16170"
wire input 131 \GTNORTHREFCLK0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16171"
wire input 132 \GTNORTHREFCLK1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16055"
wire output 16 \GTPOWERGOOD
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16172"
wire input 133 \GTREFCLK0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16173"
wire input 134 \GTREFCLK1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16056"
wire output 17 \GTREFCLKMONITOR
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16174"
wire width 16 input 135 \GTRSVD
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16175"
wire input 136 \GTRXRESET
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16176"
wire input 137 \GTRXRESETSEL
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16177"
wire input 138 \GTSOUTHREFCLK0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16178"
wire input 139 \GTSOUTHREFCLK1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16179"
wire input 140 \GTTXRESET
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16180"
wire input 141 \GTTXRESETSEL
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16181"
wire input 142 \INCPCTRL
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16182"
wire width 3 input 143 \LOOPBACK
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16183"
wire input 144 \PCIEEQRXEQADAPTDONE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16057"
wire output 18 \PCIERATEGEN3
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16058"
wire output 19 \PCIERATEIDLE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16059"
wire width 2 output 20 \PCIERATEQPLLPD
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16060"
wire width 2 output 21 \PCIERATEQPLLRESET
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16184"
wire input 145 \PCIERSTIDLE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16185"
wire input 146 \PCIERSTTXSYNCSTART
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16061"
wire output 22 \PCIESYNCTXSYNCDONE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16062"
wire output 23 \PCIEUSERGEN3RDY
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16063"
wire output 24 \PCIEUSERPHYSTATUSRST
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16186"
wire input 147 \PCIEUSERRATEDONE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16064"
wire output 25 \PCIEUSERRATESTART
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16187"
wire width 16 input 148 \PCSRSVDIN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16065"
wire width 16 output 26 \PCSRSVDOUT
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16066"
wire output 27 \PHYSTATUS
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16067"
wire width 16 output 28 \PINRSRVDAS
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16068"
wire output 29 \POWERPRESENT
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16188"
wire input 149 \QPLL0CLK
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16189"
wire input 150 \QPLL0FREQLOCK
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16190"
wire input 151 \QPLL0REFCLK
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16191"
wire input 152 \QPLL1CLK
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16192"
wire input 153 \QPLL1FREQLOCK
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16193"
wire input 154 \QPLL1REFCLK
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16069"
wire output 30 \RESETEXCEPTION
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16194"
wire input 155 \RESETOVRD
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16195"
wire input 156 \RX8B10BEN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16196"
wire input 157 \RXAFECFOKEN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16197"
wire input 158 \RXBUFRESET
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16070"
wire width 3 output 31 \RXBUFSTATUS
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16071"
wire output 32 \RXBYTEISALIGNED
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16072"
wire output 33 \RXBYTEREALIGN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16198"
wire input 159 \RXCDRFREQRESET
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16199"
wire input 160 \RXCDRHOLD
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16073"
wire output 34 \RXCDRLOCK
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16200"
wire input 161 \RXCDROVRDEN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16074"
wire output 35 \RXCDRPHDONE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16201"
wire input 162 \RXCDRRESET
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16075"
wire output 36 \RXCHANBONDSEQ
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16076"
wire output 37 \RXCHANISALIGNED
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16077"
wire output 38 \RXCHANREALIGN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16202"
wire input 163 \RXCHBONDEN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16203"
wire width 5 input 164 \RXCHBONDI
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16204"
wire width 3 input 165 \RXCHBONDLEVEL
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16205"
wire input 166 \RXCHBONDMASTER
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16078"
wire width 5 output 39 \RXCHBONDO
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16206"
wire input 167 \RXCHBONDSLAVE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16079"
wire output 40 \RXCKCALDONE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16207"
wire input 168 \RXCKCALRESET
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16208"
wire width 7 input 169 \RXCKCALSTART
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16080"
wire width 2 output 41 \RXCLKCORCNT
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16081"
wire output 42 \RXCOMINITDET
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16082"
wire output 43 \RXCOMMADET
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16209"
wire input 170 \RXCOMMADETEN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16083"
wire output 44 \RXCOMSASDET
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16084"
wire output 45 \RXCOMWAKEDET
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16085"
wire width 16 output 46 \RXCTRL0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16086"
wire width 16 output 47 \RXCTRL1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16087"
wire width 8 output 48 \RXCTRL2
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16088"
wire width 8 output 49 \RXCTRL3
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16089"
wire width 128 output 50 \RXDATA
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16090"
wire width 8 output 51 \RXDATAEXTENDRSVD
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16091"
wire width 2 output 52 \RXDATAVALID
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16210"
wire width 2 input 171 \RXDFEAGCCTRL
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16211"
wire input 172 \RXDFEAGCHOLD
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16212"
wire input 173 \RXDFEAGCOVRDEN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16213"
wire width 4 input 174 \RXDFECFOKFCNUM
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16214"
wire input 175 \RXDFECFOKFEN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16215"
wire input 176 \RXDFECFOKFPULSE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16216"
wire input 177 \RXDFECFOKHOLD
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16217"
wire input 178 \RXDFECFOKOVREN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16218"
wire input 179 \RXDFEKHHOLD
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16219"
wire input 180 \RXDFEKHOVRDEN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16220"
wire input 181 \RXDFELFHOLD
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16221"
wire input 182 \RXDFELFOVRDEN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16222"
wire input 183 \RXDFELPMRESET
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16223"
wire input 184 \RXDFETAP10HOLD
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16224"
wire input 185 \RXDFETAP10OVRDEN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16225"
wire input 186 \RXDFETAP11HOLD
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16226"
wire input 187 \RXDFETAP11OVRDEN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16227"
wire input 188 \RXDFETAP12HOLD
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16228"
wire input 189 \RXDFETAP12OVRDEN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16229"
wire input 190 \RXDFETAP13HOLD
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16230"
wire input 191 \RXDFETAP13OVRDEN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16231"
wire input 192 \RXDFETAP14HOLD
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16232"
wire input 193 \RXDFETAP14OVRDEN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16233"
wire input 194 \RXDFETAP15HOLD
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16234"
wire input 195 \RXDFETAP15OVRDEN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16235"
wire input 196 \RXDFETAP2HOLD
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16236"
wire input 197 \RXDFETAP2OVRDEN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16237"
wire input 198 \RXDFETAP3HOLD
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16238"
wire input 199 \RXDFETAP3OVRDEN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16239"
wire input 200 \RXDFETAP4HOLD
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16240"
wire input 201 \RXDFETAP4OVRDEN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16241"
wire input 202 \RXDFETAP5HOLD
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16242"
wire input 203 \RXDFETAP5OVRDEN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16243"
wire input 204 \RXDFETAP6HOLD
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16244"
wire input 205 \RXDFETAP6OVRDEN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16245"
wire input 206 \RXDFETAP7HOLD
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16246"
wire input 207 \RXDFETAP7OVRDEN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16247"
wire input 208 \RXDFETAP8HOLD
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16248"
wire input 209 \RXDFETAP8OVRDEN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16249"
wire input 210 \RXDFETAP9HOLD
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16250"
wire input 211 \RXDFETAP9OVRDEN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16251"
wire input 212 \RXDFEUTHOLD
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16252"
wire input 213 \RXDFEUTOVRDEN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16253"
wire input 214 \RXDFEVPHOLD
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16254"
wire input 215 \RXDFEVPOVRDEN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16255"
wire input 216 \RXDFEXYDEN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16256"
wire input 217 \RXDLYBYPASS
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16257"
wire input 218 \RXDLYEN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16258"
wire input 219 \RXDLYOVRDEN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16259"
wire input 220 \RXDLYSRESET
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16092"
wire output 53 \RXDLYSRESETDONE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16093"
wire output 54 \RXELECIDLE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16260"
wire width 2 input 221 \RXELECIDLEMODE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16261"
wire input 222 \RXEQTRAINING
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16262"
wire input 223 \RXGEARBOXSLIP
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16094"
wire width 6 output 55 \RXHEADER
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16095"
wire width 2 output 56 \RXHEADERVALID
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16263"
wire input 224 \RXLATCLK
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16096"
wire output 57 \RXLFPSTRESETDET
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16097"
wire output 58 \RXLFPSU2LPEXITDET
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16098"
wire output 59 \RXLFPSU3WAKEDET
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16264"
wire input 225 \RXLPMEN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16265"
wire input 226 \RXLPMGCHOLD
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16266"
wire input 227 \RXLPMGCOVRDEN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16267"
wire input 228 \RXLPMHFHOLD
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16268"
wire input 229 \RXLPMHFOVRDEN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16269"
wire input 230 \RXLPMLFHOLD
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16270"
wire input 231 \RXLPMLFKLOVRDEN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16271"
wire input 232 \RXLPMOSHOLD
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16272"
wire input 233 \RXLPMOSOVRDEN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16273"
wire input 234 \RXMCOMMAALIGNEN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16099"
wire width 8 output 60 \RXMONITOROUT
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16274"
wire width 2 input 235 \RXMONITORSEL
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16275"
wire input 236 \RXOOBRESET
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16276"
wire input 237 \RXOSCALRESET
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16277"
wire input 238 \RXOSHOLD
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16100"
wire output 61 \RXOSINTDONE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16101"
wire output 62 \RXOSINTSTARTED
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16102"
wire output 63 \RXOSINTSTROBEDONE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16103"
wire output 64 \RXOSINTSTROBESTARTED
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16278"
wire input 239 \RXOSOVRDEN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16104"
wire output 65 \RXOUTCLK
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16105"
wire output 66 \RXOUTCLKFABRIC
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16106"
wire output 67 \RXOUTCLKPCS
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16279"
wire width 3 input 240 \RXOUTCLKSEL
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16280"
wire input 241 \RXPCOMMAALIGNEN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16281"
wire input 242 \RXPCSRESET
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16282"
wire width 2 input 243 \RXPD
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16283"
wire input 244 \RXPHALIGN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16107"
wire output 68 \RXPHALIGNDONE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16284"
wire input 245 \RXPHALIGNEN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16108"
wire output 69 \RXPHALIGNERR
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16285"
wire input 246 \RXPHDLYPD
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16286"
wire input 247 \RXPHDLYRESET
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16287"
wire input 248 \RXPHOVRDEN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16288"
wire width 2 input 249 \RXPLLCLKSEL
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16289"
wire input 250 \RXPMARESET
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16109"
wire output 70 \RXPMARESETDONE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16290"
wire input 251 \RXPOLARITY
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16291"
wire input 252 \RXPRBSCNTRESET
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16110"
wire output 71 \RXPRBSERR
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16111"
wire output 72 \RXPRBSLOCKED
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16292"
wire width 4 input 253 \RXPRBSSEL
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16112"
wire output 73 \RXPRGDIVRESETDONE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16293"
wire input 254 \RXPROGDIVRESET
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16294"
wire input 255 \RXQPIEN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16113"
wire output 74 \RXQPISENN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16114"
wire output 75 \RXQPISENP
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16295"
wire width 3 input 256 \RXRATE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16115"
wire output 76 \RXRATEDONE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16296"
wire input 257 \RXRATEMODE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16116"
wire output 77 \RXRECCLKOUT
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16117"
wire output 78 \RXRESETDONE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16297"
wire input 258 \RXSLIDE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16118"
wire output 79 \RXSLIDERDY
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16119"
wire output 80 \RXSLIPDONE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16298"
wire input 259 \RXSLIPOUTCLK
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16120"
wire output 81 \RXSLIPOUTCLKRDY
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16299"
wire input 260 \RXSLIPPMA
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16121"
wire output 82 \RXSLIPPMARDY
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16122"
wire width 2 output 83 \RXSTARTOFSEQ
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16123"
wire width 3 output 84 \RXSTATUS
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16300"
wire input 261 \RXSYNCALLIN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16124"
wire output 85 \RXSYNCDONE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16301"
wire input 262 \RXSYNCIN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16302"
wire input 263 \RXSYNCMODE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16125"
wire output 86 \RXSYNCOUT
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16303"
wire width 2 input 264 \RXSYSCLKSEL
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16304"
wire input 265 \RXTERMINATION
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16305"
wire input 266 \RXUSERRDY
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16306"
wire input 267 \RXUSRCLK
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16307"
wire input 268 \RXUSRCLK2
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16126"
wire output 87 \RXVALID
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16308"
wire input 269 \SIGVALIDCLK
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16309"
wire width 20 input 270 \TSTIN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16310"
wire width 8 input 271 \TX8B10BBYPASS
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16311"
wire input 272 \TX8B10BEN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16127"
wire width 2 output 88 \TXBUFSTATUS
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16128"
wire output 89 \TXCOMFINISH
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16312"
wire input 273 \TXCOMINIT
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16313"
wire input 274 \TXCOMSAS
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16314"
wire input 275 \TXCOMWAKE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16315"
wire width 16 input 276 \TXCTRL0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16316"
wire width 16 input 277 \TXCTRL1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16317"
wire width 8 input 278 \TXCTRL2
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16318"
wire width 128 input 279 \TXDATA
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16319"
wire width 8 input 280 \TXDATAEXTENDRSVD
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16129"
wire output 90 \TXDCCDONE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16320"
wire input 281 \TXDCCFORCESTART
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16321"
wire input 282 \TXDCCRESET
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16322"
wire width 2 input 283 \TXDEEMPH
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16323"
wire input 284 \TXDETECTRX
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16324"
wire width 5 input 285 \TXDIFFCTRL
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16325"
wire input 286 \TXDLYBYPASS
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16326"
wire input 287 \TXDLYEN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16327"
wire input 288 \TXDLYHOLD
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16328"
wire input 289 \TXDLYOVRDEN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16329"
wire input 290 \TXDLYSRESET
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16130"
wire output 91 \TXDLYSRESETDONE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16330"
wire input 291 \TXDLYUPDOWN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16331"
wire input 292 \TXELECIDLE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16332"
wire width 6 input 293 \TXHEADER
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16333"
wire input 294 \TXINHIBIT
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16334"
wire input 295 \TXLATCLK
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16335"
wire input 296 \TXLFPSTRESET
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16336"
wire input 297 \TXLFPSU2LPEXIT
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16337"
wire input 298 \TXLFPSU3WAKE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16338"
wire width 7 input 299 \TXMAINCURSOR
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16339"
wire width 3 input 300 \TXMARGIN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16340"
wire input 301 \TXMUXDCDEXHOLD
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16341"
wire input 302 \TXMUXDCDORWREN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16342"
wire input 303 \TXONESZEROS
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16131"
wire output 92 \TXOUTCLK
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16132"
wire output 93 \TXOUTCLKFABRIC
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16133"
wire output 94 \TXOUTCLKPCS
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16343"
wire width 3 input 304 \TXOUTCLKSEL
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16344"
wire input 305 \TXPCSRESET
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16345"
wire width 2 input 306 \TXPD
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16346"
wire input 307 \TXPDELECIDLEMODE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16347"
wire input 308 \TXPHALIGN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16134"
wire output 95 \TXPHALIGNDONE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16348"
wire input 309 \TXPHALIGNEN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16349"
wire input 310 \TXPHDLYPD
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16350"
wire input 311 \TXPHDLYRESET
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16351"
wire input 312 \TXPHDLYTSTCLK
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16352"
wire input 313 \TXPHINIT
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16135"
wire output 96 \TXPHINITDONE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16353"
wire input 314 \TXPHOVRDEN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16354"
wire input 315 \TXPIPPMEN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16355"
wire input 316 \TXPIPPMOVRDEN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16356"
wire input 317 \TXPIPPMPD
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16357"
wire input 318 \TXPIPPMSEL
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16358"
wire width 5 input 319 \TXPIPPMSTEPSIZE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16359"
wire input 320 \TXPISOPD
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16360"
wire width 2 input 321 \TXPLLCLKSEL
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16361"
wire input 322 \TXPMARESET
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16136"
wire output 97 \TXPMARESETDONE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16362"
wire input 323 \TXPOLARITY
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16363"
wire width 5 input 324 \TXPOSTCURSOR
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16364"
wire input 325 \TXPRBSFORCEERR
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16365"
wire width 4 input 326 \TXPRBSSEL
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16366"
wire width 5 input 327 \TXPRECURSOR
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16137"
wire output 98 \TXPRGDIVRESETDONE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16367"
wire input 328 \TXPROGDIVRESET
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16368"
wire input 329 \TXQPIBIASEN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16138"
wire output 99 \TXQPISENN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16139"
wire output 100 \TXQPISENP
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16369"
wire input 330 \TXQPIWEAKPUP
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16370"
wire width 3 input 331 \TXRATE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16140"
wire output 101 \TXRATEDONE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16371"
wire input 332 \TXRATEMODE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16141"
wire output 102 \TXRESETDONE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16372"
wire width 7 input 333 \TXSEQUENCE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16373"
wire input 334 \TXSWING
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16374"
wire input 335 \TXSYNCALLIN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16142"
wire output 103 \TXSYNCDONE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16375"
wire input 336 \TXSYNCIN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16376"
wire input 337 \TXSYNCMODE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16143"
wire output 104 \TXSYNCOUT
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16377"
wire width 2 input 338 \TXSYSCLKSEL
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16378"
wire input 339 \TXUSERRDY
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16379"
wire input 340 \TXUSRCLK
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16380"
wire input 341 \TXUSRCLK2
end
attribute \blackbox 1
attribute \cells_not_processed 1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16383"
module \GTHE4_COMMON
parameter \AEN_QPLL0_FBDIV
parameter \AEN_QPLL1_FBDIV
parameter \AEN_SDM0TOGGLE
parameter \AEN_SDM1TOGGLE
parameter \A_SDM0TOGGLE
parameter \A_SDM1DATA_HIGH
parameter \A_SDM1DATA_LOW
parameter \A_SDM1TOGGLE
parameter \BIAS_CFG0
parameter \BIAS_CFG1
parameter \BIAS_CFG2
parameter \BIAS_CFG3
parameter \BIAS_CFG4
parameter \BIAS_CFG_RSVD
parameter \COMMON_CFG0
parameter \COMMON_CFG1
parameter \POR_CFG
parameter \PPF0_CFG
parameter \PPF1_CFG
parameter \QPLL0CLKOUT_RATE
parameter \QPLL0_CFG0
parameter \QPLL0_CFG1
parameter \QPLL0_CFG1_G3
parameter \QPLL0_CFG2
parameter \QPLL0_CFG2_G3
parameter \QPLL0_CFG3
parameter \QPLL0_CFG4
parameter \QPLL0_CP
parameter \QPLL0_CP_G3
parameter \QPLL0_FBDIV
parameter \QPLL0_FBDIV_G3
parameter \QPLL0_INIT_CFG0
parameter \QPLL0_INIT_CFG1
parameter \QPLL0_LOCK_CFG
parameter \QPLL0_LOCK_CFG_G3
parameter \QPLL0_LPF
parameter \QPLL0_LPF_G3
parameter \QPLL0_PCI_EN
parameter \QPLL0_RATE_SW_USE_DRP
parameter \QPLL0_REFCLK_DIV
parameter \QPLL0_SDM_CFG0
parameter \QPLL0_SDM_CFG1
parameter \QPLL0_SDM_CFG2
parameter \QPLL1CLKOUT_RATE
parameter \QPLL1_CFG0
parameter \QPLL1_CFG1
parameter \QPLL1_CFG1_G3
parameter \QPLL1_CFG2
parameter \QPLL1_CFG2_G3
parameter \QPLL1_CFG3
parameter \QPLL1_CFG4
parameter \QPLL1_CP
parameter \QPLL1_CP_G3
parameter \QPLL1_FBDIV
parameter \QPLL1_FBDIV_G3
parameter \QPLL1_INIT_CFG0
parameter \QPLL1_INIT_CFG1
parameter \QPLL1_LOCK_CFG
parameter \QPLL1_LOCK_CFG_G3
parameter \QPLL1_LPF
parameter \QPLL1_LPF_G3
parameter \QPLL1_PCI_EN
parameter \QPLL1_RATE_SW_USE_DRP
parameter \QPLL1_REFCLK_DIV
parameter \QPLL1_SDM_CFG0
parameter \QPLL1_SDM_CFG1
parameter \QPLL1_SDM_CFG2
parameter \RSVD_ATTR0
parameter \RSVD_ATTR1
parameter \RSVD_ATTR2
parameter \RSVD_ATTR3
parameter \RXRECCLKOUT0_SEL
parameter \RXRECCLKOUT1_SEL
parameter \SARC_ENB
parameter \SARC_SEL
parameter \SDM0INITSEED0_0
parameter \SDM0INITSEED0_1
parameter \SDM1INITSEED0_0
parameter \SDM1INITSEED0_1
parameter \SIM_DEVICE
parameter \SIM_MODE
parameter \SIM_RESET_SPEEDUP
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16492"
wire input 27 \BGBYPASSB
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16493"
wire input 28 \BGMONITORENB
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16494"
wire input 29 \BGPDB
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16495"
wire width 5 input 30 \BGRCALOVRD
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16496"
wire input 31 \BGRCALOVRDENB
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16497"
wire width 16 input 32 \DRPADDR
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16498"
wire input 33 \DRPCLK
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16499"
wire width 16 input 34 \DRPDI
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16466"
wire width 16 output 1 \DRPDO
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16500"
wire input 35 \DRPEN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16467"
wire output 2 \DRPRDY
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16501"
wire input 36 \DRPWE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16502"
wire input 37 \GTGREFCLK0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16503"
wire input 38 \GTGREFCLK1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16504"
wire input 39 \GTNORTHREFCLK00
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16505"
wire input 40 \GTNORTHREFCLK01
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16506"
wire input 41 \GTNORTHREFCLK10
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16507"
wire input 42 \GTNORTHREFCLK11
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16508"
wire input 43 \GTREFCLK00
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16509"
wire input 44 \GTREFCLK01
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16510"
wire input 45 \GTREFCLK10
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16511"
wire input 46 \GTREFCLK11
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16512"
wire input 47 \GTSOUTHREFCLK00
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16513"
wire input 48 \GTSOUTHREFCLK01
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16514"
wire input 49 \GTSOUTHREFCLK10
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16515"
wire input 50 \GTSOUTHREFCLK11
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16516"
wire width 3 input 51 \PCIERATEQPLL0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16517"
wire width 3 input 52 \PCIERATEQPLL1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16518"
wire width 8 input 53 \PMARSVD0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16519"
wire width 8 input 54 \PMARSVD1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16468"
wire width 8 output 3 \PMARSVDOUT0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16469"
wire width 8 output 4 \PMARSVDOUT1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16520"
wire input 55 \QPLL0CLKRSVD0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16521"
wire input 56 \QPLL0CLKRSVD1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16470"
wire output 5 \QPLL0FBCLKLOST
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16522"
wire width 8 input 57 \QPLL0FBDIV
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16471"
wire output 6 \QPLL0LOCK
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16523"
wire input 58 \QPLL0LOCKDETCLK
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16524"
wire input 59 \QPLL0LOCKEN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16472"
wire output 7 \QPLL0OUTCLK
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16473"
wire output 8 \QPLL0OUTREFCLK
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16525"
wire input 60 \QPLL0PD
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16474"
wire output 9 \QPLL0REFCLKLOST
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16526"
wire width 3 input 61 \QPLL0REFCLKSEL
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16527"
wire input 62 \QPLL0RESET
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16528"
wire input 63 \QPLL1CLKRSVD0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16529"
wire input 64 \QPLL1CLKRSVD1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16475"
wire output 10 \QPLL1FBCLKLOST
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16530"
wire width 8 input 65 \QPLL1FBDIV
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16476"
wire output 11 \QPLL1LOCK
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16531"
wire input 66 \QPLL1LOCKDETCLK
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16532"
wire input 67 \QPLL1LOCKEN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16477"
wire output 12 \QPLL1OUTCLK
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16478"
wire output 13 \QPLL1OUTREFCLK
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16533"
wire input 68 \QPLL1PD
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16479"
wire output 14 \QPLL1REFCLKLOST
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16534"
wire width 3 input 69 \QPLL1REFCLKSEL
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16535"
wire input 70 \QPLL1RESET
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16480"
wire width 8 output 15 \QPLLDMONITOR0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16481"
wire width 8 output 16 \QPLLDMONITOR1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16536"
wire width 8 input 71 \QPLLRSVD1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16537"
wire width 5 input 72 \QPLLRSVD2
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16538"
wire width 5 input 73 \QPLLRSVD3
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16539"
wire width 8 input 74 \QPLLRSVD4
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16540"
wire input 75 \RCALENB
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16482"
wire output 17 \REFCLKOUTMONITOR0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16483"
wire output 18 \REFCLKOUTMONITOR1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16484"
wire width 2 output 19 \RXRECCLK0SEL
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16485"
wire width 2 output 20 \RXRECCLK1SEL
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16541"
wire width 25 input 76 \SDM0DATA
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16486"
wire width 4 output 21 \SDM0FINALOUT
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16542"
wire input 77 \SDM0RESET
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16487"
wire width 15 output 22 \SDM0TESTDATA
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16543"
wire input 78 \SDM0TOGGLE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16544"
wire width 2 input 79 \SDM0WIDTH
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16545"
wire width 25 input 80 \SDM1DATA
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16488"
wire width 4 output 23 \SDM1FINALOUT
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16546"
wire input 81 \SDM1RESET
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16489"
wire width 15 output 24 \SDM1TESTDATA
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16547"
wire input 82 \SDM1TOGGLE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16548"
wire width 2 input 83 \SDM1WIDTH
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16549"
wire width 10 input 84 \TCONGPI
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16490"
wire width 10 output 25 \TCONGPO
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16550"
wire input 85 \TCONPOWERUP
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16551"
wire width 2 input 86 \TCONRESET
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16552"
wire width 2 input 87 \TCONRSVDIN1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16491"
wire output 26 \TCONRSVDOUT0
end
attribute \blackbox 1
attribute \cells_not_processed 1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:10006"
module \GTPA1_DUAL
parameter \AC_CAP_DIS_0
parameter \AC_CAP_DIS_1
parameter \ALIGN_COMMA_WORD_0
parameter \ALIGN_COMMA_WORD_1
parameter \CB2_INH_CC_PERIOD_0
parameter \CB2_INH_CC_PERIOD_1
parameter \CDR_PH_ADJ_TIME_0
parameter \CDR_PH_ADJ_TIME_1
parameter \CHAN_BOND_1_MAX_SKEW_0
parameter \CHAN_BOND_1_MAX_SKEW_1
parameter \CHAN_BOND_2_MAX_SKEW_0
parameter \CHAN_BOND_2_MAX_SKEW_1
parameter \CHAN_BOND_KEEP_ALIGN_0
parameter \CHAN_BOND_KEEP_ALIGN_1
parameter \CHAN_BOND_SEQ_1_1_0
parameter \CHAN_BOND_SEQ_1_1_1
parameter \CHAN_BOND_SEQ_1_2_0
parameter \CHAN_BOND_SEQ_1_2_1
parameter \CHAN_BOND_SEQ_1_3_0
parameter \CHAN_BOND_SEQ_1_3_1
parameter \CHAN_BOND_SEQ_1_4_0
parameter \CHAN_BOND_SEQ_1_4_1
parameter \CHAN_BOND_SEQ_1_ENABLE_0
parameter \CHAN_BOND_SEQ_1_ENABLE_1
parameter \CHAN_BOND_SEQ_2_1_0
parameter \CHAN_BOND_SEQ_2_1_1
parameter \CHAN_BOND_SEQ_2_2_0
parameter \CHAN_BOND_SEQ_2_2_1
parameter \CHAN_BOND_SEQ_2_3_0
parameter \CHAN_BOND_SEQ_2_3_1
parameter \CHAN_BOND_SEQ_2_4_0
parameter \CHAN_BOND_SEQ_2_4_1
parameter \CHAN_BOND_SEQ_2_ENABLE_0
parameter \CHAN_BOND_SEQ_2_ENABLE_1
parameter \CHAN_BOND_SEQ_2_USE_0
parameter \CHAN_BOND_SEQ_2_USE_1
parameter \CHAN_BOND_SEQ_LEN_0
parameter \CHAN_BOND_SEQ_LEN_1
parameter \CLK25_DIVIDER_0
parameter \CLK25_DIVIDER_1
parameter \CLKINDC_B_0
parameter \CLKINDC_B_1
parameter \CLKRCV_TRST_0
parameter \CLKRCV_TRST_1
parameter \CLK_CORRECT_USE_0
parameter \CLK_CORRECT_USE_1
parameter \CLK_COR_ADJ_LEN_0
parameter \CLK_COR_ADJ_LEN_1
parameter \CLK_COR_DET_LEN_0
parameter \CLK_COR_DET_LEN_1
parameter \CLK_COR_INSERT_IDLE_FLAG_0
parameter \CLK_COR_INSERT_IDLE_FLAG_1
parameter \CLK_COR_KEEP_IDLE_0
parameter \CLK_COR_KEEP_IDLE_1
parameter \CLK_COR_MAX_LAT_0
parameter \CLK_COR_MAX_LAT_1
parameter \CLK_COR_MIN_LAT_0
parameter \CLK_COR_MIN_LAT_1
parameter \CLK_COR_PRECEDENCE_0
parameter \CLK_COR_PRECEDENCE_1
parameter \CLK_COR_REPEAT_WAIT_0
parameter \CLK_COR_REPEAT_WAIT_1
parameter \CLK_COR_SEQ_1_1_0
parameter \CLK_COR_SEQ_1_1_1
parameter \CLK_COR_SEQ_1_2_0
parameter \CLK_COR_SEQ_1_2_1
parameter \CLK_COR_SEQ_1_3_0
parameter \CLK_COR_SEQ_1_3_1
parameter \CLK_COR_SEQ_1_4_0
parameter \CLK_COR_SEQ_1_4_1
parameter \CLK_COR_SEQ_1_ENABLE_0
parameter \CLK_COR_SEQ_1_ENABLE_1
parameter \CLK_COR_SEQ_2_1_0
parameter \CLK_COR_SEQ_2_1_1
parameter \CLK_COR_SEQ_2_2_0
parameter \CLK_COR_SEQ_2_2_1
parameter \CLK_COR_SEQ_2_3_0
parameter \CLK_COR_SEQ_2_3_1
parameter \CLK_COR_SEQ_2_4_0
parameter \CLK_COR_SEQ_2_4_1
parameter \CLK_COR_SEQ_2_ENABLE_0
parameter \CLK_COR_SEQ_2_ENABLE_1
parameter \CLK_COR_SEQ_2_USE_0
parameter \CLK_COR_SEQ_2_USE_1
parameter \CLK_OUT_GTP_SEL_0
parameter \CLK_OUT_GTP_SEL_1
parameter \CM_TRIM_0
parameter \CM_TRIM_1
parameter \COMMA_10B_ENABLE_0
parameter \COMMA_10B_ENABLE_1
parameter \COM_BURST_VAL_0
parameter \COM_BURST_VAL_1
parameter \DEC_MCOMMA_DETECT_0
parameter \DEC_MCOMMA_DETECT_1
parameter \DEC_PCOMMA_DETECT_0
parameter \DEC_PCOMMA_DETECT_1
parameter \DEC_VALID_COMMA_ONLY_0
parameter \DEC_VALID_COMMA_ONLY_1
parameter \GTP_CFG_PWRUP_0
parameter \GTP_CFG_PWRUP_1
parameter \MCOMMA_10B_VALUE_0
parameter \MCOMMA_10B_VALUE_1
parameter \MCOMMA_DETECT_0
parameter \MCOMMA_DETECT_1
parameter \OOBDETECT_THRESHOLD_0
parameter \OOBDETECT_THRESHOLD_1
parameter \OOB_CLK_DIVIDER_0
parameter \OOB_CLK_DIVIDER_1
parameter \PCI_EXPRESS_MODE_0
parameter \PCI_EXPRESS_MODE_1
parameter \PCOMMA_10B_VALUE_0
parameter \PCOMMA_10B_VALUE_1
parameter \PCOMMA_DETECT_0
parameter \PCOMMA_DETECT_1
parameter \PLLLKDET_CFG_0
parameter \PLLLKDET_CFG_1
parameter \PLL_COM_CFG_0
parameter \PLL_COM_CFG_1
parameter \PLL_CP_CFG_0
parameter \PLL_CP_CFG_1
parameter \PLL_DIVSEL_FB_0
parameter \PLL_DIVSEL_FB_1
parameter \PLL_DIVSEL_REF_0
parameter \PLL_DIVSEL_REF_1
parameter \PLL_RXDIVSEL_OUT_0
parameter \PLL_RXDIVSEL_OUT_1
parameter \PLL_SATA_0
parameter \PLL_SATA_1
parameter \PLL_SOURCE_0
parameter \PLL_SOURCE_1
parameter \PLL_TXDIVSEL_OUT_0
parameter \PLL_TXDIVSEL_OUT_1
parameter \PMA_CDR_SCAN_0
parameter \PMA_CDR_SCAN_1
parameter \PMA_COM_CFG_EAST
parameter \PMA_COM_CFG_WEST
parameter \PMA_RXSYNC_CFG_0
parameter \PMA_RXSYNC_CFG_1
parameter \PMA_RX_CFG_0
parameter \PMA_RX_CFG_1
parameter \PMA_TX_CFG_0
parameter \PMA_TX_CFG_1
parameter \RCV_TERM_GND_0
parameter \RCV_TERM_GND_1
parameter \RCV_TERM_VTTRX_0
parameter \RCV_TERM_VTTRX_1
parameter \RXEQ_CFG_0
parameter \RXEQ_CFG_1
parameter \RXPRBSERR_LOOPBACK_0
parameter \RXPRBSERR_LOOPBACK_1
parameter \RX_BUFFER_USE_0
parameter \RX_BUFFER_USE_1
parameter \RX_DECODE_SEQ_MATCH_0
parameter \RX_DECODE_SEQ_MATCH_1
parameter \RX_EN_IDLE_HOLD_CDR_0
parameter \RX_EN_IDLE_HOLD_CDR_1
parameter \RX_EN_IDLE_RESET_BUF_0
parameter \RX_EN_IDLE_RESET_BUF_1
parameter \RX_EN_IDLE_RESET_FR_0
parameter \RX_EN_IDLE_RESET_FR_1
parameter \RX_EN_IDLE_RESET_PH_0
parameter \RX_EN_IDLE_RESET_PH_1
parameter \RX_EN_MODE_RESET_BUF_0
parameter \RX_EN_MODE_RESET_BUF_1
parameter \RX_IDLE_HI_CNT_0
parameter \RX_IDLE_HI_CNT_1
parameter \RX_IDLE_LO_CNT_0
parameter \RX_IDLE_LO_CNT_1
parameter \RX_LOSS_OF_SYNC_FSM_0
parameter \RX_LOSS_OF_SYNC_FSM_1
parameter \RX_LOS_INVALID_INCR_0
parameter \RX_LOS_INVALID_INCR_1
parameter \RX_LOS_THRESHOLD_0
parameter \RX_LOS_THRESHOLD_1
parameter \RX_SLIDE_MODE_0
parameter \RX_SLIDE_MODE_1
parameter \RX_STATUS_FMT_0
parameter \RX_STATUS_FMT_1
parameter \RX_XCLK_SEL_0
parameter \RX_XCLK_SEL_1
parameter \SATA_BURST_VAL_0
parameter \SATA_BURST_VAL_1
parameter \SATA_IDLE_VAL_0
parameter \SATA_IDLE_VAL_1
parameter \SATA_MAX_BURST_0
parameter \SATA_MAX_BURST_1
parameter \SATA_MAX_INIT_0
parameter \SATA_MAX_INIT_1
parameter \SATA_MAX_WAKE_0
parameter \SATA_MAX_WAKE_1
parameter \SATA_MIN_BURST_0
parameter \SATA_MIN_BURST_1
parameter \SATA_MIN_INIT_0
parameter \SATA_MIN_INIT_1
parameter \SATA_MIN_WAKE_0
parameter \SATA_MIN_WAKE_1
parameter \SIM_GTPRESET_SPEEDUP
parameter \SIM_RECEIVER_DETECT_PASS
parameter \SIM_REFCLK0_SOURCE
parameter \SIM_REFCLK1_SOURCE
parameter \SIM_TX_ELEC_IDLE_LEVEL
parameter \SIM_VERSION
parameter \TERMINATION_CTRL_0
parameter \TERMINATION_CTRL_1
parameter \TERMINATION_OVRD_0
parameter \TERMINATION_OVRD_1
parameter \TRANS_TIME_FROM_P2_0
parameter \TRANS_TIME_FROM_P2_1
parameter \TRANS_TIME_NON_P2_0
parameter \TRANS_TIME_NON_P2_1
parameter \TRANS_TIME_TO_P2_0
parameter \TRANS_TIME_TO_P2_1
parameter \TST_ATTR_0
parameter \TST_ATTR_1
parameter \TXRX_INVERT_0
parameter \TXRX_INVERT_1
parameter \TX_BUFFER_USE_0
parameter \TX_BUFFER_USE_1
parameter \TX_DETECT_RX_CFG_0
parameter \TX_DETECT_RX_CFG_1
parameter \TX_IDLE_DELAY_0
parameter \TX_IDLE_DELAY_1
parameter \TX_TDCC_CFG_0
parameter \TX_TDCC_CFG_1
parameter \TX_XCLK_SEL_0
parameter \TX_XCLK_SEL_1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:10306"
wire input 74 \CLK00
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:10307"
wire input 75 \CLK01
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:10308"
wire input 76 \CLK10
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:10309"
wire input 77 \CLK11
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:10310"
wire input 78 \CLKINEAST0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:10311"
wire input 79 \CLKINEAST1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:10312"
wire input 80 \CLKINWEST0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:10313"
wire input 81 \CLKINWEST1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:10453"
wire width 8 input 221 \DADDR
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:10314"
wire input 82 \DCLK
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:10315"
wire input 83 \DEN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:10411"
wire width 16 input 179 \DI
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:10233"
wire output 1 \DRDY
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:10270"
wire width 16 output 38 \DRPDO
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:10316"
wire input 84 \DWE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:10317"
wire input 85 \GATERXELECIDLE0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:10318"
wire input 86 \GATERXELECIDLE1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:10319"
wire input 87 \GCLK00
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:10320"
wire input 88 \GCLK01
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:10321"
wire input 89 \GCLK10
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:10322"
wire input 90 \GCLK11
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:10271"
wire width 2 output 39 \GTPCLKFBEAST
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:10412"
wire width 2 input 180 \GTPCLKFBSEL0EAST
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:10413"
wire width 2 input 181 \GTPCLKFBSEL0WEST
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:10414"
wire width 2 input 182 \GTPCLKFBSEL1EAST
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:10415"
wire width 2 input 183 \GTPCLKFBSEL1WEST
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:10272"
wire width 2 output 40 \GTPCLKFBWEST
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:10273"
wire width 2 output 41 \GTPCLKOUT0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:10274"
wire width 2 output 42 \GTPCLKOUT1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:10323"
wire input 91 \GTPRESET0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:10324"
wire input 92 \GTPRESET1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:10454"
wire width 8 input 222 \GTPTEST0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:10455"
wire width 8 input 223 \GTPTEST1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:10325"
wire input 93 \IGNORESIGDET0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:10326"
wire input 94 \IGNORESIGDET1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:10327"
wire input 95 \INTDATAWIDTH0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:10328"
wire input 96 \INTDATAWIDTH1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:10426"
wire width 3 input 194 \LOOPBACK0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:10427"
wire width 3 input 195 \LOOPBACK1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:10234"
wire output 2 \PHYSTATUS0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:10235"
wire output 3 \PHYSTATUS1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:10329"
wire input 97 \PLLCLK00
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:10330"
wire input 98 \PLLCLK01
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:10331"
wire input 99 \PLLCLK10
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:10332"
wire input 100 \PLLCLK11
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:10236"
wire output 4 \PLLLKDET0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:10237"
wire output 5 \PLLLKDET1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:10333"
wire input 101 \PLLLKDETEN0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:10334"
wire input 102 \PLLLKDETEN1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:10335"
wire input 103 \PLLPOWERDOWN0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:10336"
wire input 104 \PLLPOWERDOWN1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:10337"
wire input 105 \PRBSCNTRESET0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:10338"
wire input 106 \PRBSCNTRESET1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:10451"
wire width 5 input 219 \RCALINEAST
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:10452"
wire width 5 input 220 \RCALINWEST
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:10302"
wire width 5 output 70 \RCALOUTEAST
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:10303"
wire width 5 output 71 \RCALOUTWEST
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:10238"
wire output 6 \REFCLKOUT0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:10239"
wire output 7 \REFCLKOUT1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:10240"
wire output 8 \REFCLKPLL0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:10241"
wire output 9 \REFCLKPLL1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:10339"
wire input 107 \REFCLKPWRDNB0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:10340"
wire input 108 \REFCLKPWRDNB1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:10428"
wire width 3 input 196 \REFSELDYPLL0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:10429"
wire width 3 input 197 \REFSELDYPLL1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:10242"
wire output 10 \RESETDONE0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:10243"
wire output 11 \RESETDONE1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:10341"
wire input 109 \RXBUFRESET0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:10342"
wire input 110 \RXBUFRESET1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:10279"
wire width 3 output 47 \RXBUFSTATUS0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:10280"
wire width 3 output 48 \RXBUFSTATUS1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:10244"
wire output 12 \RXBYTEISALIGNED0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:10245"
wire output 13 \RXBYTEISALIGNED1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:10246"
wire output 14 \RXBYTEREALIGN0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:10247"
wire output 15 \RXBYTEREALIGN1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:10343"
wire input 111 \RXCDRRESET0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:10344"
wire input 112 \RXCDRRESET1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:10248"
wire output 16 \RXCHANBONDSEQ0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:10249"
wire output 17 \RXCHANBONDSEQ1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:10250"
wire output 18 \RXCHANISALIGNED0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:10251"
wire output 19 \RXCHANISALIGNED1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:10252"
wire output 20 \RXCHANREALIGN0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:10253"
wire output 21 \RXCHANREALIGN1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:10288"
wire width 4 output 56 \RXCHARISCOMMA0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:10289"
wire width 4 output 57 \RXCHARISCOMMA1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:10290"
wire width 4 output 58 \RXCHARISK0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:10291"
wire width 4 output 59 \RXCHARISK1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:10430"
wire width 3 input 198 \RXCHBONDI
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:10345"
wire input 113 \RXCHBONDMASTER0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:10346"
wire input 114 \RXCHBONDMASTER1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:10281"
wire width 3 output 49 \RXCHBONDO
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:10347"
wire input 115 \RXCHBONDSLAVE0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:10348"
wire input 116 \RXCHBONDSLAVE1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:10282"
wire width 3 output 50 \RXCLKCORCNT0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:10283"
wire width 3 output 51 \RXCLKCORCNT1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:10254"
wire output 22 \RXCOMMADET0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:10255"
wire output 23 \RXCOMMADET1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:10349"
wire input 117 \RXCOMMADETUSE0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:10350"
wire input 118 \RXCOMMADETUSE1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:10286"
wire width 32 output 54 \RXDATA0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:10287"
wire width 32 output 55 \RXDATA1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:10416"
wire width 2 input 184 \RXDATAWIDTH0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:10417"
wire width 2 input 185 \RXDATAWIDTH1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:10351"
wire input 119 \RXDEC8B10BUSE0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:10352"
wire input 120 \RXDEC8B10BUSE1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:10292"
wire width 4 output 60 \RXDISPERR0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:10293"
wire width 4 output 61 \RXDISPERR1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:10256"
wire output 24 \RXELECIDLE0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:10257"
wire output 25 \RXELECIDLE1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:10353"
wire input 121 \RXENCHANSYNC0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:10354"
wire input 122 \RXENCHANSYNC1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:10355"
wire input 123 \RXENMCOMMAALIGN0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:10356"
wire input 124 \RXENMCOMMAALIGN1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:10357"
wire input 125 \RXENPCOMMAALIGN0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:10358"
wire input 126 \RXENPCOMMAALIGN1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:10359"
wire input 127 \RXENPMAPHASEALIGN0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:10360"
wire input 128 \RXENPMAPHASEALIGN1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:10431"
wire width 3 input 199 \RXENPRBSTST0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:10432"
wire width 3 input 200 \RXENPRBSTST1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:10418"
wire width 2 input 186 \RXEQMIX0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:10419"
wire width 2 input 187 \RXEQMIX1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:10275"
wire width 2 output 43 \RXLOSSOFSYNC0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:10276"
wire width 2 output 44 \RXLOSSOFSYNC1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:10361"
wire input 129 \RXN0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:10362"
wire input 130 \RXN1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:10294"
wire width 4 output 62 \RXNOTINTABLE0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:10295"
wire width 4 output 63 \RXNOTINTABLE1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:10363"
wire input 131 \RXP0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:10364"
wire input 132 \RXP1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:10365"
wire input 133 \RXPMASETPHASE0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:10366"
wire input 134 \RXPMASETPHASE1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:10367"
wire input 135 \RXPOLARITY0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:10368"
wire input 136 \RXPOLARITY1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:10420"
wire width 2 input 188 \RXPOWERDOWN0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:10421"
wire width 2 input 189 \RXPOWERDOWN1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:10258"
wire output 26 \RXPRBSERR0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:10259"
wire output 27 \RXPRBSERR1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:10260"
wire output 28 \RXRECCLK0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:10261"
wire output 29 \RXRECCLK1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:10369"
wire input 137 \RXRESET0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:10370"
wire input 138 \RXRESET1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:10296"
wire width 4 output 64 \RXRUNDISP0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:10297"
wire width 4 output 65 \RXRUNDISP1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:10371"
wire input 139 \RXSLIDE0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:10372"
wire input 140 \RXSLIDE1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:10284"
wire width 3 output 52 \RXSTATUS0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:10285"
wire width 3 output 53 \RXSTATUS1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:10373"
wire input 141 \RXUSRCLK0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:10374"
wire input 142 \RXUSRCLK1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:10375"
wire input 143 \RXUSRCLK20
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:10376"
wire input 144 \RXUSRCLK21
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:10262"
wire output 30 \RXVALID0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:10263"
wire output 31 \RXVALID1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:10377"
wire input 145 \TSTCLK0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:10378"
wire input 146 \TSTCLK1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:10409"
wire width 12 input 177 \TSTIN0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:10410"
wire width 12 input 178 \TSTIN1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:10304"
wire width 5 output 72 \TSTOUT0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:10305"
wire width 5 output 73 \TSTOUT1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:10433"
wire width 3 input 201 \TXBUFDIFFCTRL0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:10434"
wire width 3 input 202 \TXBUFDIFFCTRL1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:10277"
wire width 2 output 45 \TXBUFSTATUS0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:10278"
wire width 2 output 46 \TXBUFSTATUS1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:10441"
wire width 4 input 209 \TXBYPASS8B10B0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:10442"
wire width 4 input 210 \TXBYPASS8B10B1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:10443"
wire width 4 input 211 \TXCHARDISPMODE0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:10444"
wire width 4 input 212 \TXCHARDISPMODE1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:10445"
wire width 4 input 213 \TXCHARDISPVAL0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:10446"
wire width 4 input 214 \TXCHARDISPVAL1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:10447"
wire width 4 input 215 \TXCHARISK0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:10448"
wire width 4 input 216 \TXCHARISK1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:10379"
wire input 147 \TXCOMSTART0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:10380"
wire input 148 \TXCOMSTART1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:10381"
wire input 149 \TXCOMTYPE0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:10382"
wire input 150 \TXCOMTYPE1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:10439"
wire width 32 input 207 \TXDATA0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:10440"
wire width 32 input 208 \TXDATA1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:10422"
wire width 2 input 190 \TXDATAWIDTH0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:10423"
wire width 2 input 191 \TXDATAWIDTH1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:10383"
wire input 151 \TXDETECTRX0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:10384"
wire input 152 \TXDETECTRX1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:10449"
wire width 4 input 217 \TXDIFFCTRL0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:10450"
wire width 4 input 218 \TXDIFFCTRL1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:10385"
wire input 153 \TXELECIDLE0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:10386"
wire input 154 \TXELECIDLE1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:10387"
wire input 155 \TXENC8B10BUSE0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:10388"
wire input 156 \TXENC8B10BUSE1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:10389"
wire input 157 \TXENPMAPHASEALIGN0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:10390"
wire input 158 \TXENPMAPHASEALIGN1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:10435"
wire width 3 input 203 \TXENPRBSTST0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:10436"
wire width 3 input 204 \TXENPRBSTST1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:10391"
wire input 159 \TXINHIBIT0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:10392"
wire input 160 \TXINHIBIT1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:10298"
wire width 4 output 66 \TXKERR0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:10299"
wire width 4 output 67 \TXKERR1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:10264"
wire output 32 \TXN0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:10265"
wire output 33 \TXN1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:10266"
wire output 34 \TXOUTCLK0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:10267"
wire output 35 \TXOUTCLK1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:10268"
wire output 36 \TXP0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:10269"
wire output 37 \TXP1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:10393"
wire input 161 \TXPDOWNASYNCH0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:10394"
wire input 162 \TXPDOWNASYNCH1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:10395"
wire input 163 \TXPMASETPHASE0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:10396"
wire input 164 \TXPMASETPHASE1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:10397"
wire input 165 \TXPOLARITY0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:10398"
wire input 166 \TXPOLARITY1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:10424"
wire width 2 input 192 \TXPOWERDOWN0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:10425"
wire width 2 input 193 \TXPOWERDOWN1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:10399"
wire input 167 \TXPRBSFORCEERR0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:10400"
wire input 168 \TXPRBSFORCEERR1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:10437"
wire width 3 input 205 \TXPREEMPHASIS0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:10438"
wire width 3 input 206 \TXPREEMPHASIS1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:10401"
wire input 169 \TXRESET0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:10402"
wire input 170 \TXRESET1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:10300"
wire width 4 output 68 \TXRUNDISP0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:10301"
wire width 4 output 69 \TXRUNDISP1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:10403"
wire input 171 \TXUSRCLK0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:10404"
wire input 172 \TXUSRCLK1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:10405"
wire input 173 \TXUSRCLK20
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:10406"
wire input 174 \TXUSRCLK21
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:10407"
wire input 175 \USRCODEERR0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:10408"
wire input 176 \USRCODEERR1
end
attribute \blackbox 1
attribute \cells_not_processed 1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13583"
module \GTPE2_CHANNEL
parameter \ACJTAG_DEBUG_MODE
parameter \ACJTAG_MODE
parameter \ACJTAG_RESET
parameter \ADAPT_CFG0
parameter \ALIGN_COMMA_DOUBLE
parameter \ALIGN_COMMA_ENABLE
parameter \ALIGN_COMMA_WORD
parameter \ALIGN_MCOMMA_DET
parameter \ALIGN_MCOMMA_VALUE
parameter \ALIGN_PCOMMA_DET
parameter \ALIGN_PCOMMA_VALUE
parameter \CBCC_DATA_SOURCE_SEL
parameter \CFOK_CFG
parameter \CFOK_CFG2
parameter \CFOK_CFG3
parameter \CFOK_CFG4
parameter \CFOK_CFG5
parameter \CFOK_CFG6
parameter \CHAN_BOND_KEEP_ALIGN
parameter \CHAN_BOND_MAX_SKEW
parameter \CHAN_BOND_SEQ_1_1
parameter \CHAN_BOND_SEQ_1_2
parameter \CHAN_BOND_SEQ_1_3
parameter \CHAN_BOND_SEQ_1_4
parameter \CHAN_BOND_SEQ_1_ENABLE
parameter \CHAN_BOND_SEQ_2_1
parameter \CHAN_BOND_SEQ_2_2
parameter \CHAN_BOND_SEQ_2_3
parameter \CHAN_BOND_SEQ_2_4
parameter \CHAN_BOND_SEQ_2_ENABLE
parameter \CHAN_BOND_SEQ_2_USE
parameter \CHAN_BOND_SEQ_LEN
parameter \CLK_COMMON_SWING
parameter \CLK_CORRECT_USE
parameter \CLK_COR_KEEP_IDLE
parameter \CLK_COR_MAX_LAT
parameter \CLK_COR_MIN_LAT
parameter \CLK_COR_PRECEDENCE
parameter \CLK_COR_REPEAT_WAIT
parameter \CLK_COR_SEQ_1_1
parameter \CLK_COR_SEQ_1_2
parameter \CLK_COR_SEQ_1_3
parameter \CLK_COR_SEQ_1_4
parameter \CLK_COR_SEQ_1_ENABLE
parameter \CLK_COR_SEQ_2_1
parameter \CLK_COR_SEQ_2_2
parameter \CLK_COR_SEQ_2_3
parameter \CLK_COR_SEQ_2_4
parameter \CLK_COR_SEQ_2_ENABLE
parameter \CLK_COR_SEQ_2_USE
parameter \CLK_COR_SEQ_LEN
parameter \DEC_MCOMMA_DETECT
parameter \DEC_PCOMMA_DETECT
parameter \DEC_VALID_COMMA_ONLY
parameter \DMONITOR_CFG
parameter \ES_CLK_PHASE_SEL
parameter \ES_CONTROL
parameter \ES_ERRDET_EN
parameter \ES_EYE_SCAN_EN
parameter \ES_HORZ_OFFSET
parameter \ES_PMA_CFG
parameter \ES_PRESCALE
parameter \ES_QUALIFIER
parameter \ES_QUAL_MASK
parameter \ES_SDATA_MASK
parameter \ES_VERT_OFFSET
parameter \FTS_DESKEW_SEQ_ENABLE
parameter \FTS_LANE_DESKEW_CFG
parameter \FTS_LANE_DESKEW_EN
parameter \GEARBOX_MODE
parameter \IS_CLKRSVD0_INVERTED
parameter \IS_CLKRSVD1_INVERTED
parameter \IS_DMONITORCLK_INVERTED
parameter \IS_DRPCLK_INVERTED
parameter \IS_RXUSRCLK2_INVERTED
parameter \IS_RXUSRCLK_INVERTED
parameter \IS_SIGVALIDCLK_INVERTED
parameter \IS_TXPHDLYTSTCLK_INVERTED
parameter \IS_TXUSRCLK2_INVERTED
parameter \IS_TXUSRCLK_INVERTED
parameter \LOOPBACK_CFG
parameter \OUTREFCLK_SEL_INV
parameter \PCS_PCIE_EN
parameter \PCS_RSVD_ATTR
parameter \PD_TRANS_TIME_FROM_P2
parameter \PD_TRANS_TIME_NONE_P2
parameter \PD_TRANS_TIME_TO_P2
parameter \PMA_LOOPBACK_CFG
parameter \PMA_RSV
parameter \PMA_RSV2
parameter \PMA_RSV3
parameter \PMA_RSV4
parameter \PMA_RSV5
parameter \PMA_RSV6
parameter \PMA_RSV7
parameter \RXBUFRESET_TIME
parameter \RXBUF_ADDR_MODE
parameter \RXBUF_EIDLE_HI_CNT
parameter \RXBUF_EIDLE_LO_CNT
parameter \RXBUF_EN
parameter \RXBUF_RESET_ON_CB_CHANGE
parameter \RXBUF_RESET_ON_COMMAALIGN
parameter \RXBUF_RESET_ON_EIDLE
parameter \RXBUF_RESET_ON_RATE_CHANGE
parameter \RXBUF_THRESH_OVFLW
parameter \RXBUF_THRESH_OVRD
parameter \RXBUF_THRESH_UNDFLW
parameter \RXCDRFREQRESET_TIME
parameter \RXCDRPHRESET_TIME
parameter \RXCDR_CFG
parameter \RXCDR_FR_RESET_ON_EIDLE
parameter \RXCDR_HOLD_DURING_EIDLE
parameter \RXCDR_LOCK_CFG
parameter \RXCDR_PH_RESET_ON_EIDLE
parameter \RXDLY_CFG
parameter \RXDLY_LCFG
parameter \RXDLY_TAP_CFG
parameter \RXGEARBOX_EN
parameter \RXISCANRESET_TIME
parameter \RXLPMRESET_TIME
parameter \RXLPM_BIAS_STARTUP_DISABLE
parameter \RXLPM_CFG
parameter \RXLPM_CFG1
parameter \RXLPM_CM_CFG
parameter \RXLPM_GC_CFG
parameter \RXLPM_GC_CFG2
parameter \RXLPM_HF_CFG
parameter \RXLPM_HF_CFG2
parameter \RXLPM_HF_CFG3
parameter \RXLPM_HOLD_DURING_EIDLE
parameter \RXLPM_INCM_CFG
parameter \RXLPM_IPCM_CFG
parameter \RXLPM_LF_CFG
parameter \RXLPM_LF_CFG2
parameter \RXLPM_OSINT_CFG
parameter \RXOOB_CFG
parameter \RXOOB_CLK_CFG
parameter \RXOSCALRESET_TIME
parameter \RXOSCALRESET_TIMEOUT
parameter \RXOUT_DIV
parameter \RXPCSRESET_TIME
parameter \RXPHDLY_CFG
parameter \RXPH_CFG
parameter \RXPH_MONITOR_SEL
parameter \RXPI_CFG0
parameter \RXPI_CFG1
parameter \RXPI_CFG2
parameter \RXPMARESET_TIME
parameter \RXPRBS_ERR_LOOPBACK
parameter \RXSLIDE_AUTO_WAIT
parameter \RXSLIDE_MODE
parameter \RXSYNC_MULTILANE
parameter \RXSYNC_OVRD
parameter \RXSYNC_SKIP_DA
parameter \RX_BIAS_CFG
parameter \RX_BUFFER_CFG
parameter \RX_CLK25_DIV
parameter \RX_CLKMUX_EN
parameter \RX_CM_SEL
parameter \RX_CM_TRIM
parameter \RX_DATA_WIDTH
parameter \RX_DDI_SEL
parameter \RX_DEBUG_CFG
parameter \RX_DEFER_RESET_BUF_EN
parameter \RX_DISPERR_SEQ_MATCH
parameter \RX_OS_CFG
parameter \RX_SIG_VALID_DLY
parameter \RX_XCLK_SEL
parameter \SAS_MAX_COM
parameter \SAS_MIN_COM
parameter \SATA_BURST_SEQ_LEN
parameter \SATA_BURST_VAL
parameter \SATA_EIDLE_VAL
parameter \SATA_MAX_BURST
parameter \SATA_MAX_INIT
parameter \SATA_MAX_WAKE
parameter \SATA_MIN_BURST
parameter \SATA_MIN_INIT
parameter \SATA_MIN_WAKE
parameter \SATA_PLL_CFG
parameter \SHOW_REALIGN_COMMA
parameter \SIM_RECEIVER_DETECT_PASS
parameter \SIM_RESET_SPEEDUP
parameter \SIM_TX_EIDLE_DRIVE_LEVEL
parameter \SIM_VERSION
parameter \TERM_RCAL_CFG
parameter \TERM_RCAL_OVRD
parameter \TRANS_TIME_RATE
parameter \TST_RSV
parameter \TXBUF_EN
parameter \TXBUF_RESET_ON_RATE_CHANGE
parameter \TXDLY_CFG
parameter \TXDLY_LCFG
parameter \TXDLY_TAP_CFG
parameter \TXGEARBOX_EN
parameter \TXOOB_CFG
parameter \TXOUT_DIV
parameter \TXPCSRESET_TIME
parameter \TXPHDLY_CFG
parameter \TXPH_CFG
parameter \TXPH_MONITOR_SEL
parameter \TXPI_CFG0
parameter \TXPI_CFG1
parameter \TXPI_CFG2
parameter \TXPI_CFG3
parameter \TXPI_CFG4
parameter \TXPI_CFG5
parameter \TXPI_GREY_SEL
parameter \TXPI_INVSTROBE_SEL
parameter \TXPI_PPMCLK_SEL
parameter \TXPI_PPM_CFG
parameter \TXPI_SYNFREQ_PPM
parameter \TXPMARESET_TIME
parameter \TXSYNC_MULTILANE
parameter \TXSYNC_OVRD
parameter \TXSYNC_SKIP_DA
parameter \TX_CLK25_DIV
parameter \TX_CLKMUX_EN
parameter \TX_DATA_WIDTH
parameter \TX_DEEMPH0
parameter \TX_DEEMPH1
parameter \TX_DRIVE_MODE
parameter \TX_EIDLE_ASSERT_DELAY
parameter \TX_EIDLE_DEASSERT_DELAY
parameter \TX_LOOPBACK_DRIVE_HIZ
parameter \TX_MAINCURSOR_SEL
parameter \TX_MARGIN_FULL_0
parameter \TX_MARGIN_FULL_1
parameter \TX_MARGIN_FULL_2
parameter \TX_MARGIN_FULL_3
parameter \TX_MARGIN_FULL_4
parameter \TX_MARGIN_LOW_0
parameter \TX_MARGIN_LOW_1
parameter \TX_MARGIN_LOW_2
parameter \TX_MARGIN_LOW_3
parameter \TX_MARGIN_LOW_4
parameter \TX_PREDRIVER_MODE
parameter \TX_RXDETECT_CFG
parameter \TX_RXDETECT_REF
parameter \TX_XCLK_SEL
parameter \UCODEER_CLR
parameter \USE_PCS_CLK_PHASE_SEL
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13892"
wire input 67 \CFGRESET
attribute \invertible_pin "IS_CLKRSVD0_INVERTED"
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13894"
wire input 68 \CLKRSVD0
attribute \invertible_pin "IS_CLKRSVD1_INVERTED"
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13896"
wire input 69 \CLKRSVD1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13897"
wire input 70 \DMONFIFORESET
attribute \invertible_pin "IS_DMONITORCLK_INVERTED"
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13899"
wire input 71 \DMONITORCLK
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13874"
wire width 15 output 49 \DMONITOROUT
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:14062"
wire width 9 input 227 \DRPADDR
attribute \invertible_pin "IS_DRPCLK_INVERTED"
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13901"
wire input 72 \DRPCLK
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:14028"
wire width 16 input 193 \DRPDI
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13875"
wire width 16 output 50 \DRPDO
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13902"
wire input 73 \DRPEN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13826"
wire output 1 \DRPRDY
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13903"
wire input 74 \DRPWE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13827"
wire output 2 \EYESCANDATAERROR
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13904"
wire input 75 \EYESCANMODE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13905"
wire input 76 \EYESCANRESET
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13906"
wire input 77 \EYESCANTRIGGER
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13907"
wire input 78 \GTPRXN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13908"
wire input 79 \GTPRXP
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13828"
wire output 3 \GTPTXN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13829"
wire output 4 \GTPTXP
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13909"
wire input 80 \GTRESETSEL
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:14029"
wire width 16 input 194 \GTRSVD
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13910"
wire input 81 \GTRXRESET
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13911"
wire input 82 \GTTXRESET
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:14037"
wire width 3 input 202 \LOOPBACK
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:14030"
wire width 16 input 195 \PCSRSVDIN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13876"
wire width 16 output 51 \PCSRSVDOUT
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13830"
wire output 5 \PHYSTATUS
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13912"
wire input 83 \PLL0CLK
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13913"
wire input 84 \PLL0REFCLK
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13914"
wire input 85 \PLL1CLK
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13915"
wire input 86 \PLL1REFCLK
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13916"
wire input 87 \PMARSVDIN0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13917"
wire input 88 \PMARSVDIN1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13918"
wire input 89 \PMARSVDIN2
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13919"
wire input 90 \PMARSVDIN3
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13920"
wire input 91 \PMARSVDIN4
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13831"
wire output 6 \PMARSVDOUT0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13832"
wire output 7 \PMARSVDOUT1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13921"
wire input 92 \RESETOVRD
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13922"
wire input 93 \RX8B10BEN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:14027"
wire width 14 input 192 \RXADAPTSELTEST
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13923"
wire input 94 \RXBUFRESET
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13881"
wire width 3 output 56 \RXBUFSTATUS
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13833"
wire output 8 \RXBYTEISALIGNED
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13834"
wire output 9 \RXBYTEREALIGN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13924"
wire input 95 \RXCDRFREQRESET
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13925"
wire input 96 \RXCDRHOLD
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13835"
wire output 10 \RXCDRLOCK
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13926"
wire input 97 \RXCDROVRDEN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13927"
wire input 98 \RXCDRRESET
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13928"
wire input 99 \RXCDRRESETRSV
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13836"
wire output 11 \RXCHANBONDSEQ
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13837"
wire output 12 \RXCHANISALIGNED
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13838"
wire output 13 \RXCHANREALIGN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13885"
wire width 4 output 60 \RXCHARISCOMMA
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13886"
wire width 4 output 61 \RXCHARISK
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13929"
wire input 100 \RXCHBONDEN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:14049"
wire width 4 input 214 \RXCHBONDI
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:14038"
wire width 3 input 203 \RXCHBONDLEVEL
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13930"
wire input 101 \RXCHBONDMASTER
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13887"
wire width 4 output 62 \RXCHBONDO
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13931"
wire input 102 \RXCHBONDSLAVE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13877"
wire width 2 output 52 \RXCLKCORCNT
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13839"
wire output 14 \RXCOMINITDET
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13840"
wire output 15 \RXCOMMADET
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13932"
wire input 103 \RXCOMMADETEN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13841"
wire output 16 \RXCOMSASDET
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13842"
wire output 17 \RXCOMWAKEDET
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13884"
wire width 32 output 59 \RXDATA
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13878"
wire width 2 output 53 \RXDATAVALID
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13933"
wire input 104 \RXDDIEN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13934"
wire input 105 \RXDFEXYDEN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13888"
wire width 4 output 63 \RXDISPERR
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13935"
wire input 106 \RXDLYBYPASS
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13936"
wire input 107 \RXDLYEN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13937"
wire input 108 \RXDLYOVRDEN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13938"
wire input 109 \RXDLYSRESET
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13843"
wire output 18 \RXDLYSRESETDONE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13844"
wire output 19 \RXELECIDLE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:14032"
wire width 2 input 197 \RXELECIDLEMODE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13939"
wire input 110 \RXGEARBOXSLIP
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13882"
wire width 3 output 57 \RXHEADER
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13845"
wire output 20 \RXHEADERVALID
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13940"
wire input 111 \RXLPMHFHOLD
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13941"
wire input 112 \RXLPMHFOVRDEN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13942"
wire input 113 \RXLPMLFHOLD
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13943"
wire input 114 \RXLPMLFOVRDEN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13944"
wire input 115 \RXLPMOSINTNTRLEN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13945"
wire input 116 \RXLPMRESET
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13946"
wire input 117 \RXMCOMMAALIGNEN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13889"
wire width 4 output 64 \RXNOTINTABLE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13947"
wire input 118 \RXOOBRESET
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13948"
wire input 119 \RXOSCALRESET
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13949"
wire input 120 \RXOSHOLD
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:14050"
wire width 4 input 215 \RXOSINTCFG
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13846"
wire output 21 \RXOSINTDONE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13950"
wire input 121 \RXOSINTEN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13951"
wire input 122 \RXOSINTHOLD
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:14051"
wire width 4 input 216 \RXOSINTID0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13952"
wire input 123 \RXOSINTNTRLEN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13953"
wire input 124 \RXOSINTOVRDEN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13954"
wire input 125 \RXOSINTPD
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13847"
wire output 22 \RXOSINTSTARTED
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13955"
wire input 126 \RXOSINTSTROBE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13848"
wire output 23 \RXOSINTSTROBEDONE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13849"
wire output 24 \RXOSINTSTROBESTARTED
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13956"
wire input 127 \RXOSINTTESTOVRDEN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13957"
wire input 128 \RXOSOVRDEN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13850"
wire output 25 \RXOUTCLK
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13851"
wire output 26 \RXOUTCLKFABRIC
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13852"
wire output 27 \RXOUTCLKPCS
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:14039"
wire width 3 input 204 \RXOUTCLKSEL
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13958"
wire input 129 \RXPCOMMAALIGNEN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13959"
wire input 130 \RXPCSRESET
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:14033"
wire width 2 input 198 \RXPD
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13960"
wire input 131 \RXPHALIGN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13853"
wire output 28 \RXPHALIGNDONE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13961"
wire input 132 \RXPHALIGNEN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13962"
wire input 133 \RXPHDLYPD
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13963"
wire input 134 \RXPHDLYRESET
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13890"
wire width 5 output 65 \RXPHMONITOR
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13964"
wire input 135 \RXPHOVRDEN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13891"
wire width 5 output 66 \RXPHSLIPMONITOR
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13965"
wire input 136 \RXPMARESET
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13854"
wire output 29 \RXPMARESETDONE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13966"
wire input 137 \RXPOLARITY
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13967"
wire input 138 \RXPRBSCNTRESET
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13855"
wire output 30 \RXPRBSERR
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:14040"
wire width 3 input 205 \RXPRBSSEL
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:14041"
wire width 3 input 206 \RXRATE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13856"
wire output 31 \RXRATEDONE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13968"
wire input 139 \RXRATEMODE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13857"
wire output 32 \RXRESETDONE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13969"
wire input 140 \RXSLIDE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13879"
wire width 2 output 54 \RXSTARTOFSEQ
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13883"
wire width 3 output 58 \RXSTATUS
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13970"
wire input 141 \RXSYNCALLIN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13858"
wire output 33 \RXSYNCDONE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13971"
wire input 142 \RXSYNCIN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13972"
wire input 143 \RXSYNCMODE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13859"
wire output 34 \RXSYNCOUT
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:14034"
wire width 2 input 199 \RXSYSCLKSEL
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13973"
wire input 144 \RXUSERRDY
attribute \invertible_pin "IS_RXUSRCLK_INVERTED"
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13977"
wire input 146 \RXUSRCLK
attribute \invertible_pin "IS_RXUSRCLK2_INVERTED"
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13975"
wire input 145 \RXUSRCLK2
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13860"
wire output 35 \RXVALID
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13978"
wire input 147 \SETERRSTATUS
attribute \invertible_pin "IS_SIGVALIDCLK_INVERTED"
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13980"
wire input 148 \SIGVALIDCLK
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:14031"
wire width 20 input 196 \TSTIN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:14052"
wire width 4 input 217 \TX8B10BBYPASS
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13981"
wire input 149 \TX8B10BEN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:14042"
wire width 3 input 207 \TXBUFDIFFCTRL
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13880"
wire width 2 output 55 \TXBUFSTATUS
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:14053"
wire width 4 input 218 \TXCHARDISPMODE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:14054"
wire width 4 input 219 \TXCHARDISPVAL
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:14055"
wire width 4 input 220 \TXCHARISK
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13861"
wire output 36 \TXCOMFINISH
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13982"
wire input 150 \TXCOMINIT
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13983"
wire input 151 \TXCOMSAS
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13984"
wire input 152 \TXCOMWAKE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:14048"
wire width 32 input 213 \TXDATA
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13985"
wire input 153 \TXDEEMPH
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13986"
wire input 154 \TXDETECTRX
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:14056"
wire width 4 input 221 \TXDIFFCTRL
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13987"
wire input 155 \TXDIFFPD
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13988"
wire input 156 \TXDLYBYPASS
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13989"
wire input 157 \TXDLYEN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13990"
wire input 158 \TXDLYHOLD
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13991"
wire input 159 \TXDLYOVRDEN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13992"
wire input 160 \TXDLYSRESET
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13862"
wire output 37 \TXDLYSRESETDONE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13993"
wire input 161 \TXDLYUPDOWN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13994"
wire input 162 \TXELECIDLE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13863"
wire output 38 \TXGEARBOXREADY
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:14043"
wire width 3 input 208 \TXHEADER
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13995"
wire input 163 \TXINHIBIT
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:14060"
wire width 7 input 225 \TXMAINCURSOR
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:14044"
wire width 3 input 209 \TXMARGIN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13864"
wire output 39 \TXOUTCLK
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13865"
wire output 40 \TXOUTCLKFABRIC
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13866"
wire output 41 \TXOUTCLKPCS
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:14045"
wire width 3 input 210 \TXOUTCLKSEL
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13996"
wire input 164 \TXPCSRESET
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:14035"
wire width 2 input 200 \TXPD
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13997"
wire input 165 \TXPDELECIDLEMODE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13998"
wire input 166 \TXPHALIGN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13867"
wire output 42 \TXPHALIGNDONE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13999"
wire input 167 \TXPHALIGNEN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:14000"
wire input 168 \TXPHDLYPD
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:14001"
wire input 169 \TXPHDLYRESET
attribute \invertible_pin "IS_TXPHDLYTSTCLK_INVERTED"
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:14003"
wire input 170 \TXPHDLYTSTCLK
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:14004"
wire input 171 \TXPHINIT
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13868"
wire output 43 \TXPHINITDONE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:14005"
wire input 172 \TXPHOVRDEN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:14006"
wire input 173 \TXPIPPMEN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:14007"
wire input 174 \TXPIPPMOVRDEN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:14008"
wire input 175 \TXPIPPMPD
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:14009"
wire input 176 \TXPIPPMSEL
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:14057"
wire width 5 input 222 \TXPIPPMSTEPSIZE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:14010"
wire input 177 \TXPISOPD
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:14011"
wire input 178 \TXPMARESET
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13869"
wire output 44 \TXPMARESETDONE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:14012"
wire input 179 \TXPOLARITY
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:14058"
wire width 5 input 223 \TXPOSTCURSOR
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:14013"
wire input 180 \TXPOSTCURSORINV
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:14014"
wire input 181 \TXPRBSFORCEERR
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:14046"
wire width 3 input 211 \TXPRBSSEL
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:14059"
wire width 5 input 224 \TXPRECURSOR
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:14015"
wire input 182 \TXPRECURSORINV
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:14047"
wire width 3 input 212 \TXRATE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13870"
wire output 45 \TXRATEDONE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:14016"
wire input 183 \TXRATEMODE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13871"
wire output 46 \TXRESETDONE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:14061"
wire width 7 input 226 \TXSEQUENCE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:14017"
wire input 184 \TXSTARTSEQ
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:14018"
wire input 185 \TXSWING
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:14019"
wire input 186 \TXSYNCALLIN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13872"
wire output 47 \TXSYNCDONE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:14020"
wire input 187 \TXSYNCIN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:14021"
wire input 188 \TXSYNCMODE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:13873"
wire output 48 \TXSYNCOUT
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:14036"
wire width 2 input 201 \TXSYSCLKSEL
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:14022"
wire input 189 \TXUSERRDY
attribute \invertible_pin "IS_TXUSRCLK_INVERTED"
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:14026"
wire input 191 \TXUSRCLK
attribute \invertible_pin "IS_TXUSRCLK2_INVERTED"
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:14024"
wire input 190 \TXUSRCLK2
end
attribute \blackbox 1
attribute \cells_not_processed 1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:14065"
module \GTPE2_COMMON
parameter \BIAS_CFG
parameter \COMMON_CFG
parameter \IS_DRPCLK_INVERTED
parameter \IS_GTGREFCLK0_INVERTED
parameter \IS_GTGREFCLK1_INVERTED
parameter \IS_PLL0LOCKDETCLK_INVERTED
parameter \IS_PLL1LOCKDETCLK_INVERTED
parameter \PLL0_CFG
parameter \PLL0_DMON_CFG
parameter \PLL0_FBDIV
parameter \PLL0_FBDIV_45
parameter \PLL0_INIT_CFG
parameter \PLL0_LOCK_CFG
parameter \PLL0_REFCLK_DIV
parameter \PLL1_CFG
parameter \PLL1_DMON_CFG
parameter \PLL1_FBDIV
parameter \PLL1_FBDIV_45
parameter \PLL1_INIT_CFG
parameter \PLL1_LOCK_CFG
parameter \PLL1_REFCLK_DIV
parameter \PLL_CLKOUT_CFG
parameter \RSVD_ATTR0
parameter \RSVD_ATTR1
parameter \SIM_PLL0REFCLK_SEL
parameter \SIM_PLL1REFCLK_SEL
parameter \SIM_RESET_SPEEDUP
parameter \SIM_VERSION
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:14110"
wire input 17 \BGBYPASSB
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:14111"
wire input 18 \BGMONITORENB
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:14112"
wire input 19 \BGPDB
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:14143"
wire width 5 input 45 \BGRCALOVRD
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:14113"
wire input 20 \BGRCALOVRDENB
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:14109"
wire width 8 output 16 \DMONITOROUT
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:14145"
wire width 8 input 47 \DRPADDR
attribute \invertible_pin "IS_DRPCLK_INVERTED"
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:14115"
wire input 21 \DRPCLK
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:14139"
wire width 16 input 41 \DRPDI
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:14107"
wire width 16 output 14 \DRPDO
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:14116"
wire input 22 \DRPEN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:14094"
wire output 1 \DRPRDY
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:14117"
wire input 23 \DRPWE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:14118"
wire input 24 \GTEASTREFCLK0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:14119"
wire input 25 \GTEASTREFCLK1
attribute \invertible_pin "IS_GTGREFCLK0_INVERTED"
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:14121"
wire input 26 \GTGREFCLK0
attribute \invertible_pin "IS_GTGREFCLK1_INVERTED"
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:14123"
wire input 27 \GTGREFCLK1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:14124"
wire input 28 \GTREFCLK0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:14125"
wire input 29 \GTREFCLK1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:14126"
wire input 30 \GTWESTREFCLK0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:14127"
wire input 31 \GTWESTREFCLK1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:14095"
wire output 2 \PLL0FBCLKLOST
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:14096"
wire output 3 \PLL0LOCK
attribute \invertible_pin "IS_PLL0LOCKDETCLK_INVERTED"
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:14129"
wire input 32 \PLL0LOCKDETCLK
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:14130"
wire input 33 \PLL0LOCKEN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:14097"
wire output 4 \PLL0OUTCLK
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:14098"
wire output 5 \PLL0OUTREFCLK
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:14131"
wire input 34 \PLL0PD
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:14099"
wire output 6 \PLL0REFCLKLOST
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:14141"
wire width 3 input 43 \PLL0REFCLKSEL
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:14132"
wire input 35 \PLL0RESET
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:14100"
wire output 7 \PLL1FBCLKLOST
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:14101"
wire output 8 \PLL1LOCK
attribute \invertible_pin "IS_PLL1LOCKDETCLK_INVERTED"
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:14134"
wire input 36 \PLL1LOCKDETCLK
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:14135"
wire input 37 \PLL1LOCKEN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:14102"
wire output 9 \PLL1OUTCLK
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:14103"
wire output 10 \PLL1OUTREFCLK
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:14136"
wire input 38 \PLL1PD
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:14104"
wire output 11 \PLL1REFCLKLOST
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:14142"
wire width 3 input 44 \PLL1REFCLKSEL
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:14137"
wire input 39 \PLL1RESET
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:14140"
wire width 16 input 42 \PLLRSVD1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:14144"
wire width 5 input 46 \PLLRSVD2
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:14146"
wire width 8 input 48 \PMARSVD
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:14108"
wire width 16 output 15 \PMARSVDOUT
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:14138"
wire input 40 \RCALENB
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:14105"
wire output 12 \REFCLKOUTMONITOR0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:14106"
wire output 13 \REFCLKOUTMONITOR1
end
attribute \blackbox 1
attribute \cells_not_processed 1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11294"
module \GTP_DUAL
parameter \AC_CAP_DIS_0
parameter \AC_CAP_DIS_1
parameter \ALIGN_COMMA_WORD_0
parameter \ALIGN_COMMA_WORD_1
parameter \CHAN_BOND_1_MAX_SKEW_0
parameter \CHAN_BOND_1_MAX_SKEW_1
parameter \CHAN_BOND_2_MAX_SKEW_0
parameter \CHAN_BOND_2_MAX_SKEW_1
parameter \CHAN_BOND_LEVEL_0
parameter \CHAN_BOND_LEVEL_1
parameter \CHAN_BOND_MODE_0
parameter \CHAN_BOND_MODE_1
parameter \CHAN_BOND_SEQ_1_1_0
parameter \CHAN_BOND_SEQ_1_1_1
parameter \CHAN_BOND_SEQ_1_2_0
parameter \CHAN_BOND_SEQ_1_2_1
parameter \CHAN_BOND_SEQ_1_3_0
parameter \CHAN_BOND_SEQ_1_3_1
parameter \CHAN_BOND_SEQ_1_4_0
parameter \CHAN_BOND_SEQ_1_4_1
parameter \CHAN_BOND_SEQ_1_ENABLE_0
parameter \CHAN_BOND_SEQ_1_ENABLE_1
parameter \CHAN_BOND_SEQ_2_1_0
parameter \CHAN_BOND_SEQ_2_1_1
parameter \CHAN_BOND_SEQ_2_2_0
parameter \CHAN_BOND_SEQ_2_2_1
parameter \CHAN_BOND_SEQ_2_3_0
parameter \CHAN_BOND_SEQ_2_3_1
parameter \CHAN_BOND_SEQ_2_4_0
parameter \CHAN_BOND_SEQ_2_4_1
parameter \CHAN_BOND_SEQ_2_ENABLE_0
parameter \CHAN_BOND_SEQ_2_ENABLE_1
parameter \CHAN_BOND_SEQ_2_USE_0
parameter \CHAN_BOND_SEQ_2_USE_1
parameter \CHAN_BOND_SEQ_LEN_0
parameter \CHAN_BOND_SEQ_LEN_1
parameter \CLK25_DIVIDER
parameter \CLKINDC_B
parameter \CLK_CORRECT_USE_0
parameter \CLK_CORRECT_USE_1
parameter \CLK_COR_ADJ_LEN_0
parameter \CLK_COR_ADJ_LEN_1
parameter \CLK_COR_DET_LEN_0
parameter \CLK_COR_DET_LEN_1
parameter \CLK_COR_INSERT_IDLE_FLAG_0
parameter \CLK_COR_INSERT_IDLE_FLAG_1
parameter \CLK_COR_KEEP_IDLE_0
parameter \CLK_COR_KEEP_IDLE_1
parameter \CLK_COR_MAX_LAT_0
parameter \CLK_COR_MAX_LAT_1
parameter \CLK_COR_MIN_LAT_0
parameter \CLK_COR_MIN_LAT_1
parameter \CLK_COR_PRECEDENCE_0
parameter \CLK_COR_PRECEDENCE_1
parameter \CLK_COR_REPEAT_WAIT_0
parameter \CLK_COR_REPEAT_WAIT_1
parameter \CLK_COR_SEQ_1_1_0
parameter \CLK_COR_SEQ_1_1_1
parameter \CLK_COR_SEQ_1_2_0
parameter \CLK_COR_SEQ_1_2_1
parameter \CLK_COR_SEQ_1_3_0
parameter \CLK_COR_SEQ_1_3_1
parameter \CLK_COR_SEQ_1_4_0
parameter \CLK_COR_SEQ_1_4_1
parameter \CLK_COR_SEQ_1_ENABLE_0
parameter \CLK_COR_SEQ_1_ENABLE_1
parameter \CLK_COR_SEQ_2_1_0
parameter \CLK_COR_SEQ_2_1_1
parameter \CLK_COR_SEQ_2_2_0
parameter \CLK_COR_SEQ_2_2_1
parameter \CLK_COR_SEQ_2_3_0
parameter \CLK_COR_SEQ_2_3_1
parameter \CLK_COR_SEQ_2_4_0
parameter \CLK_COR_SEQ_2_4_1
parameter \CLK_COR_SEQ_2_ENABLE_0
parameter \CLK_COR_SEQ_2_ENABLE_1
parameter \CLK_COR_SEQ_2_USE_0
parameter \CLK_COR_SEQ_2_USE_1
parameter \COMMA_10B_ENABLE_0
parameter \COMMA_10B_ENABLE_1
parameter \COMMA_DOUBLE_0
parameter \COMMA_DOUBLE_1
parameter \COM_BURST_VAL_0
parameter \COM_BURST_VAL_1
parameter \DEC_MCOMMA_DETECT_0
parameter \DEC_MCOMMA_DETECT_1
parameter \DEC_PCOMMA_DETECT_0
parameter \DEC_PCOMMA_DETECT_1
parameter \DEC_VALID_COMMA_ONLY_0
parameter \DEC_VALID_COMMA_ONLY_1
parameter \MCOMMA_10B_VALUE_0
parameter \MCOMMA_10B_VALUE_1
parameter \MCOMMA_DETECT_0
parameter \MCOMMA_DETECT_1
parameter \OOBDETECT_THRESHOLD_0
parameter \OOBDETECT_THRESHOLD_1
parameter \OOB_CLK_DIVIDER
parameter \OVERSAMPLE_MODE
parameter \PCI_EXPRESS_MODE_0
parameter \PCI_EXPRESS_MODE_1
parameter \PCOMMA_10B_VALUE_0
parameter \PCOMMA_10B_VALUE_1
parameter \PCOMMA_DETECT_0
parameter \PCOMMA_DETECT_1
parameter \PCS_COM_CFG
parameter \PLL_DIVSEL_FB
parameter \PLL_DIVSEL_REF
parameter \PLL_RXDIVSEL_OUT_0
parameter \PLL_RXDIVSEL_OUT_1
parameter \PLL_SATA_0
parameter \PLL_SATA_1
parameter \PLL_TXDIVSEL_COMM_OUT
parameter \PLL_TXDIVSEL_OUT_0
parameter \PLL_TXDIVSEL_OUT_1
parameter \PMA_CDR_SCAN_0
parameter \PMA_CDR_SCAN_1
parameter \PMA_RX_CFG_0
parameter \PMA_RX_CFG_1
parameter \PRBS_ERR_THRESHOLD_0
parameter \PRBS_ERR_THRESHOLD_1
parameter \RCV_TERM_GND_0
parameter \RCV_TERM_GND_1
parameter \RCV_TERM_MID_0
parameter \RCV_TERM_MID_1
parameter \RCV_TERM_VTTRX_0
parameter \RCV_TERM_VTTRX_1
parameter \RX_BUFFER_USE_0
parameter \RX_BUFFER_USE_1
parameter \RX_DECODE_SEQ_MATCH_0
parameter \RX_DECODE_SEQ_MATCH_1
parameter \RX_LOSS_OF_SYNC_FSM_0
parameter \RX_LOSS_OF_SYNC_FSM_1
parameter \RX_LOS_INVALID_INCR_0
parameter \RX_LOS_INVALID_INCR_1
parameter \RX_LOS_THRESHOLD_0
parameter \RX_LOS_THRESHOLD_1
parameter \RX_SLIDE_MODE_0
parameter \RX_SLIDE_MODE_1
parameter \RX_STATUS_FMT_0
parameter \RX_STATUS_FMT_1
parameter \RX_XCLK_SEL_0
parameter \RX_XCLK_SEL_1
parameter \SATA_BURST_VAL_0
parameter \SATA_BURST_VAL_1
parameter \SATA_IDLE_VAL_0
parameter \SATA_IDLE_VAL_1
parameter \SATA_MAX_BURST_0
parameter \SATA_MAX_BURST_1
parameter \SATA_MAX_INIT_0
parameter \SATA_MAX_INIT_1
parameter \SATA_MAX_WAKE_0
parameter \SATA_MAX_WAKE_1
parameter \SATA_MIN_BURST_0
parameter \SATA_MIN_BURST_1
parameter \SATA_MIN_INIT_0
parameter \SATA_MIN_INIT_1
parameter \SATA_MIN_WAKE_0
parameter \SATA_MIN_WAKE_1
parameter \SIM_GTPRESET_SPEEDUP
parameter \SIM_PLL_PERDIV2
parameter \SIM_RECEIVER_DETECT_PASS0
parameter \SIM_RECEIVER_DETECT_PASS1
parameter \TERMINATION_CTRL
parameter \TERMINATION_IMP_0
parameter \TERMINATION_IMP_1
parameter \TERMINATION_OVRD
parameter \TRANS_TIME_FROM_P2_0
parameter \TRANS_TIME_FROM_P2_1
parameter \TRANS_TIME_NON_P2_0
parameter \TRANS_TIME_NON_P2_1
parameter \TRANS_TIME_TO_P2_0
parameter \TRANS_TIME_TO_P2_1
parameter \TXRX_INVERT_0
parameter \TXRX_INVERT_1
parameter \TX_BUFFER_USE_0
parameter \TX_BUFFER_USE_1
parameter \TX_DIFF_BOOST_0
parameter \TX_DIFF_BOOST_1
parameter \TX_SYNC_FILTERB
parameter \TX_XCLK_SEL_0
parameter \TX_XCLK_SEL_1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11540"
wire input 65 \CLKIN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11648"
wire width 7 input 173 \DADDR
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11541"
wire input 66 \DCLK
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11542"
wire input 67 \DEN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11614"
wire width 16 input 139 \DI
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11511"
wire width 16 output 36 \DO
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11476"
wire output 1 \DRDY
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11543"
wire input 68 \DWE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11544"
wire input 69 \GTPRESET
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11645"
wire width 4 input 170 \GTPTEST
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11545"
wire input 70 \INTDATAWIDTH
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11635"
wire width 3 input 160 \LOOPBACK0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11636"
wire width 3 input 161 \LOOPBACK1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11477"
wire output 2 \PHYSTATUS0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11478"
wire output 3 \PHYSTATUS1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11479"
wire output 4 \PLLLKDET
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11546"
wire input 71 \PLLLKDETEN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11547"
wire input 72 \PLLPOWERDOWN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11548"
wire input 73 \PRBSCNTRESET0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11549"
wire input 74 \PRBSCNTRESET1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11480"
wire output 5 \REFCLKOUT
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11550"
wire input 75 \REFCLKPWRDNB
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11481"
wire output 6 \RESETDONE0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11482"
wire output 7 \RESETDONE1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11551"
wire input 76 \RXBUFRESET0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11552"
wire input 77 \RXBUFRESET1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11532"
wire width 3 output 57 \RXBUFSTATUS0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11533"
wire width 3 output 58 \RXBUFSTATUS1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11483"
wire output 8 \RXBYTEISALIGNED0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11484"
wire output 9 \RXBYTEISALIGNED1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11485"
wire output 10 \RXBYTEREALIGN0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11486"
wire output 11 \RXBYTEREALIGN1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11553"
wire input 78 \RXCDRRESET0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11554"
wire input 79 \RXCDRRESET1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11487"
wire output 12 \RXCHANBONDSEQ0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11488"
wire output 13 \RXCHANBONDSEQ1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11489"
wire output 14 \RXCHANISALIGNED0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11490"
wire output 15 \RXCHANISALIGNED1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11491"
wire output 16 \RXCHANREALIGN0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11492"
wire output 17 \RXCHANREALIGN1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11514"
wire width 2 output 39 \RXCHARISCOMMA0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11515"
wire width 2 output 40 \RXCHARISCOMMA1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11516"
wire width 2 output 41 \RXCHARISK0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11517"
wire width 2 output 42 \RXCHARISK1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11637"
wire width 3 input 162 \RXCHBONDI0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11638"
wire width 3 input 163 \RXCHBONDI1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11534"
wire width 3 output 59 \RXCHBONDO0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11535"
wire width 3 output 60 \RXCHBONDO1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11536"
wire width 3 output 61 \RXCLKCORCNT0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11537"
wire width 3 output 62 \RXCLKCORCNT1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11493"
wire output 18 \RXCOMMADET0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11494"
wire output 19 \RXCOMMADET1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11555"
wire input 80 \RXCOMMADETUSE0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11556"
wire input 81 \RXCOMMADETUSE1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11512"
wire width 16 output 37 \RXDATA0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11513"
wire width 16 output 38 \RXDATA1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11557"
wire input 82 \RXDATAWIDTH0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11558"
wire input 83 \RXDATAWIDTH1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11559"
wire input 84 \RXDEC8B10BUSE0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11560"
wire input 85 \RXDEC8B10BUSE1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11518"
wire width 2 output 43 \RXDISPERR0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11519"
wire width 2 output 44 \RXDISPERR1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11495"
wire output 20 \RXELECIDLE0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11496"
wire output 21 \RXELECIDLE1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11561"
wire input 86 \RXELECIDLERESET0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11562"
wire input 87 \RXELECIDLERESET1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11563"
wire input 88 \RXENCHANSYNC0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11564"
wire input 89 \RXENCHANSYNC1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11565"
wire input 90 \RXENELECIDLERESETB
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11566"
wire input 91 \RXENEQB0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11567"
wire input 92 \RXENEQB1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11568"
wire input 93 \RXENMCOMMAALIGN0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11569"
wire input 94 \RXENMCOMMAALIGN1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11570"
wire input 95 \RXENPCOMMAALIGN0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11571"
wire input 96 \RXENPCOMMAALIGN1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11617"
wire width 2 input 142 \RXENPRBSTST0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11618"
wire width 2 input 143 \RXENPRBSTST1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11572"
wire input 97 \RXENSAMPLEALIGN0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11573"
wire input 98 \RXENSAMPLEALIGN1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11619"
wire width 2 input 144 \RXEQMIX0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11620"
wire width 2 input 145 \RXEQMIX1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11646"
wire width 4 input 171 \RXEQPOLE0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11647"
wire width 4 input 172 \RXEQPOLE1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11520"
wire width 2 output 45 \RXLOSSOFSYNC0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11521"
wire width 2 output 46 \RXLOSSOFSYNC1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11574"
wire input 99 \RXN0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11575"
wire input 100 \RXN1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11522"
wire width 2 output 47 \RXNOTINTABLE0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11523"
wire width 2 output 48 \RXNOTINTABLE1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11497"
wire output 22 \RXOVERSAMPLEERR0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11498"
wire output 23 \RXOVERSAMPLEERR1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11576"
wire input 101 \RXP0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11577"
wire input 102 \RXP1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11578"
wire input 103 \RXPMASETPHASE0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11579"
wire input 104 \RXPMASETPHASE1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11580"
wire input 105 \RXPOLARITY0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11581"
wire input 106 \RXPOLARITY1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11621"
wire width 2 input 146 \RXPOWERDOWN0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11622"
wire width 2 input 147 \RXPOWERDOWN1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11499"
wire output 24 \RXPRBSERR0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11500"
wire output 25 \RXPRBSERR1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11501"
wire output 26 \RXRECCLK0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11502"
wire output 27 \RXRECCLK1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11582"
wire input 107 \RXRESET0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11583"
wire input 108 \RXRESET1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11524"
wire width 2 output 49 \RXRUNDISP0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11525"
wire width 2 output 50 \RXRUNDISP1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11584"
wire input 109 \RXSLIDE0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11585"
wire input 110 \RXSLIDE1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11538"
wire width 3 output 63 \RXSTATUS0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11539"
wire width 3 output 64 \RXSTATUS1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11586"
wire input 111 \RXUSRCLK0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11587"
wire input 112 \RXUSRCLK1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11588"
wire input 113 \RXUSRCLK20
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11589"
wire input 114 \RXUSRCLK21
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11503"
wire output 28 \RXVALID0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11504"
wire output 29 \RXVALID1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11639"
wire width 3 input 164 \TXBUFDIFFCTRL0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11640"
wire width 3 input 165 \TXBUFDIFFCTRL1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11526"
wire width 2 output 51 \TXBUFSTATUS0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11527"
wire width 2 output 52 \TXBUFSTATUS1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11623"
wire width 2 input 148 \TXBYPASS8B10B0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11624"
wire width 2 input 149 \TXBYPASS8B10B1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11625"
wire width 2 input 150 \TXCHARDISPMODE0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11626"
wire width 2 input 151 \TXCHARDISPMODE1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11627"
wire width 2 input 152 \TXCHARDISPVAL0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11628"
wire width 2 input 153 \TXCHARDISPVAL1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11629"
wire width 2 input 154 \TXCHARISK0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11630"
wire width 2 input 155 \TXCHARISK1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11590"
wire input 115 \TXCOMSTART0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11591"
wire input 116 \TXCOMSTART1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11592"
wire input 117 \TXCOMTYPE0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11593"
wire input 118 \TXCOMTYPE1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11615"
wire width 16 input 140 \TXDATA0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11616"
wire width 16 input 141 \TXDATA1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11594"
wire input 119 \TXDATAWIDTH0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11595"
wire input 120 \TXDATAWIDTH1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11596"
wire input 121 \TXDETECTRX0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11597"
wire input 122 \TXDETECTRX1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11641"
wire width 3 input 166 \TXDIFFCTRL0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11642"
wire width 3 input 167 \TXDIFFCTRL1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11598"
wire input 123 \TXELECIDLE0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11599"
wire input 124 \TXELECIDLE1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11600"
wire input 125 \TXENC8B10BUSE0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11601"
wire input 126 \TXENC8B10BUSE1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11602"
wire input 127 \TXENPMAPHASEALIGN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11631"
wire width 2 input 156 \TXENPRBSTST0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11632"
wire width 2 input 157 \TXENPRBSTST1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11603"
wire input 128 \TXINHIBIT0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11604"
wire input 129 \TXINHIBIT1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11528"
wire width 2 output 53 \TXKERR0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11529"
wire width 2 output 54 \TXKERR1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11505"
wire output 30 \TXN0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11506"
wire output 31 \TXN1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11507"
wire output 32 \TXOUTCLK0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11508"
wire output 33 \TXOUTCLK1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11509"
wire output 34 \TXP0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11510"
wire output 35 \TXP1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11605"
wire input 130 \TXPMASETPHASE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11606"
wire input 131 \TXPOLARITY0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11607"
wire input 132 \TXPOLARITY1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11633"
wire width 2 input 158 \TXPOWERDOWN0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11634"
wire width 2 input 159 \TXPOWERDOWN1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11643"
wire width 3 input 168 \TXPREEMPHASIS0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11644"
wire width 3 input 169 \TXPREEMPHASIS1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11608"
wire input 133 \TXRESET0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11609"
wire input 134 \TXRESET1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11530"
wire width 2 output 55 \TXRUNDISP0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11531"
wire width 2 output 56 \TXRUNDISP1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11610"
wire input 135 \TXUSRCLK0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11611"
wire input 136 \TXUSRCLK1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11612"
wire input 137 \TXUSRCLK20
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11613"
wire input 138 \TXUSRCLK21
end
attribute \blackbox 1
attribute \cells_not_processed 1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12577"
module \GTXE1
parameter \AC_CAP_DIS
parameter \ALIGN_COMMA_WORD
parameter \BGTEST_CFG
parameter \BIAS_CFG
parameter \CDR_PH_ADJ_TIME
parameter \CHAN_BOND_1_MAX_SKEW
parameter \CHAN_BOND_2_MAX_SKEW
parameter \CHAN_BOND_KEEP_ALIGN
parameter \CHAN_BOND_SEQ_1_1
parameter \CHAN_BOND_SEQ_1_2
parameter \CHAN_BOND_SEQ_1_3
parameter \CHAN_BOND_SEQ_1_4
parameter \CHAN_BOND_SEQ_1_ENABLE
parameter \CHAN_BOND_SEQ_2_1
parameter \CHAN_BOND_SEQ_2_2
parameter \CHAN_BOND_SEQ_2_3
parameter \CHAN_BOND_SEQ_2_4
parameter \CHAN_BOND_SEQ_2_CFG
parameter \CHAN_BOND_SEQ_2_ENABLE
parameter \CHAN_BOND_SEQ_2_USE
parameter \CHAN_BOND_SEQ_LEN
parameter \CLK_CORRECT_USE
parameter \CLK_COR_ADJ_LEN
parameter \CLK_COR_DET_LEN
parameter \CLK_COR_INSERT_IDLE_FLAG
parameter \CLK_COR_KEEP_IDLE
parameter \CLK_COR_MAX_LAT
parameter \CLK_COR_MIN_LAT
parameter \CLK_COR_PRECEDENCE
parameter \CLK_COR_REPEAT_WAIT
parameter \CLK_COR_SEQ_1_1
parameter \CLK_COR_SEQ_1_2
parameter \CLK_COR_SEQ_1_3
parameter \CLK_COR_SEQ_1_4
parameter \CLK_COR_SEQ_1_ENABLE
parameter \CLK_COR_SEQ_2_1
parameter \CLK_COR_SEQ_2_2
parameter \CLK_COR_SEQ_2_3
parameter \CLK_COR_SEQ_2_4
parameter \CLK_COR_SEQ_2_ENABLE
parameter \CLK_COR_SEQ_2_USE
parameter \CM_TRIM
parameter \COMMA_10B_ENABLE
parameter \COMMA_DOUBLE
parameter \COM_BURST_VAL
parameter \DEC_MCOMMA_DETECT
parameter \DEC_PCOMMA_DETECT
parameter \DEC_VALID_COMMA_ONLY
parameter \DFE_CAL_TIME
parameter \DFE_CFG
parameter \GEARBOX_ENDEC
parameter \GEN_RXUSRCLK
parameter \GEN_TXUSRCLK
parameter \GTX_CFG_PWRUP
parameter \MCOMMA_10B_VALUE
parameter \MCOMMA_DETECT
parameter \OOBDETECT_THRESHOLD
parameter \PCI_EXPRESS_MODE
parameter \PCOMMA_10B_VALUE
parameter \PCOMMA_DETECT
parameter \PMA_CAS_CLK_EN
parameter \PMA_CDR_SCAN
parameter \PMA_CFG
parameter \PMA_RXSYNC_CFG
parameter \PMA_RX_CFG
parameter \PMA_TX_CFG
parameter \POWER_SAVE
parameter \RCV_TERM_GND
parameter \RCV_TERM_VTTRX
parameter \RXGEARBOX_USE
parameter \RXPLL_COM_CFG
parameter \RXPLL_CP_CFG
parameter \RXPLL_DIVSEL45_FB
parameter \RXPLL_DIVSEL_FB
parameter \RXPLL_DIVSEL_OUT
parameter \RXPLL_DIVSEL_REF
parameter \RXPLL_LKDET_CFG
parameter \RXPRBSERR_LOOPBACK
parameter \RXRECCLK_CTRL
parameter \RXRECCLK_DLY
parameter \RXUSRCLK_DLY
parameter \RX_BUFFER_USE
parameter \RX_CLK25_DIVIDER
parameter \RX_DATA_WIDTH
parameter \RX_DECODE_SEQ_MATCH
parameter \RX_DLYALIGN_CTRINC
parameter \RX_DLYALIGN_EDGESET
parameter \RX_DLYALIGN_LPFINC
parameter \RX_DLYALIGN_MONSEL
parameter \RX_DLYALIGN_OVRDSETTING
parameter \RX_EN_IDLE_HOLD_CDR
parameter \RX_EN_IDLE_HOLD_DFE
parameter \RX_EN_IDLE_RESET_BUF
parameter \RX_EN_IDLE_RESET_FR
parameter \RX_EN_IDLE_RESET_PH
parameter \RX_EN_MODE_RESET_BUF
parameter \RX_EN_RATE_RESET_BUF
parameter \RX_EN_REALIGN_RESET_BUF
parameter \RX_EN_REALIGN_RESET_BUF2
parameter \RX_EYE_OFFSET
parameter \RX_EYE_SCANMODE
parameter \RX_FIFO_ADDR_MODE
parameter \RX_IDLE_HI_CNT
parameter \RX_IDLE_LO_CNT
parameter \RX_LOSS_OF_SYNC_FSM
parameter \RX_LOS_INVALID_INCR
parameter \RX_LOS_THRESHOLD
parameter \RX_OVERSAMPLE_MODE
parameter \RX_SLIDE_AUTO_WAIT
parameter \RX_SLIDE_MODE
parameter \RX_XCLK_SEL
parameter \SAS_MAX_COMSAS
parameter \SAS_MIN_COMSAS
parameter \SATA_BURST_VAL
parameter \SATA_IDLE_VAL
parameter \SATA_MAX_BURST
parameter \SATA_MAX_INIT
parameter \SATA_MAX_WAKE
parameter \SATA_MIN_BURST
parameter \SATA_MIN_INIT
parameter \SATA_MIN_WAKE
parameter \SHOW_REALIGN_COMMA
parameter \SIM_GTXRESET_SPEEDUP
parameter \SIM_RECEIVER_DETECT_PASS
parameter \SIM_RXREFCLK_SOURCE
parameter \SIM_TXREFCLK_SOURCE
parameter \SIM_TX_ELEC_IDLE_LEVEL
parameter \SIM_VERSION
parameter \TERMINATION_CTRL
parameter \TERMINATION_OVRD
parameter \TRANS_TIME_FROM_P2
parameter \TRANS_TIME_NON_P2
parameter \TRANS_TIME_RATE
parameter \TRANS_TIME_TO_P2
parameter \TST_ATTR
parameter \TXDRIVE_LOOPBACK_HIZ
parameter \TXDRIVE_LOOPBACK_PD
parameter \TXGEARBOX_USE
parameter \TXOUTCLK_CTRL
parameter \TXOUTCLK_DLY
parameter \TXPLL_COM_CFG
parameter \TXPLL_CP_CFG
parameter \TXPLL_DIVSEL45_FB
parameter \TXPLL_DIVSEL_FB
parameter \TXPLL_DIVSEL_OUT
parameter \TXPLL_DIVSEL_REF
parameter \TXPLL_LKDET_CFG
parameter \TXPLL_SATA
parameter \TX_BUFFER_USE
parameter \TX_BYTECLK_CFG
parameter \TX_CLK25_DIVIDER
parameter \TX_CLK_SOURCE
parameter \TX_DATA_WIDTH
parameter \TX_DEEMPH_0
parameter \TX_DEEMPH_1
parameter \TX_DETECT_RX_CFG
parameter \TX_DLYALIGN_CTRINC
parameter \TX_DLYALIGN_LPFINC
parameter \TX_DLYALIGN_MONSEL
parameter \TX_DLYALIGN_OVRDSETTING
parameter \TX_DRIVE_MODE
parameter \TX_EN_RATE_RESET_BUF
parameter \TX_IDLE_ASSERT_DELAY
parameter \TX_IDLE_DEASSERT_DELAY
parameter \TX_MARGIN_FULL_0
parameter \TX_MARGIN_FULL_1
parameter \TX_MARGIN_FULL_2
parameter \TX_MARGIN_FULL_3
parameter \TX_MARGIN_FULL_4
parameter \TX_MARGIN_LOW_0
parameter \TX_MARGIN_LOW_1
parameter \TX_MARGIN_LOW_2
parameter \TX_MARGIN_LOW_3
parameter \TX_MARGIN_LOW_4
parameter \TX_OVERSAMPLE_MODE
parameter \TX_PMADATA_OPT
parameter \TX_TDCC_CFG
parameter \TX_USRCLK_CFG
parameter \TX_XCLK_SEL
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12757"
wire output 1 \COMFINISH
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12758"
wire output 2 \COMINITDET
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12759"
wire output 3 \COMSASDET
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12760"
wire output 4 \COMWAKEDET
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12925"
wire width 8 input 169 \DADDR
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12816"
wire input 60 \DCLK
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12817"
wire input 61 \DEN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12923"
wire width 6 input 167 \DFECLKDLYADJ
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12812"
wire width 6 output 56 \DFECLKDLYADJMON
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12818"
wire input 62 \DFEDLYOVRD
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12809"
wire width 5 output 53 \DFEEYEDACMON
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12793"
wire width 3 output 37 \DFESENSCAL
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12920"
wire width 5 input 164 \DFETAP1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12810"
wire width 5 output 54 \DFETAP1MONITOR
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12921"
wire width 5 input 165 \DFETAP2
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12811"
wire width 5 output 55 \DFETAP2MONITOR
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12911"
wire width 4 input 155 \DFETAP3
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12799"
wire width 4 output 43 \DFETAP3MONITOR
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12912"
wire width 4 input 156 \DFETAP4
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12800"
wire width 4 output 44 \DFETAP4MONITOR
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12819"
wire input 63 \DFETAPOVRD
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12889"
wire width 16 input 133 \DI
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12761"
wire output 5 \DRDY
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12789"
wire width 16 output 33 \DRPDO
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12820"
wire input 64 \DWE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12821"
wire input 65 \GATERXELECIDLE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12822"
wire input 66 \GREFCLKRX
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12823"
wire input 67 \GREFCLKTX
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12824"
wire input 68 \GTXRXRESET
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12888"
wire width 13 input 132 \GTXTEST
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12825"
wire input 69 \GTXTXRESET
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12826"
wire input 70 \IGNORESIGDET
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12901"
wire width 3 input 145 \LOOPBACK
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12790"
wire width 2 output 34 \MGTREFCLKFAB
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12891"
wire width 2 input 135 \MGTREFCLKRX
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12892"
wire width 2 input 136 \MGTREFCLKTX
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12893"
wire width 2 input 137 \NORTHREFCLKRX
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12894"
wire width 2 input 138 \NORTHREFCLKTX
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12827"
wire input 71 \PERFCLKRX
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12828"
wire input 72 \PERFCLKTX
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12762"
wire output 6 \PHYSTATUS
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12829"
wire input 73 \PLLRXRESET
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12830"
wire input 74 \PLLTXRESET
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12831"
wire input 75 \PRBSCNTRESET
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12832"
wire input 76 \RXBUFRESET
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12794"
wire width 3 output 38 \RXBUFSTATUS
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12763"
wire output 7 \RXBYTEISALIGNED
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12764"
wire output 8 \RXBYTEREALIGN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12833"
wire input 77 \RXCDRRESET
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12765"
wire output 9 \RXCHANBONDSEQ
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12766"
wire output 10 \RXCHANISALIGNED
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12767"
wire output 11 \RXCHANREALIGN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12801"
wire width 4 output 45 \RXCHARISCOMMA
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12802"
wire width 4 output 46 \RXCHARISK
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12913"
wire width 4 input 157 \RXCHBONDI
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12902"
wire width 3 input 146 \RXCHBONDLEVEL
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12834"
wire input 78 \RXCHBONDMASTER
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12803"
wire width 4 output 47 \RXCHBONDO
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12835"
wire input 79 \RXCHBONDSLAVE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12795"
wire width 3 output 39 \RXCLKCORCNT
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12768"
wire output 12 \RXCOMMADET
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12836"
wire input 80 \RXCOMMADETUSE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12798"
wire width 32 output 42 \RXDATA
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12769"
wire output 13 \RXDATAVALID
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12837"
wire input 81 \RXDEC8B10BUSE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12804"
wire width 4 output 48 \RXDISPERR
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12838"
wire input 82 \RXDLYALIGNDISABLE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12839"
wire input 83 \RXDLYALIGNMONENB
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12813"
wire width 8 output 57 \RXDLYALIGNMONITOR
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12840"
wire input 84 \RXDLYALIGNOVERRIDE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12841"
wire input 85 \RXDLYALIGNRESET
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12842"
wire input 86 \RXDLYALIGNSWPPRECURB
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12843"
wire input 87 \RXDLYALIGNUPDSW
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12770"
wire output 14 \RXELECIDLE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12844"
wire input 88 \RXENCHANSYNC
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12845"
wire input 89 \RXENMCOMMAALIGN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12846"
wire input 90 \RXENPCOMMAALIGN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12847"
wire input 91 \RXENPMAPHASEALIGN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12903"
wire width 3 input 147 \RXENPRBSTST
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12848"
wire input 92 \RXENSAMPLEALIGN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12926"
wire width 10 input 170 \RXEQMIX
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12849"
wire input 93 \RXGEARBOXSLIP
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12796"
wire width 3 output 40 \RXHEADER
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12771"
wire output 15 \RXHEADERVALID
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12791"
wire width 2 output 35 \RXLOSSOFSYNC
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12850"
wire input 94 \RXN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12805"
wire width 4 output 49 \RXNOTINTABLE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12772"
wire output 16 \RXOVERSAMPLEERR
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12851"
wire input 95 \RXP
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12773"
wire output 17 \RXPLLLKDET
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12852"
wire input 96 \RXPLLLKDETEN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12853"
wire input 97 \RXPLLPOWERDOWN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12904"
wire width 3 input 148 \RXPLLREFSELDY
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12854"
wire input 98 \RXPMASETPHASE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12855"
wire input 99 \RXPOLARITY
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12895"
wire width 2 input 139 \RXPOWERDOWN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12774"
wire output 18 \RXPRBSERR
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12896"
wire width 2 input 140 \RXRATE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12775"
wire output 19 \RXRATEDONE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12776"
wire output 20 \RXRECCLK
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12777"
wire output 21 \RXRECCLKPCS
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12856"
wire input 100 \RXRESET
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12778"
wire output 22 \RXRESETDONE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12806"
wire width 4 output 50 \RXRUNDISP
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12857"
wire input 101 \RXSLIDE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12779"
wire output 23 \RXSTARTOFSEQ
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12797"
wire width 3 output 41 \RXSTATUS
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12859"
wire input 103 \RXUSRCLK
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12858"
wire input 102 \RXUSRCLK2
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12780"
wire output 24 \RXVALID
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12897"
wire width 2 input 141 \SOUTHREFCLKRX
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12898"
wire width 2 input 142 \SOUTHREFCLKTX
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12860"
wire input 104 \TSTCLK0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12861"
wire input 105 \TSTCLK1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12890"
wire width 20 input 134 \TSTIN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12815"
wire width 10 output 59 \TSTOUT
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12905"
wire width 3 input 149 \TXBUFDIFFCTRL
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12792"
wire width 2 output 36 \TXBUFSTATUS
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12914"
wire width 4 input 158 \TXBYPASS8B10B
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12915"
wire width 4 input 159 \TXCHARDISPMODE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12916"
wire width 4 input 160 \TXCHARDISPVAL
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12917"
wire width 4 input 161 \TXCHARISK
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12862"
wire input 106 \TXCOMINIT
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12863"
wire input 107 \TXCOMSAS
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12864"
wire input 108 \TXCOMWAKE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12910"
wire width 32 input 154 \TXDATA
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12865"
wire input 109 \TXDEEMPH
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12866"
wire input 110 \TXDETECTRX
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12918"
wire width 4 input 162 \TXDIFFCTRL
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12867"
wire input 111 \TXDLYALIGNDISABLE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12868"
wire input 112 \TXDLYALIGNMONENB
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12814"
wire width 8 output 58 \TXDLYALIGNMONITOR
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12869"
wire input 113 \TXDLYALIGNOVERRIDE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12870"
wire input 114 \TXDLYALIGNRESET
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12871"
wire input 115 \TXDLYALIGNUPDSW
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12872"
wire input 116 \TXELECIDLE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12873"
wire input 117 \TXENC8B10BUSE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12874"
wire input 118 \TXENPMAPHASEALIGN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12906"
wire width 3 input 150 \TXENPRBSTST
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12781"
wire output 25 \TXGEARBOXREADY
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12907"
wire width 3 input 151 \TXHEADER
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12875"
wire input 119 \TXINHIBIT
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12807"
wire width 4 output 51 \TXKERR
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12908"
wire width 3 input 152 \TXMARGIN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12782"
wire output 26 \TXN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12783"
wire output 27 \TXOUTCLK
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12784"
wire output 28 \TXOUTCLKPCS
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12785"
wire output 29 \TXP
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12876"
wire input 120 \TXPDOWNASYNCH
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12786"
wire output 30 \TXPLLLKDET
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12877"
wire input 121 \TXPLLLKDETEN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12878"
wire input 122 \TXPLLPOWERDOWN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12909"
wire width 3 input 153 \TXPLLREFSELDY
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12879"
wire input 123 \TXPMASETPHASE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12880"
wire input 124 \TXPOLARITY
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12922"
wire width 5 input 166 \TXPOSTEMPHASIS
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12899"
wire width 2 input 143 \TXPOWERDOWN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12881"
wire input 125 \TXPRBSFORCEERR
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12919"
wire width 4 input 163 \TXPREEMPHASIS
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12900"
wire width 2 input 144 \TXRATE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12787"
wire output 31 \TXRATEDONE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12882"
wire input 126 \TXRESET
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12788"
wire output 32 \TXRESETDONE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12808"
wire width 4 output 52 \TXRUNDISP
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12924"
wire width 7 input 168 \TXSEQUENCE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12883"
wire input 127 \TXSTARTSEQ
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12884"
wire input 128 \TXSWING
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12886"
wire input 130 \TXUSRCLK
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12885"
wire input 129 \TXUSRCLK2
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12887"
wire input 131 \USRCODEERR
end
attribute \blackbox 1
attribute \cells_not_processed 1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:14149"
module \GTXE2_CHANNEL
parameter \ALIGN_COMMA_DOUBLE
parameter \ALIGN_COMMA_ENABLE
parameter \ALIGN_COMMA_WORD
parameter \ALIGN_MCOMMA_DET
parameter \ALIGN_MCOMMA_VALUE
parameter \ALIGN_PCOMMA_DET
parameter \ALIGN_PCOMMA_VALUE
parameter \CBCC_DATA_SOURCE_SEL
parameter \CHAN_BOND_KEEP_ALIGN
parameter \CHAN_BOND_MAX_SKEW
parameter \CHAN_BOND_SEQ_1_1
parameter \CHAN_BOND_SEQ_1_2
parameter \CHAN_BOND_SEQ_1_3
parameter \CHAN_BOND_SEQ_1_4
parameter \CHAN_BOND_SEQ_1_ENABLE
parameter \CHAN_BOND_SEQ_2_1
parameter \CHAN_BOND_SEQ_2_2
parameter \CHAN_BOND_SEQ_2_3
parameter \CHAN_BOND_SEQ_2_4
parameter \CHAN_BOND_SEQ_2_ENABLE
parameter \CHAN_BOND_SEQ_2_USE
parameter \CHAN_BOND_SEQ_LEN
parameter \CLK_CORRECT_USE
parameter \CLK_COR_KEEP_IDLE
parameter \CLK_COR_MAX_LAT
parameter \CLK_COR_MIN_LAT
parameter \CLK_COR_PRECEDENCE
parameter \CLK_COR_REPEAT_WAIT
parameter \CLK_COR_SEQ_1_1
parameter \CLK_COR_SEQ_1_2
parameter \CLK_COR_SEQ_1_3
parameter \CLK_COR_SEQ_1_4
parameter \CLK_COR_SEQ_1_ENABLE
parameter \CLK_COR_SEQ_2_1
parameter \CLK_COR_SEQ_2_2
parameter \CLK_COR_SEQ_2_3
parameter \CLK_COR_SEQ_2_4
parameter \CLK_COR_SEQ_2_ENABLE
parameter \CLK_COR_SEQ_2_USE
parameter \CLK_COR_SEQ_LEN
parameter \CPLL_CFG
parameter \CPLL_FBDIV
parameter \CPLL_FBDIV_45
parameter \CPLL_INIT_CFG
parameter \CPLL_LOCK_CFG
parameter \CPLL_REFCLK_DIV
parameter \DEC_MCOMMA_DETECT
parameter \DEC_PCOMMA_DETECT
parameter \DEC_VALID_COMMA_ONLY
parameter \DMONITOR_CFG
parameter \ES_CONTROL
parameter \ES_ERRDET_EN
parameter \ES_EYE_SCAN_EN
parameter \ES_HORZ_OFFSET
parameter \ES_PMA_CFG
parameter \ES_PRESCALE
parameter \ES_QUALIFIER
parameter \ES_QUAL_MASK
parameter \ES_SDATA_MASK
parameter \ES_VERT_OFFSET
parameter \FTS_DESKEW_SEQ_ENABLE
parameter \FTS_LANE_DESKEW_CFG
parameter \FTS_LANE_DESKEW_EN
parameter \GEARBOX_MODE
parameter \IS_CPLLLOCKDETCLK_INVERTED
parameter \IS_DRPCLK_INVERTED
parameter \IS_GTGREFCLK_INVERTED
parameter \IS_RXUSRCLK2_INVERTED
parameter \IS_RXUSRCLK_INVERTED
parameter \IS_TXPHDLYTSTCLK_INVERTED
parameter \IS_TXUSRCLK2_INVERTED
parameter \IS_TXUSRCLK_INVERTED
parameter \OUTREFCLK_SEL_INV
parameter \PCS_PCIE_EN
parameter \PCS_RSVD_ATTR
parameter \PD_TRANS_TIME_FROM_P2
parameter \PD_TRANS_TIME_NONE_P2
parameter \PD_TRANS_TIME_TO_P2
parameter \PMA_RSV
parameter \PMA_RSV2
parameter \PMA_RSV3
parameter \PMA_RSV4
parameter \RXBUFRESET_TIME
parameter \RXBUF_ADDR_MODE
parameter \RXBUF_EIDLE_HI_CNT
parameter \RXBUF_EIDLE_LO_CNT
parameter \RXBUF_EN
parameter \RXBUF_RESET_ON_CB_CHANGE
parameter \RXBUF_RESET_ON_COMMAALIGN
parameter \RXBUF_RESET_ON_EIDLE
parameter \RXBUF_RESET_ON_RATE_CHANGE
parameter \RXBUF_THRESH_OVFLW
parameter \RXBUF_THRESH_OVRD
parameter \RXBUF_THRESH_UNDFLW
parameter \RXCDRFREQRESET_TIME
parameter \RXCDRPHRESET_TIME
parameter \RXCDR_CFG
parameter \RXCDR_FR_RESET_ON_EIDLE
parameter \RXCDR_HOLD_DURING_EIDLE
parameter \RXCDR_LOCK_CFG
parameter \RXCDR_PH_RESET_ON_EIDLE
parameter \RXDFELPMRESET_TIME
parameter \RXDLY_CFG
parameter \RXDLY_LCFG
parameter \RXDLY_TAP_CFG
parameter \RXGEARBOX_EN
parameter \RXISCANRESET_TIME
parameter \RXLPM_HF_CFG
parameter \RXLPM_LF_CFG
parameter \RXOOB_CFG
parameter \RXOUT_DIV
parameter \RXPCSRESET_TIME
parameter \RXPHDLY_CFG
parameter \RXPH_CFG
parameter \RXPH_MONITOR_SEL
parameter \RXPMARESET_TIME
parameter \RXPRBS_ERR_LOOPBACK
parameter \RXSLIDE_AUTO_WAIT
parameter \RXSLIDE_MODE
parameter \RX_BIAS_CFG
parameter \RX_BUFFER_CFG
parameter \RX_CLK25_DIV
parameter \RX_CLKMUX_PD
parameter \RX_CM_SEL
parameter \RX_CM_TRIM
parameter \RX_DATA_WIDTH
parameter \RX_DDI_SEL
parameter \RX_DEBUG_CFG
parameter \RX_DEFER_RESET_BUF_EN
parameter \RX_DFE_GAIN_CFG
parameter \RX_DFE_H2_CFG
parameter \RX_DFE_H3_CFG
parameter \RX_DFE_H4_CFG
parameter \RX_DFE_H5_CFG
parameter \RX_DFE_KL_CFG
parameter \RX_DFE_KL_CFG2
parameter \RX_DFE_LPM_CFG
parameter \RX_DFE_LPM_HOLD_DURING_EIDLE
parameter \RX_DFE_UT_CFG
parameter \RX_DFE_VP_CFG
parameter \RX_DFE_XYD_CFG
parameter \RX_DISPERR_SEQ_MATCH
parameter \RX_INT_DATAWIDTH
parameter \RX_OS_CFG
parameter \RX_SIG_VALID_DLY
parameter \RX_XCLK_SEL
parameter \SAS_MAX_COM
parameter \SAS_MIN_COM
parameter \SATA_BURST_SEQ_LEN
parameter \SATA_BURST_VAL
parameter \SATA_CPLL_CFG
parameter \SATA_EIDLE_VAL
parameter \SATA_MAX_BURST
parameter \SATA_MAX_INIT
parameter \SATA_MAX_WAKE
parameter \SATA_MIN_BURST
parameter \SATA_MIN_INIT
parameter \SATA_MIN_WAKE
parameter \SHOW_REALIGN_COMMA
parameter \SIM_CPLLREFCLK_SEL
parameter \SIM_RECEIVER_DETECT_PASS
parameter \SIM_RESET_SPEEDUP
parameter \SIM_TX_EIDLE_DRIVE_LEVEL
parameter \SIM_VERSION
parameter \TERM_RCAL_CFG
parameter \TERM_RCAL_OVRD
parameter \TRANS_TIME_RATE
parameter \TST_RSV
parameter \TXBUF_EN
parameter \TXBUF_RESET_ON_RATE_CHANGE
parameter \TXDLY_CFG
parameter \TXDLY_LCFG
parameter \TXDLY_TAP_CFG
parameter \TXGEARBOX_EN
parameter \TXOUT_DIV
parameter \TXPCSRESET_TIME
parameter \TXPHDLY_CFG
parameter \TXPH_CFG
parameter \TXPH_MONITOR_SEL
parameter \TXPMARESET_TIME
parameter \TX_CLK25_DIV
parameter \TX_CLKMUX_PD
parameter \TX_DATA_WIDTH
parameter \TX_DEEMPH0
parameter \TX_DEEMPH1
parameter \TX_DRIVE_MODE
parameter \TX_EIDLE_ASSERT_DELAY
parameter \TX_EIDLE_DEASSERT_DELAY
parameter \TX_INT_DATAWIDTH
parameter \TX_LOOPBACK_DRIVE_HIZ
parameter \TX_MAINCURSOR_SEL
parameter \TX_MARGIN_FULL_0
parameter \TX_MARGIN_FULL_1
parameter \TX_MARGIN_FULL_2
parameter \TX_MARGIN_FULL_3
parameter \TX_MARGIN_FULL_4
parameter \TX_MARGIN_LOW_0
parameter \TX_MARGIN_LOW_1
parameter \TX_MARGIN_LOW_2
parameter \TX_MARGIN_LOW_3
parameter \TX_MARGIN_LOW_4
parameter \TX_PREDRIVER_MODE
parameter \TX_QPI_STATUS_EN
parameter \TX_RXDETECT_CFG
parameter \TX_RXDETECT_REF
parameter \TX_XCLK_SEL
parameter \UCODEER_CLR
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:14421"
wire input 65 \CFGRESET
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:14579"
wire width 4 input 215 \CLKRSVD
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:14357"
wire output 1 \CPLLFBCLKLOST
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:14358"
wire output 2 \CPLLLOCK
attribute \invertible_pin "IS_CPLLLOCKDETCLK_INVERTED"
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:14423"
wire input 66 \CPLLLOCKDETCLK
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:14424"
wire input 67 \CPLLLOCKEN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:14425"
wire input 68 \CPLLPD
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:14359"
wire output 3 \CPLLREFCLKLOST
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:14567"
wire width 3 input 203 \CPLLREFCLKSEL
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:14426"
wire input 69 \CPLLRESET
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:14415"
wire width 8 output 59 \DMONITOROUT
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:14594"
wire width 9 input 230 \DRPADDR
attribute \invertible_pin "IS_DRPCLK_INVERTED"
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:14428"
wire input 70 \DRPCLK
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:14557"
wire width 16 input 193 \DRPDI
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:14403"
wire width 16 output 47 \DRPDO
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:14429"
wire input 71 \DRPEN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:14360"
wire output 4 \DRPRDY
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:14430"
wire input 72 \DRPWE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:14361"
wire output 5 \EYESCANDATAERROR
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:14431"
wire input 73 \EYESCANMODE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:14432"
wire input 74 \EYESCANRESET
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:14433"
wire input 75 \EYESCANTRIGGER
attribute \invertible_pin "IS_GTGREFCLK_INVERTED"
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:14435"
wire input 76 \GTGREFCLK
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:14436"
wire input 77 \GTNORTHREFCLK0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:14437"
wire input 78 \GTNORTHREFCLK1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:14438"
wire input 79 \GTREFCLK0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:14439"
wire input 80 \GTREFCLK1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:14362"
wire output 6 \GTREFCLKMONITOR
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:14440"
wire input 81 \GTRESETSEL
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:14558"
wire width 16 input 194 \GTRSVD
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:14441"
wire input 82 \GTRXRESET
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:14442"
wire input 83 \GTSOUTHREFCLK0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:14443"
wire input 84 \GTSOUTHREFCLK1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:14444"
wire input 85 \GTTXRESET
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:14445"
wire input 86 \GTXRXN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:14446"
wire input 87 \GTXRXP
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:14363"
wire output 7 \GTXTXN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:14364"
wire output 8 \GTXTXP
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:14568"
wire width 3 input 204 \LOOPBACK
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:14559"
wire width 16 input 195 \PCSRSVDIN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:14581"
wire width 5 input 217 \PCSRSVDIN2
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:14404"
wire width 16 output 48 \PCSRSVDOUT
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:14365"
wire output 9 \PHYSTATUS
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:14583"
wire width 5 input 219 \PMARSVDIN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:14582"
wire width 5 input 218 \PMARSVDIN2
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:14447"
wire input 88 \QPLLCLK
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:14448"
wire input 89 \QPLLREFCLK
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:14449"
wire input 90 \RESETOVRD
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:14450"
wire input 91 \RX8B10BEN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:14451"
wire input 92 \RXBUFRESET
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:14407"
wire width 3 output 51 \RXBUFSTATUS
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:14366"
wire output 10 \RXBYTEISALIGNED
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:14367"
wire output 11 \RXBYTEREALIGN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:14452"
wire input 93 \RXCDRFREQRESET
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:14453"
wire input 94 \RXCDRHOLD
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:14368"
wire output 12 \RXCDRLOCK
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:14454"
wire input 95 \RXCDROVRDEN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:14455"
wire input 96 \RXCDRRESET
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:14456"
wire input 97 \RXCDRRESETRSV
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:14369"
wire output 13 \RXCHANBONDSEQ
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:14370"
wire output 14 \RXCHANISALIGNED
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:14371"
wire output 15 \RXCHANREALIGN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:14416"
wire width 8 output 60 \RXCHARISCOMMA
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:14417"
wire width 8 output 61 \RXCHARISK
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:14457"
wire input 98 \RXCHBONDEN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:14584"
wire width 5 input 220 \RXCHBONDI
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:14569"
wire width 3 input 205 \RXCHBONDLEVEL
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:14458"
wire input 99 \RXCHBONDMASTER
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:14410"
wire width 5 output 54 \RXCHBONDO
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:14459"
wire input 100 \RXCHBONDSLAVE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:14405"
wire width 2 output 49 \RXCLKCORCNT
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:14372"
wire output 16 \RXCOMINITDET
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:14373"
wire output 17 \RXCOMMADET
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:14460"
wire input 101 \RXCOMMADETEN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:14374"
wire output 18 \RXCOMSASDET
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:14375"
wire output 19 \RXCOMWAKEDET
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:14413"
wire width 64 output 57 \RXDATA
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:14376"
wire output 20 \RXDATAVALID
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:14461"
wire input 102 \RXDDIEN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:14462"
wire input 103 \RXDFEAGCHOLD
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:14463"
wire input 104 \RXDFEAGCOVRDEN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:14464"
wire input 105 \RXDFECM1EN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:14465"
wire input 106 \RXDFELFHOLD
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:14466"
wire input 107 \RXDFELFOVRDEN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:14467"
wire input 108 \RXDFELPMRESET
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:14468"
wire input 109 \RXDFETAP2HOLD
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:14469"
wire input 110 \RXDFETAP2OVRDEN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:14470"
wire input 111 \RXDFETAP3HOLD
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:14471"
wire input 112 \RXDFETAP3OVRDEN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:14472"
wire input 113 \RXDFETAP4HOLD
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:14473"
wire input 114 \RXDFETAP4OVRDEN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:14474"
wire input 115 \RXDFETAP5HOLD
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:14475"
wire input 116 \RXDFETAP5OVRDEN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:14476"
wire input 117 \RXDFEUTHOLD
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:14477"
wire input 118 \RXDFEUTOVRDEN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:14478"
wire input 119 \RXDFEVPHOLD
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:14479"
wire input 120 \RXDFEVPOVRDEN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:14480"
wire input 121 \RXDFEVSEN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:14481"
wire input 122 \RXDFEXYDEN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:14482"
wire input 123 \RXDFEXYDHOLD
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:14483"
wire input 124 \RXDFEXYDOVRDEN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:14418"
wire width 8 output 62 \RXDISPERR
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:14484"
wire input 125 \RXDLYBYPASS
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:14485"
wire input 126 \RXDLYEN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:14486"
wire input 127 \RXDLYOVRDEN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:14487"
wire input 128 \RXDLYSRESET
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:14377"
wire output 21 \RXDLYSRESETDONE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:14378"
wire output 22 \RXELECIDLE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:14561"
wire width 2 input 197 \RXELECIDLEMODE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:14488"
wire input 129 \RXGEARBOXSLIP
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:14408"
wire width 3 output 52 \RXHEADER
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:14379"
wire output 23 \RXHEADERVALID
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:14489"
wire input 130 \RXLPMEN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:14490"
wire input 131 \RXLPMHFHOLD
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:14491"
wire input 132 \RXLPMHFOVRDEN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:14492"
wire input 133 \RXLPMLFHOLD
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:14493"
wire input 134 \RXLPMLFKLOVRDEN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:14494"
wire input 135 \RXMCOMMAALIGNEN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:14414"
wire width 7 output 58 \RXMONITOROUT
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:14562"
wire width 2 input 198 \RXMONITORSEL
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:14419"
wire width 8 output 63 \RXNOTINTABLE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:14495"
wire input 136 \RXOOBRESET
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:14496"
wire input 137 \RXOSHOLD
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:14497"
wire input 138 \RXOSOVRDEN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:14380"
wire output 24 \RXOUTCLK
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:14381"
wire output 25 \RXOUTCLKFABRIC
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:14382"
wire output 26 \RXOUTCLKPCS
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:14570"
wire width 3 input 206 \RXOUTCLKSEL
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:14498"
wire input 139 \RXPCOMMAALIGNEN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:14499"
wire input 140 \RXPCSRESET
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:14563"
wire width 2 input 199 \RXPD
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:14500"
wire input 141 \RXPHALIGN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:14383"
wire output 27 \RXPHALIGNDONE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:14501"
wire input 142 \RXPHALIGNEN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:14502"
wire input 143 \RXPHDLYPD
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:14503"
wire input 144 \RXPHDLYRESET
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:14411"
wire width 5 output 55 \RXPHMONITOR
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:14504"
wire input 145 \RXPHOVRDEN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:14412"
wire width 5 output 56 \RXPHSLIPMONITOR
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:14505"
wire input 146 \RXPMARESET
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:14506"
wire input 147 \RXPOLARITY
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:14507"
wire input 148 \RXPRBSCNTRESET
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:14384"
wire output 28 \RXPRBSERR
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:14571"
wire width 3 input 207 \RXPRBSSEL
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:14508"
wire input 149 \RXQPIEN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:14385"
wire output 29 \RXQPISENN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:14386"
wire output 30 \RXQPISENP
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:14572"
wire width 3 input 208 \RXRATE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:14387"
wire output 31 \RXRATEDONE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:14388"
wire output 32 \RXRESETDONE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:14509"
wire input 150 \RXSLIDE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:14389"
wire output 33 \RXSTARTOFSEQ
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:14409"
wire width 3 output 53 \RXSTATUS
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:14564"
wire width 2 input 200 \RXSYSCLKSEL
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:14510"
wire input 151 \RXUSERRDY
attribute \invertible_pin "IS_RXUSRCLK_INVERTED"
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:14514"
wire input 153 \RXUSRCLK
attribute \invertible_pin "IS_RXUSRCLK2_INVERTED"
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:14512"
wire input 152 \RXUSRCLK2
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:14390"
wire output 34 \RXVALID
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:14515"
wire input 154 \SETERRSTATUS
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:14560"
wire width 20 input 196 \TSTIN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:14420"
wire width 10 output 64 \TSTOUT
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:14590"
wire width 8 input 226 \TX8B10BBYPASS
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:14516"
wire input 155 \TX8B10BEN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:14573"
wire width 3 input 209 \TXBUFDIFFCTRL
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:14406"
wire width 2 output 50 \TXBUFSTATUS
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:14591"
wire width 8 input 227 \TXCHARDISPMODE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:14592"
wire width 8 input 228 \TXCHARDISPVAL
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:14593"
wire width 8 input 229 \TXCHARISK
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:14391"
wire output 35 \TXCOMFINISH
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:14517"
wire input 156 \TXCOMINIT
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:14518"
wire input 157 \TXCOMSAS
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:14519"
wire input 158 \TXCOMWAKE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:14587"
wire width 64 input 223 \TXDATA
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:14520"
wire input 159 \TXDEEMPH
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:14521"
wire input 160 \TXDETECTRX
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:14580"
wire width 4 input 216 \TXDIFFCTRL
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:14522"
wire input 161 \TXDIFFPD
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:14523"
wire input 162 \TXDLYBYPASS
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:14524"
wire input 163 \TXDLYEN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:14525"
wire input 164 \TXDLYHOLD
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:14526"
wire input 165 \TXDLYOVRDEN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:14527"
wire input 166 \TXDLYSRESET
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:14392"
wire output 36 \TXDLYSRESETDONE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:14528"
wire input 167 \TXDLYUPDOWN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:14529"
wire input 168 \TXELECIDLE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:14393"
wire output 37 \TXGEARBOXREADY
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:14574"
wire width 3 input 210 \TXHEADER
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:14530"
wire input 169 \TXINHIBIT
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:14588"
wire width 7 input 224 \TXMAINCURSOR
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:14575"
wire width 3 input 211 \TXMARGIN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:14394"
wire output 38 \TXOUTCLK
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:14395"
wire output 39 \TXOUTCLKFABRIC
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:14396"
wire output 40 \TXOUTCLKPCS
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:14576"
wire width 3 input 212 \TXOUTCLKSEL
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:14531"
wire input 170 \TXPCSRESET
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:14565"
wire width 2 input 201 \TXPD
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:14532"
wire input 171 \TXPDELECIDLEMODE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:14533"
wire input 172 \TXPHALIGN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:14397"
wire output 41 \TXPHALIGNDONE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:14534"
wire input 173 \TXPHALIGNEN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:14535"
wire input 174 \TXPHDLYPD
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:14536"
wire input 175 \TXPHDLYRESET
attribute \invertible_pin "IS_TXPHDLYTSTCLK_INVERTED"
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:14538"
wire input 176 \TXPHDLYTSTCLK
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:14539"
wire input 177 \TXPHINIT
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:14398"
wire output 42 \TXPHINITDONE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:14540"
wire input 178 \TXPHOVRDEN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:14541"
wire input 179 \TXPISOPD
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:14542"
wire input 180 \TXPMARESET
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:14543"
wire input 181 \TXPOLARITY
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:14585"
wire width 5 input 221 \TXPOSTCURSOR
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:14544"
wire input 182 \TXPOSTCURSORINV
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:14545"
wire input 183 \TXPRBSFORCEERR
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:14577"
wire width 3 input 213 \TXPRBSSEL
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:14586"
wire width 5 input 222 \TXPRECURSOR
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:14546"
wire input 184 \TXPRECURSORINV
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:14547"
wire input 185 \TXQPIBIASEN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:14399"
wire output 43 \TXQPISENN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:14400"
wire output 44 \TXQPISENP
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:14548"
wire input 186 \TXQPISTRONGPDOWN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:14549"
wire input 187 \TXQPIWEAKPUP
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:14578"
wire width 3 input 214 \TXRATE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:14401"
wire output 45 \TXRATEDONE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:14402"
wire output 46 \TXRESETDONE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:14589"
wire width 7 input 225 \TXSEQUENCE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:14550"
wire input 188 \TXSTARTSEQ
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:14551"
wire input 189 \TXSWING
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:14566"
wire width 2 input 202 \TXSYSCLKSEL
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:14552"
wire input 190 \TXUSERRDY
attribute \invertible_pin "IS_TXUSRCLK_INVERTED"
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:14556"
wire input 192 \TXUSRCLK
attribute \invertible_pin "IS_TXUSRCLK2_INVERTED"
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:14554"
wire input 191 \TXUSRCLK2
end
attribute \blackbox 1
attribute \cells_not_processed 1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:14597"
module \GTXE2_COMMON
parameter \BIAS_CFG
parameter \COMMON_CFG
parameter \IS_DRPCLK_INVERTED
parameter \IS_GTGREFCLK_INVERTED
parameter \IS_QPLLLOCKDETCLK_INVERTED
parameter \QPLL_CFG
parameter \QPLL_CLKOUT_CFG
parameter \QPLL_COARSE_FREQ_OVRD
parameter \QPLL_COARSE_FREQ_OVRD_EN
parameter \QPLL_CP
parameter \QPLL_CP_MONITOR_EN
parameter \QPLL_DMONITOR_SEL
parameter \QPLL_FBDIV
parameter \QPLL_FBDIV_MONITOR_EN
parameter \QPLL_FBDIV_RATIO
parameter \QPLL_INIT_CFG
parameter \QPLL_LOCK_CFG
parameter \QPLL_LPF
parameter \QPLL_REFCLK_DIV
parameter \SIM_QPLLREFCLK_SEL
parameter \SIM_RESET_SPEEDUP
parameter \SIM_VERSION
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:14629"
wire input 10 \BGBYPASSB
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:14630"
wire input 11 \BGMONITORENB
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:14631"
wire input 12 \BGPDB
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:14654"
wire width 5 input 32 \BGRCALOVRD
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:14656"
wire width 8 input 34 \DRPADDR
attribute \invertible_pin "IS_DRPCLK_INVERTED"
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:14633"
wire input 13 \DRPCLK
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:14651"
wire width 16 input 29 \DRPDI
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:14627"
wire width 16 output 8 \DRPDO
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:14634"
wire input 14 \DRPEN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:14620"
wire output 1 \DRPRDY
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:14635"
wire input 15 \DRPWE
attribute \invertible_pin "IS_GTGREFCLK_INVERTED"
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:14637"
wire input 16 \GTGREFCLK
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:14638"
wire input 17 \GTNORTHREFCLK0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:14639"
wire input 18 \GTNORTHREFCLK1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:14640"
wire input 19 \GTREFCLK0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:14641"
wire input 20 \GTREFCLK1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:14642"
wire input 21 \GTSOUTHREFCLK0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:14643"
wire input 22 \GTSOUTHREFCLK1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:14657"
wire width 8 input 35 \PMARSVD
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:14628"
wire width 8 output 9 \QPLLDMONITOR
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:14621"
wire output 2 \QPLLFBCLKLOST
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:14622"
wire output 3 \QPLLLOCK
attribute \invertible_pin "IS_QPLLLOCKDETCLK_INVERTED"
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:14645"
wire input 23 \QPLLLOCKDETCLK
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:14646"
wire input 24 \QPLLLOCKEN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:14623"
wire output 4 \QPLLOUTCLK
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:14624"
wire output 5 \QPLLOUTREFCLK
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:14647"
wire input 25 \QPLLOUTRESET
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:14648"
wire input 26 \QPLLPD
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:14625"
wire output 6 \QPLLREFCLKLOST
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:14653"
wire width 3 input 31 \QPLLREFCLKSEL
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:14649"
wire input 27 \QPLLRESET
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:14652"
wire width 16 input 30 \QPLLRSVD1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:14655"
wire width 5 input 33 \QPLLRSVD2
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:14650"
wire input 28 \RCALENB
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:14626"
wire output 7 \REFCLKOUTMONITOR
end
attribute \blackbox 1
attribute \cells_not_processed 1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11651"
module \GTX_DUAL
parameter \AC_CAP_DIS_0
parameter \AC_CAP_DIS_1
parameter \ALIGN_COMMA_WORD_0
parameter \ALIGN_COMMA_WORD_1
parameter \CB2_INH_CC_PERIOD_0
parameter \CB2_INH_CC_PERIOD_1
parameter \CDR_PH_ADJ_TIME
parameter \CHAN_BOND_1_MAX_SKEW_0
parameter \CHAN_BOND_1_MAX_SKEW_1
parameter \CHAN_BOND_2_MAX_SKEW_0
parameter \CHAN_BOND_2_MAX_SKEW_1
parameter \CHAN_BOND_KEEP_ALIGN_0
parameter \CHAN_BOND_KEEP_ALIGN_1
parameter \CHAN_BOND_LEVEL_0
parameter \CHAN_BOND_LEVEL_1
parameter \CHAN_BOND_MODE_0
parameter \CHAN_BOND_MODE_1
parameter \CHAN_BOND_SEQ_1_1_0
parameter \CHAN_BOND_SEQ_1_1_1
parameter \CHAN_BOND_SEQ_1_2_0
parameter \CHAN_BOND_SEQ_1_2_1
parameter \CHAN_BOND_SEQ_1_3_0
parameter \CHAN_BOND_SEQ_1_3_1
parameter \CHAN_BOND_SEQ_1_4_0
parameter \CHAN_BOND_SEQ_1_4_1
parameter \CHAN_BOND_SEQ_1_ENABLE_0
parameter \CHAN_BOND_SEQ_1_ENABLE_1
parameter \CHAN_BOND_SEQ_2_1_0
parameter \CHAN_BOND_SEQ_2_1_1
parameter \CHAN_BOND_SEQ_2_2_0
parameter \CHAN_BOND_SEQ_2_2_1
parameter \CHAN_BOND_SEQ_2_3_0
parameter \CHAN_BOND_SEQ_2_3_1
parameter \CHAN_BOND_SEQ_2_4_0
parameter \CHAN_BOND_SEQ_2_4_1
parameter \CHAN_BOND_SEQ_2_ENABLE_0
parameter \CHAN_BOND_SEQ_2_ENABLE_1
parameter \CHAN_BOND_SEQ_2_USE_0
parameter \CHAN_BOND_SEQ_2_USE_1
parameter \CHAN_BOND_SEQ_LEN_0
parameter \CHAN_BOND_SEQ_LEN_1
parameter \CLK25_DIVIDER
parameter \CLKINDC_B
parameter \CLKRCV_TRST
parameter \CLK_CORRECT_USE_0
parameter \CLK_CORRECT_USE_1
parameter \CLK_COR_ADJ_LEN_0
parameter \CLK_COR_ADJ_LEN_1
parameter \CLK_COR_DET_LEN_0
parameter \CLK_COR_DET_LEN_1
parameter \CLK_COR_INSERT_IDLE_FLAG_0
parameter \CLK_COR_INSERT_IDLE_FLAG_1
parameter \CLK_COR_KEEP_IDLE_0
parameter \CLK_COR_KEEP_IDLE_1
parameter \CLK_COR_MAX_LAT_0
parameter \CLK_COR_MAX_LAT_1
parameter \CLK_COR_MIN_LAT_0
parameter \CLK_COR_MIN_LAT_1
parameter \CLK_COR_PRECEDENCE_0
parameter \CLK_COR_PRECEDENCE_1
parameter \CLK_COR_REPEAT_WAIT_0
parameter \CLK_COR_REPEAT_WAIT_1
parameter \CLK_COR_SEQ_1_1_0
parameter \CLK_COR_SEQ_1_1_1
parameter \CLK_COR_SEQ_1_2_0
parameter \CLK_COR_SEQ_1_2_1
parameter \CLK_COR_SEQ_1_3_0
parameter \CLK_COR_SEQ_1_3_1
parameter \CLK_COR_SEQ_1_4_0
parameter \CLK_COR_SEQ_1_4_1
parameter \CLK_COR_SEQ_1_ENABLE_0
parameter \CLK_COR_SEQ_1_ENABLE_1
parameter \CLK_COR_SEQ_2_1_0
parameter \CLK_COR_SEQ_2_1_1
parameter \CLK_COR_SEQ_2_2_0
parameter \CLK_COR_SEQ_2_2_1
parameter \CLK_COR_SEQ_2_3_0
parameter \CLK_COR_SEQ_2_3_1
parameter \CLK_COR_SEQ_2_4_0
parameter \CLK_COR_SEQ_2_4_1
parameter \CLK_COR_SEQ_2_ENABLE_0
parameter \CLK_COR_SEQ_2_ENABLE_1
parameter \CLK_COR_SEQ_2_USE_0
parameter \CLK_COR_SEQ_2_USE_1
parameter \CM_TRIM_0
parameter \CM_TRIM_1
parameter \COMMA_10B_ENABLE_0
parameter \COMMA_10B_ENABLE_1
parameter \COMMA_DOUBLE_0
parameter \COMMA_DOUBLE_1
parameter \COM_BURST_VAL_0
parameter \COM_BURST_VAL_1
parameter \DEC_MCOMMA_DETECT_0
parameter \DEC_MCOMMA_DETECT_1
parameter \DEC_PCOMMA_DETECT_0
parameter \DEC_PCOMMA_DETECT_1
parameter \DEC_VALID_COMMA_ONLY_0
parameter \DEC_VALID_COMMA_ONLY_1
parameter \DFE_CAL_TIME
parameter \DFE_CFG_0
parameter \DFE_CFG_1
parameter \GEARBOX_ENDEC_0
parameter \GEARBOX_ENDEC_1
parameter \MCOMMA_10B_VALUE_0
parameter \MCOMMA_10B_VALUE_1
parameter \MCOMMA_DETECT_0
parameter \MCOMMA_DETECT_1
parameter \OOBDETECT_THRESHOLD_0
parameter \OOBDETECT_THRESHOLD_1
parameter \OOB_CLK_DIVIDER
parameter \OVERSAMPLE_MODE
parameter \PCI_EXPRESS_MODE_0
parameter \PCI_EXPRESS_MODE_1
parameter \PCOMMA_10B_VALUE_0
parameter \PCOMMA_10B_VALUE_1
parameter \PCOMMA_DETECT_0
parameter \PCOMMA_DETECT_1
parameter \PLL_COM_CFG
parameter \PLL_CP_CFG
parameter \PLL_DIVSEL_FB
parameter \PLL_DIVSEL_REF
parameter \PLL_FB_DCCEN
parameter \PLL_LKDET_CFG
parameter \PLL_RXDIVSEL_OUT_0
parameter \PLL_RXDIVSEL_OUT_1
parameter \PLL_SATA_0
parameter \PLL_SATA_1
parameter \PLL_TDCC_CFG
parameter \PLL_TXDIVSEL_OUT_0
parameter \PLL_TXDIVSEL_OUT_1
parameter \PMA_CDR_SCAN_0
parameter \PMA_CDR_SCAN_1
parameter \PMA_COM_CFG
parameter \PMA_RXSYNC_CFG_0
parameter \PMA_RXSYNC_CFG_1
parameter \PMA_RX_CFG_0
parameter \PMA_RX_CFG_1
parameter \PMA_TX_CFG_0
parameter \PMA_TX_CFG_1
parameter \PRBS_ERR_THRESHOLD_0
parameter \PRBS_ERR_THRESHOLD_1
parameter \RCV_TERM_GND_0
parameter \RCV_TERM_GND_1
parameter \RCV_TERM_VTTRX_0
parameter \RCV_TERM_VTTRX_1
parameter \RXGEARBOX_USE_0
parameter \RXGEARBOX_USE_1
parameter \RX_BUFFER_USE_0
parameter \RX_BUFFER_USE_1
parameter \RX_DECODE_SEQ_MATCH_0
parameter \RX_DECODE_SEQ_MATCH_1
parameter \RX_EN_IDLE_HOLD_CDR
parameter \RX_EN_IDLE_HOLD_DFE_0
parameter \RX_EN_IDLE_HOLD_DFE_1
parameter \RX_EN_IDLE_RESET_BUF_0
parameter \RX_EN_IDLE_RESET_BUF_1
parameter \RX_EN_IDLE_RESET_FR
parameter \RX_EN_IDLE_RESET_PH
parameter \RX_IDLE_HI_CNT_0
parameter \RX_IDLE_HI_CNT_1
parameter \RX_IDLE_LO_CNT_0
parameter \RX_IDLE_LO_CNT_1
parameter \RX_LOSS_OF_SYNC_FSM_0
parameter \RX_LOSS_OF_SYNC_FSM_1
parameter \RX_LOS_INVALID_INCR_0
parameter \RX_LOS_INVALID_INCR_1
parameter \RX_LOS_THRESHOLD_0
parameter \RX_LOS_THRESHOLD_1
parameter \RX_SLIDE_MODE_0
parameter \RX_SLIDE_MODE_1
parameter \RX_STATUS_FMT_0
parameter \RX_STATUS_FMT_1
parameter \RX_XCLK_SEL_0
parameter \RX_XCLK_SEL_1
parameter \SATA_BURST_VAL_0
parameter \SATA_BURST_VAL_1
parameter \SATA_IDLE_VAL_0
parameter \SATA_IDLE_VAL_1
parameter \SATA_MAX_BURST_0
parameter \SATA_MAX_BURST_1
parameter \SATA_MAX_INIT_0
parameter \SATA_MAX_INIT_1
parameter \SATA_MAX_WAKE_0
parameter \SATA_MAX_WAKE_1
parameter \SATA_MIN_BURST_0
parameter \SATA_MIN_BURST_1
parameter \SATA_MIN_INIT_0
parameter \SATA_MIN_INIT_1
parameter \SATA_MIN_WAKE_0
parameter \SATA_MIN_WAKE_1
parameter \SIM_GTXRESET_SPEEDUP
parameter \SIM_PLL_PERDIV2
parameter \SIM_RECEIVER_DETECT_PASS_0
parameter \SIM_RECEIVER_DETECT_PASS_1
parameter \STEPPING
parameter \TERMINATION_CTRL
parameter \TERMINATION_IMP_0
parameter \TERMINATION_IMP_1
parameter \TERMINATION_OVRD
parameter \TRANS_TIME_FROM_P2_0
parameter \TRANS_TIME_FROM_P2_1
parameter \TRANS_TIME_NON_P2_0
parameter \TRANS_TIME_NON_P2_1
parameter \TRANS_TIME_TO_P2_0
parameter \TRANS_TIME_TO_P2_1
parameter \TXGEARBOX_USE_0
parameter \TXGEARBOX_USE_1
parameter \TXRX_INVERT_0
parameter \TXRX_INVERT_1
parameter \TX_BUFFER_USE_0
parameter \TX_BUFFER_USE_1
parameter \TX_DETECT_RX_CFG_0
parameter \TX_DETECT_RX_CFG_1
parameter \TX_IDLE_DELAY_0
parameter \TX_IDLE_DELAY_1
parameter \TX_XCLK_SEL_0
parameter \TX_XCLK_SEL_1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11957"
wire input 89 \CLKIN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12082"
wire width 7 input 214 \DADDR
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11958"
wire input 90 \DCLK
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11959"
wire input 91 \DEN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12080"
wire width 6 input 212 \DFECLKDLYADJ0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12081"
wire width 6 input 213 \DFECLKDLYADJ1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11955"
wire width 6 output 87 \DFECLKDLYADJMONITOR0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11956"
wire width 6 output 88 \DFECLKDLYADJMONITOR1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11949"
wire width 5 output 81 \DFEEYEDACMONITOR0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11950"
wire width 5 output 82 \DFEEYEDACMONITOR1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11917"
wire width 3 output 49 \DFESENSCAL0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11918"
wire width 3 output 50 \DFESENSCAL1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12076"
wire width 5 input 208 \DFETAP10
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12077"
wire width 5 input 209 \DFETAP11
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11951"
wire width 5 output 83 \DFETAP1MONITOR0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11952"
wire width 5 output 84 \DFETAP1MONITOR1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12078"
wire width 5 input 210 \DFETAP20
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12079"
wire width 5 input 211 \DFETAP21
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11953"
wire width 5 output 85 \DFETAP2MONITOR0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11954"
wire width 5 output 86 \DFETAP2MONITOR1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12058"
wire width 4 input 190 \DFETAP30
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12059"
wire width 4 input 191 \DFETAP31
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11929"
wire width 4 output 61 \DFETAP3MONITOR0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11930"
wire width 4 output 62 \DFETAP3MONITOR1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12060"
wire width 4 input 192 \DFETAP40
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12061"
wire width 4 input 193 \DFETAP41
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11931"
wire width 4 output 63 \DFETAP4MONITOR0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11932"
wire width 4 output 64 \DFETAP4MONITOR1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12033"
wire width 16 input 165 \DI
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11912"
wire width 16 output 44 \DO
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11869"
wire output 1 \DRDY
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11960"
wire input 92 \DWE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11961"
wire input 93 \GTXRESET
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12032"
wire width 14 input 164 \GTXTEST
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11962"
wire input 94 \INTDATAWIDTH
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12048"
wire width 3 input 180 \LOOPBACK0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12049"
wire width 3 input 181 \LOOPBACK1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11870"
wire output 2 \PHYSTATUS0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11871"
wire output 3 \PHYSTATUS1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11872"
wire output 4 \PLLLKDET
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11963"
wire input 95 \PLLLKDETEN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11964"
wire input 96 \PLLPOWERDOWN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11965"
wire input 97 \PRBSCNTRESET0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11966"
wire input 98 \PRBSCNTRESET1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11873"
wire output 5 \REFCLKOUT
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11967"
wire input 99 \REFCLKPWRDNB
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11874"
wire output 6 \RESETDONE0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11875"
wire output 7 \RESETDONE1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11968"
wire input 100 \RXBUFRESET0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11969"
wire input 101 \RXBUFRESET1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11919"
wire width 3 output 51 \RXBUFSTATUS0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11920"
wire width 3 output 52 \RXBUFSTATUS1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11876"
wire output 8 \RXBYTEISALIGNED0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11877"
wire output 9 \RXBYTEISALIGNED1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11878"
wire output 10 \RXBYTEREALIGN0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11879"
wire output 11 \RXBYTEREALIGN1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11970"
wire input 102 \RXCDRRESET0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11971"
wire input 103 \RXCDRRESET1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11880"
wire output 12 \RXCHANBONDSEQ0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11881"
wire output 13 \RXCHANBONDSEQ1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11882"
wire output 14 \RXCHANISALIGNED0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11883"
wire output 15 \RXCHANISALIGNED1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11884"
wire output 16 \RXCHANREALIGN0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11885"
wire output 17 \RXCHANREALIGN1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11933"
wire width 4 output 65 \RXCHARISCOMMA0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11934"
wire width 4 output 66 \RXCHARISCOMMA1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11935"
wire width 4 output 67 \RXCHARISK0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11936"
wire width 4 output 68 \RXCHARISK1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12062"
wire width 4 input 194 \RXCHBONDI0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12063"
wire width 4 input 195 \RXCHBONDI1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11937"
wire width 4 output 69 \RXCHBONDO0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11938"
wire width 4 output 70 \RXCHBONDO1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11921"
wire width 3 output 53 \RXCLKCORCNT0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11922"
wire width 3 output 54 \RXCLKCORCNT1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11886"
wire output 18 \RXCOMMADET0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11887"
wire output 19 \RXCOMMADET1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11972"
wire input 104 \RXCOMMADETUSE0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11973"
wire input 105 \RXCOMMADETUSE1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11927"
wire width 32 output 59 \RXDATA0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11928"
wire width 32 output 60 \RXDATA1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11888"
wire output 20 \RXDATAVALID0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11889"
wire output 21 \RXDATAVALID1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12034"
wire width 2 input 166 \RXDATAWIDTH0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12035"
wire width 2 input 167 \RXDATAWIDTH1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11974"
wire input 106 \RXDEC8B10BUSE0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11975"
wire input 107 \RXDEC8B10BUSE1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11939"
wire width 4 output 71 \RXDISPERR0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11940"
wire width 4 output 72 \RXDISPERR1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11890"
wire output 22 \RXELECIDLE0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11891"
wire output 23 \RXELECIDLE1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11976"
wire input 108 \RXENCHANSYNC0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11977"
wire input 109 \RXENCHANSYNC1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11978"
wire input 110 \RXENEQB0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11979"
wire input 111 \RXENEQB1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11980"
wire input 112 \RXENMCOMMAALIGN0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11981"
wire input 113 \RXENMCOMMAALIGN1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11982"
wire input 114 \RXENPCOMMAALIGN0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11983"
wire input 115 \RXENPCOMMAALIGN1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11984"
wire input 116 \RXENPMAPHASEALIGN0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11985"
wire input 117 \RXENPMAPHASEALIGN1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12036"
wire width 2 input 168 \RXENPRBSTST0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12037"
wire width 2 input 169 \RXENPRBSTST1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11986"
wire input 118 \RXENSAMPLEALIGN0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11987"
wire input 119 \RXENSAMPLEALIGN1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12038"
wire width 2 input 170 \RXEQMIX0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12039"
wire width 2 input 171 \RXEQMIX1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12064"
wire width 4 input 196 \RXEQPOLE0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12065"
wire width 4 input 197 \RXEQPOLE1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11988"
wire input 120 \RXGEARBOXSLIP0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11989"
wire input 121 \RXGEARBOXSLIP1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11923"
wire width 3 output 55 \RXHEADER0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11924"
wire width 3 output 56 \RXHEADER1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11892"
wire output 24 \RXHEADERVALID0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11893"
wire output 25 \RXHEADERVALID1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11913"
wire width 2 output 45 \RXLOSSOFSYNC0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11914"
wire width 2 output 46 \RXLOSSOFSYNC1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11990"
wire input 122 \RXN0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11991"
wire input 123 \RXN1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11941"
wire width 4 output 73 \RXNOTINTABLE0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11942"
wire width 4 output 74 \RXNOTINTABLE1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11894"
wire output 26 \RXOVERSAMPLEERR0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11895"
wire output 27 \RXOVERSAMPLEERR1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11992"
wire input 124 \RXP0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11993"
wire input 125 \RXP1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11994"
wire input 126 \RXPMASETPHASE0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11995"
wire input 127 \RXPMASETPHASE1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11996"
wire input 128 \RXPOLARITY0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11997"
wire input 129 \RXPOLARITY1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12040"
wire width 2 input 172 \RXPOWERDOWN0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12041"
wire width 2 input 173 \RXPOWERDOWN1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11896"
wire output 28 \RXPRBSERR0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11897"
wire output 29 \RXPRBSERR1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11898"
wire output 30 \RXRECCLK0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11899"
wire output 31 \RXRECCLK1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11998"
wire input 130 \RXRESET0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11999"
wire input 131 \RXRESET1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11943"
wire width 4 output 75 \RXRUNDISP0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11944"
wire width 4 output 76 \RXRUNDISP1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12000"
wire input 132 \RXSLIDE0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12001"
wire input 133 \RXSLIDE1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11900"
wire output 32 \RXSTARTOFSEQ0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11901"
wire output 33 \RXSTARTOFSEQ1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11925"
wire width 3 output 57 \RXSTATUS0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11926"
wire width 3 output 58 \RXSTATUS1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12002"
wire input 134 \RXUSRCLK0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12003"
wire input 135 \RXUSRCLK1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12004"
wire input 136 \RXUSRCLK20
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12005"
wire input 137 \RXUSRCLK21
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11902"
wire output 34 \RXVALID0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11903"
wire output 35 \RXVALID1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12050"
wire width 3 input 182 \TXBUFDIFFCTRL0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12051"
wire width 3 input 183 \TXBUFDIFFCTRL1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11915"
wire width 2 output 47 \TXBUFSTATUS0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11916"
wire width 2 output 48 \TXBUFSTATUS1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12066"
wire width 4 input 198 \TXBYPASS8B10B0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12067"
wire width 4 input 199 \TXBYPASS8B10B1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12068"
wire width 4 input 200 \TXCHARDISPMODE0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12069"
wire width 4 input 201 \TXCHARDISPMODE1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12070"
wire width 4 input 202 \TXCHARDISPVAL0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12071"
wire width 4 input 203 \TXCHARDISPVAL1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12072"
wire width 4 input 204 \TXCHARISK0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12073"
wire width 4 input 205 \TXCHARISK1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12006"
wire input 138 \TXCOMSTART0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12007"
wire input 139 \TXCOMSTART1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12008"
wire input 140 \TXCOMTYPE0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12009"
wire input 141 \TXCOMTYPE1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12056"
wire width 32 input 188 \TXDATA0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12057"
wire width 32 input 189 \TXDATA1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12042"
wire width 2 input 174 \TXDATAWIDTH0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12043"
wire width 2 input 175 \TXDATAWIDTH1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12010"
wire input 142 \TXDETECTRX0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12011"
wire input 143 \TXDETECTRX1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12052"
wire width 3 input 184 \TXDIFFCTRL0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12053"
wire width 3 input 185 \TXDIFFCTRL1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12012"
wire input 144 \TXELECIDLE0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12013"
wire input 145 \TXELECIDLE1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12014"
wire input 146 \TXENC8B10BUSE0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12015"
wire input 147 \TXENC8B10BUSE1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12016"
wire input 148 \TXENPMAPHASEALIGN0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12017"
wire input 149 \TXENPMAPHASEALIGN1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12044"
wire width 2 input 176 \TXENPRBSTST0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12045"
wire width 2 input 177 \TXENPRBSTST1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11904"
wire output 36 \TXGEARBOXREADY0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11905"
wire output 37 \TXGEARBOXREADY1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12054"
wire width 3 input 186 \TXHEADER0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12055"
wire width 3 input 187 \TXHEADER1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12018"
wire input 150 \TXINHIBIT0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12019"
wire input 151 \TXINHIBIT1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11945"
wire width 4 output 77 \TXKERR0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11946"
wire width 4 output 78 \TXKERR1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11906"
wire output 38 \TXN0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11907"
wire output 39 \TXN1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11908"
wire output 40 \TXOUTCLK0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11909"
wire output 41 \TXOUTCLK1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11910"
wire output 42 \TXP0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11911"
wire output 43 \TXP1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12020"
wire input 152 \TXPMASETPHASE0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12021"
wire input 153 \TXPMASETPHASE1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12022"
wire input 154 \TXPOLARITY0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12023"
wire input 155 \TXPOLARITY1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12046"
wire width 2 input 178 \TXPOWERDOWN0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12047"
wire width 2 input 179 \TXPOWERDOWN1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12074"
wire width 4 input 206 \TXPREEMPHASIS0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12075"
wire width 4 input 207 \TXPREEMPHASIS1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12024"
wire input 156 \TXRESET0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12025"
wire input 157 \TXRESET1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11947"
wire width 4 output 79 \TXRUNDISP0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:11948"
wire width 4 output 80 \TXRUNDISP1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12083"
wire width 7 input 215 \TXSEQUENCE0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12084"
wire width 7 input 216 \TXSEQUENCE1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12026"
wire input 158 \TXSTARTSEQ0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12027"
wire input 159 \TXSTARTSEQ1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12028"
wire input 160 \TXUSRCLK0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12029"
wire input 161 \TXUSRCLK1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12030"
wire input 162 \TXUSRCLK20
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12031"
wire input 163 \TXUSRCLK21
end
attribute \blackbox 1
attribute \cells_not_processed 1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:16555"
module \GTYE3_CHANNEL
parameter \ACJTAG_DEBUG_MODE
parameter \ACJTAG_MODE
parameter \ACJTAG_RESET
parameter \ADAPT_CFG0
parameter \ADAPT_CFG1
parameter \ADAPT_CFG2
parameter \ALIGN_COMMA_DOUBLE
parameter \ALIGN_COMMA_ENABLE
parameter \ALIGN_COMMA_WORD
parameter \ALIGN_MCOMMA_DET
parameter \ALIGN_MCOMMA_VALUE
parameter \ALIGN_PCOMMA_DET
parameter \ALIGN_PCOMMA_VALUE
parameter \AUTO_BW_SEL_BYPASS
parameter \A_RXOSCALRESET
parameter \A_RXPROGDIVRESET
parameter \A_TXDIFFCTRL
parameter \A_TXPROGDIVRESET
parameter \CAPBYPASS_FORCE
parameter \CBCC_DATA_SOURCE_SEL
parameter \CDR_SWAP_MODE_EN
parameter \CHAN_BOND_KEEP_ALIGN
parameter \CHAN_BOND_MAX_SKEW
parameter \CHAN_BOND_SEQ_1_1
parameter \CHAN_BOND_SEQ_1_2
parameter \CHAN_BOND_SEQ_1_3
parameter \CHAN_BOND_SEQ_1_4
parameter \CHAN_BOND_SEQ_1_ENABLE
parameter \CHAN_BOND_SEQ_2_1
parameter \CHAN_BOND_SEQ_2_2
parameter \CHAN_BOND_SEQ_2_3
parameter \CHAN_BOND_SEQ_2_4
parameter \CHAN_BOND_SEQ_2_ENABLE
parameter \CHAN_BOND_SEQ_2_USE
parameter \CHAN_BOND_SEQ_LEN
parameter \CH_HSPMUX
parameter \CKCAL1_CFG_0
parameter \CKCAL1_CFG_1
parameter \CKCAL1_CFG_2
parameter \CKCAL1_CFG_3
parameter \CKCAL2_CFG_0
parameter \CKCAL2_CFG_1
parameter \CKCAL2_CFG_2
parameter \CKCAL2_CFG_3
parameter \CKCAL2_CFG_4
parameter \CKCAL_RSVD0
parameter \CKCAL_RSVD1
parameter \CLK_CORRECT_USE
parameter \CLK_COR_KEEP_IDLE
parameter \CLK_COR_MAX_LAT
parameter \CLK_COR_MIN_LAT
parameter \CLK_COR_PRECEDENCE
parameter \CLK_COR_REPEAT_WAIT
parameter \CLK_COR_SEQ_1_1
parameter \CLK_COR_SEQ_1_2
parameter \CLK_COR_SEQ_1_3
parameter \CLK_COR_SEQ_1_4
parameter \CLK_COR_SEQ_1_ENABLE
parameter \CLK_COR_SEQ_2_1
parameter \CLK_COR_SEQ_2_2
parameter \CLK_COR_SEQ_2_3
parameter \CLK_COR_SEQ_2_4
parameter \CLK_COR_SEQ_2_ENABLE
parameter \CLK_COR_SEQ_2_USE
parameter \CLK_COR_SEQ_LEN
parameter \CPLL_CFG0
parameter \CPLL_CFG1
parameter \CPLL_CFG2
parameter \CPLL_CFG3
parameter \CPLL_FBDIV
parameter \CPLL_FBDIV_45
parameter \CPLL_INIT_CFG0
parameter \CPLL_INIT_CFG1
parameter \CPLL_LOCK_CFG
parameter \CPLL_REFCLK_DIV
parameter \CTLE3_OCAP_EXT_CTRL
parameter \CTLE3_OCAP_EXT_EN
parameter \DDI_CTRL
parameter \DDI_REALIGN_WAIT
parameter \DEC_MCOMMA_DETECT
parameter \DEC_PCOMMA_DETECT
parameter \DEC_VALID_COMMA_ONLY
parameter \DFE_D_X_REL_POS
parameter \DFE_VCM_COMP_EN
parameter \DMONITOR_CFG0
parameter \DMONITOR_CFG1
parameter \ES_CLK_PHASE_SEL
parameter \ES_CONTROL
parameter \ES_ERRDET_EN
parameter \ES_EYE_SCAN_EN
parameter \ES_HORZ_OFFSET
parameter \ES_PMA_CFG
parameter \ES_PRESCALE
parameter \ES_QUALIFIER0
parameter \ES_QUALIFIER1
parameter \ES_QUALIFIER2
parameter \ES_QUALIFIER3
parameter \ES_QUALIFIER4
parameter \ES_QUALIFIER5
parameter \ES_QUALIFIER6
parameter \ES_QUALIFIER7
parameter \ES_QUALIFIER8
parameter \ES_QUALIFIER9
parameter \ES_QUAL_MASK0
parameter \ES_QUAL_MASK1
parameter \ES_QUAL_MASK2
parameter \ES_QUAL_MASK3
parameter \ES_QUAL_MASK4
parameter \ES_QUAL_MASK5
parameter \ES_QUAL_MASK6
parameter \ES_QUAL_MASK7
parameter \ES_QUAL_MASK8
parameter \ES_QUAL_MASK9
parameter \ES_SDATA_MASK0
parameter \ES_SDATA_MASK1
parameter \ES_SDATA_MASK2
parameter \ES_SDATA_MASK3
parameter \ES_SDATA_MASK4
parameter \ES_SDATA_MASK5
parameter \ES_SDATA_MASK6
parameter \ES_SDATA_MASK7
parameter \ES_SDATA_MASK8
parameter \ES_SDATA_MASK9
parameter \EVODD_PHI_CFG
parameter \EYE_SCAN_SWAP_EN
parameter \FTS_DESKEW_SEQ_ENABLE
parameter \FTS_LANE_DESKEW_CFG
parameter \FTS_LANE_DESKEW_EN
parameter \GEARBOX_MODE
parameter \GM_BIAS_SELECT
parameter \ISCAN_CK_PH_SEL2
parameter \LOCAL_MASTER
parameter \LOOP0_CFG
parameter \LOOP10_CFG
parameter \LOOP11_CFG
parameter \LOOP12_CFG
parameter \LOOP13_CFG
parameter \LOOP1_CFG
parameter \LOOP2_CFG
parameter \LOOP3_CFG
parameter \LOOP4_CFG
parameter \LOOP5_CFG
parameter \LOOP6_CFG
parameter \LOOP7_CFG
parameter \LOOP8_CFG
parameter \LOOP9_CFG
parameter \LPBK_BIAS_CTRL
parameter \LPBK_EN_RCAL_B
parameter \LPBK_EXT_RCAL
parameter \LPBK_RG_CTRL
parameter \OOBDIVCTL
parameter \OOB_PWRUP
parameter \PCI3_AUTO_REALIGN
parameter \PCI3_PIPE_RX_ELECIDLE
parameter \PCI3_RX_ASYNC_EBUF_BYPASS
parameter \PCI3_RX_ELECIDLE_EI2_ENABLE
parameter \PCI3_RX_ELECIDLE_H2L_COUNT
parameter \PCI3_RX_ELECIDLE_H2L_DISABLE
parameter \PCI3_RX_ELECIDLE_HI_COUNT
parameter \PCI3_RX_ELECIDLE_LP4_DISABLE
parameter \PCI3_RX_FIFO_DISABLE
parameter \PCIE_BUFG_DIV_CTRL
parameter \PCIE_RXPCS_CFG_GEN3
parameter \PCIE_RXPMA_CFG
parameter \PCIE_TXPCS_CFG_GEN3
parameter \PCIE_TXPMA_CFG
parameter \PCS_PCIE_EN
parameter \PCS_RSVD0
parameter \PCS_RSVD1
parameter \PD_TRANS_TIME_FROM_P2
parameter \PD_TRANS_TIME_NONE_P2
parameter \PD_TRANS_TIME_TO_P2
parameter \PLL_SEL_MODE_GEN12
parameter \PLL_SEL_MODE_GEN3
parameter \PMA_RSV0
parameter \PMA_RSV1
parameter \PREIQ_FREQ_BST
parameter \PROCESS_PAR
parameter \RATE_SW_USE_DRP
parameter \RESET_POWERSAVE_DISABLE
parameter \RXBUFRESET_TIME
parameter \RXBUF_ADDR_MODE
parameter \RXBUF_EIDLE_HI_CNT
parameter \RXBUF_EIDLE_LO_CNT
parameter \RXBUF_EN
parameter \RXBUF_RESET_ON_CB_CHANGE
parameter \RXBUF_RESET_ON_COMMAALIGN
parameter \RXBUF_RESET_ON_EIDLE
parameter \RXBUF_RESET_ON_RATE_CHANGE
parameter \RXBUF_THRESH_OVFLW
parameter \RXBUF_THRESH_OVRD
parameter \RXBUF_THRESH_UNDFLW
parameter \RXCDRFREQRESET_TIME
parameter \RXCDRPHRESET_TIME
parameter \RXCDR_CFG0
parameter \RXCDR_CFG0_GEN3
parameter \RXCDR_CFG1
parameter \RXCDR_CFG1_GEN3
parameter \RXCDR_CFG2
parameter \RXCDR_CFG2_GEN3
parameter \RXCDR_CFG3
parameter \RXCDR_CFG3_GEN3
parameter \RXCDR_CFG4
parameter \RXCDR_CFG4_GEN3
parameter \RXCDR_CFG5
parameter \RXCDR_CFG5_GEN3
parameter \RXCDR_FR_RESET_ON_EIDLE
parameter \RXCDR_HOLD_DURING_EIDLE
parameter \RXCDR_LOCK_CFG0
parameter \RXCDR_LOCK_CFG1
parameter \RXCDR_LOCK_CFG2
parameter \RXCDR_LOCK_CFG3
parameter \RXCDR_PH_RESET_ON_EIDLE
parameter \RXCFOKDONE_SRC
parameter \RXCFOK_CFG0
parameter \RXCFOK_CFG1
parameter \RXCFOK_CFG2
parameter \RXDFELPMRESET_TIME
parameter \RXDFELPM_KL_CFG0
parameter \RXDFELPM_KL_CFG1
parameter \RXDFELPM_KL_CFG2
parameter \RXDFE_CFG0
parameter \RXDFE_CFG1
parameter \RXDFE_GC_CFG0
parameter \RXDFE_GC_CFG1
parameter \RXDFE_GC_CFG2
parameter \RXDFE_H2_CFG0
parameter \RXDFE_H2_CFG1
parameter \RXDFE_H3_CFG0
parameter \RXDFE_H3_CFG1
parameter \RXDFE_H4_CFG0
parameter \RXDFE_H4_CFG1
parameter \RXDFE_H5_CFG0
parameter \RXDFE_H5_CFG1
parameter \RXDFE_H6_CFG0
parameter \RXDFE_H6_CFG1
parameter \RXDFE_H7_CFG0
parameter \RXDFE_H7_CFG1
parameter \RXDFE_H8_CFG0
parameter \RXDFE_H8_CFG1
parameter \RXDFE_H9_CFG0
parameter \RXDFE_H9_CFG1
parameter \RXDFE_HA_CFG0
parameter \RXDFE_HA_CFG1
parameter \RXDFE_HB_CFG0
parameter \RXDFE_HB_CFG1
parameter \RXDFE_HC_CFG0
parameter \RXDFE_HC_CFG1
parameter \RXDFE_HD_CFG0
parameter \RXDFE_HD_CFG1
parameter \RXDFE_HE_CFG0
parameter \RXDFE_HE_CFG1
parameter \RXDFE_HF_CFG0
parameter \RXDFE_HF_CFG1
parameter \RXDFE_OS_CFG0
parameter \RXDFE_OS_CFG1
parameter \RXDFE_PWR_SAVING
parameter \RXDFE_UT_CFG0
parameter \RXDFE_UT_CFG1
parameter \RXDFE_VP_CFG0
parameter \RXDFE_VP_CFG1
parameter \RXDLY_CFG
parameter \RXDLY_LCFG
parameter \RXELECIDLE_CFG
parameter \RXGBOX_FIFO_INIT_RD_ADDR
parameter \RXGEARBOX_EN
parameter \RXISCANRESET_TIME
parameter \RXLPM_CFG
parameter \RXLPM_GC_CFG
parameter \RXLPM_KH_CFG0
parameter \RXLPM_KH_CFG1
parameter \RXLPM_OS_CFG0
parameter \RXLPM_OS_CFG1
parameter \RXOOB_CFG
parameter \RXOOB_CLK_CFG
parameter \RXOSCALRESET_TIME
parameter \RXOUT_DIV
parameter \RXPCSRESET_TIME
parameter \RXPHBEACON_CFG
parameter \RXPHDLY_CFG
parameter \RXPHSAMP_CFG
parameter \RXPHSLIP_CFG
parameter \RXPH_MONITOR_SEL
parameter \RXPI_AUTO_BW_SEL_BYPASS
parameter \RXPI_CFG
parameter \RXPI_LPM
parameter \RXPI_RSV0
parameter \RXPI_SEL_LC
parameter \RXPI_STARTCODE
parameter \RXPI_VREFSEL
parameter \RXPMACLK_SEL
parameter \RXPMARESET_TIME
parameter \RXPRBS_ERR_LOOPBACK
parameter \RXPRBS_LINKACQ_CNT
parameter \RXSLIDE_AUTO_WAIT
parameter \RXSLIDE_MODE
parameter \RXSYNC_MULTILANE
parameter \RXSYNC_OVRD
parameter \RXSYNC_SKIP_DA
parameter \RX_AFE_CM_EN
parameter \RX_BIAS_CFG0
parameter \RX_BUFFER_CFG
parameter \RX_CAPFF_SARC_ENB
parameter \RX_CLK25_DIV
parameter \RX_CLKMUX_EN
parameter \RX_CLK_SLIP_OVRD
parameter \RX_CM_BUF_CFG
parameter \RX_CM_BUF_PD
parameter \RX_CM_SEL
parameter \RX_CM_TRIM
parameter \RX_CTLE1_KHKL
parameter \RX_CTLE2_KHKL
parameter \RX_CTLE3_AGC
parameter \RX_DATA_WIDTH
parameter \RX_DDI_SEL
parameter \RX_DEFER_RESET_BUF_EN
parameter \RX_DEGEN_CTRL
parameter \RX_DFELPM_CFG0
parameter \RX_DFELPM_CFG1
parameter \RX_DFELPM_KLKH_AGC_STUP_EN
parameter \RX_DFE_AGC_CFG0
parameter \RX_DFE_AGC_CFG1
parameter \RX_DFE_KL_LPM_KH_CFG0
parameter \RX_DFE_KL_LPM_KH_CFG1
parameter \RX_DFE_KL_LPM_KL_CFG0
parameter \RX_DFE_KL_LPM_KL_CFG1
parameter \RX_DFE_LPM_HOLD_DURING_EIDLE
parameter \RX_DISPERR_SEQ_MATCH
parameter \RX_DIV2_MODE_B
parameter \RX_DIVRESET_TIME
parameter \RX_EN_CTLE_RCAL_B
parameter \RX_EN_HI_LR
parameter \RX_EXT_RL_CTRL
parameter \RX_EYESCAN_VS_CODE
parameter \RX_EYESCAN_VS_NEG_DIR
parameter \RX_EYESCAN_VS_RANGE
parameter \RX_EYESCAN_VS_UT_SIGN
parameter \RX_FABINT_USRCLK_FLOP
parameter \RX_INT_DATAWIDTH
parameter \RX_PMA_POWER_SAVE
parameter \RX_PROGDIV_CFG
parameter \RX_PROGDIV_RATE
parameter \RX_RESLOAD_CTRL
parameter \RX_RESLOAD_OVRD
parameter \RX_SAMPLE_PERIOD
parameter \RX_SIG_VALID_DLY
parameter \RX_SUM_DFETAPREP_EN
parameter \RX_SUM_IREF_TUNE
parameter \RX_SUM_VCMTUNE
parameter \RX_SUM_VCM_OVWR
parameter \RX_SUM_VREF_TUNE
parameter \RX_TUNE_AFE_OS
parameter \RX_VREG_CTRL
parameter \RX_VREG_PDB
parameter \RX_WIDEMODE_CDR
parameter \RX_XCLK_SEL
parameter \RX_XMODE_SEL
parameter \SAS_MAX_COM
parameter \SAS_MIN_COM
parameter \SATA_BURST_SEQ_LEN
parameter \SATA_BURST_VAL
parameter \SATA_CPLL_CFG
parameter \SATA_EIDLE_VAL
parameter \SATA_MAX_BURST
parameter \SATA_MAX_INIT
parameter \SATA_MAX_WAKE
parameter \SATA_MIN_BURST
parameter \SATA_MIN_INIT
parameter \SATA_MIN_WAKE
parameter \SHOW_REALIGN_COMMA
parameter \SIM_MODE
parameter \SIM_RECEIVER_DETECT_PASS
parameter \SIM_RESET_SPEEDUP
parameter \SIM_TX_EIDLE_DRIVE_LEVEL
parameter \SIM_VERSION
parameter \TAPDLY_SET_TX
parameter \TEMPERATURE_PAR
parameter \TERM_RCAL_CFG
parameter \TERM_RCAL_OVRD
parameter \TRANS_TIME_RATE
parameter \TST_RSV0
parameter \TST_RSV1
parameter \TXBUF_EN
parameter \TXBUF_RESET_ON_RATE_CHANGE
parameter \TXDLY_CFG
parameter \TXDLY_LCFG
parameter \TXFIFO_ADDR_CFG
parameter \TXGBOX_FIFO_INIT_RD_ADDR
parameter \TXGEARBOX_EN
parameter \TXOUT_DIV
parameter \TXPCSRESET_TIME
parameter \TXPHDLY_CFG0
parameter \TXPHDLY_CFG1
parameter \TXPH_CFG
parameter \TXPH_CFG2
parameter \TXPH_MONITOR_SEL
parameter \TXPI_CFG0
parameter \TXPI_CFG1
parameter \TXPI_CFG2
parameter \TXPI_CFG3
parameter \TXPI_CFG4
parameter \TXPI_CFG5
parameter \TXPI_GRAY_SEL
parameter \TXPI_INVSTROBE_SEL
parameter \TXPI_LPM
parameter \TXPI_PPMCLK_SEL
parameter \TXPI_PPM_CFG
parameter \TXPI_RSV0
parameter \TXPI_SYNFREQ_PPM
parameter \TXPI_VREFSEL
parameter \TXPMARESET_TIME
parameter \TXSYNC_MULTILANE
parameter \TXSYNC_OVRD
parameter \TXSYNC_SKIP_DA
parameter \TX_CLK25_DIV
parameter \TX_CLKMUX_EN
parameter \TX_CLKREG_PDB
parameter \TX_CLKREG_SET
parameter \TX_DATA_WIDTH
parameter \TX_DCD_CFG
parameter \TX_DCD_EN
parameter \TX_DEEMPH0
parameter \TX_DEEMPH1
parameter \TX_DIVRESET_TIME
parameter \TX_DRIVE_MODE
parameter \TX_DRVMUX_CTRL
parameter \TX_EIDLE_ASSERT_DELAY
parameter \TX_EIDLE_DEASSERT_DELAY
parameter \TX_EML_PHI_TUNE
parameter \TX_FABINT_USRCLK_FLOP
parameter \TX_FIFO_BYP_EN
parameter \TX_IDLE_DATA_ZERO
parameter \TX_INT_DATAWIDTH
parameter \TX_LOOPBACK_DRIVE_HIZ
parameter \TX_MAINCURSOR_SEL
parameter \TX_MARGIN_FULL_0
parameter \TX_MARGIN_FULL_1
parameter \TX_MARGIN_FULL_2
parameter \TX_MARGIN_FULL_3
parameter \TX_MARGIN_FULL_4
parameter \TX_MARGIN_LOW_0
parameter \TX_MARGIN_LOW_1
parameter \TX_MARGIN_LOW_2
parameter \TX_MARGIN_LOW_3
parameter \TX_MARGIN_LOW_4
parameter \TX_MODE_SEL
parameter \TX_PHICAL_CFG0
parameter \TX_PHICAL_CFG1
parameter \TX_PHICAL_CFG2
parameter \TX_PI_BIASSET
parameter \TX_PI_CFG0
parameter \TX_PI_CFG1
parameter \TX_PI_DIV2_MODE_B
parameter \TX_PI_SEL_QPLL0
parameter \TX_PI_SEL_QPLL1
parameter \TX_PMADATA_OPT
parameter \TX_PMA_POWER_SAVE
parameter \TX_PREDRV_CTRL
parameter \TX_PROGCLK_SEL
parameter \TX_PROGDIV_CFG
parameter \TX_PROGDIV_RATE
parameter \TX_RXDETECT_CFG
parameter \TX_RXDETECT_REF
parameter \TX_SAMPLE_PERIOD
parameter \TX_SARC_LPBK_ENB
parameter \TX_XCLK_SEL
parameter \USE_PCS_CLK_PHASE_SEL
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:17023"
wire width 3 output 1 \BUFGTCE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:17024"
wire width 3 output 2 \BUFGTCEMASK
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:17025"
wire width 9 output 3 \BUFGTDIV
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:17026"
wire width 3 output 4 \BUFGTRESET
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:17027"
wire width 3 output 5 \BUFGTRSTMASK
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:17118"
wire input 96 \CDRSTEPDIR
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:17119"
wire input 97 \CDRSTEPSQ
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:17120"
wire input 98 \CDRSTEPSX
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:17121"
wire input 99 \CFGRESET
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:17122"
wire input 100 \CLKRSVD0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:17123"
wire input 101 \CLKRSVD1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:17028"
wire output 6 \CPLLFBCLKLOST
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:17029"
wire output 7 \CPLLLOCK
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:17124"
wire input 102 \CPLLLOCKDETCLK
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:17125"
wire input 103 \CPLLLOCKEN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:17126"
wire input 104 \CPLLPD
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:17030"
wire output 8 \CPLLREFCLKLOST
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:17127"
wire width 3 input 105 \CPLLREFCLKSEL
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:17128"
wire input 106 \CPLLRESET
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:17129"
wire input 107 \DMONFIFORESET
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:17130"
wire input 108 \DMONITORCLK
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:17031"
wire width 17 output 9 \DMONITOROUT
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:17131"
wire width 10 input 109 \DRPADDR
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:17132"
wire input 110 \DRPCLK
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:17133"
wire width 16 input 111 \DRPDI
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:17032"
wire width 16 output 10 \DRPDO
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:17134"
wire input 112 \DRPEN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:17033"
wire output 11 \DRPRDY
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:17135"
wire input 113 \DRPWE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:17136"
wire input 114 \ELPCALDVORWREN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:17137"
wire input 115 \ELPCALPAORWREN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:17138"
wire input 116 \EVODDPHICALDONE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:17139"
wire input 117 \EVODDPHICALSTART
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:17140"
wire input 118 \EVODDPHIDRDEN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:17141"
wire input 119 \EVODDPHIDWREN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:17142"
wire input 120 \EVODDPHIXRDEN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:17143"
wire input 121 \EVODDPHIXWREN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:17034"
wire output 12 \EYESCANDATAERROR
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:17144"
wire input 122 \EYESCANMODE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:17145"
wire input 123 \EYESCANRESET
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:17146"
wire input 124 \EYESCANTRIGGER
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:17147"
wire input 125 \GTGREFCLK
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:17148"
wire input 126 \GTNORTHREFCLK0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:17149"
wire input 127 \GTNORTHREFCLK1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:17035"
wire output 13 \GTPOWERGOOD
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:17150"
wire input 128 \GTREFCLK0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:17151"
wire input 129 \GTREFCLK1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:17036"
wire output 14 \GTREFCLKMONITOR
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:17152"
wire input 130 \GTRESETSEL
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:17153"
wire width 16 input 131 \GTRSVD
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:17154"
wire input 132 \GTRXRESET
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:17155"
wire input 133 \GTSOUTHREFCLK0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:17156"
wire input 134 \GTSOUTHREFCLK1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:17157"
wire input 135 \GTTXRESET
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:17158"
wire input 136 \GTYRXN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:17159"
wire input 137 \GTYRXP
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:17037"
wire output 15 \GTYTXN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:17038"
wire output 16 \GTYTXP
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:17160"
wire width 3 input 138 \LOOPBACK
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:17161"
wire width 16 input 139 \LOOPRSVD
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:17162"
wire input 140 \LPBKRXTXSEREN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:17163"
wire input 141 \LPBKTXRXSEREN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:17164"
wire input 142 \PCIEEQRXEQADAPTDONE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:17039"
wire output 17 \PCIERATEGEN3
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:17040"
wire output 18 \PCIERATEIDLE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:17041"
wire width 2 output 19 \PCIERATEQPLLPD
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:17042"
wire width 2 output 20 \PCIERATEQPLLRESET
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:17165"
wire input 143 \PCIERSTIDLE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:17166"
wire input 144 \PCIERSTTXSYNCSTART
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:17043"
wire output 21 \PCIESYNCTXSYNCDONE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:17044"
wire output 22 \PCIEUSERGEN3RDY
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:17045"
wire output 23 \PCIEUSERPHYSTATUSRST
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:17167"
wire input 145 \PCIEUSERRATEDONE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:17046"
wire output 24 \PCIEUSERRATESTART
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:17168"
wire width 16 input 146 \PCSRSVDIN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:17169"
wire width 5 input 147 \PCSRSVDIN2
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:17047"
wire width 16 output 25 \PCSRSVDOUT
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:17048"
wire output 26 \PHYSTATUS
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:17049"
wire width 8 output 27 \PINRSRVDAS
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:17170"
wire width 5 input 148 \PMARSVDIN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:17171"
wire input 149 \QPLL0CLK
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:17172"
wire input 150 \QPLL0REFCLK
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:17173"
wire input 151 \QPLL1CLK
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:17174"
wire input 152 \QPLL1REFCLK
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:17050"
wire output 28 \RESETEXCEPTION
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:17175"
wire input 153 \RESETOVRD
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:17176"
wire input 154 \RSTCLKENTX
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:17177"
wire input 155 \RX8B10BEN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:17178"
wire input 156 \RXBUFRESET
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:17051"
wire width 3 output 29 \RXBUFSTATUS
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:17052"
wire output 30 \RXBYTEISALIGNED
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:17053"
wire output 31 \RXBYTEREALIGN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:17179"
wire input 157 \RXCDRFREQRESET
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:17180"
wire input 158 \RXCDRHOLD
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:17054"
wire output 32 \RXCDRLOCK
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:17181"
wire input 159 \RXCDROVRDEN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:17055"
wire output 33 \RXCDRPHDONE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:17182"
wire input 160 \RXCDRRESET
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:17183"
wire input 161 \RXCDRRESETRSV
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:17056"
wire output 34 \RXCHANBONDSEQ
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:17057"
wire output 35 \RXCHANISALIGNED
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:17058"
wire output 36 \RXCHANREALIGN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:17184"
wire input 162 \RXCHBONDEN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:17185"
wire width 5 input 163 \RXCHBONDI
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:17186"
wire width 3 input 164 \RXCHBONDLEVEL
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:17187"
wire input 165 \RXCHBONDMASTER
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:17059"
wire width 5 output 37 \RXCHBONDO
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:17188"
wire input 166 \RXCHBONDSLAVE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:17060"
wire output 38 \RXCKCALDONE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:17189"
wire input 167 \RXCKCALRESET
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:17061"
wire width 2 output 39 \RXCLKCORCNT
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:17062"
wire output 40 \RXCOMINITDET
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:17063"
wire output 41 \RXCOMMADET
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:17190"
wire input 168 \RXCOMMADETEN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:17064"
wire output 42 \RXCOMSASDET
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:17065"
wire output 43 \RXCOMWAKEDET
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:17066"
wire width 16 output 44 \RXCTRL0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:17067"
wire width 16 output 45 \RXCTRL1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:17068"
wire width 8 output 46 \RXCTRL2
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:17069"
wire width 8 output 47 \RXCTRL3
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:17070"
wire width 128 output 48 \RXDATA
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:17071"
wire width 8 output 49 \RXDATAEXTENDRSVD
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:17072"
wire width 2 output 50 \RXDATAVALID
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:17191"
wire input 169 \RXDCCFORCESTART
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:17192"
wire input 170 \RXDFEAGCHOLD
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:17193"
wire input 171 \RXDFEAGCOVRDEN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:17194"
wire input 172 \RXDFELFHOLD
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:17195"
wire input 173 \RXDFELFOVRDEN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:17196"
wire input 174 \RXDFELPMRESET
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:17197"
wire input 175 \RXDFETAP10HOLD
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:17198"
wire input 176 \RXDFETAP10OVRDEN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:17199"
wire input 177 \RXDFETAP11HOLD
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:17200"
wire input 178 \RXDFETAP11OVRDEN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:17201"
wire input 179 \RXDFETAP12HOLD
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:17202"
wire input 180 \RXDFETAP12OVRDEN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:17203"
wire input 181 \RXDFETAP13HOLD
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:17204"
wire input 182 \RXDFETAP13OVRDEN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:17205"
wire input 183 \RXDFETAP14HOLD
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:17206"
wire input 184 \RXDFETAP14OVRDEN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:17207"
wire input 185 \RXDFETAP15HOLD
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:17208"
wire input 186 \RXDFETAP15OVRDEN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:17209"
wire input 187 \RXDFETAP2HOLD
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:17210"
wire input 188 \RXDFETAP2OVRDEN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:17211"
wire input 189 \RXDFETAP3HOLD
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:17212"
wire input 190 \RXDFETAP3OVRDEN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:17213"
wire input 191 \RXDFETAP4HOLD
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:17214"
wire input 192 \RXDFETAP4OVRDEN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:17215"
wire input 193 \RXDFETAP5HOLD
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:17216"
wire input 194 \RXDFETAP5OVRDEN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:17217"
wire input 195 \RXDFETAP6HOLD
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:17218"
wire input 196 \RXDFETAP6OVRDEN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:17219"
wire input 197 \RXDFETAP7HOLD
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:17220"
wire input 198 \RXDFETAP7OVRDEN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:17221"
wire input 199 \RXDFETAP8HOLD
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:17222"
wire input 200 \RXDFETAP8OVRDEN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:17223"
wire input 201 \RXDFETAP9HOLD
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:17224"
wire input 202 \RXDFETAP9OVRDEN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:17225"
wire input 203 \RXDFEUTHOLD
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:17226"
wire input 204 \RXDFEUTOVRDEN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:17227"
wire input 205 \RXDFEVPHOLD
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:17228"
wire input 206 \RXDFEVPOVRDEN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:17229"
wire input 207 \RXDFEVSEN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:17230"
wire input 208 \RXDFEXYDEN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:17231"
wire input 209 \RXDLYBYPASS
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:17232"
wire input 210 \RXDLYEN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:17233"
wire input 211 \RXDLYOVRDEN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:17234"
wire input 212 \RXDLYSRESET
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:17073"
wire output 51 \RXDLYSRESETDONE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:17074"
wire output 52 \RXELECIDLE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:17235"
wire width 2 input 213 \RXELECIDLEMODE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:17236"
wire input 214 \RXGEARBOXSLIP
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:17075"
wire width 6 output 53 \RXHEADER
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:17076"
wire width 2 output 54 \RXHEADERVALID
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:17237"
wire input 215 \RXLATCLK
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:17238"
wire input 216 \RXLPMEN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:17239"
wire input 217 \RXLPMGCHOLD
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:17240"
wire input 218 \RXLPMGCOVRDEN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:17241"
wire input 219 \RXLPMHFHOLD
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:17242"
wire input 220 \RXLPMHFOVRDEN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:17243"
wire input 221 \RXLPMLFHOLD
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:17244"
wire input 222 \RXLPMLFKLOVRDEN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:17245"
wire input 223 \RXLPMOSHOLD
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:17246"
wire input 224 \RXLPMOSOVRDEN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:17247"
wire input 225 \RXMCOMMAALIGNEN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:17077"
wire width 7 output 55 \RXMONITOROUT
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:17248"
wire width 2 input 226 \RXMONITORSEL
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:17249"
wire input 227 \RXOOBRESET
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:17250"
wire input 228 \RXOSCALRESET
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:17251"
wire input 229 \RXOSHOLD
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:17252"
wire width 4 input 230 \RXOSINTCFG
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:17078"
wire output 56 \RXOSINTDONE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:17253"
wire input 231 \RXOSINTEN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:17254"
wire input 232 \RXOSINTHOLD
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:17255"
wire input 233 \RXOSINTOVRDEN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:17079"
wire output 57 \RXOSINTSTARTED
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:17256"
wire input 234 \RXOSINTSTROBE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:17080"
wire output 58 \RXOSINTSTROBEDONE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:17081"
wire output 59 \RXOSINTSTROBESTARTED
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:17257"
wire input 235 \RXOSINTTESTOVRDEN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:17258"
wire input 236 \RXOSOVRDEN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:17082"
wire output 60 \RXOUTCLK
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:17083"
wire output 61 \RXOUTCLKFABRIC
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:17084"
wire output 62 \RXOUTCLKPCS
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:17259"
wire width 3 input 237 \RXOUTCLKSEL
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:17260"
wire input 238 \RXPCOMMAALIGNEN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:17261"
wire input 239 \RXPCSRESET
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:17262"
wire width 2 input 240 \RXPD
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:17263"
wire input 241 \RXPHALIGN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:17085"
wire output 63 \RXPHALIGNDONE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:17264"
wire input 242 \RXPHALIGNEN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:17086"
wire output 64 \RXPHALIGNERR
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:17265"
wire input 243 \RXPHDLYPD
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:17266"
wire input 244 \RXPHDLYRESET
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:17267"
wire input 245 \RXPHOVRDEN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:17268"
wire width 2 input 246 \RXPLLCLKSEL
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:17269"
wire input 247 \RXPMARESET
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:17087"
wire output 65 \RXPMARESETDONE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:17270"
wire input 248 \RXPOLARITY
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:17271"
wire input 249 \RXPRBSCNTRESET
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:17088"
wire output 66 \RXPRBSERR
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:17089"
wire output 67 \RXPRBSLOCKED
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:17272"
wire width 4 input 250 \RXPRBSSEL
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:17090"
wire output 68 \RXPRGDIVRESETDONE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:17273"
wire input 251 \RXPROGDIVRESET
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:17274"
wire width 3 input 252 \RXRATE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:17091"
wire output 69 \RXRATEDONE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:17275"
wire input 253 \RXRATEMODE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:17092"
wire output 70 \RXRECCLKOUT
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:17093"
wire output 71 \RXRESETDONE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:17276"
wire input 254 \RXSLIDE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:17094"
wire output 72 \RXSLIDERDY
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:17095"
wire output 73 \RXSLIPDONE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:17277"
wire input 255 \RXSLIPOUTCLK
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:17096"
wire output 74 \RXSLIPOUTCLKRDY
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:17278"
wire input 256 \RXSLIPPMA
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:17097"
wire output 75 \RXSLIPPMARDY
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:17098"
wire width 2 output 76 \RXSTARTOFSEQ
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:17099"
wire width 3 output 77 \RXSTATUS
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:17279"
wire input 257 \RXSYNCALLIN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:17100"
wire output 78 \RXSYNCDONE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:17280"
wire input 258 \RXSYNCIN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:17281"
wire input 259 \RXSYNCMODE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:17101"
wire output 79 \RXSYNCOUT
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:17282"
wire width 2 input 260 \RXSYSCLKSEL
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:17283"
wire input 261 \RXUSERRDY
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:17284"
wire input 262 \RXUSRCLK
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:17285"
wire input 263 \RXUSRCLK2
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:17102"
wire output 80 \RXVALID
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:17286"
wire input 264 \SIGVALIDCLK
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:17287"
wire width 20 input 265 \TSTIN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:17288"
wire width 8 input 266 \TX8B10BBYPASS
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:17289"
wire input 267 \TX8B10BEN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:17290"
wire width 3 input 268 \TXBUFDIFFCTRL
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:17103"
wire width 2 output 81 \TXBUFSTATUS
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:17104"
wire output 82 \TXCOMFINISH
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:17291"
wire input 269 \TXCOMINIT
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:17292"
wire input 270 \TXCOMSAS
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:17293"
wire input 271 \TXCOMWAKE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:17294"
wire width 16 input 272 \TXCTRL0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:17295"
wire width 16 input 273 \TXCTRL1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:17296"
wire width 8 input 274 \TXCTRL2
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:17297"
wire width 128 input 275 \TXDATA
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:17298"
wire width 8 input 276 \TXDATAEXTENDRSVD
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:17105"
wire output 83 \TXDCCDONE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:17299"
wire input 277 \TXDCCFORCESTART
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:17300"
wire input 278 \TXDCCRESET
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:17301"
wire input 279 \TXDEEMPH
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:17302"
wire input 280 \TXDETECTRX
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:17303"
wire width 5 input 281 \TXDIFFCTRL
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:17304"
wire input 282 \TXDIFFPD
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:17305"
wire input 283 \TXDLYBYPASS
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:17306"
wire input 284 \TXDLYEN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:17307"
wire input 285 \TXDLYHOLD
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:17308"
wire input 286 \TXDLYOVRDEN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:17309"
wire input 287 \TXDLYSRESET
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:17106"
wire output 84 \TXDLYSRESETDONE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:17310"
wire input 288 \TXDLYUPDOWN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:17311"
wire input 289 \TXELECIDLE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:17312"
wire input 290 \TXELFORCESTART
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:17313"
wire width 6 input 291 \TXHEADER
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:17314"
wire input 292 \TXINHIBIT
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:17315"
wire input 293 \TXLATCLK
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:17316"
wire width 7 input 294 \TXMAINCURSOR
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:17317"
wire width 3 input 295 \TXMARGIN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:17107"
wire output 85 \TXOUTCLK
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:17108"
wire output 86 \TXOUTCLKFABRIC
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:17109"
wire output 87 \TXOUTCLKPCS
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:17318"
wire width 3 input 296 \TXOUTCLKSEL
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:17319"
wire input 297 \TXPCSRESET
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:17320"
wire width 2 input 298 \TXPD
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:17321"
wire input 299 \TXPDELECIDLEMODE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:17322"
wire input 300 \TXPHALIGN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:17110"
wire output 88 \TXPHALIGNDONE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:17323"
wire input 301 \TXPHALIGNEN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:17324"
wire input 302 \TXPHDLYPD
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:17325"
wire input 303 \TXPHDLYRESET
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:17326"
wire input 304 \TXPHDLYTSTCLK
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:17327"
wire input 305 \TXPHINIT
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:17111"
wire output 89 \TXPHINITDONE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:17328"
wire input 306 \TXPHOVRDEN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:17329"
wire input 307 \TXPIPPMEN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:17330"
wire input 308 \TXPIPPMOVRDEN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:17331"
wire input 309 \TXPIPPMPD
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:17332"
wire input 310 \TXPIPPMSEL
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:17333"
wire width 5 input 311 \TXPIPPMSTEPSIZE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:17334"
wire input 312 \TXPISOPD
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:17335"
wire width 2 input 313 \TXPLLCLKSEL
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:17336"
wire input 314 \TXPMARESET
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:17112"
wire output 90 \TXPMARESETDONE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:17337"
wire input 315 \TXPOLARITY
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:17338"
wire width 5 input 316 \TXPOSTCURSOR
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:17339"
wire input 317 \TXPRBSFORCEERR
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:17340"
wire width 4 input 318 \TXPRBSSEL
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:17341"
wire width 5 input 319 \TXPRECURSOR
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:17113"
wire output 91 \TXPRGDIVRESETDONE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:17342"
wire input 320 \TXPROGDIVRESET
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:17343"
wire width 3 input 321 \TXRATE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:17114"
wire output 92 \TXRATEDONE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:17344"
wire input 322 \TXRATEMODE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:17115"
wire output 93 \TXRESETDONE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:17345"
wire width 7 input 323 \TXSEQUENCE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:17346"
wire input 324 \TXSWING
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:17347"
wire input 325 \TXSYNCALLIN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:17116"
wire output 94 \TXSYNCDONE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:17348"
wire input 326 \TXSYNCIN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:17349"
wire input 327 \TXSYNCMODE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:17117"
wire output 95 \TXSYNCOUT
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:17350"
wire width 2 input 328 \TXSYSCLKSEL
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:17351"
wire input 329 \TXUSERRDY
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:17352"
wire input 330 \TXUSRCLK
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:17353"
wire input 331 \TXUSRCLK2
end
attribute \blackbox 1
attribute \cells_not_processed 1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:17356"
module \GTYE3_COMMON
parameter \A_SDM1DATA1_0
parameter \A_SDM1DATA1_1
parameter \BIAS_CFG0
parameter \BIAS_CFG1
parameter \BIAS_CFG2
parameter \BIAS_CFG3
parameter \BIAS_CFG4
parameter \BIAS_CFG_RSVD
parameter \COMMON_CFG0
parameter \COMMON_CFG1
parameter \POR_CFG
parameter \PPF0_CFG
parameter \PPF1_CFG
parameter \QPLL0CLKOUT_RATE
parameter \QPLL0_CFG0
parameter \QPLL0_CFG1
parameter \QPLL0_CFG1_G3
parameter \QPLL0_CFG2
parameter \QPLL0_CFG2_G3
parameter \QPLL0_CFG3
parameter \QPLL0_CFG4
parameter \QPLL0_CP
parameter \QPLL0_CP_G3
parameter \QPLL0_FBDIV
parameter \QPLL0_FBDIV_G3
parameter \QPLL0_INIT_CFG0
parameter \QPLL0_INIT_CFG1
parameter \QPLL0_LOCK_CFG
parameter \QPLL0_LOCK_CFG_G3
parameter \QPLL0_LPF
parameter \QPLL0_LPF_G3
parameter \QPLL0_REFCLK_DIV
parameter \QPLL0_SDM_CFG0
parameter \QPLL0_SDM_CFG1
parameter \QPLL0_SDM_CFG2
parameter \QPLL1CLKOUT_RATE
parameter \QPLL1_CFG0
parameter \QPLL1_CFG1
parameter \QPLL1_CFG1_G3
parameter \QPLL1_CFG2
parameter \QPLL1_CFG2_G3
parameter \QPLL1_CFG3
parameter \QPLL1_CFG4
parameter \QPLL1_CP
parameter \QPLL1_CP_G3
parameter \QPLL1_FBDIV
parameter \QPLL1_FBDIV_G3
parameter \QPLL1_INIT_CFG0
parameter \QPLL1_INIT_CFG1
parameter \QPLL1_LOCK_CFG
parameter \QPLL1_LOCK_CFG_G3
parameter \QPLL1_LPF
parameter \QPLL1_LPF_G3
parameter \QPLL1_REFCLK_DIV
parameter \QPLL1_SDM_CFG0
parameter \QPLL1_SDM_CFG1
parameter \QPLL1_SDM_CFG2
parameter \RSVD_ATTR0
parameter \RSVD_ATTR1
parameter \RSVD_ATTR2
parameter \RSVD_ATTR3
parameter \RXRECCLKOUT0_SEL
parameter \RXRECCLKOUT1_SEL
parameter \SARC_EN
parameter \SARC_SEL
parameter \SDM0INITSEED0_0
parameter \SDM0INITSEED0_1
parameter \SDM1INITSEED0_0
parameter \SDM1INITSEED0_1
parameter \SIM_MODE
parameter \SIM_RESET_SPEEDUP
parameter \SIM_VERSION
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:17453"
wire input 25 \BGBYPASSB
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:17454"
wire input 26 \BGMONITORENB
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:17455"
wire input 27 \BGPDB
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:17456"
wire width 5 input 28 \BGRCALOVRD
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:17457"
wire input 29 \BGRCALOVRDENB
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:17458"
wire width 10 input 30 \DRPADDR
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:17459"
wire input 31 \DRPCLK
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:17460"
wire width 16 input 32 \DRPDI
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:17429"
wire width 16 output 1 \DRPDO
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:17461"
wire input 33 \DRPEN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:17430"
wire output 2 \DRPRDY
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:17462"
wire input 34 \DRPWE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:17463"
wire input 35 \GTGREFCLK0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:17464"
wire input 36 \GTGREFCLK1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:17465"
wire input 37 \GTNORTHREFCLK00
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:17466"
wire input 38 \GTNORTHREFCLK01
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:17467"
wire input 39 \GTNORTHREFCLK10
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:17468"
wire input 40 \GTNORTHREFCLK11
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:17469"
wire input 41 \GTREFCLK00
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:17470"
wire input 42 \GTREFCLK01
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:17471"
wire input 43 \GTREFCLK10
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:17472"
wire input 44 \GTREFCLK11
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:17473"
wire input 45 \GTSOUTHREFCLK00
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:17474"
wire input 46 \GTSOUTHREFCLK01
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:17475"
wire input 47 \GTSOUTHREFCLK10
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:17476"
wire input 48 \GTSOUTHREFCLK11
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:17477"
wire width 8 input 49 \PMARSVD0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:17478"
wire width 8 input 50 \PMARSVD1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:17431"
wire width 8 output 3 \PMARSVDOUT0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:17432"
wire width 8 output 4 \PMARSVDOUT1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:17479"
wire input 51 \QPLL0CLKRSVD0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:17433"
wire output 5 \QPLL0FBCLKLOST
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:17434"
wire output 6 \QPLL0LOCK
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:17480"
wire input 52 \QPLL0LOCKDETCLK
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:17481"
wire input 53 \QPLL0LOCKEN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:17435"
wire output 7 \QPLL0OUTCLK
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:17436"
wire output 8 \QPLL0OUTREFCLK
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:17482"
wire input 54 \QPLL0PD
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:17437"
wire output 9 \QPLL0REFCLKLOST
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:17483"
wire width 3 input 55 \QPLL0REFCLKSEL
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:17484"
wire input 56 \QPLL0RESET
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:17485"
wire input 57 \QPLL1CLKRSVD0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:17438"
wire output 10 \QPLL1FBCLKLOST
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:17439"
wire output 11 \QPLL1LOCK
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:17486"
wire input 58 \QPLL1LOCKDETCLK
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:17487"
wire input 59 \QPLL1LOCKEN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:17440"
wire output 12 \QPLL1OUTCLK
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:17441"
wire output 13 \QPLL1OUTREFCLK
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:17488"
wire input 60 \QPLL1PD
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:17442"
wire output 14 \QPLL1REFCLKLOST
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:17489"
wire width 3 input 61 \QPLL1REFCLKSEL
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:17490"
wire input 62 \QPLL1RESET
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:17443"
wire width 8 output 15 \QPLLDMONITOR0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:17444"
wire width 8 output 16 \QPLLDMONITOR1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:17491"
wire width 8 input 63 \QPLLRSVD1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:17492"
wire width 5 input 64 \QPLLRSVD2
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:17493"
wire width 5 input 65 \QPLLRSVD3
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:17494"
wire width 8 input 66 \QPLLRSVD4
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:17495"
wire input 67 \RCALENB
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:17445"
wire output 17 \REFCLKOUTMONITOR0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:17446"
wire output 18 \REFCLKOUTMONITOR1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:17447"
wire width 2 output 19 \RXRECCLK0_SEL
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:17448"
wire width 2 output 20 \RXRECCLK1_SEL
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:17496"
wire width 25 input 68 \SDM0DATA
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:17449"
wire width 4 output 21 \SDM0FINALOUT
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:17497"
wire input 69 \SDM0RESET
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:17450"
wire width 15 output 22 \SDM0TESTDATA
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:17498"
wire width 2 input 70 \SDM0WIDTH
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:17499"
wire width 25 input 71 \SDM1DATA
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:17451"
wire width 4 output 23 \SDM1FINALOUT
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:17500"
wire input 72 \SDM1RESET
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:17452"
wire width 15 output 24 \SDM1TESTDATA
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:17501"
wire width 2 input 73 \SDM1WIDTH
end
attribute \blackbox 1
attribute \cells_not_processed 1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:17504"
module \GTYE4_CHANNEL
parameter \ACJTAG_DEBUG_MODE
parameter \ACJTAG_MODE
parameter \ACJTAG_RESET
parameter \ADAPT_CFG0
parameter \ADAPT_CFG1
parameter \ADAPT_CFG2
parameter \ALIGN_COMMA_DOUBLE
parameter \ALIGN_COMMA_ENABLE
parameter \ALIGN_COMMA_WORD
parameter \ALIGN_MCOMMA_DET
parameter \ALIGN_MCOMMA_VALUE
parameter \ALIGN_PCOMMA_DET
parameter \ALIGN_PCOMMA_VALUE
parameter \A_RXOSCALRESET
parameter \A_RXPROGDIVRESET
parameter \A_RXTERMINATION
parameter \A_TXDIFFCTRL
parameter \A_TXPROGDIVRESET
parameter \CBCC_DATA_SOURCE_SEL
parameter \CDR_SWAP_MODE_EN
parameter \CFOK_PWRSVE_EN
parameter \CHAN_BOND_KEEP_ALIGN
parameter \CHAN_BOND_MAX_SKEW
parameter \CHAN_BOND_SEQ_1_1
parameter \CHAN_BOND_SEQ_1_2
parameter \CHAN_BOND_SEQ_1_3
parameter \CHAN_BOND_SEQ_1_4
parameter \CHAN_BOND_SEQ_1_ENABLE
parameter \CHAN_BOND_SEQ_2_1
parameter \CHAN_BOND_SEQ_2_2
parameter \CHAN_BOND_SEQ_2_3
parameter \CHAN_BOND_SEQ_2_4
parameter \CHAN_BOND_SEQ_2_ENABLE
parameter \CHAN_BOND_SEQ_2_USE
parameter \CHAN_BOND_SEQ_LEN
parameter \CH_HSPMUX
parameter \CKCAL1_CFG_0
parameter \CKCAL1_CFG_1
parameter \CKCAL1_CFG_2
parameter \CKCAL1_CFG_3
parameter \CKCAL2_CFG_0
parameter \CKCAL2_CFG_1
parameter \CKCAL2_CFG_2
parameter \CKCAL2_CFG_3
parameter \CKCAL2_CFG_4
parameter \CLK_CORRECT_USE
parameter \CLK_COR_KEEP_IDLE
parameter \CLK_COR_MAX_LAT
parameter \CLK_COR_MIN_LAT
parameter \CLK_COR_PRECEDENCE
parameter \CLK_COR_REPEAT_WAIT
parameter \CLK_COR_SEQ_1_1
parameter \CLK_COR_SEQ_1_2
parameter \CLK_COR_SEQ_1_3
parameter \CLK_COR_SEQ_1_4
parameter \CLK_COR_SEQ_1_ENABLE
parameter \CLK_COR_SEQ_2_1
parameter \CLK_COR_SEQ_2_2
parameter \CLK_COR_SEQ_2_3
parameter \CLK_COR_SEQ_2_4
parameter \CLK_COR_SEQ_2_ENABLE
parameter \CLK_COR_SEQ_2_USE
parameter \CLK_COR_SEQ_LEN
parameter \CPLL_CFG0
parameter \CPLL_CFG1
parameter \CPLL_CFG2
parameter \CPLL_CFG3
parameter \CPLL_FBDIV
parameter \CPLL_FBDIV_45
parameter \CPLL_INIT_CFG0
parameter \CPLL_LOCK_CFG
parameter \CPLL_REFCLK_DIV
parameter \CTLE3_OCAP_EXT_CTRL
parameter \CTLE3_OCAP_EXT_EN
parameter \DDI_CTRL
parameter \DDI_REALIGN_WAIT
parameter \DEC_MCOMMA_DETECT
parameter \DEC_PCOMMA_DETECT
parameter \DEC_VALID_COMMA_ONLY
parameter \DELAY_ELEC
parameter \DMONITOR_CFG0
parameter \DMONITOR_CFG1
parameter \ES_CLK_PHASE_SEL
parameter \ES_CONTROL
parameter \ES_ERRDET_EN
parameter \ES_EYE_SCAN_EN
parameter \ES_HORZ_OFFSET
parameter \ES_PRESCALE
parameter \ES_QUALIFIER0
parameter \ES_QUALIFIER1
parameter \ES_QUALIFIER2
parameter \ES_QUALIFIER3
parameter \ES_QUALIFIER4
parameter \ES_QUALIFIER5
parameter \ES_QUALIFIER6
parameter \ES_QUALIFIER7
parameter \ES_QUALIFIER8
parameter \ES_QUALIFIER9
parameter \ES_QUAL_MASK0
parameter \ES_QUAL_MASK1
parameter \ES_QUAL_MASK2
parameter \ES_QUAL_MASK3
parameter \ES_QUAL_MASK4
parameter \ES_QUAL_MASK5
parameter \ES_QUAL_MASK6
parameter \ES_QUAL_MASK7
parameter \ES_QUAL_MASK8
parameter \ES_QUAL_MASK9
parameter \ES_SDATA_MASK0
parameter \ES_SDATA_MASK1
parameter \ES_SDATA_MASK2
parameter \ES_SDATA_MASK3
parameter \ES_SDATA_MASK4
parameter \ES_SDATA_MASK5
parameter \ES_SDATA_MASK6
parameter \ES_SDATA_MASK7
parameter \ES_SDATA_MASK8
parameter \ES_SDATA_MASK9
parameter \EYESCAN_VP_RANGE
parameter \EYE_SCAN_SWAP_EN
parameter \FTS_DESKEW_SEQ_ENABLE
parameter \FTS_LANE_DESKEW_CFG
parameter \FTS_LANE_DESKEW_EN
parameter \GEARBOX_MODE
parameter \ISCAN_CK_PH_SEL2
parameter \LOCAL_MASTER
parameter \LPBK_BIAS_CTRL
parameter \LPBK_EN_RCAL_B
parameter \LPBK_EXT_RCAL
parameter \LPBK_IND_CTRL0
parameter \LPBK_IND_CTRL1
parameter \LPBK_IND_CTRL2
parameter \LPBK_RG_CTRL
parameter \OOBDIVCTL
parameter \OOB_PWRUP
parameter \PCI3_AUTO_REALIGN
parameter \PCI3_PIPE_RX_ELECIDLE
parameter \PCI3_RX_ASYNC_EBUF_BYPASS
parameter \PCI3_RX_ELECIDLE_EI2_ENABLE
parameter \PCI3_RX_ELECIDLE_H2L_COUNT
parameter \PCI3_RX_ELECIDLE_H2L_DISABLE
parameter \PCI3_RX_ELECIDLE_HI_COUNT
parameter \PCI3_RX_ELECIDLE_LP4_DISABLE
parameter \PCI3_RX_FIFO_DISABLE
parameter \PCIE3_CLK_COR_EMPTY_THRSH
parameter \PCIE3_CLK_COR_FULL_THRSH
parameter \PCIE3_CLK_COR_MAX_LAT
parameter \PCIE3_CLK_COR_MIN_LAT
parameter \PCIE3_CLK_COR_THRSH_TIMER
parameter \PCIE_64B_DYN_CLKSW_DIS
parameter \PCIE_BUFG_DIV_CTRL
parameter \PCIE_GEN4_64BIT_INT_EN
parameter \PCIE_PLL_SEL_MODE_GEN12
parameter \PCIE_PLL_SEL_MODE_GEN3
parameter \PCIE_PLL_SEL_MODE_GEN4
parameter \PCIE_RXPCS_CFG_GEN3
parameter \PCIE_RXPMA_CFG
parameter \PCIE_TXPCS_CFG_GEN3
parameter \PCIE_TXPMA_CFG
parameter \PCS_PCIE_EN
parameter \PCS_RSVD0
parameter \PD_TRANS_TIME_FROM_P2
parameter \PD_TRANS_TIME_NONE_P2
parameter \PD_TRANS_TIME_TO_P2
parameter \PREIQ_FREQ_BST
parameter \RATE_SW_USE_DRP
parameter \RCLK_SIPO_DLY_ENB
parameter \RCLK_SIPO_INV_EN
parameter \RTX_BUF_CML_CTRL
parameter \RTX_BUF_TERM_CTRL
parameter \RXBUFRESET_TIME
parameter \RXBUF_ADDR_MODE
parameter \RXBUF_EIDLE_HI_CNT
parameter \RXBUF_EIDLE_LO_CNT
parameter \RXBUF_EN
parameter \RXBUF_RESET_ON_CB_CHANGE
parameter \RXBUF_RESET_ON_COMMAALIGN
parameter \RXBUF_RESET_ON_EIDLE
parameter \RXBUF_RESET_ON_RATE_CHANGE
parameter \RXBUF_THRESH_OVFLW
parameter \RXBUF_THRESH_OVRD
parameter \RXBUF_THRESH_UNDFLW
parameter \RXCDRFREQRESET_TIME
parameter \RXCDRPHRESET_TIME
parameter \RXCDR_CFG0
parameter \RXCDR_CFG0_GEN3
parameter \RXCDR_CFG1
parameter \RXCDR_CFG1_GEN3
parameter \RXCDR_CFG2
parameter \RXCDR_CFG2_GEN2
parameter \RXCDR_CFG2_GEN3
parameter \RXCDR_CFG2_GEN4
parameter \RXCDR_CFG3
parameter \RXCDR_CFG3_GEN2
parameter \RXCDR_CFG3_GEN3
parameter \RXCDR_CFG3_GEN4
parameter \RXCDR_CFG4
parameter \RXCDR_CFG4_GEN3
parameter \RXCDR_CFG5
parameter \RXCDR_CFG5_GEN3
parameter \RXCDR_FR_RESET_ON_EIDLE
parameter \RXCDR_HOLD_DURING_EIDLE
parameter \RXCDR_LOCK_CFG0
parameter \RXCDR_LOCK_CFG1
parameter \RXCDR_LOCK_CFG2
parameter \RXCDR_LOCK_CFG3
parameter \RXCDR_LOCK_CFG4
parameter \RXCDR_PH_RESET_ON_EIDLE
parameter \RXCFOK_CFG0
parameter \RXCFOK_CFG1
parameter \RXCFOK_CFG2
parameter \RXCKCAL1_IQ_LOOP_RST_CFG
parameter \RXCKCAL1_I_LOOP_RST_CFG
parameter \RXCKCAL1_Q_LOOP_RST_CFG
parameter \RXCKCAL2_DX_LOOP_RST_CFG
parameter \RXCKCAL2_D_LOOP_RST_CFG
parameter \RXCKCAL2_S_LOOP_RST_CFG
parameter \RXCKCAL2_X_LOOP_RST_CFG
parameter \RXDFELPMRESET_TIME
parameter \RXDFELPM_KL_CFG0
parameter \RXDFELPM_KL_CFG1
parameter \RXDFELPM_KL_CFG2
parameter \RXDFE_CFG0
parameter \RXDFE_CFG1
parameter \RXDFE_GC_CFG0
parameter \RXDFE_GC_CFG1
parameter \RXDFE_GC_CFG2
parameter \RXDFE_H2_CFG0
parameter \RXDFE_H2_CFG1
parameter \RXDFE_H3_CFG0
parameter \RXDFE_H3_CFG1
parameter \RXDFE_H4_CFG0
parameter \RXDFE_H4_CFG1
parameter \RXDFE_H5_CFG0
parameter \RXDFE_H5_CFG1
parameter \RXDFE_H6_CFG0
parameter \RXDFE_H6_CFG1
parameter \RXDFE_H7_CFG0
parameter \RXDFE_H7_CFG1
parameter \RXDFE_H8_CFG0
parameter \RXDFE_H8_CFG1
parameter \RXDFE_H9_CFG0
parameter \RXDFE_H9_CFG1
parameter \RXDFE_HA_CFG0
parameter \RXDFE_HA_CFG1
parameter \RXDFE_HB_CFG0
parameter \RXDFE_HB_CFG1
parameter \RXDFE_HC_CFG0
parameter \RXDFE_HC_CFG1
parameter \RXDFE_HD_CFG0
parameter \RXDFE_HD_CFG1
parameter \RXDFE_HE_CFG0
parameter \RXDFE_HE_CFG1
parameter \RXDFE_HF_CFG0
parameter \RXDFE_HF_CFG1
parameter \RXDFE_KH_CFG0
parameter \RXDFE_KH_CFG1
parameter \RXDFE_KH_CFG2
parameter \RXDFE_KH_CFG3
parameter \RXDFE_OS_CFG0
parameter \RXDFE_OS_CFG1
parameter \RXDFE_UT_CFG0
parameter \RXDFE_UT_CFG1
parameter \RXDFE_UT_CFG2
parameter \RXDFE_VP_CFG0
parameter \RXDFE_VP_CFG1
parameter \RXDLY_CFG
parameter \RXDLY_LCFG
parameter \RXELECIDLE_CFG
parameter \RXGBOX_FIFO_INIT_RD_ADDR
parameter \RXGEARBOX_EN
parameter \RXISCANRESET_TIME
parameter \RXLPM_CFG
parameter \RXLPM_GC_CFG
parameter \RXLPM_KH_CFG0
parameter \RXLPM_KH_CFG1
parameter \RXLPM_OS_CFG0
parameter \RXLPM_OS_CFG1
parameter \RXOOB_CFG
parameter \RXOOB_CLK_CFG
parameter \RXOSCALRESET_TIME
parameter \RXOUT_DIV
parameter \RXPCSRESET_TIME
parameter \RXPHBEACON_CFG
parameter \RXPHDLY_CFG
parameter \RXPHSAMP_CFG
parameter \RXPHSLIP_CFG
parameter \RXPH_MONITOR_SEL
parameter \RXPI_CFG0
parameter \RXPI_CFG1
parameter \RXPMACLK_SEL
parameter \RXPMARESET_TIME
parameter \RXPRBS_ERR_LOOPBACK
parameter \RXPRBS_LINKACQ_CNT
parameter \RXREFCLKDIV2_SEL
parameter \RXSLIDE_AUTO_WAIT
parameter \RXSLIDE_MODE
parameter \RXSYNC_MULTILANE
parameter \RXSYNC_OVRD
parameter \RXSYNC_SKIP_DA
parameter \RX_AFE_CM_EN
parameter \RX_BIAS_CFG0
parameter \RX_BUFFER_CFG
parameter \RX_CAPFF_SARC_ENB
parameter \RX_CLK25_DIV
parameter \RX_CLKMUX_EN
parameter \RX_CLK_SLIP_OVRD
parameter \RX_CM_BUF_CFG
parameter \RX_CM_BUF_PD
parameter \RX_CM_SEL
parameter \RX_CM_TRIM
parameter \RX_CTLE_PWR_SAVING
parameter \RX_CTLE_RES_CTRL
parameter \RX_DATA_WIDTH
parameter \RX_DDI_SEL
parameter \RX_DEFER_RESET_BUF_EN
parameter \RX_DEGEN_CTRL
parameter \RX_DFELPM_CFG0
parameter \RX_DFELPM_CFG1
parameter \RX_DFELPM_KLKH_AGC_STUP_EN
parameter \RX_DFE_AGC_CFG1
parameter \RX_DFE_KL_LPM_KH_CFG0
parameter \RX_DFE_KL_LPM_KH_CFG1
parameter \RX_DFE_KL_LPM_KL_CFG0
parameter \RX_DFE_KL_LPM_KL_CFG1
parameter \RX_DFE_LPM_HOLD_DURING_EIDLE
parameter \RX_DISPERR_SEQ_MATCH
parameter \RX_DIVRESET_TIME
parameter \RX_EN_CTLE_RCAL_B
parameter \RX_EN_SUM_RCAL_B
parameter \RX_EYESCAN_VS_CODE
parameter \RX_EYESCAN_VS_NEG_DIR
parameter \RX_EYESCAN_VS_RANGE
parameter \RX_EYESCAN_VS_UT_SIGN
parameter \RX_FABINT_USRCLK_FLOP
parameter \RX_I2V_FILTER_EN
parameter \RX_INT_DATAWIDTH
parameter \RX_PMA_POWER_SAVE
parameter \RX_PMA_RSV0
parameter \RX_PROGDIV_CFG
parameter \RX_PROGDIV_RATE
parameter \RX_RESLOAD_CTRL
parameter \RX_RESLOAD_OVRD
parameter \RX_SAMPLE_PERIOD
parameter \RX_SIG_VALID_DLY
parameter \RX_SUM_DEGEN_AVTT_OVERITE
parameter \RX_SUM_DFETAPREP_EN
parameter \RX_SUM_IREF_TUNE
parameter \RX_SUM_PWR_SAVING
parameter \RX_SUM_RES_CTRL
parameter \RX_SUM_VCMTUNE
parameter \RX_SUM_VCM_BIAS_TUNE_EN
parameter \RX_SUM_VCM_OVWR
parameter \RX_SUM_VREF_TUNE
parameter \RX_TUNE_AFE_OS
parameter \RX_VREG_CTRL
parameter \RX_VREG_PDB
parameter \RX_WIDEMODE_CDR
parameter \RX_WIDEMODE_CDR_GEN3
parameter \RX_WIDEMODE_CDR_GEN4
parameter \RX_XCLK_SEL
parameter \RX_XMODE_SEL
parameter \SAMPLE_CLK_PHASE
parameter \SAS_12G_MODE
parameter \SATA_BURST_SEQ_LEN
parameter \SATA_BURST_VAL
parameter \SATA_CPLL_CFG
parameter \SATA_EIDLE_VAL
parameter \SHOW_REALIGN_COMMA
parameter \SIM_DEVICE
parameter \SIM_MODE
parameter \SIM_RECEIVER_DETECT_PASS
parameter \SIM_RESET_SPEEDUP
parameter \SIM_TX_EIDLE_DRIVE_LEVEL
parameter \SRSTMODE
parameter \TAPDLY_SET_TX
parameter \TERM_RCAL_CFG
parameter \TERM_RCAL_OVRD
parameter \TRANS_TIME_RATE
parameter \TST_RSV0
parameter \TST_RSV1
parameter \TXBUF_EN
parameter \TXBUF_RESET_ON_RATE_CHANGE
parameter \TXDLY_CFG
parameter \TXDLY_LCFG
parameter \TXDRV_FREQBAND
parameter \TXFE_CFG0
parameter \TXFE_CFG1
parameter \TXFE_CFG2
parameter \TXFE_CFG3
parameter \TXFIFO_ADDR_CFG
parameter \TXGBOX_FIFO_INIT_RD_ADDR
parameter \TXGEARBOX_EN
parameter \TXOUT_DIV
parameter \TXPCSRESET_TIME
parameter \TXPHDLY_CFG0
parameter \TXPHDLY_CFG1
parameter \TXPH_CFG
parameter \TXPH_CFG2
parameter \TXPH_MONITOR_SEL
parameter \TXPI_CFG0
parameter \TXPI_CFG1
parameter \TXPI_GRAY_SEL
parameter \TXPI_INVSTROBE_SEL
parameter \TXPI_PPM
parameter \TXPI_PPM_CFG
parameter \TXPI_SYNFREQ_PPM
parameter \TXPMARESET_TIME
parameter \TXREFCLKDIV2_SEL
parameter \TXSWBST_BST
parameter \TXSWBST_EN
parameter \TXSWBST_MAG
parameter \TXSYNC_MULTILANE
parameter \TXSYNC_OVRD
parameter \TXSYNC_SKIP_DA
parameter \TX_CLK25_DIV
parameter \TX_CLKMUX_EN
parameter \TX_DATA_WIDTH
parameter \TX_DCC_LOOP_RST_CFG
parameter \TX_DEEMPH0
parameter \TX_DEEMPH1
parameter \TX_DEEMPH2
parameter \TX_DEEMPH3
parameter \TX_DIVRESET_TIME
parameter \TX_DRIVE_MODE
parameter \TX_EIDLE_ASSERT_DELAY
parameter \TX_EIDLE_DEASSERT_DELAY
parameter \TX_FABINT_USRCLK_FLOP
parameter \TX_FIFO_BYP_EN
parameter \TX_IDLE_DATA_ZERO
parameter \TX_INT_DATAWIDTH
parameter \TX_LOOPBACK_DRIVE_HIZ
parameter \TX_MAINCURSOR_SEL
parameter \TX_MARGIN_FULL_0
parameter \TX_MARGIN_FULL_1
parameter \TX_MARGIN_FULL_2
parameter \TX_MARGIN_FULL_3
parameter \TX_MARGIN_FULL_4
parameter \TX_MARGIN_LOW_0
parameter \TX_MARGIN_LOW_1
parameter \TX_MARGIN_LOW_2
parameter \TX_MARGIN_LOW_3
parameter \TX_MARGIN_LOW_4
parameter \TX_PHICAL_CFG0
parameter \TX_PHICAL_CFG1
parameter \TX_PI_BIASSET
parameter \TX_PMADATA_OPT
parameter \TX_PMA_POWER_SAVE
parameter \TX_PMA_RSV0
parameter \TX_PMA_RSV1
parameter \TX_PROGCLK_SEL
parameter \TX_PROGDIV_CFG
parameter \TX_PROGDIV_RATE
parameter \TX_RXDETECT_CFG
parameter \TX_RXDETECT_REF
parameter \TX_SAMPLE_PERIOD
parameter \TX_SW_MEAS
parameter \TX_VREG_CTRL
parameter \TX_VREG_PDB
parameter \TX_VREG_VREFSEL
parameter \TX_XCLK_SEL
parameter \USB_BOTH_BURST_IDLE
parameter \USB_BURSTMAX_U3WAKE
parameter \USB_BURSTMIN_U3WAKE
parameter \USB_CLK_COR_EQ_EN
parameter \USB_EXT_CNTL
parameter \USB_IDLEMAX_POLLING
parameter \USB_IDLEMIN_POLLING
parameter \USB_LFPSPING_BURST
parameter \USB_LFPSPOLLING_BURST
parameter \USB_LFPSPOLLING_IDLE_MS
parameter \USB_LFPSU1EXIT_BURST
parameter \USB_LFPSU2LPEXIT_BURST_MS
parameter \USB_LFPSU3WAKE_BURST_MS
parameter \USB_LFPS_TPERIOD
parameter \USB_LFPS_TPERIOD_ACCURATE
parameter \USB_MODE
parameter \USB_PCIE_ERR_REP_DIS
parameter \USB_PING_SATA_MAX_INIT
parameter \USB_PING_SATA_MIN_INIT
parameter \USB_POLL_SATA_MAX_BURST
parameter \USB_POLL_SATA_MIN_BURST
parameter \USB_RAW_ELEC
parameter \USB_RXIDLE_P0_CTRL
parameter \USB_TXIDLE_TUNE_ENABLE
parameter \USB_U1_SATA_MAX_WAKE
parameter \USB_U1_SATA_MIN_WAKE
parameter \USB_U2_SAS_MAX_COM
parameter \USB_U2_SAS_MIN_COM
parameter \USE_PCS_CLK_PHASE_SEL
parameter \Y_ALL_MODE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:17996"
wire output 1 \BUFGTCE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:17997"
wire width 3 output 2 \BUFGTCEMASK
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:17998"
wire width 9 output 3 \BUFGTDIV
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:17999"
wire output 4 \BUFGTRESET
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18000"
wire width 3 output 5 \BUFGTRSTMASK
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18096"
wire input 101 \CDRSTEPDIR
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18097"
wire input 102 \CDRSTEPSQ
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18098"
wire input 103 \CDRSTEPSX
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18099"
wire input 104 \CFGRESET
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18100"
wire input 105 \CLKRSVD0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18101"
wire input 106 \CLKRSVD1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18001"
wire output 6 \CPLLFBCLKLOST
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18102"
wire input 107 \CPLLFREQLOCK
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18002"
wire output 7 \CPLLLOCK
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18103"
wire input 108 \CPLLLOCKDETCLK
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18104"
wire input 109 \CPLLLOCKEN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18105"
wire input 110 \CPLLPD
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18003"
wire output 8 \CPLLREFCLKLOST
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18106"
wire width 3 input 111 \CPLLREFCLKSEL
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18107"
wire input 112 \CPLLRESET
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18108"
wire input 113 \DMONFIFORESET
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18109"
wire input 114 \DMONITORCLK
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18004"
wire width 16 output 9 \DMONITOROUT
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18005"
wire output 10 \DMONITOROUTCLK
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18110"
wire width 10 input 115 \DRPADDR
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18111"
wire input 116 \DRPCLK
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18112"
wire width 16 input 117 \DRPDI
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18006"
wire width 16 output 11 \DRPDO
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18113"
wire input 118 \DRPEN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18007"
wire output 12 \DRPRDY
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18114"
wire input 119 \DRPRST
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18115"
wire input 120 \DRPWE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18008"
wire output 13 \EYESCANDATAERROR
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18116"
wire input 121 \EYESCANRESET
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18117"
wire input 122 \EYESCANTRIGGER
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18118"
wire input 123 \FREQOS
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18119"
wire input 124 \GTGREFCLK
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18120"
wire input 125 \GTNORTHREFCLK0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18121"
wire input 126 \GTNORTHREFCLK1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18009"
wire output 14 \GTPOWERGOOD
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18122"
wire input 127 \GTREFCLK0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18123"
wire input 128 \GTREFCLK1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18010"
wire output 15 \GTREFCLKMONITOR
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18124"
wire width 16 input 129 \GTRSVD
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18125"
wire input 130 \GTRXRESET
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18126"
wire input 131 \GTRXRESETSEL
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18127"
wire input 132 \GTSOUTHREFCLK0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18128"
wire input 133 \GTSOUTHREFCLK1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18129"
wire input 134 \GTTXRESET
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18130"
wire input 135 \GTTXRESETSEL
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18131"
wire input 136 \GTYRXN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18132"
wire input 137 \GTYRXP
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18011"
wire output 16 \GTYTXN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18012"
wire output 17 \GTYTXP
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18133"
wire input 138 \INCPCTRL
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18134"
wire width 3 input 139 \LOOPBACK
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18135"
wire input 140 \PCIEEQRXEQADAPTDONE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18013"
wire output 18 \PCIERATEGEN3
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18014"
wire output 19 \PCIERATEIDLE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18015"
wire width 2 output 20 \PCIERATEQPLLPD
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18016"
wire width 2 output 21 \PCIERATEQPLLRESET
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18136"
wire input 141 \PCIERSTIDLE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18137"
wire input 142 \PCIERSTTXSYNCSTART
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18017"
wire output 22 \PCIESYNCTXSYNCDONE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18018"
wire output 23 \PCIEUSERGEN3RDY
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18019"
wire output 24 \PCIEUSERPHYSTATUSRST
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18138"
wire input 143 \PCIEUSERRATEDONE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18020"
wire output 25 \PCIEUSERRATESTART
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18139"
wire width 16 input 144 \PCSRSVDIN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18021"
wire width 16 output 26 \PCSRSVDOUT
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18022"
wire output 27 \PHYSTATUS
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18023"
wire width 16 output 28 \PINRSRVDAS
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18024"
wire output 29 \POWERPRESENT
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18140"
wire input 145 \QPLL0CLK
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18141"
wire input 146 \QPLL0FREQLOCK
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18142"
wire input 147 \QPLL0REFCLK
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18143"
wire input 148 \QPLL1CLK
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18144"
wire input 149 \QPLL1FREQLOCK
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18145"
wire input 150 \QPLL1REFCLK
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18025"
wire output 30 \RESETEXCEPTION
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18146"
wire input 151 \RESETOVRD
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18147"
wire input 152 \RX8B10BEN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18148"
wire input 153 \RXAFECFOKEN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18149"
wire input 154 \RXBUFRESET
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18026"
wire width 3 output 31 \RXBUFSTATUS
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18027"
wire output 32 \RXBYTEISALIGNED
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18028"
wire output 33 \RXBYTEREALIGN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18150"
wire input 155 \RXCDRFREQRESET
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18151"
wire input 156 \RXCDRHOLD
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18029"
wire output 34 \RXCDRLOCK
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18152"
wire input 157 \RXCDROVRDEN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18030"
wire output 35 \RXCDRPHDONE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18153"
wire input 158 \RXCDRRESET
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18031"
wire output 36 \RXCHANBONDSEQ
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18032"
wire output 37 \RXCHANISALIGNED
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18033"
wire output 38 \RXCHANREALIGN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18154"
wire input 159 \RXCHBONDEN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18155"
wire width 5 input 160 \RXCHBONDI
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18156"
wire width 3 input 161 \RXCHBONDLEVEL
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18157"
wire input 162 \RXCHBONDMASTER
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18034"
wire width 5 output 39 \RXCHBONDO
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18158"
wire input 163 \RXCHBONDSLAVE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18035"
wire output 40 \RXCKCALDONE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18159"
wire input 164 \RXCKCALRESET
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18160"
wire width 7 input 165 \RXCKCALSTART
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18036"
wire width 2 output 41 \RXCLKCORCNT
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18037"
wire output 42 \RXCOMINITDET
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18038"
wire output 43 \RXCOMMADET
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18161"
wire input 166 \RXCOMMADETEN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18039"
wire output 44 \RXCOMSASDET
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18040"
wire output 45 \RXCOMWAKEDET
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18041"
wire width 16 output 46 \RXCTRL0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18042"
wire width 16 output 47 \RXCTRL1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18043"
wire width 8 output 48 \RXCTRL2
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18044"
wire width 8 output 49 \RXCTRL3
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18045"
wire width 128 output 50 \RXDATA
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18046"
wire width 8 output 51 \RXDATAEXTENDRSVD
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18047"
wire width 2 output 52 \RXDATAVALID
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18162"
wire input 167 \RXDFEAGCHOLD
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18163"
wire input 168 \RXDFEAGCOVRDEN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18164"
wire width 4 input 169 \RXDFECFOKFCNUM
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18165"
wire input 170 \RXDFECFOKFEN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18166"
wire input 171 \RXDFECFOKFPULSE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18167"
wire input 172 \RXDFECFOKHOLD
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18168"
wire input 173 \RXDFECFOKOVREN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18169"
wire input 174 \RXDFEKHHOLD
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18170"
wire input 175 \RXDFEKHOVRDEN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18171"
wire input 176 \RXDFELFHOLD
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18172"
wire input 177 \RXDFELFOVRDEN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18173"
wire input 178 \RXDFELPMRESET
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18174"
wire input 179 \RXDFETAP10HOLD
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18175"
wire input 180 \RXDFETAP10OVRDEN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18176"
wire input 181 \RXDFETAP11HOLD
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18177"
wire input 182 \RXDFETAP11OVRDEN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18178"
wire input 183 \RXDFETAP12HOLD
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18179"
wire input 184 \RXDFETAP12OVRDEN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18180"
wire input 185 \RXDFETAP13HOLD
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18181"
wire input 186 \RXDFETAP13OVRDEN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18182"
wire input 187 \RXDFETAP14HOLD
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18183"
wire input 188 \RXDFETAP14OVRDEN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18184"
wire input 189 \RXDFETAP15HOLD
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18185"
wire input 190 \RXDFETAP15OVRDEN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18186"
wire input 191 \RXDFETAP2HOLD
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18187"
wire input 192 \RXDFETAP2OVRDEN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18188"
wire input 193 \RXDFETAP3HOLD
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18189"
wire input 194 \RXDFETAP3OVRDEN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18190"
wire input 195 \RXDFETAP4HOLD
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18191"
wire input 196 \RXDFETAP4OVRDEN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18192"
wire input 197 \RXDFETAP5HOLD
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18193"
wire input 198 \RXDFETAP5OVRDEN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18194"
wire input 199 \RXDFETAP6HOLD
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18195"
wire input 200 \RXDFETAP6OVRDEN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18196"
wire input 201 \RXDFETAP7HOLD
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18197"
wire input 202 \RXDFETAP7OVRDEN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18198"
wire input 203 \RXDFETAP8HOLD
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18199"
wire input 204 \RXDFETAP8OVRDEN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18200"
wire input 205 \RXDFETAP9HOLD
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18201"
wire input 206 \RXDFETAP9OVRDEN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18202"
wire input 207 \RXDFEUTHOLD
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18203"
wire input 208 \RXDFEUTOVRDEN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18204"
wire input 209 \RXDFEVPHOLD
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18205"
wire input 210 \RXDFEVPOVRDEN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18206"
wire input 211 \RXDFEXYDEN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18207"
wire input 212 \RXDLYBYPASS
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18208"
wire input 213 \RXDLYEN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18209"
wire input 214 \RXDLYOVRDEN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18210"
wire input 215 \RXDLYSRESET
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18048"
wire output 53 \RXDLYSRESETDONE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18049"
wire output 54 \RXELECIDLE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18211"
wire width 2 input 216 \RXELECIDLEMODE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18212"
wire input 217 \RXEQTRAINING
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18213"
wire input 218 \RXGEARBOXSLIP
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18050"
wire width 6 output 55 \RXHEADER
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18051"
wire width 2 output 56 \RXHEADERVALID
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18214"
wire input 219 \RXLATCLK
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18052"
wire output 57 \RXLFPSTRESETDET
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18053"
wire output 58 \RXLFPSU2LPEXITDET
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18054"
wire output 59 \RXLFPSU3WAKEDET
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18215"
wire input 220 \RXLPMEN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18216"
wire input 221 \RXLPMGCHOLD
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18217"
wire input 222 \RXLPMGCOVRDEN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18218"
wire input 223 \RXLPMHFHOLD
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18219"
wire input 224 \RXLPMHFOVRDEN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18220"
wire input 225 \RXLPMLFHOLD
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18221"
wire input 226 \RXLPMLFKLOVRDEN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18222"
wire input 227 \RXLPMOSHOLD
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18223"
wire input 228 \RXLPMOSOVRDEN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18224"
wire input 229 \RXMCOMMAALIGNEN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18055"
wire width 8 output 60 \RXMONITOROUT
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18225"
wire width 2 input 230 \RXMONITORSEL
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18226"
wire input 231 \RXOOBRESET
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18227"
wire input 232 \RXOSCALRESET
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18228"
wire input 233 \RXOSHOLD
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18056"
wire output 61 \RXOSINTDONE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18057"
wire output 62 \RXOSINTSTARTED
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18058"
wire output 63 \RXOSINTSTROBEDONE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18059"
wire output 64 \RXOSINTSTROBESTARTED
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18229"
wire input 234 \RXOSOVRDEN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18060"
wire output 65 \RXOUTCLK
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18061"
wire output 66 \RXOUTCLKFABRIC
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18062"
wire output 67 \RXOUTCLKPCS
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18230"
wire width 3 input 235 \RXOUTCLKSEL
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18231"
wire input 236 \RXPCOMMAALIGNEN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18232"
wire input 237 \RXPCSRESET
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18233"
wire width 2 input 238 \RXPD
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18234"
wire input 239 \RXPHALIGN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18063"
wire output 68 \RXPHALIGNDONE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18235"
wire input 240 \RXPHALIGNEN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18064"
wire output 69 \RXPHALIGNERR
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18236"
wire input 241 \RXPHDLYPD
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18237"
wire input 242 \RXPHDLYRESET
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18238"
wire width 2 input 243 \RXPLLCLKSEL
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18239"
wire input 244 \RXPMARESET
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18065"
wire output 70 \RXPMARESETDONE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18240"
wire input 245 \RXPOLARITY
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18241"
wire input 246 \RXPRBSCNTRESET
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18066"
wire output 71 \RXPRBSERR
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18067"
wire output 72 \RXPRBSLOCKED
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18242"
wire width 4 input 247 \RXPRBSSEL
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18068"
wire output 73 \RXPRGDIVRESETDONE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18243"
wire input 248 \RXPROGDIVRESET
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18244"
wire width 3 input 249 \RXRATE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18069"
wire output 74 \RXRATEDONE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18245"
wire input 250 \RXRATEMODE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18070"
wire output 75 \RXRECCLKOUT
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18071"
wire output 76 \RXRESETDONE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18246"
wire input 251 \RXSLIDE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18072"
wire output 77 \RXSLIDERDY
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18073"
wire output 78 \RXSLIPDONE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18247"
wire input 252 \RXSLIPOUTCLK
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18074"
wire output 79 \RXSLIPOUTCLKRDY
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18248"
wire input 253 \RXSLIPPMA
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18075"
wire output 80 \RXSLIPPMARDY
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18076"
wire width 2 output 81 \RXSTARTOFSEQ
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18077"
wire width 3 output 82 \RXSTATUS
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18249"
wire input 254 \RXSYNCALLIN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18078"
wire output 83 \RXSYNCDONE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18250"
wire input 255 \RXSYNCIN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18251"
wire input 256 \RXSYNCMODE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18079"
wire output 84 \RXSYNCOUT
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18252"
wire width 2 input 257 \RXSYSCLKSEL
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18253"
wire input 258 \RXTERMINATION
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18254"
wire input 259 \RXUSERRDY
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18255"
wire input 260 \RXUSRCLK
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18256"
wire input 261 \RXUSRCLK2
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18080"
wire output 85 \RXVALID
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18257"
wire input 262 \SIGVALIDCLK
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18258"
wire width 20 input 263 \TSTIN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18259"
wire width 8 input 264 \TX8B10BBYPASS
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18260"
wire input 265 \TX8B10BEN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18081"
wire width 2 output 86 \TXBUFSTATUS
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18082"
wire output 87 \TXCOMFINISH
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18261"
wire input 266 \TXCOMINIT
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18262"
wire input 267 \TXCOMSAS
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18263"
wire input 268 \TXCOMWAKE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18264"
wire width 16 input 269 \TXCTRL0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18265"
wire width 16 input 270 \TXCTRL1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18266"
wire width 8 input 271 \TXCTRL2
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18267"
wire width 128 input 272 \TXDATA
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18268"
wire width 8 input 273 \TXDATAEXTENDRSVD
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18083"
wire output 88 \TXDCCDONE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18269"
wire input 274 \TXDCCFORCESTART
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18270"
wire input 275 \TXDCCRESET
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18271"
wire width 2 input 276 \TXDEEMPH
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18272"
wire input 277 \TXDETECTRX
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18273"
wire width 5 input 278 \TXDIFFCTRL
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18274"
wire input 279 \TXDLYBYPASS
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18275"
wire input 280 \TXDLYEN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18276"
wire input 281 \TXDLYHOLD
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18277"
wire input 282 \TXDLYOVRDEN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18278"
wire input 283 \TXDLYSRESET
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18084"
wire output 89 \TXDLYSRESETDONE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18279"
wire input 284 \TXDLYUPDOWN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18280"
wire input 285 \TXELECIDLE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18281"
wire width 6 input 286 \TXHEADER
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18282"
wire input 287 \TXINHIBIT
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18283"
wire input 288 \TXLATCLK
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18284"
wire input 289 \TXLFPSTRESET
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18285"
wire input 290 \TXLFPSU2LPEXIT
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18286"
wire input 291 \TXLFPSU3WAKE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18287"
wire width 7 input 292 \TXMAINCURSOR
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18288"
wire width 3 input 293 \TXMARGIN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18289"
wire input 294 \TXMUXDCDEXHOLD
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18290"
wire input 295 \TXMUXDCDORWREN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18291"
wire input 296 \TXONESZEROS
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18085"
wire output 90 \TXOUTCLK
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18086"
wire output 91 \TXOUTCLKFABRIC
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18087"
wire output 92 \TXOUTCLKPCS
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18292"
wire width 3 input 297 \TXOUTCLKSEL
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18293"
wire input 298 \TXPCSRESET
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18294"
wire width 2 input 299 \TXPD
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18295"
wire input 300 \TXPDELECIDLEMODE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18296"
wire input 301 \TXPHALIGN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18088"
wire output 93 \TXPHALIGNDONE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18297"
wire input 302 \TXPHALIGNEN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18298"
wire input 303 \TXPHDLYPD
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18299"
wire input 304 \TXPHDLYRESET
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18300"
wire input 305 \TXPHDLYTSTCLK
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18301"
wire input 306 \TXPHINIT
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18089"
wire output 94 \TXPHINITDONE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18302"
wire input 307 \TXPHOVRDEN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18303"
wire input 308 \TXPIPPMEN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18304"
wire input 309 \TXPIPPMOVRDEN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18305"
wire input 310 \TXPIPPMPD
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18306"
wire input 311 \TXPIPPMSEL
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18307"
wire width 5 input 312 \TXPIPPMSTEPSIZE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18308"
wire input 313 \TXPISOPD
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18309"
wire width 2 input 314 \TXPLLCLKSEL
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18310"
wire input 315 \TXPMARESET
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18090"
wire output 95 \TXPMARESETDONE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18311"
wire input 316 \TXPOLARITY
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18312"
wire width 5 input 317 \TXPOSTCURSOR
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18313"
wire input 318 \TXPRBSFORCEERR
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18314"
wire width 4 input 319 \TXPRBSSEL
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18315"
wire width 5 input 320 \TXPRECURSOR
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18091"
wire output 96 \TXPRGDIVRESETDONE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18316"
wire input 321 \TXPROGDIVRESET
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18317"
wire width 3 input 322 \TXRATE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18092"
wire output 97 \TXRATEDONE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18318"
wire input 323 \TXRATEMODE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18093"
wire output 98 \TXRESETDONE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18319"
wire width 7 input 324 \TXSEQUENCE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18320"
wire input 325 \TXSWING
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18321"
wire input 326 \TXSYNCALLIN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18094"
wire output 99 \TXSYNCDONE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18322"
wire input 327 \TXSYNCIN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18323"
wire input 328 \TXSYNCMODE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18095"
wire output 100 \TXSYNCOUT
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18324"
wire width 2 input 329 \TXSYSCLKSEL
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18325"
wire input 330 \TXUSERRDY
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18326"
wire input 331 \TXUSRCLK
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18327"
wire input 332 \TXUSRCLK2
end
attribute \blackbox 1
attribute \cells_not_processed 1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18330"
module \GTYE4_COMMON
parameter \AEN_QPLL0_FBDIV
parameter \AEN_QPLL1_FBDIV
parameter \AEN_SDM0TOGGLE
parameter \AEN_SDM1TOGGLE
parameter \A_SDM0TOGGLE
parameter \A_SDM1DATA_HIGH
parameter \A_SDM1DATA_LOW
parameter \A_SDM1TOGGLE
parameter \BIAS_CFG0
parameter \BIAS_CFG1
parameter \BIAS_CFG2
parameter \BIAS_CFG3
parameter \BIAS_CFG4
parameter \BIAS_CFG_RSVD
parameter \COMMON_CFG0
parameter \COMMON_CFG1
parameter \POR_CFG
parameter \PPF0_CFG
parameter \PPF1_CFG
parameter \QPLL0CLKOUT_RATE
parameter \QPLL0_CFG0
parameter \QPLL0_CFG1
parameter \QPLL0_CFG1_G3
parameter \QPLL0_CFG2
parameter \QPLL0_CFG2_G3
parameter \QPLL0_CFG3
parameter \QPLL0_CFG4
parameter \QPLL0_CP
parameter \QPLL0_CP_G3
parameter \QPLL0_FBDIV
parameter \QPLL0_FBDIV_G3
parameter \QPLL0_INIT_CFG0
parameter \QPLL0_INIT_CFG1
parameter \QPLL0_LOCK_CFG
parameter \QPLL0_LOCK_CFG_G3
parameter \QPLL0_LPF
parameter \QPLL0_LPF_G3
parameter \QPLL0_PCI_EN
parameter \QPLL0_RATE_SW_USE_DRP
parameter \QPLL0_REFCLK_DIV
parameter \QPLL0_SDM_CFG0
parameter \QPLL0_SDM_CFG1
parameter \QPLL0_SDM_CFG2
parameter \QPLL1CLKOUT_RATE
parameter \QPLL1_CFG0
parameter \QPLL1_CFG1
parameter \QPLL1_CFG1_G3
parameter \QPLL1_CFG2
parameter \QPLL1_CFG2_G3
parameter \QPLL1_CFG3
parameter \QPLL1_CFG4
parameter \QPLL1_CP
parameter \QPLL1_CP_G3
parameter \QPLL1_FBDIV
parameter \QPLL1_FBDIV_G3
parameter \QPLL1_INIT_CFG0
parameter \QPLL1_INIT_CFG1
parameter \QPLL1_LOCK_CFG
parameter \QPLL1_LOCK_CFG_G3
parameter \QPLL1_LPF
parameter \QPLL1_LPF_G3
parameter \QPLL1_PCI_EN
parameter \QPLL1_RATE_SW_USE_DRP
parameter \QPLL1_REFCLK_DIV
parameter \QPLL1_SDM_CFG0
parameter \QPLL1_SDM_CFG1
parameter \QPLL1_SDM_CFG2
parameter \RSVD_ATTR0
parameter \RSVD_ATTR1
parameter \RSVD_ATTR2
parameter \RSVD_ATTR3
parameter \RXRECCLKOUT0_SEL
parameter \RXRECCLKOUT1_SEL
parameter \SARC_ENB
parameter \SARC_SEL
parameter \SDM0INITSEED0_0
parameter \SDM0INITSEED0_1
parameter \SDM1INITSEED0_0
parameter \SDM1INITSEED0_1
parameter \SIM_DEVICE
parameter \SIM_MODE
parameter \SIM_RESET_SPEEDUP
parameter \UB_CFG0
parameter \UB_CFG1
parameter \UB_CFG2
parameter \UB_CFG3
parameter \UB_CFG4
parameter \UB_CFG5
parameter \UB_CFG6
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18451"
wire input 32 \BGBYPASSB
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18452"
wire input 33 \BGMONITORENB
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18453"
wire input 34 \BGPDB
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18454"
wire width 5 input 35 \BGRCALOVRD
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18455"
wire input 36 \BGRCALOVRDENB
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18456"
wire width 16 input 37 \DRPADDR
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18457"
wire input 38 \DRPCLK
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18458"
wire width 16 input 39 \DRPDI
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18420"
wire width 16 output 1 \DRPDO
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18459"
wire input 40 \DRPEN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18421"
wire output 2 \DRPRDY
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18460"
wire input 41 \DRPWE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18461"
wire input 42 \GTGREFCLK0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18462"
wire input 43 \GTGREFCLK1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18463"
wire input 44 \GTNORTHREFCLK00
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18464"
wire input 45 \GTNORTHREFCLK01
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18465"
wire input 46 \GTNORTHREFCLK10
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18466"
wire input 47 \GTNORTHREFCLK11
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18467"
wire input 48 \GTREFCLK00
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18468"
wire input 49 \GTREFCLK01
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18469"
wire input 50 \GTREFCLK10
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18470"
wire input 51 \GTREFCLK11
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18471"
wire input 52 \GTSOUTHREFCLK00
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18472"
wire input 53 \GTSOUTHREFCLK01
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18473"
wire input 54 \GTSOUTHREFCLK10
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18474"
wire input 55 \GTSOUTHREFCLK11
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18475"
wire width 3 input 56 \PCIERATEQPLL0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18476"
wire width 3 input 57 \PCIERATEQPLL1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18477"
wire width 8 input 58 \PMARSVD0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18478"
wire width 8 input 59 \PMARSVD1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18422"
wire width 8 output 3 \PMARSVDOUT0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18423"
wire width 8 output 4 \PMARSVDOUT1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18479"
wire input 60 \QPLL0CLKRSVD0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18480"
wire input 61 \QPLL0CLKRSVD1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18424"
wire output 5 \QPLL0FBCLKLOST
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18481"
wire width 8 input 62 \QPLL0FBDIV
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18425"
wire output 6 \QPLL0LOCK
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18482"
wire input 63 \QPLL0LOCKDETCLK
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18483"
wire input 64 \QPLL0LOCKEN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18426"
wire output 7 \QPLL0OUTCLK
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18427"
wire output 8 \QPLL0OUTREFCLK
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18484"
wire input 65 \QPLL0PD
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18428"
wire output 9 \QPLL0REFCLKLOST
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18485"
wire width 3 input 66 \QPLL0REFCLKSEL
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18486"
wire input 67 \QPLL0RESET
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18487"
wire input 68 \QPLL1CLKRSVD0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18488"
wire input 69 \QPLL1CLKRSVD1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18429"
wire output 10 \QPLL1FBCLKLOST
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18489"
wire width 8 input 70 \QPLL1FBDIV
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18430"
wire output 11 \QPLL1LOCK
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18490"
wire input 71 \QPLL1LOCKDETCLK
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18491"
wire input 72 \QPLL1LOCKEN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18431"
wire output 12 \QPLL1OUTCLK
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18432"
wire output 13 \QPLL1OUTREFCLK
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18492"
wire input 73 \QPLL1PD
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18433"
wire output 14 \QPLL1REFCLKLOST
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18493"
wire width 3 input 74 \QPLL1REFCLKSEL
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18494"
wire input 75 \QPLL1RESET
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18434"
wire width 8 output 15 \QPLLDMONITOR0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18435"
wire width 8 output 16 \QPLLDMONITOR1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18495"
wire width 8 input 76 \QPLLRSVD1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18496"
wire width 5 input 77 \QPLLRSVD2
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18497"
wire width 5 input 78 \QPLLRSVD3
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18498"
wire width 8 input 79 \QPLLRSVD4
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18499"
wire input 80 \RCALENB
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18436"
wire output 17 \REFCLKOUTMONITOR0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18437"
wire output 18 \REFCLKOUTMONITOR1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18438"
wire width 2 output 19 \RXRECCLK0SEL
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18439"
wire width 2 output 20 \RXRECCLK1SEL
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18500"
wire width 25 input 81 \SDM0DATA
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18440"
wire width 4 output 21 \SDM0FINALOUT
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18501"
wire input 82 \SDM0RESET
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18441"
wire width 15 output 22 \SDM0TESTDATA
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18502"
wire input 83 \SDM0TOGGLE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18503"
wire width 2 input 84 \SDM0WIDTH
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18504"
wire width 25 input 85 \SDM1DATA
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18442"
wire width 4 output 23 \SDM1FINALOUT
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18505"
wire input 86 \SDM1RESET
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18443"
wire width 15 output 24 \SDM1TESTDATA
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18506"
wire input 87 \SDM1TOGGLE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18507"
wire width 2 input 88 \SDM1WIDTH
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18508"
wire input 89 \UBCFGSTREAMEN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18444"
wire width 16 output 25 \UBDADDR
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18445"
wire output 26 \UBDEN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18446"
wire width 16 output 27 \UBDI
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18509"
wire width 16 input 90 \UBDO
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18510"
wire input 91 \UBDRDY
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18447"
wire output 28 \UBDWE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18511"
wire input 92 \UBENABLE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18512"
wire width 2 input 93 \UBGPI
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18513"
wire width 2 input 94 \UBINTR
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18514"
wire input 95 \UBIOLMBRST
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18515"
wire input 96 \UBMBRST
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18516"
wire input 97 \UBMDMCAPTURE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18517"
wire input 98 \UBMDMDBGRST
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18518"
wire input 99 \UBMDMDBGUPDATE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18519"
wire width 4 input 100 \UBMDMREGEN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18520"
wire input 101 \UBMDMSHIFT
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18521"
wire input 102 \UBMDMSYSRST
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18522"
wire input 103 \UBMDMTCK
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18523"
wire input 104 \UBMDMTDI
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18448"
wire output 29 \UBMDMTDO
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18449"
wire output 30 \UBRSVDOUT
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18450"
wire output 31 \UBTXUART
end
attribute \blackbox 1
attribute \cells_not_processed 1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:9167"
module \HARD_SYNC
parameter \INIT
parameter \IS_CLK_INVERTED
parameter \LATENCY
attribute \clkbuf_sink 1
attribute \invertible_pin "IS_CLK_INVERTED"
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:9174"
wire input 2 \CLK
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:9175"
wire input 3 \DIN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:9171"
wire output 1 \DOUT
end
attribute \blackbox 1
attribute \cells_not_processed 1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7652"
module \HPIO_VREF
parameter \VREF_CNTR
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7655"
wire width 7 input 2 \FABRIC_VREF_TUNE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7654"
wire output 1 \VREF
end
attribute \blackbox 1
attribute \cells_not_processed 1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_sim.v:32"
module \IBUF
parameter \IBUF_LOW_PWR
parameter \IOSTANDARD
attribute \iopad_external_pin 1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_sim.v:35"
wire input 2 \I
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_sim.v:33"
wire output 1 \O
end
attribute \blackbox 1
attribute \cells_not_processed 1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7260"
module \IBUFDS
parameter \CAPACITANCE
parameter \DIFF_TERM
parameter \DQS_BIAS
parameter \IBUF_DELAY_VALUE
parameter \IBUF_LOW_PWR
parameter \IFD_DELAY_VALUE
parameter \IOSTANDARD
attribute \iopad_external_pin 1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7270"
wire input 2 \I
attribute \iopad_external_pin 1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7272"
wire input 3 \IB
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7268"
wire output 1 \O
end
attribute \blackbox 1
attribute \cells_not_processed 1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7364"
module \IBUFDSE3
parameter \DIFF_TERM
parameter \DQS_BIAS
parameter \IBUF_LOW_PWR
parameter \IOSTANDARD
parameter \SIM_INPUT_BUFFER_OFFSET
parameter \USE_IBUFDISABLE
attribute \iopad_external_pin 1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7373"
wire input 2 \I
attribute \iopad_external_pin 1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7375"
wire input 3 \IB
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7376"
wire input 4 \IBUFDISABLE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7371"
wire output 1 \O
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7377"
wire width 4 input 5 \OSC
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7378"
wire width 2 input 6 \OSC_EN
end
attribute \blackbox 1
attribute \cells_not_processed 1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7318"
module \IBUFDS_DIFF_OUT
parameter \DIFF_TERM
parameter \DQS_BIAS
parameter \IBUF_LOW_PWR
parameter \IOSTANDARD
attribute \iopad_external_pin 1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7326"
wire input 3 \I
attribute \iopad_external_pin 1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7328"
wire input 4 \IB
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7323"
wire output 1 \O
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7324"
wire output 2 \OB
end
attribute \blackbox 1
attribute \cells_not_processed 1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7331"
module \IBUFDS_DIFF_OUT_IBUFDISABLE
parameter \DIFF_TERM
parameter \DQS_BIAS
parameter \IBUF_LOW_PWR
parameter \IOSTANDARD
parameter \SIM_DEVICE
parameter \USE_IBUFDISABLE
attribute \iopad_external_pin 1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7341"
wire input 3 \I
attribute \iopad_external_pin 1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7343"
wire input 4 \IB
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7344"
wire input 5 \IBUFDISABLE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7338"
wire output 1 \O
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7339"
wire output 2 \OB
end
attribute \blackbox 1
attribute \cells_not_processed 1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7347"
module \IBUFDS_DIFF_OUT_INTERMDISABLE
parameter \DIFF_TERM
parameter \DQS_BIAS
parameter \IBUF_LOW_PWR
parameter \IOSTANDARD
parameter \SIM_DEVICE
parameter \USE_IBUFDISABLE
attribute \iopad_external_pin 1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7357"
wire input 3 \I
attribute \iopad_external_pin 1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7359"
wire input 4 \IB
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7360"
wire input 5 \IBUFDISABLE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7361"
wire input 6 \INTERMDISABLE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7354"
wire output 1 \O
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7355"
wire output 2 \OB
end
attribute \blackbox 1
attribute \cells_not_processed 1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7275"
module \IBUFDS_DLY_ADJ
parameter \DELAY_OFFSET
parameter \DIFF_TERM
parameter \IOSTANDARD
attribute \iopad_external_pin 1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7281"
wire input 2 \I
attribute \iopad_external_pin 1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7283"
wire input 3 \IB
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7279"
wire output 1 \O
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7284"
wire width 3 input 4 \S
end
attribute \blackbox 1
attribute \cells_not_processed 1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7381"
module \IBUFDS_DPHY
parameter \DIFF_TERM
parameter \IOSTANDARD
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7387"
wire input 4 \HSRX_DISABLE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7384"
wire output 1 \HSRX_O
attribute \iopad_external_pin 1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7389"
wire input 5 \I
attribute \iopad_external_pin 1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7391"
wire input 6 \IB
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7392"
wire input 7 \LPRX_DISABLE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7385"
wire output 2 \LPRX_O_N
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7386"
wire output 3 \LPRX_O_P
end
attribute \blackbox 1
attribute \cells_not_processed 1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:14660"
module \IBUFDS_GTE2
parameter \CLKCM_CFG
parameter \CLKRCV_TRST
parameter \CLKSWING_CFG
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:14666"
wire input 3 \CEB
attribute \iopad_external_pin 1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:14668"
wire input 4 \I
attribute \iopad_external_pin 1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:14670"
wire input 5 \IB
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:14664"
wire output 1 \O
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:14665"
wire output 2 \ODIV2
end
attribute \blackbox 1
attribute \cells_not_processed 1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18526"
module \IBUFDS_GTE3
parameter \REFCLK_EN_TX_PATH
parameter \REFCLK_HROW_CK_SEL
parameter \REFCLK_ICNTL_RX
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18532"
wire input 3 \CEB
attribute \iopad_external_pin 1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18534"
wire input 4 \I
attribute \iopad_external_pin 1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18536"
wire input 5 \IB
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18530"
wire output 1 \O
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18531"
wire output 2 \ODIV2
end
attribute \blackbox 1
attribute \cells_not_processed 1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18539"
module \IBUFDS_GTE4
parameter \REFCLK_EN_TX_PATH
parameter \REFCLK_HROW_CK_SEL
parameter \REFCLK_ICNTL_RX
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18545"
wire input 3 \CEB
attribute \iopad_external_pin 1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18547"
wire input 4 \I
attribute \iopad_external_pin 1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18549"
wire input 5 \IB
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18543"
wire output 1 \O
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:18544"
wire output 2 \ODIV2
end
attribute \blackbox 1
attribute \cells_not_processed 1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12942"
module \IBUFDS_GTHE1
attribute \iopad_external_pin 1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12945"
wire input 2 \I
attribute \iopad_external_pin 1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12947"
wire input 3 \IB
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12943"
wire output 1 \O
end
attribute \blackbox 1
attribute \cells_not_processed 1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12929"
module \IBUFDS_GTXE1
parameter \CLKCM_CFG
parameter \CLKRCV_TRST
parameter \REFCLKOUT_DLY
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12935"
wire input 3 \CEB
attribute \iopad_external_pin 1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12937"
wire input 4 \I
attribute \iopad_external_pin 1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12939"
wire input 5 \IB
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12933"
wire output 1 \O
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:12934"
wire output 2 \ODIV2
end
attribute \blackbox 1
attribute \cells_not_processed 1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7287"
module \IBUFDS_IBUFDISABLE
parameter \DIFF_TERM
parameter \DQS_BIAS
parameter \IBUF_LOW_PWR
parameter \IOSTANDARD
parameter \SIM_DEVICE
parameter \USE_IBUFDISABLE
attribute \iopad_external_pin 1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7296"
wire input 2 \I
attribute \iopad_external_pin 1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7298"
wire input 3 \IB
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7299"
wire input 4 \IBUFDISABLE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7294"
wire output 1 \O
end
attribute \blackbox 1
attribute \cells_not_processed 1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7302"
module \IBUFDS_INTERMDISABLE
parameter \DIFF_TERM
parameter \DQS_BIAS
parameter \IBUF_LOW_PWR
parameter \IOSTANDARD
parameter \SIM_DEVICE
parameter \USE_IBUFDISABLE
attribute \iopad_external_pin 1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7311"
wire input 2 \I
attribute \iopad_external_pin 1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7313"
wire input 3 \IB
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7314"
wire input 4 \IBUFDISABLE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7315"
wire input 5 \INTERMDISABLE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7309"
wire output 1 \O
end
attribute \blackbox 1
attribute \cells_not_processed 1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7246"
module \IBUFE3
parameter \IBUF_LOW_PWR
parameter \IOSTANDARD
parameter \SIM_INPUT_BUFFER_OFFSET
parameter \USE_IBUFDISABLE
attribute \iopad_external_pin 1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7253"
wire input 2 \I
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7254"
wire input 3 \IBUFDISABLE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7251"
wire output 1 \O
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7255"
wire width 4 input 4 \OSC
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7256"
wire input 5 \OSC_EN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7257"
wire input 6 \VREF
end
attribute \blackbox 1
attribute \cells_not_processed 1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_sim.v:41"
module \IBUFG
parameter \CAPACITANCE
parameter \IBUF_DELAY_VALUE
parameter \IBUF_LOW_PWR
parameter \IOSTANDARD
attribute \iopad_external_pin 1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_sim.v:44"
wire input 2 \I
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_sim.v:42"
wire output 1 \O
end
attribute \blackbox 1
attribute \cells_not_processed 1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7395"
module \IBUFGDS
parameter \CAPACITANCE
parameter \DIFF_TERM
parameter \IBUF_DELAY_VALUE
parameter \IBUF_LOW_PWR
parameter \IOSTANDARD
attribute \iopad_external_pin 1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7403"
wire input 2 \I
attribute \iopad_external_pin 1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7405"
wire input 3 \IB
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7401"
wire output 1 \O
end
attribute \blackbox 1
attribute \cells_not_processed 1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7408"
module \IBUFGDS_DIFF_OUT
parameter \DIFF_TERM
parameter \DQS_BIAS
parameter \IBUF_LOW_PWR
parameter \IOSTANDARD
attribute \iopad_external_pin 1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7416"
wire input 3 \I
attribute \iopad_external_pin 1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7418"
wire input 4 \IB
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7413"
wire output 1 \O
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7414"
wire output 2 \OB
end
attribute \blackbox 1
attribute \cells_not_processed 1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7240"
module \IBUF_ANALOG
attribute \iopad_external_pin 1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7243"
wire input 2 \I
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7241"
wire output 1 \O
end
attribute \blackbox 1
attribute \cells_not_processed 1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7208"
module \IBUF_DLY_ADJ
parameter \DELAY_OFFSET
parameter \IOSTANDARD
attribute \iopad_external_pin 1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7213"
wire input 2 \I
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7211"
wire output 1 \O
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7214"
wire width 3 input 3 \S
end
attribute \blackbox 1
attribute \cells_not_processed 1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7217"
module \IBUF_IBUFDISABLE
parameter \IBUF_LOW_PWR
parameter \IOSTANDARD
parameter \SIM_DEVICE
parameter \USE_IBUFDISABLE
attribute \iopad_external_pin 1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7224"
wire input 2 \I
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7225"
wire input 3 \IBUFDISABLE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7222"
wire output 1 \O
end
attribute \blackbox 1
attribute \cells_not_processed 1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7228"
module \IBUF_INTERMDISABLE
parameter \IBUF_LOW_PWR
parameter \IOSTANDARD
parameter \SIM_DEVICE
parameter \USE_IBUFDISABLE
attribute \iopad_external_pin 1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7235"
wire input 2 \I
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7236"
wire input 3 \IBUFDISABLE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7237"
wire input 4 \INTERMDISABLE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7233"
wire output 1 \O
end
attribute \blackbox 1
attribute \keep 1
attribute \cells_not_processed 1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:9401"
module \ICAPE2
parameter \DEVICE_ID
parameter \ICAP_WIDTH
parameter \SIM_CFG_FILE_NAME
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:9406"
wire input 2 \CLK
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:9407"
wire input 3 \CSIB
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:9409"
wire width 32 input 5 \I
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:9405"
wire width 32 output 1 \O
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:9408"
wire input 4 \RDWRB
end
attribute \blackbox 1
attribute \keep 1
attribute \cells_not_processed 1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:9413"
module \ICAPE3
parameter \DEVICE_ID
parameter \ICAP_AUTO_SWITCH
parameter \SIM_CFG_FILE_NAME
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:9417"
wire output 1 \AVAIL
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:9421"
wire input 5 \CLK
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:9422"
wire input 6 \CSIB
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:9424"
wire width 32 input 8 \I
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:9418"
wire width 32 output 2 \O
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:9419"
wire output 3 \PRDONE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:9420"
wire output 4 \PRERROR
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:9423"
wire input 7 \RDWRB
end
attribute \blackbox 1
attribute \keep 1
attribute \cells_not_processed 1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:9344"
module \ICAP_SPARTAN3A
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:9345"
wire output 1 \BUSY
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:9347"
wire input 3 \CE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:9348"
wire input 4 \CLK
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:9350"
wire width 8 input 6 \I
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:9346"
wire width 8 output 2 \O
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:9349"
wire input 5 \WRITE
end
attribute \blackbox 1
attribute \keep 1
attribute \cells_not_processed 1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:9354"
module \ICAP_SPARTAN6
parameter \DEVICE_ID
parameter \SIM_CFG_FILE_NAME
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:9357"
wire output 1 \BUSY
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:9360"
wire input 4 \CE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:9359"
wire input 3 \CLK
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:9362"
wire width 16 input 6 \I
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:9358"
wire width 16 output 2 \O
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:9361"
wire input 5 \WRITE
end
attribute \blackbox 1
attribute \keep 1
attribute \cells_not_processed 1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:9366"
module \ICAP_VIRTEX4
parameter \ICAP_WIDTH
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:9368"
wire output 1 \BUSY
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:9370"
wire input 3 \CE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:9371"
wire input 4 \CLK
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:9373"
wire width 32 input 6 \I
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:9369"
wire width 32 output 2 \O
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:9372"
wire input 5 \WRITE
end
attribute \blackbox 1
attribute \keep 1
attribute \cells_not_processed 1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:9377"
module \ICAP_VIRTEX5
parameter \ICAP_WIDTH
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:9379"
wire output 1 \BUSY
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:9381"
wire input 3 \CE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:9382"
wire input 4 \CLK
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:9384"
wire width 32 input 6 \I
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:9380"
wire width 32 output 2 \O
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:9383"
wire input 5 \WRITE
end
attribute \blackbox 1
attribute \keep 1
attribute \cells_not_processed 1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:9388"
module \ICAP_VIRTEX6
parameter \DEVICE_ID
parameter \ICAP_WIDTH
parameter \SIM_CFG_FILE_NAME
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:9392"
wire output 1 \BUSY
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:9394"
wire input 3 \CLK
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:9395"
wire input 4 \CSB
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:9397"
wire width 32 input 6 \I
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:9393"
wire width 32 output 2 \O
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:9396"
wire input 5 \RDWRB
end
attribute \blackbox 1
attribute \cells_not_processed 1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:5828"
module \IDDR
parameter \DDR_CLK_EDGE
parameter \INIT_Q1
parameter \INIT_Q2
parameter \IS_C_INVERTED
parameter \IS_D_INVERTED
parameter \MSGON
parameter \SRTYPE
parameter \XON
attribute \clkbuf_sink 1
attribute \invertible_pin "IS_C_INVERTED"
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:5841"
wire input 3 \C
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:5842"
wire input 4 \CE
attribute \invertible_pin "IS_D_INVERTED"
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:5844"
wire input 5 \D
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:5837"
wire output 1 \Q1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:5838"
wire output 2 \Q2
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:5845"
wire input 6 \R
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:5846"
wire input 7 \S
end
attribute \blackbox 1
attribute \cells_not_processed 1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:5795"
module \IDDR2
parameter \DDR_ALIGNMENT
parameter \INIT_Q0
parameter \INIT_Q1
parameter \SRTYPE
attribute \clkbuf_sink 1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:5803"
wire input 3 \C0
attribute \clkbuf_sink 1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:5805"
wire input 4 \C1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:5806"
wire input 5 \CE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:5807"
wire input 6 \D
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:5800"
wire output 1 \Q0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:5801"
wire output 2 \Q1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:5808"
wire input 7 \R
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:5809"
wire input 8 \S
end
attribute \blackbox 1
attribute \cells_not_processed 1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:6612"
module \IDDRE1
parameter \DDR_CLK_EDGE
parameter \IS_CB_INVERTED
parameter \IS_C_INVERTED
attribute \clkbuf_sink 1
attribute \invertible_pin "IS_C_INVERTED"
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:6620"
wire input 3 \C
attribute \clkbuf_sink 1
attribute \invertible_pin "IS_CB_INVERTED"
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:6623"
wire input 4 \CB
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:6624"
wire input 5 \D
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:6616"
wire output 1 \Q1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:6617"
wire output 2 \Q2
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:6625"
wire input 6 \R
end
attribute \blackbox 1
attribute \cells_not_processed 1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:5849"
module \IDDR_2CLK
parameter \DDR_CLK_EDGE
parameter \INIT_Q1
parameter \INIT_Q2
parameter \IS_CB_INVERTED
parameter \IS_C_INVERTED
parameter \IS_D_INVERTED
parameter \SRTYPE
attribute \clkbuf_sink 1
attribute \invertible_pin "IS_C_INVERTED"
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:5861"
wire input 3 \C
attribute \clkbuf_sink 1
attribute \invertible_pin "IS_CB_INVERTED"
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:5864"
wire input 4 \CB
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:5865"
wire input 5 \CE
attribute \invertible_pin "IS_D_INVERTED"
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:5867"
wire input 6 \D
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:5857"
wire output 1 \Q1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:5858"
wire output 2 \Q2
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:5868"
wire input 7 \R
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:5869"
wire input 8 \S
end
attribute \blackbox 1
attribute \cells_not_processed 1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:5903"
module \IDELAY
parameter \IOBDELAY_TYPE
parameter \IOBDELAY_VALUE
attribute \clkbuf_sink 1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:5908"
wire input 2 \C
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:5909"
wire input 3 \CE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:5910"
wire input 4 \I
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:5911"
wire input 5 \INC
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:5906"
wire output 1 \O
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:5912"
wire input 6 \RST
end
attribute \blackbox 1
attribute \keep 1
attribute \cells_not_processed 1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:5895"
module \IDELAYCTRL
parameter \SIM_DEVICE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:5897"
wire output 1 \RDY
attribute \clkbuf_sink 1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:5899"
wire input 2 \REFCLK
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:5900"
wire input 3 \RST
end
attribute \blackbox 1
attribute \cells_not_processed 1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:6175"
module \IDELAYE2
parameter \CINVCTRL_SEL
parameter \DELAY_SRC
parameter \HIGH_PERFORMANCE_MODE
parameter \IDELAY_TYPE
parameter \IDELAY_VALUE
parameter \IS_C_INVERTED
parameter \IS_DATAIN_INVERTED
parameter \IS_IDATAIN_INVERTED
parameter \PIPE_SEL
parameter \REFCLK_FREQUENCY
parameter \SIGNAL_PATTERN
parameter \SIM_DELAY_D
attribute \clkbuf_sink 1
attribute \invertible_pin "IS_C_INVERTED"
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:6192"
wire input 3 \C
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:6193"
wire input 4 \CE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:6194"
wire input 5 \CINVCTRL
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:6195"
wire width 5 input 6 \CNTVALUEIN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:6188"
wire width 5 output 1 \CNTVALUEOUT
attribute \invertible_pin "IS_DATAIN_INVERTED"
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:6197"
wire input 7 \DATAIN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:6189"
wire output 2 \DATAOUT
attribute \invertible_pin "IS_IDATAIN_INVERTED"
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:6199"
wire input 8 \IDATAIN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:6200"
wire input 9 \INC
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:6201"
wire input 10 \LD
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:6202"
wire input 11 \LDPIPEEN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:6203"
wire input 12 \REGRST
end
attribute \blackbox 1
attribute \cells_not_processed 1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:6644"
module \IDELAYE3
parameter \CASCADE
parameter \DELAY_FORMAT
parameter \DELAY_SRC
parameter \DELAY_TYPE
parameter \DELAY_VALUE
parameter \IS_CLK_INVERTED
parameter \IS_RST_INVERTED
parameter \LOOPBACK
parameter \REFCLK_FREQUENCY
parameter \SIM_DEVICE
parameter \SIM_VERSION
parameter \UPDATE_MODE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:6660"
wire input 4 \CASC_IN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:6657"
wire output 1 \CASC_OUT
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:6661"
wire input 5 \CASC_RETURN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:6662"
wire input 6 \CE
attribute \clkbuf_sink 1
attribute \invertible_pin "IS_CLK_INVERTED"
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:6665"
wire input 7 \CLK
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:6666"
wire width 9 input 8 \CNTVALUEIN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:6658"
wire width 9 output 2 \CNTVALUEOUT
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:6667"
wire input 9 \DATAIN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:6659"
wire output 3 \DATAOUT
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:6668"
wire input 10 \EN_VTC
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:6669"
wire input 11 \IDATAIN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:6670"
wire input 12 \INC
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:6671"
wire input 13 \LOAD
attribute \invertible_pin "IS_RST_INVERTED"
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:6673"
wire input 14 \RST
end
attribute \blackbox 1
attribute \cells_not_processed 1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:5709"
module \IFDDRCPE
attribute \clkbuf_sink 1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:5713"
wire input 3 \C0
attribute \clkbuf_sink 1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:5715"
wire input 4 \C1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:5716"
wire input 5 \CE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:5717"
wire input 6 \CLR
attribute \iopad_external_pin 1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:5719"
wire input 7 \D
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:5720"
wire input 8 \PRE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:5710"
wire output 1 \Q0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:5711"
wire output 2 \Q1
end
attribute \blackbox 1
attribute \cells_not_processed 1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:5723"
module \IFDDRRSE
attribute \clkbuf_sink 1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:5727"
wire input 3 \C0
attribute \clkbuf_sink 1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:5729"
wire input 4 \C1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:5730"
wire input 5 \CE
attribute \iopad_external_pin 1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:5732"
wire input 6 \D
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:5724"
wire output 1 \Q0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:5725"
wire output 2 \Q1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:5733"
wire input 7 \R
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:5734"
wire input 8 \S
end
attribute \blackbox 1
attribute \cells_not_processed 1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:27970"
module \ILKN
parameter \BYPASS
parameter \CTL_RX_BURSTMAX
parameter \CTL_RX_CHAN_EXT
parameter \CTL_RX_LAST_LANE
parameter \CTL_RX_MFRAMELEN_MINUS1
parameter \CTL_RX_PACKET_MODE
parameter \CTL_RX_RETRANS_MULT
parameter \CTL_RX_RETRANS_RETRY
parameter \CTL_RX_RETRANS_TIMER1
parameter \CTL_RX_RETRANS_TIMER2
parameter \CTL_RX_RETRANS_WDOG
parameter \CTL_RX_RETRANS_WRAP_TIMER
parameter \CTL_TEST_MODE_PIN_CHAR
parameter \CTL_TX_BURSTMAX
parameter \CTL_TX_BURSTSHORT
parameter \CTL_TX_CHAN_EXT
parameter \CTL_TX_DISABLE_SKIPWORD
parameter \CTL_TX_FC_CALLEN
parameter \CTL_TX_LAST_LANE
parameter \CTL_TX_MFRAMELEN_MINUS1
parameter \CTL_TX_RETRANS_DEPTH
parameter \CTL_TX_RETRANS_MULT
parameter \CTL_TX_RETRANS_RAM_BANKS
parameter \MODE
parameter \SIM_VERSION
parameter \TEST_MODE_PIN_CHAR
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28115"
wire input 119 \CORE_CLK
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28116"
wire input 120 \CTL_RX_FORCE_RESYNC
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28117"
wire input 121 \CTL_RX_RETRANS_ACK
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28118"
wire input 122 \CTL_RX_RETRANS_ENABLE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28119"
wire input 123 \CTL_RX_RETRANS_ERRIN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28120"
wire input 124 \CTL_RX_RETRANS_FORCE_REQ
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28121"
wire input 125 \CTL_RX_RETRANS_RESET
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28122"
wire input 126 \CTL_RX_RETRANS_RESET_MODE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28123"
wire input 127 \CTL_TX_DIAGWORD_INTFSTAT
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28124"
wire width 12 input 128 \CTL_TX_DIAGWORD_LANESTAT
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28125"
wire input 129 \CTL_TX_ENABLE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28126"
wire input 130 \CTL_TX_ERRINJ_BITERR_GO
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28127"
wire width 4 input 131 \CTL_TX_ERRINJ_BITERR_LANE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28128"
wire width 256 input 132 \CTL_TX_FC_STAT
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28129"
wire width 8 input 133 \CTL_TX_MUBITS
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28130"
wire input 134 \CTL_TX_RETRANS_ENABLE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28131"
wire input 135 \CTL_TX_RETRANS_RAM_PERRIN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28132"
wire width 644 input 136 \CTL_TX_RETRANS_RAM_RDATA
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28133"
wire input 137 \CTL_TX_RETRANS_REQ
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28134"
wire input 138 \CTL_TX_RETRANS_REQ_VALID
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28135"
wire width 12 input 139 \CTL_TX_RLIM_DELTA
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28136"
wire input 140 \CTL_TX_RLIM_ENABLE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28137"
wire width 8 input 141 \CTL_TX_RLIM_INTV
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28138"
wire width 12 input 142 \CTL_TX_RLIM_MAX
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28139"
wire width 10 input 143 \DRP_ADDR
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28140"
wire input 144 \DRP_CLK
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28141"
wire width 16 input 145 \DRP_DI
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:27997"
wire width 16 output 1 \DRP_DO
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28142"
wire input 146 \DRP_EN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:27998"
wire output 2 \DRP_RDY
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28143"
wire input 147 \DRP_WE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28144"
wire input 148 \LBUS_CLK
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:27999"
wire width 66 output 3 \RX_BYPASS_DATAOUT00
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28000"
wire width 66 output 4 \RX_BYPASS_DATAOUT01
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28001"
wire width 66 output 5 \RX_BYPASS_DATAOUT02
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28002"
wire width 66 output 6 \RX_BYPASS_DATAOUT03
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28003"
wire width 66 output 7 \RX_BYPASS_DATAOUT04
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28004"
wire width 66 output 8 \RX_BYPASS_DATAOUT05
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28005"
wire width 66 output 9 \RX_BYPASS_DATAOUT06
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28006"
wire width 66 output 10 \RX_BYPASS_DATAOUT07
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28007"
wire width 66 output 11 \RX_BYPASS_DATAOUT08
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28008"
wire width 66 output 12 \RX_BYPASS_DATAOUT09
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28009"
wire width 66 output 13 \RX_BYPASS_DATAOUT10
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28010"
wire width 66 output 14 \RX_BYPASS_DATAOUT11
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28011"
wire width 12 output 15 \RX_BYPASS_ENAOUT
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28145"
wire input 149 \RX_BYPASS_FORCE_REALIGNIN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28012"
wire width 12 output 16 \RX_BYPASS_IS_AVAILOUT
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28013"
wire width 12 output 17 \RX_BYPASS_IS_BADLYFRAMEDOUT
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28014"
wire width 12 output 18 \RX_BYPASS_IS_OVERFLOWOUT
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28015"
wire width 12 output 19 \RX_BYPASS_IS_SYNCEDOUT
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28016"
wire width 12 output 20 \RX_BYPASS_IS_SYNCWORDOUT
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28146"
wire input 150 \RX_BYPASS_RDIN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28017"
wire width 11 output 21 \RX_CHANOUT0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28018"
wire width 11 output 22 \RX_CHANOUT1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28019"
wire width 11 output 23 \RX_CHANOUT2
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28020"
wire width 11 output 24 \RX_CHANOUT3
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28021"
wire width 128 output 25 \RX_DATAOUT0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28022"
wire width 128 output 26 \RX_DATAOUT1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28023"
wire width 128 output 27 \RX_DATAOUT2
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28024"
wire width 128 output 28 \RX_DATAOUT3
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28025"
wire output 29 \RX_ENAOUT0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28026"
wire output 30 \RX_ENAOUT1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28027"
wire output 31 \RX_ENAOUT2
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28028"
wire output 32 \RX_ENAOUT3
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28029"
wire output 33 \RX_EOPOUT0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28030"
wire output 34 \RX_EOPOUT1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28031"
wire output 35 \RX_EOPOUT2
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28032"
wire output 36 \RX_EOPOUT3
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28033"
wire output 37 \RX_ERROUT0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28034"
wire output 38 \RX_ERROUT1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28035"
wire output 39 \RX_ERROUT2
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28036"
wire output 40 \RX_ERROUT3
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28037"
wire width 4 output 41 \RX_MTYOUT0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28038"
wire width 4 output 42 \RX_MTYOUT1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28039"
wire width 4 output 43 \RX_MTYOUT2
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28040"
wire width 4 output 44 \RX_MTYOUT3
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28041"
wire output 45 \RX_OVFOUT
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28147"
wire input 151 \RX_RESET
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28148"
wire width 12 input 152 \RX_SERDES_CLK
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28149"
wire width 64 input 153 \RX_SERDES_DATA00
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28150"
wire width 64 input 154 \RX_SERDES_DATA01
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28151"
wire width 64 input 155 \RX_SERDES_DATA02
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28152"
wire width 64 input 156 \RX_SERDES_DATA03
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28153"
wire width 64 input 157 \RX_SERDES_DATA04
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28154"
wire width 64 input 158 \RX_SERDES_DATA05
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28155"
wire width 64 input 159 \RX_SERDES_DATA06
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28156"
wire width 64 input 160 \RX_SERDES_DATA07
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28157"
wire width 64 input 161 \RX_SERDES_DATA08
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28158"
wire width 64 input 162 \RX_SERDES_DATA09
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28159"
wire width 64 input 163 \RX_SERDES_DATA10
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28160"
wire width 64 input 164 \RX_SERDES_DATA11
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28161"
wire width 12 input 165 \RX_SERDES_RESET
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28042"
wire output 46 \RX_SOPOUT0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28043"
wire output 47 \RX_SOPOUT1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28044"
wire output 48 \RX_SOPOUT2
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28045"
wire output 49 \RX_SOPOUT3
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28046"
wire output 50 \STAT_RX_ALIGNED
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28047"
wire output 51 \STAT_RX_ALIGNED_ERR
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28048"
wire width 12 output 52 \STAT_RX_BAD_TYPE_ERR
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28049"
wire output 53 \STAT_RX_BURSTMAX_ERR
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28050"
wire output 54 \STAT_RX_BURST_ERR
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28051"
wire output 55 \STAT_RX_CRC24_ERR
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28052"
wire width 12 output 56 \STAT_RX_CRC32_ERR
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28053"
wire width 12 output 57 \STAT_RX_CRC32_VALID
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28054"
wire width 12 output 58 \STAT_RX_DESCRAM_ERR
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28055"
wire width 12 output 59 \STAT_RX_DIAGWORD_INTFSTAT
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28056"
wire width 12 output 60 \STAT_RX_DIAGWORD_LANESTAT
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28057"
wire width 256 output 61 \STAT_RX_FC_STAT
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28058"
wire width 12 output 62 \STAT_RX_FRAMING_ERR
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28059"
wire output 63 \STAT_RX_MEOP_ERR
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28060"
wire width 12 output 64 \STAT_RX_MF_ERR
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28061"
wire width 12 output 65 \STAT_RX_MF_LEN_ERR
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28062"
wire width 12 output 66 \STAT_RX_MF_REPEAT_ERR
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28063"
wire output 67 \STAT_RX_MISALIGNED
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28064"
wire output 68 \STAT_RX_MSOP_ERR
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28065"
wire width 8 output 69 \STAT_RX_MUBITS
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28066"
wire output 70 \STAT_RX_MUBITS_UPDATED
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28067"
wire output 71 \STAT_RX_OVERFLOW_ERR
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28068"
wire output 72 \STAT_RX_RETRANS_CRC24_ERR
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28069"
wire output 73 \STAT_RX_RETRANS_DISC
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28070"
wire width 16 output 74 \STAT_RX_RETRANS_LATENCY
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28071"
wire output 75 \STAT_RX_RETRANS_REQ
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28072"
wire output 76 \STAT_RX_RETRANS_RETRY_ERR
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28073"
wire width 8 output 77 \STAT_RX_RETRANS_SEQ
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28074"
wire output 78 \STAT_RX_RETRANS_SEQ_UPDATED
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28075"
wire width 3 output 79 \STAT_RX_RETRANS_STATE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28076"
wire width 5 output 80 \STAT_RX_RETRANS_SUBSEQ
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28077"
wire output 81 \STAT_RX_RETRANS_WDOG_ERR
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28078"
wire output 82 \STAT_RX_RETRANS_WRAP_ERR
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28079"
wire width 12 output 83 \STAT_RX_SYNCED
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28080"
wire width 12 output 84 \STAT_RX_SYNCED_ERR
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28081"
wire width 12 output 85 \STAT_RX_WORD_SYNC
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28082"
wire output 86 \STAT_TX_BURST_ERR
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28083"
wire output 87 \STAT_TX_ERRINJ_BITERR_DONE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28084"
wire output 88 \STAT_TX_OVERFLOW_ERR
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28085"
wire output 89 \STAT_TX_RETRANS_BURST_ERR
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28086"
wire output 90 \STAT_TX_RETRANS_BUSY
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28087"
wire output 91 \STAT_TX_RETRANS_RAM_PERROUT
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28088"
wire width 9 output 92 \STAT_TX_RETRANS_RAM_RADDR
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28089"
wire output 93 \STAT_TX_RETRANS_RAM_RD_B0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28090"
wire output 94 \STAT_TX_RETRANS_RAM_RD_B1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28091"
wire output 95 \STAT_TX_RETRANS_RAM_RD_B2
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28092"
wire output 96 \STAT_TX_RETRANS_RAM_RD_B3
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28093"
wire width 2 output 97 \STAT_TX_RETRANS_RAM_RSEL
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28094"
wire width 9 output 98 \STAT_TX_RETRANS_RAM_WADDR
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28095"
wire width 644 output 99 \STAT_TX_RETRANS_RAM_WDATA
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28096"
wire output 100 \STAT_TX_RETRANS_RAM_WE_B0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28097"
wire output 101 \STAT_TX_RETRANS_RAM_WE_B1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28098"
wire output 102 \STAT_TX_RETRANS_RAM_WE_B2
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28099"
wire output 103 \STAT_TX_RETRANS_RAM_WE_B3
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28100"
wire output 104 \STAT_TX_UNDERFLOW_ERR
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28162"
wire input 166 \TX_BCTLIN0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28163"
wire input 167 \TX_BCTLIN1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28164"
wire input 168 \TX_BCTLIN2
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28165"
wire input 169 \TX_BCTLIN3
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28166"
wire width 12 input 170 \TX_BYPASS_CTRLIN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28167"
wire width 64 input 171 \TX_BYPASS_DATAIN00
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28168"
wire width 64 input 172 \TX_BYPASS_DATAIN01
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28169"
wire width 64 input 173 \TX_BYPASS_DATAIN02
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28170"
wire width 64 input 174 \TX_BYPASS_DATAIN03
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28171"
wire width 64 input 175 \TX_BYPASS_DATAIN04
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28172"
wire width 64 input 176 \TX_BYPASS_DATAIN05
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28173"
wire width 64 input 177 \TX_BYPASS_DATAIN06
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28174"
wire width 64 input 178 \TX_BYPASS_DATAIN07
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28175"
wire width 64 input 179 \TX_BYPASS_DATAIN08
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28176"
wire width 64 input 180 \TX_BYPASS_DATAIN09
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28177"
wire width 64 input 181 \TX_BYPASS_DATAIN10
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28178"
wire width 64 input 182 \TX_BYPASS_DATAIN11
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28179"
wire input 183 \TX_BYPASS_ENAIN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28180"
wire width 8 input 184 \TX_BYPASS_GEARBOX_SEQIN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28181"
wire width 4 input 185 \TX_BYPASS_MFRAMER_STATEIN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28182"
wire width 11 input 186 \TX_CHANIN0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28183"
wire width 11 input 187 \TX_CHANIN1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28184"
wire width 11 input 188 \TX_CHANIN2
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28185"
wire width 11 input 189 \TX_CHANIN3
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28186"
wire width 128 input 190 \TX_DATAIN0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28187"
wire width 128 input 191 \TX_DATAIN1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28188"
wire width 128 input 192 \TX_DATAIN2
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28189"
wire width 128 input 193 \TX_DATAIN3
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28190"
wire input 194 \TX_ENAIN0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28191"
wire input 195 \TX_ENAIN1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28192"
wire input 196 \TX_ENAIN2
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28193"
wire input 197 \TX_ENAIN3
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28194"
wire input 198 \TX_EOPIN0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28195"
wire input 199 \TX_EOPIN1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28196"
wire input 200 \TX_EOPIN2
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28197"
wire input 201 \TX_EOPIN3
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28198"
wire input 202 \TX_ERRIN0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28199"
wire input 203 \TX_ERRIN1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28200"
wire input 204 \TX_ERRIN2
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28201"
wire input 205 \TX_ERRIN3
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28202"
wire width 4 input 206 \TX_MTYIN0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28203"
wire width 4 input 207 \TX_MTYIN1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28204"
wire width 4 input 208 \TX_MTYIN2
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28205"
wire width 4 input 209 \TX_MTYIN3
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28101"
wire output 105 \TX_OVFOUT
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28102"
wire output 106 \TX_RDYOUT
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28206"
wire input 210 \TX_RESET
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28103"
wire width 64 output 107 \TX_SERDES_DATA00
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28104"
wire width 64 output 108 \TX_SERDES_DATA01
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28105"
wire width 64 output 109 \TX_SERDES_DATA02
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28106"
wire width 64 output 110 \TX_SERDES_DATA03
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28107"
wire width 64 output 111 \TX_SERDES_DATA04
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28108"
wire width 64 output 112 \TX_SERDES_DATA05
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28109"
wire width 64 output 113 \TX_SERDES_DATA06
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28110"
wire width 64 output 114 \TX_SERDES_DATA07
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28111"
wire width 64 output 115 \TX_SERDES_DATA08
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28112"
wire width 64 output 116 \TX_SERDES_DATA09
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28113"
wire width 64 output 117 \TX_SERDES_DATA10
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28114"
wire width 64 output 118 \TX_SERDES_DATA11
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28207"
wire input 211 \TX_SERDES_REFCLK
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28208"
wire input 212 \TX_SERDES_REFCLK_RESET
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28209"
wire input 213 \TX_SOPIN0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28210"
wire input 214 \TX_SOPIN1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28211"
wire input 215 \TX_SOPIN2
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28212"
wire input 216 \TX_SOPIN3
end
attribute \blackbox 1
attribute \cells_not_processed 1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28215"
module \ILKNE4
parameter \BYPASS
parameter \CTL_RX_BURSTMAX
parameter \CTL_RX_CHAN_EXT
parameter \CTL_RX_LAST_LANE
parameter \CTL_RX_MFRAMELEN_MINUS1
parameter \CTL_RX_PACKET_MODE
parameter \CTL_RX_RETRANS_MULT
parameter \CTL_RX_RETRANS_RETRY
parameter \CTL_RX_RETRANS_TIMER1
parameter \CTL_RX_RETRANS_TIMER2
parameter \CTL_RX_RETRANS_WDOG
parameter \CTL_RX_RETRANS_WRAP_TIMER
parameter \CTL_TEST_MODE_PIN_CHAR
parameter \CTL_TX_BURSTMAX
parameter \CTL_TX_BURSTSHORT
parameter \CTL_TX_CHAN_EXT
parameter \CTL_TX_DISABLE_SKIPWORD
parameter \CTL_TX_FC_CALLEN
parameter \CTL_TX_LAST_LANE
parameter \CTL_TX_MFRAMELEN_MINUS1
parameter \CTL_TX_RETRANS_DEPTH
parameter \CTL_TX_RETRANS_MULT
parameter \CTL_TX_RETRANS_RAM_BANKS
parameter \MODE
parameter \SIM_DEVICE
parameter \TEST_MODE_PIN_CHAR
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28360"
wire input 119 \CORE_CLK
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28361"
wire input 120 \CTL_RX_FORCE_RESYNC
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28362"
wire input 121 \CTL_RX_RETRANS_ACK
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28363"
wire input 122 \CTL_RX_RETRANS_ENABLE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28364"
wire input 123 \CTL_RX_RETRANS_ERRIN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28365"
wire input 124 \CTL_RX_RETRANS_FORCE_REQ
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28366"
wire input 125 \CTL_RX_RETRANS_RESET
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28367"
wire input 126 \CTL_RX_RETRANS_RESET_MODE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28368"
wire input 127 \CTL_TX_DIAGWORD_INTFSTAT
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28369"
wire width 12 input 128 \CTL_TX_DIAGWORD_LANESTAT
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28370"
wire input 129 \CTL_TX_ENABLE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28371"
wire input 130 \CTL_TX_ERRINJ_BITERR_GO
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28372"
wire width 4 input 131 \CTL_TX_ERRINJ_BITERR_LANE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28373"
wire width 256 input 132 \CTL_TX_FC_STAT
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28374"
wire width 8 input 133 \CTL_TX_MUBITS
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28375"
wire input 134 \CTL_TX_RETRANS_ENABLE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28376"
wire input 135 \CTL_TX_RETRANS_RAM_PERRIN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28377"
wire width 644 input 136 \CTL_TX_RETRANS_RAM_RDATA
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28378"
wire input 137 \CTL_TX_RETRANS_REQ
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28379"
wire input 138 \CTL_TX_RETRANS_REQ_VALID
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28380"
wire width 12 input 139 \CTL_TX_RLIM_DELTA
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28381"
wire input 140 \CTL_TX_RLIM_ENABLE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28382"
wire width 8 input 141 \CTL_TX_RLIM_INTV
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28383"
wire width 12 input 142 \CTL_TX_RLIM_MAX
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28384"
wire width 10 input 143 \DRP_ADDR
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28385"
wire input 144 \DRP_CLK
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28386"
wire width 16 input 145 \DRP_DI
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28242"
wire width 16 output 1 \DRP_DO
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28387"
wire input 146 \DRP_EN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28243"
wire output 2 \DRP_RDY
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28388"
wire input 147 \DRP_WE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28389"
wire input 148 \LBUS_CLK
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28244"
wire width 66 output 3 \RX_BYPASS_DATAOUT00
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28245"
wire width 66 output 4 \RX_BYPASS_DATAOUT01
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28246"
wire width 66 output 5 \RX_BYPASS_DATAOUT02
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28247"
wire width 66 output 6 \RX_BYPASS_DATAOUT03
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28248"
wire width 66 output 7 \RX_BYPASS_DATAOUT04
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28249"
wire width 66 output 8 \RX_BYPASS_DATAOUT05
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28250"
wire width 66 output 9 \RX_BYPASS_DATAOUT06
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28251"
wire width 66 output 10 \RX_BYPASS_DATAOUT07
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28252"
wire width 66 output 11 \RX_BYPASS_DATAOUT08
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28253"
wire width 66 output 12 \RX_BYPASS_DATAOUT09
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28254"
wire width 66 output 13 \RX_BYPASS_DATAOUT10
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28255"
wire width 66 output 14 \RX_BYPASS_DATAOUT11
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28256"
wire width 12 output 15 \RX_BYPASS_ENAOUT
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28390"
wire input 149 \RX_BYPASS_FORCE_REALIGNIN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28257"
wire width 12 output 16 \RX_BYPASS_IS_AVAILOUT
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28258"
wire width 12 output 17 \RX_BYPASS_IS_BADLYFRAMEDOUT
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28259"
wire width 12 output 18 \RX_BYPASS_IS_OVERFLOWOUT
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28260"
wire width 12 output 19 \RX_BYPASS_IS_SYNCEDOUT
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28261"
wire width 12 output 20 \RX_BYPASS_IS_SYNCWORDOUT
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28391"
wire input 150 \RX_BYPASS_RDIN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28262"
wire width 11 output 21 \RX_CHANOUT0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28263"
wire width 11 output 22 \RX_CHANOUT1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28264"
wire width 11 output 23 \RX_CHANOUT2
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28265"
wire width 11 output 24 \RX_CHANOUT3
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28266"
wire width 128 output 25 \RX_DATAOUT0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28267"
wire width 128 output 26 \RX_DATAOUT1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28268"
wire width 128 output 27 \RX_DATAOUT2
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28269"
wire width 128 output 28 \RX_DATAOUT3
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28270"
wire output 29 \RX_ENAOUT0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28271"
wire output 30 \RX_ENAOUT1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28272"
wire output 31 \RX_ENAOUT2
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28273"
wire output 32 \RX_ENAOUT3
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28274"
wire output 33 \RX_EOPOUT0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28275"
wire output 34 \RX_EOPOUT1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28276"
wire output 35 \RX_EOPOUT2
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28277"
wire output 36 \RX_EOPOUT3
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28278"
wire output 37 \RX_ERROUT0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28279"
wire output 38 \RX_ERROUT1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28280"
wire output 39 \RX_ERROUT2
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28281"
wire output 40 \RX_ERROUT3
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28282"
wire width 4 output 41 \RX_MTYOUT0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28283"
wire width 4 output 42 \RX_MTYOUT1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28284"
wire width 4 output 43 \RX_MTYOUT2
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28285"
wire width 4 output 44 \RX_MTYOUT3
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28286"
wire output 45 \RX_OVFOUT
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28392"
wire input 151 \RX_RESET
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28393"
wire width 12 input 152 \RX_SERDES_CLK
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28394"
wire width 64 input 153 \RX_SERDES_DATA00
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28395"
wire width 64 input 154 \RX_SERDES_DATA01
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28396"
wire width 64 input 155 \RX_SERDES_DATA02
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28397"
wire width 64 input 156 \RX_SERDES_DATA03
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28398"
wire width 64 input 157 \RX_SERDES_DATA04
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28399"
wire width 64 input 158 \RX_SERDES_DATA05
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28400"
wire width 64 input 159 \RX_SERDES_DATA06
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28401"
wire width 64 input 160 \RX_SERDES_DATA07
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28402"
wire width 64 input 161 \RX_SERDES_DATA08
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28403"
wire width 64 input 162 \RX_SERDES_DATA09
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28404"
wire width 64 input 163 \RX_SERDES_DATA10
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28405"
wire width 64 input 164 \RX_SERDES_DATA11
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28406"
wire width 12 input 165 \RX_SERDES_RESET
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28287"
wire output 46 \RX_SOPOUT0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28288"
wire output 47 \RX_SOPOUT1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28289"
wire output 48 \RX_SOPOUT2
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28290"
wire output 49 \RX_SOPOUT3
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28291"
wire output 50 \STAT_RX_ALIGNED
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28292"
wire output 51 \STAT_RX_ALIGNED_ERR
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28293"
wire width 12 output 52 \STAT_RX_BAD_TYPE_ERR
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28294"
wire output 53 \STAT_RX_BURSTMAX_ERR
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28295"
wire output 54 \STAT_RX_BURST_ERR
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28296"
wire output 55 \STAT_RX_CRC24_ERR
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28297"
wire width 12 output 56 \STAT_RX_CRC32_ERR
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28298"
wire width 12 output 57 \STAT_RX_CRC32_VALID
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28299"
wire width 12 output 58 \STAT_RX_DESCRAM_ERR
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28300"
wire width 12 output 59 \STAT_RX_DIAGWORD_INTFSTAT
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28301"
wire width 12 output 60 \STAT_RX_DIAGWORD_LANESTAT
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28302"
wire width 256 output 61 \STAT_RX_FC_STAT
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28303"
wire width 12 output 62 \STAT_RX_FRAMING_ERR
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28304"
wire output 63 \STAT_RX_MEOP_ERR
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28305"
wire width 12 output 64 \STAT_RX_MF_ERR
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28306"
wire width 12 output 65 \STAT_RX_MF_LEN_ERR
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28307"
wire width 12 output 66 \STAT_RX_MF_REPEAT_ERR
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28308"
wire output 67 \STAT_RX_MISALIGNED
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28309"
wire output 68 \STAT_RX_MSOP_ERR
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28310"
wire width 8 output 69 \STAT_RX_MUBITS
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28311"
wire output 70 \STAT_RX_MUBITS_UPDATED
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28312"
wire output 71 \STAT_RX_OVERFLOW_ERR
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28313"
wire output 72 \STAT_RX_RETRANS_CRC24_ERR
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28314"
wire output 73 \STAT_RX_RETRANS_DISC
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28315"
wire width 16 output 74 \STAT_RX_RETRANS_LATENCY
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28316"
wire output 75 \STAT_RX_RETRANS_REQ
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28317"
wire output 76 \STAT_RX_RETRANS_RETRY_ERR
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28318"
wire width 8 output 77 \STAT_RX_RETRANS_SEQ
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28319"
wire output 78 \STAT_RX_RETRANS_SEQ_UPDATED
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28320"
wire width 3 output 79 \STAT_RX_RETRANS_STATE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28321"
wire width 5 output 80 \STAT_RX_RETRANS_SUBSEQ
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28322"
wire output 81 \STAT_RX_RETRANS_WDOG_ERR
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28323"
wire output 82 \STAT_RX_RETRANS_WRAP_ERR
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28324"
wire width 12 output 83 \STAT_RX_SYNCED
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28325"
wire width 12 output 84 \STAT_RX_SYNCED_ERR
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28326"
wire width 12 output 85 \STAT_RX_WORD_SYNC
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28327"
wire output 86 \STAT_TX_BURST_ERR
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28328"
wire output 87 \STAT_TX_ERRINJ_BITERR_DONE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28329"
wire output 88 \STAT_TX_OVERFLOW_ERR
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28330"
wire output 89 \STAT_TX_RETRANS_BURST_ERR
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28331"
wire output 90 \STAT_TX_RETRANS_BUSY
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28332"
wire output 91 \STAT_TX_RETRANS_RAM_PERROUT
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28333"
wire width 9 output 92 \STAT_TX_RETRANS_RAM_RADDR
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28334"
wire output 93 \STAT_TX_RETRANS_RAM_RD_B0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28335"
wire output 94 \STAT_TX_RETRANS_RAM_RD_B1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28336"
wire output 95 \STAT_TX_RETRANS_RAM_RD_B2
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28337"
wire output 96 \STAT_TX_RETRANS_RAM_RD_B3
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28338"
wire width 2 output 97 \STAT_TX_RETRANS_RAM_RSEL
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28339"
wire width 9 output 98 \STAT_TX_RETRANS_RAM_WADDR
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28340"
wire width 644 output 99 \STAT_TX_RETRANS_RAM_WDATA
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28341"
wire output 100 \STAT_TX_RETRANS_RAM_WE_B0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28342"
wire output 101 \STAT_TX_RETRANS_RAM_WE_B1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28343"
wire output 102 \STAT_TX_RETRANS_RAM_WE_B2
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28344"
wire output 103 \STAT_TX_RETRANS_RAM_WE_B3
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28345"
wire output 104 \STAT_TX_UNDERFLOW_ERR
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28407"
wire input 166 \TX_BCTLIN0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28408"
wire input 167 \TX_BCTLIN1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28409"
wire input 168 \TX_BCTLIN2
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28410"
wire input 169 \TX_BCTLIN3
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28411"
wire width 12 input 170 \TX_BYPASS_CTRLIN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28412"
wire width 64 input 171 \TX_BYPASS_DATAIN00
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28413"
wire width 64 input 172 \TX_BYPASS_DATAIN01
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28414"
wire width 64 input 173 \TX_BYPASS_DATAIN02
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28415"
wire width 64 input 174 \TX_BYPASS_DATAIN03
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28416"
wire width 64 input 175 \TX_BYPASS_DATAIN04
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28417"
wire width 64 input 176 \TX_BYPASS_DATAIN05
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28418"
wire width 64 input 177 \TX_BYPASS_DATAIN06
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28419"
wire width 64 input 178 \TX_BYPASS_DATAIN07
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28420"
wire width 64 input 179 \TX_BYPASS_DATAIN08
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28421"
wire width 64 input 180 \TX_BYPASS_DATAIN09
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28422"
wire width 64 input 181 \TX_BYPASS_DATAIN10
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28423"
wire width 64 input 182 \TX_BYPASS_DATAIN11
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28424"
wire input 183 \TX_BYPASS_ENAIN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28425"
wire width 8 input 184 \TX_BYPASS_GEARBOX_SEQIN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28426"
wire width 4 input 185 \TX_BYPASS_MFRAMER_STATEIN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28427"
wire width 11 input 186 \TX_CHANIN0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28428"
wire width 11 input 187 \TX_CHANIN1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28429"
wire width 11 input 188 \TX_CHANIN2
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28430"
wire width 11 input 189 \TX_CHANIN3
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28431"
wire width 128 input 190 \TX_DATAIN0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28432"
wire width 128 input 191 \TX_DATAIN1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28433"
wire width 128 input 192 \TX_DATAIN2
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28434"
wire width 128 input 193 \TX_DATAIN3
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28435"
wire input 194 \TX_ENAIN0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28436"
wire input 195 \TX_ENAIN1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28437"
wire input 196 \TX_ENAIN2
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28438"
wire input 197 \TX_ENAIN3
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28439"
wire input 198 \TX_EOPIN0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28440"
wire input 199 \TX_EOPIN1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28441"
wire input 200 \TX_EOPIN2
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28442"
wire input 201 \TX_EOPIN3
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28443"
wire input 202 \TX_ERRIN0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28444"
wire input 203 \TX_ERRIN1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28445"
wire input 204 \TX_ERRIN2
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28446"
wire input 205 \TX_ERRIN3
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28447"
wire width 4 input 206 \TX_MTYIN0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28448"
wire width 4 input 207 \TX_MTYIN1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28449"
wire width 4 input 208 \TX_MTYIN2
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28450"
wire width 4 input 209 \TX_MTYIN3
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28346"
wire output 105 \TX_OVFOUT
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28347"
wire output 106 \TX_RDYOUT
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28451"
wire input 210 \TX_RESET
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28348"
wire width 64 output 107 \TX_SERDES_DATA00
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28349"
wire width 64 output 108 \TX_SERDES_DATA01
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28350"
wire width 64 output 109 \TX_SERDES_DATA02
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28351"
wire width 64 output 110 \TX_SERDES_DATA03
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28352"
wire width 64 output 111 \TX_SERDES_DATA04
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28353"
wire width 64 output 112 \TX_SERDES_DATA05
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28354"
wire width 64 output 113 \TX_SERDES_DATA06
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28355"
wire width 64 output 114 \TX_SERDES_DATA07
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28356"
wire width 64 output 115 \TX_SERDES_DATA08
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28357"
wire width 64 output 116 \TX_SERDES_DATA09
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28358"
wire width 64 output 117 \TX_SERDES_DATA10
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28359"
wire width 64 output 118 \TX_SERDES_DATA11
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28452"
wire input 211 \TX_SERDES_REFCLK
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28453"
wire input 212 \TX_SERDES_REFCLK_RESET
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28454"
wire input 213 \TX_SOPIN0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28455"
wire input 214 \TX_SOPIN1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28456"
wire input 215 \TX_SOPIN2
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:28457"
wire input 216 \TX_SOPIN3
end
attribute \blackbox 1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_sim.v:157"
module \INV
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_sim.v:160"
wire input 2 \I
attribute \clkbuf_inv "I"
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_sim.v:159"
wire output 1 \O
end
attribute \blackbox 1
attribute \cells_not_processed 1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:9090"
module \IN_FIFO
parameter \ALMOST_EMPTY_VALUE
parameter \ALMOST_FULL_VALUE
parameter \ARRAY_MODE
parameter \SYNCHRONOUS_MODE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:9095"
wire output 1 \ALMOSTEMPTY
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:9096"
wire output 2 \ALMOSTFULL
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:9116"
wire width 4 input 20 \D0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:9117"
wire width 4 input 21 \D1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:9118"
wire width 4 input 22 \D2
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:9119"
wire width 4 input 23 \D3
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:9120"
wire width 4 input 24 \D4
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:9124"
wire width 8 input 28 \D5
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:9125"
wire width 8 input 29 \D6
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:9121"
wire width 4 input 25 \D7
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:9122"
wire width 4 input 26 \D8
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:9123"
wire width 4 input 27 \D9
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:9097"
wire output 3 \EMPTY
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:9098"
wire output 4 \FULL
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:9099"
wire width 8 output 5 \Q0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:9100"
wire width 8 output 6 \Q1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:9101"
wire width 8 output 7 \Q2
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:9102"
wire width 8 output 8 \Q3
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:9103"
wire width 8 output 9 \Q4
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:9104"
wire width 8 output 10 \Q5
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:9105"
wire width 8 output 11 \Q6
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:9106"
wire width 8 output 12 \Q7
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:9107"
wire width 8 output 13 \Q8
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:9108"
wire width 8 output 14 \Q9
attribute \clkbuf_sink 1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:9110"
wire input 15 \RDCLK
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:9111"
wire input 16 \RDEN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:9112"
wire input 17 \RESET
attribute \clkbuf_sink 1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:9114"
wire input 18 \WRCLK
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:9115"
wire input 19 \WREN
end
attribute \blackbox 1
attribute \cells_not_processed 1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_sim.v:62"
module \IOBUF
parameter \DRIVE
parameter \IBUF_LOW_PWR
parameter \IOSTANDARD
parameter \SLEW
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_sim.v:66"
wire input 3 \I
attribute \iopad_external_pin 1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_sim.v:64"
wire inout 1 \IO
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_sim.v:65"
wire output 2 \O
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_sim.v:67"
wire input 4 \T
end
attribute \blackbox 1
attribute \cells_not_processed 1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7471"
module \IOBUFDS
parameter \DIFF_TERM
parameter \DQS_BIAS
parameter \IBUF_LOW_PWR
parameter \IOSTANDARD
parameter \SLEW
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7481"
wire input 4 \I
attribute \iopad_external_pin 1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7479"
wire inout 2 \IO
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7480"
wire inout 3 \IOB
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7477"
wire output 1 \O
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7482"
wire input 5 \T
end
attribute \blackbox 1
attribute \cells_not_processed 1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7579"
module \IOBUFDSE3
parameter \DIFF_TERM
parameter \DQS_BIAS
parameter \IBUF_LOW_PWR
parameter \IOSTANDARD
parameter \SIM_INPUT_BUFFER_OFFSET
parameter \USE_IBUFDISABLE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7590"
wire input 4 \DCITERMDISABLE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7591"
wire input 5 \I
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7592"
wire input 6 \IBUFDISABLE
attribute \iopad_external_pin 1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7588"
wire inout 2 \IO
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7589"
wire inout 3 \IOB
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7586"
wire output 1 \O
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7593"
wire width 4 input 7 \OSC
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7594"
wire width 2 input 8 \OSC_EN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7595"
wire input 9 \T
end
attribute \blackbox 1
attribute \cells_not_processed 1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7485"
module \IOBUFDS_DCIEN
parameter \DIFF_TERM
parameter \DQS_BIAS
parameter \IBUF_LOW_PWR
parameter \IOSTANDARD
parameter \SIM_DEVICE
parameter \SLEW
parameter \USE_IBUFDISABLE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7498"
wire input 4 \DCITERMDISABLE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7499"
wire input 5 \I
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7500"
wire input 6 \IBUFDISABLE
attribute \iopad_external_pin 1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7495"
wire inout 2 \IO
attribute \iopad_external_pin 1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7497"
wire inout 3 \IOB
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7493"
wire output 1 \O
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7501"
wire input 7 \T
end
attribute \blackbox 1
attribute \cells_not_processed 1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7523"
module \IOBUFDS_DIFF_OUT
parameter \DIFF_TERM
parameter \DQS_BIAS
parameter \IBUF_LOW_PWR
parameter \IOSTANDARD
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7534"
wire input 5 \I
attribute \iopad_external_pin 1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7531"
wire inout 3 \IO
attribute \iopad_external_pin 1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7533"
wire inout 4 \IOB
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7528"
wire output 1 \O
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7529"
wire output 2 \OB
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7535"
wire input 6 \TM
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7536"
wire input 7 \TS
end
attribute \blackbox 1
attribute \cells_not_processed 1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7539"
module \IOBUFDS_DIFF_OUT_DCIEN
parameter \DIFF_TERM
parameter \DQS_BIAS
parameter \IBUF_LOW_PWR
parameter \IOSTANDARD
parameter \SIM_DEVICE
parameter \USE_IBUFDISABLE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7552"
wire input 5 \DCITERMDISABLE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7553"
wire input 6 \I
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7554"
wire input 7 \IBUFDISABLE
attribute \iopad_external_pin 1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7549"
wire inout 3 \IO
attribute \iopad_external_pin 1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7551"
wire inout 4 \IOB
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7546"
wire output 1 \O
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7547"
wire output 2 \OB
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7555"
wire input 8 \TM
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7556"
wire input 9 \TS
end
attribute \blackbox 1
attribute \cells_not_processed 1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7559"
module \IOBUFDS_DIFF_OUT_INTERMDISABLE
parameter \DIFF_TERM
parameter \DQS_BIAS
parameter \IBUF_LOW_PWR
parameter \IOSTANDARD
parameter \SIM_DEVICE
parameter \USE_IBUFDISABLE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7572"
wire input 5 \I
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7573"
wire input 6 \IBUFDISABLE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7574"
wire input 7 \INTERMDISABLE
attribute \iopad_external_pin 1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7569"
wire inout 3 \IO
attribute \iopad_external_pin 1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7571"
wire inout 4 \IOB
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7566"
wire output 1 \O
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7567"
wire output 2 \OB
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7575"
wire input 8 \TM
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7576"
wire input 9 \TS
end
attribute \blackbox 1
attribute \cells_not_processed 1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7504"
module \IOBUFDS_INTERMDISABLE
parameter \DIFF_TERM
parameter \DQS_BIAS
parameter \IBUF_LOW_PWR
parameter \IOSTANDARD
parameter \SIM_DEVICE
parameter \SLEW
parameter \USE_IBUFDISABLE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7517"
wire input 4 \I
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7518"
wire input 5 \IBUFDISABLE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7519"
wire input 6 \INTERMDISABLE
attribute \iopad_external_pin 1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7514"
wire inout 2 \IO
attribute \iopad_external_pin 1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7516"
wire inout 3 \IOB
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7512"
wire output 1 \O
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7520"
wire input 7 \T
end
attribute \blackbox 1
attribute \cells_not_processed 1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7453"
module \IOBUFE3
parameter \DRIVE
parameter \IBUF_LOW_PWR
parameter \IOSTANDARD
parameter \SIM_INPUT_BUFFER_OFFSET
parameter \USE_IBUFDISABLE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7462"
wire input 3 \DCITERMDISABLE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7463"
wire input 4 \I
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7464"
wire input 5 \IBUFDISABLE
attribute \iopad_external_pin 1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7461"
wire inout 2 \IO
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7459"
wire output 1 \O
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7465"
wire width 4 input 6 \OSC
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7466"
wire input 7 \OSC_EN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7467"
wire input 8 \T
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7468"
wire input 9 \VREF
end
attribute \blackbox 1
attribute \cells_not_processed 1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7421"
module \IOBUF_DCIEN
parameter \DRIVE
parameter \IBUF_LOW_PWR
parameter \IOSTANDARD
parameter \SIM_DEVICE
parameter \SLEW
parameter \USE_IBUFDISABLE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7431"
wire input 3 \DCITERMDISABLE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7432"
wire input 4 \I
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7433"
wire input 5 \IBUFDISABLE
attribute \iopad_external_pin 1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7430"
wire inout 2 \IO
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7428"
wire output 1 \O
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7434"
wire input 6 \T
end
attribute \blackbox 1
attribute \cells_not_processed 1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7437"
module \IOBUF_INTERMDISABLE
parameter \DRIVE
parameter \IBUF_LOW_PWR
parameter \IOSTANDARD
parameter \SIM_DEVICE
parameter \SLEW
parameter \USE_IBUFDISABLE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7447"
wire input 3 \I
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7448"
wire input 4 \IBUFDISABLE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7449"
wire input 5 \INTERMDISABLE
attribute \iopad_external_pin 1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7446"
wire inout 2 \IO
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7444"
wire output 1 \O
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7450"
wire input 6 \T
end
attribute \blackbox 1
attribute \cells_not_processed 1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:6000"
module \IODELAY
parameter \DELAY_SRC
parameter \HIGH_PERFORMANCE_MODE
parameter \IDELAY_TYPE
parameter \IDELAY_VALUE
parameter \ODELAY_VALUE
parameter \REFCLK_FREQUENCY
parameter \SIGNAL_PATTERN
attribute \clkbuf_sink 1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:6010"
wire input 2 \C
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:6011"
wire input 3 \CE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:6012"
wire input 4 \DATAIN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:6008"
wire output 1 \DATAOUT
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:6013"
wire input 5 \IDATAIN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:6014"
wire input 6 \INC
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:6015"
wire input 7 \ODATAIN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:6016"
wire input 8 \RST
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:6017"
wire input 9 \T
end
attribute \blackbox 1
attribute \cells_not_processed 1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7051"
module \IODELAY2
parameter \COUNTER_WRAPAROUND
parameter \DATA_RATE
parameter \DELAY_SRC
parameter \IDELAY2_VALUE
parameter \IDELAY_MODE
parameter \IDELAY_TYPE
parameter \IDELAY_VALUE
parameter \ODELAY_VALUE
parameter \SERDES_MODE
parameter \SIM_TAPDELAY_VALUE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7062"
wire output 1 \BUSY
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7067"
wire input 6 \CAL
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7068"
wire input 7 \CE
attribute \clkbuf_sink 1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7070"
wire input 8 \CLK
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7064"
wire output 3 \DATAOUT
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7063"
wire output 2 \DATAOUT2
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7065"
wire output 4 \DOUT
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7071"
wire input 9 \IDATAIN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7072"
wire input 10 \INC
attribute \clkbuf_sink 1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7074"
wire input 11 \IOCLK0
attribute \clkbuf_sink 1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7076"
wire input 12 \IOCLK1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7077"
wire input 13 \ODATAIN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7078"
wire input 14 \RST
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7079"
wire input 15 \T
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7066"
wire output 5 \TOUT
end
attribute \blackbox 1
attribute \cells_not_processed 1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:6056"
module \IODELAYE1
parameter \CINVCTRL_SEL
parameter \DELAY_SRC
parameter \HIGH_PERFORMANCE_MODE
parameter \IDELAY_TYPE
parameter \IDELAY_VALUE
parameter \ODELAY_TYPE
parameter \ODELAY_VALUE
parameter \REFCLK_FREQUENCY
parameter \SIGNAL_PATTERN
attribute \clkbuf_sink 1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:6069"
wire input 3 \C
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:6070"
wire input 4 \CE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:6071"
wire input 5 \CINVCTRL
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:6072"
wire input 6 \CLKIN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:6073"
wire width 5 input 7 \CNTVALUEIN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:6066"
wire width 5 output 1 \CNTVALUEOUT
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:6074"
wire input 8 \DATAIN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:6067"
wire output 2 \DATAOUT
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:6075"
wire input 9 \IDATAIN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:6076"
wire input 10 \INC
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:6077"
wire input 11 \ODATAIN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:6078"
wire input 12 \RST
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:6079"
wire input 13 \T
end
attribute \blackbox 1
attribute \cells_not_processed 1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7082"
module \IODRP2
parameter \DATA_RATE
parameter \SIM_TAPDELAY_VALUE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7090"
wire input 6 \ADD
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7091"
wire input 7 \BKST
attribute \clkbuf_sink 1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7093"
wire input 8 \CLK
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7094"
wire input 9 \CS
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7086"
wire output 2 \DATAOUT
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7085"
wire output 1 \DATAOUT2
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7087"
wire output 3 \DOUT
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7095"
wire input 10 \IDATAIN
attribute \clkbuf_sink 1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7097"
wire input 11 \IOCLK0
attribute \clkbuf_sink 1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7099"
wire input 12 \IOCLK1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7100"
wire input 13 \ODATAIN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7101"
wire input 14 \SDI
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7088"
wire output 4 \SDO
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7102"
wire input 15 \T
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7089"
wire output 5 \TOUT
end
attribute \blackbox 1
attribute \cells_not_processed 1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7105"
module \IODRP2_MCB
parameter \DATA_RATE
parameter \IDELAY_VALUE
parameter \MCB_ADDRESS
parameter \ODELAY_VALUE
parameter \SERDES_MODE
parameter \SIM_TAPDELAY_VALUE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7120"
wire input 9 \ADD
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7135"
wire width 5 input 21 \AUXADDR
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7112"
wire output 1 \AUXSDO
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7121"
wire input 10 \AUXSDOIN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7122"
wire input 11 \BKST
attribute \clkbuf_sink 1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7124"
wire input 12 \CLK
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7125"
wire input 13 \CS
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7114"
wire output 3 \DATAOUT
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7113"
wire output 2 \DATAOUT2
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7115"
wire output 4 \DOUT
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7116"
wire output 5 \DQSOUTN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7117"
wire output 6 \DQSOUTP
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7126"
wire input 14 \IDATAIN
attribute \clkbuf_sink 1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7128"
wire input 15 \IOCLK0
attribute \clkbuf_sink 1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7130"
wire input 16 \IOCLK1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7131"
wire input 17 \MEMUPDATE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7132"
wire input 18 \ODATAIN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7133"
wire input 19 \SDI
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7118"
wire output 7 \SDO
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7134"
wire input 20 \T
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7119"
wire output 8 \TOUT
end
attribute \blackbox 1
attribute \cells_not_processed 1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:5915"
module \ISERDES
parameter \BITSLIP_ENABLE
parameter \DATA_RATE
parameter \DATA_WIDTH
parameter \INIT_Q1
parameter \INIT_Q2
parameter \INIT_Q3
parameter \INIT_Q4
parameter \INTERFACE_TYPE
parameter \IOBDELAY
parameter \IOBDELAY_TYPE
parameter \IOBDELAY_VALUE
parameter \NUM_CE
parameter \SERDES_MODE
parameter \SIM_DELAY_D
parameter \SIM_HOLD_D_CLK
parameter \SIM_SETUP_D_CLK
parameter \SRVAL_Q1
parameter \SRVAL_Q2
parameter \SRVAL_Q3
parameter \SRVAL_Q4
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:5945"
wire input 10 \BITSLIP
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:5946"
wire input 11 \CE1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:5947"
wire input 12 \CE2
attribute \clkbuf_sink 1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:5949"
wire input 13 \CLK
attribute \clkbuf_sink 1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:5951"
wire input 14 \CLKDIV
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:5952"
wire input 15 \D
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:5953"
wire input 16 \DLYCE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:5954"
wire input 17 \DLYINC
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:5955"
wire input 18 \DLYRST
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:5936"
wire output 1 \O
attribute \clkbuf_sink 1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:5957"
wire input 19 \OCLK
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:5937"
wire output 2 \Q1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:5938"
wire output 3 \Q2
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:5939"
wire output 4 \Q3
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:5940"
wire output 5 \Q4
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:5941"
wire output 6 \Q5
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:5942"
wire output 7 \Q6
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:5958"
wire input 20 \REV
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:5959"
wire input 21 \SHIFTIN1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:5960"
wire input 22 \SHIFTIN2
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:5943"
wire output 8 \SHIFTOUT1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:5944"
wire output 9 \SHIFTOUT2
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:5961"
wire input 23 \SR
end
attribute \blackbox 1
attribute \cells_not_processed 1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7138"
module \ISERDES2
parameter \BITSLIP_ENABLE
parameter \DATA_RATE
parameter \DATA_WIDTH
parameter \INTERFACE_TYPE
parameter \SERDES_MODE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7155"
wire input 12 \BITSLIP
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7156"
wire input 13 \CE0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7144"
wire output 1 \CFB0
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7145"
wire output 2 \CFB1
attribute \clkbuf_sink 1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7158"
wire input 14 \CLK0
attribute \clkbuf_sink 1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7160"
wire input 15 \CLK1
attribute \clkbuf_sink 1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7162"
wire input 16 \CLKDIV
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7163"
wire input 17 \D
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7146"
wire output 3 \DFB
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7147"
wire output 4 \FABRICOUT
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7148"
wire output 5 \INCDEC
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7164"
wire input 18 \IOCE
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7149"
wire output 6 \Q1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7150"
wire output 7 \Q2
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7151"
wire output 8 \Q3
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7152"
wire output 9 \Q4
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7165"
wire input 19 \RST
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7166"
wire input 20 \SHIFTIN
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7153"
wire output 10 \SHIFTOUT
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:7154"
wire output 11 \VALID
end
attribute \blackbox 1
attribute \cells_not_processed 1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:6082"
module \ISERDESE1
parameter \DATA_RATE
parameter \DATA_WIDTH
parameter \DYN_CLKDIV_INV_EN
parameter \DYN_CLK_INV_EN
parameter \INIT_Q1
parameter \INIT_Q2
parameter \INIT_Q3
parameter \INIT_Q4
parameter \INTERFACE_TYPE
parameter \IOBDELAY
parameter \NUM_CE
parameter \OFB_USED
parameter \SERDES_MODE
parameter \SRVAL_Q1
parameter \SRVAL_Q2
parameter \SRVAL_Q3
parameter \SRVAL_Q4
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:6109"
wire input 10 \BITSLIP
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:6110"
wire input 11 \CE1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:6111"
wire input 12 \CE2
attribute \clkbuf_sink 1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:6113"
wire input 13 \CLK
attribute \clkbuf_sink 1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:6115"
wire input 14 \CLKB
attribute \clkbuf_sink 1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:6117"
wire input 15 \CLKDIV
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:6118"
wire input 16 \D
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:6119"
wire input 17 \DDLY
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:6120"
wire input 18 \DYNCLKDIVSEL
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:6121"
wire input 19 \DYNCLKSEL
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:6100"
wire output 1 \O
attribute \clkbuf_sink 1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:6123"
wire input 20 \OCLK
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:6124"
wire input 21 \OFB
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:6101"
wire output 2 \Q1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:6102"
wire output 3 \Q2
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:6103"
wire output 4 \Q3
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:6104"
wire output 5 \Q4
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:6105"
wire output 6 \Q5
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:6106"
wire output 7 \Q6
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:6125"
wire input 22 \RST
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:6126"
wire input 23 \SHIFTIN1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:6127"
wire input 24 \SHIFTIN2
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:6107"
wire output 8 \SHIFTOUT1
attribute \src "/usr/local/bin/../share/yosys/xilinx/cells_xtra.v:6108"
wire output 9 \SHIFTOUT2
end
attribute \blackbox 1
attribute \cells_not_processed 1
attribute \src "/usr/local/bin/../share/yosys/xili
Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment