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@hikalium
Created May 21, 2017 22:23
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verilog sample 001
module led (led1,led2,clk,btn);
input clk;
input btn;
output led1;
output led2;
reg[24:0]count;
assign led1 = count[24];
assign led2 = btn;
always @(posedge(clk)) begin
if(btn == 0) count <= count + 1;
end
endmodule
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