ADDSUB8.vhd

ADDSUB8.vhd

library ieee;
use ieee.std_logic_1164.all;
entity ha is
port(
	a,b: in std_logic;
	s,c: out std_logic);
end ha;
architecture behv of ha is
begin
	s<= a xor b;
	c<= a and b;
end behv;
-----------------------------

library ieee;
use ieee.std_logic_1164.all;
entity fa is
port(
	a,b,carryIn: in std_logic;
	s,carryout: out std_logic);
end fa;
architecture behv of fa is
begin
	s<= a xor b xor carryIn;
	carryout<= (a and b) or (carryIn and (a xor b));
end behv;
-------------------------------

library ieee;
use ieee.std_logic_1164.all;
entity addsub8 is
port(
	a,b: in std_logic_vector(7 downto 0);
	carryIn: in std_logic;
	f: out std_logic_vector(7 downto 0);
	unsigned_overflow, signed_overflow: inout std_logic);
end addsub8;
architecture behv of addsub8 is
	component fa is
	port(
	a,b,carryIn: in std_logic;
	s,carryout: out std_logic);
	end component;
	signal c: std_logic_vector(7 downto 1);
begin
	G0: fa port map(a(0),b(0),carryIn,f(0),c(1));
	G1: fa port map(a(1),b(1),c(1),f(1),c(2));
	G2: fa port map(a(2),b(2),c(2),f(2),c(3));
	G3: fa port map(a(3),b(3),c(3),f(3),c(4));
	G4: fa port map(a(4),b(4),c(4),f(4),c(5));
	G5: fa port map(a(5),b(5),c(5),f(5),c(6));
	G6: fa port map(a(6),b(6),c(6),f(6),c(7));
	G7: fa port map(a(7),b(7),c(7),f(7),unsigned_overflow);
signed_overflow <= c(7) xor unsigned_overflow;
end behv;

AE8.vhd

library ieee;
use ieee.std_logic_1164.all;

entity AE is
port(
	s: in std_logic_vector(2 downto 0);
	b: in std_logic;
	y: out std_logic);
end AE;

architecture behv of AE is
begin
	process(s,b)
	begin
		case s is
			when "100" => y <= b;
			when "101" => y <= not b;
			when "110" => y <= '0';
			when "111" => y <= '1';
			when others => y <= '0'; 
		end case;
	end process;
end behv;
--------------------------------

library ieee;
use ieee.std_logic_1164.all;

entity AE8 is
port(
	s: in std_logic_vector(2 downto 0);
	b: in std_logic_vector(7 downto 0);
	y: out std_logic_vector(7 downto 0));
end AE8;

architecture behv of AE8 is
	component AE is
	port(
	s: in std_logic_vector(2 downto 0);
	b: in std_logic;
	y: out std_logic);
	end component;
begin
	G0: AE port map(s,b(0),y(0));
	G1: AE port map(s,b(1),y(1));
	G2: AE port map(s,b(2),y(2));
	G3: AE port map(s,b(3),y(3));
	G4: AE port map(s,b(4),y(4));
	G5: AE port map(s,b(5),y(5));
	G6: AE port map(s,b(6),y(6));
	G7: AE port map(s,b(7),y(7));
end behv;

ALU.vhd

library ieee;
use ieee.std_logic_1164.all;

entity ALU is port(
	s: in std_logic_vector(4 downto 0);
	a,b : in std_logic_vector(7 downto 0);
	F: out std_logic_vector(7 downto 0);
	unsigned_overflow : inout std_logic;
	signed_overflow : inout std_logic;
	carry: out std_logic;
	zero: out std_logic);
end ALU ;

architecture imp of ALU is
component LE8 is port(
	s: 	in std_logic_vector(2 downto 0);
	a,b : 	in std_logic_vector(7 downto 0);
	x: 	out std_logic_vector(7 downto 0));
end component;

component AE8 is port(
	s: 	in std_logic_vector(2 downto 0);
	b: 	in std_logic_vector(7 downto 0);
	y:	out std_logic_vector(7 downto 0));
end component;

component ADDSUB8 is port(
	a,b : 	in std_logic_vector(7 downto 0);
	f: 	out std_logic_vector(7 downto 0);
	carryIn: in std_logic;
	unsigned_overflow: inout std_logic;
	signed_overflow: inout std_logic);
end component;

component SHIFTER is port(
	s: 	in std_logic_vector(1 downto 0);
	a:	in std_logic_vector(7 downto 0);
	y: 	out std_logic_vector(7 downto 0);
	carryOut: out std_logic;
	zero: out std_logic);
end component;

signal x,y, ShiftInput: std_logic_vector(7 downto 0);
signal c0: std_logic;

begin
 
	CarryExtender_ALU: c0 <= (s(0) xor s(1)) and s(2);
	LogicExtender8_ALU: LE8 port map( s(2 downto 0), a, b, x );
	ArithmeticExtender8_ALU: AE8 port map ( s(2 downto 0), b, y );
	AddSub8_ALU: addsub8 port map ( x, y, ShiftInput, c0 , unsigned_overflow , signed_overflow );
	Shifter_ALU: SHIFTER port map ( s (4 downto 3) , ShiftInput , f , carry , zero);

end imp;

LE8.vhd

library ieee;
use ieee.std_logic_1164.all;
entity LE is
port(
	s: in std_logic_vector(2 downto 0);
	a,b: in std_logic;
	x: out std_logic);
end LE;
architecture behv of LE is
begin
	process(s,a,b)
	begin
		case s is
			when "000" => x <= a;
			when "001" => x <= a and b;
			when "010" => x <= a or b;
			when "011" => x <= not a;
			when others => x <= a; 
		end case;
	end process;
end behv;
---------------------------

library ieee;
use ieee.std_logic_1164.all;
entity LE8 is
port(
	s: in std_logic_vector(2 downto 0);
	a,b: in std_logic_vector(7 downto 0);
	x: out std_logic_vector(7 downto 0));
end LE8;
architecture behv of LE8 is
	component LE is
	port(
	s: in std_logic_vector(2 downto 0);
	a,b: in std_logic;
	x: out std_logic);
	end component;
begin
	G0: LE port map(s,a(0),b(0),x(0));
	G1: LE port map(s,a(1),b(1),x(1));
	G2: LE port map(s,a(2),b(2),x(2));
	G3: LE port map(s,a(3),b(3),x(3));
	G4: LE port map(s,a(4),b(4),x(4));
	G5: LE port map(s,a(5),b(5),x(5));
	G6: LE port map(s,a(6),b(6),x(6));
	G7: LE port map(s,a(7),b(7),x(7));
end behv;

SHIFTER.vhd

library ieee;
use ieee.std_logic_1164.all;
entity mux4 is
port(
	s: in std_logic_vector(1 downto 0);
	x0,x1,x2,x3: in std_logic;
	y: out std_logic);
end mux4;
architecture behv of mux4 is
begin
	process(s,x0,x1,x2,x3)
	begin
		case s is
			when "00" => y <= x0;
			when "01" => y <= x1;
			when "10" => y <= x2;
			when "11" => y <= x3;
			when others => y <= '0';
		end case;
	end process;
end behv;
-------------------------------

library ieee;
use ieee.std_logic_1164.all;
entity SHIFTER is
port(
	s: in std_logic_vector(1 downto 0);
	a: in std_logic_vector(7 downto 0);
	y: out std_logic_vector(7 downto 0);
	carryout,zero: out std_logic);
end SHIFTER;
architecture behv of SHIFTER is
component mux4 is
port(
	s: in std_logic_vector(1 downto 0);
	x0,x1,x2,x3: in std_logic;
	y: out std_logic);
end component;
begin
	process(s)
	begin
		if(s="01") then
			carryout <= a(7);
		elsif(s="10") then
			carryout <= a(0);
		end if;
	end process;
	G0: mux4 port map(s,a(0),'0',a(1),a(1),y(0));
	G1: mux4 port map(s,a(1),a(0),a(2),a(2),y(1));
	G2: mux4 port map(s,a(2),a(1),a(3),a(3),y(2));
	G3: mux4 port map(s,a(3),a(2),a(4),a(4),y(3));
	G4: mux4 port map(s,a(4),a(3),a(5),a(5),y(4));
	G5: mux4 port map(s,a(5),a(4),a(6),a(6),y(5));
	G6: mux4 port map(s,a(6),a(5),a(7),a(7),y(6));
	G7: mux4 port map(s,a(7),a(6),'0',a(0),y(7));
	process(s)
	begin
		if(s="00") then
			if(a="0") then
				zero <= '1';
			else
				zero <= '0';
			end if;
		end if;
	end process;
end behv;