ALU.vhd

ALU.vhd

library ieee;
use ieee.std_logic_1164.all;

entity ALU is port(
	s: in std_logic_vector(4 downto 0);
	a,b : in std_logic_vector(7 downto 0);
	F: out std_logic_vector(7 downto 0);
	unsigned_overflow : inout std_logic;
	signed_overflow : inout std_logic;
	carry: out std_logic;
	zero: out std_logic);
end ALU ;

architecture imp of ALU is
component LE8 is port(
	s: 	in std_logic_vector(2 downto 0);
	a,b : 	in std_logic_vector(7 downto 0);
	x: 	out std_logic_vector(7 downto 0));
end component;

component AE8 is port(
	s: 	in std_logic_vector(2 downto 0);
	b: 	in std_logic_vector(7 downto 0);
	y:	out std_logic_vector(7 downto 0));
end component;

component ADDSUB8 is port(
	a,b : 	in std_logic_vector(7 downto 0);
	f: 	out std_logic_vector(7 downto 0);
	carryIn: in std_logic;
	unsigned_overflow: inout std_logic;
	signed_overflow: inout std_logic);
end component;

component SHIFTER is port(
	s: 	in std_logic_vector(1 downto 0);
	a:	in std_logic_vector(7 downto 0);
	y: 	out std_logic_vector(7 downto 0);
	carryOut: out std_logic;
	zero: out std_logic);
end component;

signal x,y, ShiftInput: std_logic_vector(7 downto 0);
signal c0: std_logic;

begin
 
	CarryExtender_ALU: c0 <= (s(0) xor s(1)) and s(2);
	LogicExtender8_ALU: LE8 port map( s(2 downto 0), a, b, x );
	ArithmeticExtender8_ALU: AE8 port map ( s(2 downto 0), b, y );
	AddSub8_ALU: addsub8 port map ( x, y, ShiftInput, c0 , unsigned_overflow , signed_overflow );
	Shifter_ALU: SHIFTER port map ( s (4 downto 3) , ShiftInput , f , carry , zero);

end imp;