audio_patch_hitech95_2018_16_19.patch

audio_patch_hitech95_2018_16_21.patch

diff --git a/arch/arm/boot/dts/sun8i-a33.dtsi b/arch/arm/boot/dts/sun8i-a33.dtsi
index a21f2ed..324a13f 100644
--- a/arch/arm/boot/dts/sun8i-a33.dtsi
+++ b/arch/arm/boot/dts/sun8i-a33.dtsi
@@ -184,22 +184,27 @@
 	sound: sound {
 		compatible = "simple-audio-card";
 		simple-audio-card,name = "sun8i-a33-audio";
-		simple-audio-card,format = "i2s";
-		simple-audio-card,frame-master = <&link_codec>;
-		simple-audio-card,bitclock-master = <&link_codec>;
-		simple-audio-card,mclk-fs = <512>;
 		simple-audio-card,aux-devs = <&codec_analog>;
 		simple-audio-card,routing =
-			"Left DAC", "AIF1 Slot 0 Left",
-			"Right DAC", "AIF1 Slot 0 Right";
+			"Left Digital DAC", "AIF1 Slot 0 Left",
+			"Right Digital DAC", "AIF1 Slot 0 Right",
+			"Left DAC", "Left Digital DAC",
+			"Right DAC", "Right Digital DAC";
 		status = "disabled";
 
-		simple-audio-card,cpu {
-			sound-dai = <&dai>;
-		};
+		simple-audio-card,dai-link@0 {		/* I2S - Headphone */
+			format = "i2s";
+			frame-master = <&link_codec>;
+			bitclock-master = <&link_codec>;
+			mclk-fs = <512>;
+
+			cpu {
+				sound-dai = <&dai>;
+			};
 
-		link_codec: simple-audio-card,codec {
-			sound-dai = <&codec>;
+			link_codec: codec {
+				sound-dai = <&codec 0>;
+			};
 		};
 	};
 
diff --git a/sound/soc/codecs/Kconfig b/sound/soc/codecs/Kconfig
index 9548f63..0227559 100644
--- a/sound/soc/codecs/Kconfig
+++ b/sound/soc/codecs/Kconfig
@@ -140,6 +140,7 @@ config SND_SOC_ALL_CODECS
 	select SND_SOC_RT5677 if I2C && SPI_MASTER
 	select SND_SOC_SGTL5000 if I2C
 	select SND_SOC_SI476X if MFD_SI476X_CORE
+	select SND_SOC_SIMPLEAMP
 	select SND_SOC_SIRF_AUDIO_CODEC
 	select SND_SOC_SPDIF
 	select SND_SOC_SSM2518 if I2C
@@ -864,6 +865,9 @@ config SND_SOC_SGTL5000
 config SND_SOC_SI476X
 	tristate
 
+config SND_SOC_SIMPLEAMP
+	tristate "ASoC Simple Amplifier support"
+
 config SND_SOC_SIGMADSP
 	tristate
 	select CRC32
diff --git a/sound/soc/codecs/Makefile b/sound/soc/codecs/Makefile
index e849d14..abc0533 100644
--- a/sound/soc/codecs/Makefile
+++ b/sound/soc/codecs/Makefile
@@ -150,6 +150,7 @@ snd-soc-sigmadsp-objs := sigmadsp.o
 snd-soc-sigmadsp-i2c-objs := sigmadsp-i2c.o
 snd-soc-sigmadsp-regmap-objs := sigmadsp-regmap.o
 snd-soc-si476x-objs := si476x.o
+snd-soc-simpleamp-objs := simple-amp.o
 snd-soc-sirf-audio-codec-objs := sirf-audio-codec.o
 snd-soc-spdif-tx-objs := spdif_transmitter.o
 snd-soc-spdif-rx-objs := spdif_receiver.o
@@ -402,6 +403,7 @@ obj-$(CONFIG_SND_SOC_SIGMADSP)	+= snd-soc-sigmadsp.o
 obj-$(CONFIG_SND_SOC_SIGMADSP_I2C)	+= snd-soc-sigmadsp-i2c.o
 obj-$(CONFIG_SND_SOC_SIGMADSP_REGMAP)	+= snd-soc-sigmadsp-regmap.o
 obj-$(CONFIG_SND_SOC_SI476X)	+= snd-soc-si476x.o
+obj-$(SND_SOC_SIMPLEAMP)	+= snd-soc-simpleamp.o
 obj-$(CONFIG_SND_SOC_SPDIF)	+= snd-soc-spdif-rx.o snd-soc-spdif-tx.o
 obj-$(CONFIG_SND_SOC_SIRF_AUDIO_CODEC) += sirf-audio-codec.o
 obj-$(CONFIG_SND_SOC_SSM2518)	+= snd-soc-ssm2518.o
diff --git a/sound/soc/sunxi/sun8i-codec.c b/sound/soc/sunxi/sun8i-codec.c
index fb37dd9..52dd739 100644
--- a/sound/soc/sunxi/sun8i-codec.c
+++ b/sound/soc/sunxi/sun8i-codec.c
@@ -6,6 +6,7 @@
  * Reuuimlla Technology Co., Ltd. <www.reuuimllatech.com>
  * huangxin <huangxin@Reuuimllatech.com>
  * Mylène Josserand <mylene.josserand@free-electrons.com>
+ * Nicolò Veronese <nicveronese@gmail.com>
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -29,75 +30,182 @@
 #include <sound/soc.h>
 #include <sound/soc-dapm.h>
 
-#define SUN8I_SYSCLK_CTL				0x00c
-#define SUN8I_SYSCLK_CTL_AIF1CLK_ENA			11
-#define SUN8I_SYSCLK_CTL_AIF1CLK_SRC_PLL		9
-#define SUN8I_SYSCLK_CTL_AIF1CLK_SRC			8
-#define SUN8I_SYSCLK_CTL_SYSCLK_ENA			3
-#define SUN8I_SYSCLK_CTL_SYSCLK_SRC			0
-#define SUN8I_MOD_CLK_ENA				0x010
-#define SUN8I_MOD_CLK_ENA_AIF1				15
-#define SUN8I_MOD_CLK_ENA_ADC				3
-#define SUN8I_MOD_CLK_ENA_DAC				2
-#define SUN8I_MOD_RST_CTL				0x014
-#define SUN8I_MOD_RST_CTL_AIF1				15
-#define SUN8I_MOD_RST_CTL_ADC				3
-#define SUN8I_MOD_RST_CTL_DAC				2
-#define SUN8I_SYS_SR_CTRL				0x018
-#define SUN8I_SYS_SR_CTRL_AIF1_FS			12
-#define SUN8I_SYS_SR_CTRL_AIF2_FS			8
-#define SUN8I_AIF1CLK_CTRL				0x040
-#define SUN8I_AIF1CLK_CTRL_AIF1_MSTR_MOD		15
-#define SUN8I_AIF1CLK_CTRL_AIF1_BCLK_INV		14
-#define SUN8I_AIF1CLK_CTRL_AIF1_LRCK_INV		13
-#define SUN8I_AIF1CLK_CTRL_AIF1_BCLK_DIV		9
-#define SUN8I_AIF1CLK_CTRL_AIF1_LRCK_DIV		6
-#define SUN8I_AIF1CLK_CTRL_AIF1_LRCK_DIV_16		(1 << 6)
-#define SUN8I_AIF1CLK_CTRL_AIF1_WORD_SIZ		4
-#define SUN8I_AIF1CLK_CTRL_AIF1_WORD_SIZ_16		(1 << 4)
-#define SUN8I_AIF1CLK_CTRL_AIF1_DATA_FMT		2
-#define SUN8I_AIF1_ADCDAT_CTRL				0x044
-#define SUN8I_AIF1_ADCDAT_CTRL_AIF1_DA0L_ENA		15
-#define SUN8I_AIF1_ADCDAT_CTRL_AIF1_DA0R_ENA		14
-#define SUN8I_AIF1_DACDAT_CTRL				0x048
+/* Clocks sources */
+#define SUN8I_SYSCLK_CTL							0x00c
+#define SUN8I_SYSCLK_CTL_AIF1CLK_ENA				11
+#define SUN8I_SYSCLK_CTL_AIF1CLK_SRC_PLL			9
+#define SUN8I_SYSCLK_CTL_AIF1CLK_SRC				8
+#define SUN8I_SYSCLK_CTL_AIF2CLK_ENA				7
+#define SUN8I_SYSCLK_CTL_AIF2CLK_SRC_PLL			5
+#define SUN8I_SYSCLK_CTL_AIF2CLK_SRC				4
+#define SUN8I_SYSCLK_CTL_SYSCLK_ENA					3
+#define SUN8I_SYSCLK_CTL_SYSCLK_SRC					0
+
+/* Clocks gates */
+#define SUN8I_MOD_CLK_ENA							0x010
+#define SUN8I_MOD_CLK_ENA_AIF1						15
+#define SUN8I_MOD_CLK_ENA_AIF2						14
+#define SUN8I_MOD_CLK_ENA_AIF3						13
+#define SUN8I_MOD_CLK_ENA_HPF_AGC					7
+#define SUN8I_MOD_CLK_ENA_HPF_DRC					6
+#define SUN8I_MOD_CLK_ENA_ADC						3
+#define SUN8I_MOD_CLK_ENA_DAC						2
+
+/* Resets */
+#define SUN8I_MOD_RST_CTL							0x014
+#define SUN8I_MOD_RST_CTL_AIF1						15
+#define SUN8I_MOD_RST_CTL_AIF2						14
+#define SUN8I_MOD_RST_CTL_AIF3						13
+#define SUN8I_MOD_RST_CTL_HPF_AGC					7
+#define SUN8I_MOD_RST_CTL_HPF_DRC					6
+#define SUN8I_MOD_RST_CTL_ADC						3
+#define SUN8I_MOD_RST_CTL_DAC						2
+
+/* AIF1 & AIF2 Sample Rate */
+#define SUN8I_SYS_SR_CTRL							0x018
+#define SUN8I_SYS_SR_CTRL_AIF1_FS					12
+#define SUN8I_SYS_SR_CTRL_AIF2_FS					8
+
+/* AIF1 & AIF2 & AIF3 Clocks */
+#define SUN8I_AIF1CLK_CTRL							0x040
+#define SUN8I_AIF2CLK_CTRL							0x080
+#define SUN8I_AIF0CLK_CTRL_AIF0_MSTR_MOD			15
+#define SUN8I_AIF0CLK_CTRL_AIF0_BCLK_INV			14
+#define SUN8I_AIF0CLK_CTRL_AIF0_LRCK_INV			13
+#define SUN8I_AIF0CLK_CTRL_AIF0_BCLK_DIV			9
+#define SUN8I_AIF0CLK_CTRL_AIF0_LRCK_DIV			6
+#define SUN8I_AIF0CLK_CTRL_AIF0_LRCK_DIV_16			(1 << 6)
+#define SUN8I_AIF0CLK_CTRL_AIF0_WORD_SIZ			4
+#define SUN8I_AIF0CLK_CTRL_AIF0_WORD_SIZ_16			(1 << 4)
+#define SUN8I_AIF0CLK_CTRL_AIF0_DATA_FMT			2
+/* AIF1 has TDM capabilities */
+#define SUN8I_AIF1CLK_CTRL_AIF1_TDMM_ENA			0
+/* AIF3 share the BCLK/LRCK */
+#define SUN8I_AIF3CLK_CTRL_AIF3_CLOC_SRC			0
+
+/* AIF1 SLOTs capture enables */
+#define SUN8I_AIF1_ADCDAT_CTRL						0x044
+#define SUN8I_AIF1_ADCDAT_CTRL_AIF1_AD0L_ENA		15
+#define SUN8I_AIF1_ADCDAT_CTRL_AIF1_AD0R_ENA		14
+#define SUN8I_AIF1_ADCDAT_CTRL_AIF1_AD1L_ENA		13
+#define SUN8I_AIF1_ADCDAT_CTRL_AIF1_AD1R_ENA		12
+#define SUN8I_AIF1_ADCDAT_CTRL_AIF1_SLOT_SIZ		0
+
+/* AIF1 SLOTs playback enables */
+#define SUN8I_AIF1_DACDAT_CTRL						0x048
 #define SUN8I_AIF1_DACDAT_CTRL_AIF1_DA0L_ENA		15
 #define SUN8I_AIF1_DACDAT_CTRL_AIF1_DA0R_ENA		14
-#define SUN8I_AIF1_MXR_SRC				0x04c
+#define SUN8I_AIF1_DACDAT_CTRL_AIF1_DA1L_ENA		13
+#define SUN8I_AIF1_DACDAT_CTRL_AIF1_DA1R_ENA		12
+#define SUN8I_AIF1_DACDAT_CTRL_AIF1_LOOP_ENA		0
+
+/* AIF1 Digital Mixer  */
+/* Slot 0 */
+#define SUN8I_AIF1_MXR_SRC							0x04c
 #define SUN8I_AIF1_MXR_SRC_AD0L_MXL_SRC_AIF1DA0L	15
 #define SUN8I_AIF1_MXR_SRC_AD0L_MXL_SRC_AIF2DACL	14
 #define SUN8I_AIF1_MXR_SRC_AD0L_MXL_SRC_ADCL		13
 #define SUN8I_AIF1_MXR_SRC_AD0L_MXL_SRC_AIF2DACR	12
+
 #define SUN8I_AIF1_MXR_SRC_AD0R_MXR_SRC_AIF1DA0R	11
 #define SUN8I_AIF1_MXR_SRC_AD0R_MXR_SRC_AIF2DACR	10
 #define SUN8I_AIF1_MXR_SRC_AD0R_MXR_SRC_ADCR		9
 #define SUN8I_AIF1_MXR_SRC_AD0R_MXR_SRC_AIF2DACL	8
-#define SUN8I_ADC_DIG_CTRL				0x100
-#define SUN8I_ADC_DIG_CTRL_ENDA			15
-#define SUN8I_ADC_DIG_CTRL_ADOUT_DTS			2
-#define SUN8I_ADC_DIG_CTRL_ADOUT_DLY			1
-#define SUN8I_DAC_DIG_CTRL				0x120
-#define SUN8I_DAC_DIG_CTRL_ENDA			15
-#define SUN8I_DAC_MXR_SRC				0x130
-#define SUN8I_DAC_MXR_SRC_DACL_MXR_SRC_AIF1DA0L	15
-#define SUN8I_DAC_MXR_SRC_DACL_MXR_SRC_AIF1DA1L	14
-#define SUN8I_DAC_MXR_SRC_DACL_MXR_SRC_AIF2DACL	13
-#define SUN8I_DAC_MXR_SRC_DACL_MXR_SRC_ADCL		12
-#define SUN8I_DAC_MXR_SRC_DACR_MXR_SRC_AIF1DA0R	11
-#define SUN8I_DAC_MXR_SRC_DACR_MXR_SRC_AIF1DA1R	10
-#define SUN8I_DAC_MXR_SRC_DACR_MXR_SRC_AIF2DACR	9
-#define SUN8I_DAC_MXR_SRC_DACR_MXR_SRC_ADCR		8
-
-#define SUN8I_SYS_SR_CTRL_AIF1_FS_MASK		GENMASK(15, 12)
-#define SUN8I_SYS_SR_CTRL_AIF2_FS_MASK		GENMASK(11, 8)
-#define SUN8I_AIF1CLK_CTRL_AIF1_WORD_SIZ_MASK	GENMASK(5, 4)
-#define SUN8I_AIF1CLK_CTRL_AIF1_LRCK_DIV_MASK	GENMASK(8, 6)
-#define SUN8I_AIF1CLK_CTRL_AIF1_BCLK_DIV_MASK	GENMASK(12, 9)
+/* Slot 1 */
+#define SUN8I_AIF1_MXR_SRC_AD1L_MXR_SRC_AIF2DACL	7
+#define SUN8I_AIF1_MXR_SRC_AD1L_MXR_SRC_ADCL		6
+
+#define SUN8I_AIF1_MXR_SRC_AD1R_MXR_SRC_AIF2DACR	3
+#define SUN8I_AIF1_MXR_SRC_AD1R_MXR_SRC_ADCR		2
+
+/* AIF1 SLOT0 & SLOT1 volume control */
+#define SUN8I_AIF1_VOL_CTRL_AD0						0x050
+#define SUN8I_AIF1_VOL_CTRL_AD1						0x054
+#define SUN8I_AIF1_VOL_CTRL_DA0						0x058
+#define SUN8I_AIF1_VOL_CTRL_DA1						0x05C
+#define SUN8I_AIF1_VOL_CTRL_LEFT					8
+#define SUN8I_AIF1_VOL_CTRL_RIGHT					0
+
+/* AIF2 capture enables */
+#define SUN8I_AIF2_ADCDAT_CTRL						0x084
+#define SUN8I_AIF2_ADCDAT_CTRL_AIF2_ADCL_ENA		15
+#define SUN8I_AIF2_ADCDAT_CTRL_AIF2_ADCR_ENA		14
+#define SUN8I_AIF2_ADCDAT_CTRL_AIF2_LOOP_ENA		0
+
+/* AIF2 playback enables */
+#define SUN8I_AIF2_DACDAT_CTRL						0x088
+#define SUN8I_AIF2_DACDAT_CTRL_AIF2_DA0L_ENA		15
+#define SUN8I_AIF2_DACDAT_CTRL_AIF2_DA0R_ENA		14
+
+/* AIF2 Mixer  */
+#define SUN8I_AIF2_MXR_SRC							0x08c
+#define SUN8I_AIF2_MXR_SRC_AD0L_MXL_SRC_AIF1DA0L	15
+#define SUN8I_AIF2_MXR_SRC_AD0L_MXL_SRC_AIF1DA1L	14
+#define SUN8I_AIF2_MXR_SRC_AD0L_MXL_SRC_AIF2DA0R	13
+#define SUN8I_AIF2_MXR_SRC_AD0L_MXL_SRC_ADCL		12
+
+#define SUN8I_AIF2_MXR_SRC_AD0R_MXL_SRC_AIF1DA0R	11
+#define SUN8I_AIF2_MXR_SRC_AD0R_MXL_SRC_AIF1DA1R	10
+#define SUN8I_AIF2_MXR_SRC_AD0R_MXL_SRC_AIF2DA0L	9
+#define SUN8I_AIF2_MXR_SRC_AD0R_MXL_SRC_ADCR		8
+
+/* AIF2 volume control */
+#define SUN8I_AIF2_VOL_CTRL_AD0						0x090
+#define SUN8I_AIF2_VOL_CTRL_AD1						0x098
+#define SUN8I_AIF2_VOL_CTRL_LEFT					8
+#define SUN8I_AIF2_VOL_CTRL_RIGHT					0
+
+/* AIF3 MUX  */
+#define SUN8I_AIF3_SGP_SRC							0x0cc
+#define SUN8I_AIF3_SGP_SRC_AIF3_ADC_SRC				10
+#define SUN8I_AIF3_SGP_SRC_AIF3_DAC_SRC				8
+
+/* ADC */
+#define SUN8I_ADC_DIG_CTRL							0x100
+#define SUN8I_ADC_DIG_CTRL_ENDA						15
+#define SUN8I_ADC_DIG_CTRL_ADOUT_DTS				2
+#define SUN8I_ADC_DIG_CTRL_ADOUT_DLY				1
+
+/* ADC Volume*/
+#define SUN8I_ADC_VOL_CTRL							0x104
+#define SUN8I_ADC_VOL_CTRL_ADC_VOL_L				8
+#define SUN8I_ADC_VOL_CTRL_ADC_VOL_L				0
+
+/* DAC */
+#define SUN8I_DAC_DIG_CTRL							0x120
+#define SUN8I_DAC_DIG_CTRL_ENDA						15
+#define SUN8I_DAC_DIG_CTRL_ENHPF					14
+
+/* DAC Volume */
+#define SUN8I_DAC_DIG_CTRL							0x124
+#define SUN8I_DAC_DIG_CTRL_DAC_VOL_L				8
+#define SUN8I_DAC_DIG_CTRL_DAC_VOL_R				0
+
+/* DAC Mixer */
+#define SUN8I_DAC_MXR_SRC							0x130
+#define SUN8I_DAC_MXR_SRC_DACL_MXR_SRC_AIF1DA0L		15
+#define SUN8I_DAC_MXR_SRC_DACL_MXR_SRC_AIF1DA1L		14
+#define SUN8I_DAC_MXR_SRC_DACL_MXR_SRC_AIF2DACL		13
+#define SUN8I_DAC_MXR_SRC_DACL_MXR_SRC_ADCL			12
+
+#define SUN8I_DAC_MXR_SRC_DACR_MXR_SRC_AIF1DA0R		11
+#define SUN8I_DAC_MXR_SRC_DACR_MXR_SRC_AIF1DA1R		10
+#define SUN8I_DAC_MXR_SRC_DACR_MXR_SRC_AIF2DACR		9
+#define SUN8I_DAC_MXR_SRC_DACR_MXR_SRC_ADCR			8
+
+#define SUN8I_SYS_SR_CTRL_AIF1_FS_MASK				GENMASK(15, 12)
+#define SUN8I_SYS_SR_CTRL_AIF2_FS_MASK				GENMASK(11, 8)
+#define SUN8I_AIF0CLK_CTRL_AIF0_WORD_SIZ_MASK		GENMASK(5, 4)
+#define SUN8I_AIF0CLK_CTRL_AIF0_LRCK_DIV_MASK		GENMASK(8, 6)
+#define SUN8I_AIF0CLK_CTRL_AIF0_BCLK_DIV_MASK		GENMASK(12, 9)
 
 struct sun8i_codec {
-	struct device	*dev;
-	struct regmap	*regmap;
-	struct clk	*clk_module;
-	struct clk	*clk_bus;
+	struct	device	*dev;
+	struct	regmap	*regmap;
+	struct	clk		*clk_module;
+	struct	clk		*clk_bus;
+
+	bool	aif1_tdm;
 };
 
 static int sun8i_codec_runtime_resume(struct device *dev)
@@ -199,8 +307,8 @@ static int sun8i_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
 		return -EINVAL;
 	}
 	regmap_update_bits(scodec->regmap, SUN8I_AIF1CLK_CTRL,
-			   BIT(SUN8I_AIF1CLK_CTRL_AIF1_MSTR_MOD),
-			   value << SUN8I_AIF1CLK_CTRL_AIF1_MSTR_MOD);
+			   BIT(SUN8I_AIF0CLK_CTRL_AIF0_MSTR_MOD),
+			   value << SUN8I_AIF0CLK_CTRL_AIF0_MSTR_MOD);
 
 	/* clock inversion */
 	switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
@@ -214,8 +322,8 @@ static int sun8i_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
 		return -EINVAL;
 	}
 	regmap_update_bits(scodec->regmap, SUN8I_AIF1CLK_CTRL,
-			   BIT(SUN8I_AIF1CLK_CTRL_AIF1_BCLK_INV),
-			   value << SUN8I_AIF1CLK_CTRL_AIF1_BCLK_INV);
+			   BIT(SUN8I_AIF0CLK_CTRL_AIF0_BCLK_INV),
+			   value << SUN8I_AIF0CLK_CTRL_AIF0_BCLK_INV);
 
 	/*
 	 * It appears that the DAI and the codec don't share the same
@@ -228,8 +336,8 @@ static int sun8i_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
 	 * invert the value here.
 	 */
 	regmap_update_bits(scodec->regmap, SUN8I_AIF1CLK_CTRL,
-			   BIT(SUN8I_AIF1CLK_CTRL_AIF1_LRCK_INV),
-			   !value << SUN8I_AIF1CLK_CTRL_AIF1_LRCK_INV);
+			   BIT(SUN8I_AIF0CLK_CTRL_AIF0_LRCK_INV),
+			   !value << SUN8I_AIF0CLK_CTRL_AIF0_LRCK_INV);
 
 	/* DAI format */
 	switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
@@ -250,8 +358,8 @@ static int sun8i_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
 		return -EINVAL;
 	}
 	regmap_update_bits(scodec->regmap, SUN8I_AIF1CLK_CTRL,
-			   BIT(SUN8I_AIF1CLK_CTRL_AIF1_DATA_FMT),
-			   value << SUN8I_AIF1CLK_CTRL_AIF1_DATA_FMT);
+			   BIT(SUN8I_AIF0CLK_CTRL_AIF0_DATA_FMT),
+			   value << SUN8I_AIF0CLK_CTRL_AIF0_DATA_FMT);
 
 	return 0;
 }
@@ -305,6 +413,8 @@ static int sun8i_codec_hw_params(struct snd_pcm_substream *substream,
 				 struct snd_soc_dai *dai)
 {
 	struct sun8i_codec *scodec = snd_soc_component_get_drvdata(dai->component);
+	int id = dai->id;
+	int reg, val, mask;
 	int sample_rate;
 	u8 bclk_div;
 
@@ -313,17 +423,17 @@ static int sun8i_codec_hw_params(struct snd_pcm_substream *substream,
 	 * codec to handle this type of sample resolution.
 	 */
 	regmap_update_bits(scodec->regmap, SUN8I_AIF1CLK_CTRL,
-			   SUN8I_AIF1CLK_CTRL_AIF1_WORD_SIZ_MASK,
-			   SUN8I_AIF1CLK_CTRL_AIF1_WORD_SIZ_16);
+			   SUN8I_AIF0CLK_CTRL_AIF0_WORD_SIZ_MASK,
+			   SUN8I_AIF0CLK_CTRL_AIF0_WORD_SIZ_16);
 
 	bclk_div = sun8i_codec_get_bclk_div(scodec, params_rate(params), 16);
 	regmap_update_bits(scodec->regmap, SUN8I_AIF1CLK_CTRL,
-			   SUN8I_AIF1CLK_CTRL_AIF1_BCLK_DIV_MASK,
-			   bclk_div << SUN8I_AIF1CLK_CTRL_AIF1_BCLK_DIV);
+			   SUN8I_AIF0CLK_CTRL_AIF0_BCLK_DIV_MASK,
+			   bclk_div << SUN8I_AIF0CLK_CTRL_AIF0_BCLK_DIV);
 
 	regmap_update_bits(scodec->regmap, SUN8I_AIF1CLK_CTRL,
-			   SUN8I_AIF1CLK_CTRL_AIF1_LRCK_DIV_MASK,
-			   SUN8I_AIF1CLK_CTRL_AIF1_LRCK_DIV_16);
+			   SUN8I_AIF0CLK_CTRL_AIF0_LRCK_DIV_MASK,
+			   SUN8I_AIF0CLK_CTRL_AIF0_LRCK_DIV_16);
 
 	sample_rate = sun8i_codec_get_hw_rate(params);
 	if (sample_rate < 0)
@@ -340,91 +450,181 @@ static int sun8i_codec_hw_params(struct snd_pcm_substream *substream,
 }
 
 static const struct snd_kcontrol_new sun8i_dac_mixer_controls[] = {
-	SOC_DAPM_DOUBLE("AIF1 Slot 0 Digital DAC Playback Switch",
+	SOC_DAPM_DOUBLE("AIF1 Slot 0 Digital DAC Mixer Switch",
 			SUN8I_DAC_MXR_SRC,
 			SUN8I_DAC_MXR_SRC_DACL_MXR_SRC_AIF1DA0L,
 			SUN8I_DAC_MXR_SRC_DACR_MXR_SRC_AIF1DA0R, 1, 0),
-	SOC_DAPM_DOUBLE("AIF1 Slot 1 Digital DAC Playback Switch",
+	SOC_DAPM_DOUBLE("AIF1 Slot 1 Digital DAC Mixer Switch",
 			SUN8I_DAC_MXR_SRC,
 			SUN8I_DAC_MXR_SRC_DACL_MXR_SRC_AIF1DA1L,
 			SUN8I_DAC_MXR_SRC_DACR_MXR_SRC_AIF1DA1R, 1, 0),
-	SOC_DAPM_DOUBLE("AIF2 Digital DAC Playback Switch", SUN8I_DAC_MXR_SRC,
+	SOC_DAPM_DOUBLE("AIF2 Digital DAC Mixer Switch", SUN8I_DAC_MXR_SRC,
 			SUN8I_DAC_MXR_SRC_DACL_MXR_SRC_AIF2DACL,
 			SUN8I_DAC_MXR_SRC_DACR_MXR_SRC_AIF2DACR, 1, 0),
-	SOC_DAPM_DOUBLE("ADC Digital DAC Playback Switch", SUN8I_DAC_MXR_SRC,
+	SOC_DAPM_DOUBLE("ADC Digital DAC Mixer Switch", SUN8I_DAC_MXR_SRC,
 			SUN8I_DAC_MXR_SRC_DACL_MXR_SRC_ADCL,
 			SUN8I_DAC_MXR_SRC_DACR_MXR_SRC_ADCR, 1, 0),
 };
 
-static const struct snd_kcontrol_new sun8i_input_mixer_controls[] = {
-	SOC_DAPM_DOUBLE("AIF1 Slot 0 Digital ADC Capture Switch",
+static const struct snd_kcontrol_new sun8i_aif1_s0_adc_mixer_controls[] = {
+	SOC_DAPM_DOUBLE("AIF1 Slot 0 Playback - AIF1 S0 Mixer Switch",
 			SUN8I_AIF1_MXR_SRC,
 			SUN8I_AIF1_MXR_SRC_AD0L_MXL_SRC_AIF1DA0L,
 			SUN8I_AIF1_MXR_SRC_AD0R_MXR_SRC_AIF1DA0R, 1, 0),
-	SOC_DAPM_DOUBLE("AIF2 Digital ADC Capture Switch", SUN8I_AIF1_MXR_SRC,
+	SOC_DAPM_DOUBLE("AIF2 Playback AIF1 - S0 Mixer Switch",
+			SUN8I_AIF1_MXR_SRC,
 			SUN8I_AIF1_MXR_SRC_AD0L_MXL_SRC_AIF2DACL,
 			SUN8I_AIF1_MXR_SRC_AD0R_MXR_SRC_AIF2DACR, 1, 0),
-	SOC_DAPM_DOUBLE("AIF1 Data Digital ADC Capture Switch",
+	SOC_DAPM_DOUBLE("ADC - AIF1 S0 Mixer Switch",
 			SUN8I_AIF1_MXR_SRC,
 			SUN8I_AIF1_MXR_SRC_AD0L_MXL_SRC_ADCL,
 			SUN8I_AIF1_MXR_SRC_AD0R_MXR_SRC_ADCR, 1, 0),
-	SOC_DAPM_DOUBLE("AIF2 Inv Digital ADC Capture Switch",
+	SOC_DAPM_DOUBLE("AIF2 Inv - AIF1 S0 Mixer Switch",
 			SUN8I_AIF1_MXR_SRC,
 			SUN8I_AIF1_MXR_SRC_AD0L_MXL_SRC_AIF2DACR,
 			SUN8I_AIF1_MXR_SRC_AD0R_MXR_SRC_AIF2DACL, 1, 0),
 };
 
+static const struct snd_kcontrol_new sun8i_aif1_s1_adc_mixer_controls[] = {
+	SOC_DAPM_DOUBLE("AIF2 Playback - AIF1 S1 Mixer Switch",
+			SUN8I_AIF1_MXR_SRC,
+			SUN8I_AIF1_MXR_SRC_AD1L_MXR_SRC_AIF2DACL,
+			SUN8I_AIF1_MXR_SRC_AD1R_MXR_SRC_AIF2DACR, 1, 0),
+	SOC_DAPM_DOUBLE("ADC - AIF1 S1 Mixer Switch",
+			SUN8I_AIF1_MXR_SRC,
+			SUN8I_AIF1_MXR_SRC_AD1L_MXR_SRC_ADCL,
+			SUN8I_AIF1_MXR_SRC_AD1R_MXR_SRC_ADCR, 1, 0),
+};
+
+static const struct snd_kcontrol_new sun8i_aif2_adc_mixer_controls[] = {
+	SOC_DAPM_DOUBLE("AIF1 Slot 0 Playback - AIF2 Mixer Switch",
+			SUN8I_AIF2_MXR_SRC,
+			SUN8I_AIF2_MXR_SRC_AD0L_MXL_SRC_AIF1DA0L,
+			SUN8I_AIF2_MXR_SRC_AD0R_MXL_SRC_AIF1DA0R, 1, 0),
+	SOC_DAPM_DOUBLE("AIF1 Slot 1 Playback - AIF2 Mixer Switch",
+			SUN8I_AIF2_MXR_SRC,
+			SUN8I_AIF2_MXR_SRC_AD0L_MXL_SRC_AIF1DA1L,
+			SUN8I_AIF2_MXR_SRC_AD0R_MXL_SRC_AIF1DA1R, 1, 0),
+	SOC_DAPM_DOUBLE("AIF2 Playback Inv - AIF2 Mixer Switch",
+			SUN8I_AIF2_MXR_SRC,
+			SUN8I_AIF2_MXR_SRC_AD0L_MXL_SRC_ADCL,
+			SUN8I_AIF2_MXR_SRC_AD0R_MXL_SRC_ADCR, 1, 0),
+	SOC_DAPM_DOUBLE("ADC - AIF2 Mixer Switch",
+			SUN8I_AIF2_MXR_SRC,
+			SUN8I_AIF2_MXR_SRC_AD0R_MXL_SRC_AIF2DA0L,
+			SUN8I_AIF2_MXR_SRC_AD0L_MXL_SRC_AIF2DA0R, 1, 0),
+};
+
+
 static const struct snd_soc_dapm_widget sun8i_codec_dapm_widgets[] = {
-	/* Digital parts of the DACs and ADC */
+	/* Digital parts of the DACs and ADCs */
 	SND_SOC_DAPM_SUPPLY("DAC", SUN8I_DAC_DIG_CTRL, SUN8I_DAC_DIG_CTRL_ENDA,
 			    0, NULL, 0),
 	SND_SOC_DAPM_SUPPLY("ADC", SUN8I_ADC_DIG_CTRL, SUN8I_ADC_DIG_CTRL_ENDA,
 			    0, NULL, 0),
 
-	/* Analog DAC AIF */
-	SND_SOC_DAPM_AIF_IN("AIF1 Slot 0 Left", "Playback", 0,
+	/* AIF1 Playback */
+	SND_SOC_DAPM_AIF_IN("AIF1 Slot 0 Left Playback", "Playback", 0,
 			    SUN8I_AIF1_DACDAT_CTRL,
 			    SUN8I_AIF1_DACDAT_CTRL_AIF1_DA0L_ENA, 0),
-	SND_SOC_DAPM_AIF_IN("AIF1 Slot 0 Right", "Playback", 0,
+	SND_SOC_DAPM_AIF_IN("AIF1 Slot 0 Right Playback", "Playback", 0,
 			    SUN8I_AIF1_DACDAT_CTRL,
 			    SUN8I_AIF1_DACDAT_CTRL_AIF1_DA0R_ENA, 0),
+	SND_SOC_DAPM_AIF_IN("AIF1 Slot 1 Left Playback", "Playback", 1,
+			    SUN8I_AIF1_DACDAT_CTRL,
+			    SUN8I_AIF1_DACDAT_CTRL_AIF1_DA1L_ENA, 0),
+	SND_SOC_DAPM_AIF_IN("AIF1 Slot 1 Right Playback", "Playback", 1,
+			    SUN8I_AIF1_DACDAT_CTRL,
+			    SUN8I_AIF1_DACDAT_CTRL_AIF1_DA1R_ENA, 0),
 
-	/* Analog ADC AIF */
-	SND_SOC_DAPM_AIF_IN("AIF1 Slot 0 Left ADC", "Capture", 0,
+	/* AIF1 Capture */
+	SND_SOC_DAPM_AIF_OUT("AIF1 Slot 0 Left Capture", "Capture", 0,
 			    SUN8I_AIF1_ADCDAT_CTRL,
 			    SUN8I_AIF1_ADCDAT_CTRL_AIF1_DA0L_ENA, 0),
-	SND_SOC_DAPM_AIF_IN("AIF1 Slot 0 Right ADC", "Capture", 0,
+	SND_SOC_DAPM_AIF_OUT("AIF1 Slot 0 Right Capture", "Capture", 0,
 			    SUN8I_AIF1_ADCDAT_CTRL,
 			    SUN8I_AIF1_ADCDAT_CTRL_AIF1_DA0R_ENA, 0),
+	SND_SOC_DAPM_AIF_OUT("AIF1 Slot 1 Left ADC", "Capture", 1,
+			    SUN8I_AIF1_ADCDAT_CTRL,
+			    SUN8I_AIF1_ADCDAT_CTRL_AIF1_DA1L_ENA, 0),
+	SND_SOC_DAPM_AIF_OUT("AIF1 Slot 1 Right ADC", "Capture", 1,
+			    SUN8I_AIF1_ADCDAT_CTRL,
+			    SUN8I_AIF1_ADCDAT_CTRL_AIF1_DA1R_ENA, 0),
+
+	/* Playback/Capture AIF2 */
+	SND_SOC_DAPM_AIF_IN("AIF2 Left Playback", "Playback", 0,
+					SUN8I_AIF1_DACDAT_CTRL,
+					SUN8I_AIF1_DACDAT_CTRL_AIF1_DA0L_ENA, 0),
+	SND_SOC_DAPM_AIF_IN("AIF2 Right Playback", "Playback", 0,
+					SUN8I_AIF1_DACDAT_CTRL,
+					SUN8I_AIF1_DACDAT_CTRL_AIF1_DA0R_ENA, 0),
+	SND_SOC_DAPM_AIF_OUT("AIF2 Left Capture", "Capture", 0,
+					SUN8I_AIF1_ADCDAT_CTRL,
+					SUN8I_AIF1_ADCDAT_CTRL_AIF1_DA0L_ENA, 0),
+	SND_SOC_DAPM_AIF_OUT("AIF2 Right Capture", "Capture", 0,
+					SUN8I_AIF1_ADCDAT_CTRL,
+					SUN8I_AIF1_ADCDAT_CTRL_AIF1_DA0R_ENA, 0),
+
+	/* Playback digital outputs to analog codec */
+	SND_SOC_DAPM_AIF_OUT("Left Digital DAC", NULL, 0, SND_SOC_NOPM, 0, 0),
+	SND_SOC_DAPM_AIF_OUT("Right Digital DAC", NULL, 0, SND_SOC_NOPM, 0, 0),
+
+	/* Capture digital inputs from analog codec */
+	SND_SOC_DAPM_AIF_IN("Left Digital ADC", NULL, 0, SND_SOC_NOPM, 0, 0),
+	SND_SOC_DAPM_AIF_IN("Right Digital ADC", NULL, 0, SND_SOC_NOPM, 0, 0),
 
 	/* DAC and ADC Mixers */
 	SOC_MIXER_ARRAY("Left Digital DAC Mixer", SND_SOC_NOPM, 0, 0,
 			sun8i_dac_mixer_controls),
 	SOC_MIXER_ARRAY("Right Digital DAC Mixer", SND_SOC_NOPM, 0, 0,
 			sun8i_dac_mixer_controls),
-	SOC_MIXER_ARRAY("Left Digital ADC Mixer", SND_SOC_NOPM, 0, 0,
-			sun8i_input_mixer_controls),
-	SOC_MIXER_ARRAY("Right Digital ADC Mixer", SND_SOC_NOPM, 0, 0,
-			sun8i_input_mixer_controls),
+	SOC_MIXER_ARRAY("Left Digital AIF1 S0 Mixer", SND_SOC_NOPM, 0, 0,
+			sun8i_aif1_s0_adc_mixer_controls),
+	SOC_MIXER_ARRAY("Right Digital AIF1 S0 Mixer", SND_SOC_NOPM, 0, 0,
+			sun8i_aif1_s0_adc_mixer_controls),
+	
+	SOC_MIXER_ARRAY("Left Digital AIF1 S1 Mixer", SND_SOC_NOPM, 0, 0,
+			sun8i_aif1_s1_adc_mixer_controls),
+	SOC_MIXER_ARRAY("Right Digital AIF1 S1 Mixer", SND_SOC_NOPM, 0, 0,
+			sun8i_aif1_s1_adc_mixer_controls),
+
+	SOC_MIXER_ARRAY("Left Digital AIF2 Mixer", SND_SOC_NOPM, 0, 0,
+			sun8i_aif2_adc_mixer_controls),
+	SOC_MIXER_ARRAY("Right Digital AIF2 Mixer", SND_SOC_NOPM, 0, 0,
+			sun8i_aif2_adc_mixer_controls),
 
 	/* Clocks */
-	SND_SOC_DAPM_SUPPLY("MODCLK AFI1", SUN8I_MOD_CLK_ENA,
-			    SUN8I_MOD_CLK_ENA_AIF1, 0, NULL, 0),
-	SND_SOC_DAPM_SUPPLY("MODCLK DAC", SUN8I_MOD_CLK_ENA,
-			    SUN8I_MOD_CLK_ENA_DAC, 0, NULL, 0),
-	SND_SOC_DAPM_SUPPLY("MODCLK ADC", SUN8I_MOD_CLK_ENA,
-			    SUN8I_MOD_CLK_ENA_ADC, 0, NULL, 0),
-	SND_SOC_DAPM_SUPPLY("AIF1", SUN8I_SYSCLK_CTL,
-			    SUN8I_SYSCLK_CTL_AIF1CLK_ENA, 0, NULL, 0),
 	SND_SOC_DAPM_SUPPLY("SYSCLK", SUN8I_SYSCLK_CTL,
 			    SUN8I_SYSCLK_CTL_SYSCLK_ENA, 0, NULL, 0),
-
+	SND_SOC_DAPM_SUPPLY("AIF1", SUN8I_SYSCLK_CTL,
+			    SUN8I_SYSCLK_CTL_AIF1CLK_ENA, 0, NULL, 0),
 	SND_SOC_DAPM_SUPPLY("AIF1 PLL", SUN8I_SYSCLK_CTL,
 			    SUN8I_SYSCLK_CTL_AIF1CLK_SRC_PLL, 0, NULL, 0),
-	/* Inversion as 0=AIF1, 1=AIF2 */
+	/* Inversion as 0=AIF1, 1=AIF2 TODO - Move this into Hw params? thisis the whole codec clock */
 	SND_SOC_DAPM_SUPPLY("SYSCLK AIF1", SUN8I_SYSCLK_CTL,
 			    SUN8I_SYSCLK_CTL_SYSCLK_SRC, 1, NULL, 0),
 
+	SND_SOC_DAPM_SUPPLY("MODCLK AFI1", SUN8I_MOD_CLK_ENA,
+			    SUN8I_MOD_CLK_ENA_AIF1, 0, NULL, 0),
+	SND_SOC_DAPM_SUPPLY("MODCLK AFI2", SUN8I_MOD_CLK_ENA,
+			    SUN8I_MOD_CLK_ENA_AIF2, 0, NULL, 0),
+	SND_SOC_DAPM_SUPPLY("MODCLK AFI3", SUN8I_MOD_CLK_ENA,
+			    SUN8I_MOD_CLK_ENA_AIF3, 0, NULL, 0),
+	SND_SOC_DAPM_SUPPLY("MODCLK HPF AGC", SUN8I_MOD_CLK_ENA,
+			    SUN8I_MOD_CLK_ENA_HPF_AGC, 0, NULL, 0),
+	SND_SOC_DAPM_SUPPLY("MODCLK HPF DRC", SUN8I_MOD_CLK_ENA,
+			    SUN8I_MOD_CLK_ENA_HPF_DRC, 0, NULL, 0),
+	SND_SOC_DAPM_SUPPLY("MODCLK ADC", SUN8I_MOD_CLK_ENA,
+			    SUN8I_MOD_CLK_ENA_ADC, 0, NULL, 0),										
+	SND_SOC_DAPM_SUPPLY("MODCLK DAC", SUN8I_MOD_CLK_ENA,
+			    SUN8I_MOD_CLK_ENA_DAC, 0, NULL, 0),
+
+	
+	
+
+	
+	
+
 	/* Module reset */
 	SND_SOC_DAPM_SUPPLY("RST AIF1", SUN8I_MOD_RST_CTL,
 			    SUN8I_MOD_RST_CTL_AIF1, 0, NULL, 0),
@@ -433,17 +633,27 @@ static const struct snd_soc_dapm_widget sun8i_codec_dapm_widgets[] = {
 	SND_SOC_DAPM_SUPPLY("RST ADC", SUN8I_MOD_RST_CTL,
 			    SUN8I_MOD_RST_CTL_ADC, 0, NULL, 0),
 
-	SND_SOC_DAPM_MIC("Headset Mic", NULL),
-	SND_SOC_DAPM_MIC("Mic", NULL),
+	/* TODO - NO ide aof what is this */
+	/*SND_SOC_DAPM_MIC("Headset Mic", NULL),
+	SND_SOC_DAPM_MIC("Mic", NULL),*/
 
 };
 
 static const struct snd_soc_dapm_route sun8i_codec_dapm_routes[] = {
 	/* Clock Routes */
+	/* AIF1 */
 	{ "AIF1", NULL, "SYSCLK AIF1" },
 	{ "AIF1 PLL", NULL, "AIF1" },
 	{ "RST AIF1", NULL, "AIF1 PLL" },
 	{ "MODCLK AFI1", NULL, "RST AIF1" },
+
+	/* AIF2 */
+	{ "AIF2", NULL, "SYSCLK AIF2" },
+	{ "AIF2 PLL", NULL, "AIF2" },
+	{ "RST AIF2", NULL, "AIF2 PLL" },
+	{ "MODCLK AFI2", NULL, "RST AIF2" },
+
+
 	{ "DAC", NULL, "MODCLK AFI1" },
 	{ "ADC", NULL, "MODCLK AFI1" },
 
@@ -455,21 +665,65 @@ static const struct snd_soc_dapm_route sun8i_codec_dapm_routes[] = {
 	{ "MODCLK ADC", NULL, "RST ADC" },
 	{ "ADC", NULL, "MODCLK ADC" },
 
-	/* DAC Routes */
-	{ "AIF1 Slot 0 Right", NULL, "DAC" },
-	{ "AIF1 Slot 0 Left", NULL, "DAC" },
+	/* AIF1 Playback Routes */
+	/* DAC DAP */
+	{ "Left Digital DAC", NULL, "DAC" },
+	{ "Right Digital DAC", NULL, "DAC" },
+	/* DAC Path */
+	{ "Left Digital DAC", NULL, "Left Digital DAC Mixer" },
+	{ "Right Digital DAC", NULL, "Right Digital DAC Mixer" },
 
 	/* DAC Mixer Routes */
-	{ "Left Digital DAC Mixer", "AIF1 Slot 0 Digital DAC Playback Switch",
-	  "AIF1 Slot 0 Left"},
-	{ "Right Digital DAC Mixer", "AIF1 Slot 0 Digital DAC Playback Switch",
-	  "AIF1 Slot 0 Right"},
-
-	/* ADC routes */
-	{ "Left Digital ADC Mixer", "AIF1 Data Digital ADC Capture Switch",
-	  "AIF1 Slot 0 Left ADC" },
-	{ "Right Digital ADC Mixer", "AIF1 Data Digital ADC Capture Switch",
-	  "AIF1 Slot 0 Right ADC" },
+	/* Mixer AIF1 Slot 0 */
+	{ "Left Digital DAC Mixer", "AIF1 Slot 0 Digital DAC Mixer Switch",
+	  "AIF1 Slot 0 Left Playback"},
+	{ "Right Digital DAC Mixer", "AIF1 Slot 0 Digital DAC Mixer Switch",
+	  "AIF1 Slot 0 Right Playback"},
+	/* Mixer AIF1 Slot 1 */
+	{ "Left Digital DAC Mixer", "AIF1 Slot 1 Digital DAC Mixer Switch",
+	  "AIF1 Slot 1 Left Playback"},
+	{ "Right Digital DAC Mixer", "AIF1 Slot 1 Digital DAC Mixer Switch",
+	  "AIF1 Slot 1 Right Playback"},
+	/* Mixer AIF2 */
+	{ "Right Digital DAC Mixer", "AIF2 Digital DAC Mixer Switch",
+	  "AIF2 Left Playback"},
+	{ "Right Digital DAC Mixer", "AIF2 Digital DAC Mixer Switch",
+	  "AIF2 Right Playback"},
+	/* Mixer ADC */
+	{ "Right Digital DAC Mixer", "ADC Digital DAC Mixer Switch",
+		"Left Digital ADC"},
+	{ "Right Digital DAC Mixer", "ADC Digital DAC Mixer Switch",
+		"Right Digital ADC"},
+
+	/* AIF1 Capture Routes */
+	/* DAC DAP */
+	{ "Left Digital ADC", NULL, "ADC" },
+	{ "Right Digital ADC", NULL, "ADC" },
+	/* ADC Path */
+	{ "AIF1 Slot 0 Left Capture", NULL, "Left Digital AIF1 S0 Mixer" },
+	{ "AIF1 Slot 0 Right Capture", NULL, "Right Digital AIF1 S0 Mixer" },
+
+	/* AIF1 Slot 0 Mixer routes */
+	/* Mixer ADC */
+	{ "Left Digital AIF1 S0 Mixer", "ADC Digital AIF1 S0 Mixer Switch",
+		 "Left Digital ADC"},
+	{ "Right Digital AIF1 S0 Mixer", "ADC Digital AIF1 S0 Mixer Switch",
+		 "Right Digital ADC"},
+	/* Mixer AIF1 Slot 0 */
+	{ "Left Digital AIF1 S0 Mixer", "AIF1 Slot 0 Digital AIF1 S0 Mixer Switch",
+		"AIF1 Slot 0 Left Playback"},
+	{ "Right Digital AIF1 S0 Mixer", "AIF1 Slot 0 Digital AIF1 S0 Mixer Switch",
+		"AIF1 Slot 0 Right Playback"},
+	/* Mixer AIF2*/
+	{ "Left Digital AIF1 S0 Mixer", "AIF2 Digital AIF1 S0 Mixer Switch",
+		 "AIF1 Slot 0 Left Playback"},
+	{ "Right Digital AIF1 S0 Mixer", "AIF2 Digital AIF1 S0 Mixer Switch",
+		 "AIF1 Slot 0 Right Playback"},
+	/* Mixer AIF2 Inverted*/
+	{ "Left Digital AIF1 S0 Mixer", "AIF2 Inv Digital AIF1 S0 Mixer Switch",
+		"AIF1 Slot 0 Left Playback"},
+	{ "Right Digital AIF1 S0 Mixer", "AIF2 Inv Digital AIF1 S0 Mixer Switch",
+		"AIF1 Slot 0 Right Playback"},
 };
 
 static const struct snd_soc_dai_ops sun8i_codec_dai_ops = {
@@ -477,27 +731,73 @@ static const struct snd_soc_dai_ops sun8i_codec_dai_ops = {
 	.set_fmt = sun8i_set_fmt,
 };
 
-static struct snd_soc_dai_driver sun8i_codec_dai = {
-	.name = "sun8i",
-	/* playback capabilities */
-	.playback = {
-		.stream_name = "Playback",
-		.channels_min = 1,
-		.channels_max = 2,
-		.rates = SNDRV_PCM_RATE_8000_192000,
-		.formats = SNDRV_PCM_FMTBIT_S16_LE,
+static struct snd_soc_dai_driver sun8i_codec_dai[] = {
+	{
+		.name = "sun8i-aif1",
+		/* playback capabilities */
+		.playback = {
+			.stream_name = "Playback",
+			.channels_min = 1,
+			.channels_max = 2,
+			.rates = SNDRV_PCM_RATE_8000_192000,
+			.formats = SNDRV_PCM_FMTBIT_S16_LE,
+		},
+		/* capture capabilities */
+		.capture = {
+			.stream_name = "Capture",
+			.channels_min = 1,
+			.channels_max = 2,
+			.rates = SNDRV_PCM_RATE_8000_192000,
+			.formats = SNDRV_PCM_FMTBIT_S16_LE,
+			.sig_bits = 24,
+		},
+		/* pcm operations */
+		.ops = &sun8i_codec_dai_ops,
+	},
+	{
+		.name = "sun8i-aif2",
+		/* playback capabilities */
+		.playback = {
+			.stream_name = "Playback",
+			.channels_min = 1,
+			.channels_max = 2,
+			.rates = SNDRV_PCM_RATE_8000_192000,
+			.formats = SNDRV_PCM_FMTBIT_S16_LE,
+		},
+		/* capture capabilities */
+		.capture = {
+			.stream_name = "Capture",
+			.channels_min = 1,
+			.channels_max = 2,
+			.rates = SNDRV_PCM_RATE_8000_192000,
+			.formats = SNDRV_PCM_FMTBIT_S16_LE,
+			.sig_bits = 24,
+		},
+		/* pcm operations */
+		.ops = &sun8i_codec_dai_ops,
 	},
-	/* capture capabilities */
-	.capture = {
-		.stream_name = "Capture",
-		.channels_min = 1,
-		.channels_max = 2,
-		.rates = SNDRV_PCM_RATE_8000_192000,
-		.formats = SNDRV_PCM_FMTBIT_S16_LE,
-		.sig_bits = 24,
+	{
+		.name = "sun8i-aif3",
+		/* playback capabilities */
+		.playback = {
+			.stream_name = "Playback",
+			.channels_min = 1,
+			.channels_max = 1,
+			.rates = SNDRV_PCM_RATE_8000_192000,
+			.formats = SNDRV_PCM_FMTBIT_S16_LE,
+		},
+		/* capture capabilities */
+		.capture = {
+			.stream_name = "Capture",
+			.channels_min = 1,
+			.channels_max = 1,
+			.rates = SNDRV_PCM_RATE_8000_192000,
+			.formats = SNDRV_PCM_FMTBIT_S16_LE,
+			.sig_bits = 24,
+		},
+		/* pcm operations */
+		.ops = &sun8i_codec_dai_ops,
 	},
-	/* pcm operations */
-	.ops = &sun8i_codec_dai_ops,
 };
 
 static const struct snd_soc_component_driver sun8i_soc_component = {
@@ -569,7 +869,7 @@ static int sun8i_codec_probe(struct platform_device *pdev)
 	}
 
 	ret = devm_snd_soc_register_component(&pdev->dev, &sun8i_soc_component,
-				     &sun8i_codec_dai, 1);
+				     sun8i_codec_dai, ARRAY_SIZE(sun8i_codec_dai));
 	if (ret) {
 		dev_err(&pdev->dev, "Failed to register codec\n");
 		goto err_suspend;

wifi-bt-bpi-m2m.patch

diff --git a/arch/arm/boot/dts/sun8i-r16-bananapi-m2m.dts b/arch/arm/boot/dts/sun8i-r16-bananapi-m2m.dts
index eaf0966..e2eade4 100644
--- a/arch/arm/boot/dts/sun8i-r16-bananapi-m2m.dts
+++ b/arch/arm/boot/dts/sun8i-r16-bananapi-m2m.dts
@@ -163,6 +163,14 @@
 	bus-width = <4>;
 	non-removable;
 	status = "okay";
+
+	brcmf: bcrmf@1 {
+		reg = <1>;
+		compatible = "brcm,bcm4329-fmac";
+		interrupt-parent = <&r_pio>;
+		interrupts = <0 7 IRQ_TYPE_LEVEL_LOW>; /* PL7 / EINT7 */
+		interrupt-names = "host-wake";
+	};
 };
 
 &mmc2 {
@@ -297,10 +305,24 @@
 	status = "okay";
 };
 
+&rtc {
+	clock-output-names = "osc32k", "osc32k-out";
+};
+
 &uart1 {
 	pinctrl-names = "default";
 	pinctrl-0 = <&uart1_pins_a>, <&uart1_pins_cts_rts_a>;
 	status = "okay";
+
+	bluetooth {
+		compatible = "brcm,bcm43438-bt";
+		max-speed = <115200>;
+		shutdown-gpios = <&r_pio 0 8 GPIO_ACTIVE_HIGH>;  /* PL8 */
+		device-wakeup-gpios = <&r_pio 0 10 GPIO_ACTIVE_HIGH>;  /* PL10 */
+		host-wakeup-gpios = <&r_pio 0 9 GPIO_ACTIVE_HIGH>;  /* PL9 */
+		clocks = <&rtc 1>;
+		clock-names = "extclk";
+	};
 };
 
 &usb_otg {