FizzBuzz by FPGA DE0 (QuartusII,verilog)

bcdall0.v

module bcdall0(BCD3,BCD2,BCD1,BCD0, lampoff);
  input [3:0] BCD3;
	input [3:0] BCD2;
	input [3:0] BCD1;
	input [3:0] BCD0;
	output lampoff;
	
	assign lampoff=(BCD0==4'd0)&(BCD1==4'd0)&(BCD2==4'd0)&(BCD3==4'd0);
endmodule

bcdtofzbz

// BCD code override FizzBuzz font
//
module bcdtofzbz(
  BCD3,BCD2,BCD1,BCD0,
	fizz,buzz,lampoff,
	BCD3out,BCD2out,BCD1out,BCD0out);
	input [3:0] BCD3;
	input [3:0] BCD2;
	input [3:0] BCD1;
	input [3:0] BCD0;
	input fizz;
	input buzz;
	input lampoff;
	output [3:0] BCD3out;
	output [3:0] BCD2out;
	output [3:0] BCD1out;
	output [3:0] BCD0out;

/*
	function [15:0] bcdout;
		input fizz,buzz;lampoff;
		input [15:0] bcdin;
		case({buzz,fizz})
			0: bcdout[15:0]=~lampoff & bcdin[15:0];
			1: bcdout[15:0]=16'hfcaa; // Fizz
			2: bcdout[15:0]=16'hbdaa; // Buzz
			3: bcdout[15:0]=16'hfaba; // FizzBuzz
		endcase
	endfunction

	assign {BCD3out,BCD2out,BCD1out,BCD0out}=bcdout(fizz,buzz,{BCD3,BCD2,BCD1,BCD0}); 
*/
	reg [3:0] BCD3r;
	reg [3:0] BCD2r;
	reg [3:0] BCD1r;
	reg [3:0] BCD0r;

	assign BCD3out=~lampoff & BCD3r;
	assign BCD2out=~lampoff & BCD2r;
	assign BCD1out=~lampoff & BCD1r;
	assign BCD0out=~lampoff & BCD0r;

	always @(fizz or buzz or BCD3 or BCD2 or BCD1 or BCD0) begin
		if (fizz==1)
			if (buzz==1) begin
				BCD3r=4'hf; // F
				BCD2r=4'ha; // z
				BCD1r=4'hb; // B
				BCD0r=4'ha; // z
			end
			else begin
				BCD3r=4'hf; // F
				BCD2r=4'hc; // i
				BCD1r=4'ha; // z
				BCD0r=4'ha; // z
			end
		else if (buzz==1) begin
			BCD3r=4'hb; // B
			BCD2r=4'hd; // u
			BCD1r=4'ha; // z
			BCD0r=4'ha; // z
		end
		else begin
			BCD3r=BCD3;
			BCD2r=BCD2;
			BCD1r=BCD1;
			BCD0r=BCD0;
		end
	end

endmodule

cntb.v

// ()MAXCNT-1)bit freerun counter
//
module cntb(clk,rst, q);

  parameter cntb_MAXCNT=15; // default 15:0
	input clk;
	input rst;
	output [cntb_MAXCNT:0] q;
	reg [cntb_MAXCNT:0] cnt;
 
	assign q=cnt;

	always @(posedge clk or posedge rst) begin
		if (rst==1'b1)
			cnt<=0;
		else
			cnt<=cnt+1;
	end
 endmodule

cntbcd.v

// BCD counter
//
// data[3:0]=0~9 only
//
module cntbcd(clk,rst,en,set,data, q,carry);

  input clk;
	input rst;
	input en;
	input set;
	input [3:0] data;
	output [3:0] q;
	output carry;

	reg [3:0] cnt;
 
	assign q=cnt;

	// assign carry=(q==9)?en:0; // 9
	assign carry=q[3]& ~q[2] & ~q[1] & q[0] & en;
	
	always @(posedge clk or posedge rst) begin
		if (rst==1'b1)
			cnt<=0;
		else if (set==1'b1)
			cnt<=data;
			else if (carry==1'b1) // 9 & en=1
				cnt<=0;
				else if (en==1'b1)
					cnt<=cnt+1;
	end
 endmodule

count3.v

//
module count3(clk,rst, zout);
  input clk;
	input rst;
	output zout;
	
	reg [1:0] cnt;

	assign zout=~(|cnt); // r[1:0]==2'b00 

	
	always @(posedge clk or posedge rst) begin
		if (rst==1'b1)
			cnt<=0;
		else if (cnt==2'd2)
				cnt<=0;
			else
				cnt<=cnt+1;
	end
 endmodule

count5.v

//
module count5(clk,rst, zout);
  input clk;
	input rst;
	output zout;
	
	reg [2:0] cnt;

	assign zout=~(|cnt); // r[1:0]==2'b00 

	
	always @(posedge clk or posedge rst) begin
		if (rst==1'b1)
			cnt<=0;
		else if (cnt==3'd4)
				cnt<=0;
			else
				cnt<=cnt+1;
	end
 endmodule

fizzbuzz.v

// terasIC DE0 topmodule skeleton
// onboard I/O 3-button,10-sw,10-LED,4-7SEG
//
module fizzbuzz(clk,btn,sw,led,hled0,hled1,hled2,hled3,lcd_bl);
  input clk;
	input [2:0] btn;
	input [9:0] sw;
	output [9:0] led;
	output [7:0] hled0;
	output [7:0] hled1;
	output [7:0] hled2;
	output [7:0] hled3;
	output lcd_bl;

	wire rst;
	wire [47:0] cnt;
	wire [2:0] s_btn;
	wire [9:0] s_sw;
	wire bout3_2,bout2_1,bout1_0,bout0_0;
	wire clk_ms;
	wire [14:0] dmy;
	wire [39:16] tap;
	
	wire bcdclk;
	wire en;
	
	wire swset;
	wire [3:0] bcdc0;
	wire [3:0] bcdc1;
	wire [3:0] bcdc2;
	wire [3:0] bcdc3;
	wire cu0_1,cu1_2,cu2_3,cu3_4;
	wire cu01_2,cu012_3;
	
	wire [3:0] bcdfz0;
	wire [3:0] bcdfz1;
	wire [3:0] bcdfz2;
	wire [3:0] bcdfz3;
	wire alldp;
	wire lampoff;
	wire fizz,buzz;
	
	cntb #(39) freerun(clk,1'b0,{tap[39:16],clk_ms,dmy[14:0]});
 
 	assign bcdclk=tap[23];
	assign en=1'b1; 
	assign swset=1'b0;
	assign alldp=lampoff;
	
	count3 count3_0(bcdclk,rst,fizz);
	count5 count5_0(bcdclk,rst,buzz);
 
	cntbcd bcd0(bcdclk,rst,en,swset,s_sw[3:0],bcdc0,cu0_1);
	cntbcd bcd1(bcdclk,rst,cu0_1,swset,s_sw[7:4],bcdc1,cu1_2);
	cntbcd bcd2(bcdclk,rst,cu1_2,swset,{2'b00,s_sw[9:8]},bcdc2,cu2_3);
	cntbcd bcd3(bcdclk,rst,cu2_3,swset,{4'b0000},bcdc3,cu3_4);

	bcdall0 bcdall0_0(bcdc3,bcdc2,bcdc1,bcdc0,lampoff);
	bcdtofzbz bcdtofzbz0(bcdc3,bcdc2,bcdc1,bcdc0,fizz,buzz,lampoff,bcdfz3,bcdfz2,bcdfz1,bcdfz0);
	
	segleddec seg0(bcdfz0,alldp,lampoff,1'b0, hled0,bout0_0);
	segleddec seg1(bcdfz1,alldp,lampoff,bout2_1, hled1,bout1_0);
	segleddec seg2(bcdfz2,alldp,lampoff,bout3_2, hled2,bout2_1);
	segleddec seg3(bcdfz3,alldp,lampoff,1'b1, hled3,bout3_2);

	unchat #(10) unchat_sw(clk_ms,sw[9:0],s_sw[9:0]);
	unchat #(3) unchat_btn(clk_ms,btn[2:0],s_btn[2:0]);
	
	assign rst=~s_btn[0];
	// assign fizz=~s_btn[1];
	// assign buzz=~s_btn[2];
	
	// assign led[9:0]=cnt[31:(31-9)];
	assign led[9:0]=s_sw[9:0];
	
endmodule

segleddec.v

// 7segment LED decoder(anode common)
// support zero suppress
//

`define segleddec_out0 7'b1000000
`define segleddec_out1 7'b1111001
`define segleddec_out2 7'b0100100
`define segleddec_out3 7'b0110000
`define segleddec_out4 7'b0011001
`define segleddec_out5 7'b0010010
`define segleddec_out6 7'b0000010
`define segleddec_out7 7'b1111000
`define segleddec_out8 7'b0000000
`define segleddec_out9 7'b0010000
// ZBiu-F
`define segleddec_outA 7'b1100100
`define segleddec_outB 7'b0000011
`define segleddec_outC 7'b1111011
`define segleddec_outD 7'b1100011
`define segleddec_outE 7'b0111111
`define segleddec_outF 7'b0001110

/* original A-F
`define segleddec_outA 7'b0001000
`define segleddec_outB 7'b0000011
`define segleddec_outC 7'b0100111
`define segleddec_outD 7'b0100001
`define segleddec_outE 7'b0000110
`define segleddec_outF 7'b0001110
*/

module segleddec(bcd,dp,off,bin, led,bout);
  input [3:0] bcd;
	input dp;	// decimal point
	input off;	// display off
	input bin;
	output [7:0] led;
	output bout;
	
	// assign bout=(bcd==4'b0000)?bin:0;
	assign bout=(~(|bcd))&bin;
	
	assign led=(bout&bin)?8'b11111111:ALED(bcd,dp,off);
	
	function [7:0] ALED;
		input [3:0] bcd;
		input dp;
		input off;
		case({off,bcd})
			5'h0:	ALED={ ~dp, `segleddec_out0 }; // 0
			5'h1:	ALED={ ~dp, `segleddec_out1 }; // 1
			5'h2:	ALED={ ~dp, `segleddec_out2 }; // 2
			5'h3:	ALED={ ~dp, `segleddec_out3 }; // 3
			5'h4:	ALED={ ~dp, `segleddec_out4 }; // 4
			5'h5:	ALED={ ~dp, `segleddec_out5 }; // 5
			5'h6:	ALED={ ~dp, `segleddec_out6 }; // 6
			5'h7:	ALED={ ~dp, `segleddec_out7 }; // 7
			5'h8:	ALED={ ~dp, `segleddec_out8 }; // 8
			5'h9:	ALED={ ~dp, `segleddec_out9 }; // 9
			5'ha:	ALED={ ~dp, `segleddec_outA }; // A
			5'hb:	ALED={ ~dp, `segleddec_outB }; // B
			5'hc:	ALED={ ~dp, `segleddec_outC }; // C
			5'hd:	ALED={ ~dp, `segleddec_outD }; // D
			5'he:	ALED={ ~dp, `segleddec_outE }; // E
			5'hf:	ALED={ ~dp, `segleddec_outF }; // F
			default:	ALED={ 1'b1, 7'b1111111 }; // off
	endcase
	endfunction
endmodule

unchat

// un-chattering
//
module unchat(c_clk,inkey, s_key);

  parameter unchat_MAX=0; // default 0
	input c_clk;	// 1-30ms
	input [unchat_MAX:0] inkey;
	output [unchat_MAX:0] s_key;
	
	reg [unchat_MAX:0] hold;
	assign s_key=hold;
	
	always @(posedge c_clk) begin
		hold=inkey;
	end
endmodule