ADDRDEC + RAM WE,OE / Fenestra6502

ADDR22.jed


CUPL(WM)        5.0a  Serial# 60008009
Device          g22v10  Library DLIB-h-40-1
Created         Thu Oct 15 00:43:15 2020
Name            ADDR22
Partno          Fenestra6502
Revision        01
Date            20/10/15
Designer        Katunori Takesita
Company         
Assembly        
Location        
*QP24 
*QF5892 
*G0 
*F0 
*L00032 00000000000011111111111111111111
*L00064 11111111111111111111111110111111
*L00096 11111111111111111111111111111111
*L00128 11110000000000000000000000000000
*L00416 00000000000000000000000011111111
*L00448 11111111111111111111111111111111
*L00480 11111111111111011111111111111111
*L00512 11111111111111011111111111101111
*L00544 11111111111111111111011111110000
*L00896 00000000000000000000000000001111
*L00928 11111111111111111111111111111111
*L00960 11111111111110111011101110111011
*L00992 10111011101110111111111110111011
*L01024 10111011101110111011101101111011
*L01472 00000000000000000000000011111111
*L01504 11111111111111111111111111111111
*L01536 11111101111111111111111111111111
*L01568 11111101110111111111111111111111
*L01600 11111111110111111101111111110000
*L02144 00000000000011111111111111111111
*L02176 11111111111111111111111111011111
*L02208 11111111111111111111111111011110
*L02240 11111111111111111111111111111111
*L02272 11011110111111110000000000000000
*L05792 00000000000000001111110101000101
*L05824 01010100011001100101011011100110
*L05856 01010111001101110100011100100110
*L05888 0001
*C4F16
*254C

ADDR22.PLD

Name        ADDR22;
PartNo      Fenestra6502;
Revision    01;
Date        20/10/15;
Designer    Katunori Takesita;
Company     ;
Assembly    ;
Location    ;
Device      G22V10;

/* INPUTS */
Pin 1 = CLK;
Pin [2..11] = [A15..6];
Pin 13 = BA7;
Pin 14 = RWB;
Pin 15 = BE;
Pin 16 = WR;
Pin 17 = RD;

/* OUTPUTS */
Pin 23 = E;
Pin 22 = RA7;
Pin 21 = SEL;
Pin 20 = !OE;
Pin 19 = !WE;

$DEFINE A00 (!A15 & !A14 & !A13 & !A12 & !A11 & !A10 & !A9 & !A8)
/* $DEFINE A00_0 ((A00 & !A7 & !A6)) */
/* $DEFINE A00_1 ((A00 & !A7 & A6)) */
/* $DEFINE A00_2 ((A00 & A7 & !A6)) */

SEL = (A00 & !A7 & !A6) # (A00 & !A7 & A6) # (A00 & A7 & !A6);
RA7 = SEL & BA7 # !SEL & A7;

E = !CLK;
OE = ((BE & E & RWB) # (BE & RD));
WE = ((BE & E & !RWB) # (!BE & WR));

ADDR22.sim

%SIGNAL
PIN  11 =  A6 
PIN  10 =  A7 
PIN   9 =  A8 
PIN   8 =  A9 
PIN   7 =  A10 
PIN   6 =  A11 
PIN   5 =  A12 
PIN   4 =  A13 
PIN   3 =  A14 
PIN   2 =  A15 
PIN  13 =  BA7 
PIN  15 =  BE 
PIN   1 =  CLK 
PIN  23 =  E 
PIN  20 = !OE 
PIN  22 =  RA7 
PIN  17 =  RD 
PIN  14 =  RWB 
PIN  21 =  SEL 
PIN  19 = !WE 
PIN  16 =  WR 
%END

%FIELD
%END

%EQUATION
E =>
    !CLK

OE =>
    BE & E & RWB
  # BE & RD

RA7 =>
    BA7 & SEL
  # A7 & !SEL

SEL =>
    !A7 & !A8 & !A9 & !A10 & !A11 & !A12 & !A13 & !A14 & !A15
  # !A6 & A7 & !A8 & !A9 & !A10 & !A11 & !A12 & !A13 & !A14 & !A15

WE =>
    BE & E & !RWB
  # !BE & WR

BE.oe  =>
    0 

E.oe  =>
    1 

OE.oe  =>
    1 

RA7.oe  =>
    1 

RD.oe  =>
    0 

RWB.oe  =>
    0 

SEL.oe  =>
    1 

WE.oe  =>
    1 

WR.oe  =>
    0 

%END