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Created September 22, 2019 18:56
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log
****** START compiling Test2:DoTest(int,int,ubyte):int (MethodHash=8bafdb7c)
Generating code for Windows x64
OPTIONS: compCodeOpt = BLENDED_CODE
OPTIONS: compDbgCode = false
OPTIONS: compDbgInfo = true
OPTIONS: compDbgEnC = false
OPTIONS: compProcedureSplitting = false
OPTIONS: compProcedureSplittingEH = false
IL to import:
IL_0000 02 ldarg.0
IL_0001 03 ldarg.1
IL_0002 04 ldarg.2
IL_0003 28 0a 00 00 2b call 0x2B00000A
IL_0008 02 ldarg.0
IL_0009 03 ldarg.1
IL_000a 04 ldarg.2
IL_000b 28 0b 00 00 2b call 0x2B00000B
IL_0010 0a stloc.0
IL_0011 12 05 ldloca.s 0x5
IL_0013 fe 15 07 00 00 02 initobj 0x2000007
IL_0019 11 05 ldloc.s 0x5
IL_001b 02 ldarg.0
IL_001c 03 ldarg.1
IL_001d 04 ldarg.2
IL_001e 28 0c 00 00 2b call 0x2B00000C
IL_0023 0b stloc.1
IL_0024 73 0d 00 00 06 newobj 0x600000D
IL_0029 02 ldarg.0
IL_002a 03 ldarg.1
IL_002b 04 ldarg.2
IL_002c 28 0d 00 00 2b call 0x2B00000D
IL_0031 0c stloc.2
IL_0032 02 ldarg.0
IL_0033 03 ldarg.1
IL_0034 04 ldarg.2
IL_0035 28 0e 00 00 2b call 0x2B00000E
IL_003a 0d stloc.3
IL_003b 02 ldarg.0
IL_003c 03 ldarg.1
IL_003d 04 ldarg.2
IL_003e 28 0f 00 00 2b call 0x2B00000F
IL_0043 13 04 stloc.s 0x4
IL_0045 06 ldloc.0
IL_0046 58 add
IL_0047 07 ldloc.1
IL_0048 58 add
IL_0049 08 ldloc.2
IL_004a 58 add
IL_004b 09 ldloc.3
IL_004c 58 add
IL_004d 11 04 ldloc.s 0x4
IL_004f 58 add
IL_0050 2a ret
Arg #0 passed in register(s) rcx
Arg #1 passed in register(s) rdx
Arg #2 passed in register(s) r8
lvaGrabTemp returning 9 (V09 tmp0) (a long lifetime temp) called for OutgoingArgSpace.
; Initial local variable assignments
;
; V00 arg0 int
; V01 arg1 int
; V02 arg2 ubyte
; V03 loc0 int
; V04 loc1 int
; V05 loc2 int
; V06 loc3 int
; V07 loc4 int
; V08 loc5 struct ( 8)
; V09 OutArgs lclBlk (na) "OutgoingArgSpace"
*************** In compInitDebuggingInfo() for Test2:DoTest(int,int,ubyte):int
getVars() returned cVars = 0, extendOthers = true
info.compVarScopesCount = 9
VarNum LVNum Name Beg End
0: 00h 00h V00 arg0 000h 051h
1: 01h 01h V01 arg1 000h 051h
2: 02h 02h V02 arg2 000h 051h
3: 03h 03h V03 loc0 000h 051h
4: 04h 04h V04 loc1 000h 051h
5: 05h 05h V05 loc2 000h 051h
6: 06h 06h V06 loc3 000h 051h
7: 07h 07h V07 loc4 000h 051h
8: 08h 08h V08 loc5 000h 051h
info.compStmtOffsetsCount = 0
info.compStmtOffsetsImplicit = 0005h ( STACK_EMPTY CALL_SITE )
*************** In fgFindBasicBlocks() for Test2:DoTest(int,int,ubyte):int
Marked V03 as a single def local
Marked V04 as a single def local
Marked V05 as a single def local
Marked V06 as a single def local
Marked V07 as a single def local
Jump targets:
none
New Basic Block BB01 [0000] created.
BB01 [000..051)
IL Code Size,Instr 81, 44, Basic Block count 1, Local Variable Num,Ref count 10, 30 for method Test2:DoTest(int,int,ubyte):int
OPTIONS: opts.MinOpts() == false
Basic block list for 'Test2:DoTest(int,int,ubyte):int'
-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..051) (return)
-----------------------------------------------------------------------------------------------------------------------------------------
*************** In impImport() for Test2:DoTest(int,int,ubyte):int
impImportBlockPending for BB01
Importing BB01 (PC=000) of 'Test2:DoTest(int,int,ubyte):int'
[ 0] 0 (0x000) ldarg.0
[ 1] 1 (0x001) ldarg.1
[ 2] 2 (0x002) ldarg.2
[ 3] 3 (0x003) call 2B00000A
In Compiler::impImportCall: opcode is call, kind=0, callRetType is int, structSize is 0
STMT00000 (IL 0x000... ???)
[000003] I-C-G------- * CALL int Test2.DoTestImpl1 (exactContextHnd=0x00000000D1FFAB1E)
[000000] ------------ arg0 +--* LCL_VAR int V00 arg0
[000001] ------------ arg1 +--* LCL_VAR int V01 arg1
[000002] ------------ arg2 \--* LCL_VAR ubyte V02 arg2
[ 1] 8 (0x008) ldarg.0
[ 2] 9 (0x009) ldarg.1
[ 3] 10 (0x00a) ldarg.2
[ 4] 11 (0x00b) call 2B00000B
In Compiler::impImportCall: opcode is call, kind=0, callRetType is int, structSize is 0
lvaGrabTemp returning 10 (V10 tmp1) called for impAppendStmt.
STMT00002 (IL ???... ???)
[000011] -AC--------- * ASG int
[000010] D------N---- +--* LCL_VAR int V10 tmp1
[000004] --C--------- \--* RET_EXPR int (inl return from call [000003])
STMT00001 (IL ???... ???)
[000008] I-C-G------- * CALL int Test2.DoTestImpl2 (exactContextHnd=0x00000000D1FFAB1E)
[000009] ------------ arg0 +--* CNS_INT(h) long 0xd1ffab1e method
[000005] ------------ arg1 +--* LCL_VAR int V00 arg0
[000006] ------------ arg2 +--* LCL_VAR int V01 arg1
[000007] ------------ arg3 \--* LCL_VAR ubyte V02 arg2
[ 2] 16 (0x010) stloc.0
STMT00003 (IL ???... ???)
[000015] -AC--------- * ASG int
[000014] D------N---- +--* LCL_VAR int V03 loc0
[000013] --C--------- \--* RET_EXPR int (inl return from call [000008])
[ 1] 17 (0x011) ldloca.s 5
[ 2] 19 (0x013) initobj 02000007
STMT00004 (IL ???... ???)
[000019] IA---------- * ASG struct (init)
[000016] D------N---- +--* LCL_VAR struct V08 loc5
[000018] ------------ \--* CNS_INT int 0
[ 1] 25 (0x019) ldloc.s 5
[ 2] 27 (0x01b) ldarg.0
[ 3] 28 (0x01c) ldarg.1
[ 4] 29 (0x01d) ldarg.2
[ 5] 30 (0x01e) call 2B00000C
In Compiler::impImportCall: opcode is call, kind=0, callRetType is int, structSize is 0
Calling impNormStructVal on:
[000020] ------------ * LCL_VAR struct V08 loc5
resulting tree:
[000026] n----------- * OBJ(1) struct
[000025] ------------ \--* ADDR byref
[000020] ------------ \--* LCL_VAR struct V08 loc5
STMT00005 (IL ???... ???)
[000024] I-C-G------- * CALL int Test2.DoTestImpl3 (exactContextHnd=0x00000000D1FFAB1E)
[000026] n----------- arg0 +--* OBJ(1) struct
[000025] ------------ | \--* ADDR byref
[000020] ------------ | \--* LCL_VAR struct V08 loc5
[000021] ------------ arg1 +--* LCL_VAR int V00 arg0
[000022] ------------ arg2 +--* LCL_VAR int V01 arg1
[000023] ------------ arg3 \--* LCL_VAR ubyte V02 arg2
[ 2] 35 (0x023) stloc.1
STMT00006 (IL ???... ???)
[000029] -AC--------- * ASG int
[000028] D------N---- +--* LCL_VAR int V04 loc1
[000027] --C--------- \--* RET_EXPR int (inl return from call [000024])
[ 1] 36 (0x024) newobj
lvaGrabTemp returning 11 (V11 tmp2) called for NewObj constructor temp.
STMT00007 (IL ???... ???)
[000033] -A---------- * ASG ref
[000032] D------N---- +--* LCL_VAR ref V11 tmp2
[000031] ------------ \--* ALLOCOBJ ref
[000030] ------------ \--* CNS_INT(h) long 0xd1ffab1e method
Marked V11 as a single def local
lvaSetClass: setting class for V11 to (00000000D1FFAB1E) CalculatorClass [exact]
0600000D
In Compiler::impImportCall: opcode is newobj, kind=0, callRetType is void, structSize is 0
STMT00008 (IL ???... ???)
[000035] I-C-G------- * CALL void CalculatorClass..ctor (exactContextHnd=0x00000000D1FFAB1E)
[000034] ------------ this in rcx \--* LCL_VAR ref V11 tmp2
[ 2] 41 (0x029) ldarg.0
[ 3] 42 (0x02a) ldarg.1
[ 4] 43 (0x02b) ldarg.2
[ 5] 44 (0x02c) call 2B00000D
In Compiler::impImportCall: opcode is call, kind=0, callRetType is int, structSize is 0
STMT00009 (IL 0x029... ???)
[000040] I-C-G------- * CALL int Test2.DoTestImpl4 (exactContextHnd=0x00000000D1FFAB1E)
[000041] ------------ arg0 +--* CNS_INT(h) long 0xd1ffab1e method
[000036] ------------ arg1 +--* LCL_VAR ref V11 tmp2
[000037] ------------ arg2 +--* LCL_VAR int V00 arg0
[000038] ------------ arg3 +--* LCL_VAR int V01 arg1
[000039] ------------ arg4 \--* LCL_VAR ubyte V02 arg2
[ 2] 49 (0x031) stloc.2
STMT00010 (IL ???... ???)
[000044] -AC--------- * ASG int
[000043] D------N---- +--* LCL_VAR int V05 loc2
[000042] --C--------- \--* RET_EXPR int (inl return from call [000040])
[ 1] 50 (0x032) ldarg.0
[ 2] 51 (0x033) ldarg.1
[ 3] 52 (0x034) ldarg.2
[ 4] 53 (0x035) call 2B00000E
In Compiler::impImportCall: opcode is call, kind=0, callRetType is int, structSize is 0
STMT00011 (IL ???... ???)
[000048] I-C-G------- * CALL int Test2.DoTestImpl5 (exactContextHnd=0x00000000D1FFAB1E)
[000045] ------------ arg0 +--* LCL_VAR int V00 arg0
[000046] ------------ arg1 +--* LCL_VAR int V01 arg1
[000047] ------------ arg2 \--* LCL_VAR ubyte V02 arg2
[ 2] 58 (0x03a) stloc.3
STMT00012 (IL ???... ???)
[000051] -AC--------- * ASG int
[000050] D------N---- +--* LCL_VAR int V06 loc3
[000049] --C--------- \--* RET_EXPR int (inl return from call [000048])
[ 1] 59 (0x03b) ldarg.0
[ 2] 60 (0x03c) ldarg.1
[ 3] 61 (0x03d) ldarg.2
[ 4] 62 (0x03e) call 2B00000F
In Compiler::impImportCall: opcode is call, kind=0, callRetType is int, structSize is 0
STMT00013 (IL ???... ???)
[000055] I-C-G------- * CALL int Test2.DoTestImpl6 (exactContextHnd=0x00000000D1FFAB1E)
[000052] ------------ arg0 +--* LCL_VAR int V00 arg0
[000053] ------------ arg1 +--* LCL_VAR int V01 arg1
[000054] ------------ arg2 \--* LCL_VAR ubyte V02 arg2
[ 2] 67 (0x043) stloc.s 4
STMT00014 (IL ???... ???)
[000058] -AC--------- * ASG int
[000057] D------N---- +--* LCL_VAR int V07 loc4
[000056] --C--------- \--* RET_EXPR int (inl return from call [000055])
[ 1] 69 (0x045) ldloc.0
[ 2] 70 (0x046) add
[ 1] 71 (0x047) ldloc.1
[ 2] 72 (0x048) add
[ 1] 73 (0x049) ldloc.2
[ 2] 74 (0x04a) add
[ 1] 75 (0x04b) ldloc.3
[ 2] 76 (0x04c) add
[ 1] 77 (0x04d) ldloc.s 4
[ 2] 79 (0x04f) add
[ 1] 80 (0x050) ret
STMT00015 (IL ???... ???)
[000069] ------------ * RETURN int
[000068] ------------ \--* ADD int
[000066] ------------ +--* ADD int
[000064] ------------ | +--* ADD int
[000062] ------------ | | +--* ADD int
[000060] ------------ | | | +--* ADD int
[000012] ------------ | | | | +--* LCL_VAR int V10 tmp1
[000059] ------------ | | | | \--* LCL_VAR int V03 loc0
[000061] ------------ | | | \--* LCL_VAR int V04 loc1
[000063] ------------ | | \--* LCL_VAR int V05 loc2
[000065] ------------ | \--* LCL_VAR int V06 loc3
[000067] ------------ \--* LCL_VAR int V07 loc4
*************** in fgTransformIndirectCalls(root)
-- no candidates to transform
New BlockSet epoch 1, # of blocks (including unused BB00): 2, bitset array size: 1 (short)
*************** In fgMorph()
*************** In fgDebugCheckBBlist
*************** In fgInline()
Expanding INLINE_CANDIDATE in statement STMT00000 in BB01:
STMT00000 (IL 0x000...0x010)
[000003] I-C-G------- * CALL int Test2.DoTestImpl1 (exactContextHnd=0x00000000D1FFAB1E)
[000000] ------------ arg0 +--* LCL_VAR int V00 arg0
[000001] ------------ arg1 +--* LCL_VAR int V01 arg1
[000002] ------------ arg2 \--* LCL_VAR ubyte V02 arg2
Argument #0: is a local var
[000000] ------------ * LCL_VAR int V00 arg0
Argument #1: is a local var
[000001] ------------ * LCL_VAR int V01 arg1
Argument #2: is a local var
[000002] ------------ * LCL_VAR ubyte V02 arg2
INLINER: inlineInfo.tokenLookupContextHandle for Test2:DoTestImpl1(int,int,ubyte):int set to 0x00000000D1FFAB1E:
Invoking compiler for the inlinee method Test2:DoTestImpl1(int,int,ubyte):int :
IL to import:
IL_0000 12 00 ldloca.s 0x0
IL_0002 fe 15 06 00 00 1b initobj 0x1B000006
IL_0008 12 00 ldloca.s 0x0
IL_000a 02 ldarg.0
IL_000b 03 ldarg.1
IL_000c 04 ldarg.2
IL_000d fe 16 06 00 00 1b constrained. 0x1B000006
IL_0013 6f 10 00 00 2b callvirt 0x2B000010
IL_0018 2a ret
INLINER impTokenLookupContextHandle for Test2:DoTestImpl1(int,int,ubyte):int is 0x00000000D1FFAB1E.
*************** In fgFindBasicBlocks() for Test2:DoTestImpl1(int,int,ubyte):int
Jump targets:
none
New Basic Block BB02 [0001] created.
BB02 [000..019)
Basic block list for 'Test2:DoTestImpl1(int,int,ubyte):int'
-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB02 [0001] 1 1 [000..019) (return)
-----------------------------------------------------------------------------------------------------------------------------------------
*************** In impImport() for Test2:DoTestImpl1(int,int,ubyte):int
impImportBlockPending for BB02
Importing BB02 (PC=000) of 'Test2:DoTestImpl1(int,int,ubyte):int'
[ 0] 0 (0x000) ldloca.s 0
lvaGrabTemp returning 12 (V12 tmp3) (a long lifetime temp) called for Inline ldloca(s) first use temp.
[ 1] 2 (0x002) initobj 1B000006
[000073] IA---------- * ASG struct (init)
[000070] D------N---- +--* LCL_VAR struct V12 tmp3
[000072] ------------ \--* CNS_INT int 0
[ 0] 8 (0x008) ldloca.s 0
[ 1] 10 (0x00a) ldarg.0
[ 2] 11 (0x00b) ldarg.1
[ 3] 12 (0x00c) ldarg.2
[ 4] 13 (0x00d) constrained. (1B000006) callvirt 2B000010
In Compiler::impImportCall: opcode is callvirt, kind=0, callRetType is int, structSize is 0
** Note: inlinee IL was partially imported -- imported 0 of 25 bytes of method IL
*************** in fgTransformIndirectCalls(inlinee)
-- no candidates to transform
Inlining [000003] failed, so bashing STMT00000 to NOP
INLINER: during 'fgInline' result 'failed this callee' reason 'generic virtual' for 'Test2:DoTest(int,int,ubyte):int' calling 'Test2:DoTestImpl1(int,int,ubyte):int'
INLINER: Marking Test2:DoTestImpl1(int,int,ubyte):int as NOINLINE because of generic virtual
INLINER: during 'fgInline' result 'failed this callee' reason 'generic virtual'
Replacing the return expression placeholder [000004] with [000003]
[000004] --C--------- * RET_EXPR int (inl return from call [000003])
Inserting the inline return expression
[000003] --C-G------- * CALL int Test2.DoTestImpl1
[000000] ------------ arg0 +--* LCL_VAR int V00 arg0
[000001] ------------ arg1 +--* LCL_VAR int V01 arg1
[000002] ------------ arg2 \--* LCL_VAR ubyte V02 arg2
Expanding INLINE_CANDIDATE in statement STMT00001 in BB01:
STMT00001 (IL ???... ???)
[000008] I-C-G------- * CALL int Test2.DoTestImpl2 (exactContextHnd=0x00000000D1FFAB1E)
[000009] ------------ arg0 +--* CNS_INT(h) long 0xd1ffab1e method
[000005] ------------ arg1 +--* LCL_VAR int V00 arg0
[000006] ------------ arg2 +--* LCL_VAR int V01 arg1
[000007] ------------ arg3 \--* LCL_VAR ubyte V02 arg2
Argument #0: is a local var
[000005] ------------ * LCL_VAR int V00 arg0
Argument #1: is a local var
[000006] ------------ * LCL_VAR int V01 arg1
Argument #2: is a local var
[000007] ------------ * LCL_VAR ubyte V02 arg2
INLINER: inlineInfo.tokenLookupContextHandle for Test2:DoTestImpl2(int,int,ubyte):int set to 0x00000000D1FFAB1E:
Invoking compiler for the inlinee method Test2:DoTestImpl2(int,int,ubyte):int :
IL to import:
IL_0000 28 11 00 00 2b call 0x2B000011
IL_0005 8c 06 00 00 1b box 0x1B000006
IL_000a 02 ldarg.0
IL_000b 03 ldarg.1
IL_000c 04 ldarg.2
IL_000d 6f 12 00 00 2b callvirt 0x2B000012
IL_0012 2a ret
INLINER impTokenLookupContextHandle for Test2:DoTestImpl2(int,int,ubyte):int is 0x00000000D1FFAB1E.
*************** In fgFindBasicBlocks() for Test2:DoTestImpl2(int,int,ubyte):int
Jump targets:
none
New Basic Block BB03 [0002] created.
BB03 [000..013)
Basic block list for 'Test2:DoTestImpl2(int,int,ubyte):int'
-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB03 [0002] 1 1 [000..013) (return)
-----------------------------------------------------------------------------------------------------------------------------------------
*************** In impImport() for Test2:DoTestImpl2(int,int,ubyte):int
impImportBlockPending for BB03
Importing BB03 (PC=000) of 'Test2:DoTestImpl2(int,int,ubyte):int'
[ 0] 0 (0x000) call 2B000011
In Compiler::impImportCall: opcode is call, kind=0, callRetType is ref, structSize is 0
Named Intrinsic System.ActivatorCreateInstance: Not recognized
[000077] I-C-G------- * CALL ref Activator.CreateInstance (exactContextHnd=0x00000000D1FFAB1E)
[000078] ------------ arg0 \--* CNS_INT(h) long 0xd1ffab1e method
[ 1] 5 (0x005) box 1B000006
Importing BOX(refClass) as NOP
[ 1] 10 (0x00a) ldarg.0
[ 2] 11 (0x00b) ldarg.1
[ 3] 12 (0x00c) ldarg.2
[ 4] 13 (0x00d) callvirt 2B000012
In Compiler::impImportCall: opcode is callvirt, kind=3, callRetType is int, structSize is 0
** Note: inlinee IL was partially imported -- imported 0 of 19 bytes of method IL
*************** in fgTransformIndirectCalls(inlinee)
-- no candidates to transform
Inlining [000008] failed, so bashing STMT00001 to NOP
INLINER: during 'fgInline' result 'failed this callee' reason 'generic virtual' for 'Test2:DoTest(int,int,ubyte):int' calling 'Test2:DoTestImpl2(int,int,ubyte):int'
INLINER: Marking Test2:DoTestImpl2(int,int,ubyte):int as NOINLINE because of generic virtual
INLINER: during 'fgInline' result 'failed this callee' reason 'generic virtual'
Replacing the return expression placeholder [000013] with [000008]
[000013] --C--------- * RET_EXPR int (inl return from call [000008])
Inserting the inline return expression
[000008] --C-G------- * CALL int Test2.DoTestImpl2
[000009] ------------ arg0 +--* CNS_INT(h) long 0xd1ffab1e method
[000005] ------------ arg1 +--* LCL_VAR int V00 arg0
[000006] ------------ arg2 +--* LCL_VAR int V01 arg1
[000007] ------------ arg3 \--* LCL_VAR ubyte V02 arg2
Expanding INLINE_CANDIDATE in statement STMT00005 in BB01:
STMT00005 (IL ???...0x023)
[000024] I-C-G------- * CALL int Test2.DoTestImpl3 (exactContextHnd=0x00000000D1FFAB1E)
[000026] n----------- arg0 +--* OBJ(1) struct
[000025] ------------ | \--* ADDR byref
[000020] ------------ | \--* LCL_VAR struct V08 loc5
[000021] ------------ arg1 +--* LCL_VAR int V00 arg0
[000022] ------------ arg2 +--* LCL_VAR int V01 arg1
[000023] ------------ arg3 \--* LCL_VAR ubyte V02 arg2
Argument #0: has caller local ref
[000026] n----------- * OBJ(1) struct
[000025] ------------ \--* ADDR byref
[000020] ------------ \--* LCL_VAR struct V08 loc5
Argument #1: is a local var
[000021] ------------ * LCL_VAR int V00 arg0
Argument #2: is a local var
[000022] ------------ * LCL_VAR int V01 arg1
Argument #3: is a local var
[000023] ------------ * LCL_VAR ubyte V02 arg2
INLINER: inlineInfo.tokenLookupContextHandle for Test2:DoTestImpl3(struct,int,int,ubyte):int set to 0x00000000D1FFAB1E:
Invoking compiler for the inlinee method Test2:DoTestImpl3(struct,int,int,ubyte):int :
IL to import:
IL_0000 0f 00 ldarga.s 0x0
IL_0002 03 ldarg.1
IL_0003 04 ldarg.2
IL_0004 05 ldarg.3
IL_0005 fe 16 06 00 00 1b constrained. 0x1B000006
IL_000b 6f 10 00 00 2b callvirt 0x2B000010
IL_0010 2a ret
INLINER impTokenLookupContextHandle for Test2:DoTestImpl3(struct,int,int,ubyte):int is 0x00000000D1FFAB1E.
*************** In fgFindBasicBlocks() for Test2:DoTestImpl3(struct,int,int,ubyte):int
Jump targets:
none
New Basic Block BB04 [0003] created.
BB04 [000..011)
Basic block list for 'Test2:DoTestImpl3(struct,int,int,ubyte):int'
-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB04 [0003] 1 1 [000..011) (return)
-----------------------------------------------------------------------------------------------------------------------------------------
*************** In impImport() for Test2:DoTestImpl3(struct,int,int,ubyte):int
impImportBlockPending for BB04
Importing BB04 (PC=000) of 'Test2:DoTestImpl3(struct,int,int,ubyte):int'
[ 0] 0 (0x000) ldarga.s 0
lvaGrabTemp returning 12 (V12 tmp3) called for Inlining Arg.
[ 1] 2 (0x002) ldarg.1
[ 2] 3 (0x003) ldarg.2
[ 3] 4 (0x004) ldarg.3
[ 4] 5 (0x005) constrained. (1B000006) callvirt 2B000010
In Compiler::impImportCall: opcode is callvirt, kind=0, callRetType is int, structSize is 0
** Note: inlinee IL was partially imported -- imported 0 of 17 bytes of method IL
*************** in fgTransformIndirectCalls(inlinee)
-- no candidates to transform
Inlining [000024] failed, so bashing STMT00005 to NOP
INLINER: during 'fgInline' result 'failed this callee' reason 'generic virtual' for 'Test2:DoTest(int,int,ubyte):int' calling 'Test2:DoTestImpl3(struct,int,int,ubyte):int'
INLINER: Marking Test2:DoTestImpl3(struct,int,int,ubyte):int as NOINLINE because of generic virtual
INLINER: during 'fgInline' result 'failed this callee' reason 'generic virtual'
Replacing the return expression placeholder [000027] with [000024]
[000027] --C--------- * RET_EXPR int (inl return from call [000024])
Inserting the inline return expression
[000024] --C-G------- * CALL int Test2.DoTestImpl3
[000026] n----------- arg0 +--* OBJ(1) struct
[000025] ------------ | \--* ADDR byref
[000020] ------------ | \--* LCL_VAR struct V08 loc5
[000021] ------------ arg1 +--* LCL_VAR int V00 arg0
[000022] ------------ arg2 +--* LCL_VAR int V01 arg1
[000023] ------------ arg3 \--* LCL_VAR ubyte V02 arg2
Expanding INLINE_CANDIDATE in statement STMT00008 in BB01:
STMT00008 (IL ???... ???)
[000035] I-C-G------- * CALL void CalculatorClass..ctor (exactContextHnd=0x00000000D1FFAB1E)
[000034] ------------ this in rcx \--* LCL_VAR ref V11 tmp2
thisArg: is a local var
[000034] ------------ * LCL_VAR ref V11 tmp2
INLINER: inlineInfo.tokenLookupContextHandle for CalculatorClass:.ctor():this set to 0x00000000D1FFAB1E:
Invoking compiler for the inlinee method CalculatorClass:.ctor():this :
IL to import:
IL_0000 02 ldarg.0
IL_0001 28 0b 00 00 06 call 0x600000B
IL_0006 2a ret
INLINER impTokenLookupContextHandle for CalculatorClass:.ctor():this is 0x00000000D1FFAB1E.
*************** In fgFindBasicBlocks() for CalculatorClass:.ctor():this
Jump targets:
none
New Basic Block BB05 [0004] created.
BB05 [000..007)
Basic block list for 'CalculatorClass:.ctor():this'
-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB05 [0004] 1 1 [000..007) (return)
-----------------------------------------------------------------------------------------------------------------------------------------
*************** In impImport() for CalculatorClass:.ctor():this
impImportBlockPending for BB05
Importing BB05 (PC=000) of 'CalculatorClass:.ctor():this'
[ 0] 0 (0x000) ldarg.0
[ 1] 1 (0x001) call 0600000B
In Compiler::impImportCall: opcode is call, kind=0, callRetType is void, structSize is 0
[000084] I-C-G------- * CALL void CalculatorBase..ctor (exactContextHnd=0x00000000D1FFAB1E)
[000034] ------------ this in rcx \--* LCL_VAR ref V11 tmp2
[ 0] 6 (0x006) ret
*************** in fgTransformIndirectCalls(inlinee)
-- no candidates to transform
----------- Statements (and blocks) added due to the inlining of call [000035] -----------
Arguments setup:
Inlinee method body:
STMT00018 (IL ???... ???)
[000084] I-C-G------- * CALL void CalculatorBase..ctor (exactContextHnd=0x00000000D1FFAB1E)
[000034] ------------ this in rcx \--* LCL_VAR ref V11 tmp2
fgInlineAppendStatements: no gc ref inline locals.
Successfully inlined CalculatorClass:.ctor():this (7 IL bytes) (depth 1) [below ALWAYS_INLINE size]
--------------------------------------------------------------------------------------------
INLINER: during 'fgInline' result 'success' reason 'below ALWAYS_INLINE size' for 'Test2:DoTest(int,int,ubyte):int' calling 'CalculatorClass:.ctor():this'
INLINER: during 'fgInline' result 'success' reason 'below ALWAYS_INLINE size'
Expanding INLINE_CANDIDATE in statement STMT00018 in BB01:
STMT00018 (IL ???... ???)
[000084] I-C-G------- * CALL void CalculatorBase..ctor (exactContextHnd=0x00000000D1FFAB1E)
[000034] ------------ this in rcx \--* LCL_VAR ref V11 tmp2
thisArg: is a local var
[000034] ------------ * LCL_VAR ref V11 tmp2
INLINER: inlineInfo.tokenLookupContextHandle for CalculatorBase:.ctor():this set to 0x00000000D1FFAB1E:
Invoking compiler for the inlinee method CalculatorBase:.ctor():this :
IL to import:
IL_0000 02 ldarg.0
IL_0001 28 1a 00 00 0a call 0xA00001A
IL_0006 2a ret
INLINER impTokenLookupContextHandle for CalculatorBase:.ctor():this is 0x00000000D1FFAB1E.
*************** In fgFindBasicBlocks() for CalculatorBase:.ctor():this
Jump targets:
none
New Basic Block BB06 [0005] created.
BB06 [000..007)
Basic block list for 'CalculatorBase:.ctor():this'
-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB06 [0005] 1 1 [000..007) (return)
-----------------------------------------------------------------------------------------------------------------------------------------
*************** In impImport() for CalculatorBase:.ctor():this
impImportBlockPending for BB06
Importing BB06 (PC=000) of 'CalculatorBase:.ctor():this'
[ 0] 0 (0x000) ldarg.0
[ 1] 1 (0x001) call 0A00001A
In Compiler::impImportCall: opcode is call, kind=0, callRetType is void, structSize is 0
[000086] I-C-G------- * CALL void Object..ctor (exactContextHnd=0x00000000D1FFAB1E)
[000034] ------------ this in rcx \--* LCL_VAR ref V11 tmp2
[ 0] 6 (0x006) ret
*************** in fgTransformIndirectCalls(inlinee)
-- no candidates to transform
----------- Statements (and blocks) added due to the inlining of call [000084] -----------
Arguments setup:
Inlinee method body:
STMT00019 (IL ???... ???)
[000086] I-C-G------- * CALL void Object..ctor (exactContextHnd=0x00000000D1FFAB1E)
[000034] ------------ this in rcx \--* LCL_VAR ref V11 tmp2
fgInlineAppendStatements: no gc ref inline locals.
Successfully inlined CalculatorBase:.ctor():this (7 IL bytes) (depth 2) [below ALWAYS_INLINE size]
--------------------------------------------------------------------------------------------
INLINER: during 'fgInline' result 'success' reason 'below ALWAYS_INLINE size' for 'Test2:DoTest(int,int,ubyte):int' calling 'CalculatorBase:.ctor():this'
INLINER: during 'fgInline' result 'success' reason 'below ALWAYS_INLINE size'
Expanding INLINE_CANDIDATE in statement STMT00019 in BB01:
STMT00019 (IL ???... ???)
[000086] I-C-G------- * CALL void Object..ctor (exactContextHnd=0x00000000D1FFAB1E)
[000034] ------------ this in rcx \--* LCL_VAR ref V11 tmp2
thisArg: is a local var
[000034] ------------ * LCL_VAR ref V11 tmp2
INLINER: inlineInfo.tokenLookupContextHandle for Object:.ctor():this set to 0x00000000D1FFAB1E:
Invoking compiler for the inlinee method Object:.ctor():this :
IL to import:
IL_0000 2a ret
INLINER impTokenLookupContextHandle for Object:.ctor():this is 0x00000000D1FFAB1E.
*************** In fgFindBasicBlocks() for Object:.ctor():this
Jump targets:
none
New Basic Block BB07 [0006] created.
BB07 [000..001)
Basic block list for 'Object:.ctor():this'
-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB07 [0006] 1 1 [000..001) (return)
-----------------------------------------------------------------------------------------------------------------------------------------
*************** In impImport() for Object:.ctor():this
impImportBlockPending for BB07
Importing BB07 (PC=000) of 'Object:.ctor():this'
[ 0] 0 (0x000) ret
** Note: inlinee IL was partially imported -- imported 0 of 1 bytes of method IL
*************** in fgTransformIndirectCalls(inlinee)
-- no candidates to transform
----------- Statements (and blocks) added due to the inlining of call [000086] -----------
Arguments setup:
Inlinee method body:fgInlineAppendStatements: no gc ref inline locals.
Successfully inlined Object:.ctor():this (1 IL bytes) (depth 3) [below ALWAYS_INLINE size]
--------------------------------------------------------------------------------------------
INLINER: during 'fgInline' result 'success' reason 'below ALWAYS_INLINE size' for 'Test2:DoTest(int,int,ubyte):int' calling 'Object:.ctor():this'
INLINER: during 'fgInline' result 'success' reason 'below ALWAYS_INLINE size'
Expanding INLINE_CANDIDATE in statement STMT00009 in BB01:
STMT00009 (IL 0x029... ???)
[000040] I-C-G------- * CALL int Test2.DoTestImpl4 (exactContextHnd=0x00000000D1FFAB1E)
[000041] ------------ arg0 +--* CNS_INT(h) long 0xd1ffab1e method
[000036] ------------ arg1 +--* LCL_VAR ref V11 tmp2
[000037] ------------ arg2 +--* LCL_VAR int V00 arg0
[000038] ------------ arg3 +--* LCL_VAR int V01 arg1
[000039] ------------ arg4 \--* LCL_VAR ubyte V02 arg2
Argument #0: is a local var
[000036] ------------ * LCL_VAR ref V11 tmp2
Argument #1: is a local var
[000037] ------------ * LCL_VAR int V00 arg0
Argument #2: is a local var
[000038] ------------ * LCL_VAR int V01 arg1
Argument #3: is a local var
[000039] ------------ * LCL_VAR ubyte V02 arg2
INLINER: inlineInfo.tokenLookupContextHandle for Test2:DoTestImpl4(ref,int,int,ubyte):int set to 0x00000000D1FFAB1E:
Invoking compiler for the inlinee method Test2:DoTestImpl4(ref,int,int,ubyte):int :
IL to import:
IL_0000 02 ldarg.0
IL_0001 8c 06 00 00 1b box 0x1B000006
IL_0006 03 ldarg.1
IL_0007 04 ldarg.2
IL_0008 05 ldarg.3
IL_0009 6f 12 00 00 2b callvirt 0x2B000012
IL_000e 2a ret
INLINER impTokenLookupContextHandle for Test2:DoTestImpl4(ref,int,int,ubyte):int is 0x00000000D1FFAB1E.
*************** In fgFindBasicBlocks() for Test2:DoTestImpl4(ref,int,int,ubyte):int
Jump targets:
none
New Basic Block BB08 [0007] created.
BB08 [000..00F)
Basic block list for 'Test2:DoTestImpl4(ref,int,int,ubyte):int'
-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB08 [0007] 1 1 [000..00F) (return)
-----------------------------------------------------------------------------------------------------------------------------------------
*************** In impImport() for Test2:DoTestImpl4(ref,int,int,ubyte):int
impImportBlockPending for BB08
Importing BB08 (PC=000) of 'Test2:DoTestImpl4(ref,int,int,ubyte):int'
[ 0] 0 (0x000) ldarg.0
[ 1] 1 (0x001) box 1B000006
Importing BOX(refClass) as NOP
[ 1] 6 (0x006) ldarg.1
[ 2] 7 (0x007) ldarg.2
[ 3] 8 (0x008) ldarg.3
[ 4] 9 (0x009) callvirt 2B000012
In Compiler::impImportCall: opcode is callvirt, kind=3, callRetType is int, structSize is 0
** Note: inlinee IL was partially imported -- imported 0 of 15 bytes of method IL
*************** in fgTransformIndirectCalls(inlinee)
-- no candidates to transform
Inlining [000040] failed, so bashing STMT00009 to NOP
INLINER: during 'fgInline' result 'failed this callee' reason 'generic virtual' for 'Test2:DoTest(int,int,ubyte):int' calling 'Test2:DoTestImpl4(ref,int,int,ubyte):int'
INLINER: Marking Test2:DoTestImpl4(ref,int,int,ubyte):int as NOINLINE because of generic virtual
INLINER: during 'fgInline' result 'failed this callee' reason 'generic virtual'
Replacing the return expression placeholder [000042] with [000040]
[000042] --C--------- * RET_EXPR int (inl return from call [000040])
Inserting the inline return expression
[000040] --C-G------- * CALL int Test2.DoTestImpl4
[000041] ------------ arg0 +--* CNS_INT(h) long 0xd1ffab1e method
[000036] ------------ arg1 +--* LCL_VAR ref V11 tmp2
[000037] ------------ arg2 +--* LCL_VAR int V00 arg0
[000038] ------------ arg3 +--* LCL_VAR int V01 arg1
[000039] ------------ arg4 \--* LCL_VAR ubyte V02 arg2
Expanding INLINE_CANDIDATE in statement STMT00011 in BB01:
STMT00011 (IL ???...0x03A)
[000048] I-C-G------- * CALL int Test2.DoTestImpl5 (exactContextHnd=0x00000000D1FFAB1E)
[000045] ------------ arg0 +--* LCL_VAR int V00 arg0
[000046] ------------ arg1 +--* LCL_VAR int V01 arg1
[000047] ------------ arg2 \--* LCL_VAR ubyte V02 arg2
Argument #0: is a local var
[000045] ------------ * LCL_VAR int V00 arg0
Argument #1: is a local var
[000046] ------------ * LCL_VAR int V01 arg1
Argument #2: is a local var
[000047] ------------ * LCL_VAR ubyte V02 arg2
INLINER: inlineInfo.tokenLookupContextHandle for Test2:DoTestImpl5(int,int,ubyte):int set to 0x00000000D1FFAB1E:
Invoking compiler for the inlinee method Test2:DoTestImpl5(int,int,ubyte):int :
IL to import:
IL_0000 73 0d 00 00 06 newobj 0x600000D
IL_0005 02 ldarg.0
IL_0006 03 ldarg.1
IL_0007 04 ldarg.2
IL_0008 6f 12 00 00 2b callvirt 0x2B000012
IL_000d 2a ret
INLINER impTokenLookupContextHandle for Test2:DoTestImpl5(int,int,ubyte):int is 0x00000000D1FFAB1E.
*************** In fgFindBasicBlocks() for Test2:DoTestImpl5(int,int,ubyte):int
Jump targets:
none
New Basic Block BB09 [0008] created.
BB09 [000..00E)
Basic block list for 'Test2:DoTestImpl5(int,int,ubyte):int'
-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB09 [0008] 1 1 [000..00E) (return)
-----------------------------------------------------------------------------------------------------------------------------------------
*************** In impImport() for Test2:DoTestImpl5(int,int,ubyte):int
impImportBlockPending for BB09
Importing BB09 (PC=000) of 'Test2:DoTestImpl5(int,int,ubyte):int'
[ 0] 0 (0x000) newobj
lvaGrabTemp returning 12 (V12 tmp3) called for NewObj constructor temp.
[000093] -A---------- * ASG ref
[000092] D------N---- +--* LCL_VAR ref V12 tmp3
[000091] ------------ \--* ALLOCOBJ ref
[000090] ------------ \--* CNS_INT(h) long 0xd1ffab1e method
Marked V12 as a single def local
lvaSetClass: setting class for V12 to (00000000D1FFAB1E) CalculatorClass [exact]
0600000D
In Compiler::impImportCall: opcode is newobj, kind=0, callRetType is void, structSize is 0
[000095] I-C-G------- * CALL void CalculatorClass..ctor (exactContextHnd=0x00000000D1FFAB1E)
[000094] ------------ this in rcx \--* LCL_VAR ref V12 tmp3
[ 1] 5 (0x005) ldarg.0
[ 2] 6 (0x006) ldarg.1
[ 3] 7 (0x007) ldarg.2
[ 4] 8 (0x008) callvirt 2B000012
In Compiler::impImportCall: opcode is callvirt, kind=3, callRetType is int, structSize is 0
** Note: inlinee IL was partially imported -- imported 0 of 14 bytes of method IL
*************** in fgTransformIndirectCalls(inlinee)
-- no candidates to transform
Inlining [000048] failed, so bashing STMT00011 to NOP
INLINER: during 'fgInline' result 'failed this callee' reason 'generic virtual' for 'Test2:DoTest(int,int,ubyte):int' calling 'Test2:DoTestImpl5(int,int,ubyte):int'
INLINER: Marking Test2:DoTestImpl5(int,int,ubyte):int as NOINLINE because of generic virtual
INLINER: during 'fgInline' result 'failed this callee' reason 'generic virtual'
Replacing the return expression placeholder [000049] with [000048]
[000049] --C--------- * RET_EXPR int (inl return from call [000048])
Inserting the inline return expression
[000048] --C-G------- * CALL int Test2.DoTestImpl5
[000045] ------------ arg0 +--* LCL_VAR int V00 arg0
[000046] ------------ arg1 +--* LCL_VAR int V01 arg1
[000047] ------------ arg2 \--* LCL_VAR ubyte V02 arg2
Expanding INLINE_CANDIDATE in statement STMT00013 in BB01:
STMT00013 (IL ???...0x043)
[000055] I-C-G------- * CALL int Test2.DoTestImpl6 (exactContextHnd=0x00000000D1FFAB1E)
[000052] ------------ arg0 +--* LCL_VAR int V00 arg0
[000053] ------------ arg1 +--* LCL_VAR int V01 arg1
[000054] ------------ arg2 \--* LCL_VAR ubyte V02 arg2
Argument #0: is a local var
[000052] ------------ * LCL_VAR int V00 arg0
Argument #1: is a local var
[000053] ------------ * LCL_VAR int V01 arg1
Argument #2: is a local var
[000054] ------------ * LCL_VAR ubyte V02 arg2
INLINER: inlineInfo.tokenLookupContextHandle for Test2:DoTestImpl6(int,int,ubyte):int set to 0x00000000D1FFAB1E:
Invoking compiler for the inlinee method Test2:DoTestImpl6(int,int,ubyte):int :
IL to import:
IL_0000 12 00 ldloca.s 0x0
IL_0002 fe 15 07 00 00 02 initobj 0x2000007
IL_0008 12 00 ldloca.s 0x0
IL_000a 02 ldarg.0
IL_000b 03 ldarg.1
IL_000c 04 ldarg.2
IL_000d 28 13 00 00 2b call 0x2B000013
IL_0012 2a ret
INLINER impTokenLookupContextHandle for Test2:DoTestImpl6(int,int,ubyte):int is 0x00000000D1FFAB1E.
*************** In fgFindBasicBlocks() for Test2:DoTestImpl6(int,int,ubyte):int
Jump targets:
none
New Basic Block BB10 [0009] created.
BB10 [000..013)
Basic block list for 'Test2:DoTestImpl6(int,int,ubyte):int'
-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB10 [0009] 1 1 [000..013) (return)
-----------------------------------------------------------------------------------------------------------------------------------------
*************** In impImport() for Test2:DoTestImpl6(int,int,ubyte):int
impImportBlockPending for BB10
Importing BB10 (PC=000) of 'Test2:DoTestImpl6(int,int,ubyte):int'
[ 0] 0 (0x000) ldloca.s 0
lvaGrabTemp returning 12 (V12 tmp3) (a long lifetime temp) called for Inline ldloca(s) first use temp.
[ 1] 2 (0x002) initobj 02000007
[000101] IA---------- * ASG struct (init)
[000098] D------N---- +--* LCL_VAR struct V12 tmp3
[000100] ------------ \--* CNS_INT int 0
[ 0] 8 (0x008) ldloca.s 0
[ 1] 10 (0x00a) ldarg.0
[ 2] 11 (0x00b) ldarg.1
[ 3] 12 (0x00c) ldarg.2
[ 4] 13 (0x00d) call 2B000013
In Compiler::impImportCall: opcode is call, kind=0, callRetType is int, structSize is 0
[000104] I-C-G------- * CALL int CalculatorStruct.Calc (exactContextHnd=0x00000000D1FFAB1E)
[000103] ------------ this in rcx +--* ADDR byref
[000102] ------------ | \--* LCL_VAR struct V12 tmp3
[000052] ------------ arg1 +--* LCL_VAR int V00 arg0
[000053] ------------ arg2 +--* LCL_VAR int V01 arg1
[000054] ------------ arg3 \--* LCL_VAR ubyte V02 arg2
[ 1] 18 (0x012) ret
Inlinee Return expression (before normalization) =>
[000105] --C--------- * RET_EXPR int (inl return from call [000104])
Inlinee Return expression (after normalization) =>
[000105] --C--------- * RET_EXPR int (inl return from call [000104])
*************** in fgTransformIndirectCalls(inlinee)
-- no candidates to transform
----------- Statements (and blocks) added due to the inlining of call [000055] -----------
Arguments setup:
Zero init inlinee locals:
STMT00013 (IL ???...0x043)
[000055] I-C-G------- * CALL int Test2.DoTestImpl6 (exactContextHnd=0x00000000D1FFAB1E)
[000052] ------------ arg0 +--* LCL_VAR int V00 arg0
[000053] ------------ arg1 +--* LCL_VAR int V01 arg1
[000054] ------------ arg2 \--* LCL_VAR ubyte V02 arg2
Inlinee method body:
STMT00022 (IL ???... ???)
[000101] IA---------- * ASG struct (init)
[000098] D------N---- +--* LCL_VAR struct V12 tmp3
[000100] ------------ \--* CNS_INT int 0
STMT00023 (IL ???... ???)
[000104] I-C-G------- * CALL int CalculatorStruct.Calc (exactContextHnd=0x00000000D1FFAB1E)
[000103] ------------ this in rcx +--* ADDR byref
[000102] ------------ | \--* LCL_VAR struct V12 tmp3
[000052] ------------ arg1 +--* LCL_VAR int V00 arg0
[000053] ------------ arg2 +--* LCL_VAR int V01 arg1
[000054] ------------ arg3 \--* LCL_VAR ubyte V02 arg2
fgInlineAppendStatements: no gc ref inline locals.
Return expression for call at [000055] is
[000105] --C--------- * RET_EXPR int (inl return from call [000104])
Successfully inlined Test2:DoTestImpl6(int,int,ubyte):int (19 IL bytes) (depth 1) [aggressive inline attribute]
--------------------------------------------------------------------------------------------
INLINER: during 'fgInline' result 'success' reason 'aggressive inline attribute' for 'Test2:DoTest(int,int,ubyte):int' calling 'Test2:DoTestImpl6(int,int,ubyte):int'
INLINER: during 'fgInline' result 'success' reason 'aggressive inline attribute'
Expanding INLINE_CANDIDATE in statement STMT00023 in BB01:
STMT00023 (IL ???... ???)
[000104] I-C-G------- * CALL int CalculatorStruct.Calc (exactContextHnd=0x00000000D1FFAB1E)
[000103] ------------ this in rcx +--* ADDR byref
[000102] ------------ | \--* LCL_VAR struct V12 tmp3
[000052] ------------ arg1 +--* LCL_VAR int V00 arg0
[000053] ------------ arg2 +--* LCL_VAR int V01 arg1
[000054] ------------ arg3 \--* LCL_VAR ubyte V02 arg2
thisArg: is a constant is byref to a struct local
[000103] ------------ * ADDR byref
[000102] ------------ \--* LCL_VAR struct V12 tmp3
Argument #1: is a local var
[000052] ------------ * LCL_VAR int V00 arg0
Argument #2: is a local var
[000053] ------------ * LCL_VAR int V01 arg1
Argument #3: is a local var
[000054] ------------ * LCL_VAR ubyte V02 arg2
INLINER: inlineInfo.tokenLookupContextHandle for CalculatorStruct:Calc(int,int,ubyte):int:this set to 0x00000000D1FFAB1E:
Invoking compiler for the inlinee method CalculatorStruct:Calc(int,int,ubyte):int:this :
IL to import:
IL_0000 03 ldarg.1
IL_0001 04 ldarg.2
IL_0002 05 ldarg.3
IL_0003 28 09 00 00 2b call 0x2B000009
IL_0008 2a ret
INLINER impTokenLookupContextHandle for CalculatorStruct:Calc(int,int,ubyte):int:this is 0x00000000D1FFAB1E.
*************** In fgFindBasicBlocks() for CalculatorStruct:Calc(int,int,ubyte):int:this
Jump targets:
none
New Basic Block BB11 [0010] created.
BB11 [000..009)
Basic block list for 'CalculatorStruct:Calc(int,int,ubyte):int:this'
-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB11 [0010] 1 1 [000..009) (return)
-----------------------------------------------------------------------------------------------------------------------------------------
*************** In impImport() for CalculatorStruct:Calc(int,int,ubyte):int:this
impImportBlockPending for BB11
Importing BB11 (PC=000) of 'CalculatorStruct:Calc(int,int,ubyte):int:this'
[ 0] 0 (0x000) ldarg.1
[ 1] 1 (0x001) ldarg.2
[ 2] 2 (0x002) ldarg.3
[ 3] 3 (0x003) call 2B000009
In Compiler::impImportCall: opcode is call, kind=0, callRetType is int, structSize is 0
[000107] I-C-G------- * CALL int CalcMethods.Calc (exactContextHnd=0x00000000D1FFAB1E)
[000052] ------------ arg0 +--* LCL_VAR int V00 this
[000053] ------------ arg1 +--* LCL_VAR int V01 arg1
[000054] ------------ arg2 \--* LCL_VAR ubyte V02 arg2
[ 1] 8 (0x008) ret
Inlinee Return expression (before normalization) =>
[000108] --C--------- * RET_EXPR int (inl return from call [000107])
Inlinee Return expression (after normalization) =>
[000108] --C--------- * RET_EXPR int (inl return from call [000107])
*************** in fgTransformIndirectCalls(inlinee)
-- no candidates to transform
----------- Statements (and blocks) added due to the inlining of call [000104] -----------
Arguments setup:
Inlinee method body:
STMT00024 (IL ???... ???)
[000107] I-C-G------- * CALL int CalcMethods.Calc (exactContextHnd=0x00000000D1FFAB1E)
[000052] ------------ arg0 +--* LCL_VAR int V00 arg0
[000053] ------------ arg1 +--* LCL_VAR int V01 arg1
[000054] ------------ arg2 \--* LCL_VAR ubyte V02 arg2
fgInlineAppendStatements: no gc ref inline locals.
Return expression for call at [000104] is
[000108] --C--------- * RET_EXPR int (inl return from call [000107])
Successfully inlined CalculatorStruct:Calc(int,int,ubyte):int:this (9 IL bytes) (depth 2) [aggressive inline attribute]
--------------------------------------------------------------------------------------------
INLINER: during 'fgInline' result 'success' reason 'aggressive inline attribute' for 'Test2:DoTest(int,int,ubyte):int' calling 'CalculatorStruct:Calc(int,int,ubyte):int:this'
INLINER: during 'fgInline' result 'success' reason 'aggressive inline attribute'
Expanding INLINE_CANDIDATE in statement STMT00024 in BB01:
STMT00024 (IL ???... ???)
[000107] I-C-G------- * CALL int CalcMethods.Calc (exactContextHnd=0x00000000D1FFAB1E)
[000052] ------------ arg0 +--* LCL_VAR int V00 arg0
[000053] ------------ arg1 +--* LCL_VAR int V01 arg1
[000054] ------------ arg2 \--* LCL_VAR ubyte V02 arg2
Argument #0: is a local var
[000052] ------------ * LCL_VAR int V00 arg0
Argument #1: is a local var
[000053] ------------ * LCL_VAR int V01 arg1
Argument #2: is a local var
[000054] ------------ * LCL_VAR ubyte V02 arg2
INLINER: inlineInfo.tokenLookupContextHandle for CalcMethods:Calc(int,int,ubyte):int set to 0x00000000D1FFAB1E:
Invoking compiler for the inlinee method CalcMethods:Calc(int,int,ubyte):int :
IL to import:
IL_0000 02 ldarg.0
IL_0001 03 ldarg.1
IL_0002 28 04 00 00 2b call 0x2B000004
IL_0007 04 ldarg.2
IL_0008 28 05 00 00 2b call 0x2B000005
IL_000d 28 06 00 00 2b call 0x2B000006
IL_0012 0a stloc.0
IL_0013 02 ldarg.0
IL_0014 04 ldarg.2
IL_0015 28 05 00 00 2b call 0x2B000005
IL_001a 28 06 00 00 2b call 0x2B000006
IL_001f 06 ldloc.0
IL_0020 18 ldc.i4.2
IL_0021 28 07 00 00 2b call 0x2B000007
IL_0026 28 08 00 00 2b call 0x2B000008
IL_002b 2a ret
INLINER impTokenLookupContextHandle for CalcMethods:Calc(int,int,ubyte):int is 0x00000000D1FFAB1E.
*************** In fgFindBasicBlocks() for CalcMethods:Calc(int,int,ubyte):int
Jump targets:
none
New Basic Block BB12 [0011] created.
BB12 [000..02C)
Basic block list for 'CalcMethods:Calc(int,int,ubyte):int'
-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB12 [0011] 1 1 [000..02C) (return)
-----------------------------------------------------------------------------------------------------------------------------------------
*************** In impImport() for CalcMethods:Calc(int,int,ubyte):int
impImportBlockPending for BB12
Importing BB12 (PC=000) of 'CalcMethods:Calc(int,int,ubyte):int'
[ 0] 0 (0x000) ldarg.0
[ 1] 1 (0x001) ldarg.1
[ 2] 2 (0x002) call 2B000004
In Compiler::impImportCall: opcode is call, kind=0, callRetType is int, structSize is 0
[000110] I-C-G------- * CALL int UnsafeMath.Add (exactContextHnd=0x00000000D1FFAB1E)
[000052] ------------ arg0 +--* LCL_VAR int V00 arg0
[000053] ------------ arg1 \--* LCL_VAR int V01 arg1
[ 1] 7 (0x007) ldarg.2
[ 2] 8 (0x008) call 2B000005
In Compiler::impImportCall: opcode is call, kind=0, callRetType is int, structSize is 0
lvaGrabTemp returning 13 (V13 tmp4) called for impAppendStmt.
[000114] -AC--------- * ASG int
[000113] D------N---- +--* LCL_VAR int V13 tmp4
[000111] --C--------- \--* RET_EXPR int (inl return from call [000110])
[000112] I-C-G------- * CALL int UnsafeMath.Cast (exactContextHnd=0x00000000D1FFAB1E)
[000054] ------------ arg0 \--* LCL_VAR ubyte V02 arg2
[ 2] 13 (0x00d) call 2B000006
In Compiler::impImportCall: opcode is call, kind=0, callRetType is int, structSize is 0
[000117] I-C-G------- * CALL int UnsafeMath.Mul (exactContextHnd=0x00000000D1FFAB1E)
[000115] ------------ arg0 +--* LCL_VAR int V13 tmp4
[000116] --C--------- arg1 \--* RET_EXPR int (inl return from call [000112])
[ 1] 18 (0x012) stloc.0
lvaGrabTemp returning 14 (V14 tmp5) (a long lifetime temp) called for Inline stloc first use temp.
[000120] -AC--------- * ASG int
[000119] D------N---- +--* LCL_VAR int V14 tmp5
[000118] --C--------- \--* RET_EXPR int (inl return from call [000117])
[ 0] 19 (0x013) ldarg.0
[ 1] 20 (0x014) ldarg.2
[ 2] 21 (0x015) call 2B000005
In Compiler::impImportCall: opcode is call, kind=0, callRetType is int, structSize is 0
[000123] I-C-G------- * CALL int UnsafeMath.Cast (exactContextHnd=0x00000000D1FFAB1E)
[000122] ------------ arg0 \--* LCL_VAR ubyte V02 arg2
[ 2] 26 (0x01a) call 2B000006
In Compiler::impImportCall: opcode is call, kind=0, callRetType is int, structSize is 0
[000125] I-C-G------- * CALL int UnsafeMath.Mul (exactContextHnd=0x00000000D1FFAB1E)
[000121] ------------ arg0 +--* LCL_VAR int V00 arg0
[000124] --C--------- arg1 \--* RET_EXPR int (inl return from call [000123])
[ 1] 31 (0x01f) ldloc.0
[ 2] 32 (0x020) ldc.i4.2 2
[ 3] 33 (0x021) call 2B000007
In Compiler::impImportCall: opcode is call, kind=0, callRetType is int, structSize is 0
lvaGrabTemp returning 15 (V15 tmp6) called for impAppendStmt.
[000131] -AC--------- * ASG int
[000130] D------N---- +--* LCL_VAR int V15 tmp6
[000126] --C--------- \--* RET_EXPR int (inl return from call [000125])
[000129] I-C-G------- * CALL int UnsafeMath.Shr (exactContextHnd=0x00000000D1FFAB1E)
[000127] ------------ arg0 +--* LCL_VAR int V14 tmp5
[000128] ------------ arg1 \--* CNS_INT int 2
[ 2] 38 (0x026) call 2B000008
In Compiler::impImportCall: opcode is call, kind=0, callRetType is int, structSize is 0
[000134] I-C-G------- * CALL int UnsafeMath.Div (exactContextHnd=0x00000000D1FFAB1E)
[000132] ------------ arg0 +--* LCL_VAR int V15 tmp6
[000133] --C--------- arg1 \--* RET_EXPR int (inl return from call [000129])
[ 1] 43 (0x02b) ret
Inlinee Return expression (before normalization) =>
[000135] --C--------- * RET_EXPR int (inl return from call [000134])
Inlinee Return expression (after normalization) =>
[000135] --C--------- * RET_EXPR int (inl return from call [000134])
*************** in fgTransformIndirectCalls(inlinee)
-- no candidates to transform
----------- Statements (and blocks) added due to the inlining of call [000107] -----------
Arguments setup:
Zero init inlinee locals:
STMT00035 (IL ???... ???)
[000138] -A---------- * ASG int
[000137] D------N---- +--* LCL_VAR int V14 tmp5
[000136] ------------ \--* CNS_INT int 0
Inlinee method body:
STMT00025 (IL ???... ???)
[000110] I-C-G------- * CALL int UnsafeMath.Add (exactContextHnd=0x00000000D1FFAB1E)
[000052] ------------ arg0 +--* LCL_VAR int V00 arg0
[000053] ------------ arg1 \--* LCL_VAR int V01 arg1
STMT00027 (IL ???... ???)
[000114] -AC--------- * ASG int
[000113] D------N---- +--* LCL_VAR int V13 tmp4
[000111] --C--------- \--* RET_EXPR int (inl return from call [000110])
STMT00026 (IL ???... ???)
[000112] I-C-G------- * CALL int UnsafeMath.Cast (exactContextHnd=0x00000000D1FFAB1E)
[000054] ------------ arg0 \--* LCL_VAR ubyte V02 arg2
STMT00028 (IL ???... ???)
[000117] I-C-G------- * CALL int UnsafeMath.Mul (exactContextHnd=0x00000000D1FFAB1E)
[000115] ------------ arg0 +--* LCL_VAR int V13 tmp4
[000116] --C--------- arg1 \--* RET_EXPR int (inl return from call [000112])
STMT00029 (IL ???... ???)
[000120] -AC--------- * ASG int
[000119] D------N---- +--* LCL_VAR int V14 tmp5
[000118] --C--------- \--* RET_EXPR int (inl return from call [000117])
STMT00030 (IL ???... ???)
[000123] I-C-G------- * CALL int UnsafeMath.Cast (exactContextHnd=0x00000000D1FFAB1E)
[000122] ------------ arg0 \--* LCL_VAR ubyte V02 arg2
STMT00031 (IL ???... ???)
[000125] I-C-G------- * CALL int UnsafeMath.Mul (exactContextHnd=0x00000000D1FFAB1E)
[000121] ------------ arg0 +--* LCL_VAR int V00 arg0
[000124] --C--------- arg1 \--* RET_EXPR int (inl return from call [000123])
STMT00033 (IL ???... ???)
[000131] -AC--------- * ASG int
[000130] D------N---- +--* LCL_VAR int V15 tmp6
[000126] --C--------- \--* RET_EXPR int (inl return from call [000125])
STMT00032 (IL ???... ???)
[000129] I-C-G------- * CALL int UnsafeMath.Shr (exactContextHnd=0x00000000D1FFAB1E)
[000127] ------------ arg0 +--* LCL_VAR int V14 tmp5
[000128] ------------ arg1 \--* CNS_INT int 2
STMT00034 (IL ???... ???)
[000134] I-C-G------- * CALL int UnsafeMath.Div (exactContextHnd=0x00000000D1FFAB1E)
[000132] ------------ arg0 +--* LCL_VAR int V15 tmp6
[000133] --C--------- arg1 \--* RET_EXPR int (inl return from call [000129])
fgInlineAppendStatements: no gc ref inline locals.
Return expression for call at [000107] is
[000135] --C--------- * RET_EXPR int (inl return from call [000134])
Successfully inlined CalcMethods:Calc(int,int,ubyte):int (44 IL bytes) (depth 3) [aggressive inline attribute]
--------------------------------------------------------------------------------------------
INLINER: during 'fgInline' result 'success' reason 'aggressive inline attribute' for 'Test2:DoTest(int,int,ubyte):int' calling 'CalcMethods:Calc(int,int,ubyte):int'
INLINER: during 'fgInline' result 'success' reason 'aggressive inline attribute'
Expanding INLINE_CANDIDATE in statement STMT00025 in BB01:
STMT00025 (IL ???... ???)
[000110] I-C-G------- * CALL int UnsafeMath.Add (exactContextHnd=0x00000000D1FFAB1E)
[000052] ------------ arg0 +--* LCL_VAR int V00 arg0
[000053] ------------ arg1 \--* LCL_VAR int V01 arg1
Argument #0: is a local var
[000052] ------------ * LCL_VAR int V00 arg0
Argument #1: is a local var
[000053] ------------ * LCL_VAR int V01 arg1
INLINER: inlineInfo.tokenLookupContextHandle for UnsafeMath:Add(int,int):int set to 0x00000000D1FFAB1E:
Invoking compiler for the inlinee method UnsafeMath:Add(int,int):int :
IL to import:
IL_0000 02 ldarg.0
IL_0001 03 ldarg.1
IL_0002 58 add
IL_0003 2a ret
INLINER impTokenLookupContextHandle for UnsafeMath:Add(int,int):int is 0x00000000D1FFAB1E.
*************** In fgFindBasicBlocks() for UnsafeMath:Add(int,int):int
Jump targets:
none
New Basic Block BB13 [0012] created.
BB13 [000..004)
Basic block list for 'UnsafeMath:Add(int,int):int'
-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB13 [0012] 1 1 [000..004) (return)
-----------------------------------------------------------------------------------------------------------------------------------------
*************** In impImport() for UnsafeMath:Add(int,int):int
impImportBlockPending for BB13
Importing BB13 (PC=000) of 'UnsafeMath:Add(int,int):int'
[ 0] 0 (0x000) ldarg.0
[ 1] 1 (0x001) ldarg.1
[ 2] 2 (0x002) add
[ 1] 3 (0x003) ret
Inlinee Return expression (before normalization) =>
[000140] ------------ * ADD int
[000052] ------------ +--* LCL_VAR int V00 arg0
[000053] ------------ \--* LCL_VAR int V01 arg1
Inlinee Return expression (after normalization) =>
[000140] ------------ * ADD int
[000052] ------------ +--* LCL_VAR int V00 arg0
[000053] ------------ \--* LCL_VAR int V01 arg1
** Note: inlinee IL was partially imported -- imported 0 of 4 bytes of method IL
*************** in fgTransformIndirectCalls(inlinee)
-- no candidates to transform
----------- Statements (and blocks) added due to the inlining of call [000110] -----------
Arguments setup:
Inlinee method body:fgInlineAppendStatements: no gc ref inline locals.
Return expression for call at [000110] is
[000140] ------------ * ADD int
[000052] ------------ +--* LCL_VAR int V00 arg0
[000053] ------------ \--* LCL_VAR int V01 arg1
Successfully inlined UnsafeMath:Add(int,int):int (4 IL bytes) (depth 4) [aggressive inline attribute]
--------------------------------------------------------------------------------------------
INLINER: during 'fgInline' result 'success' reason 'aggressive inline attribute' for 'Test2:DoTest(int,int,ubyte):int' calling 'UnsafeMath:Add(int,int):int'
INLINER: during 'fgInline' result 'success' reason 'aggressive inline attribute'
Replacing the return expression placeholder [000111] with [000140]
[000111] --C--------- * RET_EXPR int (inl return from call [000140])
Inserting the inline return expression
[000140] ------------ * ADD int
[000052] ------------ +--* LCL_VAR int V00 arg0
[000053] ------------ \--* LCL_VAR int V01 arg1
Expanding INLINE_CANDIDATE in statement STMT00026 in BB01:
STMT00026 (IL ???... ???)
[000112] I-C-G------- * CALL int UnsafeMath.Cast (exactContextHnd=0x00000000D1FFAB1E)
[000054] ------------ arg0 \--* LCL_VAR ubyte V02 arg2
Argument #0: is a local var
[000054] ------------ * LCL_VAR ubyte V02 arg2
INLINER: inlineInfo.tokenLookupContextHandle for UnsafeMath:Cast(ubyte):int set to 0x00000000D1FFAB1E:
Invoking compiler for the inlinee method UnsafeMath:Cast(ubyte):int :
IL to import:
IL_0000 02 ldarg.0
IL_0001 2a ret
INLINER impTokenLookupContextHandle for UnsafeMath:Cast(ubyte):int is 0x00000000D1FFAB1E.
*************** In fgFindBasicBlocks() for UnsafeMath:Cast(ubyte):int
Jump targets:
none
New Basic Block BB14 [0013] created.
BB14 [000..002)
Basic block list for 'UnsafeMath:Cast(ubyte):int'
-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB14 [0013] 1 1 [000..002) (return)
-----------------------------------------------------------------------------------------------------------------------------------------
*************** In impImport() for UnsafeMath:Cast(ubyte):int
impImportBlockPending for BB14
Importing BB14 (PC=000) of 'UnsafeMath:Cast(ubyte):int'
[ 0] 0 (0x000) ldarg.0
[ 1] 1 (0x001) ret
Inlinee Return expression (before normalization) =>
[000054] ------------ * LCL_VAR ubyte V02 arg2
Inlinee Return expression (after normalization) =>
[000142] ------------ * CAST int <- int
[000054] ------------ \--* LCL_VAR ubyte V02 arg2
** Note: inlinee IL was partially imported -- imported 0 of 2 bytes of method IL
*************** in fgTransformIndirectCalls(inlinee)
-- no candidates to transform
----------- Statements (and blocks) added due to the inlining of call [000112] -----------
Arguments setup:
Inlinee method body:fgInlineAppendStatements: no gc ref inline locals.
Return expression for call at [000112] is
[000142] ------------ * CAST int <- int
[000054] ------------ \--* LCL_VAR ubyte V02 arg2
Successfully inlined UnsafeMath:Cast(ubyte):int (2 IL bytes) (depth 4) [aggressive inline attribute]
--------------------------------------------------------------------------------------------
INLINER: during 'fgInline' result 'success' reason 'aggressive inline attribute' for 'Test2:DoTest(int,int,ubyte):int' calling 'UnsafeMath:Cast(ubyte):int'
INLINER: during 'fgInline' result 'success' reason 'aggressive inline attribute'
Expanding INLINE_CANDIDATE in statement STMT00028 in BB01:
STMT00028 (IL ???... ???)
[000117] I-C-G------- * CALL int UnsafeMath.Mul (exactContextHnd=0x00000000D1FFAB1E)
[000115] ------------ arg0 +--* LCL_VAR int V13 tmp4
[000116] --C--------- arg1 \--* RET_EXPR int (inl return from call [000142])
Argument #0: is a local var
[000115] ------------ * LCL_VAR int V13 tmp4
Argument #1:
[000142] ------------ * CAST int <- int
[000054] ------------ \--* LCL_VAR ubyte V02 arg2
INLINER: inlineInfo.tokenLookupContextHandle for UnsafeMath:Mul(int,int):int set to 0x00000000D1FFAB1E:
Invoking compiler for the inlinee method UnsafeMath:Mul(int,int):int :
IL to import:
IL_0000 02 ldarg.0
IL_0001 03 ldarg.1
IL_0002 5a mul
IL_0003 2a ret
INLINER impTokenLookupContextHandle for UnsafeMath:Mul(int,int):int is 0x00000000D1FFAB1E.
*************** In fgFindBasicBlocks() for UnsafeMath:Mul(int,int):int
Jump targets:
none
New Basic Block BB15 [0014] created.
BB15 [000..004)
Basic block list for 'UnsafeMath:Mul(int,int):int'
-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB15 [0014] 1 1 [000..004) (return)
-----------------------------------------------------------------------------------------------------------------------------------------
*************** In impImport() for UnsafeMath:Mul(int,int):int
impImportBlockPending for BB15
Importing BB15 (PC=000) of 'UnsafeMath:Mul(int,int):int'
[ 0] 0 (0x000) ldarg.0
[ 1] 1 (0x001) ldarg.1
lvaGrabTemp returning 16 (V16 tmp7) called for Inlining Arg.
[ 2] 2 (0x002) mul
[ 1] 3 (0x003) ret
Inlinee Return expression (before normalization) =>
[000145] ------------ * MUL int
[000115] ------------ +--* LCL_VAR int V13 tmp4
[000144] ------------ \--* LCL_VAR int V16 tmp7
Inlinee Return expression (after normalization) =>
[000145] ------------ * MUL int
[000115] ------------ +--* LCL_VAR int V13 tmp4
[000144] ------------ \--* LCL_VAR int V16 tmp7
** Note: inlinee IL was partially imported -- imported 0 of 4 bytes of method IL
*************** in fgTransformIndirectCalls(inlinee)
-- no candidates to transform
----------- Statements (and blocks) added due to the inlining of call [000117] -----------
Arguments setup:
Inlinee method body:fgInlineAppendStatements: no gc ref inline locals.
Return expression for call at [000117] is
[000145] ------------ * MUL int
[000115] ------------ +--* LCL_VAR int V13 tmp4
[000142] ------------ \--* CAST int <- int
[000054] ------------ \--* LCL_VAR ubyte V02 arg2
Successfully inlined UnsafeMath:Mul(int,int):int (4 IL bytes) (depth 4) [aggressive inline attribute]
--------------------------------------------------------------------------------------------
INLINER: during 'fgInline' result 'success' reason 'aggressive inline attribute' for 'Test2:DoTest(int,int,ubyte):int' calling 'UnsafeMath:Mul(int,int):int'
INLINER: during 'fgInline' result 'success' reason 'aggressive inline attribute'
Replacing the return expression placeholder [000118] with [000145]
[000118] --C--------- * RET_EXPR int (inl return from call [000145])
Inserting the inline return expression
[000145] ------------ * MUL int
[000115] ------------ +--* LCL_VAR int V13 tmp4
[000142] ------------ \--* CAST int <- int
[000054] ------------ \--* LCL_VAR ubyte V02 arg2
Expanding INLINE_CANDIDATE in statement STMT00030 in BB01:
STMT00030 (IL ???... ???)
[000123] I-C-G------- * CALL int UnsafeMath.Cast (exactContextHnd=0x00000000D1FFAB1E)
[000122] ------------ arg0 \--* LCL_VAR ubyte V02 arg2
Argument #0: is a local var
[000122] ------------ * LCL_VAR ubyte V02 arg2
INLINER: inlineInfo.tokenLookupContextHandle for UnsafeMath:Cast(ubyte):int set to 0x00000000D1FFAB1E:
Invoking compiler for the inlinee method UnsafeMath:Cast(ubyte):int :
IL to import:
IL_0000 02 ldarg.0
IL_0001 2a ret
INLINER impTokenLookupContextHandle for UnsafeMath:Cast(ubyte):int is 0x00000000D1FFAB1E.
*************** In fgFindBasicBlocks() for UnsafeMath:Cast(ubyte):int
Jump targets:
none
New Basic Block BB16 [0015] created.
BB16 [000..002)
Basic block list for 'UnsafeMath:Cast(ubyte):int'
-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB16 [0015] 1 1 [000..002) (return)
-----------------------------------------------------------------------------------------------------------------------------------------
*************** In impImport() for UnsafeMath:Cast(ubyte):int
impImportBlockPending for BB16
Importing BB16 (PC=000) of 'UnsafeMath:Cast(ubyte):int'
[ 0] 0 (0x000) ldarg.0
[ 1] 1 (0x001) ret
Inlinee Return expression (before normalization) =>
[000122] ------------ * LCL_VAR ubyte V02 arg2
Inlinee Return expression (after normalization) =>
[000147] ------------ * CAST int <- int
[000122] ------------ \--* LCL_VAR ubyte V02 arg2
** Note: inlinee IL was partially imported -- imported 0 of 2 bytes of method IL
*************** in fgTransformIndirectCalls(inlinee)
-- no candidates to transform
----------- Statements (and blocks) added due to the inlining of call [000123] -----------
Arguments setup:
Inlinee method body:fgInlineAppendStatements: no gc ref inline locals.
Return expression for call at [000123] is
[000147] ------------ * CAST int <- int
[000122] ------------ \--* LCL_VAR ubyte V02 arg2
Successfully inlined UnsafeMath:Cast(ubyte):int (2 IL bytes) (depth 4) [aggressive inline attribute]
--------------------------------------------------------------------------------------------
INLINER: during 'fgInline' result 'success' reason 'aggressive inline attribute' for 'Test2:DoTest(int,int,ubyte):int' calling 'UnsafeMath:Cast(ubyte):int'
INLINER: during 'fgInline' result 'success' reason 'aggressive inline attribute'
Expanding INLINE_CANDIDATE in statement STMT00031 in BB01:
STMT00031 (IL ???... ???)
[000125] I-C-G------- * CALL int UnsafeMath.Mul (exactContextHnd=0x00000000D1FFAB1E)
[000121] ------------ arg0 +--* LCL_VAR int V00 arg0
[000124] --C--------- arg1 \--* RET_EXPR int (inl return from call [000147])
Argument #0: is a local var
[000121] ------------ * LCL_VAR int V00 arg0
Argument #1:
[000147] ------------ * CAST int <- int
[000122] ------------ \--* LCL_VAR ubyte V02 arg2
INLINER: inlineInfo.tokenLookupContextHandle for UnsafeMath:Mul(int,int):int set to 0x00000000D1FFAB1E:
Invoking compiler for the inlinee method UnsafeMath:Mul(int,int):int :
IL to import:
IL_0000 02 ldarg.0
IL_0001 03 ldarg.1
IL_0002 5a mul
IL_0003 2a ret
INLINER impTokenLookupContextHandle for UnsafeMath:Mul(int,int):int is 0x00000000D1FFAB1E.
*************** In fgFindBasicBlocks() for UnsafeMath:Mul(int,int):int
Jump targets:
none
New Basic Block BB17 [0016] created.
BB17 [000..004)
Basic block list for 'UnsafeMath:Mul(int,int):int'
-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB17 [0016] 1 1 [000..004) (return)
-----------------------------------------------------------------------------------------------------------------------------------------
*************** In impImport() for UnsafeMath:Mul(int,int):int
impImportBlockPending for BB17
Importing BB17 (PC=000) of 'UnsafeMath:Mul(int,int):int'
[ 0] 0 (0x000) ldarg.0
[ 1] 1 (0x001) ldarg.1
lvaGrabTemp returning 17 (V17 tmp8) called for Inlining Arg.
[ 2] 2 (0x002) mul
[ 1] 3 (0x003) ret
Inlinee Return expression (before normalization) =>
[000150] ------------ * MUL int
[000121] ------------ +--* LCL_VAR int V00 arg0
[000149] ------------ \--* LCL_VAR int V17 tmp8
Inlinee Return expression (after normalization) =>
[000150] ------------ * MUL int
[000121] ------------ +--* LCL_VAR int V00 arg0
[000149] ------------ \--* LCL_VAR int V17 tmp8
** Note: inlinee IL was partially imported -- imported 0 of 4 bytes of method IL
*************** in fgTransformIndirectCalls(inlinee)
-- no candidates to transform
----------- Statements (and blocks) added due to the inlining of call [000125] -----------
Arguments setup:
Inlinee method body:fgInlineAppendStatements: no gc ref inline locals.
Return expression for call at [000125] is
[000150] ------------ * MUL int
[000121] ------------ +--* LCL_VAR int V00 arg0
[000147] ------------ \--* CAST int <- int
[000122] ------------ \--* LCL_VAR ubyte V02 arg2
Successfully inlined UnsafeMath:Mul(int,int):int (4 IL bytes) (depth 4) [aggressive inline attribute]
--------------------------------------------------------------------------------------------
INLINER: during 'fgInline' result 'success' reason 'aggressive inline attribute' for 'Test2:DoTest(int,int,ubyte):int' calling 'UnsafeMath:Mul(int,int):int'
INLINER: during 'fgInline' result 'success' reason 'aggressive inline attribute'
Replacing the return expression placeholder [000126] with [000150]
[000126] --C--------- * RET_EXPR int (inl return from call [000150])
Inserting the inline return expression
[000150] ------------ * MUL int
[000121] ------------ +--* LCL_VAR int V00 arg0
[000147] ------------ \--* CAST int <- int
[000122] ------------ \--* LCL_VAR ubyte V02 arg2
Expanding INLINE_CANDIDATE in statement STMT00032 in BB01:
STMT00032 (IL ???... ???)
[000129] I-C-G------- * CALL int UnsafeMath.Shr (exactContextHnd=0x00000000D1FFAB1E)
[000127] ------------ arg0 +--* LCL_VAR int V14 tmp5
[000128] ------------ arg1 \--* CNS_INT int 2
Argument #0: is a local var
[000127] ------------ * LCL_VAR int V14 tmp5
Argument #1: is a constant
[000128] ------------ * CNS_INT int 2
INLINER: inlineInfo.tokenLookupContextHandle for UnsafeMath:Shr(int,int):int set to 0x00000000D1FFAB1E:
Invoking compiler for the inlinee method UnsafeMath:Shr(int,int):int :
IL to import:
IL_0000 02 ldarg.0
IL_0001 03 ldarg.1
IL_0002 63 shr
IL_0003 2a ret
INLINER impTokenLookupContextHandle for UnsafeMath:Shr(int,int):int is 0x00000000D1FFAB1E.
*************** In fgFindBasicBlocks() for UnsafeMath:Shr(int,int):int
Jump targets:
none
New Basic Block BB18 [0017] created.
BB18 [000..004)
Basic block list for 'UnsafeMath:Shr(int,int):int'
-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB18 [0017] 1 1 [000..004) (return)
-----------------------------------------------------------------------------------------------------------------------------------------
*************** In impImport() for UnsafeMath:Shr(int,int):int
impImportBlockPending for BB18
Importing BB18 (PC=000) of 'UnsafeMath:Shr(int,int):int'
[ 0] 0 (0x000) ldarg.0
[ 1] 1 (0x001) ldarg.1
[ 2] 2 (0x002) shr
[ 1] 3 (0x003) ret
Inlinee Return expression (before normalization) =>
[000153] ------------ * RSH int
[000127] ------------ +--* LCL_VAR int V14 tmp5
[000152] ------------ \--* CNS_INT int 2
Inlinee Return expression (after normalization) =>
[000153] ------------ * RSH int
[000127] ------------ +--* LCL_VAR int V14 tmp5
[000152] ------------ \--* CNS_INT int 2
** Note: inlinee IL was partially imported -- imported 0 of 4 bytes of method IL
*************** in fgTransformIndirectCalls(inlinee)
-- no candidates to transform
----------- Statements (and blocks) added due to the inlining of call [000129] -----------
Arguments setup:
Inlinee method body:fgInlineAppendStatements: no gc ref inline locals.
Return expression for call at [000129] is
[000153] ------------ * RSH int
[000127] ------------ +--* LCL_VAR int V14 tmp5
[000152] ------------ \--* CNS_INT int 2
Successfully inlined UnsafeMath:Shr(int,int):int (4 IL bytes) (depth 4) [aggressive inline attribute]
--------------------------------------------------------------------------------------------
INLINER: during 'fgInline' result 'success' reason 'aggressive inline attribute' for 'Test2:DoTest(int,int,ubyte):int' calling 'UnsafeMath:Shr(int,int):int'
INLINER: during 'fgInline' result 'success' reason 'aggressive inline attribute'
Expanding INLINE_CANDIDATE in statement STMT00034 in BB01:
STMT00034 (IL ???... ???)
[000134] I-C-G------- * CALL int UnsafeMath.Div (exactContextHnd=0x00000000D1FFAB1E)
[000132] ------------ arg0 +--* LCL_VAR int V15 tmp6
[000133] --C--------- arg1 \--* RET_EXPR int (inl return from call [000153])
Argument #0: is a local var
[000132] ------------ * LCL_VAR int V15 tmp6
Argument #1:
[000153] ------------ * RSH int
[000127] ------------ +--* LCL_VAR int V14 tmp5
[000152] ------------ \--* CNS_INT int 2
INLINER: inlineInfo.tokenLookupContextHandle for UnsafeMath:Div(int,int):int set to 0x00000000D1FFAB1E:
Invoking compiler for the inlinee method UnsafeMath:Div(int,int):int :
IL to import:
IL_0000 02 ldarg.0
IL_0001 03 ldarg.1
IL_0002 5b div
IL_0003 2a ret
INLINER impTokenLookupContextHandle for UnsafeMath:Div(int,int):int is 0x00000000D1FFAB1E.
*************** In fgFindBasicBlocks() for UnsafeMath:Div(int,int):int
Jump targets:
none
New Basic Block BB19 [0018] created.
BB19 [000..004)
Basic block list for 'UnsafeMath:Div(int,int):int'
-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB19 [0018] 1 1 [000..004) (return)
-----------------------------------------------------------------------------------------------------------------------------------------
*************** In impImport() for UnsafeMath:Div(int,int):int
impImportBlockPending for BB19
Importing BB19 (PC=000) of 'UnsafeMath:Div(int,int):int'
[ 0] 0 (0x000) ldarg.0
[ 1] 1 (0x001) ldarg.1
lvaGrabTemp returning 18 (V18 tmp9) called for Inlining Arg.
[ 2] 2 (0x002) div
[ 1] 3 (0x003) ret
Inlinee Return expression (before normalization) =>
[000156] ---X-------- * DIV int
[000132] ------------ +--* LCL_VAR int V15 tmp6
[000155] ------------ \--* LCL_VAR int V18 tmp9
Inlinee Return expression (after normalization) =>
[000156] ---X-------- * DIV int
[000132] ------------ +--* LCL_VAR int V15 tmp6
[000155] ------------ \--* LCL_VAR int V18 tmp9
** Note: inlinee IL was partially imported -- imported 0 of 4 bytes of method IL
*************** in fgTransformIndirectCalls(inlinee)
-- no candidates to transform
----------- Statements (and blocks) added due to the inlining of call [000134] -----------
Arguments setup:
Inlinee method body:fgInlineAppendStatements: no gc ref inline locals.
Return expression for call at [000134] is
[000156] ---X-------- * DIV int
[000132] ------------ +--* LCL_VAR int V15 tmp6
[000153] ------------ \--* RSH int
[000127] ------------ +--* LCL_VAR int V14 tmp5
[000152] ------------ \--* CNS_INT int 2
Successfully inlined UnsafeMath:Div(int,int):int (4 IL bytes) (depth 4) [aggressive inline attribute]
--------------------------------------------------------------------------------------------
INLINER: during 'fgInline' result 'success' reason 'aggressive inline attribute' for 'Test2:DoTest(int,int,ubyte):int' calling 'UnsafeMath:Div(int,int):int'
INLINER: during 'fgInline' result 'success' reason 'aggressive inline attribute'
Replacing the return expression placeholder [000056] with [000156]
[000056] --C--------- * RET_EXPR int (inl return from call [000105])
Inserting the inline return expression
[000156] ---X-------- * DIV int
[000132] ------------ +--* LCL_VAR int V15 tmp6
[000153] ------------ \--* RSH int
[000127] ------------ +--* LCL_VAR int V14 tmp5
[000152] ------------ \--* CNS_INT int 2
*************** After fgInline()
-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..051) (return) i newobj
-----------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [000..051) (return), preds={} succs={}
***** BB01
STMT00002 (IL ???... ???)
[000011] -AC--------- * ASG int
[000010] D------N---- +--* LCL_VAR int V10 tmp1
[000003] --C-G------- \--* CALL int Test2.DoTestImpl1
[000000] ------------ arg0 +--* LCL_VAR int V00 arg0
[000001] ------------ arg1 +--* LCL_VAR int V01 arg1
[000002] ------------ arg2 \--* LCL_VAR ubyte V02 arg2
***** BB01
STMT00003 (IL ???... ???)
[000015] -AC--------- * ASG int
[000014] D------N---- +--* LCL_VAR int V03 loc0
[000008] --C-G------- \--* CALL int Test2.DoTestImpl2
[000009] ------------ arg0 +--* CNS_INT(h) long 0xd1ffab1e method
[000005] ------------ arg1 +--* LCL_VAR int V00 arg0
[000006] ------------ arg2 +--* LCL_VAR int V01 arg1
[000007] ------------ arg3 \--* LCL_VAR ubyte V02 arg2
***** BB01
STMT00004 (IL ???...0x014)
[000019] IA---------- * ASG struct (init)
[000016] D------N---- +--* LCL_VAR struct V08 loc5
[000018] ------------ \--* CNS_INT int 0
***** BB01
STMT00006 (IL ???... ???)
[000029] -AC--------- * ASG int
[000028] D------N---- +--* LCL_VAR int V04 loc1
[000024] --C-G------- \--* CALL int Test2.DoTestImpl3
[000026] n----------- arg0 +--* OBJ(1) struct
[000025] ------------ | \--* ADDR byref
[000020] ------------ | \--* LCL_VAR struct V08 loc5
[000021] ------------ arg1 +--* LCL_VAR int V00 arg0
[000022] ------------ arg2 +--* LCL_VAR int V01 arg1
[000023] ------------ arg3 \--* LCL_VAR ubyte V02 arg2
***** BB01
STMT00007 (IL ???...0x031)
[000033] -A---------- * ASG ref
[000032] D------N---- +--* LCL_VAR ref V11 tmp2
[000031] ------------ \--* ALLOCOBJ ref
[000030] ------------ \--* CNS_INT(h) long 0xd1ffab1e method
***** BB01
STMT00010 (IL ???... ???)
[000044] -AC--------- * ASG int
[000043] D------N---- +--* LCL_VAR int V05 loc2
[000040] --C-G------- \--* CALL int Test2.DoTestImpl4
[000041] ------------ arg0 +--* CNS_INT(h) long 0xd1ffab1e method
[000036] ------------ arg1 +--* LCL_VAR ref V11 tmp2
[000037] ------------ arg2 +--* LCL_VAR int V00 arg0
[000038] ------------ arg3 +--* LCL_VAR int V01 arg1
[000039] ------------ arg4 \--* LCL_VAR ubyte V02 arg2
***** BB01
STMT00012 (IL ???... ???)
[000051] -AC--------- * ASG int
[000050] D------N---- +--* LCL_VAR int V06 loc3
[000048] --C-G------- \--* CALL int Test2.DoTestImpl5
[000045] ------------ arg0 +--* LCL_VAR int V00 arg0
[000046] ------------ arg1 +--* LCL_VAR int V01 arg1
[000047] ------------ arg2 \--* LCL_VAR ubyte V02 arg2
***** BB01
STMT00022 (IL ???... ???)
[000101] IA---------- * ASG struct (init)
[000098] D------N---- +--* LCL_VAR struct V12 tmp3
[000100] ------------ \--* CNS_INT int 0
***** BB01
STMT00035 (IL ???... ???)
[000138] -A---------- * ASG int
[000137] D------N---- +--* LCL_VAR int V14 tmp5
[000136] ------------ \--* CNS_INT int 0
***** BB01
STMT00027 (IL ???... ???)
[000114] -AC--------- * ASG int
[000113] D------N---- +--* LCL_VAR int V13 tmp4
[000140] ------------ \--* ADD int
[000052] ------------ +--* LCL_VAR int V00 arg0
[000053] ------------ \--* LCL_VAR int V01 arg1
***** BB01
STMT00029 (IL ???... ???)
[000120] -AC--------- * ASG int
[000119] D------N---- +--* LCL_VAR int V14 tmp5
[000145] ------------ \--* MUL int
[000115] ------------ +--* LCL_VAR int V13 tmp4
[000142] ------------ \--* CAST int <- int
[000054] ------------ \--* LCL_VAR ubyte V02 arg2
***** BB01
STMT00033 (IL ???... ???)
[000131] -AC--------- * ASG int
[000130] D------N---- +--* LCL_VAR int V15 tmp6
[000150] ------------ \--* MUL int
[000121] ------------ +--* LCL_VAR int V00 arg0
[000147] ------------ \--* CAST int <- int
[000122] ------------ \--* LCL_VAR ubyte V02 arg2
***** BB01
STMT00014 (IL ???... ???)
[000058] -AC--------- * ASG int
[000057] D------N---- +--* LCL_VAR int V07 loc4
[000156] ---X-------- \--* DIV int
[000132] ------------ +--* LCL_VAR int V15 tmp6
[000153] ------------ \--* RSH int
[000127] ------------ +--* LCL_VAR int V14 tmp5
[000152] ------------ \--* CNS_INT int 2
***** BB01
STMT00015 (IL ???...0x050)
[000069] ------------ * RETURN int
[000068] ------------ \--* ADD int
[000066] ------------ +--* ADD int
[000064] ------------ | +--* ADD int
[000062] ------------ | | +--* ADD int
[000060] ------------ | | | +--* ADD int
[000012] ------------ | | | | +--* LCL_VAR int V10 tmp1
[000059] ------------ | | | | \--* LCL_VAR int V03 loc0
[000061] ------------ | | | \--* LCL_VAR int V04 loc1
[000063] ------------ | | \--* LCL_VAR int V05 loc2
[000065] ------------ | \--* LCL_VAR int V06 loc3
[000067] ------------ \--* LCL_VAR int V07 loc4
-------------------------------------------------------------------------------------------------------------------
*************** Exception Handling table is empty
**************** Inline Tree
Inlines into 0600000F Test2:DoTest(int,int,ubyte):int
[0 IL=0003 TR=000003 06000010] [FAILED: generic virtual] Test2:DoTestImpl1(int,int,ubyte):int
[0 IL=0011 TR=000008 06000011] [FAILED: generic virtual] Test2:DoTestImpl2(int,int,ubyte):int
[0 IL=0030 TR=000024 06000012] [FAILED: generic virtual] Test2:DoTestImpl3(struct,int,int,ubyte):int
[1 IL=0036 TR=000035 0600000D] [below ALWAYS_INLINE size] CalculatorClass:.ctor():this
[2 IL=0001 TR=000084 0600000B] [below ALWAYS_INLINE size] CalculatorBase:.ctor():this
[3 IL=0001 TR=000086 06000464] [below ALWAYS_INLINE size] Object:.ctor():this
[0 IL=0044 TR=000040 06000013] [FAILED: generic virtual] Test2:DoTestImpl4(ref,int,int,ubyte):int
[0 IL=0053 TR=000048 06000014] [FAILED: generic virtual] Test2:DoTestImpl5(int,int,ubyte):int
[4 IL=0062 TR=000055 06000015] [aggressive inline attribute] Test2:DoTestImpl6(int,int,ubyte):int
[5 IL=0013 TR=000104 06000009] [aggressive inline attribute] CalculatorStruct:Calc(int,int,ubyte):int:this
[6 IL=0003 TR=000107 0600000E] [aggressive inline attribute] CalcMethods:Calc(int,int,ubyte):int
[7 IL=0002 TR=000110 0600002B] [aggressive inline attribute] UnsafeMath:Add(int,int):int
[8 IL=0008 TR=000112 0600003A] [aggressive inline attribute] UnsafeMath:Cast(ubyte):int
[9 IL=0013 TR=000117 0600002D] [aggressive inline attribute] UnsafeMath:Mul(int,int):int
[10 IL=0021 TR=000123 0600003A] [aggressive inline attribute] UnsafeMath:Cast(ubyte):int
[11 IL=0026 TR=000125 0600002D] [aggressive inline attribute] UnsafeMath:Mul(int,int):int
[12 IL=0033 TR=000129 0600002F] [aggressive inline attribute] UnsafeMath:Shr(int,int):int
[13 IL=0038 TR=000134 0600002E] [aggressive inline attribute] UnsafeMath:Div(int,int):int
Budget: initialTime=303, finalTime=293, initialBudget=3030, currentBudget=3132
Budget: increased by 102 because of force inlines
Budget: initialSize=1978, finalSize=1978
*************** In Allocate Objects
Trees before Allocate Objects
-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..051) (return) i newobj
-----------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [000..051) (return), preds={} succs={}
***** BB01
STMT00002 (IL ???... ???)
[000011] -AC--------- * ASG int
[000010] D------N---- +--* LCL_VAR int V10 tmp1
[000003] --C-G------- \--* CALL int Test2.DoTestImpl1
[000000] ------------ arg0 +--* LCL_VAR int V00 arg0
[000001] ------------ arg1 +--* LCL_VAR int V01 arg1
[000002] ------------ arg2 \--* LCL_VAR ubyte V02 arg2
***** BB01
STMT00003 (IL ???... ???)
[000015] -AC--------- * ASG int
[000014] D------N---- +--* LCL_VAR int V03 loc0
[000008] --C-G------- \--* CALL int Test2.DoTestImpl2
[000009] ------------ arg0 +--* CNS_INT(h) long 0xd1ffab1e method
[000005] ------------ arg1 +--* LCL_VAR int V00 arg0
[000006] ------------ arg2 +--* LCL_VAR int V01 arg1
[000007] ------------ arg3 \--* LCL_VAR ubyte V02 arg2
***** BB01
STMT00004 (IL ???...0x014)
[000019] IA---------- * ASG struct (init)
[000016] D------N---- +--* LCL_VAR struct V08 loc5
[000018] ------------ \--* CNS_INT int 0
***** BB01
STMT00006 (IL ???... ???)
[000029] -AC--------- * ASG int
[000028] D------N---- +--* LCL_VAR int V04 loc1
[000024] --C-G------- \--* CALL int Test2.DoTestImpl3
[000026] n----------- arg0 +--* OBJ(1) struct
[000025] ------------ | \--* ADDR byref
[000020] ------------ | \--* LCL_VAR struct V08 loc5
[000021] ------------ arg1 +--* LCL_VAR int V00 arg0
[000022] ------------ arg2 +--* LCL_VAR int V01 arg1
[000023] ------------ arg3 \--* LCL_VAR ubyte V02 arg2
***** BB01
STMT00007 (IL ???...0x031)
[000033] -A---------- * ASG ref
[000032] D------N---- +--* LCL_VAR ref V11 tmp2
[000031] ------------ \--* ALLOCOBJ ref
[000030] ------------ \--* CNS_INT(h) long 0xd1ffab1e method
***** BB01
STMT00010 (IL ???... ???)
[000044] -AC--------- * ASG int
[000043] D------N---- +--* LCL_VAR int V05 loc2
[000040] --C-G------- \--* CALL int Test2.DoTestImpl4
[000041] ------------ arg0 +--* CNS_INT(h) long 0xd1ffab1e method
[000036] ------------ arg1 +--* LCL_VAR ref V11 tmp2
[000037] ------------ arg2 +--* LCL_VAR int V00 arg0
[000038] ------------ arg3 +--* LCL_VAR int V01 arg1
[000039] ------------ arg4 \--* LCL_VAR ubyte V02 arg2
***** BB01
STMT00012 (IL ???... ???)
[000051] -AC--------- * ASG int
[000050] D------N---- +--* LCL_VAR int V06 loc3
[000048] --C-G------- \--* CALL int Test2.DoTestImpl5
[000045] ------------ arg0 +--* LCL_VAR int V00 arg0
[000046] ------------ arg1 +--* LCL_VAR int V01 arg1
[000047] ------------ arg2 \--* LCL_VAR ubyte V02 arg2
***** BB01
STMT00022 (IL ???... ???)
[000101] IA---------- * ASG struct (init)
[000098] D------N---- +--* LCL_VAR struct V12 tmp3
[000100] ------------ \--* CNS_INT int 0
***** BB01
STMT00035 (IL ???... ???)
[000138] -A---------- * ASG int
[000137] D------N---- +--* LCL_VAR int V14 tmp5
[000136] ------------ \--* CNS_INT int 0
***** BB01
STMT00027 (IL ???... ???)
[000114] -AC--------- * ASG int
[000113] D------N---- +--* LCL_VAR int V13 tmp4
[000140] ------------ \--* ADD int
[000052] ------------ +--* LCL_VAR int V00 arg0
[000053] ------------ \--* LCL_VAR int V01 arg1
***** BB01
STMT00029 (IL ???... ???)
[000120] -AC--------- * ASG int
[000119] D------N---- +--* LCL_VAR int V14 tmp5
[000145] ------------ \--* MUL int
[000115] ------------ +--* LCL_VAR int V13 tmp4
[000142] ------------ \--* CAST int <- int
[000054] ------------ \--* LCL_VAR ubyte V02 arg2
***** BB01
STMT00033 (IL ???... ???)
[000131] -AC--------- * ASG int
[000130] D------N---- +--* LCL_VAR int V15 tmp6
[000150] ------------ \--* MUL int
[000121] ------------ +--* LCL_VAR int V00 arg0
[000147] ------------ \--* CAST int <- int
[000122] ------------ \--* LCL_VAR ubyte V02 arg2
***** BB01
STMT00014 (IL ???... ???)
[000058] -AC--------- * ASG int
[000057] D------N---- +--* LCL_VAR int V07 loc4
[000156] ---X-------- \--* DIV int
[000132] ------------ +--* LCL_VAR int V15 tmp6
[000153] ------------ \--* RSH int
[000127] ------------ +--* LCL_VAR int V14 tmp5
[000152] ------------ \--* CNS_INT int 2
***** BB01
STMT00015 (IL ???...0x050)
[000069] ------------ * RETURN int
[000068] ------------ \--* ADD int
[000066] ------------ +--* ADD int
[000064] ------------ | +--* ADD int
[000062] ------------ | | +--* ADD int
[000060] ------------ | | | +--* ADD int
[000012] ------------ | | | | +--* LCL_VAR int V10 tmp1
[000059] ------------ | | | | \--* LCL_VAR int V03 loc0
[000061] ------------ | | | \--* LCL_VAR int V04 loc1
[000063] ------------ | | \--* LCL_VAR int V05 loc2
[000065] ------------ | \--* LCL_VAR int V06 loc3
[000067] ------------ \--* LCL_VAR int V07 loc4
-------------------------------------------------------------------------------------------------------------------
*** ObjectAllocationPhase: disabled, punting
*************** Exiting Allocate Objects
Trees after Allocate Objects
-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..051) (return) i newobj
-----------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [000..051) (return), preds={} succs={}
***** BB01
STMT00002 (IL ???... ???)
[000011] -AC--------- * ASG int
[000010] D------N---- +--* LCL_VAR int V10 tmp1
[000003] --C-G------- \--* CALL int Test2.DoTestImpl1
[000000] ------------ arg0 +--* LCL_VAR int V00 arg0
[000001] ------------ arg1 +--* LCL_VAR int V01 arg1
[000002] ------------ arg2 \--* LCL_VAR ubyte V02 arg2
***** BB01
STMT00003 (IL ???... ???)
[000015] -AC--------- * ASG int
[000014] D------N---- +--* LCL_VAR int V03 loc0
[000008] --C-G------- \--* CALL int Test2.DoTestImpl2
[000009] ------------ arg0 +--* CNS_INT(h) long 0xd1ffab1e method
[000005] ------------ arg1 +--* LCL_VAR int V00 arg0
[000006] ------------ arg2 +--* LCL_VAR int V01 arg1
[000007] ------------ arg3 \--* LCL_VAR ubyte V02 arg2
***** BB01
STMT00004 (IL ???...0x014)
[000019] IA---------- * ASG struct (init)
[000016] D------N---- +--* LCL_VAR struct V08 loc5
[000018] ------------ \--* CNS_INT int 0
***** BB01
STMT00006 (IL ???... ???)
[000029] -AC--------- * ASG int
[000028] D------N---- +--* LCL_VAR int V04 loc1
[000024] --C-G------- \--* CALL int Test2.DoTestImpl3
[000026] n----------- arg0 +--* OBJ(1) struct
[000025] ------------ | \--* ADDR byref
[000020] ------------ | \--* LCL_VAR struct V08 loc5
[000021] ------------ arg1 +--* LCL_VAR int V00 arg0
[000022] ------------ arg2 +--* LCL_VAR int V01 arg1
[000023] ------------ arg3 \--* LCL_VAR ubyte V02 arg2
***** BB01
STMT00007 (IL ???...0x031)
[000033] -AC--------- * ASG ref
[000032] D------N---- +--* LCL_VAR ref V11 tmp2
[000031] --C--------- \--* CALL help ref HELPER.CORINFO_HELP_NEWSFAST
[000030] ------------ arg0 \--* CNS_INT(h) long 0xd1ffab1e method
***** BB01
STMT00010 (IL ???... ???)
[000044] -AC--------- * ASG int
[000043] D------N---- +--* LCL_VAR int V05 loc2
[000040] --C-G------- \--* CALL int Test2.DoTestImpl4
[000041] ------------ arg0 +--* CNS_INT(h) long 0xd1ffab1e method
[000036] ------------ arg1 +--* LCL_VAR ref V11 tmp2
[000037] ------------ arg2 +--* LCL_VAR int V00 arg0
[000038] ------------ arg3 +--* LCL_VAR int V01 arg1
[000039] ------------ arg4 \--* LCL_VAR ubyte V02 arg2
***** BB01
STMT00012 (IL ???... ???)
[000051] -AC--------- * ASG int
[000050] D------N---- +--* LCL_VAR int V06 loc3
[000048] --C-G------- \--* CALL int Test2.DoTestImpl5
[000045] ------------ arg0 +--* LCL_VAR int V00 arg0
[000046] ------------ arg1 +--* LCL_VAR int V01 arg1
[000047] ------------ arg2 \--* LCL_VAR ubyte V02 arg2
***** BB01
STMT00022 (IL ???... ???)
[000101] IA---------- * ASG struct (init)
[000098] D------N---- +--* LCL_VAR struct V12 tmp3
[000100] ------------ \--* CNS_INT int 0
***** BB01
STMT00035 (IL ???... ???)
[000138] -A---------- * ASG int
[000137] D------N---- +--* LCL_VAR int V14 tmp5
[000136] ------------ \--* CNS_INT int 0
***** BB01
STMT00027 (IL ???... ???)
[000114] -AC--------- * ASG int
[000113] D------N---- +--* LCL_VAR int V13 tmp4
[000140] ------------ \--* ADD int
[000052] ------------ +--* LCL_VAR int V00 arg0
[000053] ------------ \--* LCL_VAR int V01 arg1
***** BB01
STMT00029 (IL ???... ???)
[000120] -AC--------- * ASG int
[000119] D------N---- +--* LCL_VAR int V14 tmp5
[000145] ------------ \--* MUL int
[000115] ------------ +--* LCL_VAR int V13 tmp4
[000142] ------------ \--* CAST int <- int
[000054] ------------ \--* LCL_VAR ubyte V02 arg2
***** BB01
STMT00033 (IL ???... ???)
[000131] -AC--------- * ASG int
[000130] D------N---- +--* LCL_VAR int V15 tmp6
[000150] ------------ \--* MUL int
[000121] ------------ +--* LCL_VAR int V00 arg0
[000147] ------------ \--* CAST int <- int
[000122] ------------ \--* LCL_VAR ubyte V02 arg2
***** BB01
STMT00014 (IL ???... ???)
[000058] -AC--------- * ASG int
[000057] D------N---- +--* LCL_VAR int V07 loc4
[000156] ---X-------- \--* DIV int
[000132] ------------ +--* LCL_VAR int V15 tmp6
[000153] ------------ \--* RSH int
[000127] ------------ +--* LCL_VAR int V14 tmp5
[000152] ------------ \--* CNS_INT int 2
***** BB01
STMT00015 (IL ???...0x050)
[000069] ------------ * RETURN int
[000068] ------------ \--* ADD int
[000066] ------------ +--* ADD int
[000064] ------------ | +--* ADD int
[000062] ------------ | | +--* ADD int
[000060] ------------ | | | +--* ADD int
[000012] ------------ | | | | +--* LCL_VAR int V10 tmp1
[000059] ------------ | | | | \--* LCL_VAR int V03 loc0
[000061] ------------ | | | \--* LCL_VAR int V04 loc1
[000063] ------------ | | \--* LCL_VAR int V05 loc2
[000065] ------------ | \--* LCL_VAR int V06 loc3
[000067] ------------ \--* LCL_VAR int V07 loc4
-------------------------------------------------------------------------------------------------------------------
*************** After fgAddInternal()
-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..051) (return) i newobj
-----------------------------------------------------------------------------------------------------------------------------------------
*************** Exception Handling table is empty
*************** In fgDebugCheckBBlist
*************** In fgRemoveEmptyTry()
No EH in this method, nothing to remove.
*************** In fgRemoveEmptyFinally()
No EH in this method, nothing to remove.
*************** In fgMergeFinallyChains()
No EH in this method, nothing to merge.
*************** In fgCloneFinally()
No EH in this method, no cloning.
*************** In fgResetImplicitByRefRefCount()
*************** In fgPromoteStructs()
lvaTable before fgPromoteStructs
; Initial local variable assignments
;
; V00 arg0 int
; V01 arg1 int
; V02 arg2 ubyte
; V03 loc0 int
; V04 loc1 int
; V05 loc2 int
; V06 loc3 int
; V07 loc4 int
; V08 loc5 struct ( 8) ld-addr-op
; V09 OutArgs lclBlk (na) "OutgoingArgSpace"
; V10 tmp1 int "impAppendStmt"
; V11 tmp2 ref class-hnd exact "NewObj constructor temp"
; V12 tmp3 struct ( 8) ld-addr-op "Inline ldloca(s) first use temp"
; V13 tmp4 int "impAppendStmt"
; V14 tmp5 int "Inline stloc first use temp"
; V15 tmp6 int "impAppendStmt"
; V16 tmp7 int "Inlining Arg"
; V17 tmp8 int "Inlining Arg"
; V18 tmp9 int "Inlining Arg"
lvaTable after fgPromoteStructs
; Initial local variable assignments
;
; V00 arg0 int
; V01 arg1 int
; V02 arg2 ubyte
; V03 loc0 int
; V04 loc1 int
; V05 loc2 int
; V06 loc3 int
; V07 loc4 int
; V08 loc5 struct ( 8) ld-addr-op
; V09 OutArgs lclBlk (na) "OutgoingArgSpace"
; V10 tmp1 int "impAppendStmt"
; V11 tmp2 ref class-hnd exact "NewObj constructor temp"
; V12 tmp3 struct ( 8) ld-addr-op "Inline ldloca(s) first use temp"
; V13 tmp4 int "impAppendStmt"
; V14 tmp5 int "Inline stloc first use temp"
; V15 tmp6 int "impAppendStmt"
; V16 tmp7 int "Inlining Arg"
; V17 tmp8 int "Inlining Arg"
; V18 tmp9 int "Inlining Arg"
*************** In fgMarkAddressExposedLocals()
LocalAddressVisitor visiting statement:
STMT00002 (IL ???... ???)
[000011] -AC--------- * ASG int
[000010] D------N---- +--* LCL_VAR int V10 tmp1
[000003] --C-G------- \--* CALL int Test2.DoTestImpl1
[000000] ------------ arg0 +--* LCL_VAR int V00 arg0
[000001] ------------ arg1 +--* LCL_VAR int V01 arg1
[000002] ------------ arg2 \--* LCL_VAR ubyte V02 arg2
LocalAddressVisitor visiting statement:
STMT00003 (IL ???... ???)
[000015] -AC--------- * ASG int
[000014] D------N---- +--* LCL_VAR int V03 loc0
[000008] --C-G------- \--* CALL int Test2.DoTestImpl2
[000009] ------------ arg0 +--* CNS_INT(h) long 0xd1ffab1e method
[000005] ------------ arg1 +--* LCL_VAR int V00 arg0
[000006] ------------ arg2 +--* LCL_VAR int V01 arg1
[000007] ------------ arg3 \--* LCL_VAR ubyte V02 arg2
LocalAddressVisitor visiting statement:
STMT00004 (IL ???...0x014)
[000019] IA---------- * ASG struct (init)
[000016] D------N---- +--* LCL_VAR struct V08 loc5
[000018] ------------ \--* CNS_INT int 0
LocalAddressVisitor visiting statement:
STMT00006 (IL ???... ???)
[000029] -AC--------- * ASG int
[000028] D------N---- +--* LCL_VAR int V04 loc1
[000024] --C-G------- \--* CALL int Test2.DoTestImpl3
[000026] n----------- arg0 +--* OBJ(1) struct
[000025] ------------ | \--* ADDR byref
[000020] ------------ | \--* LCL_VAR struct V08 loc5
[000021] ------------ arg1 +--* LCL_VAR int V00 arg0
[000022] ------------ arg2 +--* LCL_VAR int V01 arg1
[000023] ------------ arg3 \--* LCL_VAR ubyte V02 arg2
LocalAddressVisitor visiting statement:
STMT00007 (IL ???...0x031)
[000033] -AC--------- * ASG ref
[000032] D------N---- +--* LCL_VAR ref V11 tmp2
[000031] --C--------- \--* CALL help ref HELPER.CORINFO_HELP_NEWSFAST
[000030] ------------ arg0 \--* CNS_INT(h) long 0xd1ffab1e method
LocalAddressVisitor visiting statement:
STMT00010 (IL ???... ???)
[000044] -AC--------- * ASG int
[000043] D------N---- +--* LCL_VAR int V05 loc2
[000040] --C-G------- \--* CALL int Test2.DoTestImpl4
[000041] ------------ arg0 +--* CNS_INT(h) long 0xd1ffab1e method
[000036] ------------ arg1 +--* LCL_VAR ref V11 tmp2
[000037] ------------ arg2 +--* LCL_VAR int V00 arg0
[000038] ------------ arg3 +--* LCL_VAR int V01 arg1
[000039] ------------ arg4 \--* LCL_VAR ubyte V02 arg2
LocalAddressVisitor visiting statement:
STMT00012 (IL ???... ???)
[000051] -AC--------- * ASG int
[000050] D------N---- +--* LCL_VAR int V06 loc3
[000048] --C-G------- \--* CALL int Test2.DoTestImpl5
[000045] ------------ arg0 +--* LCL_VAR int V00 arg0
[000046] ------------ arg1 +--* LCL_VAR int V01 arg1
[000047] ------------ arg2 \--* LCL_VAR ubyte V02 arg2
LocalAddressVisitor visiting statement:
STMT00022 (IL ???... ???)
[000101] IA---------- * ASG struct (init)
[000098] D------N---- +--* LCL_VAR struct V12 tmp3
[000100] ------------ \--* CNS_INT int 0
LocalAddressVisitor visiting statement:
STMT00035 (IL ???... ???)
[000138] -A---------- * ASG int
[000137] D------N---- +--* LCL_VAR int V14 tmp5
[000136] ------------ \--* CNS_INT int 0
LocalAddressVisitor visiting statement:
STMT00027 (IL ???... ???)
[000114] -AC--------- * ASG int
[000113] D------N---- +--* LCL_VAR int V13 tmp4
[000140] ------------ \--* ADD int
[000052] ------------ +--* LCL_VAR int V00 arg0
[000053] ------------ \--* LCL_VAR int V01 arg1
LocalAddressVisitor visiting statement:
STMT00029 (IL ???... ???)
[000120] -AC--------- * ASG int
[000119] D------N---- +--* LCL_VAR int V14 tmp5
[000145] ------------ \--* MUL int
[000115] ------------ +--* LCL_VAR int V13 tmp4
[000142] ------------ \--* CAST int <- int
[000054] ------------ \--* LCL_VAR ubyte V02 arg2
LocalAddressVisitor visiting statement:
STMT00033 (IL ???... ???)
[000131] -AC--------- * ASG int
[000130] D------N---- +--* LCL_VAR int V15 tmp6
[000150] ------------ \--* MUL int
[000121] ------------ +--* LCL_VAR int V00 arg0
[000147] ------------ \--* CAST int <- int
[000122] ------------ \--* LCL_VAR ubyte V02 arg2
LocalAddressVisitor visiting statement:
STMT00014 (IL ???... ???)
[000058] -AC--------- * ASG int
[000057] D------N---- +--* LCL_VAR int V07 loc4
[000156] ---X-------- \--* DIV int
[000132] ------------ +--* LCL_VAR int V15 tmp6
[000153] ------------ \--* RSH int
[000127] ------------ +--* LCL_VAR int V14 tmp5
[000152] ------------ \--* CNS_INT int 2
LocalAddressVisitor visiting statement:
STMT00015 (IL ???...0x050)
[000069] ------------ * RETURN int
[000068] ------------ \--* ADD int
[000066] ------------ +--* ADD int
[000064] ------------ | +--* ADD int
[000062] ------------ | | +--* ADD int
[000060] ------------ | | | +--* ADD int
[000012] ------------ | | | | +--* LCL_VAR int V10 tmp1
[000059] ------------ | | | | \--* LCL_VAR int V03 loc0
[000061] ------------ | | | \--* LCL_VAR int V04 loc1
[000063] ------------ | | \--* LCL_VAR int V05 loc2
[000065] ------------ | \--* LCL_VAR int V06 loc3
[000067] ------------ \--* LCL_VAR int V07 loc4
*************** In fgRetypeImplicitByRefArgs()
*************** In fgMorphBlocks()
Morphing BB01 of 'Test2:DoTest(int,int,ubyte):int'
fgMorphTree BB01, STMT00002 (before)
[000011] -AC--------- * ASG int
[000010] D------N---- +--* LCL_VAR int V10 tmp1
[000003] --C-G------- \--* CALL int Test2.DoTestImpl1
[000000] ------------ arg0 +--* LCL_VAR int V00 arg0
[000001] ------------ arg1 +--* LCL_VAR int V01 arg1
[000002] ------------ arg2 \--* LCL_VAR ubyte V02 arg2
Initializing arg info for 3.CALL:
ArgTable for 3.CALL after fgInitArgInfo:
fgArgTabEntry[arg 0 0.LCL_VAR int, 1 reg: rcx, align=1]
fgArgTabEntry[arg 1 1.LCL_VAR int, 1 reg: rdx, align=1]
fgArgTabEntry[arg 2 2.LCL_VAR ubyte, 1 reg: r8, align=1]
Morphing args for 3.CALL:
argSlots=3, preallocatedArgCount=4, nextSlotNum=4, outgoingArgSpaceSize=32
Sorting the arguments:
Deferred argument ('r8'):
[000158] -----+------ * CAST int <- ubyte <- int
[000002] -----+------ \--* LCL_VAR int V02 arg2
Replaced with placeholder node:
[000159] ----------L- * ARGPLACE int
Deferred argument ('rcx'):
[000000] -----+------ * LCL_VAR int V00 arg0
Replaced with placeholder node:
[000160] ----------L- * ARGPLACE int
Deferred argument ('rdx'):
[000001] -----+------ * LCL_VAR int V01 arg1
Replaced with placeholder node:
[000161] ----------L- * ARGPLACE int
Shuffled argument table: r8 rcx rdx
ArgTable for 3.CALL after fgMorphArgs:
fgArgTabEntry[arg 2 158.CAST ubyte, 1 reg: r8, align=1, lateArgInx=0, processed]
fgArgTabEntry[arg 0 0.LCL_VAR int, 1 reg: rcx, align=1, lateArgInx=1, processed]
fgArgTabEntry[arg 1 1.LCL_VAR int, 1 reg: rdx, align=1, lateArgInx=2, processed]
fgMorphTree BB01, STMT00002 (after)
[000011] -ACXG+------ * ASG int
[000010] D----+-N---- +--* LCL_VAR int V10 tmp1
[000003] --CXG+------ \--* CALL int Test2.DoTestImpl1
[000158] -----+------ arg2 in r8 +--* CAST int <- ubyte <- int
[000002] -----+------ | \--* LCL_VAR int V02 arg2
[000000] -----+------ arg0 in rcx +--* LCL_VAR int V00 arg0
[000001] -----+------ arg1 in rdx \--* LCL_VAR int V01 arg1
fgMorphTree BB01, STMT00003 (before)
[000015] -AC--------- * ASG int
[000014] D------N---- +--* LCL_VAR int V03 loc0
[000008] --C-G------- \--* CALL int Test2.DoTestImpl2
[000009] ------------ arg0 +--* CNS_INT(h) long 0xd1ffab1e method
[000005] ------------ arg1 +--* LCL_VAR int V00 arg0
[000006] ------------ arg2 +--* LCL_VAR int V01 arg1
[000007] ------------ arg3 \--* LCL_VAR ubyte V02 arg2
Initializing arg info for 8.CALL:
ArgTable for 8.CALL after fgInitArgInfo:
fgArgTabEntry[arg 0 9.CNS_INT long, 1 reg: rcx, align=1]
fgArgTabEntry[arg 1 5.LCL_VAR int, 1 reg: rdx, align=1]
fgArgTabEntry[arg 2 6.LCL_VAR int, 1 reg: r8, align=1]
fgArgTabEntry[arg 3 7.LCL_VAR ubyte, 1 reg: r9, align=1]
Morphing args for 8.CALL:
argSlots=4, preallocatedArgCount=4, nextSlotNum=4, outgoingArgSpaceSize=32
Sorting the arguments:
Deferred argument ('r9'):
[000162] -----+------ * CAST int <- ubyte <- int
[000007] -----+------ \--* LCL_VAR int V02 arg2
Replaced with placeholder node:
[000163] ----------L- * ARGPLACE int
Deferred argument ('rdx'):
[000005] -----+------ * LCL_VAR int V00 arg0
Replaced with placeholder node:
[000164] ----------L- * ARGPLACE int
Deferred argument ('r8'):
[000006] -----+------ * LCL_VAR int V01 arg1
Replaced with placeholder node:
[000165] ----------L- * ARGPLACE int
Deferred argument ('rcx'):
[000009] -----+------ * CNS_INT(h) long 0xd1ffab1e method
Replaced with placeholder node:
[000166] ----------L- * ARGPLACE long
Shuffled argument table: r9 rdx r8 rcx
ArgTable for 8.CALL after fgMorphArgs:
fgArgTabEntry[arg 3 162.CAST ubyte, 1 reg: r9, align=1, lateArgInx=0, processed]
fgArgTabEntry[arg 1 5.LCL_VAR int, 1 reg: rdx, align=1, lateArgInx=1, processed]
fgArgTabEntry[arg 2 6.LCL_VAR int, 1 reg: r8, align=1, lateArgInx=2, processed]
fgArgTabEntry[arg 0 9.CNS_INT long, 1 reg: rcx, align=1, lateArgInx=3, processed]
fgMorphTree BB01, STMT00003 (after)
[000015] -ACXG+------ * ASG int
[000014] D----+-N---- +--* LCL_VAR int V03 loc0
[000008] --CXG+------ \--* CALL int Test2.DoTestImpl2
[000162] -----+------ arg3 in r9 +--* CAST int <- ubyte <- int
[000007] -----+------ | \--* LCL_VAR int V02 arg2
[000005] -----+------ arg1 in rdx +--* LCL_VAR int V00 arg0
[000006] -----+------ arg2 in r8 +--* LCL_VAR int V01 arg1
[000009] -----+------ arg0 in rcx \--* CNS_INT(h) long 0xd1ffab1e method
fgMorphTree BB01, STMT00004 (before)
[000019] IA---------- * ASG struct (init)
[000016] D------N---- +--* LCL_VAR struct V08 loc5
[000018] ------------ \--* CNS_INT int 0
fgMorphInitBlock:
Local V08 should not be enregistered because: was accessed as a local field
fgMorphOneAsgBlock (after):
[000019] -A---------- * ASG byte
[000168] n------N---- +--* IND byte
[000167] ------------ | \--* ADDR byref
[000016] D----+-N---- | \--* LCL_VAR struct V08 loc5
[000018] -----+------ \--* CNS_INT int 0
using oneAsgTree.
fgMorphTree BB01, STMT00004 (after)
[000019] -A---+------ * ASG byte
[000168] n------N---- +--* IND byte
[000167] ------------ | \--* ADDR byref
[000016] D----+-N---- | \--* LCL_VAR struct V08 loc5
[000018] -----+------ \--* CNS_INT int 0
fgMorphTree BB01, STMT00006 (before)
[000029] -AC--------- * ASG int
[000028] D------N---- +--* LCL_VAR int V04 loc1
[000024] --C-G------- \--* CALL int Test2.DoTestImpl3
[000026] n----------- arg0 +--* OBJ(1) struct
[000025] ------------ | \--* ADDR byref
[000020] ------------ | \--* LCL_VAR struct V08 loc5
[000021] ------------ arg1 +--* LCL_VAR int V00 arg0
[000022] ------------ arg2 +--* LCL_VAR int V01 arg1
[000023] ------------ arg3 \--* LCL_VAR ubyte V02 arg2
Initializing arg info for 24.CALL:
ArgTable for 24.CALL after fgInitArgInfo:
fgArgTabEntry[arg 0 26.OBJ byte, 1 reg: rcx, align=1, isStruct]
fgArgTabEntry[arg 1 21.LCL_VAR int, 1 reg: rdx, align=1]
fgArgTabEntry[arg 2 22.LCL_VAR int, 1 reg: r8, align=1]
fgArgTabEntry[arg 3 23.LCL_VAR ubyte, 1 reg: r9, align=1]
Morphing args for 24.CALL:
argSlots=4, preallocatedArgCount=4, nextSlotNum=4, outgoingArgSpaceSize=32
Sorting the arguments:
Deferred argument ('r9'):
[000169] -----+------ * CAST int <- ubyte <- int
[000023] -----+------ \--* LCL_VAR int V02 arg2
Replaced with placeholder node:
[000170] ----------L- * ARGPLACE int
Deferred argument ('rcx'):
[000020] -----+------ * LCL_FLD byte V08 loc5 [+0]
Replaced with placeholder node:
[000171] ----------L- * ARGPLACE byte
Deferred argument ('rdx'):
[000021] -----+------ * LCL_VAR int V00 arg0
Replaced with placeholder node:
[000172] ----------L- * ARGPLACE int
Deferred argument ('r8'):
[000022] -----+------ * LCL_VAR int V01 arg1
Replaced with placeholder node:
[000173] ----------L- * ARGPLACE int
Shuffled argument table: r9 rcx rdx r8
ArgTable for 24.CALL after fgMorphArgs:
fgArgTabEntry[arg 3 169.CAST ubyte, 1 reg: r9, align=1, lateArgInx=0, processed]
fgArgTabEntry[arg 0 20.LCL_FLD byte, 1 reg: rcx, align=1, lateArgInx=1, processed, isStruct]
fgArgTabEntry[arg 1 21.LCL_VAR int, 1 reg: rdx, align=1, lateArgInx=2, processed]
fgArgTabEntry[arg 2 22.LCL_VAR int, 1 reg: r8, align=1, lateArgInx=3, processed]
fgMorphTree BB01, STMT00006 (after)
[000029] -ACXG+------ * ASG int
[000028] D----+-N---- +--* LCL_VAR int V04 loc1
[000024] --CXG+------ \--* CALL int Test2.DoTestImpl3
[000169] -----+------ arg3 in r9 +--* CAST int <- ubyte <- int
[000023] -----+------ | \--* LCL_VAR int V02 arg2
[000020] -----+------ arg0 in rcx +--* LCL_FLD byte V08 loc5 [+0]
[000021] -----+------ arg1 in rdx +--* LCL_VAR int V00 arg0
[000022] -----+------ arg2 in r8 \--* LCL_VAR int V01 arg1
fgMorphTree BB01, STMT00007 (before)
[000033] -AC--------- * ASG ref
[000032] D------N---- +--* LCL_VAR ref V11 tmp2
[000031] --C--------- \--* CALL help ref HELPER.CORINFO_HELP_NEWSFAST
[000030] ------------ arg0 \--* CNS_INT(h) long 0xd1ffab1e method
Initializing arg info for 31.CALL:
ArgTable for 31.CALL after fgInitArgInfo:
fgArgTabEntry[arg 0 30.CNS_INT long, 1 reg: rcx, align=1]
Morphing args for 31.CALL:
argSlots=1, preallocatedArgCount=4, nextSlotNum=4, outgoingArgSpaceSize=32
Sorting the arguments:
Deferred argument ('rcx'):
[000030] -----+------ * CNS_INT(h) long 0xd1ffab1e method
Replaced with placeholder node:
[000174] ----------L- * ARGPLACE long
Shuffled argument table: rcx
ArgTable for 31.CALL after fgMorphArgs:
fgArgTabEntry[arg 0 30.CNS_INT long, 1 reg: rcx, align=1, lateArgInx=0, processed]
fgMorphTree BB01, STMT00007 (after)
[000033] -AC--+------ * ASG ref
[000032] D----+-N---- +--* LCL_VAR ref V11 tmp2
[000031] --C--+------ \--* CALL help ref HELPER.CORINFO_HELP_NEWSFAST
[000030] -----+------ arg0 in rcx \--* CNS_INT(h) long 0xd1ffab1e method
fgMorphTree BB01, STMT00010 (before)
[000044] -AC--------- * ASG int
[000043] D------N---- +--* LCL_VAR int V05 loc2
[000040] --C-G------- \--* CALL int Test2.DoTestImpl4
[000041] ------------ arg0 +--* CNS_INT(h) long 0xd1ffab1e method
[000036] ------------ arg1 +--* LCL_VAR ref V11 tmp2
[000037] ------------ arg2 +--* LCL_VAR int V00 arg0
[000038] ------------ arg3 +--* LCL_VAR int V01 arg1
[000039] ------------ arg4 \--* LCL_VAR ubyte V02 arg2
Initializing arg info for 40.CALL:
ArgTable for 40.CALL after fgInitArgInfo:
fgArgTabEntry[arg 0 41.CNS_INT long, 1 reg: rcx, align=1]
fgArgTabEntry[arg 1 36.LCL_VAR ref, 1 reg: rdx, align=1]
fgArgTabEntry[arg 2 37.LCL_VAR int, 1 reg: r8, align=1]
fgArgTabEntry[arg 3 38.LCL_VAR int, 1 reg: r9, align=1]
fgArgTabEntry[arg 4 39.LCL_VAR ubyte, numSlots=1, slotNum=4, align=1]
Morphing args for 40.CALL:
argSlots=5, preallocatedArgCount=5, nextSlotNum=5, outgoingArgSpaceSize=40
Sorting the arguments:
Deferred argument ('rdx'):
[000036] -----+------ * LCL_VAR ref V11 tmp2
Replaced with placeholder node:
[000176] ----------L- * ARGPLACE ref
Deferred argument ('r8'):
[000037] -----+------ * LCL_VAR int V00 arg0
Replaced with placeholder node:
[000177] ----------L- * ARGPLACE int
Deferred argument ('r9'):
[000038] -----+------ * LCL_VAR int V01 arg1
Replaced with placeholder node:
[000178] ----------L- * ARGPLACE int
Deferred argument ('rcx'):
[000041] -----+------ * CNS_INT(h) long 0xd1ffab1e method
Replaced with placeholder node:
[000179] ----------L- * ARGPLACE long
Shuffled argument table: rdx r8 r9 rcx
ArgTable for 40.CALL after fgMorphArgs:
fgArgTabEntry[arg 4 175.CAST ubyte, numSlots=1, slotNum=4, align=1, processed]
fgArgTabEntry[arg 1 36.LCL_VAR ref, 1 reg: rdx, align=1, lateArgInx=0, processed]
fgArgTabEntry[arg 2 37.LCL_VAR int, 1 reg: r8, align=1, lateArgInx=1, processed]
fgArgTabEntry[arg 3 38.LCL_VAR int, 1 reg: r9, align=1, lateArgInx=2, processed]
fgArgTabEntry[arg 0 41.CNS_INT long, 1 reg: rcx, align=1, lateArgInx=3, processed]
fgMorphTree BB01, STMT00010 (after)
[000044] -ACXG+------ * ASG int
[000043] D----+-N---- +--* LCL_VAR int V05 loc2
[000040] --CXG+------ \--* CALL int Test2.DoTestImpl4
[000175] -----+------ arg4 out+20 +--* CAST int <- ubyte <- int
[000039] -----+------ | \--* LCL_VAR int V02 arg2
[000036] -----+------ arg1 in rdx +--* LCL_VAR ref V11 tmp2
[000037] -----+------ arg2 in r8 +--* LCL_VAR int V00 arg0
[000038] -----+------ arg3 in r9 +--* LCL_VAR int V01 arg1
[000041] -----+------ arg0 in rcx \--* CNS_INT(h) long 0xd1ffab1e method
fgMorphTree BB01, STMT00012 (before)
[000051] -AC--------- * ASG int
[000050] D------N---- +--* LCL_VAR int V06 loc3
[000048] --C-G------- \--* CALL int Test2.DoTestImpl5
[000045] ------------ arg0 +--* LCL_VAR int V00 arg0
[000046] ------------ arg1 +--* LCL_VAR int V01 arg1
[000047] ------------ arg2 \--* LCL_VAR ubyte V02 arg2
Initializing arg info for 48.CALL:
ArgTable for 48.CALL after fgInitArgInfo:
fgArgTabEntry[arg 0 45.LCL_VAR int, 1 reg: rcx, align=1]
fgArgTabEntry[arg 1 46.LCL_VAR int, 1 reg: rdx, align=1]
fgArgTabEntry[arg 2 47.LCL_VAR ubyte, 1 reg: r8, align=1]
Morphing args for 48.CALL:
argSlots=3, preallocatedArgCount=4, nextSlotNum=4, outgoingArgSpaceSize=32
Sorting the arguments:
Deferred argument ('r8'):
[000180] -----+------ * CAST int <- ubyte <- int
[000047] -----+------ \--* LCL_VAR int V02 arg2
Replaced with placeholder node:
[000181] ----------L- * ARGPLACE int
Deferred argument ('rcx'):
[000045] -----+------ * LCL_VAR int V00 arg0
Replaced with placeholder node:
[000182] ----------L- * ARGPLACE int
Deferred argument ('rdx'):
[000046] -----+------ * LCL_VAR int V01 arg1
Replaced with placeholder node:
[000183] ----------L- * ARGPLACE int
Shuffled argument table: r8 rcx rdx
ArgTable for 48.CALL after fgMorphArgs:
fgArgTabEntry[arg 2 180.CAST ubyte, 1 reg: r8, align=1, lateArgInx=0, processed]
fgArgTabEntry[arg 0 45.LCL_VAR int, 1 reg: rcx, align=1, lateArgInx=1, processed]
fgArgTabEntry[arg 1 46.LCL_VAR int, 1 reg: rdx, align=1, lateArgInx=2, processed]
fgMorphTree BB01, STMT00012 (after)
[000051] -ACXG+------ * ASG int
[000050] D----+-N---- +--* LCL_VAR int V06 loc3
[000048] --CXG+------ \--* CALL int Test2.DoTestImpl5
[000180] -----+------ arg2 in r8 +--* CAST int <- ubyte <- int
[000047] -----+------ | \--* LCL_VAR int V02 arg2
[000045] -----+------ arg0 in rcx +--* LCL_VAR int V00 arg0
[000046] -----+------ arg1 in rdx \--* LCL_VAR int V01 arg1
fgMorphTree BB01, STMT00022 (before)
[000101] IA---------- * ASG struct (init)
[000098] D------N---- +--* LCL_VAR struct V12 tmp3
[000100] ------------ \--* CNS_INT int 0
fgMorphInitBlock:
Local V12 should not be enregistered because: was accessed as a local field
fgMorphOneAsgBlock (after):
[000101] -A---------- * ASG byte
[000185] n------N---- +--* IND byte
[000184] ------------ | \--* ADDR byref
[000098] D----+-N---- | \--* LCL_VAR struct V12 tmp3
[000100] -----+------ \--* CNS_INT int 0
using oneAsgTree.
fgMorphTree BB01, STMT00022 (after)
[000101] -A---+------ * ASG byte
[000185] n------N---- +--* IND byte
[000184] ------------ | \--* ADDR byref
[000098] D----+-N---- | \--* LCL_VAR struct V12 tmp3
[000100] -----+------ \--* CNS_INT int 0
fgMorphTree BB01, STMT00035 (before)
[000138] -A---------- * ASG int
[000137] D------N---- +--* LCL_VAR int V14 tmp5
[000136] ------------ \--* CNS_INT int 0
GenTreeNode creates assertion:
[000138] -A---------- * ASG int
In BB01 New Local Constant Assertion: V14 == 0 index=#01, mask=0000000000000001
fgMorphTree BB01, STMT00027 (before)
[000114] -AC--------- * ASG int
[000113] D------N---- +--* LCL_VAR int V13 tmp4
[000140] ------------ \--* ADD int
[000052] ------------ +--* LCL_VAR int V00 arg0
[000053] ------------ \--* LCL_VAR int V01 arg1
fgMorphTree BB01, STMT00029 (before)
[000120] -AC--------- * ASG int
[000119] D------N---- +--* LCL_VAR int V14 tmp5
[000145] ------------ \--* MUL int
[000115] ------------ +--* LCL_VAR int V13 tmp4
[000142] ------------ \--* CAST int <- int
[000054] ------------ \--* LCL_VAR ubyte V02 arg2
The assignment [000120] using V14 removes: Constant Assertion: V14 == 0
fgMorphTree BB01, STMT00029 (after)
[000120] -A---+------ * ASG int
[000119] D----+-N---- +--* LCL_VAR int V14 tmp5
[000145] -----+------ \--* MUL int
[000115] -----+------ +--* LCL_VAR int V13 tmp4
[000186] -----+------ \--* CAST int <- ubyte <- int
[000054] -----+------ \--* LCL_VAR int V02 arg2
fgMorphTree BB01, STMT00033 (before)
[000131] -AC--------- * ASG int
[000130] D------N---- +--* LCL_VAR int V15 tmp6
[000150] ------------ \--* MUL int
[000121] ------------ +--* LCL_VAR int V00 arg0
[000147] ------------ \--* CAST int <- int
[000122] ------------ \--* LCL_VAR ubyte V02 arg2
fgMorphTree BB01, STMT00033 (after)
[000131] -A---+------ * ASG int
[000130] D----+-N---- +--* LCL_VAR int V15 tmp6
[000150] -----+------ \--* MUL int
[000121] -----+------ +--* LCL_VAR int V00 arg0
[000187] -----+------ \--* CAST int <- ubyte <- int
[000122] -----+------ \--* LCL_VAR int V02 arg2
fgMorphTree BB01, STMT00014 (before)
[000058] -AC--------- * ASG int
[000057] D------N---- +--* LCL_VAR int V07 loc4
[000156] ---X-------- \--* DIV int
[000132] ------------ +--* LCL_VAR int V15 tmp6
[000153] ------------ \--* RSH int
[000127] ------------ +--* LCL_VAR int V14 tmp5
[000152] ------------ \--* CNS_INT int 2
fgMorphTree BB01, STMT00015 (before)
[000069] ------------ * RETURN int
[000068] ------------ \--* ADD int
[000066] ------------ +--* ADD int
[000064] ------------ | +--* ADD int
[000062] ------------ | | +--* ADD int
[000060] ------------ | | | +--* ADD int
[000012] ------------ | | | | +--* LCL_VAR int V10 tmp1
[000059] ------------ | | | | \--* LCL_VAR int V03 loc0
[000061] ------------ | | | \--* LCL_VAR int V04 loc1
[000063] ------------ | | \--* LCL_VAR int V05 loc2
[000065] ------------ | \--* LCL_VAR int V06 loc3
[000067] ------------ \--* LCL_VAR int V07 loc4
Renumbering the basic blocks for fgComputePred
*************** Before renumbering the basic blocks
-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..051) (return) i gcsafe newobj
-----------------------------------------------------------------------------------------------------------------------------------------
*************** Exception Handling table is empty
*************** After renumbering the basic blocks
=============== No blocks renumbered!
New BlockSet epoch 2, # of blocks (including unused BB00): 2, bitset array size: 1 (short)
*************** In fgComputePreds()
-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..051) (return) i gcsafe newobj
-----------------------------------------------------------------------------------------------------------------------------------------
*************** After fgComputePreds()
-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..051) (return) i label target gcsafe newobj
-----------------------------------------------------------------------------------------------------------------------------------------
*************** In fgComputeBlockAndEdgeWeights()
-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..051) (return) i label target gcsafe newobj
-----------------------------------------------------------------------------------------------------------------------------------------
-- no profile data, so using default called count
fgComputeEdgeWeights() was able to compute exact edge weights for all of the 0 edges, using 1 passes.
*************** In fgCreateFunclets()
After fgCreateFunclets()
-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..051) (return) i label target gcsafe newobj
-----------------------------------------------------------------------------------------------------------------------------------------
*************** Exception Handling table is empty
*************** In fgDebugCheckBBlist
*************** In optOptimizeLayout()
*************** Exception Handling table is empty
*************** In fgDebugCheckBBlist
*************** In fgUpdateFlowGraph()
Before updating the flow graph:
-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..051) (return) i label target gcsafe newobj
-----------------------------------------------------------------------------------------------------------------------------------------
*************** In fgDebugCheckBBlist
*************** In fgUpdateFlowGraph()
Before updating the flow graph:
-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..051) (return) i label target gcsafe newobj
-----------------------------------------------------------------------------------------------------------------------------------------
*************** In fgDebugCheckBBlist
*************** In fgComputeReachability
*************** In fgDebugCheckBBlist
Renumbering the basic blocks for fgComputeReachability pass #1
*************** Before renumbering the basic blocks
-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..051) (return) i label target gcsafe newobj
-----------------------------------------------------------------------------------------------------------------------------------------
*************** Exception Handling table is empty
*************** After renumbering the basic blocks
=============== No blocks renumbered!
Enter blocks: BB01
After computing reachability sets:
------------------------------------------------
BBnum Reachable by
------------------------------------------------
BB01 : BB01
After computing reachability:
-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..051) (return) i label target gcsafe newobj
-----------------------------------------------------------------------------------------------------------------------------------------
*************** In fgDebugCheckBBlist
*************** In fgComputeDoms
*************** In fgDebugCheckBBlist
Dominator computation start blocks (those blocks with no incoming edges):
BB01
------------------------------------------------
BBnum Dominated by
------------------------------------------------
BB01: BB01
Inside fgBuildDomTree
After computing the Dominance Tree:
*************** In optOptimizeLoops()
*************** In fgDebugCheckBBlist
*************** In optCloneLoops()
*************** In lvaMarkLocalVars()
*** lvaComputeRefCounts ***
*** lvaComputeRefCounts -- explicit counts ***
*** marking local variables in block BB01 (weight=1 )
STMT00002 (IL ???... ???)
[000011] -ACXG+------ * ASG int
[000010] D----+-N---- +--* LCL_VAR int V10 tmp1
[000003] --CXG+------ \--* CALL int Test2.DoTestImpl1
[000158] -----+------ arg2 in r8 +--* CAST int <- ubyte <- int
[000002] -----+------ | \--* LCL_VAR int V02 arg2
[000000] -----+------ arg0 in rcx +--* LCL_VAR int V00 arg0
[000001] -----+------ arg1 in rdx \--* LCL_VAR int V01 arg1
New refCnts for V10: refCnt = 1, refCntWtd = 2
New refCnts for V02: refCnt = 1, refCntWtd = 1
New refCnts for V00: refCnt = 1, refCntWtd = 1
New refCnts for V01: refCnt = 1, refCntWtd = 1
STMT00003 (IL ???... ???)
[000015] -ACXG+------ * ASG int
[000014] D----+-N---- +--* LCL_VAR int V03 loc0
[000008] --CXG+------ \--* CALL int Test2.DoTestImpl2
[000162] -----+------ arg3 in r9 +--* CAST int <- ubyte <- int
[000007] -----+------ | \--* LCL_VAR int V02 arg2
[000005] -----+------ arg1 in rdx +--* LCL_VAR int V00 arg0
[000006] -----+------ arg2 in r8 +--* LCL_VAR int V01 arg1
[000009] -----+------ arg0 in rcx \--* CNS_INT(h) long 0xd1ffab1e method
New refCnts for V03: refCnt = 1, refCntWtd = 1
New refCnts for V02: refCnt = 2, refCntWtd = 2
New refCnts for V00: refCnt = 2, refCntWtd = 2
New refCnts for V01: refCnt = 2, refCntWtd = 2
STMT00004 (IL ???...0x014)
[000019] -A---+------ * ASG byte
[000168] n------N---- +--* IND byte
[000167] ------------ | \--* ADDR byref
[000016] D----+-N---- | \--* LCL_VAR struct V08 loc5
[000018] -----+------ \--* CNS_INT int 0
New refCnts for V08: refCnt = 1, refCntWtd = 1
STMT00006 (IL ???... ???)
[000029] -ACXG+------ * ASG int
[000028] D----+-N---- +--* LCL_VAR int V04 loc1
[000024] --CXG+------ \--* CALL int Test2.DoTestImpl3
[000169] -----+------ arg3 in r9 +--* CAST int <- ubyte <- int
[000023] -----+------ | \--* LCL_VAR int V02 arg2
[000020] -----+------ arg0 in rcx +--* LCL_FLD byte V08 loc5 [+0]
[000021] -----+------ arg1 in rdx +--* LCL_VAR int V00 arg0
[000022] -----+------ arg2 in r8 \--* LCL_VAR int V01 arg1
New refCnts for V04: refCnt = 1, refCntWtd = 1
New refCnts for V02: refCnt = 3, refCntWtd = 3
New refCnts for V08: refCnt = 2, refCntWtd = 2
New refCnts for V00: refCnt = 3, refCntWtd = 3
New refCnts for V01: refCnt = 3, refCntWtd = 3
STMT00007 (IL ???...0x031)
[000033] -AC--+------ * ASG ref
[000032] D----+-N---- +--* LCL_VAR ref V11 tmp2
[000031] --C--+------ \--* CALL help ref HELPER.CORINFO_HELP_NEWSFAST
[000030] -----+------ arg0 in rcx \--* CNS_INT(h) long 0xd1ffab1e method
New refCnts for V11: refCnt = 1, refCntWtd = 2
STMT00010 (IL ???... ???)
[000044] -ACXG+------ * ASG int
[000043] D----+-N---- +--* LCL_VAR int V05 loc2
[000040] --CXG+------ \--* CALL int Test2.DoTestImpl4
[000175] -----+------ arg4 out+20 +--* CAST int <- ubyte <- int
[000039] -----+------ | \--* LCL_VAR int V02 arg2
[000036] -----+------ arg1 in rdx +--* LCL_VAR ref V11 tmp2
[000037] -----+------ arg2 in r8 +--* LCL_VAR int V00 arg0
[000038] -----+------ arg3 in r9 +--* LCL_VAR int V01 arg1
[000041] -----+------ arg0 in rcx \--* CNS_INT(h) long 0xd1ffab1e method
New refCnts for V05: refCnt = 1, refCntWtd = 1
New refCnts for V02: refCnt = 4, refCntWtd = 4
New refCnts for V11: refCnt = 2, refCntWtd = 4
New refCnts for V00: refCnt = 4, refCntWtd = 4
New refCnts for V01: refCnt = 4, refCntWtd = 4
STMT00012 (IL ???... ???)
[000051] -ACXG+------ * ASG int
[000050] D----+-N---- +--* LCL_VAR int V06 loc3
[000048] --CXG+------ \--* CALL int Test2.DoTestImpl5
[000180] -----+------ arg2 in r8 +--* CAST int <- ubyte <- int
[000047] -----+------ | \--* LCL_VAR int V02 arg2
[000045] -----+------ arg0 in rcx +--* LCL_VAR int V00 arg0
[000046] -----+------ arg1 in rdx \--* LCL_VAR int V01 arg1
New refCnts for V06: refCnt = 1, refCntWtd = 1
New refCnts for V02: refCnt = 5, refCntWtd = 5
New refCnts for V00: refCnt = 5, refCntWtd = 5
New refCnts for V01: refCnt = 5, refCntWtd = 5
STMT00022 (IL ???... ???)
[000101] -A---+------ * ASG byte
[000185] n------N---- +--* IND byte
[000184] ------------ | \--* ADDR byref
[000098] D----+-N---- | \--* LCL_VAR struct V12 tmp3
[000100] -----+------ \--* CNS_INT int 0
New refCnts for V12: refCnt = 1, refCntWtd = 1
STMT00035 (IL ???... ???)
[000138] -A---+------ * ASG int
[000137] D----+-N---- +--* LCL_VAR int V14 tmp5
[000136] -----+------ \--* CNS_INT int 0
New refCnts for V14: refCnt = 1, refCntWtd = 1
STMT00027 (IL ???... ???)
[000114] -A---+------ * ASG int
[000113] D----+-N---- +--* LCL_VAR int V13 tmp4
[000140] -----+------ \--* ADD int
[000052] -----+------ +--* LCL_VAR int V00 arg0
[000053] -----+------ \--* LCL_VAR int V01 arg1
New refCnts for V13: refCnt = 1, refCntWtd = 2
New refCnts for V00: refCnt = 6, refCntWtd = 6
New refCnts for V01: refCnt = 6, refCntWtd = 6
STMT00029 (IL ???... ???)
[000120] -A---+------ * ASG int
[000119] D----+-N---- +--* LCL_VAR int V14 tmp5
[000145] -----+------ \--* MUL int
[000115] -----+------ +--* LCL_VAR int V13 tmp4
[000186] -----+------ \--* CAST int <- ubyte <- int
[000054] -----+------ \--* LCL_VAR int V02 arg2
New refCnts for V14: refCnt = 2, refCntWtd = 2
New refCnts for V13: refCnt = 2, refCntWtd = 4
New refCnts for V02: refCnt = 6, refCntWtd = 6
STMT00033 (IL ???... ???)
[000131] -A---+------ * ASG int
[000130] D----+-N---- +--* LCL_VAR int V15 tmp6
[000150] -----+------ \--* MUL int
[000121] -----+------ +--* LCL_VAR int V00 arg0
[000187] -----+------ \--* CAST int <- ubyte <- int
[000122] -----+------ \--* LCL_VAR int V02 arg2
New refCnts for V15: refCnt = 1, refCntWtd = 2
New refCnts for V00: refCnt = 7, refCntWtd = 7
New refCnts for V02: refCnt = 7, refCntWtd = 7
STMT00014 (IL ???... ???)
[000058] -A-X-+------ * ASG int
[000057] D----+-N---- +--* LCL_VAR int V07 loc4
[000156] ---X-+------ \--* DIV int
[000132] -----+------ +--* LCL_VAR int V15 tmp6
[000153] -----+------ \--* RSH int
[000127] -----+------ +--* LCL_VAR int V14 tmp5
[000152] -----+------ \--* CNS_INT int 2
New refCnts for V07: refCnt = 1, refCntWtd = 1
New refCnts for V15: refCnt = 2, refCntWtd = 4
New refCnts for V14: refCnt = 3, refCntWtd = 3
STMT00015 (IL ???...0x050)
[000069] -----+------ * RETURN int
[000068] -----+------ \--* ADD int
[000066] -----+------ +--* ADD int
[000064] -----+------ | +--* ADD int
[000062] -----+------ | | +--* ADD int
[000060] -----+------ | | | +--* ADD int
[000012] -----+------ | | | | +--* LCL_VAR int V10 tmp1
[000059] -----+------ | | | | \--* LCL_VAR int V03 loc0
[000061] -----+------ | | | \--* LCL_VAR int V04 loc1
[000063] -----+------ | | \--* LCL_VAR int V05 loc2
[000065] -----+------ | \--* LCL_VAR int V06 loc3
[000067] -----+------ \--* LCL_VAR int V07 loc4
New refCnts for V10: refCnt = 2, refCntWtd = 4
New refCnts for V03: refCnt = 2, refCntWtd = 2
New refCnts for V04: refCnt = 2, refCntWtd = 2
New refCnts for V05: refCnt = 2, refCntWtd = 2
New refCnts for V06: refCnt = 2, refCntWtd = 2
New refCnts for V07: refCnt = 2, refCntWtd = 2
*** lvaComputeRefCounts -- implicit counts ***
New refCnts for V00: refCnt = 8, refCntWtd = 8
New refCnts for V00: refCnt = 9, refCntWtd = 9
New refCnts for V01: refCnt = 7, refCntWtd = 7
New refCnts for V01: refCnt = 8, refCntWtd = 8
New refCnts for V02: refCnt = 8, refCntWtd = 8
New refCnts for V02: refCnt = 9, refCntWtd = 9
*************** In optAddCopies()
*************** In optOptimizeBools()
*************** In fgDebugCheckBBlist
*************** In fgFindOperOrder()
*************** In fgSetBlockOrder()
The biggest BB has 13 tree nodes
-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..051) (return) i label target gcsafe newobj
-----------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [000..051) (return), preds={} succs={}
***** BB01
STMT00002 (IL ???... ???)
N010 ( 19, 14) [000011] -ACXG---R--- * ASG int
N009 ( 1, 1) [000010] D------N---- +--* LCL_VAR int V10 tmp1
N008 ( 19, 14) [000003] --CXG------- \--* CALL int Test2.DoTestImpl1
N005 ( 3, 4) [000158] ------------ arg2 in r8 +--* CAST int <- ubyte <- int
N004 ( 2, 2) [000002] ------------ | \--* LCL_VAR int V02 arg2
N006 ( 1, 1) [000000] ------------ arg0 in rcx +--* LCL_VAR int V00 arg0
N007 ( 1, 1) [000001] ------------ arg1 in rdx \--* LCL_VAR int V01 arg1
***** BB01
STMT00003 (IL ???... ???)
N012 ( 26, 28) [000015] -ACXG---R--- * ASG int
N011 ( 3, 2) [000014] D------N---- +--* LCL_VAR int V03 loc0
N010 ( 22, 25) [000008] --CXG------- \--* CALL int Test2.DoTestImpl2
N006 ( 3, 4) [000162] ------------ arg3 in r9 +--* CAST int <- ubyte <- int
N005 ( 2, 2) [000007] ------------ | \--* LCL_VAR int V02 arg2
N007 ( 1, 1) [000005] ------------ arg1 in rdx +--* LCL_VAR int V00 arg0
N008 ( 1, 1) [000006] ------------ arg2 in r8 +--* LCL_VAR int V01 arg1
N009 ( 3, 10) [000009] ------------ arg0 in rcx \--* CNS_INT(h) long 0xd1ffab1e method
***** BB01
STMT00004 (IL ???...0x014)
N005 ( 9, 8) [000019] -A------R--- * ASG byte
N004 ( 7, 6) [000168] n------N---- +--* IND byte
N003 ( 3, 3) [000167] ------------ | \--* ADDR byref
N002 ( 3, 2) [000016] D------N---- | \--* LCL_VAR struct V08 loc5
N001 ( 1, 1) [000018] ------------ \--* CNS_INT int 0
***** BB01
STMT00006 (IL ???... ???)
N012 ( 27, 23) [000029] -ACXG---R--- * ASG int
N011 ( 3, 2) [000028] D------N---- +--* LCL_VAR int V04 loc1
N010 ( 23, 20) [000024] --CXG------- \--* CALL int Test2.DoTestImpl3
N006 ( 3, 4) [000169] ------------ arg3 in r9 +--* CAST int <- ubyte <- int
N005 ( 2, 2) [000023] ------------ | \--* LCL_VAR int V02 arg2
N007 ( 4, 5) [000020] ------------ arg0 in rcx +--* LCL_FLD byte V08 loc5 [+0]
N008 ( 1, 1) [000021] ------------ arg1 in rdx +--* LCL_VAR int V00 arg0
N009 ( 1, 1) [000022] ------------ arg2 in r8 \--* LCL_VAR int V01 arg1
***** BB01
STMT00007 (IL ???...0x031)
N005 ( 17, 16) [000033] -AC-----R--- * ASG ref
N004 ( 1, 1) [000032] D------N---- +--* LCL_VAR ref V11 tmp2
N003 ( 17, 16) [000031] --C--------- \--* CALL help ref HELPER.CORINFO_HELP_NEWSFAST
N002 ( 3, 10) [000030] ------------ arg0 in rcx \--* CNS_INT(h) long 0xd1ffab1e method
***** BB01
STMT00010 (IL ???... ???)
N013 ( 30, 29) [000044] -ACXG---R--- * ASG int
N012 ( 3, 2) [000043] D------N---- +--* LCL_VAR int V05 loc2
N011 ( 26, 26) [000040] --CXG------- \--* CALL int Test2.DoTestImpl4
N006 ( 3, 4) [000175] ------------ arg4 out+20 +--* CAST int <- ubyte <- int
N005 ( 2, 2) [000039] ------------ | \--* LCL_VAR int V02 arg2
N007 ( 1, 1) [000036] ------------ arg1 in rdx +--* LCL_VAR ref V11 tmp2
N008 ( 1, 1) [000037] ------------ arg2 in r8 +--* LCL_VAR int V00 arg0
N009 ( 1, 1) [000038] ------------ arg3 in r9 +--* LCL_VAR int V01 arg1
N010 ( 3, 10) [000041] ------------ arg0 in rcx \--* CNS_INT(h) long 0xd1ffab1e method
***** BB01
STMT00012 (IL ???... ???)
N010 ( 23, 17) [000051] -ACXG---R--- * ASG int
N009 ( 3, 2) [000050] D------N---- +--* LCL_VAR int V06 loc3
N008 ( 19, 14) [000048] --CXG------- \--* CALL int Test2.DoTestImpl5
N005 ( 3, 4) [000180] ------------ arg2 in r8 +--* CAST int <- ubyte <- int
N004 ( 2, 2) [000047] ------------ | \--* LCL_VAR int V02 arg2
N006 ( 1, 1) [000045] ------------ arg0 in rcx +--* LCL_VAR int V00 arg0
N007 ( 1, 1) [000046] ------------ arg1 in rdx \--* LCL_VAR int V01 arg1
***** BB01
STMT00022 (IL ???... ???)
N005 ( 9, 8) [000101] -A------R--- * ASG byte
N004 ( 7, 6) [000185] n------N---- +--* IND byte
N003 ( 3, 3) [000184] ------------ | \--* ADDR byref
N002 ( 3, 2) [000098] D------N---- | \--* LCL_VAR struct V12 tmp3
N001 ( 1, 1) [000100] ------------ \--* CNS_INT int 0
***** BB01
STMT00035 (IL ???... ???)
N003 ( 1, 3) [000138] -A------R--- * ASG int
N002 ( 1, 1) [000137] D------N---- +--* LCL_VAR int V14 tmp5
N001 ( 1, 1) [000136] ------------ \--* CNS_INT int 0
***** BB01
STMT00027 (IL ???... ???)
N005 ( 3, 3) [000114] -A------R--- * ASG int
N004 ( 1, 1) [000113] D------N---- +--* LCL_VAR int V13 tmp4
N003 ( 3, 3) [000140] ------------ \--* ADD int
N001 ( 1, 1) [000052] ------------ +--* LCL_VAR int V00 arg0
N002 ( 1, 1) [000053] ------------ \--* LCL_VAR int V01 arg1
***** BB01
STMT00029 (IL ???... ???)
N006 ( 8, 8) [000120] -A------R--- * ASG int
N005 ( 1, 1) [000119] D------N---- +--* LCL_VAR int V14 tmp5
N004 ( 8, 8) [000145] ------------ \--* MUL int
N001 ( 1, 1) [000115] ------------ +--* LCL_VAR int V13 tmp4
N003 ( 3, 4) [000186] ------------ \--* CAST int <- ubyte <- int
N002 ( 2, 2) [000054] ------------ \--* LCL_VAR int V02 arg2
***** BB01
STMT00033 (IL ???... ???)
N006 ( 8, 8) [000131] -A------R--- * ASG int
N005 ( 1, 1) [000130] D------N---- +--* LCL_VAR int V15 tmp6
N004 ( 8, 8) [000150] ------------ \--* MUL int
N001 ( 1, 1) [000121] ------------ +--* LCL_VAR int V00 arg0
N003 ( 3, 4) [000187] ------------ \--* CAST int <- ubyte <- int
N002 ( 2, 2) [000122] ------------ \--* LCL_VAR int V02 arg2
***** BB01
STMT00014 (IL ???... ???)
N007 ( 28, 10) [000058] -A-X----R--- * ASG int
N006 ( 3, 2) [000057] D------N---- +--* LCL_VAR int V07 loc4
N005 ( 24, 7) [000156] ---X-------- \--* DIV int
N001 ( 1, 1) [000132] ------------ +--* LCL_VAR int V15 tmp6
N004 ( 3, 3) [000153] ------------ \--* RSH int
N002 ( 1, 1) [000127] ------------ +--* LCL_VAR int V14 tmp5
N003 ( 1, 1) [000152] ------------ \--* CNS_INT int 2
***** BB01
STMT00015 (IL ???...0x050)
N012 ( 22, 17) [000069] ------------ * RETURN int
N011 ( 21, 16) [000068] ------------ \--* ADD int
N009 ( 17, 13) [000066] ------------ +--* ADD int
N007 ( 13, 10) [000064] ------------ | +--* ADD int
N005 ( 9, 7) [000062] ------------ | | +--* ADD int
N003 ( 5, 4) [000060] ------------ | | | +--* ADD int
N001 ( 1, 1) [000012] ------------ | | | | +--* LCL_VAR int V10 tmp1
N002 ( 3, 2) [000059] ------------ | | | | \--* LCL_VAR int V03 loc0
N004 ( 3, 2) [000061] ------------ | | | \--* LCL_VAR int V04 loc1
N006 ( 3, 2) [000063] ------------ | | \--* LCL_VAR int V05 loc2
N008 ( 3, 2) [000065] ------------ | \--* LCL_VAR int V06 loc3
N010 ( 3, 2) [000067] ------------ \--* LCL_VAR int V07 loc4
-------------------------------------------------------------------------------------------------------------------
*************** In SsaBuilder::Build()
[SsaBuilder] Max block count is 2.
-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..051) (return) i label target gcsafe newobj
-----------------------------------------------------------------------------------------------------------------------------------------
*************** Exception Handling table is empty
[SsaBuilder] Topologically sorted the graph.
[SsaBuilder::ComputeImmediateDom]
*************** In SsaBuilder::ComputeDominators(BasicBlock** postOrder, int count, ...)
*************** In fgLocalVarLiveness()
In fgLocalVarLivenessInit
Local V08 should not be enregistered because: it is a struct
Local V12 should not be enregistered because: it is a struct
Tracked variable (15 out of 19) table:
V00 arg0 [ int]: refCnt = 9, refCntWtd = 9
V02 arg2 [ ubyte]: refCnt = 9, refCntWtd = 9
V01 arg1 [ int]: refCnt = 8, refCntWtd = 8
V11 tmp2 [ ref]: refCnt = 2, refCntWtd = 4
V10 tmp1 [ int]: refCnt = 2, refCntWtd = 4
V13 tmp4 [ int]: refCnt = 2, refCntWtd = 4
V15 tmp6 [ int]: refCnt = 2, refCntWtd = 4
V14 tmp5 [ int]: refCnt = 3, refCntWtd = 3
V03 loc0 [ int]: refCnt = 2, refCntWtd = 2
V04 loc1 [ int]: refCnt = 2, refCntWtd = 2
V05 loc2 [ int]: refCnt = 2, refCntWtd = 2
V06 loc3 [ int]: refCnt = 2, refCntWtd = 2
V07 loc4 [ int]: refCnt = 2, refCntWtd = 2
V08 loc5 [struct]: refCnt = 2, refCntWtd = 2
V12 tmp3 [struct]: refCnt = 1, refCntWtd = 1
*************** In fgPerBlockLocalVarLiveness()
BB01 USE(3)={V00 V02 V01 } + ByrefExposed + GcHeap
DEF(12)={ V11 V10 V13 V15 V14 V03 V04 V05 V06 V07 V08 V12} + ByrefExposed* + GcHeap*
** Memory liveness computed, GcHeap states and ByrefExposed states match
*************** In fgInterBlockLocalVarLiveness()
BB liveness after fgLiveVarAnalysis():
BB01 IN (3)={V00 V02 V01} + ByrefExposed + GcHeap
OUT(0)={ }
top level assign
removing stmt with no side effects
Removing statement STMT00035 (IL ???... ???)
N003 ( 1, 3) [000138] -A------R--- * ASG int
N002 ( 1, 1) [000137] D------N---- +--* LCL_VAR int V14 tmp5
N001 ( 1, 1) [000136] ------------ \--* CNS_INT int 0
in BB01 as useless:
top level assign
removing stmt with no side effects
Removing statement STMT00022 (IL ???... ???)
N005 ( 9, 8) [000101] -A------R--- * ASG byte
N004 ( 7, 6) [000185] n------N---- +--* IND byte
N003 ( 3, 3) [000184] ------------ | \--* ADDR byref
N002 ( 3, 2) [000098] D------N---- | \--* LCL_VAR struct V12 tmp3
N001 ( 1, 1) [000100] ------------ \--* CNS_INT int 0
in BB01 as useless:
*************** In SsaBuilder::InsertPhiFunctions()
Inserting phi functions:
*************** In SsaBuilder::RenameVariables()
After fgSsaBuild:
-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..051) (return) i label target gcsafe newobj
-----------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [000..051) (return), preds={} succs={}
***** BB01
STMT00002 (IL ???... ???)
N010 ( 19, 14) [000011] -ACXG---R--- * ASG int
N009 ( 1, 1) [000010] D------N---- +--* LCL_VAR int V10 tmp1 d:2
N008 ( 19, 14) [000003] --CXG------- \--* CALL int Test2.DoTestImpl1
N005 ( 3, 4) [000158] ------------ arg2 in r8 +--* CAST int <- ubyte <- int
N004 ( 2, 2) [000002] ------------ | \--* LCL_VAR int V02 arg2 u:1
N006 ( 1, 1) [000000] ------------ arg0 in rcx +--* LCL_VAR int V00 arg0 u:1
N007 ( 1, 1) [000001] ------------ arg1 in rdx \--* LCL_VAR int V01 arg1 u:1
***** BB01
STMT00003 (IL ???... ???)
N012 ( 26, 28) [000015] -ACXG---R--- * ASG int
N011 ( 3, 2) [000014] D------N---- +--* LCL_VAR int V03 loc0 d:2
N010 ( 22, 25) [000008] --CXG------- \--* CALL int Test2.DoTestImpl2
N006 ( 3, 4) [000162] ------------ arg3 in r9 +--* CAST int <- ubyte <- int
N005 ( 2, 2) [000007] ------------ | \--* LCL_VAR int V02 arg2 u:1
N007 ( 1, 1) [000005] ------------ arg1 in rdx +--* LCL_VAR int V00 arg0 u:1
N008 ( 1, 1) [000006] ------------ arg2 in r8 +--* LCL_VAR int V01 arg1 u:1
N009 ( 3, 10) [000009] ------------ arg0 in rcx \--* CNS_INT(h) long 0xd1ffab1e method
***** BB01
STMT00004 (IL ???...0x014)
N005 ( 9, 8) [000019] -A------R--- * ASG byte
N004 ( 7, 6) [000168] n------N---- +--* IND byte
N003 ( 3, 3) [000167] ------------ | \--* ADDR byref
N002 ( 3, 2) [000016] D------N---- | \--* LCL_VAR struct V08 loc5 d:2
N001 ( 1, 1) [000018] ------------ \--* CNS_INT int 0
***** BB01
STMT00006 (IL ???... ???)
N012 ( 27, 23) [000029] -ACXG---R--- * ASG int
N011 ( 3, 2) [000028] D------N---- +--* LCL_VAR int V04 loc1 d:2
N010 ( 23, 20) [000024] --CXG------- \--* CALL int Test2.DoTestImpl3
N006 ( 3, 4) [000169] ------------ arg3 in r9 +--* CAST int <- ubyte <- int
N005 ( 2, 2) [000023] ------------ | \--* LCL_VAR int V02 arg2 u:1
N007 ( 4, 5) [000020] ------------ arg0 in rcx +--* LCL_FLD byte V08 loc5 u:2[+0] (last use)
N008 ( 1, 1) [000021] ------------ arg1 in rdx +--* LCL_VAR int V00 arg0 u:1
N009 ( 1, 1) [000022] ------------ arg2 in r8 \--* LCL_VAR int V01 arg1 u:1
***** BB01
STMT00007 (IL ???...0x031)
N005 ( 17, 16) [000033] -AC-----R--- * ASG ref
N004 ( 1, 1) [000032] D------N---- +--* LCL_VAR ref V11 tmp2 d:2
N003 ( 17, 16) [000031] --C--------- \--* CALL help ref HELPER.CORINFO_HELP_NEWSFAST
N002 ( 3, 10) [000030] ------------ arg0 in rcx \--* CNS_INT(h) long 0xd1ffab1e method
***** BB01
STMT00010 (IL ???... ???)
N013 ( 30, 29) [000044] -ACXG---R--- * ASG int
N012 ( 3, 2) [000043] D------N---- +--* LCL_VAR int V05 loc2 d:2
N011 ( 26, 26) [000040] --CXG------- \--* CALL int Test2.DoTestImpl4
N006 ( 3, 4) [000175] ------------ arg4 out+20 +--* CAST int <- ubyte <- int
N005 ( 2, 2) [000039] ------------ | \--* LCL_VAR int V02 arg2 u:1
N007 ( 1, 1) [000036] ------------ arg1 in rdx +--* LCL_VAR ref V11 tmp2 u:2 (last use)
N008 ( 1, 1) [000037] ------------ arg2 in r8 +--* LCL_VAR int V00 arg0 u:1
N009 ( 1, 1) [000038] ------------ arg3 in r9 +--* LCL_VAR int V01 arg1 u:1
N010 ( 3, 10) [000041] ------------ arg0 in rcx \--* CNS_INT(h) long 0xd1ffab1e method
***** BB01
STMT00012 (IL ???... ???)
N010 ( 23, 17) [000051] -ACXG---R--- * ASG int
N009 ( 3, 2) [000050] D------N---- +--* LCL_VAR int V06 loc3 d:2
N008 ( 19, 14) [000048] --CXG------- \--* CALL int Test2.DoTestImpl5
N005 ( 3, 4) [000180] ------------ arg2 in r8 +--* CAST int <- ubyte <- int
N004 ( 2, 2) [000047] ------------ | \--* LCL_VAR int V02 arg2 u:1
N006 ( 1, 1) [000045] ------------ arg0 in rcx +--* LCL_VAR int V00 arg0 u:1
N007 ( 1, 1) [000046] ------------ arg1 in rdx \--* LCL_VAR int V01 arg1 u:1
***** BB01
STMT00027 (IL ???... ???)
N005 ( 3, 3) [000114] -A------R--- * ASG int
N004 ( 1, 1) [000113] D------N---- +--* LCL_VAR int V13 tmp4 d:2
N003 ( 3, 3) [000140] ------------ \--* ADD int
N001 ( 1, 1) [000052] ------------ +--* LCL_VAR int V00 arg0 u:1
N002 ( 1, 1) [000053] ------------ \--* LCL_VAR int V01 arg1 u:1 (last use)
***** BB01
STMT00029 (IL ???... ???)
N006 ( 8, 8) [000120] -A------R--- * ASG int
N005 ( 1, 1) [000119] D------N---- +--* LCL_VAR int V14 tmp5 d:2
N004 ( 8, 8) [000145] ------------ \--* MUL int
N001 ( 1, 1) [000115] ------------ +--* LCL_VAR int V13 tmp4 u:2 (last use)
N003 ( 3, 4) [000186] ------------ \--* CAST int <- ubyte <- int
N002 ( 2, 2) [000054] ------------ \--* LCL_VAR int V02 arg2 u:1
***** BB01
STMT00033 (IL ???... ???)
N006 ( 8, 8) [000131] -A------R--- * ASG int
N005 ( 1, 1) [000130] D------N---- +--* LCL_VAR int V15 tmp6 d:2
N004 ( 8, 8) [000150] ------------ \--* MUL int
N001 ( 1, 1) [000121] ------------ +--* LCL_VAR int V00 arg0 u:1 (last use)
N003 ( 3, 4) [000187] ------------ \--* CAST int <- ubyte <- int
N002 ( 2, 2) [000122] ------------ \--* LCL_VAR int V02 arg2 u:1 (last use)
***** BB01
STMT00014 (IL ???... ???)
N007 ( 28, 10) [000058] -A-X----R--- * ASG int
N006 ( 3, 2) [000057] D------N---- +--* LCL_VAR int V07 loc4 d:2
N005 ( 24, 7) [000156] ---X-------- \--* DIV int
N001 ( 1, 1) [000132] ------------ +--* LCL_VAR int V15 tmp6 u:2 (last use)
N004 ( 3, 3) [000153] ------------ \--* RSH int
N002 ( 1, 1) [000127] ------------ +--* LCL_VAR int V14 tmp5 u:2 (last use)
N003 ( 1, 1) [000152] ------------ \--* CNS_INT int 2
***** BB01
STMT00015 (IL ???...0x050)
N012 ( 22, 17) [000069] ------------ * RETURN int
N011 ( 21, 16) [000068] ------------ \--* ADD int
N009 ( 17, 13) [000066] ------------ +--* ADD int
N007 ( 13, 10) [000064] ------------ | +--* ADD int
N005 ( 9, 7) [000062] ------------ | | +--* ADD int
N003 ( 5, 4) [000060] ------------ | | | +--* ADD int
N001 ( 1, 1) [000012] ------------ | | | | +--* LCL_VAR int V10 tmp1 u:2 (last use)
N002 ( 3, 2) [000059] ------------ | | | | \--* LCL_VAR int V03 loc0 u:2 (last use)
N004 ( 3, 2) [000061] ------------ | | | \--* LCL_VAR int V04 loc1 u:2 (last use)
N006 ( 3, 2) [000063] ------------ | | \--* LCL_VAR int V05 loc2 u:2 (last use)
N008 ( 3, 2) [000065] ------------ | \--* LCL_VAR int V06 loc3 u:2 (last use)
N010 ( 3, 2) [000067] ------------ \--* LCL_VAR int V07 loc4 u:2 (last use)
-------------------------------------------------------------------------------------------------------------------
*************** In optEarlyProp()
*************** In fgValueNumber()
Memory Initial Value in BB01 is: $100
The SSA definition for ByrefExposed (#1) at start of BB01 is $100 {InitVal($43)}
The SSA definition for GcHeap (#1) at start of BB01 is $100 {InitVal($43)}
***** BB01, STMT00002(before)
N010 ( 19, 14) [000011] -ACXG---R--- * ASG int
N009 ( 1, 1) [000010] D------N---- +--* LCL_VAR int V10 tmp1 d:2
N008 ( 19, 14) [000003] --CXG------- \--* CALL int Test2.DoTestImpl1
N005 ( 3, 4) [000158] ------------ arg2 in r8 +--* CAST int <- ubyte <- int
N004 ( 2, 2) [000002] ------------ | \--* LCL_VAR int V02 arg2 u:1
N006 ( 1, 1) [000000] ------------ arg0 in rcx +--* LCL_VAR int V00 arg0 u:1
N007 ( 1, 1) [000001] ------------ arg1 in rdx \--* LCL_VAR int V01 arg1 u:1
N001 [000160] ARGPLACE => $140 {140}
N002 [000161] ARGPLACE => $141 {141}
N003 [000159] ARGPLACE => $142 {142}
N004 [000002] LCL_VAR V02 arg2 u:1 => $c0 {InitVal($42)}
VNForCastOper(ubyte) is $44
N005 [000158] CAST => $180 {Cast($c0, $44)}
N006 [000000] LCL_VAR V00 arg0 u:1 => $80 {InitVal($40)}
N007 [000001] LCL_VAR V01 arg1 u:1 => $81 {InitVal($41)}
VN of ARGPLACE tree [000160] updated to $80 {InitVal($40)}
VN of ARGPLACE tree [000161] updated to $81 {InitVal($41)}
VN of ARGPLACE tree [000159] updated to $180 {Cast($c0, $44)}
fgCurMemoryVN[GcHeap] assigned for CALL at [000003] to VN: $1c0.
N008 [000003] CALL => $143 {143}
N009 [000010] LCL_VAR V10 tmp1 d:2 => $143 {143}
N010 [000011] ASG => $143 {143}
***** BB01, STMT00002(after)
N010 ( 19, 14) [000011] -ACXG---R--- * ASG int $143
N009 ( 1, 1) [000010] D------N---- +--* LCL_VAR int V10 tmp1 d:2 $143
N008 ( 19, 14) [000003] --CXG------- \--* CALL int Test2.DoTestImpl1 $143
N005 ( 3, 4) [000158] ------------ arg2 in r8 +--* CAST int <- ubyte <- int $180
N004 ( 2, 2) [000002] ------------ | \--* LCL_VAR int V02 arg2 u:1 $c0
N006 ( 1, 1) [000000] ------------ arg0 in rcx +--* LCL_VAR int V00 arg0 u:1 $80
N007 ( 1, 1) [000001] ------------ arg1 in rdx \--* LCL_VAR int V01 arg1 u:1 $81
---------
***** BB01, STMT00003(before)
N012 ( 26, 28) [000015] -ACXG---R--- * ASG int
N011 ( 3, 2) [000014] D------N---- +--* LCL_VAR int V03 loc0 d:2
N010 ( 22, 25) [000008] --CXG------- \--* CALL int Test2.DoTestImpl2
N006 ( 3, 4) [000162] ------------ arg3 in r9 +--* CAST int <- ubyte <- int
N005 ( 2, 2) [000007] ------------ | \--* LCL_VAR int V02 arg2 u:1
N007 ( 1, 1) [000005] ------------ arg1 in rdx +--* LCL_VAR int V00 arg0 u:1
N008 ( 1, 1) [000006] ------------ arg2 in r8 +--* LCL_VAR int V01 arg1 u:1
N009 ( 3, 10) [000009] ------------ arg0 in rcx \--* CNS_INT(h) long 0xd1ffab1e method
N001 [000166] ARGPLACE => $200 {200}
N002 [000164] ARGPLACE => $145 {145}
N003 [000165] ARGPLACE => $146 {146}
N004 [000163] ARGPLACE => $147 {147}
N005 [000007] LCL_VAR V02 arg2 u:1 => $c0 {InitVal($42)}
VNForCastOper(ubyte) is $44
N006 [000162] CAST => $180 {Cast($c0, $44)}
N007 [000005] LCL_VAR V00 arg0 u:1 => $80 {InitVal($40)}
N008 [000006] LCL_VAR V01 arg1 u:1 => $81 {InitVal($41)}
N009 [000009] CNS_INT(h) 0xd1ffab1e method => $240 {Hnd const: 0x00000000D1FFAB1E}
VN of ARGPLACE tree [000166] updated to $240 {Hnd const: 0x00000000D1FFAB1E}
VN of ARGPLACE tree [000164] updated to $80 {InitVal($40)}
VN of ARGPLACE tree [000165] updated to $81 {InitVal($41)}
VN of ARGPLACE tree [000163] updated to $180 {Cast($c0, $44)}
fgCurMemoryVN[GcHeap] assigned for CALL at [000008] to VN: $1c1.
N010 [000008] CALL => $148 {148}
N011 [000014] LCL_VAR V03 loc0 d:2 => $148 {148}
N012 [000015] ASG => $148 {148}
***** BB01, STMT00003(after)
N012 ( 26, 28) [000015] -ACXG---R--- * ASG int $148
N011 ( 3, 2) [000014] D------N---- +--* LCL_VAR int V03 loc0 d:2 $148
N010 ( 22, 25) [000008] --CXG------- \--* CALL int Test2.DoTestImpl2 $148
N006 ( 3, 4) [000162] ------------ arg3 in r9 +--* CAST int <- ubyte <- int $180
N005 ( 2, 2) [000007] ------------ | \--* LCL_VAR int V02 arg2 u:1 $c0
N007 ( 1, 1) [000005] ------------ arg1 in rdx +--* LCL_VAR int V00 arg0 u:1 $80
N008 ( 1, 1) [000006] ------------ arg2 in r8 +--* LCL_VAR int V01 arg1 u:1 $81
N009 ( 3, 10) [000009] ------------ arg0 in rcx \--* CNS_INT(h) long 0xd1ffab1e method $240
---------
***** BB01, STMT00004(before)
N005 ( 9, 8) [000019] -A------R--- * ASG byte
N004 ( 7, 6) [000168] n------N---- +--* IND byte
N003 ( 3, 3) [000167] ------------ | \--* ADDR byref
N002 ( 3, 2) [000016] D------N---- | \--* LCL_VAR struct V08 loc5 d:2
N001 ( 1, 1) [000018] ------------ \--* CNS_INT int 0
N001 [000018] CNS_INT 0 => $40 {IntCns 0}
N003 [000167] ADDR => $2c0 {PtrToLoc($44, $0)}
VNForCastOper(byte) is $45
Tree [000019] assigned VN to local var V08/2: VN $40 {IntCns 0}
N005 [000019] ASG => $VN.Void
***** BB01, STMT00004(after)
N005 ( 9, 8) [000019] -A------R--- * ASG byte $VN.Void
N004 ( 7, 6) [000168] n------N---- +--* IND byte $40
N003 ( 3, 3) [000167] ------------ | \--* ADDR byref $2c0
N002 ( 3, 2) [000016] D------N---- | \--* LCL_VAR struct V08 loc5 d:2
N001 ( 1, 1) [000018] ------------ \--* CNS_INT int 0 $40
---------
***** BB01, STMT00006(before)
N012 ( 27, 23) [000029] -ACXG---R--- * ASG int
N011 ( 3, 2) [000028] D------N---- +--* LCL_VAR int V04 loc1 d:2
N010 ( 23, 20) [000024] --CXG------- \--* CALL int Test2.DoTestImpl3
N006 ( 3, 4) [000169] ------------ arg3 in r9 +--* CAST int <- ubyte <- int
N005 ( 2, 2) [000023] ------------ | \--* LCL_VAR int V02 arg2 u:1
N007 ( 4, 5) [000020] ------------ arg0 in rcx +--* LCL_FLD byte V08 loc5 u:2[+0] (last use)
N008 ( 1, 1) [000021] ------------ arg1 in rdx +--* LCL_VAR int V00 arg0 u:1
N009 ( 1, 1) [000022] ------------ arg2 in r8 \--* LCL_VAR int V01 arg1 u:1
N001 [000171] ARGPLACE => $300 {300}
N002 [000172] ARGPLACE => $14a {14a}
N003 [000173] ARGPLACE => $14b {14b}
N004 [000170] ARGPLACE => $14c {14c}
N005 [000023] LCL_VAR V02 arg2 u:1 => $c0 {InitVal($42)}
VNForCastOper(ubyte) is $44
N006 [000169] CAST => $180 {Cast($c0, $44)}
N007 [000020] LCL_FLD V08 loc5 u:2[+0] (last use) => $301 {301}
N008 [000021] LCL_VAR V00 arg0 u:1 => $80 {InitVal($40)}
N009 [000022] LCL_VAR V01 arg1 u:1 => $81 {InitVal($41)}
VN of ARGPLACE tree [000171] updated to $301 {301}
VN of ARGPLACE tree [000172] updated to $80 {InitVal($40)}
VN of ARGPLACE tree [000173] updated to $81 {InitVal($41)}
VN of ARGPLACE tree [000170] updated to $180 {Cast($c0, $44)}
fgCurMemoryVN[GcHeap] assigned for CALL at [000024] to VN: $1c2.
N010 [000024] CALL => $14d {14d}
N011 [000028] LCL_VAR V04 loc1 d:2 => $14d {14d}
N012 [000029] ASG => $14d {14d}
***** BB01, STMT00006(after)
N012 ( 27, 23) [000029] -ACXG---R--- * ASG int $14d
N011 ( 3, 2) [000028] D------N---- +--* LCL_VAR int V04 loc1 d:2 $14d
N010 ( 23, 20) [000024] --CXG------- \--* CALL int Test2.DoTestImpl3 $14d
N006 ( 3, 4) [000169] ------------ arg3 in r9 +--* CAST int <- ubyte <- int $180
N005 ( 2, 2) [000023] ------------ | \--* LCL_VAR int V02 arg2 u:1 $c0
N007 ( 4, 5) [000020] ------------ arg0 in rcx +--* LCL_FLD byte V08 loc5 u:2[+0] (last use) $301
N008 ( 1, 1) [000021] ------------ arg1 in rdx +--* LCL_VAR int V00 arg0 u:1 $80
N009 ( 1, 1) [000022] ------------ arg2 in r8 \--* LCL_VAR int V01 arg1 u:1 $81
---------
***** BB01, STMT00007(before)
N005 ( 17, 16) [000033] -AC-----R--- * ASG ref
N004 ( 1, 1) [000032] D------N---- +--* LCL_VAR ref V11 tmp2 d:2
N003 ( 17, 16) [000031] --C--------- \--* CALL help ref HELPER.CORINFO_HELP_NEWSFAST
N002 ( 3, 10) [000030] ------------ arg0 in rcx \--* CNS_INT(h) long 0xd1ffab1e method
N001 [000174] ARGPLACE => $201 {201}
N002 [000030] CNS_INT(h) 0xd1ffab1e method => $241 {Hnd const: 0x00000000D1FFAB1E}
VN of ARGPLACE tree [000174] updated to $241 {Hnd const: 0x00000000D1FFAB1E}
N003 [000031] CALL help => $340 {JitNew($241, $1c3)}
N004 [000032] LCL_VAR V11 tmp2 d:2 => $340 {JitNew($241, $1c3)}
N005 [000033] ASG => $340 {JitNew($241, $1c3)}
***** BB01, STMT00007(after)
N005 ( 17, 16) [000033] -AC-----R--- * ASG ref $340
N004 ( 1, 1) [000032] D------N---- +--* LCL_VAR ref V11 tmp2 d:2 $340
N003 ( 17, 16) [000031] --C--------- \--* CALL help ref HELPER.CORINFO_HELP_NEWSFAST $340
N002 ( 3, 10) [000030] ------------ arg0 in rcx \--* CNS_INT(h) long 0xd1ffab1e method $241
---------
***** BB01, STMT00010(before)
N013 ( 30, 29) [000044] -ACXG---R--- * ASG int
N012 ( 3, 2) [000043] D------N---- +--* LCL_VAR int V05 loc2 d:2
N011 ( 26, 26) [000040] --CXG------- \--* CALL int Test2.DoTestImpl4
N006 ( 3, 4) [000175] ------------ arg4 out+20 +--* CAST int <- ubyte <- int
N005 ( 2, 2) [000039] ------------ | \--* LCL_VAR int V02 arg2 u:1
N007 ( 1, 1) [000036] ------------ arg1 in rdx +--* LCL_VAR ref V11 tmp2 u:2 (last use)
N008 ( 1, 1) [000037] ------------ arg2 in r8 +--* LCL_VAR int V00 arg0 u:1
N009 ( 1, 1) [000038] ------------ arg3 in r9 +--* LCL_VAR int V01 arg1 u:1
N010 ( 3, 10) [000041] ------------ arg0 in rcx \--* CNS_INT(h) long 0xd1ffab1e method
N001 [000179] ARGPLACE => $202 {202}
N002 [000176] ARGPLACE => $1c5 {1c5}
N003 [000177] ARGPLACE => $14f {14f}
N004 [000178] ARGPLACE => $150 {150}
N005 [000039] LCL_VAR V02 arg2 u:1 => $c0 {InitVal($42)}
VNForCastOper(ubyte) is $44
N006 [000175] CAST => $180 {Cast($c0, $44)}
N007 [000036] LCL_VAR V11 tmp2 u:2 (last use) => $340 {JitNew($241, $1c3)}
N008 [000037] LCL_VAR V00 arg0 u:1 => $80 {InitVal($40)}
N009 [000038] LCL_VAR V01 arg1 u:1 => $81 {InitVal($41)}
N010 [000041] CNS_INT(h) 0xd1ffab1e method => $242 {Hnd const: 0x00000000D1FFAB1E}
VN of ARGPLACE tree [000179] updated to $242 {Hnd const: 0x00000000D1FFAB1E}
VN of ARGPLACE tree [000176] updated to $340 {JitNew($241, $1c3)}
VN of ARGPLACE tree [000177] updated to $80 {InitVal($40)}
VN of ARGPLACE tree [000178] updated to $81 {InitVal($41)}
fgCurMemoryVN[GcHeap] assigned for CALL at [000040] to VN: $1c6.
N011 [000040] CALL => $151 {151}
N012 [000043] LCL_VAR V05 loc2 d:2 => $151 {151}
N013 [000044] ASG => $151 {151}
***** BB01, STMT00010(after)
N013 ( 30, 29) [000044] -ACXG---R--- * ASG int $151
N012 ( 3, 2) [000043] D------N---- +--* LCL_VAR int V05 loc2 d:2 $151
N011 ( 26, 26) [000040] --CXG------- \--* CALL int Test2.DoTestImpl4 $151
N006 ( 3, 4) [000175] ------------ arg4 out+20 +--* CAST int <- ubyte <- int $180
N005 ( 2, 2) [000039] ------------ | \--* LCL_VAR int V02 arg2 u:1 $c0
N007 ( 1, 1) [000036] ------------ arg1 in rdx +--* LCL_VAR ref V11 tmp2 u:2 (last use) $340
N008 ( 1, 1) [000037] ------------ arg2 in r8 +--* LCL_VAR int V00 arg0 u:1 $80
N009 ( 1, 1) [000038] ------------ arg3 in r9 +--* LCL_VAR int V01 arg1 u:1 $81
N010 ( 3, 10) [000041] ------------ arg0 in rcx \--* CNS_INT(h) long 0xd1ffab1e method $242
---------
***** BB01, STMT00012(before)
N010 ( 23, 17) [000051] -ACXG---R--- * ASG int
N009 ( 3, 2) [000050] D------N---- +--* LCL_VAR int V06 loc3 d:2
N008 ( 19, 14) [000048] --CXG------- \--* CALL int Test2.DoTestImpl5
N005 ( 3, 4) [000180] ------------ arg2 in r8 +--* CAST int <- ubyte <- int
N004 ( 2, 2) [000047] ------------ | \--* LCL_VAR int V02 arg2 u:1
N006 ( 1, 1) [000045] ------------ arg0 in rcx +--* LCL_VAR int V00 arg0 u:1
N007 ( 1, 1) [000046] ------------ arg1 in rdx \--* LCL_VAR int V01 arg1 u:1
N001 [000182] ARGPLACE => $153 {153}
N002 [000183] ARGPLACE => $154 {154}
N003 [000181] ARGPLACE => $155 {155}
N004 [000047] LCL_VAR V02 arg2 u:1 => $c0 {InitVal($42)}
VNForCastOper(ubyte) is $44
N005 [000180] CAST => $180 {Cast($c0, $44)}
N006 [000045] LCL_VAR V00 arg0 u:1 => $80 {InitVal($40)}
N007 [000046] LCL_VAR V01 arg1 u:1 => $81 {InitVal($41)}
VN of ARGPLACE tree [000182] updated to $80 {InitVal($40)}
VN of ARGPLACE tree [000183] updated to $81 {InitVal($41)}
VN of ARGPLACE tree [000181] updated to $180 {Cast($c0, $44)}
fgCurMemoryVN[GcHeap] assigned for CALL at [000048] to VN: $1c7.
N008 [000048] CALL => $156 {156}
N009 [000050] LCL_VAR V06 loc3 d:2 => $156 {156}
N010 [000051] ASG => $156 {156}
***** BB01, STMT00012(after)
N010 ( 23, 17) [000051] -ACXG---R--- * ASG int $156
N009 ( 3, 2) [000050] D------N---- +--* LCL_VAR int V06 loc3 d:2 $156
N008 ( 19, 14) [000048] --CXG------- \--* CALL int Test2.DoTestImpl5 $156
N005 ( 3, 4) [000180] ------------ arg2 in r8 +--* CAST int <- ubyte <- int $180
N004 ( 2, 2) [000047] ------------ | \--* LCL_VAR int V02 arg2 u:1 $c0
N006 ( 1, 1) [000045] ------------ arg0 in rcx +--* LCL_VAR int V00 arg0 u:1 $80
N007 ( 1, 1) [000046] ------------ arg1 in rdx \--* LCL_VAR int V01 arg1 u:1 $81
---------
***** BB01, STMT00027(before)
N005 ( 3, 3) [000114] -A------R--- * ASG int
N004 ( 1, 1) [000113] D------N---- +--* LCL_VAR int V13 tmp4 d:2
N003 ( 3, 3) [000140] ------------ \--* ADD int
N001 ( 1, 1) [000052] ------------ +--* LCL_VAR int V00 arg0 u:1
N002 ( 1, 1) [000053] ------------ \--* LCL_VAR int V01 arg1 u:1 (last use)
N001 [000052] LCL_VAR V00 arg0 u:1 => $80 {InitVal($40)}
N002 [000053] LCL_VAR V01 arg1 u:1 (last use) => $81 {InitVal($41)}
N003 [000140] ADD => $181 {ADD($80, $81)}
N004 [000113] LCL_VAR V13 tmp4 d:2 => $181 {ADD($80, $81)}
N005 [000114] ASG => $181 {ADD($80, $81)}
***** BB01, STMT00027(after)
N005 ( 3, 3) [000114] -A------R--- * ASG int $181
N004 ( 1, 1) [000113] D------N---- +--* LCL_VAR int V13 tmp4 d:2 $181
N003 ( 3, 3) [000140] ------------ \--* ADD int $181
N001 ( 1, 1) [000052] ------------ +--* LCL_VAR int V00 arg0 u:1 $80
N002 ( 1, 1) [000053] ------------ \--* LCL_VAR int V01 arg1 u:1 (last use) $81
---------
***** BB01, STMT00029(before)
N006 ( 8, 8) [000120] -A------R--- * ASG int
N005 ( 1, 1) [000119] D------N---- +--* LCL_VAR int V14 tmp5 d:2
N004 ( 8, 8) [000145] ------------ \--* MUL int
N001 ( 1, 1) [000115] ------------ +--* LCL_VAR int V13 tmp4 u:2 (last use)
N003 ( 3, 4) [000186] ------------ \--* CAST int <- ubyte <- int
N002 ( 2, 2) [000054] ------------ \--* LCL_VAR int V02 arg2 u:1
N001 [000115] LCL_VAR V13 tmp4 u:2 (last use) => $181 {ADD($80, $81)}
N002 [000054] LCL_VAR V02 arg2 u:1 => $c0 {InitVal($42)}
VNForCastOper(ubyte) is $44
N003 [000186] CAST => $180 {Cast($c0, $44)}
N004 [000145] MUL => $182 {MUL($180, $181)}
N005 [000119] LCL_VAR V14 tmp5 d:2 => $182 {MUL($180, $181)}
N006 [000120] ASG => $182 {MUL($180, $181)}
***** BB01, STMT00029(after)
N006 ( 8, 8) [000120] -A------R--- * ASG int $182
N005 ( 1, 1) [000119] D------N---- +--* LCL_VAR int V14 tmp5 d:2 $182
N004 ( 8, 8) [000145] ------------ \--* MUL int $182
N001 ( 1, 1) [000115] ------------ +--* LCL_VAR int V13 tmp4 u:2 (last use) $181
N003 ( 3, 4) [000186] ------------ \--* CAST int <- ubyte <- int $180
N002 ( 2, 2) [000054] ------------ \--* LCL_VAR int V02 arg2 u:1 $c0
---------
***** BB01, STMT00033(before)
N006 ( 8, 8) [000131] -A------R--- * ASG int
N005 ( 1, 1) [000130] D------N---- +--* LCL_VAR int V15 tmp6 d:2
N004 ( 8, 8) [000150] ------------ \--* MUL int
N001 ( 1, 1) [000121] ------------ +--* LCL_VAR int V00 arg0 u:1 (last use)
N003 ( 3, 4) [000187] ------------ \--* CAST int <- ubyte <- int
N002 ( 2, 2) [000122] ------------ \--* LCL_VAR int V02 arg2 u:1 (last use)
N001 [000121] LCL_VAR V00 arg0 u:1 (last use) => $80 {InitVal($40)}
N002 [000122] LCL_VAR V02 arg2 u:1 (last use) => $c0 {InitVal($42)}
VNForCastOper(ubyte) is $44
N003 [000187] CAST => $180 {Cast($c0, $44)}
N004 [000150] MUL => $183 {MUL($80, $180)}
N005 [000130] LCL_VAR V15 tmp6 d:2 => $183 {MUL($80, $180)}
N006 [000131] ASG => $183 {MUL($80, $180)}
***** BB01, STMT00033(after)
N006 ( 8, 8) [000131] -A------R--- * ASG int $183
N005 ( 1, 1) [000130] D------N---- +--* LCL_VAR int V15 tmp6 d:2 $183
N004 ( 8, 8) [000150] ------------ \--* MUL int $183
N001 ( 1, 1) [000121] ------------ +--* LCL_VAR int V00 arg0 u:1 (last use) $80
N003 ( 3, 4) [000187] ------------ \--* CAST int <- ubyte <- int $180
N002 ( 2, 2) [000122] ------------ \--* LCL_VAR int V02 arg2 u:1 (last use) $c0
---------
***** BB01, STMT00014(before)
N007 ( 28, 10) [000058] -A-X----R--- * ASG int
N006 ( 3, 2) [000057] D------N---- +--* LCL_VAR int V07 loc4 d:2
N005 ( 24, 7) [000156] ---X-------- \--* DIV int
N001 ( 1, 1) [000132] ------------ +--* LCL_VAR int V15 tmp6 u:2 (last use)
N004 ( 3, 3) [000153] ------------ \--* RSH int
N002 ( 1, 1) [000127] ------------ +--* LCL_VAR int V14 tmp5 u:2 (last use)
N003 ( 1, 1) [000152] ------------ \--* CNS_INT int 2
N001 [000132] LCL_VAR V15 tmp6 u:2 (last use) => $183 {MUL($80, $180)}
N002 [000127] LCL_VAR V14 tmp5 u:2 (last use) => $182 {MUL($180, $181)}
N003 [000152] CNS_INT 2 => $42 {IntCns 2}
N004 [000153] RSH => $184 {RSH($182, $42)}
N005 [000156] DIV => $186 {norm=$185 {DIV($183, $184)}, exc=$344( {DivideByZeroExc($184)}, {ArithmeticExc($183, $184)})}
N006 [000057] LCL_VAR V07 loc4 d:2 => $185 {DIV($183, $184)}
N007 [000058] ASG => $186 {norm=$185 {DIV($183, $184)}, exc=$344( {DivideByZeroExc($184)}, {ArithmeticExc($183, $184)})}
***** BB01, STMT00014(after)
N007 ( 28, 10) [000058] -A-X----R--- * ASG int $186
N006 ( 3, 2) [000057] D------N---- +--* LCL_VAR int V07 loc4 d:2 $185
N005 ( 24, 7) [000156] ---X-------- \--* DIV int $186
N001 ( 1, 1) [000132] ------------ +--* LCL_VAR int V15 tmp6 u:2 (last use) $183
N004 ( 3, 3) [000153] ------------ \--* RSH int $184
N002 ( 1, 1) [000127] ------------ +--* LCL_VAR int V14 tmp5 u:2 (last use) $182
N003 ( 1, 1) [000152] ------------ \--* CNS_INT int 2 $42
---------
***** BB01, STMT00015(before)
N012 ( 22, 17) [000069] ------------ * RETURN int
N011 ( 21, 16) [000068] ------------ \--* ADD int
N009 ( 17, 13) [000066] ------------ +--* ADD int
N007 ( 13, 10) [000064] ------------ | +--* ADD int
N005 ( 9, 7) [000062] ------------ | | +--* ADD int
N003 ( 5, 4) [000060] ------------ | | | +--* ADD int
N001 ( 1, 1) [000012] ------------ | | | | +--* LCL_VAR int V10 tmp1 u:2 (last use)
N002 ( 3, 2) [000059] ------------ | | | | \--* LCL_VAR int V03 loc0 u:2 (last use)
N004 ( 3, 2) [000061] ------------ | | | \--* LCL_VAR int V04 loc1 u:2 (last use)
N006 ( 3, 2) [000063] ------------ | | \--* LCL_VAR int V05 loc2 u:2 (last use)
N008 ( 3, 2) [000065] ------------ | \--* LCL_VAR int V06 loc3 u:2 (last use)
N010 ( 3, 2) [000067] ------------ \--* LCL_VAR int V07 loc4 u:2 (last use)
N001 [000012] LCL_VAR V10 tmp1 u:2 (last use) => $143 {143}
N002 [000059] LCL_VAR V03 loc0 u:2 (last use) => $148 {148}
N003 [000060] ADD => $187 {ADD($143, $148)}
N004 [000061] LCL_VAR V04 loc1 u:2 (last use) => $14d {14d}
N005 [000062] ADD => $188 {ADD($14d, $187)}
N006 [000063] LCL_VAR V05 loc2 u:2 (last use) => $151 {151}
N007 [000064] ADD => $189 {ADD($151, $188)}
N008 [000065] LCL_VAR V06 loc3 u:2 (last use) => $156 {156}
N009 [000066] ADD => $18a {ADD($156, $189)}
N010 [000067] LCL_VAR V07 loc4 u:2 (last use) => $185 {DIV($183, $184)}
N011 [000068] ADD => $18b {ADD($185, $18a)}
N012 [000069] RETURN => $15c {15c}
***** BB01, STMT00015(after)
N012 ( 22, 17) [000069] ------------ * RETURN int $15c
N011 ( 21, 16) [000068] ------------ \--* ADD int $18b
N009 ( 17, 13) [000066] ------------ +--* ADD int $18a
N007 ( 13, 10) [000064] ------------ | +--* ADD int $189
N005 ( 9, 7) [000062] ------------ | | +--* ADD int $188
N003 ( 5, 4) [000060] ------------ | | | +--* ADD int $187
N001 ( 1, 1) [000012] ------------ | | | | +--* LCL_VAR int V10 tmp1 u:2 (last use) $143
N002 ( 3, 2) [000059] ------------ | | | | \--* LCL_VAR int V03 loc0 u:2 (last use) $148
N004 ( 3, 2) [000061] ------------ | | | \--* LCL_VAR int V04 loc1 u:2 (last use) $14d
N006 ( 3, 2) [000063] ------------ | | \--* LCL_VAR int V05 loc2 u:2 (last use) $151
N008 ( 3, 2) [000065] ------------ | \--* LCL_VAR int V06 loc3 u:2 (last use) $156
N010 ( 3, 2) [000067] ------------ \--* LCL_VAR int V07 loc4 u:2 (last use) $185
finish(BB01).
*************** In optVnCopyProp()
*************** In SsaBuilder::ComputeDominators(Compiler*, ...)
Copy Assertion for BB01
curSsaName stack: { }
Live vars: {V00 V01 V02} => {V00 V01 V02 V10}
Live vars: {V00 V01 V02 V10} => {V00 V01 V02 V03 V10}
Live vars: {V00 V01 V02 V03 V10} => {V00 V01 V02 V03 V08 V10}
Live vars: {V00 V01 V02 V03 V08 V10} => {V00 V01 V02 V03 V10}
Live vars: {V00 V01 V02 V03 V10} => {V00 V01 V02 V03 V04 V10}
Live vars: {V00 V01 V02 V03 V04 V10} => {V00 V01 V02 V03 V04 V10 V11}
Live vars: {V00 V01 V02 V03 V04 V10 V11} => {V00 V01 V02 V03 V04 V10}
Live vars: {V00 V01 V02 V03 V04 V10} => {V00 V01 V02 V03 V04 V05 V10}
Live vars: {V00 V01 V02 V03 V04 V05 V10} => {V00 V01 V02 V03 V04 V05 V06 V10}
Live vars: {V00 V01 V02 V03 V04 V05 V06 V10} => {V00 V02 V03 V04 V05 V06 V10}
Live vars: {V00 V02 V03 V04 V05 V06 V10} => {V00 V02 V03 V04 V05 V06 V10 V13}
Live vars: {V00 V02 V03 V04 V05 V06 V10 V13} => {V00 V02 V03 V04 V05 V06 V10}
Live vars: {V00 V02 V03 V04 V05 V06 V10} => {V00 V02 V03 V04 V05 V06 V10 V14}
Live vars: {V00 V02 V03 V04 V05 V06 V10 V14} => {V02 V03 V04 V05 V06 V10 V14}
Live vars: {V02 V03 V04 V05 V06 V10 V14} => {V03 V04 V05 V06 V10 V14}
Live vars: {V03 V04 V05 V06 V10 V14} => {V03 V04 V05 V06 V10 V14 V15}
Live vars: {V03 V04 V05 V06 V10 V14 V15} => {V03 V04 V05 V06 V10 V14}
Live vars: {V03 V04 V05 V06 V10 V14} => {V03 V04 V05 V06 V10}
Live vars: {V03 V04 V05 V06 V10} => {V03 V04 V05 V06 V07 V10}
Live vars: {V03 V04 V05 V06 V07 V10} => {V03 V04 V05 V06 V07}
Live vars: {V03 V04 V05 V06 V07} => {V04 V05 V06 V07}
Live vars: {V04 V05 V06 V07} => {V05 V06 V07}
Live vars: {V05 V06 V07} => {V06 V07}
Live vars: {V06 V07} => {V07}
Live vars: {V07} => {}
*************** In optOptimizeCSEs()
Blocks/Trees at start of optOptimizeCSE phase
-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..051) (return) i label target gcsafe newobj
-----------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [000..051) (return), preds={} succs={}
***** BB01
STMT00002 (IL ???... ???)
N010 ( 19, 14) [000011] -ACXG---R--- * ASG int $143
N009 ( 1, 1) [000010] D------N---- +--* LCL_VAR int V10 tmp1 d:2 $143
N008 ( 19, 14) [000003] --CXG------- \--* CALL int Test2.DoTestImpl1 $143
N005 ( 3, 4) [000158] ------------ arg2 in r8 +--* CAST int <- ubyte <- int $180
N004 ( 2, 2) [000002] ------------ | \--* LCL_VAR int V02 arg2 u:1 $c0
N006 ( 1, 1) [000000] ------------ arg0 in rcx +--* LCL_VAR int V00 arg0 u:1 $80
N007 ( 1, 1) [000001] ------------ arg1 in rdx \--* LCL_VAR int V01 arg1 u:1 $81
***** BB01
STMT00003 (IL ???... ???)
N012 ( 26, 28) [000015] -ACXG---R--- * ASG int $148
N011 ( 3, 2) [000014] D------N---- +--* LCL_VAR int V03 loc0 d:2 $148
N010 ( 22, 25) [000008] --CXG------- \--* CALL int Test2.DoTestImpl2 $148
N006 ( 3, 4) [000162] ------------ arg3 in r9 +--* CAST int <- ubyte <- int $180
N005 ( 2, 2) [000007] ------------ | \--* LCL_VAR int V02 arg2 u:1 $c0
N007 ( 1, 1) [000005] ------------ arg1 in rdx +--* LCL_VAR int V00 arg0 u:1 $80
N008 ( 1, 1) [000006] ------------ arg2 in r8 +--* LCL_VAR int V01 arg1 u:1 $81
N009 ( 3, 10) [000009] ------------ arg0 in rcx \--* CNS_INT(h) long 0xd1ffab1e method $240
***** BB01
STMT00004 (IL ???...0x014)
N005 ( 9, 8) [000019] -A------R--- * ASG byte $VN.Void
N004 ( 7, 6) [000168] n------N---- +--* IND byte $40
N003 ( 3, 3) [000167] ------------ | \--* ADDR byref $2c0
N002 ( 3, 2) [000016] D------N---- | \--* LCL_VAR struct V08 loc5 d:2
N001 ( 1, 1) [000018] ------------ \--* CNS_INT int 0 $40
***** BB01
STMT00006 (IL ???... ???)
N012 ( 27, 23) [000029] -ACXG---R--- * ASG int $14d
N011 ( 3, 2) [000028] D------N---- +--* LCL_VAR int V04 loc1 d:2 $14d
N010 ( 23, 20) [000024] --CXG------- \--* CALL int Test2.DoTestImpl3 $14d
N006 ( 3, 4) [000169] ------------ arg3 in r9 +--* CAST int <- ubyte <- int $180
N005 ( 2, 2) [000023] ------------ | \--* LCL_VAR int V02 arg2 u:1 $c0
N007 ( 4, 5) [000020] ------------ arg0 in rcx +--* LCL_FLD byte V08 loc5 u:2[+0] (last use) $301
N008 ( 1, 1) [000021] ------------ arg1 in rdx +--* LCL_VAR int V00 arg0 u:1 $80
N009 ( 1, 1) [000022] ------------ arg2 in r8 \--* LCL_VAR int V01 arg1 u:1 $81
***** BB01
STMT00007 (IL ???...0x031)
N005 ( 17, 16) [000033] -AC-----R--- * ASG ref $340
N004 ( 1, 1) [000032] D------N---- +--* LCL_VAR ref V11 tmp2 d:2 $340
N003 ( 17, 16) [000031] --C--------- \--* CALL help ref HELPER.CORINFO_HELP_NEWSFAST $340
N002 ( 3, 10) [000030] ------------ arg0 in rcx \--* CNS_INT(h) long 0xd1ffab1e method $241
***** BB01
STMT00010 (IL ???... ???)
N013 ( 30, 29) [000044] -ACXG---R--- * ASG int $151
N012 ( 3, 2) [000043] D------N---- +--* LCL_VAR int V05 loc2 d:2 $151
N011 ( 26, 26) [000040] --CXG------- \--* CALL int Test2.DoTestImpl4 $151
N006 ( 3, 4) [000175] ------------ arg4 out+20 +--* CAST int <- ubyte <- int $180
N005 ( 2, 2) [000039] ------------ | \--* LCL_VAR int V02 arg2 u:1 $c0
N007 ( 1, 1) [000036] ------------ arg1 in rdx +--* LCL_VAR ref V11 tmp2 u:2 (last use) $340
N008 ( 1, 1) [000037] ------------ arg2 in r8 +--* LCL_VAR int V00 arg0 u:1 $80
N009 ( 1, 1) [000038] ------------ arg3 in r9 +--* LCL_VAR int V01 arg1 u:1 $81
N010 ( 3, 10) [000041] ------------ arg0 in rcx \--* CNS_INT(h) long 0xd1ffab1e method $242
***** BB01
STMT00012 (IL ???... ???)
N010 ( 23, 17) [000051] -ACXG---R--- * ASG int $156
N009 ( 3, 2) [000050] D------N---- +--* LCL_VAR int V06 loc3 d:2 $156
N008 ( 19, 14) [000048] --CXG------- \--* CALL int Test2.DoTestImpl5 $156
N005 ( 3, 4) [000180] ------------ arg2 in r8 +--* CAST int <- ubyte <- int $180
N004 ( 2, 2) [000047] ------------ | \--* LCL_VAR int V02 arg2 u:1 $c0
N006 ( 1, 1) [000045] ------------ arg0 in rcx +--* LCL_VAR int V00 arg0 u:1 $80
N007 ( 1, 1) [000046] ------------ arg1 in rdx \--* LCL_VAR int V01 arg1 u:1 $81
***** BB01
STMT00027 (IL ???... ???)
N005 ( 3, 3) [000114] -A------R--- * ASG int $181
N004 ( 1, 1) [000113] D------N---- +--* LCL_VAR int V13 tmp4 d:2 $181
N003 ( 3, 3) [000140] ------------ \--* ADD int $181
N001 ( 1, 1) [000052] ------------ +--* LCL_VAR int V00 arg0 u:1 $80
N002 ( 1, 1) [000053] ------------ \--* LCL_VAR int V01 arg1 u:1 (last use) $81
***** BB01
STMT00029 (IL ???... ???)
N006 ( 8, 8) [000120] -A------R--- * ASG int $182
N005 ( 1, 1) [000119] D------N---- +--* LCL_VAR int V14 tmp5 d:2 $182
N004 ( 8, 8) [000145] ------------ \--* MUL int $182
N001 ( 1, 1) [000115] ------------ +--* LCL_VAR int V13 tmp4 u:2 (last use) $181
N003 ( 3, 4) [000186] ------------ \--* CAST int <- ubyte <- int $180
N002 ( 2, 2) [000054] ------------ \--* LCL_VAR int V02 arg2 u:1 $c0
***** BB01
STMT00033 (IL ???... ???)
N006 ( 8, 8) [000131] -A------R--- * ASG int $183
N005 ( 1, 1) [000130] D------N---- +--* LCL_VAR int V15 tmp6 d:2 $183
N004 ( 8, 8) [000150] ------------ \--* MUL int $183
N001 ( 1, 1) [000121] ------------ +--* LCL_VAR int V00 arg0 u:1 (last use) $80
N003 ( 3, 4) [000187] ------------ \--* CAST int <- ubyte <- int $180
N002 ( 2, 2) [000122] ------------ \--* LCL_VAR int V02 arg2 u:1 (last use) $c0
***** BB01
STMT00014 (IL ???... ???)
N007 ( 28, 10) [000058] -A-X----R--- * ASG int $186
N006 ( 3, 2) [000057] D------N---- +--* LCL_VAR int V07 loc4 d:2 $185
N005 ( 24, 7) [000156] ---X-------- \--* DIV int $186
N001 ( 1, 1) [000132] ------------ +--* LCL_VAR int V15 tmp6 u:2 (last use) $183
N004 ( 3, 3) [000153] ------------ \--* RSH int $184
N002 ( 1, 1) [000127] ------------ +--* LCL_VAR int V14 tmp5 u:2 (last use) $182
N003 ( 1, 1) [000152] ------------ \--* CNS_INT int 2 $42
***** BB01
STMT00015 (IL ???...0x050)
N012 ( 22, 17) [000069] ------------ * RETURN int $15c
N011 ( 21, 16) [000068] ------------ \--* ADD int $18b
N009 ( 17, 13) [000066] ------------ +--* ADD int $18a
N007 ( 13, 10) [000064] ------------ | +--* ADD int $189
N005 ( 9, 7) [000062] ------------ | | +--* ADD int $188
N003 ( 5, 4) [000060] ------------ | | | +--* ADD int $187
N001 ( 1, 1) [000012] ------------ | | | | +--* LCL_VAR int V10 tmp1 u:2 (last use) $143
N002 ( 3, 2) [000059] ------------ | | | | \--* LCL_VAR int V03 loc0 u:2 (last use) $148
N004 ( 3, 2) [000061] ------------ | | | \--* LCL_VAR int V04 loc1 u:2 (last use) $14d
N006 ( 3, 2) [000063] ------------ | | \--* LCL_VAR int V05 loc2 u:2 (last use) $151
N008 ( 3, 2) [000065] ------------ | \--* LCL_VAR int V06 loc3 u:2 (last use) $156
N010 ( 3, 2) [000067] ------------ \--* LCL_VAR int V07 loc4 u:2 (last use) $185
-------------------------------------------------------------------------------------------------------------------
*************** In optOptimizeValnumCSEs()
CSE candidate #01, vn=$180 cseMask=0000000000000001 in BB01, [cost= 3, size= 4]:
N006 ( 3, 4) CSE #01 (use)[000162] ------------ * CAST int <- ubyte <- int $180
N005 ( 2, 2) [000007] ------------ \--* LCL_VAR int V02 arg2 u:1 $c0
Blocks that generate CSE def/uses
BB01 cseGen = 0000000000000001
After performing DataFlow for ValnumCSE's
BB01 cseIn = 0000000000000000 cseOut = 0000000000000001
Labeling the CSEs with Use/Def information
BB01 [000158] Def of CSE #01 [weight=1 ]
BB01 [000162] Use of CSE #01 [weight=1 ]
BB01 [000169] Use of CSE #01 [weight=1 ]
BB01 [000175] Use of CSE #01 [weight=1 ]
BB01 [000180] Use of CSE #01 [weight=1 ]
BB01 [000186] Use of CSE #01 [weight=1 ]
BB01 [000187] Use of CSE #01 [weight=1 ]
************ Trees at start of optValnumCSE_Heuristic()
------------ BB01 [000..051) (return), preds={} succs={}
***** BB01
STMT00002 (IL ???... ???)
N010 ( 19, 14) [000011] -ACXG---R--- * ASG int $143
N009 ( 1, 1) [000010] D------N---- +--* LCL_VAR int V10 tmp1 d:2 $143
N008 ( 19, 14) [000003] --CXG------- \--* CALL int Test2.DoTestImpl1 $143
N005 ( 3, 4) CSE #01 (def)[000158] ------------ arg2 in r8 +--* CAST int <- ubyte <- int $180
N004 ( 2, 2) [000002] ------------ | \--* LCL_VAR int V02 arg2 u:1 $c0
N006 ( 1, 1) [000000] ------------ arg0 in rcx +--* LCL_VAR int V00 arg0 u:1 $80
N007 ( 1, 1) [000001] ------------ arg1 in rdx \--* LCL_VAR int V01 arg1 u:1 $81
***** BB01
STMT00003 (IL ???... ???)
N012 ( 26, 28) [000015] -ACXG---R--- * ASG int $148
N011 ( 3, 2) [000014] D------N---- +--* LCL_VAR int V03 loc0 d:2 $148
N010 ( 22, 25) [000008] --CXG------- \--* CALL int Test2.DoTestImpl2 $148
N006 ( 3, 4) CSE #01 (use)[000162] ------------ arg3 in r9 +--* CAST int <- ubyte <- int $180
N005 ( 2, 2) [000007] ------------ | \--* LCL_VAR int V02 arg2 u:1 $c0
N007 ( 1, 1) [000005] ------------ arg1 in rdx +--* LCL_VAR int V00 arg0 u:1 $80
N008 ( 1, 1) [000006] ------------ arg2 in r8 +--* LCL_VAR int V01 arg1 u:1 $81
N009 ( 3, 10) [000009] ------------ arg0 in rcx \--* CNS_INT(h) long 0xd1ffab1e method $240
***** BB01
STMT00004 (IL ???...0x014)
N005 ( 9, 8) [000019] -A------R--- * ASG byte $VN.Void
N004 ( 7, 6) [000168] n------N---- +--* IND byte $40
N003 ( 3, 3) [000167] ------------ | \--* ADDR byref $2c0
N002 ( 3, 2) [000016] D------N---- | \--* LCL_VAR struct V08 loc5 d:2
N001 ( 1, 1) [000018] ------------ \--* CNS_INT int 0 $40
***** BB01
STMT00006 (IL ???... ???)
N012 ( 27, 23) [000029] -ACXG---R--- * ASG int $14d
N011 ( 3, 2) [000028] D------N---- +--* LCL_VAR int V04 loc1 d:2 $14d
N010 ( 23, 20) [000024] --CXG------- \--* CALL int Test2.DoTestImpl3 $14d
N006 ( 3, 4) CSE #01 (use)[000169] ------------ arg3 in r9 +--* CAST int <- ubyte <- int $180
N005 ( 2, 2) [000023] ------------ | \--* LCL_VAR int V02 arg2 u:1 $c0
N007 ( 4, 5) [000020] ------------ arg0 in rcx +--* LCL_FLD byte V08 loc5 u:2[+0] (last use) $301
N008 ( 1, 1) [000021] ------------ arg1 in rdx +--* LCL_VAR int V00 arg0 u:1 $80
N009 ( 1, 1) [000022] ------------ arg2 in r8 \--* LCL_VAR int V01 arg1 u:1 $81
***** BB01
STMT00007 (IL ???...0x031)
N005 ( 17, 16) [000033] -AC-----R--- * ASG ref $340
N004 ( 1, 1) [000032] D------N---- +--* LCL_VAR ref V11 tmp2 d:2 $340
N003 ( 17, 16) [000031] --C--------- \--* CALL help ref HELPER.CORINFO_HELP_NEWSFAST $340
N002 ( 3, 10) [000030] ------------ arg0 in rcx \--* CNS_INT(h) long 0xd1ffab1e method $241
***** BB01
STMT00010 (IL ???... ???)
N013 ( 30, 29) [000044] -ACXG---R--- * ASG int $151
N012 ( 3, 2) [000043] D------N---- +--* LCL_VAR int V05 loc2 d:2 $151
N011 ( 26, 26) [000040] --CXG------- \--* CALL int Test2.DoTestImpl4 $151
N006 ( 3, 4) CSE #01 (use)[000175] ------------ arg4 out+20 +--* CAST int <- ubyte <- int $180
N005 ( 2, 2) [000039] ------------ | \--* LCL_VAR int V02 arg2 u:1 $c0
N007 ( 1, 1) [000036] ------------ arg1 in rdx +--* LCL_VAR ref V11 tmp2 u:2 (last use) $340
N008 ( 1, 1) [000037] ------------ arg2 in r8 +--* LCL_VAR int V00 arg0 u:1 $80
N009 ( 1, 1) [000038] ------------ arg3 in r9 +--* LCL_VAR int V01 arg1 u:1 $81
N010 ( 3, 10) [000041] ------------ arg0 in rcx \--* CNS_INT(h) long 0xd1ffab1e method $242
***** BB01
STMT00012 (IL ???... ???)
N010 ( 23, 17) [000051] -ACXG---R--- * ASG int $156
N009 ( 3, 2) [000050] D------N---- +--* LCL_VAR int V06 loc3 d:2 $156
N008 ( 19, 14) [000048] --CXG------- \--* CALL int Test2.DoTestImpl5 $156
N005 ( 3, 4) CSE #01 (use)[000180] ------------ arg2 in r8 +--* CAST int <- ubyte <- int $180
N004 ( 2, 2) [000047] ------------ | \--* LCL_VAR int V02 arg2 u:1 $c0
N006 ( 1, 1) [000045] ------------ arg0 in rcx +--* LCL_VAR int V00 arg0 u:1 $80
N007 ( 1, 1) [000046] ------------ arg1 in rdx \--* LCL_VAR int V01 arg1 u:1 $81
***** BB01
STMT00027 (IL ???... ???)
N005 ( 3, 3) [000114] -A------R--- * ASG int $181
N004 ( 1, 1) [000113] D------N---- +--* LCL_VAR int V13 tmp4 d:2 $181
N003 ( 3, 3) [000140] ------------ \--* ADD int $181
N001 ( 1, 1) [000052] ------------ +--* LCL_VAR int V00 arg0 u:1 $80
N002 ( 1, 1) [000053] ------------ \--* LCL_VAR int V01 arg1 u:1 (last use) $81
***** BB01
STMT00029 (IL ???... ???)
N006 ( 8, 8) [000120] -A------R--- * ASG int $182
N005 ( 1, 1) [000119] D------N---- +--* LCL_VAR int V14 tmp5 d:2 $182
N004 ( 8, 8) [000145] ------------ \--* MUL int $182
N001 ( 1, 1) [000115] ------------ +--* LCL_VAR int V13 tmp4 u:2 (last use) $181
N003 ( 3, 4) CSE #01 (use)[000186] ------------ \--* CAST int <- ubyte <- int $180
N002 ( 2, 2) [000054] ------------ \--* LCL_VAR int V02 arg2 u:1 $c0
***** BB01
STMT00033 (IL ???... ???)
N006 ( 8, 8) [000131] -A------R--- * ASG int $183
N005 ( 1, 1) [000130] D------N---- +--* LCL_VAR int V15 tmp6 d:2 $183
N004 ( 8, 8) [000150] ------------ \--* MUL int $183
N001 ( 1, 1) [000121] ------------ +--* LCL_VAR int V00 arg0 u:1 (last use) $80
N003 ( 3, 4) CSE #01 (use)[000187] ------------ \--* CAST int <- ubyte <- int $180
N002 ( 2, 2) [000122] ------------ \--* LCL_VAR int V02 arg2 u:1 (last use) $c0
***** BB01
STMT00014 (IL ???... ???)
N007 ( 28, 10) [000058] -A-X----R--- * ASG int $186
N006 ( 3, 2) [000057] D------N---- +--* LCL_VAR int V07 loc4 d:2 $185
N005 ( 24, 7) [000156] ---X-------- \--* DIV int $186
N001 ( 1, 1) [000132] ------------ +--* LCL_VAR int V15 tmp6 u:2 (last use) $183
N004 ( 3, 3) [000153] ------------ \--* RSH int $184
N002 ( 1, 1) [000127] ------------ +--* LCL_VAR int V14 tmp5 u:2 (last use) $182
N003 ( 1, 1) [000152] ------------ \--* CNS_INT int 2 $42
***** BB01
STMT00015 (IL ???...0x050)
N012 ( 22, 17) [000069] ------------ * RETURN int $15c
N011 ( 21, 16) [000068] ------------ \--* ADD int $18b
N009 ( 17, 13) [000066] ------------ +--* ADD int $18a
N007 ( 13, 10) [000064] ------------ | +--* ADD int $189
N005 ( 9, 7) [000062] ------------ | | +--* ADD int $188
N003 ( 5, 4) [000060] ------------ | | | +--* ADD int $187
N001 ( 1, 1) [000012] ------------ | | | | +--* LCL_VAR int V10 tmp1 u:2 (last use) $143
N002 ( 3, 2) [000059] ------------ | | | | \--* LCL_VAR int V03 loc0 u:2 (last use) $148
N004 ( 3, 2) [000061] ------------ | | | \--* LCL_VAR int V04 loc1 u:2 (last use) $14d
N006 ( 3, 2) [000063] ------------ | | \--* LCL_VAR int V05 loc2 u:2 (last use) $151
N008 ( 3, 2) [000065] ------------ | \--* LCL_VAR int V06 loc3 u:2 (last use) $156
N010 ( 3, 2) [000067] ------------ \--* LCL_VAR int V07 loc4 u:2 (last use) $185
-------------------------------------------------------------------------------------------------------------------
Aggressive CSE Promotion cutoff is 300
Moderate CSE Promotion cutoff is 150
Framesize estimate is 0x0010
We have a small frame
Sorted CSE candidates:
CSE #01, {$180, $4 } cseMask=0000000000000001,useCnt=6: [def=100, use=600] :: N005 ( 3, 4) CSE #01 (def)[000158] ------------ * CAST int <- ubyte <- int $180
Considering CSE #01 {$180, $4 } [def=100, use=600, cost= 3] CSE Expression:
N005 ( 3, 4) CSE #01 (def)[000158] ------------ * CAST int <- ubyte <- int $180
N004 ( 2, 2) [000002] ------------ \--* LCL_VAR int V02 arg2 u:1 $c0
Aggressive CSE Promotion (800 >= 300)
cseRefCnt=800, aggressiveRefCnt=300, moderateRefCnt=150
defCnt=100, useCnt=600, cost=3, size=4
def_cost=1, use_cost=1, extra_no_cost=36, extra_yes_cost=0
CSE cost savings check (1836 >= 700) passes
Promoting CSE:
lvaGrabTemp returning 19 (V19 rat0) (a long lifetime temp) called for ValNumCSE.
CSE #01 def at [000158] replaced in BB01 with def of V19
ReMorphing args for 3.CALL:
argSlots=3, preallocatedArgCount=4, nextSlotNum=4, outgoingArgSpaceSize=32
ArgTable for 3.CALL after fgMorphArgs:
fgArgTabEntry[arg 2 191.COMMA ubyte, 1 reg: r8, align=1, lateArgInx=0, processed]
fgArgTabEntry[arg 0 0.LCL_VAR int, 1 reg: rcx, align=1, lateArgInx=1, processed]
fgArgTabEntry[arg 1 1.LCL_VAR int, 1 reg: rdx, align=1, lateArgInx=2, processed]
optValnumCSE morphed tree:
N014 ( 26, 19) [000011] -ACXG---R--- * ASG int $143
N013 ( 1, 1) [000010] D------N---- +--* LCL_VAR int V10 tmp1 d:2 $143
N012 ( 26, 19) [000003] -ACXG------- \--* CALL int Test2.DoTestImpl1 $143
N009 ( 10, 9) [000191] -A---------- arg2 in r8 +--* COMMA int $180
N007 ( 7, 7) [000189] -A------R--- | +--* ASG int $VN.Void
N006 ( 3, 2) [000188] D------N---- | | +--* LCL_VAR int V19 cse0 $180
N005 ( 3, 4) [000158] ------------ | | \--* CAST int <- ubyte <- int $180
N004 ( 2, 2) [000002] ------------ | | \--* LCL_VAR int V02 arg2 u:1 $c0
N008 ( 3, 2) [000190] ------------ | \--* LCL_VAR int V19 cse0 $180
N010 ( 1, 1) [000000] ------------ arg0 in rcx +--* LCL_VAR int V00 arg0 u:1 $80
N011 ( 1, 1) [000001] ------------ arg1 in rdx \--* LCL_VAR int V01 arg1 u:1 $81
Working on the replacement of the CSE #01 use at [000162] in BB01
ReMorphing args for 8.CALL:
argSlots=4, preallocatedArgCount=4, nextSlotNum=4, outgoingArgSpaceSize=32
ArgTable for 8.CALL after fgMorphArgs:
fgArgTabEntry[arg 3 192.LCL_VAR ubyte, 1 reg: r9, align=1, lateArgInx=0, processed]
fgArgTabEntry[arg 1 5.LCL_VAR int, 1 reg: rdx, align=1, lateArgInx=1, processed]
fgArgTabEntry[arg 2 6.LCL_VAR int, 1 reg: r8, align=1, lateArgInx=2, processed]
fgArgTabEntry[arg 0 9.CNS_INT long, 1 reg: rcx, align=1, lateArgInx=3, processed]
optValnumCSE morphed tree:
N011 ( 26, 26) [000015] -ACXG---R--- * ASG int $148
N010 ( 3, 2) [000014] D------N---- +--* LCL_VAR int V03 loc0 d:2 $148
N009 ( 22, 23) [000008] --CXG------- \--* CALL int Test2.DoTestImpl2 $148
N005 ( 3, 2) [000192] ------------ arg3 in r9 +--* LCL_VAR int V19 cse0 $180
N006 ( 1, 1) [000005] ------------ arg1 in rdx +--* LCL_VAR int V00 arg0 u:1 $80
N007 ( 1, 1) [000006] ------------ arg2 in r8 +--* LCL_VAR int V01 arg1 u:1 $81
N008 ( 3, 10) [000009] ------------ arg0 in rcx \--* CNS_INT(h) long 0xd1ffab1e method $240
Working on the replacement of the CSE #01 use at [000169] in BB01
ReMorphing args for 24.CALL:
argSlots=4, preallocatedArgCount=4, nextSlotNum=4, outgoingArgSpaceSize=32
ArgTable for 24.CALL after fgMorphArgs:
fgArgTabEntry[arg 3 193.LCL_VAR ubyte, 1 reg: r9, align=1, lateArgInx=0, processed]
fgArgTabEntry[arg 0 20.LCL_FLD byte, 1 reg: rcx, align=1, lateArgInx=1, processed, isStruct]
fgArgTabEntry[arg 1 21.LCL_VAR int, 1 reg: rdx, align=1, lateArgInx=2, processed]
fgArgTabEntry[arg 2 22.LCL_VAR int, 1 reg: r8, align=1, lateArgInx=3, processed]
optValnumCSE morphed tree:
N011 ( 27, 21) [000029] -ACXG---R--- * ASG int $14d
N010 ( 3, 2) [000028] D------N---- +--* LCL_VAR int V04 loc1 d:2 $14d
N009 ( 23, 18) [000024] --CXG------- \--* CALL int Test2.DoTestImpl3 $14d
N005 ( 3, 2) [000193] ------------ arg3 in r9 +--* LCL_VAR int V19 cse0 $180
N006 ( 4, 5) [000020] ------------ arg0 in rcx +--* LCL_FLD byte V08 loc5 u:2[+0] (last use) $301
N007 ( 1, 1) [000021] ------------ arg1 in rdx +--* LCL_VAR int V00 arg0 u:1 $80
N008 ( 1, 1) [000022] ------------ arg2 in r8 \--* LCL_VAR int V01 arg1 u:1 $81
Working on the replacement of the CSE #01 use at [000175] in BB01
ReMorphing args for 40.CALL:
argSlots=5, preallocatedArgCount=5, nextSlotNum=5, outgoingArgSpaceSize=40
ArgTable for 40.CALL after fgMorphArgs:
fgArgTabEntry[arg 4 194.LCL_VAR ubyte, numSlots=1, slotNum=4, align=1, processed]
fgArgTabEntry[arg 1 36.LCL_VAR ref, 1 reg: rdx, align=1, lateArgInx=0, processed]
fgArgTabEntry[arg 2 37.LCL_VAR int, 1 reg: r8, align=1, lateArgInx=1, processed]
fgArgTabEntry[arg 3 38.LCL_VAR int, 1 reg: r9, align=1, lateArgInx=2, processed]
fgArgTabEntry[arg 0 41.CNS_INT long, 1 reg: rcx, align=1, lateArgInx=3, processed]
optValnumCSE morphed tree:
N012 ( 30, 27) [000044] -ACXG---R--- * ASG int $151
N011 ( 3, 2) [000043] D------N---- +--* LCL_VAR int V05 loc2 d:2 $151
N010 ( 26, 24) [000040] --CXG------- \--* CALL int Test2.DoTestImpl4 $151
N005 ( 3, 2) [000194] ------------ arg4 out+20 +--* LCL_VAR int V19 cse0 $180
N006 ( 1, 1) [000036] ------------ arg1 in rdx +--* LCL_VAR ref V11 tmp2 u:2 (last use) $340
N007 ( 1, 1) [000037] ------------ arg2 in r8 +--* LCL_VAR int V00 arg0 u:1 $80
N008 ( 1, 1) [000038] ------------ arg3 in r9 +--* LCL_VAR int V01 arg1 u:1 $81
N009 ( 3, 10) [000041] ------------ arg0 in rcx \--* CNS_INT(h) long 0xd1ffab1e method $242
Working on the replacement of the CSE #01 use at [000180] in BB01
ReMorphing args for 48.CALL:
argSlots=3, preallocatedArgCount=4, nextSlotNum=4, outgoingArgSpaceSize=32
ArgTable for 48.CALL after fgMorphArgs:
fgArgTabEntry[arg 2 195.LCL_VAR ubyte, 1 reg: r8, align=1, lateArgInx=0, processed]
fgArgTabEntry[arg 0 45.LCL_VAR int, 1 reg: rcx, align=1, lateArgInx=1, processed]
fgArgTabEntry[arg 1 46.LCL_VAR int, 1 reg: rdx, align=1, lateArgInx=2, processed]
optValnumCSE morphed tree:
N009 ( 23, 15) [000051] -ACXG---R--- * ASG int $156
N008 ( 3, 2) [000050] D------N---- +--* LCL_VAR int V06 loc3 d:2 $156
N007 ( 19, 12) [000048] --CXG------- \--* CALL int Test2.DoTestImpl5 $156
N004 ( 3, 2) [000195] ------------ arg2 in r8 +--* LCL_VAR int V19 cse0 $180
N005 ( 1, 1) [000045] ------------ arg0 in rcx +--* LCL_VAR int V00 arg0 u:1 $80
N006 ( 1, 1) [000046] ------------ arg1 in rdx \--* LCL_VAR int V01 arg1 u:1 $81
Working on the replacement of the CSE #01 use at [000186] in BB01
optValnumCSE morphed tree:
N005 ( 8, 6) [000120] -A------R--- * ASG int $182
N004 ( 1, 1) [000119] D------N---- +--* LCL_VAR int V14 tmp5 d:2 $182
N003 ( 8, 6) [000145] ------------ \--* MUL int $182
N001 ( 1, 1) [000115] ------------ +--* LCL_VAR int V13 tmp4 u:2 (last use) $181
N002 ( 3, 2) [000196] ------------ \--* LCL_VAR int V19 cse0 $180
Working on the replacement of the CSE #01 use at [000187] in BB01
optValnumCSE morphed tree:
N005 ( 8, 6) [000131] -A------R--- * ASG int $183
N004 ( 1, 1) [000130] D------N---- +--* LCL_VAR int V15 tmp6 d:2 $183
N003 ( 8, 6) [000150] ------------ \--* MUL int $183
N001 ( 1, 1) [000121] ------------ +--* LCL_VAR int V00 arg0 u:1 (last use) $80
N002 ( 3, 2) [000197] ------------ \--* LCL_VAR int V19 cse0 $180
*************** In optAssertionPropMain()
Blocks/Trees at start of phase
-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..051) (return) i label target gcsafe newobj
-----------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [000..051) (return), preds={} succs={}
***** BB01
STMT00002 (IL ???... ???)
N014 ( 26, 19) [000011] -ACXG---R--- * ASG int $143
N013 ( 1, 1) [000010] D------N---- +--* LCL_VAR int V10 tmp1 d:2 $143
N012 ( 26, 19) [000003] -ACXG------- \--* CALL int Test2.DoTestImpl1 $143
N009 ( 10, 9) [000191] -A---------- arg2 in r8 +--* COMMA int $180
N007 ( 7, 7) [000189] -A------R--- | +--* ASG int $VN.Void
N006 ( 3, 2) [000188] D------N---- | | +--* LCL_VAR int V19 cse0 $180
N005 ( 3, 4) [000158] ------------ | | \--* CAST int <- ubyte <- int $180
N004 ( 2, 2) [000002] ------------ | | \--* LCL_VAR int V02 arg2 u:1 $c0
N008 ( 3, 2) [000190] ------------ | \--* LCL_VAR int V19 cse0 $180
N010 ( 1, 1) [000000] ------------ arg0 in rcx +--* LCL_VAR int V00 arg0 u:1 $80
N011 ( 1, 1) [000001] ------------ arg1 in rdx \--* LCL_VAR int V01 arg1 u:1 $81
***** BB01
STMT00003 (IL ???... ???)
N011 ( 26, 26) [000015] -ACXG---R--- * ASG int $148
N010 ( 3, 2) [000014] D------N---- +--* LCL_VAR int V03 loc0 d:2 $148
N009 ( 22, 23) [000008] --CXG------- \--* CALL int Test2.DoTestImpl2 $148
N005 ( 3, 2) [000192] ------------ arg3 in r9 +--* LCL_VAR int V19 cse0 $180
N006 ( 1, 1) [000005] ------------ arg1 in rdx +--* LCL_VAR int V00 arg0 u:1 $80
N007 ( 1, 1) [000006] ------------ arg2 in r8 +--* LCL_VAR int V01 arg1 u:1 $81
N008 ( 3, 10) [000009] ------------ arg0 in rcx \--* CNS_INT(h) long 0xd1ffab1e method $240
***** BB01
STMT00004 (IL ???...0x014)
N005 ( 9, 8) [000019] -A------R--- * ASG byte $VN.Void
N004 ( 7, 6) [000168] n------N---- +--* IND byte $40
N003 ( 3, 3) [000167] ------------ | \--* ADDR byref $2c0
N002 ( 3, 2) [000016] D------N---- | \--* LCL_VAR struct V08 loc5 d:2
N001 ( 1, 1) [000018] ------------ \--* CNS_INT int 0 $40
***** BB01
STMT00006 (IL ???... ???)
N011 ( 27, 21) [000029] -ACXG---R--- * ASG int $14d
N010 ( 3, 2) [000028] D------N---- +--* LCL_VAR int V04 loc1 d:2 $14d
N009 ( 23, 18) [000024] --CXG------- \--* CALL int Test2.DoTestImpl3 $14d
N005 ( 3, 2) [000193] ------------ arg3 in r9 +--* LCL_VAR int V19 cse0 $180
N006 ( 4, 5) [000020] ------------ arg0 in rcx +--* LCL_FLD byte V08 loc5 u:2[+0] (last use) $301
N007 ( 1, 1) [000021] ------------ arg1 in rdx +--* LCL_VAR int V00 arg0 u:1 $80
N008 ( 1, 1) [000022] ------------ arg2 in r8 \--* LCL_VAR int V01 arg1 u:1 $81
***** BB01
STMT00007 (IL ???...0x031)
N005 ( 17, 16) [000033] -AC-----R--- * ASG ref $340
N004 ( 1, 1) [000032] D------N---- +--* LCL_VAR ref V11 tmp2 d:2 $340
N003 ( 17, 16) [000031] --C--------- \--* CALL help ref HELPER.CORINFO_HELP_NEWSFAST $340
N002 ( 3, 10) [000030] ------------ arg0 in rcx \--* CNS_INT(h) long 0xd1ffab1e method $241
***** BB01
STMT00010 (IL ???... ???)
N012 ( 30, 27) [000044] -ACXG---R--- * ASG int $151
N011 ( 3, 2) [000043] D------N---- +--* LCL_VAR int V05 loc2 d:2 $151
N010 ( 26, 24) [000040] --CXG------- \--* CALL int Test2.DoTestImpl4 $151
N005 ( 3, 2) [000194] ------------ arg4 out+20 +--* LCL_VAR int V19 cse0 $180
N006 ( 1, 1) [000036] ------------ arg1 in rdx +--* LCL_VAR ref V11 tmp2 u:2 (last use) $340
N007 ( 1, 1) [000037] ------------ arg2 in r8 +--* LCL_VAR int V00 arg0 u:1 $80
N008 ( 1, 1) [000038] ------------ arg3 in r9 +--* LCL_VAR int V01 arg1 u:1 $81
N009 ( 3, 10) [000041] ------------ arg0 in rcx \--* CNS_INT(h) long 0xd1ffab1e method $242
***** BB01
STMT00012 (IL ???... ???)
N009 ( 23, 15) [000051] -ACXG---R--- * ASG int $156
N008 ( 3, 2) [000050] D------N---- +--* LCL_VAR int V06 loc3 d:2 $156
N007 ( 19, 12) [000048] --CXG------- \--* CALL int Test2.DoTestImpl5 $156
N004 ( 3, 2) [000195] ------------ arg2 in r8 +--* LCL_VAR int V19 cse0 $180
N005 ( 1, 1) [000045] ------------ arg0 in rcx +--* LCL_VAR int V00 arg0 u:1 $80
N006 ( 1, 1) [000046] ------------ arg1 in rdx \--* LCL_VAR int V01 arg1 u:1 $81
***** BB01
STMT00027 (IL ???... ???)
N005 ( 3, 3) [000114] -A------R--- * ASG int $181
N004 ( 1, 1) [000113] D------N---- +--* LCL_VAR int V13 tmp4 d:2 $181
N003 ( 3, 3) [000140] ------------ \--* ADD int $181
N001 ( 1, 1) [000052] ------------ +--* LCL_VAR int V00 arg0 u:1 $80
N002 ( 1, 1) [000053] ------------ \--* LCL_VAR int V01 arg1 u:1 (last use) $81
***** BB01
STMT00029 (IL ???... ???)
N005 ( 8, 6) [000120] -A------R--- * ASG int $182
N004 ( 1, 1) [000119] D------N---- +--* LCL_VAR int V14 tmp5 d:2 $182
N003 ( 8, 6) [000145] ------------ \--* MUL int $182
N001 ( 1, 1) [000115] ------------ +--* LCL_VAR int V13 tmp4 u:2 (last use) $181
N002 ( 3, 2) [000196] ------------ \--* LCL_VAR int V19 cse0 $180
***** BB01
STMT00033 (IL ???... ???)
N005 ( 8, 6) [000131] -A------R--- * ASG int $183
N004 ( 1, 1) [000130] D------N---- +--* LCL_VAR int V15 tmp6 d:2 $183
N003 ( 8, 6) [000150] ------------ \--* MUL int $183
N001 ( 1, 1) [000121] ------------ +--* LCL_VAR int V00 arg0 u:1 (last use) $80
N002 ( 3, 2) [000197] ------------ \--* LCL_VAR int V19 cse0 $180
***** BB01
STMT00014 (IL ???... ???)
N007 ( 28, 10) [000058] -A-X----R--- * ASG int $186
N006 ( 3, 2) [000057] D------N---- +--* LCL_VAR int V07 loc4 d:2 $185
N005 ( 24, 7) [000156] ---X-------- \--* DIV int $186
N001 ( 1, 1) [000132] ------------ +--* LCL_VAR int V15 tmp6 u:2 (last use) $183
N004 ( 3, 3) [000153] ------------ \--* RSH int $184
N002 ( 1, 1) [000127] ------------ +--* LCL_VAR int V14 tmp5 u:2 (last use) $182
N003 ( 1, 1) [000152] ------------ \--* CNS_INT int 2 $42
***** BB01
STMT00015 (IL ???...0x050)
N012 ( 22, 17) [000069] ------------ * RETURN int $15c
N011 ( 21, 16) [000068] ------------ \--* ADD int $18b
N009 ( 17, 13) [000066] ------------ +--* ADD int $18a
N007 ( 13, 10) [000064] ------------ | +--* ADD int $189
N005 ( 9, 7) [000062] ------------ | | +--* ADD int $188
N003 ( 5, 4) [000060] ------------ | | | +--* ADD int $187
N001 ( 1, 1) [000012] ------------ | | | | +--* LCL_VAR int V10 tmp1 u:2 (last use) $143
N002 ( 3, 2) [000059] ------------ | | | | \--* LCL_VAR int V03 loc0 u:2 (last use) $148
N004 ( 3, 2) [000061] ------------ | | | \--* LCL_VAR int V04 loc1 u:2 (last use) $14d
N006 ( 3, 2) [000063] ------------ | | \--* LCL_VAR int V05 loc2 u:2 (last use) $151
N008 ( 3, 2) [000065] ------------ | \--* LCL_VAR int V06 loc3 u:2 (last use) $156
N010 ( 3, 2) [000067] ------------ \--* LCL_VAR int V07 loc4 u:2 (last use) $185
-------------------------------------------------------------------------------------------------------------------
GenTreeNode creates assertion:
N005 ( 3, 4) [000158] ------------ * CAST int <- ubyte <- int $180
In BB01 New Global Subrange Assertion: (192, 0) ($c0,$0) V02.01 in [0..255] index=#01, mask=0000000000000001
BB01 valueGen = 0000000000000000AssertionPropCallback::StartMerge: BB01 in -> 0000000000000000
AssertionPropCallback::EndMerge : BB01 in -> 0000000000000000
AssertionPropCallback::Changed : BB01 before out -> 0000000000000001; after out -> 0000000000000000;
jumpDest before out -> 0000000000000001; jumpDest after out -> 0000000000000000;
BB01 valueIn = 0000000000000000 valueOut = 0000000000000000
Propagating 0000000000000000 assertions for BB01, stmt STMT00002, tree [000160], tree -> 0
Propagating 0000000000000000 assertions for BB01, stmt STMT00002, tree [000161], tree -> 0
Propagating 0000000000000000 assertions for BB01, stmt STMT00002, tree [000159], tree -> 0
Propagating 0000000000000000 assertions for BB01, stmt STMT00002, tree [000002], tree -> 0
Propagating 0000000000000000 assertions for BB01, stmt STMT00002, tree [000158], tree -> 0
Propagating 0000000000000000 assertions for BB01, stmt STMT00002, tree [000188], tree -> 0
Propagating 0000000000000000 assertions for BB01, stmt STMT00002, tree [000189], tree -> 0
Propagating 0000000000000000 assertions for BB01, stmt STMT00002, tree [000190], tree -> 0
Propagating 0000000000000000 assertions for BB01, stmt STMT00002, tree [000191], tree -> 0
Propagating 0000000000000000 assertions for BB01, stmt STMT00002, tree [000000], tree -> 0
Propagating 0000000000000000 assertions for BB01, stmt STMT00002, tree [000001], tree -> 0
Propagating 0000000000000000 assertions for BB01, stmt STMT00002, tree [000003], tree -> 0
Propagating 0000000000000000 assertions for BB01, stmt STMT00002, tree [000010], tree -> 0
Propagating 0000000000000000 assertions for BB01, stmt STMT00002, tree [000011], tree -> 0
Propagating 0000000000000000 assertions for BB01, stmt STMT00003, tree [000166], tree -> 0
Propagating 0000000000000000 assertions for BB01, stmt STMT00003, tree [000164], tree -> 0
Propagating 0000000000000000 assertions for BB01, stmt STMT00003, tree [000165], tree -> 0
Propagating 0000000000000000 assertions for BB01, stmt STMT00003, tree [000163], tree -> 0
Propagating 0000000000000000 assertions for BB01, stmt STMT00003, tree [000192], tree -> 0
Propagating 0000000000000000 assertions for BB01, stmt STMT00003, tree [000005], tree -> 0
Propagating 0000000000000000 assertions for BB01, stmt STMT00003, tree [000006], tree -> 0
Propagating 0000000000000000 assertions for BB01, stmt STMT00003, tree [000009], tree -> 0
Propagating 0000000000000000 assertions for BB01, stmt STMT00003, tree [000008], tree -> 0
Propagating 0000000000000000 assertions for BB01, stmt STMT00003, tree [000014], tree -> 0
Propagating 0000000000000000 assertions for BB01, stmt STMT00003, tree [000015], tree -> 0
Propagating 0000000000000000 assertions for BB01, stmt STMT00004, tree [000018], tree -> 0
Propagating 0000000000000000 assertions for BB01, stmt STMT00004, tree [000016], tree -> 0
Propagating 0000000000000000 assertions for BB01, stmt STMT00004, tree [000167], tree -> 0
Propagating 0000000000000000 assertions for BB01, stmt STMT00004, tree [000168], tree -> 0
Propagating 0000000000000000 assertions for BB01, stmt STMT00004, tree [000019], tree -> 0
Propagating 0000000000000000 assertions for BB01, stmt STMT00006, tree [000171], tree -> 0
Propagating 0000000000000000 assertions for BB01, stmt STMT00006, tree [000172], tree -> 0
Propagating 0000000000000000 assertions for BB01, stmt STMT00006, tree [000173], tree -> 0
Propagating 0000000000000000 assertions for BB01, stmt STMT00006, tree [000170], tree -> 0
Propagating 0000000000000000 assertions for BB01, stmt STMT00006, tree [000193], tree -> 0
Propagating 0000000000000000 assertions for BB01, stmt STMT00006, tree [000020], tree -> 0
Propagating 0000000000000000 assertions for BB01, stmt STMT00006, tree [000021], tree -> 0
Propagating 0000000000000000 assertions for BB01, stmt STMT00006, tree [000022], tree -> 0
Propagating 0000000000000000 assertions for BB01, stmt STMT00006, tree [000024], tree -> 0
Propagating 0000000000000000 assertions for BB01, stmt STMT00006, tree [000028], tree -> 0
Propagating 0000000000000000 assertions for BB01, stmt STMT00006, tree [000029], tree -> 0
Propagating 0000000000000000 assertions for BB01, stmt STMT00007, tree [000174], tree -> 0
Propagating 0000000000000000 assertions for BB01, stmt STMT00007, tree [000030], tree -> 0
Propagating 0000000000000000 assertions for BB01, stmt STMT00007, tree [000031], tree -> 0
Propagating 0000000000000000 assertions for BB01, stmt STMT00007, tree [000032], tree -> 0
Propagating 0000000000000000 assertions for BB01, stmt STMT00007, tree [000033], tree -> 0
Propagating 0000000000000000 assertions for BB01, stmt STMT00010, tree [000179], tree -> 0
Propagating 0000000000000000 assertions for BB01, stmt STMT00010, tree [000176], tree -> 0
Propagating 0000000000000000 assertions for BB01, stmt STMT00010, tree [000177], tree -> 0
Propagating 0000000000000000 assertions for BB01, stmt STMT00010, tree [000178], tree -> 0
Propagating 0000000000000000 assertions for BB01, stmt STMT00010, tree [000194], tree -> 0
Propagating 0000000000000000 assertions for BB01, stmt STMT00010, tree [000036], tree -> 0
Propagating 0000000000000000 assertions for BB01, stmt STMT00010, tree [000037], tree -> 0
Propagating 0000000000000000 assertions for BB01, stmt STMT00010, tree [000038], tree -> 0
Propagating 0000000000000000 assertions for BB01, stmt STMT00010, tree [000041], tree -> 0
Propagating 0000000000000000 assertions for BB01, stmt STMT00010, tree [000040], tree -> 0
Propagating 0000000000000000 assertions for BB01, stmt STMT00010, tree [000043], tree -> 0
Propagating 0000000000000000 assertions for BB01, stmt STMT00010, tree [000044], tree -> 0
Propagating 0000000000000000 assertions for BB01, stmt STMT00012, tree [000182], tree -> 0
Propagating 0000000000000000 assertions for BB01, stmt STMT00012, tree [000183], tree -> 0
Propagating 0000000000000000 assertions for BB01, stmt STMT00012, tree [000181], tree -> 0
Propagating 0000000000000000 assertions for BB01, stmt STMT00012, tree [000195], tree -> 0
Propagating 0000000000000000 assertions for BB01, stmt STMT00012, tree [000045], tree -> 0
Propagating 0000000000000000 assertions for BB01, stmt STMT00012, tree [000046], tree -> 0
Propagating 0000000000000000 assertions for BB01, stmt STMT00012, tree [000048], tree -> 0
Propagating 0000000000000000 assertions for BB01, stmt STMT00012, tree [000050], tree -> 0
Propagating 0000000000000000 assertions for BB01, stmt STMT00012, tree [000051], tree -> 0
Propagating 0000000000000000 assertions for BB01, stmt STMT00027, tree [000052], tree -> 0
Propagating 0000000000000000 assertions for BB01, stmt STMT00027, tree [000053], tree -> 0
Propagating 0000000000000000 assertions for BB01, stmt STMT00027, tree [000140], tree -> 0
Propagating 0000000000000000 assertions for BB01, stmt STMT00027, tree [000113], tree -> 0
Propagating 0000000000000000 assertions for BB01, stmt STMT00027, tree [000114], tree -> 0
Propagating 0000000000000000 assertions for BB01, stmt STMT00029, tree [000115], tree -> 0
Propagating 0000000000000000 assertions for BB01, stmt STMT00029, tree [000196], tree -> 0
Propagating 0000000000000000 assertions for BB01, stmt STMT00029, tree [000145], tree -> 0
Propagating 0000000000000000 assertions for BB01, stmt STMT00029, tree [000119], tree -> 0
Propagating 0000000000000000 assertions for BB01, stmt STMT00029, tree [000120], tree -> 0
Propagating 0000000000000000 assertions for BB01, stmt STMT00033, tree [000121], tree -> 0
Propagating 0000000000000000 assertions for BB01, stmt STMT00033, tree [000197], tree -> 0
Propagating 0000000000000000 assertions for BB01, stmt STMT00033, tree [000150], tree -> 0
Propagating 0000000000000000 assertions for BB01, stmt STMT00033, tree [000130], tree -> 0
Propagating 0000000000000000 assertions for BB01, stmt STMT00033, tree [000131], tree -> 0
Propagating 0000000000000000 assertions for BB01, stmt STMT00014, tree [000132], tree -> 0
Propagating 0000000000000000 assertions for BB01, stmt STMT00014, tree [000127], tree -> 0
Propagating 0000000000000000 assertions for BB01, stmt STMT00014, tree [000152], tree -> 0
Propagating 0000000000000000 assertions for BB01, stmt STMT00014, tree [000153], tree -> 0
Propagating 0000000000000000 assertions for BB01, stmt STMT00014, tree [000156], tree -> 0
Propagating 0000000000000000 assertions for BB01, stmt STMT00014, tree [000057], tree -> 0
Propagating 0000000000000000 assertions for BB01, stmt STMT00014, tree [000058], tree -> 0
Propagating 0000000000000000 assertions for BB01, stmt STMT00015, tree [000012], tree -> 0
Propagating 0000000000000000 assertions for BB01, stmt STMT00015, tree [000059], tree -> 0
Propagating 0000000000000000 assertions for BB01, stmt STMT00015, tree [000060], tree -> 0
Propagating 0000000000000000 assertions for BB01, stmt STMT00015, tree [000061], tree -> 0
Propagating 0000000000000000 assertions for BB01, stmt STMT00015, tree [000062], tree -> 0
Propagating 0000000000000000 assertions for BB01, stmt STMT00015, tree [000063], tree -> 0
Propagating 0000000000000000 assertions for BB01, stmt STMT00015, tree [000064], tree -> 0
Propagating 0000000000000000 assertions for BB01, stmt STMT00015, tree [000065], tree -> 0
Propagating 0000000000000000 assertions for BB01, stmt STMT00015, tree [000066], tree -> 0
Propagating 0000000000000000 assertions for BB01, stmt STMT00015, tree [000067], tree -> 0
Propagating 0000000000000000 assertions for BB01, stmt STMT00015, tree [000068], tree -> 0
Propagating 0000000000000000 assertions for BB01, stmt STMT00015, tree [000069], tree -> 0
*************** In fgDebugCheckBBlist
*************** In OptimizeRangeChecks()
Blocks/trees before phase
-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..051) (return) i label target gcsafe newobj
-----------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [000..051) (return), preds={} succs={}
***** BB01
STMT00002 (IL ???... ???)
N014 ( 26, 19) [000011] -ACXG---R--- * ASG int $143
N013 ( 1, 1) [000010] D------N---- +--* LCL_VAR int V10 tmp1 d:2 $143
N012 ( 26, 19) [000003] -ACXG------- \--* CALL int Test2.DoTestImpl1 $143
N009 ( 10, 9) [000191] -A---------- arg2 in r8 +--* COMMA int $180
N007 ( 7, 7) [000189] -A------R--- | +--* ASG int $VN.Void
N006 ( 3, 2) [000188] D------N---- | | +--* LCL_VAR int V19 cse0 $180
N005 ( 3, 4) [000158] ------------ | | \--* CAST int <- ubyte <- int $180
N004 ( 2, 2) [000002] ------------ | | \--* LCL_VAR int V02 arg2 u:1 $c0
N008 ( 3, 2) [000190] ------------ | \--* LCL_VAR int V19 cse0 $180
N010 ( 1, 1) [000000] ------------ arg0 in rcx +--* LCL_VAR int V00 arg0 u:1 $80
N011 ( 1, 1) [000001] ------------ arg1 in rdx \--* LCL_VAR int V01 arg1 u:1 $81
***** BB01
STMT00003 (IL ???... ???)
N011 ( 26, 26) [000015] -ACXG---R--- * ASG int $148
N010 ( 3, 2) [000014] D------N---- +--* LCL_VAR int V03 loc0 d:2 $148
N009 ( 22, 23) [000008] --CXG------- \--* CALL int Test2.DoTestImpl2 $148
N005 ( 3, 2) [000192] ------------ arg3 in r9 +--* LCL_VAR int V19 cse0 $180
N006 ( 1, 1) [000005] ------------ arg1 in rdx +--* LCL_VAR int V00 arg0 u:1 $80
N007 ( 1, 1) [000006] ------------ arg2 in r8 +--* LCL_VAR int V01 arg1 u:1 $81
N008 ( 3, 10) [000009] ------------ arg0 in rcx \--* CNS_INT(h) long 0xd1ffab1e method $240
***** BB01
STMT00004 (IL ???...0x014)
N005 ( 9, 8) [000019] -A------R--- * ASG byte $VN.Void
N004 ( 7, 6) [000168] n------N---- +--* IND byte $40
N003 ( 3, 3) [000167] ------------ | \--* ADDR byref $2c0
N002 ( 3, 2) [000016] D------N---- | \--* LCL_VAR struct V08 loc5 d:2
N001 ( 1, 1) [000018] ------------ \--* CNS_INT int 0 $40
***** BB01
STMT00006 (IL ???... ???)
N011 ( 27, 21) [000029] -ACXG---R--- * ASG int $14d
N010 ( 3, 2) [000028] D------N---- +--* LCL_VAR int V04 loc1 d:2 $14d
N009 ( 23, 18) [000024] --CXG------- \--* CALL int Test2.DoTestImpl3 $14d
N005 ( 3, 2) [000193] ------------ arg3 in r9 +--* LCL_VAR int V19 cse0 $180
N006 ( 4, 5) [000020] ------------ arg0 in rcx +--* LCL_FLD byte V08 loc5 u:2[+0] (last use) $301
N007 ( 1, 1) [000021] ------------ arg1 in rdx +--* LCL_VAR int V00 arg0 u:1 $80
N008 ( 1, 1) [000022] ------------ arg2 in r8 \--* LCL_VAR int V01 arg1 u:1 $81
***** BB01
STMT00007 (IL ???...0x031)
N005 ( 17, 16) [000033] -AC-----R--- * ASG ref $340
N004 ( 1, 1) [000032] D------N---- +--* LCL_VAR ref V11 tmp2 d:2 $340
N003 ( 17, 16) [000031] --C--------- \--* CALL help ref HELPER.CORINFO_HELP_NEWSFAST $340
N002 ( 3, 10) [000030] ------------ arg0 in rcx \--* CNS_INT(h) long 0xd1ffab1e method $241
***** BB01
STMT00010 (IL ???... ???)
N012 ( 30, 27) [000044] -ACXG---R--- * ASG int $151
N011 ( 3, 2) [000043] D------N---- +--* LCL_VAR int V05 loc2 d:2 $151
N010 ( 26, 24) [000040] --CXG------- \--* CALL int Test2.DoTestImpl4 $151
N005 ( 3, 2) [000194] ------------ arg4 out+20 +--* LCL_VAR int V19 cse0 $180
N006 ( 1, 1) [000036] ------------ arg1 in rdx +--* LCL_VAR ref V11 tmp2 u:2 (last use) $340
N007 ( 1, 1) [000037] ------------ arg2 in r8 +--* LCL_VAR int V00 arg0 u:1 $80
N008 ( 1, 1) [000038] ------------ arg3 in r9 +--* LCL_VAR int V01 arg1 u:1 $81
N009 ( 3, 10) [000041] ------------ arg0 in rcx \--* CNS_INT(h) long 0xd1ffab1e method $242
***** BB01
STMT00012 (IL ???... ???)
N009 ( 23, 15) [000051] -ACXG---R--- * ASG int $156
N008 ( 3, 2) [000050] D------N---- +--* LCL_VAR int V06 loc3 d:2 $156
N007 ( 19, 12) [000048] --CXG------- \--* CALL int Test2.DoTestImpl5 $156
N004 ( 3, 2) [000195] ------------ arg2 in r8 +--* LCL_VAR int V19 cse0 $180
N005 ( 1, 1) [000045] ------------ arg0 in rcx +--* LCL_VAR int V00 arg0 u:1 $80
N006 ( 1, 1) [000046] ------------ arg1 in rdx \--* LCL_VAR int V01 arg1 u:1 $81
***** BB01
STMT00027 (IL ???... ???)
N005 ( 3, 3) [000114] -A------R--- * ASG int $181
N004 ( 1, 1) [000113] D------N---- +--* LCL_VAR int V13 tmp4 d:2 $181
N003 ( 3, 3) [000140] ------------ \--* ADD int $181
N001 ( 1, 1) [000052] ------------ +--* LCL_VAR int V00 arg0 u:1 $80
N002 ( 1, 1) [000053] ------------ \--* LCL_VAR int V01 arg1 u:1 (last use) $81
***** BB01
STMT00029 (IL ???... ???)
N005 ( 8, 6) [000120] -A------R--- * ASG int $182
N004 ( 1, 1) [000119] D------N---- +--* LCL_VAR int V14 tmp5 d:2 $182
N003 ( 8, 6) [000145] ------------ \--* MUL int $182
N001 ( 1, 1) [000115] ------------ +--* LCL_VAR int V13 tmp4 u:2 (last use) $181
N002 ( 3, 2) [000196] ------------ \--* LCL_VAR int V19 cse0 $180
***** BB01
STMT00033 (IL ???... ???)
N005 ( 8, 6) [000131] -A------R--- * ASG int $183
N004 ( 1, 1) [000130] D------N---- +--* LCL_VAR int V15 tmp6 d:2 $183
N003 ( 8, 6) [000150] ------------ \--* MUL int $183
N001 ( 1, 1) [000121] ------------ +--* LCL_VAR int V00 arg0 u:1 (last use) $80
N002 ( 3, 2) [000197] ------------ \--* LCL_VAR int V19 cse0 $180
***** BB01
STMT00014 (IL ???... ???)
N007 ( 28, 10) [000058] -A-X----R--- * ASG int $186
N006 ( 3, 2) [000057] D------N---- +--* LCL_VAR int V07 loc4 d:2 $185
N005 ( 24, 7) [000156] ---X-------- \--* DIV int $186
N001 ( 1, 1) [000132] ------------ +--* LCL_VAR int V15 tmp6 u:2 (last use) $183
N004 ( 3, 3) [000153] ------------ \--* RSH int $184
N002 ( 1, 1) [000127] ------------ +--* LCL_VAR int V14 tmp5 u:2 (last use) $182
N003 ( 1, 1) [000152] ------------ \--* CNS_INT int 2 $42
***** BB01
STMT00015 (IL ???...0x050)
N012 ( 22, 17) [000069] ------------ * RETURN int $15c
N011 ( 21, 16) [000068] ------------ \--* ADD int $18b
N009 ( 17, 13) [000066] ------------ +--* ADD int $18a
N007 ( 13, 10) [000064] ------------ | +--* ADD int $189
N005 ( 9, 7) [000062] ------------ | | +--* ADD int $188
N003 ( 5, 4) [000060] ------------ | | | +--* ADD int $187
N001 ( 1, 1) [000012] ------------ | | | | +--* LCL_VAR int V10 tmp1 u:2 (last use) $143
N002 ( 3, 2) [000059] ------------ | | | | \--* LCL_VAR int V03 loc0 u:2 (last use) $148
N004 ( 3, 2) [000061] ------------ | | | \--* LCL_VAR int V04 loc1 u:2 (last use) $14d
N006 ( 3, 2) [000063] ------------ | | \--* LCL_VAR int V05 loc2 u:2 (last use) $151
N008 ( 3, 2) [000065] ------------ | \--* LCL_VAR int V06 loc3 u:2 (last use) $156
N010 ( 3, 2) [000067] ------------ \--* LCL_VAR int V07 loc4 u:2 (last use) $185
-------------------------------------------------------------------------------------------------------------------
*************** In fgDetermineFirstColdBlock()
No procedure splitting will be done for this method
*************** In IR Rationalize
Trees before IR Rationalize
-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..051) (return) i label target gcsafe newobj
-----------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [000..051) (return), preds={} succs={}
***** BB01
STMT00002 (IL ???... ???)
N014 ( 26, 19) [000011] -ACXG---R--- * ASG int $143
N013 ( 1, 1) [000010] D------N---- +--* LCL_VAR int V10 tmp1 d:2 $143
N012 ( 26, 19) [000003] -ACXG------- \--* CALL int Test2.DoTestImpl1 $143
N009 ( 10, 9) [000191] -A---------- arg2 in r8 +--* COMMA int $180
N007 ( 7, 7) [000189] -A------R--- | +--* ASG int $VN.Void
N006 ( 3, 2) [000188] D------N---- | | +--* LCL_VAR int V19 cse0 $180
N005 ( 3, 4) [000158] ------------ | | \--* CAST int <- ubyte <- int $180
N004 ( 2, 2) [000002] ------------ | | \--* LCL_VAR int V02 arg2 u:1 $c0
N008 ( 3, 2) [000190] ------------ | \--* LCL_VAR int V19 cse0 $180
N010 ( 1, 1) [000000] ------------ arg0 in rcx +--* LCL_VAR int V00 arg0 u:1 $80
N011 ( 1, 1) [000001] ------------ arg1 in rdx \--* LCL_VAR int V01 arg1 u:1 $81
***** BB01
STMT00003 (IL ???... ???)
N011 ( 26, 26) [000015] -ACXG---R--- * ASG int $148
N010 ( 3, 2) [000014] D------N---- +--* LCL_VAR int V03 loc0 d:2 $148
N009 ( 22, 23) [000008] --CXG------- \--* CALL int Test2.DoTestImpl2 $148
N005 ( 3, 2) [000192] ------------ arg3 in r9 +--* LCL_VAR int V19 cse0 $180
N006 ( 1, 1) [000005] ------------ arg1 in rdx +--* LCL_VAR int V00 arg0 u:1 $80
N007 ( 1, 1) [000006] ------------ arg2 in r8 +--* LCL_VAR int V01 arg1 u:1 $81
N008 ( 3, 10) [000009] ------------ arg0 in rcx \--* CNS_INT(h) long 0xd1ffab1e method $240
***** BB01
STMT00004 (IL ???...0x014)
N005 ( 9, 8) [000019] -A------R--- * ASG byte $VN.Void
N004 ( 7, 6) [000168] n------N---- +--* IND byte $40
N003 ( 3, 3) [000167] ------------ | \--* ADDR byref $2c0
N002 ( 3, 2) [000016] D------N---- | \--* LCL_VAR struct V08 loc5 d:2
N001 ( 1, 1) [000018] ------------ \--* CNS_INT int 0 $40
***** BB01
STMT00006 (IL ???... ???)
N011 ( 27, 21) [000029] -ACXG---R--- * ASG int $14d
N010 ( 3, 2) [000028] D------N---- +--* LCL_VAR int V04 loc1 d:2 $14d
N009 ( 23, 18) [000024] --CXG------- \--* CALL int Test2.DoTestImpl3 $14d
N005 ( 3, 2) [000193] ------------ arg3 in r9 +--* LCL_VAR int V19 cse0 $180
N006 ( 4, 5) [000020] ------------ arg0 in rcx +--* LCL_FLD byte V08 loc5 u:2[+0] (last use) $301
N007 ( 1, 1) [000021] ------------ arg1 in rdx +--* LCL_VAR int V00 arg0 u:1 $80
N008 ( 1, 1) [000022] ------------ arg2 in r8 \--* LCL_VAR int V01 arg1 u:1 $81
***** BB01
STMT00007 (IL ???...0x031)
N005 ( 17, 16) [000033] -AC-----R--- * ASG ref $340
N004 ( 1, 1) [000032] D------N---- +--* LCL_VAR ref V11 tmp2 d:2 $340
N003 ( 17, 16) [000031] --C--------- \--* CALL help ref HELPER.CORINFO_HELP_NEWSFAST $340
N002 ( 3, 10) [000030] ------------ arg0 in rcx \--* CNS_INT(h) long 0xd1ffab1e method $241
***** BB01
STMT00010 (IL ???... ???)
N012 ( 30, 27) [000044] -ACXG---R--- * ASG int $151
N011 ( 3, 2) [000043] D------N---- +--* LCL_VAR int V05 loc2 d:2 $151
N010 ( 26, 24) [000040] --CXG------- \--* CALL int Test2.DoTestImpl4 $151
N005 ( 3, 2) [000194] ------------ arg4 out+20 +--* LCL_VAR int V19 cse0 $180
N006 ( 1, 1) [000036] ------------ arg1 in rdx +--* LCL_VAR ref V11 tmp2 u:2 (last use) $340
N007 ( 1, 1) [000037] ------------ arg2 in r8 +--* LCL_VAR int V00 arg0 u:1 $80
N008 ( 1, 1) [000038] ------------ arg3 in r9 +--* LCL_VAR int V01 arg1 u:1 $81
N009 ( 3, 10) [000041] ------------ arg0 in rcx \--* CNS_INT(h) long 0xd1ffab1e method $242
***** BB01
STMT00012 (IL ???... ???)
N009 ( 23, 15) [000051] -ACXG---R--- * ASG int $156
N008 ( 3, 2) [000050] D------N---- +--* LCL_VAR int V06 loc3 d:2 $156
N007 ( 19, 12) [000048] --CXG------- \--* CALL int Test2.DoTestImpl5 $156
N004 ( 3, 2) [000195] ------------ arg2 in r8 +--* LCL_VAR int V19 cse0 $180
N005 ( 1, 1) [000045] ------------ arg0 in rcx +--* LCL_VAR int V00 arg0 u:1 $80
N006 ( 1, 1) [000046] ------------ arg1 in rdx \--* LCL_VAR int V01 arg1 u:1 $81
***** BB01
STMT00027 (IL ???... ???)
N005 ( 3, 3) [000114] -A------R--- * ASG int $181
N004 ( 1, 1) [000113] D------N---- +--* LCL_VAR int V13 tmp4 d:2 $181
N003 ( 3, 3) [000140] ------------ \--* ADD int $181
N001 ( 1, 1) [000052] ------------ +--* LCL_VAR int V00 arg0 u:1 $80
N002 ( 1, 1) [000053] ------------ \--* LCL_VAR int V01 arg1 u:1 (last use) $81
***** BB01
STMT00029 (IL ???... ???)
N005 ( 8, 6) [000120] -A------R--- * ASG int $182
N004 ( 1, 1) [000119] D------N---- +--* LCL_VAR int V14 tmp5 d:2 $182
N003 ( 8, 6) [000145] ------------ \--* MUL int $182
N001 ( 1, 1) [000115] ------------ +--* LCL_VAR int V13 tmp4 u:2 (last use) $181
N002 ( 3, 2) [000196] ------------ \--* LCL_VAR int V19 cse0 $180
***** BB01
STMT00033 (IL ???... ???)
N005 ( 8, 6) [000131] -A------R--- * ASG int $183
N004 ( 1, 1) [000130] D------N---- +--* LCL_VAR int V15 tmp6 d:2 $183
N003 ( 8, 6) [000150] ------------ \--* MUL int $183
N001 ( 1, 1) [000121] ------------ +--* LCL_VAR int V00 arg0 u:1 (last use) $80
N002 ( 3, 2) [000197] ------------ \--* LCL_VAR int V19 cse0 $180
***** BB01
STMT00014 (IL ???... ???)
N007 ( 28, 10) [000058] -A-X----R--- * ASG int $186
N006 ( 3, 2) [000057] D------N---- +--* LCL_VAR int V07 loc4 d:2 $185
N005 ( 24, 7) [000156] ---X-------- \--* DIV int $186
N001 ( 1, 1) [000132] ------------ +--* LCL_VAR int V15 tmp6 u:2 (last use) $183
N004 ( 3, 3) [000153] ------------ \--* RSH int $184
N002 ( 1, 1) [000127] ------------ +--* LCL_VAR int V14 tmp5 u:2 (last use) $182
N003 ( 1, 1) [000152] ------------ \--* CNS_INT int 2 $42
***** BB01
STMT00015 (IL ???...0x050)
N012 ( 22, 17) [000069] ------------ * RETURN int $15c
N011 ( 21, 16) [000068] ------------ \--* ADD int $18b
N009 ( 17, 13) [000066] ------------ +--* ADD int $18a
N007 ( 13, 10) [000064] ------------ | +--* ADD int $189
N005 ( 9, 7) [000062] ------------ | | +--* ADD int $188
N003 ( 5, 4) [000060] ------------ | | | +--* ADD int $187
N001 ( 1, 1) [000012] ------------ | | | | +--* LCL_VAR int V10 tmp1 u:2 (last use) $143
N002 ( 3, 2) [000059] ------------ | | | | \--* LCL_VAR int V03 loc0 u:2 (last use) $148
N004 ( 3, 2) [000061] ------------ | | | \--* LCL_VAR int V04 loc1 u:2 (last use) $14d
N006 ( 3, 2) [000063] ------------ | | \--* LCL_VAR int V05 loc2 u:2 (last use) $151
N008 ( 3, 2) [000065] ------------ | \--* LCL_VAR int V06 loc3 u:2 (last use) $156
N010 ( 3, 2) [000067] ------------ \--* LCL_VAR int V07 loc4 u:2 (last use) $185
-------------------------------------------------------------------------------------------------------------------
rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X)
N007 ( 7, 7) [000189] DA---------- * STORE_LCL_VAR int V19 cse0
rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X)
N014 ( 26, 19) [000011] DACXG------- * STORE_LCL_VAR int V10 tmp1 d:2
rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X)
N011 ( 26, 26) [000015] DACXG------- * STORE_LCL_VAR int V03 loc0 d:2
Rewriting GT_ADDR(GT_LCL_VAR) to GT_LCL_VAR_ADDR:
N002 ( 3, 2) [000016] D------N---- t16 = LCL_VAR_ADDR byref V08 loc5 d:2
rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X)
N011 ( 27, 21) [000029] DACXG------- * STORE_LCL_VAR int V04 loc1 d:2
rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X)
N005 ( 17, 16) [000033] DAC--------- * STORE_LCL_VAR ref V11 tmp2 d:2
rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X)
N012 ( 30, 27) [000044] DACXG------- * STORE_LCL_VAR int V05 loc2 d:2
rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X)
N009 ( 23, 15) [000051] DACXG------- * STORE_LCL_VAR int V06 loc3 d:2
rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X)
N005 ( 3, 3) [000114] DA---------- * STORE_LCL_VAR int V13 tmp4 d:2
rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X)
N005 ( 8, 6) [000120] DA---------- * STORE_LCL_VAR int V14 tmp5 d:2
rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X)
N005 ( 8, 6) [000131] DA---------- * STORE_LCL_VAR int V15 tmp6 d:2
rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X)
N007 ( 28, 10) [000058] DA-X-------- * STORE_LCL_VAR int V07 loc4 d:2
*************** Exiting IR Rationalize
Trees after IR Rationalize
-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..051) (return) i label target gcsafe newobj LIR
-----------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [000..051) (return), preds={} succs={}
N004 ( 2, 2) [000002] ------------ t2 = LCL_VAR int V02 arg2 u:1 $c0
/--* t2 int
N005 ( 3, 4) [000158] ------------ t158 = * CAST int <- ubyte <- int $180
/--* t158 int
N007 ( 7, 7) [000189] DA---------- * STORE_LCL_VAR int V19 cse0
N008 ( 3, 2) [000190] ------------ t190 = LCL_VAR int V19 cse0 $180
N010 ( 1, 1) [000000] ------------ t0 = LCL_VAR int V00 arg0 u:1 $80
N011 ( 1, 1) [000001] ------------ t1 = LCL_VAR int V01 arg1 u:1 $81
/--* t190 int arg2 in r8
+--* t0 int arg0 in rcx
+--* t1 int arg1 in rdx
N012 ( 26, 19) [000003] --CXG------- t3 = * CALL int Test2.DoTestImpl1 $143
/--* t3 int
N014 ( 26, 19) [000011] DA-XG------- * STORE_LCL_VAR int V10 tmp1 d:2
N005 ( 3, 2) [000192] ------------ t192 = LCL_VAR int V19 cse0 $180
N006 ( 1, 1) [000005] ------------ t5 = LCL_VAR int V00 arg0 u:1 $80
N007 ( 1, 1) [000006] ------------ t6 = LCL_VAR int V01 arg1 u:1 $81
N008 ( 3, 10) [000009] ------------ t9 = CNS_INT(h) long 0xd1ffab1e method $240
/--* t192 int arg3 in r9
+--* t5 int arg1 in rdx
+--* t6 int arg2 in r8
+--* t9 long arg0 in rcx
N009 ( 22, 23) [000008] --CXG------- t8 = * CALL int Test2.DoTestImpl2 $148
/--* t8 int
N011 ( 26, 26) [000015] DA-XG------- * STORE_LCL_VAR int V03 loc0 d:2
N001 ( 1, 1) [000018] ------------ t18 = CNS_INT int 0 $40
N002 ( 3, 2) [000016] D------N---- t16 = LCL_VAR_ADDR byref V08 loc5 d:2
/--* t16 byref
+--* t18 int
[000198] -A---------- * STOREIND byte
N005 ( 3, 2) [000193] ------------ t193 = LCL_VAR int V19 cse0 $180
N006 ( 4, 5) [000020] ------------ t20 = LCL_FLD byte V08 loc5 u:2[+0] (last use) $301
N007 ( 1, 1) [000021] ------------ t21 = LCL_VAR int V00 arg0 u:1 $80
N008 ( 1, 1) [000022] ------------ t22 = LCL_VAR int V01 arg1 u:1 $81
/--* t193 int arg3 in r9
+--* t20 byte arg0 in rcx
+--* t21 int arg1 in rdx
+--* t22 int arg2 in r8
N009 ( 23, 18) [000024] --CXG------- t24 = * CALL int Test2.DoTestImpl3 $14d
/--* t24 int
N011 ( 27, 21) [000029] DA-XG------- * STORE_LCL_VAR int V04 loc1 d:2
N002 ( 3, 10) [000030] ------------ t30 = CNS_INT(h) long 0xd1ffab1e method $241
/--* t30 long arg0 in rcx
N003 ( 17, 16) [000031] --C--------- t31 = * CALL help ref HELPER.CORINFO_HELP_NEWSFAST $340
/--* t31 ref
N005 ( 17, 16) [000033] DA---------- * STORE_LCL_VAR ref V11 tmp2 d:2
N005 ( 3, 2) [000194] ------------ t194 = LCL_VAR int V19 cse0 $180
N006 ( 1, 1) [000036] ------------ t36 = LCL_VAR ref V11 tmp2 u:2 (last use) $340
N007 ( 1, 1) [000037] ------------ t37 = LCL_VAR int V00 arg0 u:1 $80
N008 ( 1, 1) [000038] ------------ t38 = LCL_VAR int V01 arg1 u:1 $81
N009 ( 3, 10) [000041] ------------ t41 = CNS_INT(h) long 0xd1ffab1e method $242
/--* t194 int arg4 out+20
+--* t36 ref arg1 in rdx
+--* t37 int arg2 in r8
+--* t38 int arg3 in r9
+--* t41 long arg0 in rcx
N010 ( 26, 24) [000040] --CXG------- t40 = * CALL int Test2.DoTestImpl4 $151
/--* t40 int
N012 ( 30, 27) [000044] DA-XG------- * STORE_LCL_VAR int V05 loc2 d:2
N004 ( 3, 2) [000195] ------------ t195 = LCL_VAR int V19 cse0 $180
N005 ( 1, 1) [000045] ------------ t45 = LCL_VAR int V00 arg0 u:1 $80
N006 ( 1, 1) [000046] ------------ t46 = LCL_VAR int V01 arg1 u:1 $81
/--* t195 int arg2 in r8
+--* t45 int arg0 in rcx
+--* t46 int arg1 in rdx
N007 ( 19, 12) [000048] --CXG------- t48 = * CALL int Test2.DoTestImpl5 $156
/--* t48 int
N009 ( 23, 15) [000051] DA-XG------- * STORE_LCL_VAR int V06 loc3 d:2
N001 ( 1, 1) [000052] ------------ t52 = LCL_VAR int V00 arg0 u:1 $80
N002 ( 1, 1) [000053] ------------ t53 = LCL_VAR int V01 arg1 u:1 (last use) $81
/--* t52 int
+--* t53 int
N003 ( 3, 3) [000140] ------------ t140 = * ADD int $181
/--* t140 int
N005 ( 3, 3) [000114] DA---------- * STORE_LCL_VAR int V13 tmp4 d:2
N001 ( 1, 1) [000115] ------------ t115 = LCL_VAR int V13 tmp4 u:2 (last use) $181
N002 ( 3, 2) [000196] ------------ t196 = LCL_VAR int V19 cse0 $180
/--* t115 int
+--* t196 int
N003 ( 8, 6) [000145] ------------ t145 = * MUL int $182
/--* t145 int
N005 ( 8, 6) [000120] DA---------- * STORE_LCL_VAR int V14 tmp5 d:2
N001 ( 1, 1) [000121] ------------ t121 = LCL_VAR int V00 arg0 u:1 (last use) $80
N002 ( 3, 2) [000197] ------------ t197 = LCL_VAR int V19 cse0 $180
/--* t121 int
+--* t197 int
N003 ( 8, 6) [000150] ------------ t150 = * MUL int $183
/--* t150 int
N005 ( 8, 6) [000131] DA---------- * STORE_LCL_VAR int V15 tmp6 d:2
N001 ( 1, 1) [000132] ------------ t132 = LCL_VAR int V15 tmp6 u:2 (last use) $183
N002 ( 1, 1) [000127] ------------ t127 = LCL_VAR int V14 tmp5 u:2 (last use) $182
N003 ( 1, 1) [000152] ------------ t152 = CNS_INT int 2 $42
/--* t127 int
+--* t152 int
N004 ( 3, 3) [000153] ------------ t153 = * RSH int $184
/--* t132 int
+--* t153 int
N005 ( 24, 7) [000156] ---X-------- t156 = * DIV int $186
/--* t156 int
N007 ( 28, 10) [000058] DA-X-------- * STORE_LCL_VAR int V07 loc4 d:2
N001 ( 1, 1) [000012] ------------ t12 = LCL_VAR int V10 tmp1 u:2 (last use) $143
N002 ( 3, 2) [000059] ------------ t59 = LCL_VAR int V03 loc0 u:2 (last use) $148
/--* t12 int
+--* t59 int
N003 ( 5, 4) [000060] ------------ t60 = * ADD int $187
N004 ( 3, 2) [000061] ------------ t61 = LCL_VAR int V04 loc1 u:2 (last use) $14d
/--* t60 int
+--* t61 int
N005 ( 9, 7) [000062] ------------ t62 = * ADD int $188
N006 ( 3, 2) [000063] ------------ t63 = LCL_VAR int V05 loc2 u:2 (last use) $151
/--* t62 int
+--* t63 int
N007 ( 13, 10) [000064] ------------ t64 = * ADD int $189
N008 ( 3, 2) [000065] ------------ t65 = LCL_VAR int V06 loc3 u:2 (last use) $156
/--* t64 int
+--* t65 int
N009 ( 17, 13) [000066] ------------ t66 = * ADD int $18a
N010 ( 3, 2) [000067] ------------ t67 = LCL_VAR int V07 loc4 u:2 (last use) $185
/--* t66 int
+--* t67 int
N011 ( 21, 16) [000068] ------------ t68 = * ADD int $18b
/--* t68 int
N012 ( 22, 17) [000069] ------------ * RETURN int $15c
-------------------------------------------------------------------------------------------------------------------
*************** In fgDebugCheckBBlist
Bumping outgoingArgSpaceSize to 32 for call [000003]
outgoingArgSpaceSize 32 sufficient for call [000008], which needs 32
outgoingArgSpaceSize 32 sufficient for call [000024], which needs 32
outgoingArgSpaceSize 32 sufficient for call [000031], which needs 32
Bumping outgoingArgSpaceSize to 40 for call [000040]
outgoingArgSpaceSize 40 sufficient for call [000048], which needs 32
*************** In fgDebugCheckBBlist
*************** In Lowering
Trees before Lowering
-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..051) (return) i label target gcsafe newobj LIR
-----------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [000..051) (return), preds={} succs={}
N004 ( 2, 2) [000002] ------------ t2 = LCL_VAR int V02 arg2 u:1 $c0
/--* t2 int
N005 ( 3, 4) [000158] ------------ t158 = * CAST int <- ubyte <- int $180
/--* t158 int
N007 ( 7, 7) [000189] DA---------- * STORE_LCL_VAR int V19 cse0
N008 ( 3, 2) [000190] ------------ t190 = LCL_VAR int V19 cse0 $180
N010 ( 1, 1) [000000] ------------ t0 = LCL_VAR int V00 arg0 u:1 $80
N011 ( 1, 1) [000001] ------------ t1 = LCL_VAR int V01 arg1 u:1 $81
/--* t190 int arg2 in r8
+--* t0 int arg0 in rcx
+--* t1 int arg1 in rdx
N012 ( 26, 19) [000003] --CXG------- t3 = * CALL int Test2.DoTestImpl1 $143
/--* t3 int
N014 ( 26, 19) [000011] DA-XG------- * STORE_LCL_VAR int V10 tmp1 d:2
N005 ( 3, 2) [000192] ------------ t192 = LCL_VAR int V19 cse0 $180
N006 ( 1, 1) [000005] ------------ t5 = LCL_VAR int V00 arg0 u:1 $80
N007 ( 1, 1) [000006] ------------ t6 = LCL_VAR int V01 arg1 u:1 $81
N008 ( 3, 10) [000009] ------------ t9 = CNS_INT(h) long 0xd1ffab1e method $240
/--* t192 int arg3 in r9
+--* t5 int arg1 in rdx
+--* t6 int arg2 in r8
+--* t9 long arg0 in rcx
N009 ( 22, 23) [000008] --CXG------- t8 = * CALL int Test2.DoTestImpl2 $148
/--* t8 int
N011 ( 26, 26) [000015] DA-XG------- * STORE_LCL_VAR int V03 loc0 d:2
N001 ( 1, 1) [000018] ------------ t18 = CNS_INT int 0 $40
N002 ( 3, 2) [000016] D------N---- t16 = LCL_VAR_ADDR byref V08 loc5 d:2
/--* t16 byref
+--* t18 int
[000198] -A---------- * STOREIND byte
N005 ( 3, 2) [000193] ------------ t193 = LCL_VAR int V19 cse0 $180
N006 ( 4, 5) [000020] ------------ t20 = LCL_FLD byte V08 loc5 u:2[+0] (last use) $301
N007 ( 1, 1) [000021] ------------ t21 = LCL_VAR int V00 arg0 u:1 $80
N008 ( 1, 1) [000022] ------------ t22 = LCL_VAR int V01 arg1 u:1 $81
/--* t193 int arg3 in r9
+--* t20 byte arg0 in rcx
+--* t21 int arg1 in rdx
+--* t22 int arg2 in r8
N009 ( 23, 18) [000024] --CXG------- t24 = * CALL int Test2.DoTestImpl3 $14d
/--* t24 int
N011 ( 27, 21) [000029] DA-XG------- * STORE_LCL_VAR int V04 loc1 d:2
N002 ( 3, 10) [000030] ------------ t30 = CNS_INT(h) long 0xd1ffab1e method $241
/--* t30 long arg0 in rcx
N003 ( 17, 16) [000031] --C--------- t31 = * CALL help ref HELPER.CORINFO_HELP_NEWSFAST $340
/--* t31 ref
N005 ( 17, 16) [000033] DA---------- * STORE_LCL_VAR ref V11 tmp2 d:2
N005 ( 3, 2) [000194] ------------ t194 = LCL_VAR int V19 cse0 $180
N006 ( 1, 1) [000036] ------------ t36 = LCL_VAR ref V11 tmp2 u:2 (last use) $340
N007 ( 1, 1) [000037] ------------ t37 = LCL_VAR int V00 arg0 u:1 $80
N008 ( 1, 1) [000038] ------------ t38 = LCL_VAR int V01 arg1 u:1 $81
N009 ( 3, 10) [000041] ------------ t41 = CNS_INT(h) long 0xd1ffab1e method $242
/--* t194 int arg4 out+20
+--* t36 ref arg1 in rdx
+--* t37 int arg2 in r8
+--* t38 int arg3 in r9
+--* t41 long arg0 in rcx
N010 ( 26, 24) [000040] --CXG------- t40 = * CALL int Test2.DoTestImpl4 $151
/--* t40 int
N012 ( 30, 27) [000044] DA-XG------- * STORE_LCL_VAR int V05 loc2 d:2
N004 ( 3, 2) [000195] ------------ t195 = LCL_VAR int V19 cse0 $180
N005 ( 1, 1) [000045] ------------ t45 = LCL_VAR int V00 arg0 u:1 $80
N006 ( 1, 1) [000046] ------------ t46 = LCL_VAR int V01 arg1 u:1 $81
/--* t195 int arg2 in r8
+--* t45 int arg0 in rcx
+--* t46 int arg1 in rdx
N007 ( 19, 12) [000048] --CXG------- t48 = * CALL int Test2.DoTestImpl5 $156
/--* t48 int
N009 ( 23, 15) [000051] DA-XG------- * STORE_LCL_VAR int V06 loc3 d:2
N001 ( 1, 1) [000052] ------------ t52 = LCL_VAR int V00 arg0 u:1 $80
N002 ( 1, 1) [000053] ------------ t53 = LCL_VAR int V01 arg1 u:1 (last use) $81
/--* t52 int
+--* t53 int
N003 ( 3, 3) [000140] ------------ t140 = * ADD int $181
/--* t140 int
N005 ( 3, 3) [000114] DA---------- * STORE_LCL_VAR int V13 tmp4 d:2
N001 ( 1, 1) [000115] ------------ t115 = LCL_VAR int V13 tmp4 u:2 (last use) $181
N002 ( 3, 2) [000196] ------------ t196 = LCL_VAR int V19 cse0 $180
/--* t115 int
+--* t196 int
N003 ( 8, 6) [000145] ------------ t145 = * MUL int $182
/--* t145 int
N005 ( 8, 6) [000120] DA---------- * STORE_LCL_VAR int V14 tmp5 d:2
N001 ( 1, 1) [000121] ------------ t121 = LCL_VAR int V00 arg0 u:1 (last use) $80
N002 ( 3, 2) [000197] ------------ t197 = LCL_VAR int V19 cse0 $180
/--* t121 int
+--* t197 int
N003 ( 8, 6) [000150] ------------ t150 = * MUL int $183
/--* t150 int
N005 ( 8, 6) [000131] DA---------- * STORE_LCL_VAR int V15 tmp6 d:2
N001 ( 1, 1) [000132] ------------ t132 = LCL_VAR int V15 tmp6 u:2 (last use) $183
N002 ( 1, 1) [000127] ------------ t127 = LCL_VAR int V14 tmp5 u:2 (last use) $182
N003 ( 1, 1) [000152] ------------ t152 = CNS_INT int 2 $42
/--* t127 int
+--* t152 int
N004 ( 3, 3) [000153] ------------ t153 = * RSH int $184
/--* t132 int
+--* t153 int
N005 ( 24, 7) [000156] ---X-------- t156 = * DIV int $186
/--* t156 int
N007 ( 28, 10) [000058] DA-X-------- * STORE_LCL_VAR int V07 loc4 d:2
N001 ( 1, 1) [000012] ------------ t12 = LCL_VAR int V10 tmp1 u:2 (last use) $143
N002 ( 3, 2) [000059] ------------ t59 = LCL_VAR int V03 loc0 u:2 (last use) $148
/--* t12 int
+--* t59 int
N003 ( 5, 4) [000060] ------------ t60 = * ADD int $187
N004 ( 3, 2) [000061] ------------ t61 = LCL_VAR int V04 loc1 u:2 (last use) $14d
/--* t60 int
+--* t61 int
N005 ( 9, 7) [000062] ------------ t62 = * ADD int $188
N006 ( 3, 2) [000063] ------------ t63 = LCL_VAR int V05 loc2 u:2 (last use) $151
/--* t62 int
+--* t63 int
N007 ( 13, 10) [000064] ------------ t64 = * ADD int $189
N008 ( 3, 2) [000065] ------------ t65 = LCL_VAR int V06 loc3 u:2 (last use) $156
/--* t64 int
+--* t65 int
N009 ( 17, 13) [000066] ------------ t66 = * ADD int $18a
N010 ( 3, 2) [000067] ------------ t67 = LCL_VAR int V07 loc4 u:2 (last use) $185
/--* t66 int
+--* t67 int
N011 ( 21, 16) [000068] ------------ t68 = * ADD int $18b
/--* t68 int
N012 ( 22, 17) [000069] ------------ * RETURN int $15c
-------------------------------------------------------------------------------------------------------------------
lowering call (before):
N008 ( 3, 2) [000190] ------------ t190 = LCL_VAR int V19 cse0 $180
N010 ( 1, 1) [000000] ------------ t0 = LCL_VAR int V00 arg0 u:1 $80
N011 ( 1, 1) [000001] ------------ t1 = LCL_VAR int V01 arg1 u:1 $81
/--* t190 int arg2 in r8
+--* t0 int arg0 in rcx
+--* t1 int arg1 in rdx
N012 ( 26, 19) [000003] --CXG------- t3 = * CALL int Test2.DoTestImpl1 $143
objp:
======
args:
======
lowering arg : N001 ( 0, 0) [000160] ----------L- * ARGPLACE int $80
lowering arg : N002 ( 0, 0) [000161] ----------L- * ARGPLACE int $81
lowering arg : N003 ( 0, 0) [000159] ----------L- * ARGPLACE int $180
late:
======
lowering arg : N008 ( 3, 2) [000190] ------------ * LCL_VAR int V19 cse0 $180
new node is : [000199] ------------ * PUTARG_REG int REG r8
lowering arg : N010 ( 1, 1) [000000] ------------ * LCL_VAR int V00 arg0 u:1 $80
new node is : [000200] ------------ * PUTARG_REG int REG rcx
lowering arg : N011 ( 1, 1) [000001] ------------ * LCL_VAR int V01 arg1 u:1 $81
new node is : [000201] ------------ * PUTARG_REG int REG rdx
lowering call (after):
N008 ( 3, 2) [000190] ------------ t190 = LCL_VAR int V19 cse0 $180
/--* t190 int
[000199] ------------ t199 = * PUTARG_REG int REG r8
N010 ( 1, 1) [000000] ------------ t0 = LCL_VAR int V00 arg0 u:1 $80
/--* t0 int
[000200] ------------ t200 = * PUTARG_REG int REG rcx
N011 ( 1, 1) [000001] ------------ t1 = LCL_VAR int V01 arg1 u:1 $81
/--* t1 int
[000201] ------------ t201 = * PUTARG_REG int REG rdx
/--* t199 int arg2 in r8
+--* t200 int arg0 in rcx
+--* t201 int arg1 in rdx
N012 ( 26, 19) [000003] --CXG------- t3 = * CALL int Test2.DoTestImpl1 $143
lowering call (before):
N005 ( 3, 2) [000192] ------------ t192 = LCL_VAR int V19 cse0 $180
N006 ( 1, 1) [000005] ------------ t5 = LCL_VAR int V00 arg0 u:1 $80
N007 ( 1, 1) [000006] ------------ t6 = LCL_VAR int V01 arg1 u:1 $81
N008 ( 3, 10) [000009] ------------ t9 = CNS_INT(h) long 0xd1ffab1e method $240
/--* t192 int arg3 in r9
+--* t5 int arg1 in rdx
+--* t6 int arg2 in r8
+--* t9 long arg0 in rcx
N009 ( 22, 23) [000008] --CXG------- t8 = * CALL int Test2.DoTestImpl2 $148
objp:
======
args:
======
lowering arg : N001 ( 0, 0) [000166] ----------L- * ARGPLACE long $240
lowering arg : N002 ( 0, 0) [000164] ----------L- * ARGPLACE int $80
lowering arg : N003 ( 0, 0) [000165] ----------L- * ARGPLACE int $81
lowering arg : N004 ( 0, 0) [000163] ----------L- * ARGPLACE int $180
late:
======
lowering arg : N005 ( 3, 2) [000192] ------------ * LCL_VAR int V19 cse0 $180
new node is : [000202] ------------ * PUTARG_REG int REG r9
lowering arg : N006 ( 1, 1) [000005] ------------ * LCL_VAR int V00 arg0 u:1 $80
new node is : [000203] ------------ * PUTARG_REG int REG rdx
lowering arg : N007 ( 1, 1) [000006] ------------ * LCL_VAR int V01 arg1 u:1 $81
new node is : [000204] ------------ * PUTARG_REG int REG r8
lowering arg : N008 ( 3, 10) [000009] ------------ * CNS_INT(h) long 0xd1ffab1e method $240
new node is : [000205] ------------ * PUTARG_REG long REG rcx
lowering call (after):
N005 ( 3, 2) [000192] ------------ t192 = LCL_VAR int V19 cse0 $180
/--* t192 int
[000202] ------------ t202 = * PUTARG_REG int REG r9
N006 ( 1, 1) [000005] ------------ t5 = LCL_VAR int V00 arg0 u:1 $80
/--* t5 int
[000203] ------------ t203 = * PUTARG_REG int REG rdx
N007 ( 1, 1) [000006] ------------ t6 = LCL_VAR int V01 arg1 u:1 $81
/--* t6 int
[000204] ------------ t204 = * PUTARG_REG int REG r8
N008 ( 3, 10) [000009] ------------ t9 = CNS_INT(h) long 0xd1ffab1e method $240
/--* t9 long
[000205] ------------ t205 = * PUTARG_REG long REG rcx
/--* t202 int arg3 in r9
+--* t203 int arg1 in rdx
+--* t204 int arg2 in r8
+--* t205 long arg0 in rcx
N009 ( 22, 23) [000008] --CXG------- t8 = * CALL int Test2.DoTestImpl2 $148
No addressing mode:
N002 ( 3, 2) [000016] D------N---- * LCL_VAR_ADDR byref V08 loc5 d:2
Lower of StoreInd didn't mark the node as self contained for reason: 4
N001 ( 1, 1) [000018] ------------ t18 = CNS_INT int 0 $40
N002 ( 3, 2) [000016] D------N---- t16 = LCL_VAR_ADDR byref V08 loc5 d:2
/--* t16 byref
+--* t18 int
[000198] -A---------- * STOREIND byte
lowering call (before):
N005 ( 3, 2) [000193] ------------ t193 = LCL_VAR int V19 cse0 $180
N006 ( 4, 5) [000020] ------------ t20 = LCL_FLD byte V08 loc5 u:2[+0] (last use) $301
N007 ( 1, 1) [000021] ------------ t21 = LCL_VAR int V00 arg0 u:1 $80
N008 ( 1, 1) [000022] ------------ t22 = LCL_VAR int V01 arg1 u:1 $81
/--* t193 int arg3 in r9
+--* t20 byte arg0 in rcx
+--* t21 int arg1 in rdx
+--* t22 int arg2 in r8
N009 ( 23, 18) [000024] --CXG------- t24 = * CALL int Test2.DoTestImpl3 $14d
objp:
======
args:
======
lowering arg : N001 ( 0, 0) [000171] ----------L- * ARGPLACE byte $301
lowering arg : N002 ( 0, 0) [000172] ----------L- * ARGPLACE int $80
lowering arg : N003 ( 0, 0) [000173] ----------L- * ARGPLACE int $81
lowering arg : N004 ( 0, 0) [000170] ----------L- * ARGPLACE int $180
late:
======
lowering arg : N005 ( 3, 2) [000193] ------------ * LCL_VAR int V19 cse0 $180
new node is : [000206] ------------ * PUTARG_REG int REG r9
lowering arg : N006 ( 4, 5) [000020] ------------ * LCL_FLD byte V08 loc5 u:2[+0] (last use) $301
new node is : [000207] ------------ * PUTARG_REG int REG rcx
lowering arg : N007 ( 1, 1) [000021] ------------ * LCL_VAR int V00 arg0 u:1 $80
new node is : [000208] ------------ * PUTARG_REG int REG rdx
lowering arg : N008 ( 1, 1) [000022] ------------ * LCL_VAR int V01 arg1 u:1 $81
new node is : [000209] ------------ * PUTARG_REG int REG r8
lowering call (after):
N005 ( 3, 2) [000193] ------------ t193 = LCL_VAR int V19 cse0 $180
/--* t193 int
[000206] ------------ t206 = * PUTARG_REG int REG r9
N006 ( 4, 5) [000020] ------------ t20 = LCL_FLD byte V08 loc5 u:2[+0] (last use) $301
/--* t20 byte
[000207] ------------ t207 = * PUTARG_REG int REG rcx
N007 ( 1, 1) [000021] ------------ t21 = LCL_VAR int V00 arg0 u:1 $80
/--* t21 int
[000208] ------------ t208 = * PUTARG_REG int REG rdx
N008 ( 1, 1) [000022] ------------ t22 = LCL_VAR int V01 arg1 u:1 $81
/--* t22 int
[000209] ------------ t209 = * PUTARG_REG int REG r8
/--* t206 int arg3 in r9
+--* t207 int arg0 in rcx
+--* t208 int arg1 in rdx
+--* t209 int arg2 in r8
N009 ( 23, 18) [000024] --CXG------- t24 = * CALL int Test2.DoTestImpl3 $14d
lowering call (before):
N002 ( 3, 10) [000030] ------------ t30 = CNS_INT(h) long 0xd1ffab1e method $241
/--* t30 long arg0 in rcx
N003 ( 17, 16) [000031] --C--------- t31 = * CALL help ref HELPER.CORINFO_HELP_NEWSFAST $340
objp:
======
args:
======
lowering arg : N001 ( 0, 0) [000174] ----------L- * ARGPLACE long $241
late:
======
lowering arg : N002 ( 3, 10) [000030] ------------ * CNS_INT(h) long 0xd1ffab1e method $241
new node is : [000210] ------------ * PUTARG_REG long REG rcx
lowering call (after):
N002 ( 3, 10) [000030] ------------ t30 = CNS_INT(h) long 0xd1ffab1e method $241
/--* t30 long
[000210] ------------ t210 = * PUTARG_REG long REG rcx
/--* t210 long arg0 in rcx
N003 ( 17, 16) [000031] --C--------- t31 = * CALL help ref HELPER.CORINFO_HELP_NEWSFAST $340
lowering call (before):
N005 ( 3, 2) [000194] ------------ t194 = LCL_VAR int V19 cse0 $180
N006 ( 1, 1) [000036] ------------ t36 = LCL_VAR ref V11 tmp2 u:2 (last use) $340
N007 ( 1, 1) [000037] ------------ t37 = LCL_VAR int V00 arg0 u:1 $80
N008 ( 1, 1) [000038] ------------ t38 = LCL_VAR int V01 arg1 u:1 $81
N009 ( 3, 10) [000041] ------------ t41 = CNS_INT(h) long 0xd1ffab1e method $242
/--* t194 int arg4 out+20
+--* t36 ref arg1 in rdx
+--* t37 int arg2 in r8
+--* t38 int arg3 in r9
+--* t41 long arg0 in rcx
N010 ( 26, 24) [000040] --CXG------- t40 = * CALL int Test2.DoTestImpl4 $151
objp:
======
args:
======
lowering arg : N001 ( 0, 0) [000179] ----------L- * ARGPLACE long $242
lowering arg : N002 ( 0, 0) [000176] ----------L- * ARGPLACE ref $340
lowering arg : N003 ( 0, 0) [000177] ----------L- * ARGPLACE int $80
lowering arg : N004 ( 0, 0) [000178] ----------L- * ARGPLACE int $81
lowering arg : N005 ( 3, 2) [000194] ------------ * LCL_VAR int V19 cse0 $180
new node is : [000211] ------------ * PUTARG_STK [+0x20] void
late:
======
lowering arg : N006 ( 1, 1) [000036] ------------ * LCL_VAR ref V11 tmp2 u:2 (last use) $340
new node is : [000212] ------------ * PUTARG_REG ref REG rdx
lowering arg : N007 ( 1, 1) [000037] ------------ * LCL_VAR int V00 arg0 u:1 $80
new node is : [000213] ------------ * PUTARG_REG int REG r8
lowering arg : N008 ( 1, 1) [000038] ------------ * LCL_VAR int V01 arg1 u:1 $81
new node is : [000214] ------------ * PUTARG_REG int REG r9
lowering arg : N009 ( 3, 10) [000041] ------------ * CNS_INT(h) long 0xd1ffab1e method $242
new node is : [000215] ------------ * PUTARG_REG long REG rcx
lowering call (after):
N005 ( 3, 2) [000194] ------------ t194 = LCL_VAR int V19 cse0 $180
/--* t194 int
[000211] ------------ * PUTARG_STK [+0x20] void
N006 ( 1, 1) [000036] ------------ t36 = LCL_VAR ref V11 tmp2 u:2 (last use) $340
/--* t36 ref
[000212] ------------ t212 = * PUTARG_REG ref REG rdx
N007 ( 1, 1) [000037] ------------ t37 = LCL_VAR int V00 arg0 u:1 $80
/--* t37 int
[000213] ------------ t213 = * PUTARG_REG int REG r8
N008 ( 1, 1) [000038] ------------ t38 = LCL_VAR int V01 arg1 u:1 $81
/--* t38 int
[000214] ------------ t214 = * PUTARG_REG int REG r9
N009 ( 3, 10) [000041] ------------ t41 = CNS_INT(h) long 0xd1ffab1e method $242
/--* t41 long
[000215] ------------ t215 = * PUTARG_REG long REG rcx
/--* t212 ref arg1 in rdx
+--* t213 int arg2 in r8
+--* t214 int arg3 in r9
+--* t215 long arg0 in rcx
N010 ( 26, 24) [000040] --CXG------- t40 = * CALL int Test2.DoTestImpl4 $151
lowering call (before):
N004 ( 3, 2) [000195] ------------ t195 = LCL_VAR int V19 cse0 $180
N005 ( 1, 1) [000045] ------------ t45 = LCL_VAR int V00 arg0 u:1 $80
N006 ( 1, 1) [000046] ------------ t46 = LCL_VAR int V01 arg1 u:1 $81
/--* t195 int arg2 in r8
+--* t45 int arg0 in rcx
+--* t46 int arg1 in rdx
N007 ( 19, 12) [000048] --CXG------- t48 = * CALL int Test2.DoTestImpl5 $156
objp:
======
args:
======
lowering arg : N001 ( 0, 0) [000182] ----------L- * ARGPLACE int $80
lowering arg : N002 ( 0, 0) [000183] ----------L- * ARGPLACE int $81
lowering arg : N003 ( 0, 0) [000181] ----------L- * ARGPLACE int $180
late:
======
lowering arg : N004 ( 3, 2) [000195] ------------ * LCL_VAR int V19 cse0 $180
new node is : [000216] ------------ * PUTARG_REG int REG r8
lowering arg : N005 ( 1, 1) [000045] ------------ * LCL_VAR int V00 arg0 u:1 $80
new node is : [000217] ------------ * PUTARG_REG int REG rcx
lowering arg : N006 ( 1, 1) [000046] ------------ * LCL_VAR int V01 arg1 u:1 $81
new node is : [000218] ------------ * PUTARG_REG int REG rdx
lowering call (after):
N004 ( 3, 2) [000195] ------------ t195 = LCL_VAR int V19 cse0 $180
/--* t195 int
[000216] ------------ t216 = * PUTARG_REG int REG r8
N005 ( 1, 1) [000045] ------------ t45 = LCL_VAR int V00 arg0 u:1 $80
/--* t45 int
[000217] ------------ t217 = * PUTARG_REG int REG rcx
N006 ( 1, 1) [000046] ------------ t46 = LCL_VAR int V01 arg1 u:1 $81
/--* t46 int
[000218] ------------ t218 = * PUTARG_REG int REG rdx
/--* t216 int arg2 in r8
+--* t217 int arg0 in rcx
+--* t218 int arg1 in rdx
N007 ( 19, 12) [000048] --CXG------- t48 = * CALL int Test2.DoTestImpl5 $156
lowering GT_RETURN
N012 ( 22, 17) [000069] ------------ * RETURN int $15c
============Lower has completed modifying nodes.
-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..051) (return) i label target gcsafe newobj LIR
-----------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [000..051) (return), preds={} succs={}
N004 ( 2, 2) [000002] ------------ t2 = LCL_VAR int V02 arg2 u:1 $c0
/--* t2 int
N005 ( 3, 4) [000158] ------------ t158 = * CAST int <- ubyte <- int $180
/--* t158 int
N007 ( 7, 7) [000189] DA---------- * STORE_LCL_VAR int V19 cse0
N008 ( 3, 2) [000190] ------------ t190 = LCL_VAR int V19 cse0 $180
/--* t190 int
[000199] ------------ t199 = * PUTARG_REG int REG r8
N010 ( 1, 1) [000000] ------------ t0 = LCL_VAR int V00 arg0 u:1 $80
/--* t0 int
[000200] ------------ t200 = * PUTARG_REG int REG rcx
N011 ( 1, 1) [000001] ------------ t1 = LCL_VAR int V01 arg1 u:1 $81
/--* t1 int
[000201] ------------ t201 = * PUTARG_REG int REG rdx
/--* t199 int arg2 in r8
+--* t200 int arg0 in rcx
+--* t201 int arg1 in rdx
N012 ( 26, 19) [000003] --CXG------- t3 = * CALL int Test2.DoTestImpl1 $143
/--* t3 int
N014 ( 26, 19) [000011] DA-XG------- * STORE_LCL_VAR int V10 tmp1 d:2
N005 ( 3, 2) [000192] ------------ t192 = LCL_VAR int V19 cse0 $180
/--* t192 int
[000202] ------------ t202 = * PUTARG_REG int REG r9
N006 ( 1, 1) [000005] ------------ t5 = LCL_VAR int V00 arg0 u:1 $80
/--* t5 int
[000203] ------------ t203 = * PUTARG_REG int REG rdx
N007 ( 1, 1) [000006] ------------ t6 = LCL_VAR int V01 arg1 u:1 $81
/--* t6 int
[000204] ------------ t204 = * PUTARG_REG int REG r8
N008 ( 3, 10) [000009] ------------ t9 = CNS_INT(h) long 0xd1ffab1e method $240
/--* t9 long
[000205] ------------ t205 = * PUTARG_REG long REG rcx
/--* t202 int arg3 in r9
+--* t203 int arg1 in rdx
+--* t204 int arg2 in r8
+--* t205 long arg0 in rcx
N009 ( 22, 23) [000008] --CXG------- t8 = * CALL int Test2.DoTestImpl2 $148
/--* t8 int
N011 ( 26, 26) [000015] DA-XG------- * STORE_LCL_VAR int V03 loc0 d:2
N001 ( 1, 1) [000018] -c---------- t18 = CNS_INT int 0 $40
N002 ( 3, 2) [000016] Dc-----N---- t16 = LCL_VAR_ADDR byref V08 loc5 d:2
/--* t16 byref
+--* t18 int
[000198] -A---------- * STOREIND byte
N005 ( 3, 2) [000193] ------------ t193 = LCL_VAR int V19 cse0 $180
/--* t193 int
[000206] ------------ t206 = * PUTARG_REG int REG r9
N006 ( 4, 5) [000020] ------------ t20 = LCL_FLD byte V08 loc5 u:2[+0] (last use) $301
/--* t20 byte
[000207] ------------ t207 = * PUTARG_REG int REG rcx
N007 ( 1, 1) [000021] ------------ t21 = LCL_VAR int V00 arg0 u:1 $80
/--* t21 int
[000208] ------------ t208 = * PUTARG_REG int REG rdx
N008 ( 1, 1) [000022] ------------ t22 = LCL_VAR int V01 arg1 u:1 $81
/--* t22 int
[000209] ------------ t209 = * PUTARG_REG int REG r8
/--* t206 int arg3 in r9
+--* t207 int arg0 in rcx
+--* t208 int arg1 in rdx
+--* t209 int arg2 in r8
N009 ( 23, 18) [000024] --CXG------- t24 = * CALL int Test2.DoTestImpl3 $14d
/--* t24 int
N011 ( 27, 21) [000029] DA-XG------- * STORE_LCL_VAR int V04 loc1 d:2
N002 ( 3, 10) [000030] ------------ t30 = CNS_INT(h) long 0xd1ffab1e method $241
/--* t30 long
[000210] ------------ t210 = * PUTARG_REG long REG rcx
/--* t210 long arg0 in rcx
N003 ( 17, 16) [000031] --C--------- t31 = * CALL help ref HELPER.CORINFO_HELP_NEWSFAST $340
/--* t31 ref
N005 ( 17, 16) [000033] DA---------- * STORE_LCL_VAR ref V11 tmp2 d:2
N005 ( 3, 2) [000194] ------------ t194 = LCL_VAR int V19 cse0 $180
/--* t194 int
[000211] ------------ * PUTARG_STK [+0x20] void
N006 ( 1, 1) [000036] ------------ t36 = LCL_VAR ref V11 tmp2 u:2 (last use) $340
/--* t36 ref
[000212] ------------ t212 = * PUTARG_REG ref REG rdx
N007 ( 1, 1) [000037] ------------ t37 = LCL_VAR int V00 arg0 u:1 $80
/--* t37 int
[000213] ------------ t213 = * PUTARG_REG int REG r8
N008 ( 1, 1) [000038] ------------ t38 = LCL_VAR int V01 arg1 u:1 $81
/--* t38 int
[000214] ------------ t214 = * PUTARG_REG int REG r9
N009 ( 3, 10) [000041] ------------ t41 = CNS_INT(h) long 0xd1ffab1e method $242
/--* t41 long
[000215] ------------ t215 = * PUTARG_REG long REG rcx
/--* t212 ref arg1 in rdx
+--* t213 int arg2 in r8
+--* t214 int arg3 in r9
+--* t215 long arg0 in rcx
N010 ( 26, 24) [000040] --CXG------- t40 = * CALL int Test2.DoTestImpl4 $151
/--* t40 int
N012 ( 30, 27) [000044] DA-XG------- * STORE_LCL_VAR int V05 loc2 d:2
N004 ( 3, 2) [000195] ------------ t195 = LCL_VAR int V19 cse0 $180
/--* t195 int
[000216] ------------ t216 = * PUTARG_REG int REG r8
N005 ( 1, 1) [000045] ------------ t45 = LCL_VAR int V00 arg0 u:1 $80
/--* t45 int
[000217] ------------ t217 = * PUTARG_REG int REG rcx
N006 ( 1, 1) [000046] ------------ t46 = LCL_VAR int V01 arg1 u:1 $81
/--* t46 int
[000218] ------------ t218 = * PUTARG_REG int REG rdx
/--* t216 int arg2 in r8
+--* t217 int arg0 in rcx
+--* t218 int arg1 in rdx
N007 ( 19, 12) [000048] --CXG------- t48 = * CALL int Test2.DoTestImpl5 $156
/--* t48 int
N009 ( 23, 15) [000051] DA-XG------- * STORE_LCL_VAR int V06 loc3 d:2
N001 ( 1, 1) [000052] ------------ t52 = LCL_VAR int V00 arg0 u:1 $80
N002 ( 1, 1) [000053] ------------ t53 = LCL_VAR int V01 arg1 u:1 (last use) $81
/--* t52 int
+--* t53 int
N003 ( 3, 3) [000140] ------------ t140 = * ADD int $181
/--* t140 int
N005 ( 3, 3) [000114] DA---------- * STORE_LCL_VAR int V13 tmp4 d:2
N001 ( 1, 1) [000115] ------------ t115 = LCL_VAR int V13 tmp4 u:2 (last use) $181
N002 ( 3, 2) [000196] ------------ t196 = LCL_VAR int V19 cse0 $180
/--* t115 int
+--* t196 int
N003 ( 8, 6) [000145] ------------ t145 = * MUL int $182
/--* t145 int
N005 ( 8, 6) [000120] DA---------- * STORE_LCL_VAR int V14 tmp5 d:2
N001 ( 1, 1) [000121] ------------ t121 = LCL_VAR int V00 arg0 u:1 (last use) $80
N002 ( 3, 2) [000197] ------------ t197 = LCL_VAR int V19 cse0 $180
/--* t121 int
+--* t197 int
N003 ( 8, 6) [000150] ------------ t150 = * MUL int $183
/--* t150 int
N005 ( 8, 6) [000131] DA---------- * STORE_LCL_VAR int V15 tmp6 d:2
N001 ( 1, 1) [000132] ------------ t132 = LCL_VAR int V15 tmp6 u:2 (last use) $183
N002 ( 1, 1) [000127] ------------ t127 = LCL_VAR int V14 tmp5 u:2 (last use) $182
N003 ( 1, 1) [000152] -c---------- t152 = CNS_INT int 2 $42
/--* t127 int
+--* t152 int
N004 ( 3, 3) [000153] ------------ t153 = * RSH int $184
/--* t132 int
+--* t153 int
N005 ( 24, 7) [000156] ---X-------- t156 = * DIV int $186
/--* t156 int
N007 ( 28, 10) [000058] DA-X-------- * STORE_LCL_VAR int V07 loc4 d:2
N001 ( 1, 1) [000012] ------------ t12 = LCL_VAR int V10 tmp1 u:2 (last use) $143
N002 ( 3, 2) [000059] ------------ t59 = LCL_VAR int V03 loc0 u:2 (last use) $148
/--* t12 int
+--* t59 int
N003 ( 5, 4) [000060] ------------ t60 = * ADD int $187
N004 ( 3, 2) [000061] ------------ t61 = LCL_VAR int V04 loc1 u:2 (last use) $14d
/--* t60 int
+--* t61 int
N005 ( 9, 7) [000062] ------------ t62 = * ADD int $188
N006 ( 3, 2) [000063] ------------ t63 = LCL_VAR int V05 loc2 u:2 (last use) $151
/--* t62 int
+--* t63 int
N007 ( 13, 10) [000064] ------------ t64 = * ADD int $189
N008 ( 3, 2) [000065] ------------ t65 = LCL_VAR int V06 loc3 u:2 (last use) $156
/--* t64 int
+--* t65 int
N009 ( 17, 13) [000066] ------------ t66 = * ADD int $18a
N010 ( 3, 2) [000067] ------------ t67 = LCL_VAR int V07 loc4 u:2 (last use) $185
/--* t66 int
+--* t67 int
N011 ( 21, 16) [000068] ------------ t68 = * ADD int $18b
/--* t68 int
N012 ( 22, 17) [000069] ------------ * RETURN int $15c
-------------------------------------------------------------------------------------------------------------------
*** lvaComputeRefCounts ***
*** lvaComputeRefCounts -- explicit counts ***
New refCnts for V02: refCnt = 1, refCntWtd = 1
New refCnts for V19: refCnt = 1, refCntWtd = 1
New refCnts for V19: refCnt = 2, refCntWtd = 2
New refCnts for V00: refCnt = 1, refCntWtd = 1
New refCnts for V01: refCnt = 1, refCntWtd = 1
New refCnts for V10: refCnt = 1, refCntWtd = 2
New refCnts for V19: refCnt = 3, refCntWtd = 3
New refCnts for V00: refCnt = 2, refCntWtd = 2
New refCnts for V01: refCnt = 2, refCntWtd = 2
New refCnts for V03: refCnt = 1, refCntWtd = 1
New refCnts for V08: refCnt = 1, refCntWtd = 1
New refCnts for V19: refCnt = 4, refCntWtd = 4
New refCnts for V08: refCnt = 2, refCntWtd = 2
New refCnts for V00: refCnt = 3, refCntWtd = 3
New refCnts for V01: refCnt = 3, refCntWtd = 3
New refCnts for V04: refCnt = 1, refCntWtd = 1
New refCnts for V11: refCnt = 1, refCntWtd = 2
New refCnts for V19: refCnt = 5, refCntWtd = 5
New refCnts for V11: refCnt = 2, refCntWtd = 4
New refCnts for V00: refCnt = 4, refCntWtd = 4
New refCnts for V01: refCnt = 4, refCntWtd = 4
New refCnts for V05: refCnt = 1, refCntWtd = 1
New refCnts for V19: refCnt = 6, refCntWtd = 6
New refCnts for V00: refCnt = 5, refCntWtd = 5
New refCnts for V01: refCnt = 5, refCntWtd = 5
New refCnts for V06: refCnt = 1, refCntWtd = 1
New refCnts for V00: refCnt = 6, refCntWtd = 6
New refCnts for V01: refCnt = 6, refCntWtd = 6
New refCnts for V13: refCnt = 1, refCntWtd = 2
New refCnts for V13: refCnt = 2, refCntWtd = 4
New refCnts for V19: refCnt = 7, refCntWtd = 7
New refCnts for V14: refCnt = 1, refCntWtd = 1
New refCnts for V00: refCnt = 7, refCntWtd = 7
New refCnts for V19: refCnt = 8, refCntWtd = 8
New refCnts for V15: refCnt = 1, refCntWtd = 2
New refCnts for V15: refCnt = 2, refCntWtd = 4
New refCnts for V14: refCnt = 2, refCntWtd = 2
New refCnts for V07: refCnt = 1, refCntWtd = 1
New refCnts for V10: refCnt = 2, refCntWtd = 4
New refCnts for V03: refCnt = 2, refCntWtd = 2
New refCnts for V04: refCnt = 2, refCntWtd = 2
New refCnts for V05: refCnt = 2, refCntWtd = 2
New refCnts for V06: refCnt = 2, refCntWtd = 2
New refCnts for V07: refCnt = 2, refCntWtd = 2
*** lvaComputeRefCounts -- implicit counts ***
New refCnts for V00: refCnt = 8, refCntWtd = 8
New refCnts for V00: refCnt = 9, refCntWtd = 9
New refCnts for V01: refCnt = 7, refCntWtd = 7
New refCnts for V01: refCnt = 8, refCntWtd = 8
New refCnts for V02: refCnt = 2, refCntWtd = 2
New refCnts for V02: refCnt = 3, refCntWtd = 3
*************** In fgLocalVarLiveness()
; Initial local variable assignments
;
; V00 arg0 int
; V01 arg1 int
; V02 arg2 ubyte
; V03 loc0 int
; V04 loc1 int
; V05 loc2 int
; V06 loc3 int
; V07 loc4 int
; V08 loc5 struct ( 8) do-not-enreg[SF] ld-addr-op
; V09 OutArgs lclBlk (40) "OutgoingArgSpace"
; V10 tmp1 int "impAppendStmt"
; V11 tmp2 ref class-hnd exact "NewObj constructor temp"
; V12 tmp3 struct ( 8) do-not-enreg[SF] ld-addr-op "Inline ldloca(s) first use temp"
; V13 tmp4 int "impAppendStmt"
; V14 tmp5 int "Inline stloc first use temp"
; V15 tmp6 int "impAppendStmt"
; V16 tmp7 int "Inlining Arg"
; V17 tmp8 int "Inlining Arg"
; V18 tmp9 int "Inlining Arg"
; V19 cse0 int "ValNumCSE"
In fgLocalVarLivenessInit
Local V08 should not be enregistered because: it is a struct
Local V12 should not be enregistered because: it is a struct
Tracked variable (15 out of 20) table:
V00 arg0 [ int]: refCnt = 9, refCntWtd = 9
V01 arg1 [ int]: refCnt = 8, refCntWtd = 8
V19 cse0 [ int]: refCnt = 8, refCntWtd = 8
V02 arg2 [ ubyte]: refCnt = 3, refCntWtd = 3
V11 tmp2 [ ref]: refCnt = 2, refCntWtd = 4
V10 tmp1 [ int]: refCnt = 2, refCntWtd = 4
V13 tmp4 [ int]: refCnt = 2, refCntWtd = 4
V15 tmp6 [ int]: refCnt = 2, refCntWtd = 4
V03 loc0 [ int]: refCnt = 2, refCntWtd = 2
V04 loc1 [ int]: refCnt = 2, refCntWtd = 2
V05 loc2 [ int]: refCnt = 2, refCntWtd = 2
V06 loc3 [ int]: refCnt = 2, refCntWtd = 2
V07 loc4 [ int]: refCnt = 2, refCntWtd = 2
V08 loc5 [struct]: refCnt = 2, refCntWtd = 2
V14 tmp5 [ int]: refCnt = 2, refCntWtd = 2
*************** In fgPerBlockLocalVarLiveness()
BB01 USE(3)={V00 V01 V02 } + ByrefExposed + GcHeap
DEF(12)={ V19 V11 V10 V13 V15 V03 V04 V05 V06 V07 V08 V14} + ByrefExposed* + GcHeap*
** Memory liveness computed, GcHeap states and ByrefExposed states match
*************** In fgInterBlockLocalVarLiveness()
BB liveness after fgLiveVarAnalysis():
BB01 IN (3)={V00 V01 V02} + ByrefExposed + GcHeap
OUT(0)={ }
*************** In fgUpdateFlowGraph()
Before updating the flow graph:
-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..051) (return) i label target gcsafe newobj LIR
-----------------------------------------------------------------------------------------------------------------------------------------
*************** In fgDebugCheckBBlist
*** lvaComputeRefCounts ***
*** lvaComputeRefCounts -- explicit counts ***
New refCnts for V02: refCnt = 1, refCntWtd = 1
New refCnts for V19: refCnt = 1, refCntWtd = 1
New refCnts for V19: refCnt = 2, refCntWtd = 2
New refCnts for V00: refCnt = 1, refCntWtd = 1
New refCnts for V01: refCnt = 1, refCntWtd = 1
New refCnts for V10: refCnt = 1, refCntWtd = 2
New refCnts for V19: refCnt = 3, refCntWtd = 3
New refCnts for V00: refCnt = 2, refCntWtd = 2
New refCnts for V01: refCnt = 2, refCntWtd = 2
New refCnts for V03: refCnt = 1, refCntWtd = 1
New refCnts for V08: refCnt = 1, refCntWtd = 1
New refCnts for V19: refCnt = 4, refCntWtd = 4
New refCnts for V08: refCnt = 2, refCntWtd = 2
New refCnts for V00: refCnt = 3, refCntWtd = 3
New refCnts for V01: refCnt = 3, refCntWtd = 3
New refCnts for V04: refCnt = 1, refCntWtd = 1
New refCnts for V11: refCnt = 1, refCntWtd = 2
New refCnts for V19: refCnt = 5, refCntWtd = 5
New refCnts for V11: refCnt = 2, refCntWtd = 4
New refCnts for V00: refCnt = 4, refCntWtd = 4
New refCnts for V01: refCnt = 4, refCntWtd = 4
New refCnts for V05: refCnt = 1, refCntWtd = 1
New refCnts for V19: refCnt = 6, refCntWtd = 6
New refCnts for V00: refCnt = 5, refCntWtd = 5
New refCnts for V01: refCnt = 5, refCntWtd = 5
New refCnts for V06: refCnt = 1, refCntWtd = 1
New refCnts for V00: refCnt = 6, refCntWtd = 6
New refCnts for V01: refCnt = 6, refCntWtd = 6
New refCnts for V13: refCnt = 1, refCntWtd = 2
New refCnts for V13: refCnt = 2, refCntWtd = 4
New refCnts for V19: refCnt = 7, refCntWtd = 7
New refCnts for V14: refCnt = 1, refCntWtd = 1
New refCnts for V00: refCnt = 7, refCntWtd = 7
New refCnts for V19: refCnt = 8, refCntWtd = 8
New refCnts for V15: refCnt = 1, refCntWtd = 2
New refCnts for V15: refCnt = 2, refCntWtd = 4
New refCnts for V14: refCnt = 2, refCntWtd = 2
New refCnts for V07: refCnt = 1, refCntWtd = 1
New refCnts for V10: refCnt = 2, refCntWtd = 4
New refCnts for V03: refCnt = 2, refCntWtd = 2
New refCnts for V04: refCnt = 2, refCntWtd = 2
New refCnts for V05: refCnt = 2, refCntWtd = 2
New refCnts for V06: refCnt = 2, refCntWtd = 2
New refCnts for V07: refCnt = 2, refCntWtd = 2
*** lvaComputeRefCounts -- implicit counts ***
New refCnts for V00: refCnt = 8, refCntWtd = 8
New refCnts for V00: refCnt = 9, refCntWtd = 9
New refCnts for V01: refCnt = 7, refCntWtd = 7
New refCnts for V01: refCnt = 8, refCntWtd = 8
New refCnts for V02: refCnt = 2, refCntWtd = 2
New refCnts for V02: refCnt = 3, refCntWtd = 3
Liveness pass finished after lowering, IR:
-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..051) (return) i label target gcsafe newobj LIR
-----------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [000..051) (return), preds={} succs={}
N004 ( 2, 2) [000002] ------------ t2 = LCL_VAR int V02 arg2 u:1 (last use) $c0
/--* t2 int
N005 ( 3, 4) [000158] ------------ t158 = * CAST int <- ubyte <- int $180
/--* t158 int
N007 ( 7, 7) [000189] DA---------- * STORE_LCL_VAR int V19 cse0
N008 ( 3, 2) [000190] ------------ t190 = LCL_VAR int V19 cse0 $180
/--* t190 int
[000199] ------------ t199 = * PUTARG_REG int REG r8
N010 ( 1, 1) [000000] ------------ t0 = LCL_VAR int V00 arg0 u:1 $80
/--* t0 int
[000200] ------------ t200 = * PUTARG_REG int REG rcx
N011 ( 1, 1) [000001] ------------ t1 = LCL_VAR int V01 arg1 u:1 $81
/--* t1 int
[000201] ------------ t201 = * PUTARG_REG int REG rdx
/--* t199 int arg2 in r8
+--* t200 int arg0 in rcx
+--* t201 int arg1 in rdx
N012 ( 26, 19) [000003] --CXG------- t3 = * CALL int Test2.DoTestImpl1 $143
/--* t3 int
N014 ( 26, 19) [000011] DA-XG------- * STORE_LCL_VAR int V10 tmp1 d:2
N005 ( 3, 2) [000192] ------------ t192 = LCL_VAR int V19 cse0 $180
/--* t192 int
[000202] ------------ t202 = * PUTARG_REG int REG r9
N006 ( 1, 1) [000005] ------------ t5 = LCL_VAR int V00 arg0 u:1 $80
/--* t5 int
[000203] ------------ t203 = * PUTARG_REG int REG rdx
N007 ( 1, 1) [000006] ------------ t6 = LCL_VAR int V01 arg1 u:1 $81
/--* t6 int
[000204] ------------ t204 = * PUTARG_REG int REG r8
N008 ( 3, 10) [000009] ------------ t9 = CNS_INT(h) long 0xd1ffab1e method $240
/--* t9 long
[000205] ------------ t205 = * PUTARG_REG long REG rcx
/--* t202 int arg3 in r9
+--* t203 int arg1 in rdx
+--* t204 int arg2 in r8
+--* t205 long arg0 in rcx
N009 ( 22, 23) [000008] --CXG------- t8 = * CALL int Test2.DoTestImpl2 $148
/--* t8 int
N011 ( 26, 26) [000015] DA-XG------- * STORE_LCL_VAR int V03 loc0 d:2
N001 ( 1, 1) [000018] -c---------- t18 = CNS_INT int 0 $40
N002 ( 3, 2) [000016] Dc-----N---- t16 = LCL_VAR_ADDR byref V08 loc5 d:2
/--* t16 byref
+--* t18 int
[000198] -A---------- * STOREIND byte
N005 ( 3, 2) [000193] ------------ t193 = LCL_VAR int V19 cse0 $180
/--* t193 int
[000206] ------------ t206 = * PUTARG_REG int REG r9
N006 ( 4, 5) [000020] ------------ t20 = LCL_FLD byte V08 loc5 u:2[+0] (last use) $301
/--* t20 byte
[000207] ------------ t207 = * PUTARG_REG int REG rcx
N007 ( 1, 1) [000021] ------------ t21 = LCL_VAR int V00 arg0 u:1 $80
/--* t21 int
[000208] ------------ t208 = * PUTARG_REG int REG rdx
N008 ( 1, 1) [000022] ------------ t22 = LCL_VAR int V01 arg1 u:1 $81
/--* t22 int
[000209] ------------ t209 = * PUTARG_REG int REG r8
/--* t206 int arg3 in r9
+--* t207 int arg0 in rcx
+--* t208 int arg1 in rdx
+--* t209 int arg2 in r8
N009 ( 23, 18) [000024] --CXG------- t24 = * CALL int Test2.DoTestImpl3 $14d
/--* t24 int
N011 ( 27, 21) [000029] DA-XG------- * STORE_LCL_VAR int V04 loc1 d:2
N002 ( 3, 10) [000030] ------------ t30 = CNS_INT(h) long 0xd1ffab1e method $241
/--* t30 long
[000210] ------------ t210 = * PUTARG_REG long REG rcx
/--* t210 long arg0 in rcx
N003 ( 17, 16) [000031] --C--------- t31 = * CALL help ref HELPER.CORINFO_HELP_NEWSFAST $340
/--* t31 ref
N005 ( 17, 16) [000033] DA---------- * STORE_LCL_VAR ref V11 tmp2 d:2
N005 ( 3, 2) [000194] ------------ t194 = LCL_VAR int V19 cse0 $180
/--* t194 int
[000211] ------------ * PUTARG_STK [+0x20] void
N006 ( 1, 1) [000036] ------------ t36 = LCL_VAR ref V11 tmp2 u:2 (last use) $340
/--* t36 ref
[000212] ------------ t212 = * PUTARG_REG ref REG rdx
N007 ( 1, 1) [000037] ------------ t37 = LCL_VAR int V00 arg0 u:1 $80
/--* t37 int
[000213] ------------ t213 = * PUTARG_REG int REG r8
N008 ( 1, 1) [000038] ------------ t38 = LCL_VAR int V01 arg1 u:1 $81
/--* t38 int
[000214] ------------ t214 = * PUTARG_REG int REG r9
N009 ( 3, 10) [000041] ------------ t41 = CNS_INT(h) long 0xd1ffab1e method $242
/--* t41 long
[000215] ------------ t215 = * PUTARG_REG long REG rcx
/--* t212 ref arg1 in rdx
+--* t213 int arg2 in r8
+--* t214 int arg3 in r9
+--* t215 long arg0 in rcx
N010 ( 26, 24) [000040] --CXG------- t40 = * CALL int Test2.DoTestImpl4 $151
/--* t40 int
N012 ( 30, 27) [000044] DA-XG------- * STORE_LCL_VAR int V05 loc2 d:2
N004 ( 3, 2) [000195] ------------ t195 = LCL_VAR int V19 cse0 $180
/--* t195 int
[000216] ------------ t216 = * PUTARG_REG int REG r8
N005 ( 1, 1) [000045] ------------ t45 = LCL_VAR int V00 arg0 u:1 $80
/--* t45 int
[000217] ------------ t217 = * PUTARG_REG int REG rcx
N006 ( 1, 1) [000046] ------------ t46 = LCL_VAR int V01 arg1 u:1 $81
/--* t46 int
[000218] ------------ t218 = * PUTARG_REG int REG rdx
/--* t216 int arg2 in r8
+--* t217 int arg0 in rcx
+--* t218 int arg1 in rdx
N007 ( 19, 12) [000048] --CXG------- t48 = * CALL int Test2.DoTestImpl5 $156
/--* t48 int
N009 ( 23, 15) [000051] DA-XG------- * STORE_LCL_VAR int V06 loc3 d:2
N001 ( 1, 1) [000052] ------------ t52 = LCL_VAR int V00 arg0 u:1 $80
N002 ( 1, 1) [000053] ------------ t53 = LCL_VAR int V01 arg1 u:1 (last use) $81
/--* t52 int
+--* t53 int
N003 ( 3, 3) [000140] ------------ t140 = * ADD int $181
/--* t140 int
N005 ( 3, 3) [000114] DA---------- * STORE_LCL_VAR int V13 tmp4 d:2
N001 ( 1, 1) [000115] ------------ t115 = LCL_VAR int V13 tmp4 u:2 (last use) $181
N002 ( 3, 2) [000196] ------------ t196 = LCL_VAR int V19 cse0 $180
/--* t115 int
+--* t196 int
N003 ( 8, 6) [000145] ------------ t145 = * MUL int $182
/--* t145 int
N005 ( 8, 6) [000120] DA---------- * STORE_LCL_VAR int V14 tmp5 d:2
N001 ( 1, 1) [000121] ------------ t121 = LCL_VAR int V00 arg0 u:1 (last use) $80
N002 ( 3, 2) [000197] ------------ t197 = LCL_VAR int V19 cse0 (last use) $180
/--* t121 int
+--* t197 int
N003 ( 8, 6) [000150] ------------ t150 = * MUL int $183
/--* t150 int
N005 ( 8, 6) [000131] DA---------- * STORE_LCL_VAR int V15 tmp6 d:2
N001 ( 1, 1) [000132] ------------ t132 = LCL_VAR int V15 tmp6 u:2 (last use) $183
N002 ( 1, 1) [000127] ------------ t127 = LCL_VAR int V14 tmp5 u:2 (last use) $182
N003 ( 1, 1) [000152] -c---------- t152 = CNS_INT int 2 $42
/--* t127 int
+--* t152 int
N004 ( 3, 3) [000153] ------------ t153 = * RSH int $184
/--* t132 int
+--* t153 int
N005 ( 24, 7) [000156] ---X-------- t156 = * DIV int $186
/--* t156 int
N007 ( 28, 10) [000058] DA-X-------- * STORE_LCL_VAR int V07 loc4 d:2
N001 ( 1, 1) [000012] ------------ t12 = LCL_VAR int V10 tmp1 u:2 (last use) $143
N002 ( 3, 2) [000059] ------------ t59 = LCL_VAR int V03 loc0 u:2 (last use) $148
/--* t12 int
+--* t59 int
N003 ( 5, 4) [000060] ------------ t60 = * ADD int $187
N004 ( 3, 2) [000061] ------------ t61 = LCL_VAR int V04 loc1 u:2 (last use) $14d
/--* t60 int
+--* t61 int
N005 ( 9, 7) [000062] ------------ t62 = * ADD int $188
N006 ( 3, 2) [000063] ------------ t63 = LCL_VAR int V05 loc2 u:2 (last use) $151
/--* t62 int
+--* t63 int
N007 ( 13, 10) [000064] ------------ t64 = * ADD int $189
N008 ( 3, 2) [000065] ------------ t65 = LCL_VAR int V06 loc3 u:2 (last use) $156
/--* t64 int
+--* t65 int
N009 ( 17, 13) [000066] ------------ t66 = * ADD int $18a
N010 ( 3, 2) [000067] ------------ t67 = LCL_VAR int V07 loc4 u:2 (last use) $185
/--* t66 int
+--* t67 int
N011 ( 21, 16) [000068] ------------ t68 = * ADD int $18b
/--* t68 int
N012 ( 22, 17) [000069] ------------ * RETURN int $15c
-------------------------------------------------------------------------------------------------------------------
*************** Exiting Lowering
Trees after Lowering
-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..051) (return) i label target gcsafe newobj LIR
-----------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [000..051) (return), preds={} succs={}
N004 ( 2, 2) [000002] ------------ t2 = LCL_VAR int V02 arg2 u:1 (last use) $c0
/--* t2 int
N005 ( 3, 4) [000158] ------------ t158 = * CAST int <- ubyte <- int $180
/--* t158 int
N007 ( 7, 7) [000189] DA---------- * STORE_LCL_VAR int V19 cse0
N008 ( 3, 2) [000190] ------------ t190 = LCL_VAR int V19 cse0 $180
/--* t190 int
[000199] ------------ t199 = * PUTARG_REG int REG r8
N010 ( 1, 1) [000000] ------------ t0 = LCL_VAR int V00 arg0 u:1 $80
/--* t0 int
[000200] ------------ t200 = * PUTARG_REG int REG rcx
N011 ( 1, 1) [000001] ------------ t1 = LCL_VAR int V01 arg1 u:1 $81
/--* t1 int
[000201] ------------ t201 = * PUTARG_REG int REG rdx
/--* t199 int arg2 in r8
+--* t200 int arg0 in rcx
+--* t201 int arg1 in rdx
N012 ( 26, 19) [000003] --CXG------- t3 = * CALL int Test2.DoTestImpl1 $143
/--* t3 int
N014 ( 26, 19) [000011] DA-XG------- * STORE_LCL_VAR int V10 tmp1 d:2
N005 ( 3, 2) [000192] ------------ t192 = LCL_VAR int V19 cse0 $180
/--* t192 int
[000202] ------------ t202 = * PUTARG_REG int REG r9
N006 ( 1, 1) [000005] ------------ t5 = LCL_VAR int V00 arg0 u:1 $80
/--* t5 int
[000203] ------------ t203 = * PUTARG_REG int REG rdx
N007 ( 1, 1) [000006] ------------ t6 = LCL_VAR int V01 arg1 u:1 $81
/--* t6 int
[000204] ------------ t204 = * PUTARG_REG int REG r8
N008 ( 3, 10) [000009] ------------ t9 = CNS_INT(h) long 0xd1ffab1e method $240
/--* t9 long
[000205] ------------ t205 = * PUTARG_REG long REG rcx
/--* t202 int arg3 in r9
+--* t203 int arg1 in rdx
+--* t204 int arg2 in r8
+--* t205 long arg0 in rcx
N009 ( 22, 23) [000008] --CXG------- t8 = * CALL int Test2.DoTestImpl2 $148
/--* t8 int
N011 ( 26, 26) [000015] DA-XG------- * STORE_LCL_VAR int V03 loc0 d:2
N001 ( 1, 1) [000018] -c---------- t18 = CNS_INT int 0 $40
N002 ( 3, 2) [000016] Dc-----N---- t16 = LCL_VAR_ADDR byref V08 loc5 d:2
/--* t16 byref
+--* t18 int
[000198] -A---------- * STOREIND byte
N005 ( 3, 2) [000193] ------------ t193 = LCL_VAR int V19 cse0 $180
/--* t193 int
[000206] ------------ t206 = * PUTARG_REG int REG r9
N006 ( 4, 5) [000020] ------------ t20 = LCL_FLD byte V08 loc5 u:2[+0] (last use) $301
/--* t20 byte
[000207] ------------ t207 = * PUTARG_REG int REG rcx
N007 ( 1, 1) [000021] ------------ t21 = LCL_VAR int V00 arg0 u:1 $80
/--* t21 int
[000208] ------------ t208 = * PUTARG_REG int REG rdx
N008 ( 1, 1) [000022] ------------ t22 = LCL_VAR int V01 arg1 u:1 $81
/--* t22 int
[000209] ------------ t209 = * PUTARG_REG int REG r8
/--* t206 int arg3 in r9
+--* t207 int arg0 in rcx
+--* t208 int arg1 in rdx
+--* t209 int arg2 in r8
N009 ( 23, 18) [000024] --CXG------- t24 = * CALL int Test2.DoTestImpl3 $14d
/--* t24 int
N011 ( 27, 21) [000029] DA-XG------- * STORE_LCL_VAR int V04 loc1 d:2
N002 ( 3, 10) [000030] ------------ t30 = CNS_INT(h) long 0xd1ffab1e method $241
/--* t30 long
[000210] ------------ t210 = * PUTARG_REG long REG rcx
/--* t210 long arg0 in rcx
N003 ( 17, 16) [000031] --C--------- t31 = * CALL help ref HELPER.CORINFO_HELP_NEWSFAST $340
/--* t31 ref
N005 ( 17, 16) [000033] DA---------- * STORE_LCL_VAR ref V11 tmp2 d:2
N005 ( 3, 2) [000194] ------------ t194 = LCL_VAR int V19 cse0 $180
/--* t194 int
[000211] ------------ * PUTARG_STK [+0x20] void
N006 ( 1, 1) [000036] ------------ t36 = LCL_VAR ref V11 tmp2 u:2 (last use) $340
/--* t36 ref
[000212] ------------ t212 = * PUTARG_REG ref REG rdx
N007 ( 1, 1) [000037] ------------ t37 = LCL_VAR int V00 arg0 u:1 $80
/--* t37 int
[000213] ------------ t213 = * PUTARG_REG int REG r8
N008 ( 1, 1) [000038] ------------ t38 = LCL_VAR int V01 arg1 u:1 $81
/--* t38 int
[000214] ------------ t214 = * PUTARG_REG int REG r9
N009 ( 3, 10) [000041] ------------ t41 = CNS_INT(h) long 0xd1ffab1e method $242
/--* t41 long
[000215] ------------ t215 = * PUTARG_REG long REG rcx
/--* t212 ref arg1 in rdx
+--* t213 int arg2 in r8
+--* t214 int arg3 in r9
+--* t215 long arg0 in rcx
N010 ( 26, 24) [000040] --CXG------- t40 = * CALL int Test2.DoTestImpl4 $151
/--* t40 int
N012 ( 30, 27) [000044] DA-XG------- * STORE_LCL_VAR int V05 loc2 d:2
N004 ( 3, 2) [000195] ------------ t195 = LCL_VAR int V19 cse0 $180
/--* t195 int
[000216] ------------ t216 = * PUTARG_REG int REG r8
N005 ( 1, 1) [000045] ------------ t45 = LCL_VAR int V00 arg0 u:1 $80
/--* t45 int
[000217] ------------ t217 = * PUTARG_REG int REG rcx
N006 ( 1, 1) [000046] ------------ t46 = LCL_VAR int V01 arg1 u:1 $81
/--* t46 int
[000218] ------------ t218 = * PUTARG_REG int REG rdx
/--* t216 int arg2 in r8
+--* t217 int arg0 in rcx
+--* t218 int arg1 in rdx
N007 ( 19, 12) [000048] --CXG------- t48 = * CALL int Test2.DoTestImpl5 $156
/--* t48 int
N009 ( 23, 15) [000051] DA-XG------- * STORE_LCL_VAR int V06 loc3 d:2
N001 ( 1, 1) [000052] ------------ t52 = LCL_VAR int V00 arg0 u:1 $80
N002 ( 1, 1) [000053] ------------ t53 = LCL_VAR int V01 arg1 u:1 (last use) $81
/--* t52 int
+--* t53 int
N003 ( 3, 3) [000140] ------------ t140 = * ADD int $181
/--* t140 int
N005 ( 3, 3) [000114] DA---------- * STORE_LCL_VAR int V13 tmp4 d:2
N001 ( 1, 1) [000115] ------------ t115 = LCL_VAR int V13 tmp4 u:2 (last use) $181
N002 ( 3, 2) [000196] ------------ t196 = LCL_VAR int V19 cse0 $180
/--* t115 int
+--* t196 int
N003 ( 8, 6) [000145] ------------ t145 = * MUL int $182
/--* t145 int
N005 ( 8, 6) [000120] DA---------- * STORE_LCL_VAR int V14 tmp5 d:2
N001 ( 1, 1) [000121] ------------ t121 = LCL_VAR int V00 arg0 u:1 (last use) $80
N002 ( 3, 2) [000197] ------------ t197 = LCL_VAR int V19 cse0 (last use) $180
/--* t121 int
+--* t197 int
N003 ( 8, 6) [000150] ------------ t150 = * MUL int $183
/--* t150 int
N005 ( 8, 6) [000131] DA---------- * STORE_LCL_VAR int V15 tmp6 d:2
N001 ( 1, 1) [000132] ------------ t132 = LCL_VAR int V15 tmp6 u:2 (last use) $183
N002 ( 1, 1) [000127] ------------ t127 = LCL_VAR int V14 tmp5 u:2 (last use) $182
N003 ( 1, 1) [000152] -c---------- t152 = CNS_INT int 2 $42
/--* t127 int
+--* t152 int
N004 ( 3, 3) [000153] ------------ t153 = * RSH int $184
/--* t132 int
+--* t153 int
N005 ( 24, 7) [000156] ---X-------- t156 = * DIV int $186
/--* t156 int
N007 ( 28, 10) [000058] DA-X-------- * STORE_LCL_VAR int V07 loc4 d:2
N001 ( 1, 1) [000012] ------------ t12 = LCL_VAR int V10 tmp1 u:2 (last use) $143
N002 ( 3, 2) [000059] ------------ t59 = LCL_VAR int V03 loc0 u:2 (last use) $148
/--* t12 int
+--* t59 int
N003 ( 5, 4) [000060] ------------ t60 = * ADD int $187
N004 ( 3, 2) [000061] ------------ t61 = LCL_VAR int V04 loc1 u:2 (last use) $14d
/--* t60 int
+--* t61 int
N005 ( 9, 7) [000062] ------------ t62 = * ADD int $188
N006 ( 3, 2) [000063] ------------ t63 = LCL_VAR int V05 loc2 u:2 (last use) $151
/--* t62 int
+--* t63 int
N007 ( 13, 10) [000064] ------------ t64 = * ADD int $189
N008 ( 3, 2) [000065] ------------ t65 = LCL_VAR int V06 loc3 u:2 (last use) $156
/--* t64 int
+--* t65 int
N009 ( 17, 13) [000066] ------------ t66 = * ADD int $18a
N010 ( 3, 2) [000067] ------------ t67 = LCL_VAR int V07 loc4 u:2 (last use) $185
/--* t66 int
+--* t67 int
N011 ( 21, 16) [000068] ------------ t68 = * ADD int $18b
/--* t68 int
N012 ( 22, 17) [000069] ------------ * RETURN int $15c
-------------------------------------------------------------------------------------------------------------------
*************** In fgDebugCheckBBlist
*************** In StackLevelSetter
Trees before StackLevelSetter
-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..051) (return) i label target gcsafe newobj LIR
-----------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [000..051) (return), preds={} succs={}
N004 ( 2, 2) [000002] ------------ t2 = LCL_VAR int V02 arg2 u:1 (last use) $c0
/--* t2 int
N005 ( 3, 4) [000158] ------------ t158 = * CAST int <- ubyte <- int $180
/--* t158 int
N007 ( 7, 7) [000189] DA---------- * STORE_LCL_VAR int V19 cse0
N008 ( 3, 2) [000190] ------------ t190 = LCL_VAR int V19 cse0 $180
/--* t190 int
[000199] ------------ t199 = * PUTARG_REG int REG r8
N010 ( 1, 1) [000000] ------------ t0 = LCL_VAR int V00 arg0 u:1 $80
/--* t0 int
[000200] ------------ t200 = * PUTARG_REG int REG rcx
N011 ( 1, 1) [000001] ------------ t1 = LCL_VAR int V01 arg1 u:1 $81
/--* t1 int
[000201] ------------ t201 = * PUTARG_REG int REG rdx
/--* t199 int arg2 in r8
+--* t200 int arg0 in rcx
+--* t201 int arg1 in rdx
N012 ( 26, 19) [000003] --CXG------- t3 = * CALL int Test2.DoTestImpl1 $143
/--* t3 int
N014 ( 26, 19) [000011] DA-XG------- * STORE_LCL_VAR int V10 tmp1 d:2
N005 ( 3, 2) [000192] ------------ t192 = LCL_VAR int V19 cse0 $180
/--* t192 int
[000202] ------------ t202 = * PUTARG_REG int REG r9
N006 ( 1, 1) [000005] ------------ t5 = LCL_VAR int V00 arg0 u:1 $80
/--* t5 int
[000203] ------------ t203 = * PUTARG_REG int REG rdx
N007 ( 1, 1) [000006] ------------ t6 = LCL_VAR int V01 arg1 u:1 $81
/--* t6 int
[000204] ------------ t204 = * PUTARG_REG int REG r8
N008 ( 3, 10) [000009] ------------ t9 = CNS_INT(h) long 0xd1ffab1e method $240
/--* t9 long
[000205] ------------ t205 = * PUTARG_REG long REG rcx
/--* t202 int arg3 in r9
+--* t203 int arg1 in rdx
+--* t204 int arg2 in r8
+--* t205 long arg0 in rcx
N009 ( 22, 23) [000008] --CXG------- t8 = * CALL int Test2.DoTestImpl2 $148
/--* t8 int
N011 ( 26, 26) [000015] DA-XG------- * STORE_LCL_VAR int V03 loc0 d:2
N001 ( 1, 1) [000018] -c---------- t18 = CNS_INT int 0 $40
N002 ( 3, 2) [000016] Dc-----N---- t16 = LCL_VAR_ADDR byref V08 loc5 d:2
/--* t16 byref
+--* t18 int
[000198] -A---------- * STOREIND byte
N005 ( 3, 2) [000193] ------------ t193 = LCL_VAR int V19 cse0 $180
/--* t193 int
[000206] ------------ t206 = * PUTARG_REG int REG r9
N006 ( 4, 5) [000020] ------------ t20 = LCL_FLD byte V08 loc5 u:2[+0] (last use) $301
/--* t20 byte
[000207] ------------ t207 = * PUTARG_REG int REG rcx
N007 ( 1, 1) [000021] ------------ t21 = LCL_VAR int V00 arg0 u:1 $80
/--* t21 int
[000208] ------------ t208 = * PUTARG_REG int REG rdx
N008 ( 1, 1) [000022] ------------ t22 = LCL_VAR int V01 arg1 u:1 $81
/--* t22 int
[000209] ------------ t209 = * PUTARG_REG int REG r8
/--* t206 int arg3 in r9
+--* t207 int arg0 in rcx
+--* t208 int arg1 in rdx
+--* t209 int arg2 in r8
N009 ( 23, 18) [000024] --CXG------- t24 = * CALL int Test2.DoTestImpl3 $14d
/--* t24 int
N011 ( 27, 21) [000029] DA-XG------- * STORE_LCL_VAR int V04 loc1 d:2
N002 ( 3, 10) [000030] ------------ t30 = CNS_INT(h) long 0xd1ffab1e method $241
/--* t30 long
[000210] ------------ t210 = * PUTARG_REG long REG rcx
/--* t210 long arg0 in rcx
N003 ( 17, 16) [000031] --C--------- t31 = * CALL help ref HELPER.CORINFO_HELP_NEWSFAST $340
/--* t31 ref
N005 ( 17, 16) [000033] DA---------- * STORE_LCL_VAR ref V11 tmp2 d:2
N005 ( 3, 2) [000194] ------------ t194 = LCL_VAR int V19 cse0 $180
/--* t194 int
[000211] ------------ * PUTARG_STK [+0x20] void
N006 ( 1, 1) [000036] ------------ t36 = LCL_VAR ref V11 tmp2 u:2 (last use) $340
/--* t36 ref
[000212] ------------ t212 = * PUTARG_REG ref REG rdx
N007 ( 1, 1) [000037] ------------ t37 = LCL_VAR int V00 arg0 u:1 $80
/--* t37 int
[000213] ------------ t213 = * PUTARG_REG int REG r8
N008 ( 1, 1) [000038] ------------ t38 = LCL_VAR int V01 arg1 u:1 $81
/--* t38 int
[000214] ------------ t214 = * PUTARG_REG int REG r9
N009 ( 3, 10) [000041] ------------ t41 = CNS_INT(h) long 0xd1ffab1e method $242
/--* t41 long
[000215] ------------ t215 = * PUTARG_REG long REG rcx
/--* t212 ref arg1 in rdx
+--* t213 int arg2 in r8
+--* t214 int arg3 in r9
+--* t215 long arg0 in rcx
N010 ( 26, 24) [000040] --CXG------- t40 = * CALL int Test2.DoTestImpl4 $151
/--* t40 int
N012 ( 30, 27) [000044] DA-XG------- * STORE_LCL_VAR int V05 loc2 d:2
N004 ( 3, 2) [000195] ------------ t195 = LCL_VAR int V19 cse0 $180
/--* t195 int
[000216] ------------ t216 = * PUTARG_REG int REG r8
N005 ( 1, 1) [000045] ------------ t45 = LCL_VAR int V00 arg0 u:1 $80
/--* t45 int
[000217] ------------ t217 = * PUTARG_REG int REG rcx
N006 ( 1, 1) [000046] ------------ t46 = LCL_VAR int V01 arg1 u:1 $81
/--* t46 int
[000218] ------------ t218 = * PUTARG_REG int REG rdx
/--* t216 int arg2 in r8
+--* t217 int arg0 in rcx
+--* t218 int arg1 in rdx
N007 ( 19, 12) [000048] --CXG------- t48 = * CALL int Test2.DoTestImpl5 $156
/--* t48 int
N009 ( 23, 15) [000051] DA-XG------- * STORE_LCL_VAR int V06 loc3 d:2
N001 ( 1, 1) [000052] ------------ t52 = LCL_VAR int V00 arg0 u:1 $80
N002 ( 1, 1) [000053] ------------ t53 = LCL_VAR int V01 arg1 u:1 (last use) $81
/--* t52 int
+--* t53 int
N003 ( 3, 3) [000140] ------------ t140 = * ADD int $181
/--* t140 int
N005 ( 3, 3) [000114] DA---------- * STORE_LCL_VAR int V13 tmp4 d:2
N001 ( 1, 1) [000115] ------------ t115 = LCL_VAR int V13 tmp4 u:2 (last use) $181
N002 ( 3, 2) [000196] ------------ t196 = LCL_VAR int V19 cse0 $180
/--* t115 int
+--* t196 int
N003 ( 8, 6) [000145] ------------ t145 = * MUL int $182
/--* t145 int
N005 ( 8, 6) [000120] DA---------- * STORE_LCL_VAR int V14 tmp5 d:2
N001 ( 1, 1) [000121] ------------ t121 = LCL_VAR int V00 arg0 u:1 (last use) $80
N002 ( 3, 2) [000197] ------------ t197 = LCL_VAR int V19 cse0 (last use) $180
/--* t121 int
+--* t197 int
N003 ( 8, 6) [000150] ------------ t150 = * MUL int $183
/--* t150 int
N005 ( 8, 6) [000131] DA---------- * STORE_LCL_VAR int V15 tmp6 d:2
N001 ( 1, 1) [000132] ------------ t132 = LCL_VAR int V15 tmp6 u:2 (last use) $183
N002 ( 1, 1) [000127] ------------ t127 = LCL_VAR int V14 tmp5 u:2 (last use) $182
N003 ( 1, 1) [000152] -c---------- t152 = CNS_INT int 2 $42
/--* t127 int
+--* t152 int
N004 ( 3, 3) [000153] ------------ t153 = * RSH int $184
/--* t132 int
+--* t153 int
N005 ( 24, 7) [000156] ---X-------- t156 = * DIV int $186
/--* t156 int
N007 ( 28, 10) [000058] DA-X-------- * STORE_LCL_VAR int V07 loc4 d:2
N001 ( 1, 1) [000012] ------------ t12 = LCL_VAR int V10 tmp1 u:2 (last use) $143
N002 ( 3, 2) [000059] ------------ t59 = LCL_VAR int V03 loc0 u:2 (last use) $148
/--* t12 int
+--* t59 int
N003 ( 5, 4) [000060] ------------ t60 = * ADD int $187
N004 ( 3, 2) [000061] ------------ t61 = LCL_VAR int V04 loc1 u:2 (last use) $14d
/--* t60 int
+--* t61 int
N005 ( 9, 7) [000062] ------------ t62 = * ADD int $188
N006 ( 3, 2) [000063] ------------ t63 = LCL_VAR int V05 loc2 u:2 (last use) $151
/--* t62 int
+--* t63 int
N007 ( 13, 10) [000064] ------------ t64 = * ADD int $189
N008 ( 3, 2) [000065] ------------ t65 = LCL_VAR int V06 loc3 u:2 (last use) $156
/--* t64 int
+--* t65 int
N009 ( 17, 13) [000066] ------------ t66 = * ADD int $18a
N010 ( 3, 2) [000067] ------------ t67 = LCL_VAR int V07 loc4 u:2 (last use) $185
/--* t66 int
+--* t67 int
N011 ( 21, 16) [000068] ------------ t68 = * ADD int $18b
/--* t68 int
N012 ( 22, 17) [000069] ------------ * RETURN int $15c
-------------------------------------------------------------------------------------------------------------------
*************** Exiting StackLevelSetter
Trees after StackLevelSetter
-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..051) (return) i label target gcsafe newobj LIR
-----------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [000..051) (return), preds={} succs={}
N004 ( 2, 2) [000002] ------------ t2 = LCL_VAR int V02 arg2 u:1 (last use) $c0
/--* t2 int
N005 ( 3, 4) [000158] ------------ t158 = * CAST int <- ubyte <- int $180
/--* t158 int
N007 ( 7, 7) [000189] DA---------- * STORE_LCL_VAR int V19 cse0
N008 ( 3, 2) [000190] ------------ t190 = LCL_VAR int V19 cse0 $180
/--* t190 int
[000199] ------------ t199 = * PUTARG_REG int REG r8
N010 ( 1, 1) [000000] ------------ t0 = LCL_VAR int V00 arg0 u:1 $80
/--* t0 int
[000200] ------------ t200 = * PUTARG_REG int REG rcx
N011 ( 1, 1) [000001] ------------ t1 = LCL_VAR int V01 arg1 u:1 $81
/--* t1 int
[000201] ------------ t201 = * PUTARG_REG int REG rdx
/--* t199 int arg2 in r8
+--* t200 int arg0 in rcx
+--* t201 int arg1 in rdx
N012 ( 26, 19) [000003] --CXG------- t3 = * CALL int Test2.DoTestImpl1 $143
/--* t3 int
N014 ( 26, 19) [000011] DA-XG------- * STORE_LCL_VAR int V10 tmp1 d:2
N005 ( 3, 2) [000192] ------------ t192 = LCL_VAR int V19 cse0 $180
/--* t192 int
[000202] ------------ t202 = * PUTARG_REG int REG r9
N006 ( 1, 1) [000005] ------------ t5 = LCL_VAR int V00 arg0 u:1 $80
/--* t5 int
[000203] ------------ t203 = * PUTARG_REG int REG rdx
N007 ( 1, 1) [000006] ------------ t6 = LCL_VAR int V01 arg1 u:1 $81
/--* t6 int
[000204] ------------ t204 = * PUTARG_REG int REG r8
N008 ( 3, 10) [000009] ------------ t9 = CNS_INT(h) long 0xd1ffab1e method $240
/--* t9 long
[000205] ------------ t205 = * PUTARG_REG long REG rcx
/--* t202 int arg3 in r9
+--* t203 int arg1 in rdx
+--* t204 int arg2 in r8
+--* t205 long arg0 in rcx
N009 ( 22, 23) [000008] --CXG------- t8 = * CALL int Test2.DoTestImpl2 $148
/--* t8 int
N011 ( 26, 26) [000015] DA-XG------- * STORE_LCL_VAR int V03 loc0 d:2
N001 ( 1, 1) [000018] -c---------- t18 = CNS_INT int 0 $40
N002 ( 3, 2) [000016] Dc-----N---- t16 = LCL_VAR_ADDR byref V08 loc5 d:2
/--* t16 byref
+--* t18 int
[000198] -A---------- * STOREIND byte
N005 ( 3, 2) [000193] ------------ t193 = LCL_VAR int V19 cse0 $180
/--* t193 int
[000206] ------------ t206 = * PUTARG_REG int REG r9
N006 ( 4, 5) [000020] ------------ t20 = LCL_FLD byte V08 loc5 u:2[+0] (last use) $301
/--* t20 byte
[000207] ------------ t207 = * PUTARG_REG int REG rcx
N007 ( 1, 1) [000021] ------------ t21 = LCL_VAR int V00 arg0 u:1 $80
/--* t21 int
[000208] ------------ t208 = * PUTARG_REG int REG rdx
N008 ( 1, 1) [000022] ------------ t22 = LCL_VAR int V01 arg1 u:1 $81
/--* t22 int
[000209] ------------ t209 = * PUTARG_REG int REG r8
/--* t206 int arg3 in r9
+--* t207 int arg0 in rcx
+--* t208 int arg1 in rdx
+--* t209 int arg2 in r8
N009 ( 23, 18) [000024] --CXG------- t24 = * CALL int Test2.DoTestImpl3 $14d
/--* t24 int
N011 ( 27, 21) [000029] DA-XG------- * STORE_LCL_VAR int V04 loc1 d:2
N002 ( 3, 10) [000030] ------------ t30 = CNS_INT(h) long 0xd1ffab1e method $241
/--* t30 long
[000210] ------------ t210 = * PUTARG_REG long REG rcx
/--* t210 long arg0 in rcx
N003 ( 17, 16) [000031] --C--------- t31 = * CALL help ref HELPER.CORINFO_HELP_NEWSFAST $340
/--* t31 ref
N005 ( 17, 16) [000033] DA---------- * STORE_LCL_VAR ref V11 tmp2 d:2
N005 ( 3, 2) [000194] ------------ t194 = LCL_VAR int V19 cse0 $180
/--* t194 int
[000211] ------------ * PUTARG_STK [+0x20] void
N006 ( 1, 1) [000036] ------------ t36 = LCL_VAR ref V11 tmp2 u:2 (last use) $340
/--* t36 ref
[000212] ------------ t212 = * PUTARG_REG ref REG rdx
N007 ( 1, 1) [000037] ------------ t37 = LCL_VAR int V00 arg0 u:1 $80
/--* t37 int
[000213] ------------ t213 = * PUTARG_REG int REG r8
N008 ( 1, 1) [000038] ------------ t38 = LCL_VAR int V01 arg1 u:1 $81
/--* t38 int
[000214] ------------ t214 = * PUTARG_REG int REG r9
N009 ( 3, 10) [000041] ------------ t41 = CNS_INT(h) long 0xd1ffab1e method $242
/--* t41 long
[000215] ------------ t215 = * PUTARG_REG long REG rcx
/--* t212 ref arg1 in rdx
+--* t213 int arg2 in r8
+--* t214 int arg3 in r9
+--* t215 long arg0 in rcx
N010 ( 26, 24) [000040] --CXG------- t40 = * CALL int Test2.DoTestImpl4 $151
/--* t40 int
N012 ( 30, 27) [000044] DA-XG------- * STORE_LCL_VAR int V05 loc2 d:2
N004 ( 3, 2) [000195] ------------ t195 = LCL_VAR int V19 cse0 $180
/--* t195 int
[000216] ------------ t216 = * PUTARG_REG int REG r8
N005 ( 1, 1) [000045] ------------ t45 = LCL_VAR int V00 arg0 u:1 $80
/--* t45 int
[000217] ------------ t217 = * PUTARG_REG int REG rcx
N006 ( 1, 1) [000046] ------------ t46 = LCL_VAR int V01 arg1 u:1 $81
/--* t46 int
[000218] ------------ t218 = * PUTARG_REG int REG rdx
/--* t216 int arg2 in r8
+--* t217 int arg0 in rcx
+--* t218 int arg1 in rdx
N007 ( 19, 12) [000048] --CXG------- t48 = * CALL int Test2.DoTestImpl5 $156
/--* t48 int
N009 ( 23, 15) [000051] DA-XG------- * STORE_LCL_VAR int V06 loc3 d:2
N001 ( 1, 1) [000052] ------------ t52 = LCL_VAR int V00 arg0 u:1 $80
N002 ( 1, 1) [000053] ------------ t53 = LCL_VAR int V01 arg1 u:1 (last use) $81
/--* t52 int
+--* t53 int
N003 ( 3, 3) [000140] ------------ t140 = * ADD int $181
/--* t140 int
N005 ( 3, 3) [000114] DA---------- * STORE_LCL_VAR int V13 tmp4 d:2
N001 ( 1, 1) [000115] ------------ t115 = LCL_VAR int V13 tmp4 u:2 (last use) $181
N002 ( 3, 2) [000196] ------------ t196 = LCL_VAR int V19 cse0 $180
/--* t115 int
+--* t196 int
N003 ( 8, 6) [000145] ------------ t145 = * MUL int $182
/--* t145 int
N005 ( 8, 6) [000120] DA---------- * STORE_LCL_VAR int V14 tmp5 d:2
N001 ( 1, 1) [000121] ------------ t121 = LCL_VAR int V00 arg0 u:1 (last use) $80
N002 ( 3, 2) [000197] ------------ t197 = LCL_VAR int V19 cse0 (last use) $180
/--* t121 int
+--* t197 int
N003 ( 8, 6) [000150] ------------ t150 = * MUL int $183
/--* t150 int
N005 ( 8, 6) [000131] DA---------- * STORE_LCL_VAR int V15 tmp6 d:2
N001 ( 1, 1) [000132] ------------ t132 = LCL_VAR int V15 tmp6 u:2 (last use) $183
N002 ( 1, 1) [000127] ------------ t127 = LCL_VAR int V14 tmp5 u:2 (last use) $182
N003 ( 1, 1) [000152] -c---------- t152 = CNS_INT int 2 $42
/--* t127 int
+--* t152 int
N004 ( 3, 3) [000153] ------------ t153 = * RSH int $184
/--* t132 int
+--* t153 int
N005 ( 24, 7) [000156] ---X-------- t156 = * DIV int $186
/--* t156 int
N007 ( 28, 10) [000058] DA-X-------- * STORE_LCL_VAR int V07 loc4 d:2
N001 ( 1, 1) [000012] ------------ t12 = LCL_VAR int V10 tmp1 u:2 (last use) $143
N002 ( 3, 2) [000059] ------------ t59 = LCL_VAR int V03 loc0 u:2 (last use) $148
/--* t12 int
+--* t59 int
N003 ( 5, 4) [000060] ------------ t60 = * ADD int $187
N004 ( 3, 2) [000061] ------------ t61 = LCL_VAR int V04 loc1 u:2 (last use) $14d
/--* t60 int
+--* t61 int
N005 ( 9, 7) [000062] ------------ t62 = * ADD int $188
N006 ( 3, 2) [000063] ------------ t63 = LCL_VAR int V05 loc2 u:2 (last use) $151
/--* t62 int
+--* t63 int
N007 ( 13, 10) [000064] ------------ t64 = * ADD int $189
N008 ( 3, 2) [000065] ------------ t65 = LCL_VAR int V06 loc3 u:2 (last use) $156
/--* t64 int
+--* t65 int
N009 ( 17, 13) [000066] ------------ t66 = * ADD int $18a
N010 ( 3, 2) [000067] ------------ t67 = LCL_VAR int V07 loc4 u:2 (last use) $185
/--* t66 int
+--* t67 int
N011 ( 21, 16) [000068] ------------ t68 = * ADD int $18b
/--* t68 int
N012 ( 22, 17) [000069] ------------ * RETURN int $15c
-------------------------------------------------------------------------------------------------------------------
*************** In fgDebugCheckBBlist
Clearing modified regs.
buildIntervals ========
-----------------
LIVENESS:
-----------------
BB01 use def in out
{V00 V01 V02}
{V03 V04 V05 V06 V07 V08 V10 V11 V13 V14 V15 V19}
{V00 V01 V02}
{}
Interval 0: int RefPositions {} physReg:NA Preferences=[allInt]
Interval 1: int RefPositions {} physReg:NA Preferences=[allInt]
Interval 2: int RefPositions {} physReg:NA Preferences=[allInt]
Interval 3: int RefPositions {} physReg:NA Preferences=[allInt]
Interval 4: int RefPositions {} physReg:NA Preferences=[allInt]
Interval 5: int RefPositions {} physReg:NA Preferences=[allInt]
Interval 6: int RefPositions {} physReg:NA Preferences=[allInt]
Interval 7: int RefPositions {} physReg:NA Preferences=[allInt]
Local V08 should not be enregistered because: it is a struct
Interval 8: int RefPositions {} physReg:NA Preferences=[allInt]
Interval 9: ref RefPositions {} physReg:NA Preferences=[allInt]
Interval 10: int RefPositions {} physReg:NA Preferences=[allInt]
Interval 11: int RefPositions {} physReg:NA Preferences=[allInt]
Interval 12: int RefPositions {} physReg:NA Preferences=[allInt]
Interval 13: int RefPositions {} physReg:NA Preferences=[allInt]
FP callee save candidate vars: None
floatVarCount = 0; hasLoops = 0, singleExit = 1
TUPLE STYLE DUMP BEFORE LSRA
LSRA Block Sequence: BB01( 1 )
BB01 [000..051) (return), preds={} succs={}
=====
N004. V02(t2*)
N005. t158 = CAST ; t2*
N007. V19(t189); t158
N008. V19(t190)
N000. t199 = PUTARG_REG; t190
N010. V00(t0)
N000. t200 = PUTARG_REG; t0
N011. V01(t1)
N000. t201 = PUTARG_REG; t1
N012. t3 = CALL ; t199,t200,t201
N014. V10(t11); t3
N005. V19(t192)
N000. t202 = PUTARG_REG; t192
N006. V00(t5)
N000. t203 = PUTARG_REG; t5
N007. V01(t6)
N000. t204 = PUTARG_REG; t6
N008. t9 = CNS_INT(h) 0xd1ffab1e method
N000. t205 = PUTARG_REG; t9
N009. t8 = CALL ; t202,t203,t204,t205
N011. V03(t15); t8
N001. CNS_INT 0
N002. LCL_VAR_ADDR V08 loc5 d:2
N000. STOREIND
N005. V19(t193)
N000. t206 = PUTARG_REG; t193
N006. t20* = V08 MEM
N000. t207 = PUTARG_REG; t20*
N007. V00(t21)
N000. t208 = PUTARG_REG; t21
N008. V01(t22)
N000. t209 = PUTARG_REG; t22
N009. t24 = CALL ; t206,t207,t208,t209
N011. V04(t29); t24
N002. t30 = CNS_INT(h) 0xd1ffab1e method
N000. t210 = PUTARG_REG; t30
N003. t31 = CALL help; t210
N005. V11(t33); t31
N005. V19(t194)
N000. PUTARG_STK [+0x20]; t194
N006. V11(t36*)
N000. t212 = PUTARG_REG; t36*
N007. V00(t37)
N000. t213 = PUTARG_REG; t37
N008. V01(t38)
N000. t214 = PUTARG_REG; t38
N009. t41 = CNS_INT(h) 0xd1ffab1e method
N000. t215 = PUTARG_REG; t41
N010. t40 = CALL ; t212,t213,t214,t215
N012. V05(t44); t40
N004. V19(t195)
N000. t216 = PUTARG_REG; t195
N005. V00(t45)
N000. t217 = PUTARG_REG; t45
N006. V01(t46)
N000. t218 = PUTARG_REG; t46
N007. t48 = CALL ; t216,t217,t218
N009. V06(t51); t48
N001. V00(t52)
N002. V01(t53*)
N003. t140 = ADD ; t52,t53*
N005. V13(t114); t140
N001. V13(t115*)
N002. V19(t196)
N003. t145 = MUL ; t115*,t196
N005. V14(t120); t145
N001. V00(t121*)
N002. V19(t197*)
N003. t150 = MUL ; t121*,t197*
N005. V15(t131); t150
N001. V15(t132*)
N002. V14(t127*)
N003. CNS_INT 2
N004. t153 = RSH ; t127*
N005. t156 = DIV ; t132*,t153
N007. V07(t58); t156
N001. V10(t12*)
N002. V03(t59*)
N003. t60 = ADD ; t12*,t59*
N004. V04(t61*)
N005. t62 = ADD ; t60,t61*
N006. V05(t63*)
N007. t64 = ADD ; t62,t63*
N008. V06(t65*)
N009. t66 = ADD ; t64,t65*
N010. V07(t67*)
N011. t68 = ADD ; t66,t67*
N012. RETURN ; t68
buildIntervals second part ========
Int arg V00 in reg rcx
<RefPosition #0 @0 RefTypeParamDef <Ivl:0 V00> BB00 regmask=[rcx] minReg=1 fixed>
Int arg V01 in reg rdx
<RefPosition #1 @0 RefTypeParamDef <Ivl:1 V01> BB00 regmask=[rdx] minReg=1 fixed>
Int arg V02 in reg r8
<RefPosition #2 @0 RefTypeParamDef <Ivl:2 V02> BB00 regmask=[r8] minReg=1 fixed>
NEW BLOCK BB01
<RefPosition #3 @1 RefTypeBB BB01 regmask=[] minReg=1>
DefList: { }
N003 ( 2, 2) [000002] ------------ * LCL_VAR int V02 arg2 u:1 NA (last use) REG NA $c0
DefList: { }
N005 ( 3, 4) [000158] ------------ * CAST int <- ubyte <- int REG NA $180
<RefPosition #4 @5 RefTypeUse <Ivl:2 V02> LCL_VAR BB01 regmask=[allInt] minReg=1 last>
Interval 14: int RefPositions {} physReg:NA Preferences=[allInt]
<RefPosition #5 @6 RefTypeDef <Ivl:14> CAST BB01 regmask=[allInt] minReg=1>
DefList: { N005.t158. CAST }
N007 ( 7, 7) [000189] DA---------- * STORE_LCL_VAR int V19 cse0 NA REG NA
<RefPosition #6 @7 RefTypeUse <Ivl:14> BB01 regmask=[allInt] minReg=1 last>
Assigning related <V19/L13> to <I14>
<RefPosition #7 @8 RefTypeDef <Ivl:13 V19> STORE_LCL_VAR BB01 regmask=[allInt] minReg=1 last>
DefList: { }
N009 ( 3, 2) [000190] ------------ * LCL_VAR int V19 cse0 NA REG NA $180
DefList: { }
N011 (???,???) [000199] ------------ * PUTARG_REG int REG r8
<RefPosition #8 @11 RefTypeFixedReg <Reg:r8 > BB01 regmask=[r8] minReg=1>
<RefPosition #9 @11 RefTypeUse <Ivl:13 V19> LCL_VAR BB01 regmask=[r8] minReg=1 last fixed>
Setting putarg_reg as a pass-through of a non-last use lclVar
Interval 15: int RefPositions {} physReg:NA Preferences=[allInt]
<RefPosition #10 @12 RefTypeFixedReg <Reg:r8 > BB01 regmask=[r8] minReg=1>
<RefPosition #11 @12 RefTypeDef <Ivl:15> PUTARG_REG BB01 regmask=[r8] minReg=1 fixed>
Assigning related <V19/L13> to <I15>
DefList: { N011.t199. PUTARG_REG }
N013 ( 1, 1) [000000] ------------ * LCL_VAR int V00 arg0 u:1 NA REG NA $80
DefList: { N011.t199. PUTARG_REG }
N015 (???,???) [000200] ------------ * PUTARG_REG int REG rcx
<RefPosition #12 @15 RefTypeFixedReg <Reg:rcx> BB01 regmask=[rcx] minReg=1>
<RefPosition #13 @15 RefTypeUse <Ivl:0 V00> LCL_VAR BB01 regmask=[rcx] minReg=1 last fixed>
Setting putarg_reg as a pass-through of a non-last use lclVar
Interval 16: int RefPositions {} physReg:NA Preferences=[allInt]
<RefPosition #14 @16 RefTypeFixedReg <Reg:rcx> BB01 regmask=[rcx] minReg=1>
<RefPosition #15 @16 RefTypeDef <Ivl:16> PUTARG_REG BB01 regmask=[rcx] minReg=1 fixed>
Assigning related <V00/L0> to <I16>
DefList: { N011.t199. PUTARG_REG; N015.t200. PUTARG_REG }
N017 ( 1, 1) [000001] ------------ * LCL_VAR int V01 arg1 u:1 NA REG NA $81
DefList: { N011.t199. PUTARG_REG; N015.t200. PUTARG_REG }
N019 (???,???) [000201] ------------ * PUTARG_REG int REG rdx
<RefPosition #16 @19 RefTypeFixedReg <Reg:rdx> BB01 regmask=[rdx] minReg=1>
<RefPosition #17 @19 RefTypeUse <Ivl:1 V01> LCL_VAR BB01 regmask=[rdx] minReg=1 last fixed>
Setting putarg_reg as a pass-through of a non-last use lclVar
Interval 17: int RefPositions {} physReg:NA Preferences=[allInt]
<RefPosition #18 @20 RefTypeFixedReg <Reg:rdx> BB01 regmask=[rdx] minReg=1>
<RefPosition #19 @20 RefTypeDef <Ivl:17> PUTARG_REG BB01 regmask=[rdx] minReg=1 fixed>
Assigning related <V01/L1> to <I17>
DefList: { N011.t199. PUTARG_REG; N015.t200. PUTARG_REG; N019.t201. PUTARG_REG }
N021 ( 26, 19) [000003] --CXG------- * CALL int Test2.DoTestImpl1 REG NA $143
<RefPosition #20 @21 RefTypeFixedReg <Reg:r8 > BB01 regmask=[r8] minReg=1>
<RefPosition #21 @21 RefTypeUse <Ivl:15> BB01 regmask=[r8] minReg=1 last fixed>
<RefPosition #22 @21 RefTypeFixedReg <Reg:rcx> BB01 regmask=[rcx] minReg=1>
<RefPosition #23 @21 RefTypeUse <Ivl:16> BB01 regmask=[rcx] minReg=1 last fixed>
<RefPosition #24 @21 RefTypeFixedReg <Reg:rdx> BB01 regmask=[rdx] minReg=1>
<RefPosition #25 @21 RefTypeUse <Ivl:17> BB01 regmask=[rdx] minReg=1 last fixed>
<RefPosition #26 @22 RefTypeKill <Reg:rax> BB01 regmask=[rax] minReg=1>
<RefPosition #27 @22 RefTypeKill <Reg:rcx> BB01 regmask=[rcx] minReg=1>
<RefPosition #28 @22 RefTypeKill <Reg:rdx> BB01 regmask=[rdx] minReg=1>
<RefPosition #29 @22 RefTypeKill <Reg:r8 > BB01 regmask=[r8] minReg=1>
<RefPosition #30 @22 RefTypeKill <Reg:r9 > BB01 regmask=[r9] minReg=1>
<RefPosition #31 @22 RefTypeKill <Reg:r10> BB01 regmask=[r10] minReg=1>
<RefPosition #32 @22 RefTypeKill <Reg:r11> BB01 regmask=[r11] minReg=1>
Interval 18: int RefPositions {} physReg:NA Preferences=[allInt]
<RefPosition #33 @22 RefTypeFixedReg <Reg:rax> BB01 regmask=[rax] minReg=1>
<RefPosition #34 @22 RefTypeDef <Ivl:18> CALL BB01 regmask=[rax] minReg=1 fixed>
DefList: { N021.t3. CALL }
N023 ( 26, 19) [000011] DA-XG------- * STORE_LCL_VAR int V10 tmp1 d:2 NA REG NA
<RefPosition #35 @23 RefTypeUse <Ivl:18> BB01 regmask=[allInt] minReg=1 last>
Assigning related <V10/L8> to <I18>
<RefPosition #36 @24 RefTypeDef <Ivl:8 V10> STORE_LCL_VAR BB01 regmask=[allInt] minReg=1 last>
DefList: { }
N025 ( 3, 2) [000192] ------------ * LCL_VAR int V19 cse0 NA REG NA $180
DefList: { }
N027 (???,???) [000202] ------------ * PUTARG_REG int REG r9
<RefPosition #37 @27 RefTypeFixedReg <Reg:r9 > BB01 regmask=[r9] minReg=1>
<RefPosition #38 @27 RefTypeUse <Ivl:13 V19> LCL_VAR BB01 regmask=[r9] minReg=1 last fixed>
Setting putarg_reg as a pass-through of a non-last use lclVar
Interval 19: int RefPositions {} physReg:NA Preferences=[allInt]
<RefPosition #39 @28 RefTypeFixedReg <Reg:r9 > BB01 regmask=[r9] minReg=1>
<RefPosition #40 @28 RefTypeDef <Ivl:19> PUTARG_REG BB01 regmask=[r9] minReg=1 fixed>
Assigning related <V19/L13> to <I19>
DefList: { N027.t202. PUTARG_REG }
N029 ( 1, 1) [000005] ------------ * LCL_VAR int V00 arg0 u:1 NA REG NA $80
DefList: { N027.t202. PUTARG_REG }
N031 (???,???) [000203] ------------ * PUTARG_REG int REG rdx
<RefPosition #41 @31 RefTypeFixedReg <Reg:rdx> BB01 regmask=[rdx] minReg=1>
<RefPosition #42 @31 RefTypeUse <Ivl:0 V00> LCL_VAR BB01 regmask=[rdx] minReg=1 last fixed>
Setting putarg_reg as a pass-through of a non-last use lclVar
Interval 20: int RefPositions {} physReg:NA Preferences=[allInt]
<RefPosition #43 @32 RefTypeFixedReg <Reg:rdx> BB01 regmask=[rdx] minReg=1>
<RefPosition #44 @32 RefTypeDef <Ivl:20> PUTARG_REG BB01 regmask=[rdx] minReg=1 fixed>
Assigning related <V00/L0> to <I20>
DefList: { N027.t202. PUTARG_REG; N031.t203. PUTARG_REG }
N033 ( 1, 1) [000006] ------------ * LCL_VAR int V01 arg1 u:1 NA REG NA $81
DefList: { N027.t202. PUTARG_REG; N031.t203. PUTARG_REG }
N035 (???,???) [000204] ------------ * PUTARG_REG int REG r8
<RefPosition #45 @35 RefTypeFixedReg <Reg:r8 > BB01 regmask=[r8] minReg=1>
<RefPosition #46 @35 RefTypeUse <Ivl:1 V01> LCL_VAR BB01 regmask=[r8] minReg=1 last fixed>
Setting putarg_reg as a pass-through of a non-last use lclVar
Interval 21: int RefPositions {} physReg:NA Preferences=[allInt]
<RefPosition #47 @36 RefTypeFixedReg <Reg:r8 > BB01 regmask=[r8] minReg=1>
<RefPosition #48 @36 RefTypeDef <Ivl:21> PUTARG_REG BB01 regmask=[r8] minReg=1 fixed>
Assigning related <V01/L1> to <I21>
DefList: { N027.t202. PUTARG_REG; N031.t203. PUTARG_REG; N035.t204. PUTARG_REG }
N037 ( 3, 10) [000009] ------------ * CNS_INT(h) long 0xd1ffab1e method REG NA $240
Interval 22: long RefPositions {} physReg:NA Preferences=[allInt]
<RefPosition #49 @38 RefTypeDef <Ivl:22> CNS_INT BB01 regmask=[allInt] minReg=1>
DefList: { N027.t202. PUTARG_REG; N031.t203. PUTARG_REG; N035.t204. PUTARG_REG; N037.t9. CNS_INT }
N039 (???,???) [000205] ------------ * PUTARG_REG long REG rcx
<RefPosition #50 @39 RefTypeFixedReg <Reg:rcx> BB01 regmask=[rcx] minReg=1>
<RefPosition #51 @39 RefTypeUse <Ivl:22> BB01 regmask=[rcx] minReg=1 last fixed>
Interval 23: long RefPositions {} physReg:NA Preferences=[allInt]
<RefPosition #52 @40 RefTypeFixedReg <Reg:rcx> BB01 regmask=[rcx] minReg=1>
<RefPosition #53 @40 RefTypeDef <Ivl:23> PUTARG_REG BB01 regmask=[rcx] minReg=1 fixed>
DefList: { N027.t202. PUTARG_REG; N031.t203. PUTARG_REG; N035.t204. PUTARG_REG; N039.t205. PUTARG_REG }
N041 ( 22, 23) [000008] --CXG------- * CALL int Test2.DoTestImpl2 REG NA $148
<RefPosition #54 @41 RefTypeFixedReg <Reg:r9 > BB01 regmask=[r9] minReg=1>
<RefPosition #55 @41 RefTypeUse <Ivl:19> BB01 regmask=[r9] minReg=1 last fixed>
<RefPosition #56 @41 RefTypeFixedReg <Reg:rdx> BB01 regmask=[rdx] minReg=1>
<RefPosition #57 @41 RefTypeUse <Ivl:20> BB01 regmask=[rdx] minReg=1 last fixed>
<RefPosition #58 @41 RefTypeFixedReg <Reg:r8 > BB01 regmask=[r8] minReg=1>
<RefPosition #59 @41 RefTypeUse <Ivl:21> BB01 regmask=[r8] minReg=1 last fixed>
<RefPosition #60 @41 RefTypeFixedReg <Reg:rcx> BB01 regmask=[rcx] minReg=1>
<RefPosition #61 @41 RefTypeUse <Ivl:23> BB01 regmask=[rcx] minReg=1 last fixed>
<RefPosition #62 @42 RefTypeKill <Reg:rax> BB01 regmask=[rax] minReg=1>
<RefPosition #63 @42 RefTypeKill <Reg:rcx> BB01 regmask=[rcx] minReg=1>
<RefPosition #64 @42 RefTypeKill <Reg:rdx> BB01 regmask=[rdx] minReg=1>
<RefPosition #65 @42 RefTypeKill <Reg:r8 > BB01 regmask=[r8] minReg=1>
<RefPosition #66 @42 RefTypeKill <Reg:r9 > BB01 regmask=[r9] minReg=1>
<RefPosition #67 @42 RefTypeKill <Reg:r10> BB01 regmask=[r10] minReg=1>
<RefPosition #68 @42 RefTypeKill <Reg:r11> BB01 regmask=[r11] minReg=1>
Interval 24: int RefPositions {} physReg:NA Preferences=[allInt]
<RefPosition #69 @42 RefTypeFixedReg <Reg:rax> BB01 regmask=[rax] minReg=1>
<RefPosition #70 @42 RefTypeDef <Ivl:24> CALL BB01 regmask=[rax] minReg=1 fixed>
DefList: { N041.t8. CALL }
N043 ( 26, 26) [000015] DA-XG------- * STORE_LCL_VAR int V03 loc0 d:2 NA REG NA
<RefPosition #71 @43 RefTypeUse <Ivl:24> BB01 regmask=[allInt] minReg=1 last>
Assigning related <V03/L3> to <I24>
<RefPosition #72 @44 RefTypeDef <Ivl:3 V03> STORE_LCL_VAR BB01 regmask=[allInt] minReg=1 last>
DefList: { }
N045 ( 1, 1) [000018] -c---------- * CNS_INT int 0 REG NA $40
Contained
DefList: { }
N047 ( 3, 2) [000016] Dc-----N---- * LCL_VAR_ADDR byref V08 loc5 d:2 NA REG NA
Contained
DefList: { }
N049 (???,???) [000198] -A---------- * STOREIND byte REG NA
DefList: { }
N051 ( 3, 2) [000193] ------------ * LCL_VAR int V19 cse0 NA REG NA $180
DefList: { }
N053 (???,???) [000206] ------------ * PUTARG_REG int REG r9
<RefPosition #73 @53 RefTypeFixedReg <Reg:r9 > BB01 regmask=[r9] minReg=1>
<RefPosition #74 @53 RefTypeUse <Ivl:13 V19> LCL_VAR BB01 regmask=[r9] minReg=1 last fixed>
Setting putarg_reg as a pass-through of a non-last use lclVar
Interval 25: int RefPositions {} physReg:NA Preferences=[allInt]
<RefPosition #75 @54 RefTypeFixedReg <Reg:r9 > BB01 regmask=[r9] minReg=1>
<RefPosition #76 @54 RefTypeDef <Ivl:25> PUTARG_REG BB01 regmask=[r9] minReg=1 fixed>
Assigning related <V19/L13> to <I25>
DefList: { N053.t206. PUTARG_REG }
N055 ( 4, 5) [000020] ------------ * LCL_FLD byte V08 loc5 u:2[+0] NA (last use) REG NA $301
Interval 26: byte RefPositions {} physReg:NA Preferences=[allInt]
<RefPosition #77 @56 RefTypeDef <Ivl:26> LCL_FLD BB01 regmask=[allInt] minReg=1>
DefList: { N053.t206. PUTARG_REG; N055.t20. LCL_FLD }
N057 (???,???) [000207] ------------ * PUTARG_REG int REG rcx
<RefPosition #78 @57 RefTypeFixedReg <Reg:rcx> BB01 regmask=[rcx] minReg=1>
<RefPosition #79 @57 RefTypeUse <Ivl:26> BB01 regmask=[rcx] minReg=1 last fixed>
Interval 27: int RefPositions {} physReg:NA Preferences=[allInt]
<RefPosition #80 @58 RefTypeFixedReg <Reg:rcx> BB01 regmask=[rcx] minReg=1>
<RefPosition #81 @58 RefTypeDef <Ivl:27> PUTARG_REG BB01 regmask=[rcx] minReg=1 fixed>
DefList: { N053.t206. PUTARG_REG; N057.t207. PUTARG_REG }
N059 ( 1, 1) [000021] ------------ * LCL_VAR int V00 arg0 u:1 NA REG NA $80
DefList: { N053.t206. PUTARG_REG; N057.t207. PUTARG_REG }
N061 (???,???) [000208] ------------ * PUTARG_REG int REG rdx
<RefPosition #82 @61 RefTypeFixedReg <Reg:rdx> BB01 regmask=[rdx] minReg=1>
<RefPosition #83 @61 RefTypeUse <Ivl:0 V00> LCL_VAR BB01 regmask=[rdx] minReg=1 last fixed>
Setting putarg_reg as a pass-through of a non-last use lclVar
Interval 28: int RefPositions {} physReg:NA Preferences=[allInt]
<RefPosition #84 @62 RefTypeFixedReg <Reg:rdx> BB01 regmask=[rdx] minReg=1>
<RefPosition #85 @62 RefTypeDef <Ivl:28> PUTARG_REG BB01 regmask=[rdx] minReg=1 fixed>
Assigning related <V00/L0> to <I28>
DefList: { N053.t206. PUTARG_REG; N057.t207. PUTARG_REG; N061.t208. PUTARG_REG }
N063 ( 1, 1) [000022] ------------ * LCL_VAR int V01 arg1 u:1 NA REG NA $81
DefList: { N053.t206. PUTARG_REG; N057.t207. PUTARG_REG; N061.t208. PUTARG_REG }
N065 (???,???) [000209] ------------ * PUTARG_REG int REG r8
<RefPosition #86 @65 RefTypeFixedReg <Reg:r8 > BB01 regmask=[r8] minReg=1>
<RefPosition #87 @65 RefTypeUse <Ivl:1 V01> LCL_VAR BB01 regmask=[r8] minReg=1 last fixed>
Setting putarg_reg as a pass-through of a non-last use lclVar
Interval 29: int RefPositions {} physReg:NA Preferences=[allInt]
<RefPosition #88 @66 RefTypeFixedReg <Reg:r8 > BB01 regmask=[r8] minReg=1>
<RefPosition #89 @66 RefTypeDef <Ivl:29> PUTARG_REG BB01 regmask=[r8] minReg=1 fixed>
Assigning related <V01/L1> to <I29>
DefList: { N053.t206. PUTARG_REG; N057.t207. PUTARG_REG; N061.t208. PUTARG_REG; N065.t209. PUTARG_REG }
N067 ( 23, 18) [000024] --CXG------- * CALL int Test2.DoTestImpl3 REG NA $14d
<RefPosition #90 @67 RefTypeFixedReg <Reg:r9 > BB01 regmask=[r9] minReg=1>
<RefPosition #91 @67 RefTypeUse <Ivl:25> BB01 regmask=[r9] minReg=1 last fixed>
<RefPosition #92 @67 RefTypeFixedReg <Reg:rcx> BB01 regmask=[rcx] minReg=1>
<RefPosition #93 @67 RefTypeUse <Ivl:27> BB01 regmask=[rcx] minReg=1 last fixed>
<RefPosition #94 @67 RefTypeFixedReg <Reg:rdx> BB01 regmask=[rdx] minReg=1>
<RefPosition #95 @67 RefTypeUse <Ivl:28> BB01 regmask=[rdx] minReg=1 last fixed>
<RefPosition #96 @67 RefTypeFixedReg <Reg:r8 > BB01 regmask=[r8] minReg=1>
<RefPosition #97 @67 RefTypeUse <Ivl:29> BB01 regmask=[r8] minReg=1 last fixed>
<RefPosition #98 @68 RefTypeKill <Reg:rax> BB01 regmask=[rax] minReg=1>
<RefPosition #99 @68 RefTypeKill <Reg:rcx> BB01 regmask=[rcx] minReg=1>
<RefPosition #100 @68 RefTypeKill <Reg:rdx> BB01 regmask=[rdx] minReg=1>
<RefPosition #101 @68 RefTypeKill <Reg:r8 > BB01 regmask=[r8] minReg=1>
<RefPosition #102 @68 RefTypeKill <Reg:r9 > BB01 regmask=[r9] minReg=1>
<RefPosition #103 @68 RefTypeKill <Reg:r10> BB01 regmask=[r10] minReg=1>
<RefPosition #104 @68 RefTypeKill <Reg:r11> BB01 regmask=[r11] minReg=1>
Interval 30: int RefPositions {} physReg:NA Preferences=[allInt]
<RefPosition #105 @68 RefTypeFixedReg <Reg:rax> BB01 regmask=[rax] minReg=1>
<RefPosition #106 @68 RefTypeDef <Ivl:30> CALL BB01 regmask=[rax] minReg=1 fixed>
DefList: { N067.t24. CALL }
N069 ( 27, 21) [000029] DA-XG------- * STORE_LCL_VAR int V04 loc1 d:2 NA REG NA
<RefPosition #107 @69 RefTypeUse <Ivl:30> BB01 regmask=[allInt] minReg=1 last>
Assigning related <V04/L4> to <I30>
<RefPosition #108 @70 RefTypeDef <Ivl:4 V04> STORE_LCL_VAR BB01 regmask=[allInt] minReg=1 last>
DefList: { }
N071 ( 3, 10) [000030] ------------ * CNS_INT(h) long 0xd1ffab1e method REG NA $241
Interval 31: long RefPositions {} physReg:NA Preferences=[allInt]
<RefPosition #109 @72 RefTypeDef <Ivl:31> CNS_INT BB01 regmask=[allInt] minReg=1>
DefList: { N071.t30. CNS_INT }
N073 (???,???) [000210] ------------ * PUTARG_REG long REG rcx
<RefPosition #110 @73 RefTypeFixedReg <Reg:rcx> BB01 regmask=[rcx] minReg=1>
<RefPosition #111 @73 RefTypeUse <Ivl:31> BB01 regmask=[rcx] minReg=1 last fixed>
Interval 32: long RefPositions {} physReg:NA Preferences=[allInt]
<RefPosition #112 @74 RefTypeFixedReg <Reg:rcx> BB01 regmask=[rcx] minReg=1>
<RefPosition #113 @74 RefTypeDef <Ivl:32> PUTARG_REG BB01 regmask=[rcx] minReg=1 fixed>
DefList: { N073.t210. PUTARG_REG }
N075 ( 17, 16) [000031] --C--------- * CALL help ref HELPER.CORINFO_HELP_NEWSFAST REG NA $340
<RefPosition #114 @75 RefTypeFixedReg <Reg:rcx> BB01 regmask=[rcx] minReg=1>
<RefPosition #115 @75 RefTypeUse <Ivl:32> BB01 regmask=[rcx] minReg=1 last fixed>
<RefPosition #116 @76 RefTypeKill <Reg:rax> BB01 regmask=[rax] minReg=1>
<RefPosition #117 @76 RefTypeKill <Reg:rcx> BB01 regmask=[rcx] minReg=1>
<RefPosition #118 @76 RefTypeKill <Reg:rdx> BB01 regmask=[rdx] minReg=1>
<RefPosition #119 @76 RefTypeKill <Reg:r8 > BB01 regmask=[r8] minReg=1>
<RefPosition #120 @76 RefTypeKill <Reg:r9 > BB01 regmask=[r9] minReg=1>
<RefPosition #121 @76 RefTypeKill <Reg:r10> BB01 regmask=[r10] minReg=1>
<RefPosition #122 @76 RefTypeKill <Reg:r11> BB01 regmask=[r11] minReg=1>
Interval 33: ref RefPositions {} physReg:NA Preferences=[allInt]
<RefPosition #123 @76 RefTypeFixedReg <Reg:rax> BB01 regmask=[rax] minReg=1>
<RefPosition #124 @76 RefTypeDef <Ivl:33> CALL BB01 regmask=[rax] minReg=1 fixed>
DefList: { N075.t31. CALL }
N077 ( 17, 16) [000033] DA---------- * STORE_LCL_VAR ref V11 tmp2 d:2 NA REG NA
<RefPosition #125 @77 RefTypeUse <Ivl:33> BB01 regmask=[allInt] minReg=1 last>
Assigning related <V11/L9> to <I33>
<RefPosition #126 @78 RefTypeDef <Ivl:9 V11> STORE_LCL_VAR BB01 regmask=[allInt] minReg=1 last>
DefList: { }
N079 ( 3, 2) [000194] ------------ * LCL_VAR int V19 cse0 NA REG NA $180
DefList: { }
N081 (???,???) [000211] ------------ * PUTARG_STK [+0x20] void REG NA
<RefPosition #127 @81 RefTypeUse <Ivl:13 V19> LCL_VAR BB01 regmask=[allInt] minReg=1 last>
DefList: { }
N083 ( 1, 1) [000036] ------------ * LCL_VAR ref V11 tmp2 u:2 NA (last use) REG NA $340
DefList: { }
N085 (???,???) [000212] ------------ * PUTARG_REG ref REG rdx
<RefPosition #128 @85 RefTypeFixedReg <Reg:rdx> BB01 regmask=[rdx] minReg=1>
<RefPosition #129 @85 RefTypeUse <Ivl:9 V11> LCL_VAR BB01 regmask=[rdx] minReg=1 last fixed>
Interval 34: ref RefPositions {} physReg:NA Preferences=[allInt]
<RefPosition #130 @86 RefTypeFixedReg <Reg:rdx> BB01 regmask=[rdx] minReg=1>
<RefPosition #131 @86 RefTypeDef <Ivl:34> PUTARG_REG BB01 regmask=[rdx] minReg=1 fixed>
DefList: { N085.t212. PUTARG_REG }
N087 ( 1, 1) [000037] ------------ * LCL_VAR int V00 arg0 u:1 NA REG NA $80
DefList: { N085.t212. PUTARG_REG }
N089 (???,???) [000213] ------------ * PUTARG_REG int REG r8
<RefPosition #132 @89 RefTypeFixedReg <Reg:r8 > BB01 regmask=[r8] minReg=1>
<RefPosition #133 @89 RefTypeUse <Ivl:0 V00> LCL_VAR BB01 regmask=[r8] minReg=1 last fixed>
Setting putarg_reg as a pass-through of a non-last use lclVar
Interval 35: int RefPositions {} physReg:NA Preferences=[allInt]
<RefPosition #134 @90 RefTypeFixedReg <Reg:r8 > BB01 regmask=[r8] minReg=1>
<RefPosition #135 @90 RefTypeDef <Ivl:35> PUTARG_REG BB01 regmask=[r8] minReg=1 fixed>
Assigning related <V00/L0> to <I35>
DefList: { N085.t212. PUTARG_REG; N089.t213. PUTARG_REG }
N091 ( 1, 1) [000038] ------------ * LCL_VAR int V01 arg1 u:1 NA REG NA $81
DefList: { N085.t212. PUTARG_REG; N089.t213. PUTARG_REG }
N093 (???,???) [000214] ------------ * PUTARG_REG int REG r9
<RefPosition #136 @93 RefTypeFixedReg <Reg:r9 > BB01 regmask=[r9] minReg=1>
<RefPosition #137 @93 RefTypeUse <Ivl:1 V01> LCL_VAR BB01 regmask=[r9] minReg=1 last fixed>
Setting putarg_reg as a pass-through of a non-last use lclVar
Interval 36: int RefPositions {} physReg:NA Preferences=[allInt]
<RefPosition #138 @94 RefTypeFixedReg <Reg:r9 > BB01 regmask=[r9] minReg=1>
<RefPosition #139 @94 RefTypeDef <Ivl:36> PUTARG_REG BB01 regmask=[r9] minReg=1 fixed>
Assigning related <V01/L1> to <I36>
DefList: { N085.t212. PUTARG_REG; N089.t213. PUTARG_REG; N093.t214. PUTARG_REG }
N095 ( 3, 10) [000041] ------------ * CNS_INT(h) long 0xd1ffab1e method REG NA $242
Interval 37: long RefPositions {} physReg:NA Preferences=[allInt]
<RefPosition #140 @96 RefTypeDef <Ivl:37> CNS_INT BB01 regmask=[allInt] minReg=1>
DefList: { N085.t212. PUTARG_REG; N089.t213. PUTARG_REG; N093.t214. PUTARG_REG; N095.t41. CNS_INT }
N097 (???,???) [000215] ------------ * PUTARG_REG long REG rcx
<RefPosition #141 @97 RefTypeFixedReg <Reg:rcx> BB01 regmask=[rcx] minReg=1>
<RefPosition #142 @97 RefTypeUse <Ivl:37> BB01 regmask=[rcx] minReg=1 last fixed>
Interval 38: long RefPositions {} physReg:NA Preferences=[allInt]
<RefPosition #143 @98 RefTypeFixedReg <Reg:rcx> BB01 regmask=[rcx] minReg=1>
<RefPosition #144 @98 RefTypeDef <Ivl:38> PUTARG_REG BB01 regmask=[rcx] minReg=1 fixed>
DefList: { N085.t212. PUTARG_REG; N089.t213. PUTARG_REG; N093.t214. PUTARG_REG; N097.t215. PUTARG_REG }
N099 ( 26, 24) [000040] --CXG------- * CALL int Test2.DoTestImpl4 REG NA $151
<RefPosition #145 @99 RefTypeFixedReg <Reg:rdx> BB01 regmask=[rdx] minReg=1>
<RefPosition #146 @99 RefTypeUse <Ivl:34> BB01 regmask=[rdx] minReg=1 last fixed>
<RefPosition #147 @99 RefTypeFixedReg <Reg:r8 > BB01 regmask=[r8] minReg=1>
<RefPosition #148 @99 RefTypeUse <Ivl:35> BB01 regmask=[r8] minReg=1 last fixed>
<RefPosition #149 @99 RefTypeFixedReg <Reg:r9 > BB01 regmask=[r9] minReg=1>
<RefPosition #150 @99 RefTypeUse <Ivl:36> BB01 regmask=[r9] minReg=1 last fixed>
<RefPosition #151 @99 RefTypeFixedReg <Reg:rcx> BB01 regmask=[rcx] minReg=1>
<RefPosition #152 @99 RefTypeUse <Ivl:38> BB01 regmask=[rcx] minReg=1 last fixed>
<RefPosition #153 @100 RefTypeKill <Reg:rax> BB01 regmask=[rax] minReg=1>
<RefPosition #154 @100 RefTypeKill <Reg:rcx> BB01 regmask=[rcx] minReg=1>
<RefPosition #155 @100 RefTypeKill <Reg:rdx> BB01 regmask=[rdx] minReg=1>
<RefPosition #156 @100 RefTypeKill <Reg:r8 > BB01 regmask=[r8] minReg=1>
<RefPosition #157 @100 RefTypeKill <Reg:r9 > BB01 regmask=[r9] minReg=1>
<RefPosition #158 @100 RefTypeKill <Reg:r10> BB01 regmask=[r10] minReg=1>
<RefPosition #159 @100 RefTypeKill <Reg:r11> BB01 regmask=[r11] minReg=1>
Interval 39: int RefPositions {} physReg:NA Preferences=[allInt]
<RefPosition #160 @100 RefTypeFixedReg <Reg:rax> BB01 regmask=[rax] minReg=1>
<RefPosition #161 @100 RefTypeDef <Ivl:39> CALL BB01 regmask=[rax] minReg=1 fixed>
DefList: { N099.t40. CALL }
N101 ( 30, 27) [000044] DA-XG------- * STORE_LCL_VAR int V05 loc2 d:2 NA REG NA
<RefPosition #162 @101 RefTypeUse <Ivl:39> BB01 regmask=[allInt] minReg=1 last>
Assigning related <V05/L5> to <I39>
<RefPosition #163 @102 RefTypeDef <Ivl:5 V05> STORE_LCL_VAR BB01 regmask=[allInt] minReg=1 last>
DefList: { }
N103 ( 3, 2) [000195] ------------ * LCL_VAR int V19 cse0 NA REG NA $180
DefList: { }
N105 (???,???) [000216] ------------ * PUTARG_REG int REG r8
<RefPosition #164 @105 RefTypeFixedReg <Reg:r8 > BB01 regmask=[r8] minReg=1>
<RefPosition #165 @105 RefTypeUse <Ivl:13 V19> LCL_VAR BB01 regmask=[r8] minReg=1 last fixed>
Setting putarg_reg as a pass-through of a non-last use lclVar
Interval 40: int RefPositions {} physReg:NA Preferences=[allInt]
<RefPosition #166 @106 RefTypeFixedReg <Reg:r8 > BB01 regmask=[r8] minReg=1>
<RefPosition #167 @106 RefTypeDef <Ivl:40> PUTARG_REG BB01 regmask=[r8] minReg=1 fixed>
Assigning related <V19/L13> to <I40>
DefList: { N105.t216. PUTARG_REG }
N107 ( 1, 1) [000045] ------------ * LCL_VAR int V00 arg0 u:1 NA REG NA $80
DefList: { N105.t216. PUTARG_REG }
N109 (???,???) [000217] ------------ * PUTARG_REG int REG rcx
<RefPosition #168 @109 RefTypeFixedReg <Reg:rcx> BB01 regmask=[rcx] minReg=1>
<RefPosition #169 @109 RefTypeUse <Ivl:0 V00> LCL_VAR BB01 regmask=[rcx] minReg=1 last fixed>
Setting putarg_reg as a pass-through of a non-last use lclVar
Interval 41: int RefPositions {} physReg:NA Preferences=[allInt]
<RefPosition #170 @110 RefTypeFixedReg <Reg:rcx> BB01 regmask=[rcx] minReg=1>
<RefPosition #171 @110 RefTypeDef <Ivl:41> PUTARG_REG BB01 regmask=[rcx] minReg=1 fixed>
Assigning related <V00/L0> to <I41>
DefList: { N105.t216. PUTARG_REG; N109.t217. PUTARG_REG }
N111 ( 1, 1) [000046] ------------ * LCL_VAR int V01 arg1 u:1 NA REG NA $81
DefList: { N105.t216. PUTARG_REG; N109.t217. PUTARG_REG }
N113 (???,???) [000218] ------------ * PUTARG_REG int REG rdx
<RefPosition #172 @113 RefTypeFixedReg <Reg:rdx> BB01 regmask=[rdx] minReg=1>
<RefPosition #173 @113 RefTypeUse <Ivl:1 V01> LCL_VAR BB01 regmask=[rdx] minReg=1 last fixed>
Setting putarg_reg as a pass-through of a non-last use lclVar
Interval 42: int RefPositions {} physReg:NA Preferences=[allInt]
<RefPosition #174 @114 RefTypeFixedReg <Reg:rdx> BB01 regmask=[rdx] minReg=1>
<RefPosition #175 @114 RefTypeDef <Ivl:42> PUTARG_REG BB01 regmask=[rdx] minReg=1 fixed>
Assigning related <V01/L1> to <I42>
DefList: { N105.t216. PUTARG_REG; N109.t217. PUTARG_REG; N113.t218. PUTARG_REG }
N115 ( 19, 12) [000048] --CXG------- * CALL int Test2.DoTestImpl5 REG NA $156
<RefPosition #176 @115 RefTypeFixedReg <Reg:r8 > BB01 regmask=[r8] minReg=1>
<RefPosition #177 @115 RefTypeUse <Ivl:40> BB01 regmask=[r8] minReg=1 last fixed>
<RefPosition #178 @115 RefTypeFixedReg <Reg:rcx> BB01 regmask=[rcx] minReg=1>
<RefPosition #179 @115 RefTypeUse <Ivl:41> BB01 regmask=[rcx] minReg=1 last fixed>
<RefPosition #180 @115 RefTypeFixedReg <Reg:rdx> BB01 regmask=[rdx] minReg=1>
<RefPosition #181 @115 RefTypeUse <Ivl:42> BB01 regmask=[rdx] minReg=1 last fixed>
<RefPosition #182 @116 RefTypeKill <Reg:rax> BB01 regmask=[rax] minReg=1>
<RefPosition #183 @116 RefTypeKill <Reg:rcx> BB01 regmask=[rcx] minReg=1>
<RefPosition #184 @116 RefTypeKill <Reg:rdx> BB01 regmask=[rdx] minReg=1>
<RefPosition #185 @116 RefTypeKill <Reg:r8 > BB01 regmask=[r8] minReg=1>
<RefPosition #186 @116 RefTypeKill <Reg:r9 > BB01 regmask=[r9] minReg=1>
<RefPosition #187 @116 RefTypeKill <Reg:r10> BB01 regmask=[r10] minReg=1>
<RefPosition #188 @116 RefTypeKill <Reg:r11> BB01 regmask=[r11] minReg=1>
Interval 43: int RefPositions {} physReg:NA Preferences=[allInt]
<RefPosition #189 @116 RefTypeFixedReg <Reg:rax> BB01 regmask=[rax] minReg=1>
<RefPosition #190 @116 RefTypeDef <Ivl:43> CALL BB01 regmask=[rax] minReg=1 fixed>
DefList: { N115.t48. CALL }
N117 ( 23, 15) [000051] DA-XG------- * STORE_LCL_VAR int V06 loc3 d:2 NA REG NA
<RefPosition #191 @117 RefTypeUse <Ivl:43> BB01 regmask=[allInt] minReg=1 last>
Assigning related <V06/L6> to <I43>
<RefPosition #192 @118 RefTypeDef <Ivl:6 V06> STORE_LCL_VAR BB01 regmask=[allInt] minReg=1 last>
DefList: { }
N119 ( 1, 1) [000052] ------------ * LCL_VAR int V00 arg0 u:1 NA REG NA $80
DefList: { }
N121 ( 1, 1) [000053] ------------ * LCL_VAR int V01 arg1 u:1 NA (last use) REG NA $81
DefList: { }
N123 ( 3, 3) [000140] ------------ * ADD int REG NA $181
<RefPosition #193 @123 RefTypeUse <Ivl:0 V00> LCL_VAR BB01 regmask=[allInt] minReg=1 last>
<RefPosition #194 @123 RefTypeUse <Ivl:1 V01> LCL_VAR BB01 regmask=[allInt] minReg=1 last>
Interval 44: int RefPositions {} physReg:NA Preferences=[allInt]
<RefPosition #195 @124 RefTypeDef <Ivl:44> ADD BB01 regmask=[allInt] minReg=1>
Assigning related <I44> to <V01/L1>
DefList: { N123.t140. ADD }
N125 ( 3, 3) [000114] DA---------- * STORE_LCL_VAR int V13 tmp4 d:2 NA REG NA
<RefPosition #196 @125 RefTypeUse <Ivl:44> BB01 regmask=[allInt] minReg=1 last>
Assigning related <V13/L10> to <I44>
<RefPosition #197 @126 RefTypeDef <Ivl:10 V13> STORE_LCL_VAR BB01 regmask=[allInt] minReg=1 last>
DefList: { }
N127 ( 1, 1) [000115] ------------ * LCL_VAR int V13 tmp4 u:2 NA (last use) REG NA $181
DefList: { }
N129 ( 3, 2) [000196] ------------ * LCL_VAR int V19 cse0 NA REG NA $180
DefList: { }
N131 ( 8, 6) [000145] ------------ * MUL int REG NA $182
<RefPosition #198 @131 RefTypeUse <Ivl:10 V13> LCL_VAR BB01 regmask=[allInt] minReg=1 last>
<RefPosition #199 @131 RefTypeUse <Ivl:13 V19> LCL_VAR BB01 regmask=[allInt] minReg=1 last>
Interval 45: int RefPositions {} physReg:NA Preferences=[allInt]
<RefPosition #200 @132 RefTypeDef <Ivl:45> MUL BB01 regmask=[allInt] minReg=1>
Assigning related <I45> to <V13/L10>
DefList: { N131.t145. MUL }
N133 ( 8, 6) [000120] DA---------- * STORE_LCL_VAR int V14 tmp5 d:2 NA REG NA
<RefPosition #201 @133 RefTypeUse <Ivl:45> BB01 regmask=[allInt] minReg=1 last>
Assigning related <V14/L11> to <I45>
<RefPosition #202 @134 RefTypeDef <Ivl:11 V14> STORE_LCL_VAR BB01 regmask=[allInt] minReg=1 last>
DefList: { }
N135 ( 1, 1) [000121] ------------ * LCL_VAR int V00 arg0 u:1 NA (last use) REG NA $80
DefList: { }
N137 ( 3, 2) [000197] ------------ * LCL_VAR int V19 cse0 NA (last use) REG NA $180
DefList: { }
N139 ( 8, 6) [000150] ------------ * MUL int REG NA $183
<RefPosition #203 @139 RefTypeUse <Ivl:0 V00> LCL_VAR BB01 regmask=[allInt] minReg=1 last>
<RefPosition #204 @139 RefTypeUse <Ivl:13 V19> LCL_VAR BB01 regmask=[allInt] minReg=1 last>
Interval 46: int RefPositions {} physReg:NA Preferences=[allInt]
<RefPosition #205 @140 RefTypeDef <Ivl:46> MUL BB01 regmask=[allInt] minReg=1>
Assigning related <I46> to <V00/L0>
Assigning related <I46> to <V19/L13>
DefList: { N139.t150. MUL }
N141 ( 8, 6) [000131] DA---------- * STORE_LCL_VAR int V15 tmp6 d:2 NA REG NA
<RefPosition #206 @141 RefTypeUse <Ivl:46> BB01 regmask=[allInt] minReg=1 last>
Assigning related <V15/L12> to <I46>
<RefPosition #207 @142 RefTypeDef <Ivl:12 V15> STORE_LCL_VAR BB01 regmask=[allInt] minReg=1 last>
DefList: { }
N143 ( 1, 1) [000132] ------------ * LCL_VAR int V15 tmp6 u:2 NA (last use) REG NA $183
DefList: { }
N145 ( 1, 1) [000127] ------------ * LCL_VAR int V14 tmp5 u:2 NA (last use) REG NA $182
DefList: { }
N147 ( 1, 1) [000152] -c---------- * CNS_INT int 2 REG NA $42
Contained
DefList: { }
N149 ( 3, 3) [000153] ------------ * RSH int REG NA $184
<RefPosition #208 @149 RefTypeUse <Ivl:11 V14> LCL_VAR BB01 regmask=[allInt] minReg=1 last>
Interval 47: int RefPositions {} physReg:NA Preferences=[allInt]
<RefPosition #209 @150 RefTypeDef <Ivl:47> RSH BB01 regmask=[allInt] minReg=1>
Assigning related <I47> to <V14/L11>
DefList: { N149.t153. RSH }
N151 ( 24, 7) [000156] ---X-------- * DIV int REG NA $186
<RefPosition #210 @151 RefTypeFixedReg <Reg:rax> BB01 regmask=[rax] minReg=1>
<RefPosition #211 @151 RefTypeUse <Ivl:12 V15> LCL_VAR BB01 regmask=[rax] minReg=1 last fixed>
<RefPosition #212 @151 RefTypeUse <Ivl:47> BB01 regmask=[rcx rbx rbp rsi rdi r8-r15] minReg=1 last>
<RefPosition #213 @152 RefTypeKill <Reg:rax> BB01 regmask=[rax] minReg=1>
<RefPosition #214 @152 RefTypeKill <Reg:rdx> BB01 regmask=[rdx] minReg=1>
Interval 48: int RefPositions {} physReg:NA Preferences=[allInt]
<RefPosition #215 @152 RefTypeFixedReg <Reg:rax> BB01 regmask=[rax] minReg=1>
<RefPosition #216 @152 RefTypeDef <Ivl:48> DIV BB01 regmask=[rax] minReg=1 fixed>
Assigning related <I48> to <V15/L12>
DefList: { N151.t156. DIV }
N153 ( 28, 10) [000058] DA-X-------- * STORE_LCL_VAR int V07 loc4 d:2 NA REG NA
<RefPosition #217 @153 RefTypeUse <Ivl:48> BB01 regmask=[allInt] minReg=1 last>
Assigning related <V07/L7> to <I48>
<RefPosition #218 @154 RefTypeDef <Ivl:7 V07> STORE_LCL_VAR BB01 regmask=[allInt] minReg=1 last>
DefList: { }
N155 ( 1, 1) [000012] ------------ * LCL_VAR int V10 tmp1 u:2 NA (last use) REG NA $143
DefList: { }
N157 ( 3, 2) [000059] ------------ * LCL_VAR int V03 loc0 u:2 NA (last use) REG NA $148
DefList: { }
N159 ( 5, 4) [000060] ------------ * ADD int REG NA $187
<RefPosition #219 @159 RefTypeUse <Ivl:8 V10> LCL_VAR BB01 regmask=[allInt] minReg=1 last>
<RefPosition #220 @159 RefTypeUse <Ivl:3 V03> LCL_VAR BB01 regmask=[allInt] minReg=1 last>
Interval 49: int RefPositions {} physReg:NA Preferences=[allInt]
<RefPosition #221 @160 RefTypeDef <Ivl:49> ADD BB01 regmask=[allInt] minReg=1>
Assigning related <I49> to <V10/L8>
Assigning related <I49> to <V03/L3>
DefList: { N159.t60. ADD }
N161 ( 3, 2) [000061] ------------ * LCL_VAR int V04 loc1 u:2 NA (last use) REG NA $14d
DefList: { N159.t60. ADD }
N163 ( 9, 7) [000062] ------------ * ADD int REG NA $188
<RefPosition #222 @163 RefTypeUse <Ivl:49> BB01 regmask=[allInt] minReg=1 last>
<RefPosition #223 @163 RefTypeUse <Ivl:4 V04> LCL_VAR BB01 regmask=[allInt] minReg=1 last>
Interval 50: int RefPositions {} physReg:NA Preferences=[allInt]
<RefPosition #224 @164 RefTypeDef <Ivl:50> ADD BB01 regmask=[allInt] minReg=1>
Assigning related <I50> to <I49>
Assigning related <I50> to <V04/L4>
DefList: { N163.t62. ADD }
N165 ( 3, 2) [000063] ------------ * LCL_VAR int V05 loc2 u:2 NA (last use) REG NA $151
DefList: { N163.t62. ADD }
N167 ( 13, 10) [000064] ------------ * ADD int REG NA $189
<RefPosition #225 @167 RefTypeUse <Ivl:50> BB01 regmask=[allInt] minReg=1 last>
<RefPosition #226 @167 RefTypeUse <Ivl:5 V05> LCL_VAR BB01 regmask=[allInt] minReg=1 last>
Interval 51: int RefPositions {} physReg:NA Preferences=[allInt]
<RefPosition #227 @168 RefTypeDef <Ivl:51> ADD BB01 regmask=[allInt] minReg=1>
Assigning related <I51> to <I50>
Assigning related <I51> to <V05/L5>
DefList: { N167.t64. ADD }
N169 ( 3, 2) [000065] ------------ * LCL_VAR int V06 loc3 u:2 NA (last use) REG NA $156
DefList: { N167.t64. ADD }
N171 ( 17, 13) [000066] ------------ * ADD int REG NA $18a
<RefPosition #228 @171 RefTypeUse <Ivl:51> BB01 regmask=[allInt] minReg=1 last>
<RefPosition #229 @171 RefTypeUse <Ivl:6 V06> LCL_VAR BB01 regmask=[allInt] minReg=1 last>
Interval 52: int RefPositions {} physReg:NA Preferences=[allInt]
<RefPosition #230 @172 RefTypeDef <Ivl:52> ADD BB01 regmask=[allInt] minReg=1>
Assigning related <I52> to <I51>
Assigning related <I52> to <V06/L6>
DefList: { N171.t66. ADD }
N173 ( 3, 2) [000067] ------------ * LCL_VAR int V07 loc4 u:2 NA (last use) REG NA $185
DefList: { N171.t66. ADD }
N175 ( 21, 16) [000068] ------------ * ADD int REG NA $18b
<RefPosition #231 @175 RefTypeUse <Ivl:52> BB01 regmask=[allInt] minReg=1 last>
<RefPosition #232 @175 RefTypeUse <Ivl:7 V07> LCL_VAR BB01 regmask=[allInt] minReg=1 last>
Interval 53: int RefPositions {} physReg:NA Preferences=[allInt]
<RefPosition #233 @176 RefTypeDef <Ivl:53> ADD BB01 regmask=[allInt] minReg=1>
Assigning related <I53> to <I52>
Assigning related <I53> to <V07/L7>
DefList: { N175.t68. ADD }
N177 ( 22, 17) [000069] ------------ * RETURN int REG NA $15c
<RefPosition #234 @177 RefTypeFixedReg <Reg:rax> BB01 regmask=[rax] minReg=1>
<RefPosition #235 @177 RefTypeUse <Ivl:53> BB01 regmask=[rax] minReg=1 last fixed>
CHECKING LAST USES for BB01, liveout={}
==============================
use: {V00 V01 V02}
def: {V03 V04 V05 V06 V07 V08 V10 V11 V13 V14 V15 V19}
Linear scan intervals BEFORE VALIDATING INTERVALS:
Interval 0: (V00) int RefPositions {#0@0 #13@15 #42@31 #83@61 #133@89 #169@109 #193@123 #203@139} physReg:rcx Preferences=[rbx rbp rsi rdi r12-r15] RelatedInterval <I46>
Interval 1: (V01) int RefPositions {#1@0 #17@19 #46@35 #87@65 #137@93 #173@113 #194@123} physReg:rdx Preferences=[rbx rbp rsi rdi r12-r15] RelatedInterval <I44>
Interval 2: (V02) int RefPositions {#2@0 #4@5} physReg:r8 Preferences=[r8]
Interval 3: (V03) int RefPositions {#72@44 #220@159} physReg:NA Preferences=[rbx rbp rsi rdi r12-r15] RelatedInterval <I49>
Interval 4: (V04) int RefPositions {#108@70 #223@163} physReg:NA Preferences=[rbx rbp rsi rdi r12-r15] RelatedInterval <I50>
Interval 5: (V05) int RefPositions {#163@102 #226@167} physReg:NA Preferences=[rbx rbp rsi rdi r12-r15] RelatedInterval <I51>
Interval 6: (V06) int RefPositions {#192@118 #229@171} physReg:NA Preferences=[rcx rbx rbp rsi rdi r8-r15] RelatedInterval <I52>
Interval 7: (V07) int RefPositions {#218@154 #232@175} physReg:NA Preferences=[allInt] RelatedInterval <I53>
Interval 8: (V10) int RefPositions {#36@24 #219@159} physReg:NA Preferences=[rbx rbp rsi rdi r12-r15] RelatedInterval <I49>
Interval 9: (V11) ref RefPositions {#126@78 #129@85} physReg:NA Preferences=[rdx]
Interval 10: (V13) int RefPositions {#197@126 #198@131} physReg:NA Preferences=[allInt] RelatedInterval <I45>
Interval 11: (V14) int RefPositions {#202@134 #208@149} physReg:NA Preferences=[allInt] RelatedInterval <I47>
Interval 12: (V15) int RefPositions {#207@142 #211@151} physReg:NA Preferences=[rax] RelatedInterval <I48>
Interval 13: (V19) int RefPositions {#7@8 #9@11 #38@27 #74@53 #127@81 #165@105 #199@131 #204@139} physReg:NA Preferences=[rbx rbp rsi rdi r12-r15] RelatedInterval <I46>
Interval 14: int RefPositions {#5@6 #6@7} physReg:NA Preferences=[allInt] RelatedInterval <V19/L13>
Interval 15: int (specialPutArg) RefPositions {#11@12 #21@21} physReg:NA Preferences=[r8] RelatedInterval <V19/L13>
Interval 16: int (specialPutArg) RefPositions {#15@16 #23@21} physReg:NA Preferences=[rcx] RelatedInterval <V00/L0>
Interval 17: int (specialPutArg) RefPositions {#19@20 #25@21} physReg:NA Preferences=[rdx] RelatedInterval <V01/L1>
Interval 18: int RefPositions {#34@22 #35@23} physReg:NA Preferences=[rax] RelatedInterval <V10/L8>
Interval 19: int (specialPutArg) RefPositions {#40@28 #55@41} physReg:NA Preferences=[r9] RelatedInterval <V19/L13>
Interval 20: int (specialPutArg) RefPositions {#44@32 #57@41} physReg:NA Preferences=[rdx] RelatedInterval <V00/L0>
Interval 21: int (specialPutArg) RefPositions {#48@36 #59@41} physReg:NA Preferences=[r8] RelatedInterval <V01/L1>
Interval 22: long (constant) RefPositions {#49@38 #51@39} physReg:NA Preferences=[rcx]
Interval 23: long RefPositions {#53@40 #61@41} physReg:NA Preferences=[rcx]
Interval 24: int RefPositions {#70@42 #71@43} physReg:NA Preferences=[rax] RelatedInterval <V03/L3>
Interval 25: int (specialPutArg) RefPositions {#76@54 #91@67} physReg:NA Preferences=[r9] RelatedInterval <V19/L13>
Interval 26: byte RefPositions {#77@56 #79@57} physReg:NA Preferences=[rcx]
Interval 27: int RefPositions {#81@58 #93@67} physReg:NA Preferences=[rcx]
Interval 28: int (specialPutArg) RefPositions {#85@62 #95@67} physReg:NA Preferences=[rdx] RelatedInterval <V00/L0>
Interval 29: int (specialPutArg) RefPositions {#89@66 #97@67} physReg:NA Preferences=[r8] RelatedInterval <V01/L1>
Interval 30: int RefPositions {#106@68 #107@69} physReg:NA Preferences=[rax] RelatedInterval <V04/L4>
Interval 31: long (constant) RefPositions {#109@72 #111@73} physReg:NA Preferences=[rcx]
Interval 32: long RefPositions {#113@74 #115@75} physReg:NA Preferences=[rcx]
Interval 33: ref RefPositions {#124@76 #125@77} physReg:NA Preferences=[rax] RelatedInterval <V11/L9>
Interval 34: ref RefPositions {#131@86 #146@99} physReg:NA Preferences=[rdx]
Interval 35: int (specialPutArg) RefPositions {#135@90 #148@99} physReg:NA Preferences=[r8] RelatedInterval <V00/L0>
Interval 36: int (specialPutArg) RefPositions {#139@94 #150@99} physReg:NA Preferences=[r9] RelatedInterval <V01/L1>
Interval 37: long (constant) RefPositions {#140@96 #142@97} physReg:NA Preferences=[rcx]
Interval 38: long RefPositions {#144@98 #152@99} physReg:NA Preferences=[rcx]
Interval 39: int RefPositions {#161@100 #162@101} physReg:NA Preferences=[rax] RelatedInterval <V05/L5>
Interval 40: int (specialPutArg) RefPositions {#167@106 #177@115} physReg:NA Preferences=[r8] RelatedInterval <V19/L13>
Interval 41: int (specialPutArg) RefPositions {#171@110 #179@115} physReg:NA Preferences=[rcx] RelatedInterval <V00/L0>
Interval 42: int (specialPutArg) RefPositions {#175@114 #181@115} physReg:NA Preferences=[rdx] RelatedInterval <V01/L1>
Interval 43: int RefPositions {#190@116 #191@117} physReg:NA Preferences=[rax] RelatedInterval <V06/L6>
Interval 44: int RefPositions {#195@124 #196@125} physReg:NA Preferences=[allInt] RelatedInterval <V13/L10>
Interval 45: int RefPositions {#200@132 #201@133} physReg:NA Preferences=[allInt] RelatedInterval <V14/L11>
Interval 46: int RefPositions {#205@140 #206@141} physReg:NA Preferences=[allInt] RelatedInterval <V15/L12>
Interval 47: int RefPositions {#209@150 #212@151} physReg:NA Preferences=[rcx rbx rbp rsi rdi r8-r15]
Interval 48: int (interfering uses) RefPositions {#216@152 #217@153} physReg:NA Preferences=[rax] RelatedInterval <V07/L7>
Interval 49: int RefPositions {#221@160 #222@163} physReg:NA Preferences=[allInt] RelatedInterval <I50>
Interval 50: int RefPositions {#224@164 #225@167} physReg:NA Preferences=[allInt] RelatedInterval <I51>
Interval 51: int RefPositions {#227@168 #228@171} physReg:NA Preferences=[allInt] RelatedInterval <I52>
Interval 52: int RefPositions {#230@172 #231@175} physReg:NA Preferences=[allInt] RelatedInterval <I53>
Interval 53: int RefPositions {#233@176 #235@177} physReg:NA Preferences=[rax]
------------
REFPOSITIONS BEFORE VALIDATING INTERVALS:
------------
<RefPosition #0 @0 RefTypeParamDef <Ivl:0 V00> BB00 regmask=[rcx] minReg=1 fixed regOptional>
<RefPosition #1 @0 RefTypeParamDef <Ivl:1 V01> BB00 regmask=[rdx] minReg=1 fixed regOptional>
<RefPosition #2 @0 RefTypeParamDef <Ivl:2 V02> BB00 regmask=[r8] minReg=1 fixed regOptional>
<RefPosition #3 @1 RefTypeBB BB01 regmask=[] minReg=1>
<RefPosition #4 @5 RefTypeUse <Ivl:2 V02> LCL_VAR BB01 regmask=[allInt] minReg=1 last>
<RefPosition #5 @6 RefTypeDef <Ivl:14> CAST BB01 regmask=[allInt] minReg=1>
<RefPosition #6 @7 RefTypeUse <Ivl:14> BB01 regmask=[allInt] minReg=1 last>
<RefPosition #7 @8 RefTypeDef <Ivl:13 V19> STORE_LCL_VAR BB01 regmask=[allInt] minReg=1>
<RefPosition #8 @11 RefTypeFixedReg <Reg:r8 > BB01 regmask=[r8] minReg=1>
<RefPosition #9 @11 RefTypeUse <Ivl:13 V19> LCL_VAR BB01 regmask=[r8] minReg=1 fixed>
<RefPosition #10 @12 RefTypeFixedReg <Reg:r8 > BB01 regmask=[r8] minReg=1>
<RefPosition #11 @12 RefTypeDef <Ivl:15> PUTARG_REG BB01 regmask=[r8] minReg=1 fixed>
<RefPosition #12 @15 RefTypeFixedReg <Reg:rcx> BB01 regmask=[rcx] minReg=1>
<RefPosition #13 @15 RefTypeUse <Ivl:0 V00> LCL_VAR BB01 regmask=[rcx] minReg=1 fixed>
<RefPosition #14 @16 RefTypeFixedReg <Reg:rcx> BB01 regmask=[rcx] minReg=1>
<RefPosition #15 @16 RefTypeDef <Ivl:16> PUTARG_REG BB01 regmask=[rcx] minReg=1 fixed>
<RefPosition #16 @19 RefTypeFixedReg <Reg:rdx> BB01 regmask=[rdx] minReg=1>
<RefPosition #17 @19 RefTypeUse <Ivl:1 V01> LCL_VAR BB01 regmask=[rdx] minReg=1 fixed>
<RefPosition #18 @20 RefTypeFixedReg <Reg:rdx> BB01 regmask=[rdx] minReg=1>
<RefPosition #19 @20 RefTypeDef <Ivl:17> PUTARG_REG BB01 regmask=[rdx] minReg=1 fixed>
<RefPosition #20 @21 RefTypeFixedReg <Reg:r8 > BB01 regmask=[r8] minReg=1>
<RefPosition #21 @21 RefTypeUse <Ivl:15> BB01 regmask=[r8] minReg=1 last fixed>
<RefPosition #22 @21 RefTypeFixedReg <Reg:rcx> BB01 regmask=[rcx] minReg=1>
<RefPosition #23 @21 RefTypeUse <Ivl:16> BB01 regmask=[rcx] minReg=1 last fixed>
<RefPosition #24 @21 RefTypeFixedReg <Reg:rdx> BB01 regmask=[rdx] minReg=1>
<RefPosition #25 @21 RefTypeUse <Ivl:17> BB01 regmask=[rdx] minReg=1 last fixed>
<RefPosition #26 @22 RefTypeKill <Reg:rax> BB01 regmask=[rax] minReg=1 last>
<RefPosition #27 @22 RefTypeKill <Reg:rcx> BB01 regmask=[rcx] minReg=1 last>
<RefPosition #28 @22 RefTypeKill <Reg:rdx> BB01 regmask=[rdx] minReg=1 last>
<RefPosition #29 @22 RefTypeKill <Reg:r8 > BB01 regmask=[r8] minReg=1 last>
<RefPosition #30 @22 RefTypeKill <Reg:r9 > BB01 regmask=[r9] minReg=1 last>
<RefPosition #31 @22 RefTypeKill <Reg:r10> BB01 regmask=[r10] minReg=1 last>
<RefPosition #32 @22 RefTypeKill <Reg:r11> BB01 regmask=[r11] minReg=1 last>
<RefPosition #33 @22 RefTypeFixedReg <Reg:rax> BB01 regmask=[rax] minReg=1>
<RefPosition #34 @22 RefTypeDef <Ivl:18> CALL BB01 regmask=[rax] minReg=1 fixed>
<RefPosition #35 @23 RefTypeUse <Ivl:18> BB01 regmask=[allInt] minReg=1 last>
<RefPosition #36 @24 RefTypeDef <Ivl:8 V10> STORE_LCL_VAR BB01 regmask=[allInt] minReg=1>
<RefPosition #37 @27 RefTypeFixedReg <Reg:r9 > BB01 regmask=[r9] minReg=1>
<RefPosition #38 @27 RefTypeUse <Ivl:13 V19> LCL_VAR BB01 regmask=[r9] minReg=1 fixed>
<RefPosition #39 @28 RefTypeFixedReg <Reg:r9 > BB01 regmask=[r9] minReg=1>
<RefPosition #40 @28 RefTypeDef <Ivl:19> PUTARG_REG BB01 regmask=[r9] minReg=1 fixed>
<RefPosition #41 @31 RefTypeFixedReg <Reg:rdx> BB01 regmask=[rdx] minReg=1>
<RefPosition #42 @31 RefTypeUse <Ivl:0 V00> LCL_VAR BB01 regmask=[rdx] minReg=1 fixed>
<RefPosition #43 @32 RefTypeFixedReg <Reg:rdx> BB01 regmask=[rdx] minReg=1>
<RefPosition #44 @32 RefTypeDef <Ivl:20> PUTARG_REG BB01 regmask=[rdx] minReg=1 fixed>
<RefPosition #45 @35 RefTypeFixedReg <Reg:r8 > BB01 regmask=[r8] minReg=1>
<RefPosition #46 @35 RefTypeUse <Ivl:1 V01> LCL_VAR BB01 regmask=[r8] minReg=1 fixed>
<RefPosition #47 @36 RefTypeFixedReg <Reg:r8 > BB01 regmask=[r8] minReg=1>
<RefPosition #48 @36 RefTypeDef <Ivl:21> PUTARG_REG BB01 regmask=[r8] minReg=1 fixed>
<RefPosition #49 @38 RefTypeDef <Ivl:22> CNS_INT BB01 regmask=[rcx] minReg=1>
<RefPosition #50 @39 RefTypeFixedReg <Reg:rcx> BB01 regmask=[rcx] minReg=1>
<RefPosition #51 @39 RefTypeUse <Ivl:22> BB01 regmask=[rcx] minReg=1 last fixed>
<RefPosition #52 @40 RefTypeFixedReg <Reg:rcx> BB01 regmask=[rcx] minReg=1>
<RefPosition #53 @40 RefTypeDef <Ivl:23> PUTARG_REG BB01 regmask=[rcx] minReg=1 fixed>
<RefPosition #54 @41 RefTypeFixedReg <Reg:r9 > BB01 regmask=[r9] minReg=1>
<RefPosition #55 @41 RefTypeUse <Ivl:19> BB01 regmask=[r9] minReg=1 last fixed>
<RefPosition #56 @41 RefTypeFixedReg <Reg:rdx> BB01 regmask=[rdx] minReg=1>
<RefPosition #57 @41 RefTypeUse <Ivl:20> BB01 regmask=[rdx] minReg=1 last fixed>
<RefPosition #58 @41 RefTypeFixedReg <Reg:r8 > BB01 regmask=[r8] minReg=1>
<RefPosition #59 @41 RefTypeUse <Ivl:21> BB01 regmask=[r8] minReg=1 last fixed>
<RefPosition #60 @41 RefTypeFixedReg <Reg:rcx> BB01 regmask=[rcx] minReg=1>
<RefPosition #61 @41 RefTypeUse <Ivl:23> BB01 regmask=[rcx] minReg=1 last fixed>
<RefPosition #62 @42 RefTypeKill <Reg:rax> BB01 regmask=[rax] minReg=1 last>
<RefPosition #63 @42 RefTypeKill <Reg:rcx> BB01 regmask=[rcx] minReg=1 last>
<RefPosition #64 @42 RefTypeKill <Reg:rdx> BB01 regmask=[rdx] minReg=1 last>
<RefPosition #65 @42 RefTypeKill <Reg:r8 > BB01 regmask=[r8] minReg=1 last>
<RefPosition #66 @42 RefTypeKill <Reg:r9 > BB01 regmask=[r9] minReg=1 last>
<RefPosition #67 @42 RefTypeKill <Reg:r10> BB01 regmask=[r10] minReg=1 last>
<RefPosition #68 @42 RefTypeKill <Reg:r11> BB01 regmask=[r11] minReg=1 last>
<RefPosition #69 @42 RefTypeFixedReg <Reg:rax> BB01 regmask=[rax] minReg=1>
<RefPosition #70 @42 RefTypeDef <Ivl:24> CALL BB01 regmask=[rax] minReg=1 fixed>
<RefPosition #71 @43 RefTypeUse <Ivl:24> BB01 regmask=[allInt] minReg=1 last>
<RefPosition #72 @44 RefTypeDef <Ivl:3 V03> STORE_LCL_VAR BB01 regmask=[allInt] minReg=1>
<RefPosition #73 @53 RefTypeFixedReg <Reg:r9 > BB01 regmask=[r9] minReg=1>
<RefPosition #74 @53 RefTypeUse <Ivl:13 V19> LCL_VAR BB01 regmask=[r9] minReg=1 fixed>
<RefPosition #75 @54 RefTypeFixedReg <Reg:r9 > BB01 regmask=[r9] minReg=1>
<RefPosition #76 @54 RefTypeDef <Ivl:25> PUTARG_REG BB01 regmask=[r9] minReg=1 fixed>
<RefPosition #77 @56 RefTypeDef <Ivl:26> LCL_FLD BB01 regmask=[rcx] minReg=1>
<RefPosition #78 @57 RefTypeFixedReg <Reg:rcx> BB01 regmask=[rcx] minReg=1>
<RefPosition #79 @57 RefTypeUse <Ivl:26> BB01 regmask=[rcx] minReg=1 last fixed>
<RefPosition #80 @58 RefTypeFixedReg <Reg:rcx> BB01 regmask=[rcx] minReg=1>
<RefPosition #81 @58 RefTypeDef <Ivl:27> PUTARG_REG BB01 regmask=[rcx] minReg=1 fixed>
<RefPosition #82 @61 RefTypeFixedReg <Reg:rdx> BB01 regmask=[rdx] minReg=1>
<RefPosition #83 @61 RefTypeUse <Ivl:0 V00> LCL_VAR BB01 regmask=[rdx] minReg=1 fixed>
<RefPosition #84 @62 RefTypeFixedReg <Reg:rdx> BB01 regmask=[rdx] minReg=1>
<RefPosition #85 @62 RefTypeDef <Ivl:28> PUTARG_REG BB01 regmask=[rdx] minReg=1 fixed>
<RefPosition #86 @65 RefTypeFixedReg <Reg:r8 > BB01 regmask=[r8] minReg=1>
<RefPosition #87 @65 RefTypeUse <Ivl:1 V01> LCL_VAR BB01 regmask=[r8] minReg=1 fixed>
<RefPosition #88 @66 RefTypeFixedReg <Reg:r8 > BB01 regmask=[r8] minReg=1>
<RefPosition #89 @66 RefTypeDef <Ivl:29> PUTARG_REG BB01 regmask=[r8] minReg=1 fixed>
<RefPosition #90 @67 RefTypeFixedReg <Reg:r9 > BB01 regmask=[r9] minReg=1>
<RefPosition #91 @67 RefTypeUse <Ivl:25> BB01 regmask=[r9] minReg=1 last fixed>
<RefPosition #92 @67 RefTypeFixedReg <Reg:rcx> BB01 regmask=[rcx] minReg=1>
<RefPosition #93 @67 RefTypeUse <Ivl:27> BB01 regmask=[rcx] minReg=1 last fixed>
<RefPosition #94 @67 RefTypeFixedReg <Reg:rdx> BB01 regmask=[rdx] minReg=1>
<RefPosition #95 @67 RefTypeUse <Ivl:28> BB01 regmask=[rdx] minReg=1 last fixed>
<RefPosition #96 @67 RefTypeFixedReg <Reg:r8 > BB01 regmask=[r8] minReg=1>
<RefPosition #97 @67 RefTypeUse <Ivl:29> BB01 regmask=[r8] minReg=1 last fixed>
<RefPosition #98 @68 RefTypeKill <Reg:rax> BB01 regmask=[rax] minReg=1 last>
<RefPosition #99 @68 RefTypeKill <Reg:rcx> BB01 regmask=[rcx] minReg=1 last>
<RefPosition #100 @68 RefTypeKill <Reg:rdx> BB01 regmask=[rdx] minReg=1 last>
<RefPosition #101 @68 RefTypeKill <Reg:r8 > BB01 regmask=[r8] minReg=1 last>
<RefPosition #102 @68 RefTypeKill <Reg:r9 > BB01 regmask=[r9] minReg=1 last>
<RefPosition #103 @68 RefTypeKill <Reg:r10> BB01 regmask=[r10] minReg=1 last>
<RefPosition #104 @68 RefTypeKill <Reg:r11> BB01 regmask=[r11] minReg=1 last>
<RefPosition #105 @68 RefTypeFixedReg <Reg:rax> BB01 regmask=[rax] minReg=1>
<RefPosition #106 @68 RefTypeDef <Ivl:30> CALL BB01 regmask=[rax] minReg=1 fixed>
<RefPosition #107 @69 RefTypeUse <Ivl:30> BB01 regmask=[allInt] minReg=1 last>
<RefPosition #108 @70 RefTypeDef <Ivl:4 V04> STORE_LCL_VAR BB01 regmask=[allInt] minReg=1>
<RefPosition #109 @72 RefTypeDef <Ivl:31> CNS_INT BB01 regmask=[rcx] minReg=1>
<RefPosition #110 @73 RefTypeFixedReg <Reg:rcx> BB01 regmask=[rcx] minReg=1>
<RefPosition #111 @73 RefTypeUse <Ivl:31> BB01 regmask=[rcx] minReg=1 last fixed>
<RefPosition #112 @74 RefTypeFixedReg <Reg:rcx> BB01 regmask=[rcx] minReg=1>
<RefPosition #113 @74 RefTypeDef <Ivl:32> PUTARG_REG BB01 regmask=[rcx] minReg=1 fixed>
<RefPosition #114 @75 RefTypeFixedReg <Reg:rcx> BB01 regmask=[rcx] minReg=1>
<RefPosition #115 @75 RefTypeUse <Ivl:32> BB01 regmask=[rcx] minReg=1 last fixed>
<RefPosition #116 @76 RefTypeKill <Reg:rax> BB01 regmask=[rax] minReg=1 last>
<RefPosition #117 @76 RefTypeKill <Reg:rcx> BB01 regmask=[rcx] minReg=1 last>
<RefPosition #118 @76 RefTypeKill <Reg:rdx> BB01 regmask=[rdx] minReg=1 last>
<RefPosition #119 @76 RefTypeKill <Reg:r8 > BB01 regmask=[r8] minReg=1 last>
<RefPosition #120 @76 RefTypeKill <Reg:r9 > BB01 regmask=[r9] minReg=1 last>
<RefPosition #121 @76 RefTypeKill <Reg:r10> BB01 regmask=[r10] minReg=1 last>
<RefPosition #122 @76 RefTypeKill <Reg:r11> BB01 regmask=[r11] minReg=1 last>
<RefPosition #123 @76 RefTypeFixedReg <Reg:rax> BB01 regmask=[rax] minReg=1>
<RefPosition #124 @76 RefTypeDef <Ivl:33> CALL BB01 regmask=[rax] minReg=1 fixed>
<RefPosition #125 @77 RefTypeUse <Ivl:33> BB01 regmask=[allInt] minReg=1 last>
<RefPosition #126 @78 RefTypeDef <Ivl:9 V11> STORE_LCL_VAR BB01 regmask=[allInt] minReg=1>
<RefPosition #127 @81 RefTypeUse <Ivl:13 V19> LCL_VAR BB01 regmask=[allInt] minReg=1>
<RefPosition #128 @85 RefTypeFixedReg <Reg:rdx> BB01 regmask=[rdx] minReg=1>
<RefPosition #129 @85 RefTypeUse <Ivl:9 V11> LCL_VAR BB01 regmask=[rdx] minReg=1 last fixed>
<RefPosition #130 @86 RefTypeFixedReg <Reg:rdx> BB01 regmask=[rdx] minReg=1>
<RefPosition #131 @86 RefTypeDef <Ivl:34> PUTARG_REG BB01 regmask=[rdx] minReg=1 fixed>
<RefPosition #132 @89 RefTypeFixedReg <Reg:r8 > BB01 regmask=[r8] minReg=1>
<RefPosition #133 @89 RefTypeUse <Ivl:0 V00> LCL_VAR BB01 regmask=[r8] minReg=1 fixed>
<RefPosition #134 @90 RefTypeFixedReg <Reg:r8 > BB01 regmask=[r8] minReg=1>
<RefPosition #135 @90 RefTypeDef <Ivl:35> PUTARG_REG BB01 regmask=[r8] minReg=1 fixed>
<RefPosition #136 @93 RefTypeFixedReg <Reg:r9 > BB01 regmask=[r9] minReg=1>
<RefPosition #137 @93 RefTypeUse <Ivl:1 V01> LCL_VAR BB01 regmask=[r9] minReg=1 fixed>
<RefPosition #138 @94 RefTypeFixedReg <Reg:r9 > BB01 regmask=[r9] minReg=1>
<RefPosition #139 @94 RefTypeDef <Ivl:36> PUTARG_REG BB01 regmask=[r9] minReg=1 fixed>
<RefPosition #140 @96 RefTypeDef <Ivl:37> CNS_INT BB01 regmask=[rcx] minReg=1>
<RefPosition #141 @97 RefTypeFixedReg <Reg:rcx> BB01 regmask=[rcx] minReg=1>
<RefPosition #142 @97 RefTypeUse <Ivl:37> BB01 regmask=[rcx] minReg=1 last fixed>
<RefPosition #143 @98 RefTypeFixedReg <Reg:rcx> BB01 regmask=[rcx] minReg=1>
<RefPosition #144 @98 RefTypeDef <Ivl:38> PUTARG_REG BB01 regmask=[rcx] minReg=1 fixed>
<RefPosition #145 @99 RefTypeFixedReg <Reg:rdx> BB01 regmask=[rdx] minReg=1>
<RefPosition #146 @99 RefTypeUse <Ivl:34> BB01 regmask=[rdx] minReg=1 last fixed>
<RefPosition #147 @99 RefTypeFixedReg <Reg:r8 > BB01 regmask=[r8] minReg=1>
<RefPosition #148 @99 RefTypeUse <Ivl:35> BB01 regmask=[r8] minReg=1 last fixed>
<RefPosition #149 @99 RefTypeFixedReg <Reg:r9 > BB01 regmask=[r9] minReg=1>
<RefPosition #150 @99 RefTypeUse <Ivl:36> BB01 regmask=[r9] minReg=1 last fixed>
<RefPosition #151 @99 RefTypeFixedReg <Reg:rcx> BB01 regmask=[rcx] minReg=1>
<RefPosition #152 @99 RefTypeUse <Ivl:38> BB01 regmask=[rcx] minReg=1 last fixed>
<RefPosition #153 @100 RefTypeKill <Reg:rax> BB01 regmask=[rax] minReg=1 last>
<RefPosition #154 @100 RefTypeKill <Reg:rcx> BB01 regmask=[rcx] minReg=1 last>
<RefPosition #155 @100 RefTypeKill <Reg:rdx> BB01 regmask=[rdx] minReg=1 last>
<RefPosition #156 @100 RefTypeKill <Reg:r8 > BB01 regmask=[r8] minReg=1 last>
<RefPosition #157 @100 RefTypeKill <Reg:r9 > BB01 regmask=[r9] minReg=1 last>
<RefPosition #158 @100 RefTypeKill <Reg:r10> BB01 regmask=[r10] minReg=1 last>
<RefPosition #159 @100 RefTypeKill <Reg:r11> BB01 regmask=[r11] minReg=1 last>
<RefPosition #160 @100 RefTypeFixedReg <Reg:rax> BB01 regmask=[rax] minReg=1>
<RefPosition #161 @100 RefTypeDef <Ivl:39> CALL BB01 regmask=[rax] minReg=1 fixed>
<RefPosition #162 @101 RefTypeUse <Ivl:39> BB01 regmask=[allInt] minReg=1 last>
<RefPosition #163 @102 RefTypeDef <Ivl:5 V05> STORE_LCL_VAR BB01 regmask=[allInt] minReg=1>
<RefPosition #164 @105 RefTypeFixedReg <Reg:r8 > BB01 regmask=[r8] minReg=1>
<RefPosition #165 @105 RefTypeUse <Ivl:13 V19> LCL_VAR BB01 regmask=[r8] minReg=1 fixed>
<RefPosition #166 @106 RefTypeFixedReg <Reg:r8 > BB01 regmask=[r8] minReg=1>
<RefPosition #167 @106 RefTypeDef <Ivl:40> PUTARG_REG BB01 regmask=[r8] minReg=1 fixed>
<RefPosition #168 @109 RefTypeFixedReg <Reg:rcx> BB01 regmask=[rcx] minReg=1>
<RefPosition #169 @109 RefTypeUse <Ivl:0 V00> LCL_VAR BB01 regmask=[rcx] minReg=1 fixed>
<RefPosition #170 @110 RefTypeFixedReg <Reg:rcx> BB01 regmask=[rcx] minReg=1>
<RefPosition #171 @110 RefTypeDef <Ivl:41> PUTARG_REG BB01 regmask=[rcx] minReg=1 fixed>
<RefPosition #172 @113 RefTypeFixedReg <Reg:rdx> BB01 regmask=[rdx] minReg=1>
<RefPosition #173 @113 RefTypeUse <Ivl:1 V01> LCL_VAR BB01 regmask=[rdx] minReg=1 fixed>
<RefPosition #174 @114 RefTypeFixedReg <Reg:rdx> BB01 regmask=[rdx] minReg=1>
<RefPosition #175 @114 RefTypeDef <Ivl:42> PUTARG_REG BB01 regmask=[rdx] minReg=1 fixed>
<RefPosition #176 @115 RefTypeFixedReg <Reg:r8 > BB01 regmask=[r8] minReg=1>
<RefPosition #177 @115 RefTypeUse <Ivl:40> BB01 regmask=[r8] minReg=1 last fixed>
<RefPosition #178 @115 RefTypeFixedReg <Reg:rcx> BB01 regmask=[rcx] minReg=1>
<RefPosition #179 @115 RefTypeUse <Ivl:41> BB01 regmask=[rcx] minReg=1 last fixed>
<RefPosition #180 @115 RefTypeFixedReg <Reg:rdx> BB01 regmask=[rdx] minReg=1>
<RefPosition #181 @115 RefTypeUse <Ivl:42> BB01 regmask=[rdx] minReg=1 last fixed>
<RefPosition #182 @116 RefTypeKill <Reg:rax> BB01 regmask=[rax] minReg=1 last>
<RefPosition #183 @116 RefTypeKill <Reg:rcx> BB01 regmask=[rcx] minReg=1 last>
<RefPosition #184 @116 RefTypeKill <Reg:rdx> BB01 regmask=[rdx] minReg=1 last>
<RefPosition #185 @116 RefTypeKill <Reg:r8 > BB01 regmask=[r8] minReg=1 last>
<RefPosition #186 @116 RefTypeKill <Reg:r9 > BB01 regmask=[r9] minReg=1 last>
<RefPosition #187 @116 RefTypeKill <Reg:r10> BB01 regmask=[r10] minReg=1 last>
<RefPosition #188 @116 RefTypeKill <Reg:r11> BB01 regmask=[r11] minReg=1 last>
<RefPosition #189 @116 RefTypeFixedReg <Reg:rax> BB01 regmask=[rax] minReg=1>
<RefPosition #190 @116 RefTypeDef <Ivl:43> CALL BB01 regmask=[rax] minReg=1 fixed>
<RefPosition #191 @117 RefTypeUse <Ivl:43> BB01 regmask=[allInt] minReg=1 last>
<RefPosition #192 @118 RefTypeDef <Ivl:6 V06> STORE_LCL_VAR BB01 regmask=[allInt] minReg=1>
<RefPosition #193 @123 RefTypeUse <Ivl:0 V00> LCL_VAR BB01 regmask=[allInt] minReg=1>
<RefPosition #194 @123 RefTypeUse <Ivl:1 V01> LCL_VAR BB01 regmask=[allInt] minReg=1 last regOptional>
<RefPosition #195 @124 RefTypeDef <Ivl:44> ADD BB01 regmask=[allInt] minReg=1>
<RefPosition #196 @125 RefTypeUse <Ivl:44> BB01 regmask=[allInt] minReg=1 last>
<RefPosition #197 @126 RefTypeDef <Ivl:10 V13> STORE_LCL_VAR BB01 regmask=[allInt] minReg=1>
<RefPosition #198 @131 RefTypeUse <Ivl:10 V13> LCL_VAR BB01 regmask=[allInt] minReg=1 last regOptional>
<RefPosition #199 @131 RefTypeUse <Ivl:13 V19> LCL_VAR BB01 regmask=[allInt] minReg=1>
<RefPosition #200 @132 RefTypeDef <Ivl:45> MUL BB01 regmask=[allInt] minReg=1>
<RefPosition #201 @133 RefTypeUse <Ivl:45> BB01 regmask=[allInt] minReg=1 last>
<RefPosition #202 @134 RefTypeDef <Ivl:11 V14> STORE_LCL_VAR BB01 regmask=[allInt] minReg=1>
<RefPosition #203 @139 RefTypeUse <Ivl:0 V00> LCL_VAR BB01 regmask=[allInt] minReg=1 last regOptional>
<RefPosition #204 @139 RefTypeUse <Ivl:13 V19> LCL_VAR BB01 regmask=[allInt] minReg=1 last>
<RefPosition #205 @140 RefTypeDef <Ivl:46> MUL BB01 regmask=[allInt] minReg=1>
<RefPosition #206 @141 RefTypeUse <Ivl:46> BB01 regmask=[allInt] minReg=1 last>
<RefPosition #207 @142 RefTypeDef <Ivl:12 V15> STORE_LCL_VAR BB01 regmask=[allInt] minReg=1>
<RefPosition #208 @149 RefTypeUse <Ivl:11 V14> LCL_VAR BB01 regmask=[allInt] minReg=1 last>
<RefPosition #209 @150 RefTypeDef <Ivl:47> RSH BB01 regmask=[rcx rbx rbp rsi rdi r8-r15] minReg=1>
<RefPosition #210 @151 RefTypeFixedReg <Reg:rax> BB01 regmask=[rax] minReg=1>
<RefPosition #211 @151 RefTypeUse <Ivl:12 V15> LCL_VAR BB01 regmask=[rax] minReg=1 last fixed>
<RefPosition #212 @151 RefTypeUse <Ivl:47> BB01 regmask=[rcx rbx rbp rsi rdi r8-r15] minReg=1 last delay regOptional>
<RefPosition #213 @152 RefTypeKill <Reg:rax> BB01 regmask=[rax] minReg=1 last>
<RefPosition #214 @152 RefTypeKill <Reg:rdx> BB01 regmask=[rdx] minReg=1 last>
<RefPosition #215 @152 RefTypeFixedReg <Reg:rax> BB01 regmask=[rax] minReg=1>
<RefPosition #216 @152 RefTypeDef <Ivl:48> DIV BB01 regmask=[rax] minReg=1 fixed>
<RefPosition #217 @153 RefTypeUse <Ivl:48> BB01 regmask=[allInt] minReg=1 last>
<RefPosition #218 @154 RefTypeDef <Ivl:7 V07> STORE_LCL_VAR BB01 regmask=[allInt] minReg=1>
<RefPosition #219 @159 RefTypeUse <Ivl:8 V10> LCL_VAR BB01 regmask=[allInt] minReg=1 last>
<RefPosition #220 @159 RefTypeUse <Ivl:3 V03> LCL_VAR BB01 regmask=[allInt] minReg=1 last regOptional>
<RefPosition #221 @160 RefTypeDef <Ivl:49> ADD BB01 regmask=[allInt] minReg=1>
<RefPosition #222 @163 RefTypeUse <Ivl:49> BB01 regmask=[allInt] minReg=1 last>
<RefPosition #223 @163 RefTypeUse <Ivl:4 V04> LCL_VAR BB01 regmask=[allInt] minReg=1 last regOptional>
<RefPosition #224 @164 RefTypeDef <Ivl:50> ADD BB01 regmask=[allInt] minReg=1>
<RefPosition #225 @167 RefTypeUse <Ivl:50> BB01 regmask=[allInt] minReg=1 last>
<RefPosition #226 @167 RefTypeUse <Ivl:5 V05> LCL_VAR BB01 regmask=[allInt] minReg=1 last regOptional>
<RefPosition #227 @168 RefTypeDef <Ivl:51> ADD BB01 regmask=[allInt] minReg=1>
<RefPosition #228 @171 RefTypeUse <Ivl:51> BB01 regmask=[allInt] minReg=1 last>
<RefPosition #229 @171 RefTypeUse <Ivl:6 V06> LCL_VAR BB01 regmask=[allInt] minReg=1 last regOptional>
<RefPosition #230 @172 RefTypeDef <Ivl:52> ADD BB01 regmask=[allInt] minReg=1>
<RefPosition #231 @175 RefTypeUse <Ivl:52> BB01 regmask=[allInt] minReg=1 last>
<RefPosition #232 @175 RefTypeUse <Ivl:7 V07> LCL_VAR BB01 regmask=[allInt] minReg=1 last regOptional>
<RefPosition #233 @176 RefTypeDef <Ivl:53> ADD BB01 regmask=[rax] minReg=1>
<RefPosition #234 @177 RefTypeFixedReg <Reg:rax> BB01 regmask=[rax] minReg=1>
<RefPosition #235 @177 RefTypeUse <Ivl:53> BB01 regmask=[rax] minReg=1 last fixed>
-----------------
<RefPosition #0 @0 RefTypeParamDef <Ivl:0 V00> BB00 regmask=[rcx] minReg=1 fixed regOptional>
<RefPosition #13 @15 RefTypeUse <Ivl:0 V00> LCL_VAR BB01 regmask=[rcx] minReg=1 fixed>
<RefPosition #42 @31 RefTypeUse <Ivl:0 V00> LCL_VAR BB01 regmask=[rdx] minReg=1 fixed>
<RefPosition #83 @61 RefTypeUse <Ivl:0 V00> LCL_VAR BB01 regmask=[rdx] minReg=1 fixed>
<RefPosition #133 @89 RefTypeUse <Ivl:0 V00> LCL_VAR BB01 regmask=[r8] minReg=1 fixed>
<RefPosition #169 @109 RefTypeUse <Ivl:0 V00> LCL_VAR BB01 regmask=[rcx] minReg=1 fixed>
<RefPosition #193 @123 RefTypeUse <Ivl:0 V00> LCL_VAR BB01 regmask=[allInt] minReg=1>
<RefPosition #203 @139 RefTypeUse <Ivl:0 V00> LCL_VAR BB01 regmask=[allInt] minReg=1 last regOptional>
-----------------
<RefPosition #1 @0 RefTypeParamDef <Ivl:1 V01> BB00 regmask=[rdx] minReg=1 fixed regOptional>
<RefPosition #17 @19 RefTypeUse <Ivl:1 V01> LCL_VAR BB01 regmask=[rdx] minReg=1 fixed>
<RefPosition #46 @35 RefTypeUse <Ivl:1 V01> LCL_VAR BB01 regmask=[r8] minReg=1 fixed>
<RefPosition #87 @65 RefTypeUse <Ivl:1 V01> LCL_VAR BB01 regmask=[r8] minReg=1 fixed>
<RefPosition #137 @93 RefTypeUse <Ivl:1 V01> LCL_VAR BB01 regmask=[r9] minReg=1 fixed>
<RefPosition #173 @113 RefTypeUse <Ivl:1 V01> LCL_VAR BB01 regmask=[rdx] minReg=1 fixed>
<RefPosition #194 @123 RefTypeUse <Ivl:1 V01> LCL_VAR BB01 regmask=[allInt] minReg=1 last regOptional>
-----------------
<RefPosition #7 @8 RefTypeDef <Ivl:13 V19> STORE_LCL_VAR BB01 regmask=[allInt] minReg=1>
<RefPosition #9 @11 RefTypeUse <Ivl:13 V19> LCL_VAR BB01 regmask=[r8] minReg=1 fixed>
<RefPosition #38 @27 RefTypeUse <Ivl:13 V19> LCL_VAR BB01 regmask=[r9] minReg=1 fixed>
<RefPosition #74 @53 RefTypeUse <Ivl:13 V19> LCL_VAR BB01 regmask=[r9] minReg=1 fixed>
<RefPosition #127 @81 RefTypeUse <Ivl:13 V19> LCL_VAR BB01 regmask=[allInt] minReg=1>
<RefPosition #165 @105 RefTypeUse <Ivl:13 V19> LCL_VAR BB01 regmask=[r8] minReg=1 fixed>
<RefPosition #199 @131 RefTypeUse <Ivl:13 V19> LCL_VAR BB01 regmask=[allInt] minReg=1>
<RefPosition #204 @139 RefTypeUse <Ivl:13 V19> LCL_VAR BB01 regmask=[allInt] minReg=1 last>
-----------------
<RefPosition #2 @0 RefTypeParamDef <Ivl:2 V02> BB00 regmask=[r8] minReg=1 fixed regOptional>
<RefPosition #4 @5 RefTypeUse <Ivl:2 V02> LCL_VAR BB01 regmask=[allInt] minReg=1 last>
-----------------
<RefPosition #126 @78 RefTypeDef <Ivl:9 V11> STORE_LCL_VAR BB01 regmask=[allInt] minReg=1>
<RefPosition #129 @85 RefTypeUse <Ivl:9 V11> LCL_VAR BB01 regmask=[rdx] minReg=1 last fixed>
-----------------
<RefPosition #36 @24 RefTypeDef <Ivl:8 V10> STORE_LCL_VAR BB01 regmask=[allInt] minReg=1>
<RefPosition #219 @159 RefTypeUse <Ivl:8 V10> LCL_VAR BB01 regmask=[allInt] minReg=1 last>
-----------------
<RefPosition #197 @126 RefTypeDef <Ivl:10 V13> STORE_LCL_VAR BB01 regmask=[allInt] minReg=1>
<RefPosition #198 @131 RefTypeUse <Ivl:10 V13> LCL_VAR BB01 regmask=[allInt] minReg=1 last regOptional>
-----------------
<RefPosition #207 @142 RefTypeDef <Ivl:12 V15> STORE_LCL_VAR BB01 regmask=[allInt] minReg=1>
<RefPosition #211 @151 RefTypeUse <Ivl:12 V15> LCL_VAR BB01 regmask=[rax] minReg=1 last fixed>
-----------------
<RefPosition #72 @44 RefTypeDef <Ivl:3 V03> STORE_LCL_VAR BB01 regmask=[allInt] minReg=1>
<RefPosition #220 @159 RefTypeUse <Ivl:3 V03> LCL_VAR BB01 regmask=[allInt] minReg=1 last regOptional>
-----------------
<RefPosition #108 @70 RefTypeDef <Ivl:4 V04> STORE_LCL_VAR BB01 regmask=[allInt] minReg=1>
<RefPosition #223 @163 RefTypeUse <Ivl:4 V04> LCL_VAR BB01 regmask=[allInt] minReg=1 last regOptional>
-----------------
<RefPosition #163 @102 RefTypeDef <Ivl:5 V05> STORE_LCL_VAR BB01 regmask=[allInt] minReg=1>
<RefPosition #226 @167 RefTypeUse <Ivl:5 V05> LCL_VAR BB01 regmask=[allInt] minReg=1 last regOptional>
-----------------
<RefPosition #192 @118 RefTypeDef <Ivl:6 V06> STORE_LCL_VAR BB01 regmask=[allInt] minReg=1>
<RefPosition #229 @171 RefTypeUse <Ivl:6 V06> LCL_VAR BB01 regmask=[allInt] minReg=1 last regOptional>
-----------------
<RefPosition #218 @154 RefTypeDef <Ivl:7 V07> STORE_LCL_VAR BB01 regmask=[allInt] minReg=1>
<RefPosition #232 @175 RefTypeUse <Ivl:7 V07> LCL_VAR BB01 regmask=[allInt] minReg=1 last regOptional>
-----------------
<RefPosition #202 @134 RefTypeDef <Ivl:11 V14> STORE_LCL_VAR BB01 regmask=[allInt] minReg=1>
<RefPosition #208 @149 RefTypeUse <Ivl:11 V14> LCL_VAR BB01 regmask=[allInt] minReg=1 last>
TUPLE STYLE DUMP WITH REF POSITIONS
Incoming Parameters: V00 V01 V02
BB01 [000..051) (return), preds={} succs={}
=====
N003. V02(L2)
N005. CAST
Use:<V02/L2>(#4) *
Def:<I14>(#5) Pref:<V19/L13>
N007. V19(L13)
Use:<I14>(#6) *
Def:<V19/L13>(#7) Pref:<I46>
N009. V19(L13)
N011. PUTARG_REG
Use:<V19/L13>(#9) Fixed:r8(#8)
Def:<I15>(#11) r8 Pref:<V19/L13>
N013. V00(L0)
N015. PUTARG_REG
Use:<V00/L0>(#13) Fixed:rcx(#12)
Def:<I16>(#15) rcx Pref:<V00/L0>
N017. V01(L1)
N019. PUTARG_REG
Use:<V01/L1>(#17) Fixed:rdx(#16)
Def:<I17>(#19) rdx Pref:<V01/L1>
N021. CALL
Use:<I15>(#21) Fixed:r8(#20) *
Use:<I16>(#23) Fixed:rcx(#22) *
Use:<I17>(#25) Fixed:rdx(#24) *
Kill: rax rcx rdx r8 r9 r10 r11
Def:<I18>(#34) rax Pref:<V10/L8>
N023. V10(L8)
Use:<I18>(#35) *
Def:<V10/L8>(#36) Pref:<I49>
N025. V19(L13)
N027. PUTARG_REG
Use:<V19/L13>(#38) Fixed:r9(#37)
Def:<I19>(#40) r9 Pref:<V19/L13>
N029. V00(L0)
N031. PUTARG_REG
Use:<V00/L0>(#42) Fixed:rdx(#41)
Def:<I20>(#44) rdx Pref:<V00/L0>
N033. V01(L1)
N035. PUTARG_REG
Use:<V01/L1>(#46) Fixed:r8(#45)
Def:<I21>(#48) r8 Pref:<V01/L1>
N037. CNS_INT(h) 0xd1ffab1e method
Def:<I22>(#49)
N039. PUTARG_REG
Use:<I22>(#51) Fixed:rcx(#50) *
Def:<I23>(#53) rcx
N041. CALL
Use:<I19>(#55) Fixed:r9(#54) *
Use:<I20>(#57) Fixed:rdx(#56) *
Use:<I21>(#59) Fixed:r8(#58) *
Use:<I23>(#61) Fixed:rcx(#60) *
Kill: rax rcx rdx r8 r9 r10 r11
Def:<I24>(#70) rax Pref:<V03/L3>
N043. V03(L3)
Use:<I24>(#71) *
Def:<V03/L3>(#72) Pref:<I49>
N045. CNS_INT 0
N047. LCL_VAR_ADDR V08 loc5 d:2 NA
N049. STOREIND
N051. V19(L13)
N053. PUTARG_REG
Use:<V19/L13>(#74) Fixed:r9(#73)
Def:<I25>(#76) r9 Pref:<V19/L13>
N055. V08 MEM
Def:<I26>(#77)
N057. PUTARG_REG
Use:<I26>(#79) Fixed:rcx(#78) *
Def:<I27>(#81) rcx
N059. V00(L0)
N061. PUTARG_REG
Use:<V00/L0>(#83) Fixed:rdx(#82)
Def:<I28>(#85) rdx Pref:<V00/L0>
N063. V01(L1)
N065. PUTARG_REG
Use:<V01/L1>(#87) Fixed:r8(#86)
Def:<I29>(#89) r8 Pref:<V01/L1>
N067. CALL
Use:<I25>(#91) Fixed:r9(#90) *
Use:<I27>(#93) Fixed:rcx(#92) *
Use:<I28>(#95) Fixed:rdx(#94) *
Use:<I29>(#97) Fixed:r8(#96) *
Kill: rax rcx rdx r8 r9 r10 r11
Def:<I30>(#106) rax Pref:<V04/L4>
N069. V04(L4)
Use:<I30>(#107) *
Def:<V04/L4>(#108) Pref:<I50>
N071. CNS_INT(h) 0xd1ffab1e method
Def:<I31>(#109)
N073. PUTARG_REG
Use:<I31>(#111) Fixed:rcx(#110) *
Def:<I32>(#113) rcx
N075. CALL help
Use:<I32>(#115) Fixed:rcx(#114) *
Kill: rax rcx rdx r8 r9 r10 r11
Def:<I33>(#124) rax Pref:<V11/L9>
N077. V11(L9)
Use:<I33>(#125) *
Def:<V11/L9>(#126)
N079. V19(L13)
N081. PUTARG_STK [+0x20]
Use:<V19/L13>(#127)
N083. V11(L9)
N085. PUTARG_REG
Use:<V11/L9>(#129) Fixed:rdx(#128) *
Def:<I34>(#131) rdx
N087. V00(L0)
N089. PUTARG_REG
Use:<V00/L0>(#133) Fixed:r8(#132)
Def:<I35>(#135) r8 Pref:<V00/L0>
N091. V01(L1)
N093. PUTARG_REG
Use:<V01/L1>(#137) Fixed:r9(#136)
Def:<I36>(#139) r9 Pref:<V01/L1>
N095. CNS_INT(h) 0xd1ffab1e method
Def:<I37>(#140)
N097. PUTARG_REG
Use:<I37>(#142) Fixed:rcx(#141) *
Def:<I38>(#144) rcx
N099. CALL
Use:<I34>(#146) Fixed:rdx(#145) *
Use:<I35>(#148) Fixed:r8(#147) *
Use:<I36>(#150) Fixed:r9(#149) *
Use:<I38>(#152) Fixed:rcx(#151) *
Kill: rax rcx rdx r8 r9 r10 r11
Def:<I39>(#161) rax Pref:<V05/L5>
N101. V05(L5)
Use:<I39>(#162) *
Def:<V05/L5>(#163) Pref:<I51>
N103. V19(L13)
N105. PUTARG_REG
Use:<V19/L13>(#165) Fixed:r8(#164)
Def:<I40>(#167) r8 Pref:<V19/L13>
N107. V00(L0)
N109. PUTARG_REG
Use:<V00/L0>(#169) Fixed:rcx(#168)
Def:<I41>(#171) rcx Pref:<V00/L0>
N111. V01(L1)
N113. PUTARG_REG
Use:<V01/L1>(#173) Fixed:rdx(#172)
Def:<I42>(#175) rdx Pref:<V01/L1>
N115. CALL
Use:<I40>(#177) Fixed:r8(#176) *
Use:<I41>(#179) Fixed:rcx(#178) *
Use:<I42>(#181) Fixed:rdx(#180) *
Kill: rax rcx rdx r8 r9 r10 r11
Def:<I43>(#190) rax Pref:<V06/L6>
N117. V06(L6)
Use:<I43>(#191) *
Def:<V06/L6>(#192) Pref:<I52>
N119. V00(L0)
N121. V01(L1)
N123. ADD
Use:<V00/L0>(#193)
Use:<V01/L1>(#194) *
Def:<I44>(#195) Pref:<V13/L10>
N125. V13(L10)
Use:<I44>(#196) *
Def:<V13/L10>(#197) Pref:<I45>
N127. V13(L10)
N129. V19(L13)
N131. MUL
Use:<V13/L10>(#198) *
Use:<V19/L13>(#199)
Def:<I45>(#200) Pref:<V14/L11>
N133. V14(L11)
Use:<I45>(#201) *
Def:<V14/L11>(#202) Pref:<I47>
N135. V00(L0)
N137. V19(L13)
N139. MUL
Use:<V00/L0>(#203) *
Use:<V19/L13>(#204) *
Def:<I46>(#205) Pref:<V15/L12>
N141. V15(L12)
Use:<I46>(#206) *
Def:<V15/L12>(#207) Pref:<I48>
N143. V15(L12)
N145. V14(L11)
N147. CNS_INT 2
N149. RSH
Use:<V14/L11>(#208) *
Def:<I47>(#209)
N151. DIV
Use:<V15/L12>(#211) Fixed:rax(#210) *
Use:<I47>(#212) *
Kill: rax rdx
Def:<I48>(#216) rax Pref:<V07/L7>
N153. V07(L7)
Use:<I48>(#217) *
Def:<V07/L7>(#218) Pref:<I53>
N155. V10(L8)
N157. V03(L3)
N159. ADD
Use:<V10/L8>(#219) *
Use:<V03/L3>(#220) *
Def:<I49>(#221) Pref:<I50>
N161. V04(L4)
N163. ADD
Use:<I49>(#222) *
Use:<V04/L4>(#223) *
Def:<I50>(#224) Pref:<I51>
N165. V05(L5)
N167. ADD
Use:<I50>(#225) *
Use:<V05/L5>(#226) *
Def:<I51>(#227) Pref:<I52>
N169. V06(L6)
N171. ADD
Use:<I51>(#228) *
Use:<V06/L6>(#229) *
Def:<I52>(#230) Pref:<I53>
N173. V07(L7)
N175. ADD
Use:<I52>(#231) *
Use:<V07/L7>(#232) *
Def:<I53>(#233)
N177. RETURN
Use:<I53>(#235) Fixed:rax(#234) *
Linear scan intervals after buildIntervals:
Interval 0: (V00) int RefPositions {#0@0 #13@15 #42@31 #83@61 #133@89 #169@109 #193@123 #203@139} physReg:rcx Preferences=[rbx rbp rsi rdi r12-r15] RelatedInterval <I46>
Interval 1: (V01) int RefPositions {#1@0 #17@19 #46@35 #87@65 #137@93 #173@113 #194@123} physReg:rdx Preferences=[rbx rbp rsi rdi r12-r15] RelatedInterval <I44>
Interval 2: (V02) int RefPositions {#2@0 #4@5} physReg:r8 Preferences=[r8]
Interval 3: (V03) int RefPositions {#72@44 #220@159} physReg:NA Preferences=[rbx rbp rsi rdi r12-r15] RelatedInterval <I49>
Interval 4: (V04) int RefPositions {#108@70 #223@163} physReg:NA Preferences=[rbx rbp rsi rdi r12-r15] RelatedInterval <I50>
Interval 5: (V05) int RefPositions {#163@102 #226@167} physReg:NA Preferences=[rbx rbp rsi rdi r12-r15] RelatedInterval <I51>
Interval 6: (V06) int RefPositions {#192@118 #229@171} physReg:NA Preferences=[rcx rbx rbp rsi rdi r8-r15] RelatedInterval <I52>
Interval 7: (V07) int RefPositions {#218@154 #232@175} physReg:NA Preferences=[allInt] RelatedInterval <I53>
Interval 8: (V10) int RefPositions {#36@24 #219@159} physReg:NA Preferences=[rbx rbp rsi rdi r12-r15] RelatedInterval <I49>
Interval 9: (V11) ref RefPositions {#126@78 #129@85} physReg:NA Preferences=[rdx]
Interval 10: (V13) int RefPositions {#197@126 #198@131} physReg:NA Preferences=[allInt] RelatedInterval <I45>
Interval 11: (V14) int RefPositions {#202@134 #208@149} physReg:NA Preferences=[allInt] RelatedInterval <I47>
Interval 12: (V15) int RefPositions {#207@142 #211@151} physReg:NA Preferences=[rax] RelatedInterval <I48>
Interval 13: (V19) int RefPositions {#7@8 #9@11 #38@27 #74@53 #127@81 #165@105 #199@131 #204@139} physReg:NA Preferences=[rbx rbp rsi rdi r12-r15] RelatedInterval <I46>
Interval 14: int RefPositions {#5@6 #6@7} physReg:NA Preferences=[allInt] RelatedInterval <V19/L13>
Interval 15: int (specialPutArg) RefPositions {#11@12 #21@21} physReg:NA Preferences=[r8] RelatedInterval <V19/L13>
Interval 16: int (specialPutArg) RefPositions {#15@16 #23@21} physReg:NA Preferences=[rcx] RelatedInterval <V00/L0>
Interval 17: int (specialPutArg) RefPositions {#19@20 #25@21} physReg:NA Preferences=[rdx] RelatedInterval <V01/L1>
Interval 18: int RefPositions {#34@22 #35@23} physReg:NA Preferences=[rax] RelatedInterval <V10/L8>
Interval 19: int (specialPutArg) RefPositions {#40@28 #55@41} physReg:NA Preferences=[r9] RelatedInterval <V19/L13>
Interval 20: int (specialPutArg) RefPositions {#44@32 #57@41} physReg:NA Preferences=[rdx] RelatedInterval <V00/L0>
Interval 21: int (specialPutArg) RefPositions {#48@36 #59@41} physReg:NA Preferences=[r8] RelatedInterval <V01/L1>
Interval 22: long (constant) RefPositions {#49@38 #51@39} physReg:NA Preferences=[rcx]
Interval 23: long RefPositions {#53@40 #61@41} physReg:NA Preferences=[rcx]
Interval 24: int RefPositions {#70@42 #71@43} physReg:NA Preferences=[rax] RelatedInterval <V03/L3>
Interval 25: int (specialPutArg) RefPositions {#76@54 #91@67} physReg:NA Preferences=[r9] RelatedInterval <V19/L13>
Interval 26: byte RefPositions {#77@56 #79@57} physReg:NA Preferences=[rcx]
Interval 27: int RefPositions {#81@58 #93@67} physReg:NA Preferences=[rcx]
Interval 28: int (specialPutArg) RefPositions {#85@62 #95@67} physReg:NA Preferences=[rdx] RelatedInterval <V00/L0>
Interval 29: int (specialPutArg) RefPositions {#89@66 #97@67} physReg:NA Preferences=[r8] RelatedInterval <V01/L1>
Interval 30: int RefPositions {#106@68 #107@69} physReg:NA Preferences=[rax] RelatedInterval <V04/L4>
Interval 31: long (constant) RefPositions {#109@72 #111@73} physReg:NA Preferences=[rcx]
Interval 32: long RefPositions {#113@74 #115@75} physReg:NA Preferences=[rcx]
Interval 33: ref RefPositions {#124@76 #125@77} physReg:NA Preferences=[rax] RelatedInterval <V11/L9>
Interval 34: ref RefPositions {#131@86 #146@99} physReg:NA Preferences=[rdx]
Interval 35: int (specialPutArg) RefPositions {#135@90 #148@99} physReg:NA Preferences=[r8] RelatedInterval <V00/L0>
Interval 36: int (specialPutArg) RefPositions {#139@94 #150@99} physReg:NA Preferences=[r9] RelatedInterval <V01/L1>
Interval 37: long (constant) RefPositions {#140@96 #142@97} physReg:NA Preferences=[rcx]
Interval 38: long RefPositions {#144@98 #152@99} physReg:NA Preferences=[rcx]
Interval 39: int RefPositions {#161@100 #162@101} physReg:NA Preferences=[rax] RelatedInterval <V05/L5>
Interval 40: int (specialPutArg) RefPositions {#167@106 #177@115} physReg:NA Preferences=[r8] RelatedInterval <V19/L13>
Interval 41: int (specialPutArg) RefPositions {#171@110 #179@115} physReg:NA Preferences=[rcx] RelatedInterval <V00/L0>
Interval 42: int (specialPutArg) RefPositions {#175@114 #181@115} physReg:NA Preferences=[rdx] RelatedInterval <V01/L1>
Interval 43: int RefPositions {#190@116 #191@117} physReg:NA Preferences=[rax] RelatedInterval <V06/L6>
Interval 44: int RefPositions {#195@124 #196@125} physReg:NA Preferences=[allInt] RelatedInterval <V13/L10>
Interval 45: int RefPositions {#200@132 #201@133} physReg:NA Preferences=[allInt] RelatedInterval <V14/L11>
Interval 46: int RefPositions {#205@140 #206@141} physReg:NA Preferences=[allInt] RelatedInterval <V15/L12>
Interval 47: int RefPositions {#209@150 #212@151} physReg:NA Preferences=[rcx rbx rbp rsi rdi r8-r15]
Interval 48: int (interfering uses) RefPositions {#216@152 #217@153} physReg:NA Preferences=[rax] RelatedInterval <V07/L7>
Interval 49: int RefPositions {#221@160 #222@163} physReg:NA Preferences=[allInt] RelatedInterval <I50>
Interval 50: int RefPositions {#224@164 #225@167} physReg:NA Preferences=[allInt] RelatedInterval <I51>
Interval 51: int RefPositions {#227@168 #228@171} physReg:NA Preferences=[allInt] RelatedInterval <I52>
Interval 52: int RefPositions {#230@172 #231@175} physReg:NA Preferences=[allInt] RelatedInterval <I53>
Interval 53: int RefPositions {#233@176 #235@177} physReg:NA Preferences=[rax]
*************** In LinearScan::allocateRegisters()
Linear scan intervals before allocateRegisters:
Interval 0: (V00) int RefPositions {#0@0 #13@15 #42@31 #83@61 #133@89 #169@109 #193@123 #203@139} physReg:rcx Preferences=[rbx rbp rsi rdi r12-r15] RelatedInterval <I46>
Interval 1: (V01) int RefPositions {#1@0 #17@19 #46@35 #87@65 #137@93 #173@113 #194@123} physReg:rdx Preferences=[rbx rbp rsi rdi r12-r15] RelatedInterval <I44>
Interval 2: (V02) int RefPositions {#2@0 #4@5} physReg:r8 Preferences=[r8]
Interval 3: (V03) int RefPositions {#72@44 #220@159} physReg:NA Preferences=[rbx rbp rsi rdi r12-r15] RelatedInterval <I49>
Interval 4: (V04) int RefPositions {#108@70 #223@163} physReg:NA Preferences=[rbx rbp rsi rdi r12-r15] RelatedInterval <I50>
Interval 5: (V05) int RefPositions {#163@102 #226@167} physReg:NA Preferences=[rbx rbp rsi rdi r12-r15] RelatedInterval <I51>
Interval 6: (V06) int RefPositions {#192@118 #229@171} physReg:NA Preferences=[rcx rbx rbp rsi rdi r8-r15] RelatedInterval <I52>
Interval 7: (V07) int RefPositions {#218@154 #232@175} physReg:NA Preferences=[allInt] RelatedInterval <I53>
Interval 8: (V10) int RefPositions {#36@24 #219@159} physReg:NA Preferences=[rbx rbp rsi rdi r12-r15] RelatedInterval <I49>
Interval 9: (V11) ref RefPositions {#126@78 #129@85} physReg:NA Preferences=[rdx]
Interval 10: (V13) int RefPositions {#197@126 #198@131} physReg:NA Preferences=[allInt] RelatedInterval <I45>
Interval 11: (V14) int RefPositions {#202@134 #208@149} physReg:NA Preferences=[allInt] RelatedInterval <I47>
Interval 12: (V15) int RefPositions {#207@142 #211@151} physReg:NA Preferences=[rax] RelatedInterval <I48>
Interval 13: (V19) int RefPositions {#7@8 #9@11 #38@27 #74@53 #127@81 #165@105 #199@131 #204@139} physReg:NA Preferences=[rbx rbp rsi rdi r12-r15] RelatedInterval <I46>
Interval 14: int RefPositions {#5@6 #6@7} physReg:NA Preferences=[allInt] RelatedInterval <V19/L13>
Interval 15: int (specialPutArg) RefPositions {#11@12 #21@21} physReg:NA Preferences=[r8] RelatedInterval <V19/L13>
Interval 16: int (specialPutArg) RefPositions {#15@16 #23@21} physReg:NA Preferences=[rcx] RelatedInterval <V00/L0>
Interval 17: int (specialPutArg) RefPositions {#19@20 #25@21} physReg:NA Preferences=[rdx] RelatedInterval <V01/L1>
Interval 18: int RefPositions {#34@22 #35@23} physReg:NA Preferences=[rax] RelatedInterval <V10/L8>
Interval 19: int (specialPutArg) RefPositions {#40@28 #55@41} physReg:NA Preferences=[r9] RelatedInterval <V19/L13>
Interval 20: int (specialPutArg) RefPositions {#44@32 #57@41} physReg:NA Preferences=[rdx] RelatedInterval <V00/L0>
Interval 21: int (specialPutArg) RefPositions {#48@36 #59@41} physReg:NA Preferences=[r8] RelatedInterval <V01/L1>
Interval 22: long (constant) RefPositions {#49@38 #51@39} physReg:NA Preferences=[rcx]
Interval 23: long RefPositions {#53@40 #61@41} physReg:NA Preferences=[rcx]
Interval 24: int RefPositions {#70@42 #71@43} physReg:NA Preferences=[rax] RelatedInterval <V03/L3>
Interval 25: int (specialPutArg) RefPositions {#76@54 #91@67} physReg:NA Preferences=[r9] RelatedInterval <V19/L13>
Interval 26: byte RefPositions {#77@56 #79@57} physReg:NA Preferences=[rcx]
Interval 27: int RefPositions {#81@58 #93@67} physReg:NA Preferences=[rcx]
Interval 28: int (specialPutArg) RefPositions {#85@62 #95@67} physReg:NA Preferences=[rdx] RelatedInterval <V00/L0>
Interval 29: int (specialPutArg) RefPositions {#89@66 #97@67} physReg:NA Preferences=[r8] RelatedInterval <V01/L1>
Interval 30: int RefPositions {#106@68 #107@69} physReg:NA Preferences=[rax] RelatedInterval <V04/L4>
Interval 31: long (constant) RefPositions {#109@72 #111@73} physReg:NA Preferences=[rcx]
Interval 32: long RefPositions {#113@74 #115@75} physReg:NA Preferences=[rcx]
Interval 33: ref RefPositions {#124@76 #125@77} physReg:NA Preferences=[rax] RelatedInterval <V11/L9>
Interval 34: ref RefPositions {#131@86 #146@99} physReg:NA Preferences=[rdx]
Interval 35: int (specialPutArg) RefPositions {#135@90 #148@99} physReg:NA Preferences=[r8] RelatedInterval <V00/L0>
Interval 36: int (specialPutArg) RefPositions {#139@94 #150@99} physReg:NA Preferences=[r9] RelatedInterval <V01/L1>
Interval 37: long (constant) RefPositions {#140@96 #142@97} physReg:NA Preferences=[rcx]
Interval 38: long RefPositions {#144@98 #152@99} physReg:NA Preferences=[rcx]
Interval 39: int RefPositions {#161@100 #162@101} physReg:NA Preferences=[rax] RelatedInterval <V05/L5>
Interval 40: int (specialPutArg) RefPositions {#167@106 #177@115} physReg:NA Preferences=[r8] RelatedInterval <V19/L13>
Interval 41: int (specialPutArg) RefPositions {#171@110 #179@115} physReg:NA Preferences=[rcx] RelatedInterval <V00/L0>
Interval 42: int (specialPutArg) RefPositions {#175@114 #181@115} physReg:NA Preferences=[rdx] RelatedInterval <V01/L1>
Interval 43: int RefPositions {#190@116 #191@117} physReg:NA Preferences=[rax] RelatedInterval <V06/L6>
Interval 44: int RefPositions {#195@124 #196@125} physReg:NA Preferences=[allInt] RelatedInterval <V13/L10>
Interval 45: int RefPositions {#200@132 #201@133} physReg:NA Preferences=[allInt] RelatedInterval <V14/L11>
Interval 46: int RefPositions {#205@140 #206@141} physReg:NA Preferences=[allInt] RelatedInterval <V15/L12>
Interval 47: int RefPositions {#209@150 #212@151} physReg:NA Preferences=[rcx rbx rbp rsi rdi r8-r15]
Interval 48: int (interfering uses) RefPositions {#216@152 #217@153} physReg:NA Preferences=[rax] RelatedInterval <V07/L7>
Interval 49: int RefPositions {#221@160 #222@163} physReg:NA Preferences=[allInt] RelatedInterval <I50>
Interval 50: int RefPositions {#224@164 #225@167} physReg:NA Preferences=[allInt] RelatedInterval <I51>
Interval 51: int RefPositions {#227@168 #228@171} physReg:NA Preferences=[allInt] RelatedInterval <I52>
Interval 52: int RefPositions {#230@172 #231@175} physReg:NA Preferences=[allInt] RelatedInterval <I53>
Interval 53: int RefPositions {#233@176 #235@177} physReg:NA Preferences=[rax]
------------
REFPOSITIONS BEFORE ALLOCATION:
------------
<RefPosition #0 @0 RefTypeParamDef <Ivl:0 V00> BB00 regmask=[rcx] minReg=1 fixed regOptional>
<RefPosition #1 @0 RefTypeParamDef <Ivl:1 V01> BB00 regmask=[rdx] minReg=1 fixed regOptional>
<RefPosition #2 @0 RefTypeParamDef <Ivl:2 V02> BB00 regmask=[r8] minReg=1 fixed regOptional>
<RefPosition #3 @1 RefTypeBB BB01 regmask=[] minReg=1>
<RefPosition #4 @5 RefTypeUse <Ivl:2 V02> LCL_VAR BB01 regmask=[allInt] minReg=1 last>
<RefPosition #5 @6 RefTypeDef <Ivl:14> CAST BB01 regmask=[allInt] minReg=1>
<RefPosition #6 @7 RefTypeUse <Ivl:14> BB01 regmask=[allInt] minReg=1 last>
<RefPosition #7 @8 RefTypeDef <Ivl:13 V19> STORE_LCL_VAR BB01 regmask=[allInt] minReg=1>
<RefPosition #8 @11 RefTypeFixedReg <Reg:r8 > BB01 regmask=[r8] minReg=1>
<RefPosition #9 @11 RefTypeUse <Ivl:13 V19> LCL_VAR BB01 regmask=[r8] minReg=1 fixed>
<RefPosition #10 @12 RefTypeFixedReg <Reg:r8 > BB01 regmask=[r8] minReg=1>
<RefPosition #11 @12 RefTypeDef <Ivl:15> PUTARG_REG BB01 regmask=[r8] minReg=1 fixed>
<RefPosition #12 @15 RefTypeFixedReg <Reg:rcx> BB01 regmask=[rcx] minReg=1>
<RefPosition #13 @15 RefTypeUse <Ivl:0 V00> LCL_VAR BB01 regmask=[rcx] minReg=1 fixed>
<RefPosition #14 @16 RefTypeFixedReg <Reg:rcx> BB01 regmask=[rcx] minReg=1>
<RefPosition #15 @16 RefTypeDef <Ivl:16> PUTARG_REG BB01 regmask=[rcx] minReg=1 fixed>
<RefPosition #16 @19 RefTypeFixedReg <Reg:rdx> BB01 regmask=[rdx] minReg=1>
<RefPosition #17 @19 RefTypeUse <Ivl:1 V01> LCL_VAR BB01 regmask=[rdx] minReg=1 fixed>
<RefPosition #18 @20 RefTypeFixedReg <Reg:rdx> BB01 regmask=[rdx] minReg=1>
<RefPosition #19 @20 RefTypeDef <Ivl:17> PUTARG_REG BB01 regmask=[rdx] minReg=1 fixed>
<RefPosition #20 @21 RefTypeFixedReg <Reg:r8 > BB01 regmask=[r8] minReg=1>
<RefPosition #21 @21 RefTypeUse <Ivl:15> BB01 regmask=[r8] minReg=1 last fixed>
<RefPosition #22 @21 RefTypeFixedReg <Reg:rcx> BB01 regmask=[rcx] minReg=1>
<RefPosition #23 @21 RefTypeUse <Ivl:16> BB01 regmask=[rcx] minReg=1 last fixed>
<RefPosition #24 @21 RefTypeFixedReg <Reg:rdx> BB01 regmask=[rdx] minReg=1>
<RefPosition #25 @21 RefTypeUse <Ivl:17> BB01 regmask=[rdx] minReg=1 last fixed>
<RefPosition #26 @22 RefTypeKill <Reg:rax> BB01 regmask=[rax] minReg=1 last>
<RefPosition #27 @22 RefTypeKill <Reg:rcx> BB01 regmask=[rcx] minReg=1 last>
<RefPosition #28 @22 RefTypeKill <Reg:rdx> BB01 regmask=[rdx] minReg=1 last>
<RefPosition #29 @22 RefTypeKill <Reg:r8 > BB01 regmask=[r8] minReg=1 last>
<RefPosition #30 @22 RefTypeKill <Reg:r9 > BB01 regmask=[r9] minReg=1 last>
<RefPosition #31 @22 RefTypeKill <Reg:r10> BB01 regmask=[r10] minReg=1 last>
<RefPosition #32 @22 RefTypeKill <Reg:r11> BB01 regmask=[r11] minReg=1 last>
<RefPosition #33 @22 RefTypeFixedReg <Reg:rax> BB01 regmask=[rax] minReg=1>
<RefPosition #34 @22 RefTypeDef <Ivl:18> CALL BB01 regmask=[rax] minReg=1 fixed>
<RefPosition #35 @23 RefTypeUse <Ivl:18> BB01 regmask=[allInt] minReg=1 last>
<RefPosition #36 @24 RefTypeDef <Ivl:8 V10> STORE_LCL_VAR BB01 regmask=[allInt] minReg=1>
<RefPosition #37 @27 RefTypeFixedReg <Reg:r9 > BB01 regmask=[r9] minReg=1>
<RefPosition #38 @27 RefTypeUse <Ivl:13 V19> LCL_VAR BB01 regmask=[r9] minReg=1 fixed>
<RefPosition #39 @28 RefTypeFixedReg <Reg:r9 > BB01 regmask=[r9] minReg=1>
<RefPosition #40 @28 RefTypeDef <Ivl:19> PUTARG_REG BB01 regmask=[r9] minReg=1 fixed>
<RefPosition #41 @31 RefTypeFixedReg <Reg:rdx> BB01 regmask=[rdx] minReg=1>
<RefPosition #42 @31 RefTypeUse <Ivl:0 V00> LCL_VAR BB01 regmask=[rdx] minReg=1 fixed>
<RefPosition #43 @32 RefTypeFixedReg <Reg:rdx> BB01 regmask=[rdx] minReg=1>
<RefPosition #44 @32 RefTypeDef <Ivl:20> PUTARG_REG BB01 regmask=[rdx] minReg=1 fixed>
<RefPosition #45 @35 RefTypeFixedReg <Reg:r8 > BB01 regmask=[r8] minReg=1>
<RefPosition #46 @35 RefTypeUse <Ivl:1 V01> LCL_VAR BB01 regmask=[r8] minReg=1 fixed>
<RefPosition #47 @36 RefTypeFixedReg <Reg:r8 > BB01 regmask=[r8] minReg=1>
<RefPosition #48 @36 RefTypeDef <Ivl:21> PUTARG_REG BB01 regmask=[r8] minReg=1 fixed>
<RefPosition #49 @38 RefTypeDef <Ivl:22> CNS_INT BB01 regmask=[rcx] minReg=1>
<RefPosition #50 @39 RefTypeFixedReg <Reg:rcx> BB01 regmask=[rcx] minReg=1>
<RefPosition #51 @39 RefTypeUse <Ivl:22> BB01 regmask=[rcx] minReg=1 last fixed>
<RefPosition #52 @40 RefTypeFixedReg <Reg:rcx> BB01 regmask=[rcx] minReg=1>
<RefPosition #53 @40 RefTypeDef <Ivl:23> PUTARG_REG BB01 regmask=[rcx] minReg=1 fixed>
<RefPosition #54 @41 RefTypeFixedReg <Reg:r9 > BB01 regmask=[r9] minReg=1>
<RefPosition #55 @41 RefTypeUse <Ivl:19> BB01 regmask=[r9] minReg=1 last fixed>
<RefPosition #56 @41 RefTypeFixedReg <Reg:rdx> BB01 regmask=[rdx] minReg=1>
<RefPosition #57 @41 RefTypeUse <Ivl:20> BB01 regmask=[rdx] minReg=1 last fixed>
<RefPosition #58 @41 RefTypeFixedReg <Reg:r8 > BB01 regmask=[r8] minReg=1>
<RefPosition #59 @41 RefTypeUse <Ivl:21> BB01 regmask=[r8] minReg=1 last fixed>
<RefPosition #60 @41 RefTypeFixedReg <Reg:rcx> BB01 regmask=[rcx] minReg=1>
<RefPosition #61 @41 RefTypeUse <Ivl:23> BB01 regmask=[rcx] minReg=1 last fixed>
<RefPosition #62 @42 RefTypeKill <Reg:rax> BB01 regmask=[rax] minReg=1 last>
<RefPosition #63 @42 RefTypeKill <Reg:rcx> BB01 regmask=[rcx] minReg=1 last>
<RefPosition #64 @42 RefTypeKill <Reg:rdx> BB01 regmask=[rdx] minReg=1 last>
<RefPosition #65 @42 RefTypeKill <Reg:r8 > BB01 regmask=[r8] minReg=1 last>
<RefPosition #66 @42 RefTypeKill <Reg:r9 > BB01 regmask=[r9] minReg=1 last>
<RefPosition #67 @42 RefTypeKill <Reg:r10> BB01 regmask=[r10] minReg=1 last>
<RefPosition #68 @42 RefTypeKill <Reg:r11> BB01 regmask=[r11] minReg=1 last>
<RefPosition #69 @42 RefTypeFixedReg <Reg:rax> BB01 regmask=[rax] minReg=1>
<RefPosition #70 @42 RefTypeDef <Ivl:24> CALL BB01 regmask=[rax] minReg=1 fixed>
<RefPosition #71 @43 RefTypeUse <Ivl:24> BB01 regmask=[allInt] minReg=1 last>
<RefPosition #72 @44 RefTypeDef <Ivl:3 V03> STORE_LCL_VAR BB01 regmask=[allInt] minReg=1>
<RefPosition #73 @53 RefTypeFixedReg <Reg:r9 > BB01 regmask=[r9] minReg=1>
<RefPosition #74 @53 RefTypeUse <Ivl:13 V19> LCL_VAR BB01 regmask=[r9] minReg=1 fixed>
<RefPosition #75 @54 RefTypeFixedReg <Reg:r9 > BB01 regmask=[r9] minReg=1>
<RefPosition #76 @54 RefTypeDef <Ivl:25> PUTARG_REG BB01 regmask=[r9] minReg=1 fixed>
<RefPosition #77 @56 RefTypeDef <Ivl:26> LCL_FLD BB01 regmask=[rcx] minReg=1>
<RefPosition #78 @57 RefTypeFixedReg <Reg:rcx> BB01 regmask=[rcx] minReg=1>
<RefPosition #79 @57 RefTypeUse <Ivl:26> BB01 regmask=[rcx] minReg=1 last fixed>
<RefPosition #80 @58 RefTypeFixedReg <Reg:rcx> BB01 regmask=[rcx] minReg=1>
<RefPosition #81 @58 RefTypeDef <Ivl:27> PUTARG_REG BB01 regmask=[rcx] minReg=1 fixed>
<RefPosition #82 @61 RefTypeFixedReg <Reg:rdx> BB01 regmask=[rdx] minReg=1>
<RefPosition #83 @61 RefTypeUse <Ivl:0 V00> LCL_VAR BB01 regmask=[rdx] minReg=1 fixed>
<RefPosition #84 @62 RefTypeFixedReg <Reg:rdx> BB01 regmask=[rdx] minReg=1>
<RefPosition #85 @62 RefTypeDef <Ivl:28> PUTARG_REG BB01 regmask=[rdx] minReg=1 fixed>
<RefPosition #86 @65 RefTypeFixedReg <Reg:r8 > BB01 regmask=[r8] minReg=1>
<RefPosition #87 @65 RefTypeUse <Ivl:1 V01> LCL_VAR BB01 regmask=[r8] minReg=1 fixed>
<RefPosition #88 @66 RefTypeFixedReg <Reg:r8 > BB01 regmask=[r8] minReg=1>
<RefPosition #89 @66 RefTypeDef <Ivl:29> PUTARG_REG BB01 regmask=[r8] minReg=1 fixed>
<RefPosition #90 @67 RefTypeFixedReg <Reg:r9 > BB01 regmask=[r9] minReg=1>
<RefPosition #91 @67 RefTypeUse <Ivl:25> BB01 regmask=[r9] minReg=1 last fixed>
<RefPosition #92 @67 RefTypeFixedReg <Reg:rcx> BB01 regmask=[rcx] minReg=1>
<RefPosition #93 @67 RefTypeUse <Ivl:27> BB01 regmask=[rcx] minReg=1 last fixed>
<RefPosition #94 @67 RefTypeFixedReg <Reg:rdx> BB01 regmask=[rdx] minReg=1>
<RefPosition #95 @67 RefTypeUse <Ivl:28> BB01 regmask=[rdx] minReg=1 last fixed>
<RefPosition #96 @67 RefTypeFixedReg <Reg:r8 > BB01 regmask=[r8] minReg=1>
<RefPosition #97 @67 RefTypeUse <Ivl:29> BB01 regmask=[r8] minReg=1 last fixed>
<RefPosition #98 @68 RefTypeKill <Reg:rax> BB01 regmask=[rax] minReg=1 last>
<RefPosition #99 @68 RefTypeKill <Reg:rcx> BB01 regmask=[rcx] minReg=1 last>
<RefPosition #100 @68 RefTypeKill <Reg:rdx> BB01 regmask=[rdx] minReg=1 last>
<RefPosition #101 @68 RefTypeKill <Reg:r8 > BB01 regmask=[r8] minReg=1 last>
<RefPosition #102 @68 RefTypeKill <Reg:r9 > BB01 regmask=[r9] minReg=1 last>
<RefPosition #103 @68 RefTypeKill <Reg:r10> BB01 regmask=[r10] minReg=1 last>
<RefPosition #104 @68 RefTypeKill <Reg:r11> BB01 regmask=[r11] minReg=1 last>
<RefPosition #105 @68 RefTypeFixedReg <Reg:rax> BB01 regmask=[rax] minReg=1>
<RefPosition #106 @68 RefTypeDef <Ivl:30> CALL BB01 regmask=[rax] minReg=1 fixed>
<RefPosition #107 @69 RefTypeUse <Ivl:30> BB01 regmask=[allInt] minReg=1 last>
<RefPosition #108 @70 RefTypeDef <Ivl:4 V04> STORE_LCL_VAR BB01 regmask=[allInt] minReg=1>
<RefPosition #109 @72 RefTypeDef <Ivl:31> CNS_INT BB01 regmask=[rcx] minReg=1>
<RefPosition #110 @73 RefTypeFixedReg <Reg:rcx> BB01 regmask=[rcx] minReg=1>
<RefPosition #111 @73 RefTypeUse <Ivl:31> BB01 regmask=[rcx] minReg=1 last fixed>
<RefPosition #112 @74 RefTypeFixedReg <Reg:rcx> BB01 regmask=[rcx] minReg=1>
<RefPosition #113 @74 RefTypeDef <Ivl:32> PUTARG_REG BB01 regmask=[rcx] minReg=1 fixed>
<RefPosition #114 @75 RefTypeFixedReg <Reg:rcx> BB01 regmask=[rcx] minReg=1>
<RefPosition #115 @75 RefTypeUse <Ivl:32> BB01 regmask=[rcx] minReg=1 last fixed>
<RefPosition #116 @76 RefTypeKill <Reg:rax> BB01 regmask=[rax] minReg=1 last>
<RefPosition #117 @76 RefTypeKill <Reg:rcx> BB01 regmask=[rcx] minReg=1 last>
<RefPosition #118 @76 RefTypeKill <Reg:rdx> BB01 regmask=[rdx] minReg=1 last>
<RefPosition #119 @76 RefTypeKill <Reg:r8 > BB01 regmask=[r8] minReg=1 last>
<RefPosition #120 @76 RefTypeKill <Reg:r9 > BB01 regmask=[r9] minReg=1 last>
<RefPosition #121 @76 RefTypeKill <Reg:r10> BB01 regmask=[r10] minReg=1 last>
<RefPosition #122 @76 RefTypeKill <Reg:r11> BB01 regmask=[r11] minReg=1 last>
<RefPosition #123 @76 RefTypeFixedReg <Reg:rax> BB01 regmask=[rax] minReg=1>
<RefPosition #124 @76 RefTypeDef <Ivl:33> CALL BB01 regmask=[rax] minReg=1 fixed>
<RefPosition #125 @77 RefTypeUse <Ivl:33> BB01 regmask=[allInt] minReg=1 last>
<RefPosition #126 @78 RefTypeDef <Ivl:9 V11> STORE_LCL_VAR BB01 regmask=[allInt] minReg=1>
<RefPosition #127 @81 RefTypeUse <Ivl:13 V19> LCL_VAR BB01 regmask=[allInt] minReg=1>
<RefPosition #128 @85 RefTypeFixedReg <Reg:rdx> BB01 regmask=[rdx] minReg=1>
<RefPosition #129 @85 RefTypeUse <Ivl:9 V11> LCL_VAR BB01 regmask=[rdx] minReg=1 last fixed>
<RefPosition #130 @86 RefTypeFixedReg <Reg:rdx> BB01 regmask=[rdx] minReg=1>
<RefPosition #131 @86 RefTypeDef <Ivl:34> PUTARG_REG BB01 regmask=[rdx] minReg=1 fixed>
<RefPosition #132 @89 RefTypeFixedReg <Reg:r8 > BB01 regmask=[r8] minReg=1>
<RefPosition #133 @89 RefTypeUse <Ivl:0 V00> LCL_VAR BB01 regmask=[r8] minReg=1 fixed>
<RefPosition #134 @90 RefTypeFixedReg <Reg:r8 > BB01 regmask=[r8] minReg=1>
<RefPosition #135 @90 RefTypeDef <Ivl:35> PUTARG_REG BB01 regmask=[r8] minReg=1 fixed>
<RefPosition #136 @93 RefTypeFixedReg <Reg:r9 > BB01 regmask=[r9] minReg=1>
<RefPosition #137 @93 RefTypeUse <Ivl:1 V01> LCL_VAR BB01 regmask=[r9] minReg=1 fixed>
<RefPosition #138 @94 RefTypeFixedReg <Reg:r9 > BB01 regmask=[r9] minReg=1>
<RefPosition #139 @94 RefTypeDef <Ivl:36> PUTARG_REG BB01 regmask=[r9] minReg=1 fixed>
<RefPosition #140 @96 RefTypeDef <Ivl:37> CNS_INT BB01 regmask=[rcx] minReg=1>
<RefPosition #141 @97 RefTypeFixedReg <Reg:rcx> BB01 regmask=[rcx] minReg=1>
<RefPosition #142 @97 RefTypeUse <Ivl:37> BB01 regmask=[rcx] minReg=1 last fixed>
<RefPosition #143 @98 RefTypeFixedReg <Reg:rcx> BB01 regmask=[rcx] minReg=1>
<RefPosition #144 @98 RefTypeDef <Ivl:38> PUTARG_REG BB01 regmask=[rcx] minReg=1 fixed>
<RefPosition #145 @99 RefTypeFixedReg <Reg:rdx> BB01 regmask=[rdx] minReg=1>
<RefPosition #146 @99 RefTypeUse <Ivl:34> BB01 regmask=[rdx] minReg=1 last fixed>
<RefPosition #147 @99 RefTypeFixedReg <Reg:r8 > BB01 regmask=[r8] minReg=1>
<RefPosition #148 @99 RefTypeUse <Ivl:35> BB01 regmask=[r8] minReg=1 last fixed>
<RefPosition #149 @99 RefTypeFixedReg <Reg:r9 > BB01 regmask=[r9] minReg=1>
<RefPosition #150 @99 RefTypeUse <Ivl:36> BB01 regmask=[r9] minReg=1 last fixed>
<RefPosition #151 @99 RefTypeFixedReg <Reg:rcx> BB01 regmask=[rcx] minReg=1>
<RefPosition #152 @99 RefTypeUse <Ivl:38> BB01 regmask=[rcx] minReg=1 last fixed>
<RefPosition #153 @100 RefTypeKill <Reg:rax> BB01 regmask=[rax] minReg=1 last>
<RefPosition #154 @100 RefTypeKill <Reg:rcx> BB01 regmask=[rcx] minReg=1 last>
<RefPosition #155 @100 RefTypeKill <Reg:rdx> BB01 regmask=[rdx] minReg=1 last>
<RefPosition #156 @100 RefTypeKill <Reg:r8 > BB01 regmask=[r8] minReg=1 last>
<RefPosition #157 @100 RefTypeKill <Reg:r9 > BB01 regmask=[r9] minReg=1 last>
<RefPosition #158 @100 RefTypeKill <Reg:r10> BB01 regmask=[r10] minReg=1 last>
<RefPosition #159 @100 RefTypeKill <Reg:r11> BB01 regmask=[r11] minReg=1 last>
<RefPosition #160 @100 RefTypeFixedReg <Reg:rax> BB01 regmask=[rax] minReg=1>
<RefPosition #161 @100 RefTypeDef <Ivl:39> CALL BB01 regmask=[rax] minReg=1 fixed>
<RefPosition #162 @101 RefTypeUse <Ivl:39> BB01 regmask=[allInt] minReg=1 last>
<RefPosition #163 @102 RefTypeDef <Ivl:5 V05> STORE_LCL_VAR BB01 regmask=[allInt] minReg=1>
<RefPosition #164 @105 RefTypeFixedReg <Reg:r8 > BB01 regmask=[r8] minReg=1>
<RefPosition #165 @105 RefTypeUse <Ivl:13 V19> LCL_VAR BB01 regmask=[r8] minReg=1 fixed>
<RefPosition #166 @106 RefTypeFixedReg <Reg:r8 > BB01 regmask=[r8] minReg=1>
<RefPosition #167 @106 RefTypeDef <Ivl:40> PUTARG_REG BB01 regmask=[r8] minReg=1 fixed>
<RefPosition #168 @109 RefTypeFixedReg <Reg:rcx> BB01 regmask=[rcx] minReg=1>
<RefPosition #169 @109 RefTypeUse <Ivl:0 V00> LCL_VAR BB01 regmask=[rcx] minReg=1 fixed>
<RefPosition #170 @110 RefTypeFixedReg <Reg:rcx> BB01 regmask=[rcx] minReg=1>
<RefPosition #171 @110 RefTypeDef <Ivl:41> PUTARG_REG BB01 regmask=[rcx] minReg=1 fixed>
<RefPosition #172 @113 RefTypeFixedReg <Reg:rdx> BB01 regmask=[rdx] minReg=1>
<RefPosition #173 @113 RefTypeUse <Ivl:1 V01> LCL_VAR BB01 regmask=[rdx] minReg=1 fixed>
<RefPosition #174 @114 RefTypeFixedReg <Reg:rdx> BB01 regmask=[rdx] minReg=1>
<RefPosition #175 @114 RefTypeDef <Ivl:42> PUTARG_REG BB01 regmask=[rdx] minReg=1 fixed>
<RefPosition #176 @115 RefTypeFixedReg <Reg:r8 > BB01 regmask=[r8] minReg=1>
<RefPosition #177 @115 RefTypeUse <Ivl:40> BB01 regmask=[r8] minReg=1 last fixed>
<RefPosition #178 @115 RefTypeFixedReg <Reg:rcx> BB01 regmask=[rcx] minReg=1>
<RefPosition #179 @115 RefTypeUse <Ivl:41> BB01 regmask=[rcx] minReg=1 last fixed>
<RefPosition #180 @115 RefTypeFixedReg <Reg:rdx> BB01 regmask=[rdx] minReg=1>
<RefPosition #181 @115 RefTypeUse <Ivl:42> BB01 regmask=[rdx] minReg=1 last fixed>
<RefPosition #182 @116 RefTypeKill <Reg:rax> BB01 regmask=[rax] minReg=1 last>
<RefPosition #183 @116 RefTypeKill <Reg:rcx> BB01 regmask=[rcx] minReg=1 last>
<RefPosition #184 @116 RefTypeKill <Reg:rdx> BB01 regmask=[rdx] minReg=1 last>
<RefPosition #185 @116 RefTypeKill <Reg:r8 > BB01 regmask=[r8] minReg=1 last>
<RefPosition #186 @116 RefTypeKill <Reg:r9 > BB01 regmask=[r9] minReg=1 last>
<RefPosition #187 @116 RefTypeKill <Reg:r10> BB01 regmask=[r10] minReg=1 last>
<RefPosition #188 @116 RefTypeKill <Reg:r11> BB01 regmask=[r11] minReg=1 last>
<RefPosition #189 @116 RefTypeFixedReg <Reg:rax> BB01 regmask=[rax] minReg=1>
<RefPosition #190 @116 RefTypeDef <Ivl:43> CALL BB01 regmask=[rax] minReg=1 fixed>
<RefPosition #191 @117 RefTypeUse <Ivl:43> BB01 regmask=[allInt] minReg=1 last>
<RefPosition #192 @118 RefTypeDef <Ivl:6 V06> STORE_LCL_VAR BB01 regmask=[allInt] minReg=1>
<RefPosition #193 @123 RefTypeUse <Ivl:0 V00> LCL_VAR BB01 regmask=[allInt] minReg=1>
<RefPosition #194 @123 RefTypeUse <Ivl:1 V01> LCL_VAR BB01 regmask=[allInt] minReg=1 last regOptional>
<RefPosition #195 @124 RefTypeDef <Ivl:44> ADD BB01 regmask=[allInt] minReg=1>
<RefPosition #196 @125 RefTypeUse <Ivl:44> BB01 regmask=[allInt] minReg=1 last>
<RefPosition #197 @126 RefTypeDef <Ivl:10 V13> STORE_LCL_VAR BB01 regmask=[allInt] minReg=1>
<RefPosition #198 @131 RefTypeUse <Ivl:10 V13> LCL_VAR BB01 regmask=[allInt] minReg=1 last regOptional>
<RefPosition #199 @131 RefTypeUse <Ivl:13 V19> LCL_VAR BB01 regmask=[allInt] minReg=1>
<RefPosition #200 @132 RefTypeDef <Ivl:45> MUL BB01 regmask=[allInt] minReg=1>
<RefPosition #201 @133 RefTypeUse <Ivl:45> BB01 regmask=[allInt] minReg=1 last>
<RefPosition #202 @134 RefTypeDef <Ivl:11 V14> STORE_LCL_VAR BB01 regmask=[allInt] minReg=1>
<RefPosition #203 @139 RefTypeUse <Ivl:0 V00> LCL_VAR BB01 regmask=[allInt] minReg=1 last regOptional>
<RefPosition #204 @139 RefTypeUse <Ivl:13 V19> LCL_VAR BB01 regmask=[allInt] minReg=1 last>
<RefPosition #205 @140 RefTypeDef <Ivl:46> MUL BB01 regmask=[allInt] minReg=1>
<RefPosition #206 @141 RefTypeUse <Ivl:46> BB01 regmask=[allInt] minReg=1 last>
<RefPosition #207 @142 RefTypeDef <Ivl:12 V15> STORE_LCL_VAR BB01 regmask=[allInt] minReg=1>
<RefPosition #208 @149 RefTypeUse <Ivl:11 V14> LCL_VAR BB01 regmask=[allInt] minReg=1 last>
<RefPosition #209 @150 RefTypeDef <Ivl:47> RSH BB01 regmask=[rcx rbx rbp rsi rdi r8-r15] minReg=1>
<RefPosition #210 @151 RefTypeFixedReg <Reg:rax> BB01 regmask=[rax] minReg=1>
<RefPosition #211 @151 RefTypeUse <Ivl:12 V15> LCL_VAR BB01 regmask=[rax] minReg=1 last fixed>
<RefPosition #212 @151 RefTypeUse <Ivl:47> BB01 regmask=[rcx rbx rbp rsi rdi r8-r15] minReg=1 last delay regOptional>
<RefPosition #213 @152 RefTypeKill <Reg:rax> BB01 regmask=[rax] minReg=1 last>
<RefPosition #214 @152 RefTypeKill <Reg:rdx> BB01 regmask=[rdx] minReg=1 last>
<RefPosition #215 @152 RefTypeFixedReg <Reg:rax> BB01 regmask=[rax] minReg=1>
<RefPosition #216 @152 RefTypeDef <Ivl:48> DIV BB01 regmask=[rax] minReg=1 fixed>
<RefPosition #217 @153 RefTypeUse <Ivl:48> BB01 regmask=[allInt] minReg=1 last>
<RefPosition #218 @154 RefTypeDef <Ivl:7 V07> STORE_LCL_VAR BB01 regmask=[allInt] minReg=1>
<RefPosition #219 @159 RefTypeUse <Ivl:8 V10> LCL_VAR BB01 regmask=[allInt] minReg=1 last>
<RefPosition #220 @159 RefTypeUse <Ivl:3 V03> LCL_VAR BB01 regmask=[allInt] minReg=1 last regOptional>
<RefPosition #221 @160 RefTypeDef <Ivl:49> ADD BB01 regmask=[allInt] minReg=1>
<RefPosition #222 @163 RefTypeUse <Ivl:49> BB01 regmask=[allInt] minReg=1 last>
<RefPosition #223 @163 RefTypeUse <Ivl:4 V04> LCL_VAR BB01 regmask=[allInt] minReg=1 last regOptional>
<RefPosition #224 @164 RefTypeDef <Ivl:50> ADD BB01 regmask=[allInt] minReg=1>
<RefPosition #225 @167 RefTypeUse <Ivl:50> BB01 regmask=[allInt] minReg=1 last>
<RefPosition #226 @167 RefTypeUse <Ivl:5 V05> LCL_VAR BB01 regmask=[allInt] minReg=1 last regOptional>
<RefPosition #227 @168 RefTypeDef <Ivl:51> ADD BB01 regmask=[allInt] minReg=1>
<RefPosition #228 @171 RefTypeUse <Ivl:51> BB01 regmask=[allInt] minReg=1 last>
<RefPosition #229 @171 RefTypeUse <Ivl:6 V06> LCL_VAR BB01 regmask=[allInt] minReg=1 last regOptional>
<RefPosition #230 @172 RefTypeDef <Ivl:52> ADD BB01 regmask=[allInt] minReg=1>
<RefPosition #231 @175 RefTypeUse <Ivl:52> BB01 regmask=[allInt] minReg=1 last>
<RefPosition #232 @175 RefTypeUse <Ivl:7 V07> LCL_VAR BB01 regmask=[allInt] minReg=1 last regOptional>
<RefPosition #233 @176 RefTypeDef <Ivl:53> ADD BB01 regmask=[rax] minReg=1>
<RefPosition #234 @177 RefTypeFixedReg <Reg:rax> BB01 regmask=[rax] minReg=1>
<RefPosition #235 @177 RefTypeUse <Ivl:53> BB01 regmask=[rax] minReg=1 last fixed>
VAR REFPOSITIONS BEFORE ALLOCATION
--- V00 (Interval 0)
<RefPosition #0 @0 RefTypeParamDef <Ivl:0 V00> BB00 regmask=[rcx] minReg=1 fixed regOptional>
<RefPosition #13 @15 RefTypeUse <Ivl:0 V00> LCL_VAR BB01 regmask=[rcx] minReg=1 fixed>
<RefPosition #42 @31 RefTypeUse <Ivl:0 V00> LCL_VAR BB01 regmask=[rdx] minReg=1 fixed>
<RefPosition #83 @61 RefTypeUse <Ivl:0 V00> LCL_VAR BB01 regmask=[rdx] minReg=1 fixed>
<RefPosition #133 @89 RefTypeUse <Ivl:0 V00> LCL_VAR BB01 regmask=[r8] minReg=1 fixed>
<RefPosition #169 @109 RefTypeUse <Ivl:0 V00> LCL_VAR BB01 regmask=[rcx] minReg=1 fixed>
<RefPosition #193 @123 RefTypeUse <Ivl:0 V00> LCL_VAR BB01 regmask=[allInt] minReg=1>
<RefPosition #203 @139 RefTypeUse <Ivl:0 V00> LCL_VAR BB01 regmask=[allInt] minReg=1 last regOptional>
--- V01 (Interval 1)
<RefPosition #1 @0 RefTypeParamDef <Ivl:1 V01> BB00 regmask=[rdx] minReg=1 fixed regOptional>
<RefPosition #17 @19 RefTypeUse <Ivl:1 V01> LCL_VAR BB01 regmask=[rdx] minReg=1 fixed>
<RefPosition #46 @35 RefTypeUse <Ivl:1 V01> LCL_VAR BB01 regmask=[r8] minReg=1 fixed>
<RefPosition #87 @65 RefTypeUse <Ivl:1 V01> LCL_VAR BB01 regmask=[r8] minReg=1 fixed>
<RefPosition #137 @93 RefTypeUse <Ivl:1 V01> LCL_VAR BB01 regmask=[r9] minReg=1 fixed>
<RefPosition #173 @113 RefTypeUse <Ivl:1 V01> LCL_VAR BB01 regmask=[rdx] minReg=1 fixed>
<RefPosition #194 @123 RefTypeUse <Ivl:1 V01> LCL_VAR BB01 regmask=[allInt] minReg=1 last regOptional>
--- V02 (Interval 2)
<RefPosition #2 @0 RefTypeParamDef <Ivl:2 V02> BB00 regmask=[r8] minReg=1 fixed regOptional>
<RefPosition #4 @5 RefTypeUse <Ivl:2 V02> LCL_VAR BB01 regmask=[allInt] minReg=1 last>
--- V03 (Interval 3)
<RefPosition #72 @44 RefTypeDef <Ivl:3 V03> STORE_LCL_VAR BB01 regmask=[allInt] minReg=1>
<RefPosition #220 @159 RefTypeUse <Ivl:3 V03> LCL_VAR BB01 regmask=[allInt] minReg=1 last regOptional>
--- V04 (Interval 4)
<RefPosition #108 @70 RefTypeDef <Ivl:4 V04> STORE_LCL_VAR BB01 regmask=[allInt] minReg=1>
<RefPosition #223 @163 RefTypeUse <Ivl:4 V04> LCL_VAR BB01 regmask=[allInt] minReg=1 last regOptional>
--- V05 (Interval 5)
<RefPosition #163 @102 RefTypeDef <Ivl:5 V05> STORE_LCL_VAR BB01 regmask=[allInt] minReg=1>
<RefPosition #226 @167 RefTypeUse <Ivl:5 V05> LCL_VAR BB01 regmask=[allInt] minReg=1 last regOptional>
--- V06 (Interval 6)
<RefPosition #192 @118 RefTypeDef <Ivl:6 V06> STORE_LCL_VAR BB01 regmask=[allInt] minReg=1>
<RefPosition #229 @171 RefTypeUse <Ivl:6 V06> LCL_VAR BB01 regmask=[allInt] minReg=1 last regOptional>
--- V07 (Interval 7)
<RefPosition #218 @154 RefTypeDef <Ivl:7 V07> STORE_LCL_VAR BB01 regmask=[allInt] minReg=1>
<RefPosition #232 @175 RefTypeUse <Ivl:7 V07> LCL_VAR BB01 regmask=[allInt] minReg=1 last regOptional>
--- V08
--- V09
--- V10 (Interval 8)
<RefPosition #36 @24 RefTypeDef <Ivl:8 V10> STORE_LCL_VAR BB01 regmask=[allInt] minReg=1>
<RefPosition #219 @159 RefTypeUse <Ivl:8 V10> LCL_VAR BB01 regmask=[allInt] minReg=1 last>
--- V11 (Interval 9)
<RefPosition #126 @78 RefTypeDef <Ivl:9 V11> STORE_LCL_VAR BB01 regmask=[allInt] minReg=1>
<RefPosition #129 @85 RefTypeUse <Ivl:9 V11> LCL_VAR BB01 regmask=[rdx] minReg=1 last fixed>
--- V12
--- V13 (Interval 10)
<RefPosition #197 @126 RefTypeDef <Ivl:10 V13> STORE_LCL_VAR BB01 regmask=[allInt] minReg=1>
<RefPosition #198 @131 RefTypeUse <Ivl:10 V13> LCL_VAR BB01 regmask=[allInt] minReg=1 last regOptional>
--- V14 (Interval 11)
<RefPosition #202 @134 RefTypeDef <Ivl:11 V14> STORE_LCL_VAR BB01 regmask=[allInt] minReg=1>
<RefPosition #208 @149 RefTypeUse <Ivl:11 V14> LCL_VAR BB01 regmask=[allInt] minReg=1 last>
--- V15 (Interval 12)
<RefPosition #207 @142 RefTypeDef <Ivl:12 V15> STORE_LCL_VAR BB01 regmask=[allInt] minReg=1>
<RefPosition #211 @151 RefTypeUse <Ivl:12 V15> LCL_VAR BB01 regmask=[rax] minReg=1 last fixed>
--- V16
--- V17
--- V18
--- V19 (Interval 13)
<RefPosition #7 @8 RefTypeDef <Ivl:13 V19> STORE_LCL_VAR BB01 regmask=[allInt] minReg=1>
<RefPosition #9 @11 RefTypeUse <Ivl:13 V19> LCL_VAR BB01 regmask=[r8] minReg=1 fixed>
<RefPosition #38 @27 RefTypeUse <Ivl:13 V19> LCL_VAR BB01 regmask=[r9] minReg=1 fixed>
<RefPosition #74 @53 RefTypeUse <Ivl:13 V19> LCL_VAR BB01 regmask=[r9] minReg=1 fixed>
<RefPosition #127 @81 RefTypeUse <Ivl:13 V19> LCL_VAR BB01 regmask=[allInt] minReg=1>
<RefPosition #165 @105 RefTypeUse <Ivl:13 V19> LCL_VAR BB01 regmask=[r8] minReg=1 fixed>
<RefPosition #199 @131 RefTypeUse <Ivl:13 V19> LCL_VAR BB01 regmask=[allInt] minReg=1>
<RefPosition #204 @139 RefTypeUse <Ivl:13 V19> LCL_VAR BB01 regmask=[allInt] minReg=1 last>
Allocating Registers
--------------------
The following table has one or more rows for each RefPosition that is handled during allocation.
The first column provides the basic information about the RefPosition, with its type (e.g. Def,
Use, Fixd) followed by a '*' if it is a last use, and a 'D' if it is delayRegFree, and then the
action taken during allocation (e.g. Alloc a new register, or Keep an existing one).
The subsequent columns show the Interval occupying each register, if any, followed by 'a' if it is
active, a 'p' if it is a large vector that has been partially spilled, and 'i'if it is inactive.
Columns are only printed up to the last modifed register, which may increase during allocation,in which case additional columns will appear.
Registers which are not marked modified have ---- in their column.
--------------------------------+----+----+----+----+----+----+
Loc RP# Name Type Action Reg |rax |rcx |rbx |rbp |rsi |rdi |
--------------------------------+----+----+----+----+----+----+
| |V0 a| | | | |
0.#0 V0 Parm Alloc rsi | | | | |V0 a| |
0.#1 V1 Parm Alloc rdi | | | | |V0 a|V1 a|
--------------------------------+----+----+----+----+----+----+----+
Loc RP# Name Type Action Reg |rax |rcx |rbx |rbp |rsi |rdi |r8 |
--------------------------------+----+----+----+----+----+----+----+
0.#2 V2 Parm Keep r8 | | | | |V0 a|V1 a|V2 a|
1.#3 BB1 PredBB0 | | | | |V0 a|V1 a|V2 a|
5.#4 V2 Use * Keep r8 | | | | |V0 a|V1 a|V2 a|
6.#5 I14 Def Alloc rbx | | |I14a| |V0 a|V1 a| |
7.#6 I14 Use * Keep rbx | | |I14a| |V0 a|V1 a| |
8.#7 V19 Def Alloc rbx | | |V19a| |V0 a|V1 a| |
11.#8 r8 Fixd Keep r8 | | |V19a| |V0 a|V1 a| |
11.#9 V19 Use Copy r8 | | |V19a| |V0 a|V1 a|V19a|
12.#10 r8 Fixd Keep r8 | | |V19a| |V0 a|V1 a|V19a|
12.#11 I15 Def Alloc r8 | | |V19a| |V0 a|V1 a|I15a|
15.#12 rcx Fixd Keep rcx | | |V19a| |V0 a|V1 a|I15a|
15.#13 V0 Use Copy rcx | |V0 a|V19a| |V0 a|V1 a|I15a|
16.#14 rcx Fixd Keep rcx | |V0 a|V19a| |V0 a|V1 a|I15a|
16.#15 I16 Def Alloc rcx | |I16a|V19a| |V0 a|V1 a|I15a|
19.#16 rdx Fixd Keep rdx | |I16a|V19a| |V0 a|V1 a|I15a|
--------------------------------+----+----+----+----+----+----+----+----+
Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |
--------------------------------+----+----+----+----+----+----+----+----+
19.#17 V1 Use Copy rdx | |I16a|V1 a|V19a| |V0 a|V1 a|I15a|
20.#18 rdx Fixd Keep rdx | |I16a|V1 a|V19a| |V0 a|V1 a|I15a|
20.#19 I17 Def Alloc rdx | |I16a|I17a|V19a| |V0 a|V1 a|I15a|
21.#20 r8 Fixd Keep r8 | |I16a|I17a|V19a| |V0 a|V1 a|I15a|
21.#21 I15 Use * Keep r8 | |I16a|I17a|V19a| |V0 a|V1 a|I15a|
21.#22 rcx Fixd Keep rcx | |I16a|I17a|V19a| |V0 a|V1 a|I15a|
21.#23 I16 Use * Keep rcx | |I16a|I17a|V19a| |V0 a|V1 a|I15a|
21.#24 rdx Fixd Keep rdx | |I16a|I17a|V19a| |V0 a|V1 a|I15a|
21.#25 I17 Use * Keep rdx | |I16a|I17a|V19a| |V0 a|V1 a|I15a|
22.#26 rax Kill Keep rax | | | |V19a| |V0 a|V1 a| |
22.#27 rcx Kill Keep rcx | | | |V19a| |V0 a|V1 a| |
22.#28 rdx Kill Keep rdx | | | |V19a| |V0 a|V1 a| |
22.#29 r8 Kill Keep r8 | | | |V19a| |V0 a|V1 a| |
22.#30 r9 Kill Keep r9 | | | |V19a| |V0 a|V1 a| |
22.#31 r10 Kill Keep r10 | | | |V19a| |V0 a|V1 a| |
22.#32 r11 Kill Keep r11 | | | |V19a| |V0 a|V1 a| |
22.#33 rax Fixd Keep rax | | | |V19a| |V0 a|V1 a| |
22.#34 I18 Def Alloc rax |I18a| | |V19a| |V0 a|V1 a| |
23.#35 I18 Use * Keep rax |I18a| | |V19a| |V0 a|V1 a| |
24.#36 V10 Def Alloc rbp | | | |V19a|V10a|V0 a|V1 a| |
27.#37 r9 Fixd Keep r9 | | | |V19a|V10a|V0 a|V1 a| |
--------------------------------+----+----+----+----+----+----+----+----+----+
Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |
--------------------------------+----+----+----+----+----+----+----+----+----+
27.#38 V19 Use Copy r9 | | | |V19a|V10a|V0 a|V1 a| |V19a|
28.#39 r9 Fixd Keep r9 | | | |V19a|V10a|V0 a|V1 a| |V19a|
28.#40 I19 Def Alloc r9 | | | |V19a|V10a|V0 a|V1 a| |I19a|
31.#41 rdx Fixd Keep rdx | | | |V19a|V10a|V0 a|V1 a| |I19a|
31.#42 V0 Use Copy rdx | | |V0 a|V19a|V10a|V0 a|V1 a| |I19a|
32.#43 rdx Fixd Keep rdx | | |V0 a|V19a|V10a|V0 a|V1 a| |I19a|
32.#44 I20 Def Alloc rdx | | |I20a|V19a|V10a|V0 a|V1 a| |I19a|
35.#45 r8 Fixd Keep r8 | | |I20a|V19a|V10a|V0 a|V1 a| |I19a|
35.#46 V1 Use Copy r8 | | |I20a|V19a|V10a|V0 a|V1 a|V1 a|I19a|
36.#47 r8 Fixd Keep r8 | | |I20a|V19a|V10a|V0 a|V1 a|V1 a|I19a|
36.#48 I21 Def Alloc r8 | | |I20a|V19a|V10a|V0 a|V1 a|I21a|I19a|
38.#49 C22 Def Alloc rcx | |C22a|I20a|V19a|V10a|V0 a|V1 a|I21a|I19a|
39.#50 rcx Fixd Keep rcx | |C22a|I20a|V19a|V10a|V0 a|V1 a|I21a|I19a|
39.#51 C22 Use * Keep rcx | |C22a|I20a|V19a|V10a|V0 a|V1 a|I21a|I19a|
40.#52 rcx Fixd Keep rcx | | |I20a|V19a|V10a|V0 a|V1 a|I21a|I19a|
40.#53 I23 Def Alloc rcx | |I23a|I20a|V19a|V10a|V0 a|V1 a|I21a|I19a|
41.#54 r9 Fixd Keep r9 | |I23a|I20a|V19a|V10a|V0 a|V1 a|I21a|I19a|
41.#55 I19 Use * Keep r9 | |I23a|I20a|V19a|V10a|V0 a|V1 a|I21a|I19a|
41.#56 rdx Fixd Keep rdx | |I23a|I20a|V19a|V10a|V0 a|V1 a|I21a|I19a|
41.#57 I20 Use * Keep rdx | |I23a|I20a|V19a|V10a|V0 a|V1 a|I21a|I19a|
41.#58 r8 Fixd Keep r8 | |I23a|I20a|V19a|V10a|V0 a|V1 a|I21a|I19a|
41.#59 I21 Use * Keep r8 | |I23a|I20a|V19a|V10a|V0 a|V1 a|I21a|I19a|
41.#60 rcx Fixd Keep rcx | |I23a|I20a|V19a|V10a|V0 a|V1 a|I21a|I19a|
41.#61 I23 Use * Keep rcx | |I23a|I20a|V19a|V10a|V0 a|V1 a|I21a|I19a|
42.#62 rax Kill Keep rax | | | |V19a|V10a|V0 a|V1 a| | |
42.#63 rcx Kill Keep rcx | | | |V19a|V10a|V0 a|V1 a| | |
42.#64 rdx Kill Keep rdx | | | |V19a|V10a|V0 a|V1 a| | |
42.#65 r8 Kill Keep r8 | | | |V19a|V10a|V0 a|V1 a| | |
42.#66 r9 Kill Keep r9 | | | |V19a|V10a|V0 a|V1 a| | |
42.#67 r10 Kill Keep r10 | | | |V19a|V10a|V0 a|V1 a| | |
42.#68 r11 Kill Keep r11 | | | |V19a|V10a|V0 a|V1 a| | |
42.#69 rax Fixd Keep rax | | | |V19a|V10a|V0 a|V1 a| | |
42.#70 I24 Def Alloc rax |I24a| | |V19a|V10a|V0 a|V1 a| | |
43.#71 I24 Use * Keep rax |I24a| | |V19a|V10a|V0 a|V1 a| | |
--------------------------------+----+----+----+----+----+----+----+----+----+----+
Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |r14 |
--------------------------------+----+----+----+----+----+----+----+----+----+----+
44.#72 V3 Def Alloc r14 | | | |V19a|V10a|V0 a|V1 a| | |V3 a|
53.#73 r9 Fixd Keep r9 | | | |V19a|V10a|V0 a|V1 a| | |V3 a|
53.#74 V19 Use Copy r9 | | | |V19a|V10a|V0 a|V1 a| |V19a|V3 a|
54.#75 r9 Fixd Keep r9 | | | |V19a|V10a|V0 a|V1 a| |V19a|V3 a|
54.#76 I25 Def Alloc r9 | | | |V19a|V10a|V0 a|V1 a| |I25a|V3 a|
56.#77 I26 Def Alloc rcx | |I26a| |V19a|V10a|V0 a|V1 a| |I25a|V3 a|
57.#78 rcx Fixd Keep rcx | |I26a| |V19a|V10a|V0 a|V1 a| |I25a|V3 a|
57.#79 I26 Use * Keep rcx | |I26a| |V19a|V10a|V0 a|V1 a| |I25a|V3 a|
58.#80 rcx Fixd Keep rcx | | | |V19a|V10a|V0 a|V1 a| |I25a|V3 a|
58.#81 I27 Def Alloc rcx | |I27a| |V19a|V10a|V0 a|V1 a| |I25a|V3 a|
61.#82 rdx Fixd Keep rdx | |I27a| |V19a|V10a|V0 a|V1 a| |I25a|V3 a|
61.#83 V0 Use Copy rdx | |I27a|V0 a|V19a|V10a|V0 a|V1 a| |I25a|V3 a|
62.#84 rdx Fixd Keep rdx | |I27a|V0 a|V19a|V10a|V0 a|V1 a| |I25a|V3 a|
62.#85 I28 Def Alloc rdx | |I27a|I28a|V19a|V10a|V0 a|V1 a| |I25a|V3 a|
65.#86 r8 Fixd Keep r8 | |I27a|I28a|V19a|V10a|V0 a|V1 a| |I25a|V3 a|
65.#87 V1 Use Copy r8 | |I27a|I28a|V19a|V10a|V0 a|V1 a|V1 a|I25a|V3 a|
66.#88 r8 Fixd Keep r8 | |I27a|I28a|V19a|V10a|V0 a|V1 a|V1 a|I25a|V3 a|
66.#89 I29 Def Alloc r8 | |I27a|I28a|V19a|V10a|V0 a|V1 a|I29a|I25a|V3 a|
67.#90 r9 Fixd Keep r9 | |I27a|I28a|V19a|V10a|V0 a|V1 a|I29a|I25a|V3 a|
67.#91 I25 Use * Keep r9 | |I27a|I28a|V19a|V10a|V0 a|V1 a|I29a|I25a|V3 a|
67.#92 rcx Fixd Keep rcx | |I27a|I28a|V19a|V10a|V0 a|V1 a|I29a|I25a|V3 a|
67.#93 I27 Use * Keep rcx | |I27a|I28a|V19a|V10a|V0 a|V1 a|I29a|I25a|V3 a|
67.#94 rdx Fixd Keep rdx | |I27a|I28a|V19a|V10a|V0 a|V1 a|I29a|I25a|V3 a|
67.#95 I28 Use * Keep rdx | |I27a|I28a|V19a|V10a|V0 a|V1 a|I29a|I25a|V3 a|
67.#96 r8 Fixd Keep r8 | |I27a|I28a|V19a|V10a|V0 a|V1 a|I29a|I25a|V3 a|
67.#97 I29 Use * Keep r8 | |I27a|I28a|V19a|V10a|V0 a|V1 a|I29a|I25a|V3 a|
68.#98 rax Kill Keep rax | | | |V19a|V10a|V0 a|V1 a| | |V3 a|
68.#99 rcx Kill Keep rcx | | | |V19a|V10a|V0 a|V1 a| | |V3 a|
68.#100 rdx Kill Keep rdx | | | |V19a|V10a|V0 a|V1 a| | |V3 a|
68.#101 r8 Kill Keep r8 | | | |V19a|V10a|V0 a|V1 a| | |V3 a|
68.#102 r9 Kill Keep r9 | | | |V19a|V10a|V0 a|V1 a| | |V3 a|
68.#103 r10 Kill Keep r10 | | | |V19a|V10a|V0 a|V1 a| | |V3 a|
68.#104 r11 Kill Keep r11 | | | |V19a|V10a|V0 a|V1 a| | |V3 a|
68.#105 rax Fixd Keep rax | | | |V19a|V10a|V0 a|V1 a| | |V3 a|
68.#106 I30 Def Alloc rax |I30a| | |V19a|V10a|V0 a|V1 a| | |V3 a|
69.#107 I30 Use * Keep rax |I30a| | |V19a|V10a|V0 a|V1 a| | |V3 a|
--------------------------------+----+----+----+----+----+----+----+----+----+----+----+
Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |r14 |r15 |
--------------------------------+----+----+----+----+----+----+----+----+----+----+----+
70.#108 V4 Def Alloc r15 | | | |V19a|V10a|V0 a|V1 a| | |V3 a|V4 a|
72.#109 C31 Def Alloc rcx | |C31a| |V19a|V10a|V0 a|V1 a| | |V3 a|V4 a|
73.#110 rcx Fixd Keep rcx | |C31a| |V19a|V10a|V0 a|V1 a| | |V3 a|V4 a|
73.#111 C31 Use * Keep rcx | |C31a| |V19a|V10a|V0 a|V1 a| | |V3 a|V4 a|
74.#112 rcx Fixd Keep rcx | | | |V19a|V10a|V0 a|V1 a| | |V3 a|V4 a|
74.#113 I32 Def Alloc rcx | |I32a| |V19a|V10a|V0 a|V1 a| | |V3 a|V4 a|
75.#114 rcx Fixd Keep rcx | |I32a| |V19a|V10a|V0 a|V1 a| | |V3 a|V4 a|
75.#115 I32 Use * Keep rcx | |I32a| |V19a|V10a|V0 a|V1 a| | |V3 a|V4 a|
76.#116 rax Kill Keep rax | | | |V19a|V10a|V0 a|V1 a| | |V3 a|V4 a|
76.#117 rcx Kill Keep rcx | | | |V19a|V10a|V0 a|V1 a| | |V3 a|V4 a|
76.#118 rdx Kill Keep rdx | | | |V19a|V10a|V0 a|V1 a| | |V3 a|V4 a|
76.#119 r8 Kill Keep r8 | | | |V19a|V10a|V0 a|V1 a| | |V3 a|V4 a|
76.#120 r9 Kill Keep r9 | | | |V19a|V10a|V0 a|V1 a| | |V3 a|V4 a|
76.#121 r10 Kill Keep r10 | | | |V19a|V10a|V0 a|V1 a| | |V3 a|V4 a|
76.#122 r11 Kill Keep r11 | | | |V19a|V10a|V0 a|V1 a| | |V3 a|V4 a|
76.#123 rax Fixd Keep rax | | | |V19a|V10a|V0 a|V1 a| | |V3 a|V4 a|
76.#124 I33 Def Alloc rax |I33a| | |V19a|V10a|V0 a|V1 a| | |V3 a|V4 a|
77.#125 I33 Use * Keep rax |I33a| | |V19a|V10a|V0 a|V1 a| | |V3 a|V4 a|
78.#126 V11 Def Alloc rdx | | |V11a|V19a|V10a|V0 a|V1 a| | |V3 a|V4 a|
81.#127 V19 Use Keep rbx | | |V11a|V19a|V10a|V0 a|V1 a| | |V3 a|V4 a|
85.#128 rdx Fixd Keep rdx | | |V11a|V19a|V10a|V0 a|V1 a| | |V3 a|V4 a|
85.#129 V11 Use * Keep rdx | | |V11a|V19a|V10a|V0 a|V1 a| | |V3 a|V4 a|
86.#130 rdx Fixd Keep rdx | | | |V19a|V10a|V0 a|V1 a| | |V3 a|V4 a|
86.#131 I34 Def Alloc rdx | | |I34a|V19a|V10a|V0 a|V1 a| | |V3 a|V4 a|
89.#132 r8 Fixd Keep r8 | | |I34a|V19a|V10a|V0 a|V1 a| | |V3 a|V4 a|
89.#133 V0 Use Copy r8 | | |I34a|V19a|V10a|V0 a|V1 a|V0 a| |V3 a|V4 a|
90.#134 r8 Fixd Keep r8 | | |I34a|V19a|V10a|V0 a|V1 a|V0 a| |V3 a|V4 a|
90.#135 I35 Def Alloc r8 | | |I34a|V19a|V10a|V0 a|V1 a|I35a| |V3 a|V4 a|
93.#136 r9 Fixd Keep r9 | | |I34a|V19a|V10a|V0 a|V1 a|I35a| |V3 a|V4 a|
93.#137 V1 Use Copy r9 | | |I34a|V19a|V10a|V0 a|V1 a|I35a|V1 a|V3 a|V4 a|
94.#138 r9 Fixd Keep r9 | | |I34a|V19a|V10a|V0 a|V1 a|I35a|V1 a|V3 a|V4 a|
94.#139 I36 Def Alloc r9 | | |I34a|V19a|V10a|V0 a|V1 a|I35a|I36a|V3 a|V4 a|
96.#140 C37 Def Alloc rcx | |C37a|I34a|V19a|V10a|V0 a|V1 a|I35a|I36a|V3 a|V4 a|
97.#141 rcx Fixd Keep rcx | |C37a|I34a|V19a|V10a|V0 a|V1 a|I35a|I36a|V3 a|V4 a|
97.#142 C37 Use * Keep rcx | |C37a|I34a|V19a|V10a|V0 a|V1 a|I35a|I36a|V3 a|V4 a|
98.#143 rcx Fixd Keep rcx | | |I34a|V19a|V10a|V0 a|V1 a|I35a|I36a|V3 a|V4 a|
98.#144 I38 Def Alloc rcx | |I38a|I34a|V19a|V10a|V0 a|V1 a|I35a|I36a|V3 a|V4 a|
99.#145 rdx Fixd Keep rdx | |I38a|I34a|V19a|V10a|V0 a|V1 a|I35a|I36a|V3 a|V4 a|
99.#146 I34 Use * Keep rdx | |I38a|I34a|V19a|V10a|V0 a|V1 a|I35a|I36a|V3 a|V4 a|
99.#147 r8 Fixd Keep r8 | |I38a|I34a|V19a|V10a|V0 a|V1 a|I35a|I36a|V3 a|V4 a|
99.#148 I35 Use * Keep r8 | |I38a|I34a|V19a|V10a|V0 a|V1 a|I35a|I36a|V3 a|V4 a|
99.#149 r9 Fixd Keep r9 | |I38a|I34a|V19a|V10a|V0 a|V1 a|I35a|I36a|V3 a|V4 a|
99.#150 I36 Use * Keep r9 | |I38a|I34a|V19a|V10a|V0 a|V1 a|I35a|I36a|V3 a|V4 a|
99.#151 rcx Fixd Keep rcx | |I38a|I34a|V19a|V10a|V0 a|V1 a|I35a|I36a|V3 a|V4 a|
99.#152 I38 Use * Keep rcx | |I38a|I34a|V19a|V10a|V0 a|V1 a|I35a|I36a|V3 a|V4 a|
100.#153 rax Kill Keep rax | | | |V19a|V10a|V0 a|V1 a| | |V3 a|V4 a|
100.#154 rcx Kill Keep rcx | | | |V19a|V10a|V0 a|V1 a| | |V3 a|V4 a|
100.#155 rdx Kill Keep rdx | | | |V19a|V10a|V0 a|V1 a| | |V3 a|V4 a|
100.#156 r8 Kill Keep r8 | | | |V19a|V10a|V0 a|V1 a| | |V3 a|V4 a|
100.#157 r9 Kill Keep r9 | | | |V19a|V10a|V0 a|V1 a| | |V3 a|V4 a|
100.#158 r10 Kill Keep r10 | | | |V19a|V10a|V0 a|V1 a| | |V3 a|V4 a|
100.#159 r11 Kill Keep r11 | | | |V19a|V10a|V0 a|V1 a| | |V3 a|V4 a|
100.#160 rax Fixd Keep rax | | | |V19a|V10a|V0 a|V1 a| | |V3 a|V4 a|
--------------------------------+----+----+----+----+----+----+----+----+----+----+----+
Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |r14 |r15 |
--------------------------------+----+----+----+----+----+----+----+----+----+----+----+
100.#161 I39 Def Alloc rax |I39a| | |V19a|V10a|V0 a|V1 a| | |V3 a|V4 a|
101.#162 I39 Use * Keep rax |I39a| | |V19a|V10a|V0 a|V1 a| | |V3 a|V4 a|
--------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+
Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |r12 |r14 |r15 |
--------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+
102.#163 V5 Def Alloc r12 | | | |V19a|V10a|V0 a|V1 a| | |V5 a|V3 a|V4 a|
105.#164 r8 Fixd Keep r8 | | | |V19a|V10a|V0 a|V1 a| | |V5 a|V3 a|V4 a|
105.#165 V19 Use Copy r8 | | | |V19a|V10a|V0 a|V1 a|V19a| |V5 a|V3 a|V4 a|
106.#166 r8 Fixd Keep r8 | | | |V19a|V10a|V0 a|V1 a|V19a| |V5 a|V3 a|V4 a|
106.#167 I40 Def Alloc r8 | | | |V19a|V10a|V0 a|V1 a|I40a| |V5 a|V3 a|V4 a|
109.#168 rcx Fixd Keep rcx | | | |V19a|V10a|V0 a|V1 a|I40a| |V5 a|V3 a|V4 a|
109.#169 V0 Use Copy rcx | |V0 a| |V19a|V10a|V0 a|V1 a|I40a| |V5 a|V3 a|V4 a|
110.#170 rcx Fixd Keep rcx | |V0 a| |V19a|V10a|V0 a|V1 a|I40a| |V5 a|V3 a|V4 a|
110.#171 I41 Def Alloc rcx | |I41a| |V19a|V10a|V0 a|V1 a|I40a| |V5 a|V3 a|V4 a|
113.#172 rdx Fixd Keep rdx | |I41a| |V19a|V10a|V0 a|V1 a|I40a| |V5 a|V3 a|V4 a|
113.#173 V1 Use Copy rdx | |I41a|V1 a|V19a|V10a|V0 a|V1 a|I40a| |V5 a|V3 a|V4 a|
114.#174 rdx Fixd Keep rdx | |I41a|V1 a|V19a|V10a|V0 a|V1 a|I40a| |V5 a|V3 a|V4 a|
114.#175 I42 Def Alloc rdx | |I41a|I42a|V19a|V10a|V0 a|V1 a|I40a| |V5 a|V3 a|V4 a|
115.#176 r8 Fixd Keep r8 | |I41a|I42a|V19a|V10a|V0 a|V1 a|I40a| |V5 a|V3 a|V4 a|
115.#177 I40 Use * Keep r8 | |I41a|I42a|V19a|V10a|V0 a|V1 a|I40a| |V5 a|V3 a|V4 a|
115.#178 rcx Fixd Keep rcx | |I41a|I42a|V19a|V10a|V0 a|V1 a|I40a| |V5 a|V3 a|V4 a|
115.#179 I41 Use * Keep rcx | |I41a|I42a|V19a|V10a|V0 a|V1 a|I40a| |V5 a|V3 a|V4 a|
115.#180 rdx Fixd Keep rdx | |I41a|I42a|V19a|V10a|V0 a|V1 a|I40a| |V5 a|V3 a|V4 a|
115.#181 I42 Use * Keep rdx | |I41a|I42a|V19a|V10a|V0 a|V1 a|I40a| |V5 a|V3 a|V4 a|
116.#182 rax Kill Keep rax | | | |V19a|V10a|V0 a|V1 a| | |V5 a|V3 a|V4 a|
116.#183 rcx Kill Keep rcx | | | |V19a|V10a|V0 a|V1 a| | |V5 a|V3 a|V4 a|
116.#184 rdx Kill Keep rdx | | | |V19a|V10a|V0 a|V1 a| | |V5 a|V3 a|V4 a|
116.#185 r8 Kill Keep r8 | | | |V19a|V10a|V0 a|V1 a| | |V5 a|V3 a|V4 a|
116.#186 r9 Kill Keep r9 | | | |V19a|V10a|V0 a|V1 a| | |V5 a|V3 a|V4 a|
116.#187 r10 Kill Keep r10 | | | |V19a|V10a|V0 a|V1 a| | |V5 a|V3 a|V4 a|
116.#188 r11 Kill Keep r11 | | | |V19a|V10a|V0 a|V1 a| | |V5 a|V3 a|V4 a|
116.#189 rax Fixd Keep rax | | | |V19a|V10a|V0 a|V1 a| | |V5 a|V3 a|V4 a|
116.#190 I43 Def Alloc rax |I43a| | |V19a|V10a|V0 a|V1 a| | |V5 a|V3 a|V4 a|
117.#191 I43 Use * Keep rax |I43a| | |V19a|V10a|V0 a|V1 a| | |V5 a|V3 a|V4 a|
118.#192 V6 Def Alloc rcx | |V6 a| |V19a|V10a|V0 a|V1 a| | |V5 a|V3 a|V4 a|
123.#193 V0 Use Keep rsi | |V6 a| |V19a|V10a|V0 a|V1 a| | |V5 a|V3 a|V4 a|
123.#194 V1 Use * Keep rdi | |V6 a| |V19a|V10a|V0 a|V1 a| | |V5 a|V3 a|V4 a|
124.#195 I44 Def Alloc rdi | |V6 a| |V19a|V10a|V0 a|I44a| | |V5 a|V3 a|V4 a|
125.#196 I44 Use * Keep rdi | |V6 a| |V19a|V10a|V0 a|I44a| | |V5 a|V3 a|V4 a|
126.#197 V13 Def Alloc rdi | |V6 a| |V19a|V10a|V0 a|V13a| | |V5 a|V3 a|V4 a|
131.#198 V13 Use * Keep rdi | |V6 a| |V19a|V10a|V0 a|V13a| | |V5 a|V3 a|V4 a|
131.#199 V19 Use Keep rbx | |V6 a| |V19a|V10a|V0 a|V13a| | |V5 a|V3 a|V4 a|
132.#200 I45 Def Alloc rdi | |V6 a| |V19a|V10a|V0 a|I45a| | |V5 a|V3 a|V4 a|
133.#201 I45 Use * Keep rdi | |V6 a| |V19a|V10a|V0 a|I45a| | |V5 a|V3 a|V4 a|
134.#202 V14 Def Alloc rdi | |V6 a| |V19a|V10a|V0 a|V14a| | |V5 a|V3 a|V4 a|
139.#203 V0 Use * Keep rsi | |V6 a| |V19a|V10a|V0 a|V14a| | |V5 a|V3 a|V4 a|
139.#204 V19 Use * Keep rbx | |V6 a| |V19a|V10a|V0 a|V14a| | |V5 a|V3 a|V4 a|
140.#205 I46 Def Alloc rax |I46a|V6 a| | |V10a| |V14a| | |V5 a|V3 a|V4 a|
141.#206 I46 Use * Keep rax |I46a|V6 a| | |V10a| |V14a| | |V5 a|V3 a|V4 a|
142.#207 V15 Def Alloc rax |V15a|V6 a| | |V10a| |V14a| | |V5 a|V3 a|V4 a|
149.#208 V14 Use * Keep rdi |V15a|V6 a| | |V10a| |V14a| | |V5 a|V3 a|V4 a|
150.#209 I47 Def Alloc rdi |V15a|V6 a| | |V10a| |I47a| | |V5 a|V3 a|V4 a|
151.#210 rax Fixd Keep rax |V15a|V6 a| | |V10a| |I47a| | |V5 a|V3 a|V4 a|
151.#211 V15 Use * Keep rax |V15a|V6 a| | |V10a| |I47a| | |V5 a|V3 a|V4 a|
151.#212 I47 Use *D Keep rdi |V15a|V6 a| | |V10a| |I47a| | |V5 a|V3 a|V4 a|
152.#213 rax Kill Keep rax | |V6 a| | |V10a| |I47a| | |V5 a|V3 a|V4 a|
152.#214 rdx Kill Keep rdx | |V6 a| | |V10a| |I47a| | |V5 a|V3 a|V4 a|
152.#215 rax Fixd Keep rax | |V6 a| | |V10a| |I47a| | |V5 a|V3 a|V4 a|
--------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+
Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |r12 |r14 |r15 |
--------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+
152.#216 I48 Def Alloc rax |I48a|V6 a| | |V10a| |I47a| | |V5 a|V3 a|V4 a|
153.#217 I48 Use * Keep rax |I48a|V6 a| | |V10a| | | | |V5 a|V3 a|V4 a|
154.#218 V7 Def Alloc rax |V7 a|V6 a| | |V10a| | | | |V5 a|V3 a|V4 a|
159.#219 V10 Use * Keep rbp |V7 a|V6 a| | |V10a| | | | |V5 a|V3 a|V4 a|
159.#220 V3 Use * Keep r14 |V7 a|V6 a| | |V10a| | | | |V5 a|V3 a|V4 a|
160.#221 I49 Def Alloc rbp |V7 a|V6 a| | |I49a| | | | |V5 a| |V4 a|
163.#222 I49 Use * Keep rbp |V7 a|V6 a| | |I49a| | | | |V5 a| |V4 a|
163.#223 V4 Use * Keep r15 |V7 a|V6 a| | |I49a| | | | |V5 a| |V4 a|
164.#224 I50 Def Alloc rbp |V7 a|V6 a| | |I50a| | | | |V5 a| | |
167.#225 I50 Use * Keep rbp |V7 a|V6 a| | |I50a| | | | |V5 a| | |
167.#226 V5 Use * Keep r12 |V7 a|V6 a| | |I50a| | | | |V5 a| | |
168.#227 I51 Def Alloc rbp |V7 a|V6 a| | |I51a| | | | | | | |
171.#228 I51 Use * Keep rbp |V7 a|V6 a| | |I51a| | | | | | | |
171.#229 V6 Use * Keep rcx |V7 a|V6 a| | |I51a| | | | | | | |
172.#230 I52 Def Alloc rcx |V7 a|I52a| | | | | | | | | | |
175.#231 I52 Use * Keep rcx |V7 a|I52a| | | | | | | | | | |
175.#232 V7 Use * Keep rax |V7 a|I52a| | | | | | | | | | |
176.#233 I53 Def Alloc rax |I53a| | | | | | | | | | | |
177.#234 rax Fixd Keep rax |I53a| | | | | | | | | | | |
177.#235 I53 Use * Keep rax | | | | | | | | | | | | |
------------
REFPOSITIONS AFTER ALLOCATION:
------------
<RefPosition #0 @0 RefTypeParamDef <Ivl:0 V00> BB00 regmask=[rsi] minReg=1 fixed regOptional>
<RefPosition #1 @0 RefTypeParamDef <Ivl:1 V01> BB00 regmask=[rdi] minReg=1 fixed regOptional>
<RefPosition #2 @0 RefTypeParamDef <Ivl:2 V02> BB00 regmask=[r8] minReg=1 fixed regOptional>
<RefPosition #3 @1 RefTypeBB BB01 regmask=[] minReg=1>
<RefPosition #4 @5 RefTypeUse <Ivl:2 V02> LCL_VAR BB01 regmask=[r8] minReg=1 last>
<RefPosition #5 @6 RefTypeDef <Ivl:14> CAST BB01 regmask=[rbx] minReg=1>
<RefPosition #6 @7 RefTypeUse <Ivl:14> BB01 regmask=[rbx] minReg=1 last>
<RefPosition #7 @8 RefTypeDef <Ivl:13 V19> STORE_LCL_VAR BB01 regmask=[rbx] minReg=1>
<RefPosition #8 @11 RefTypeFixedReg <Reg:r8 > BB01 regmask=[r8] minReg=1>
<RefPosition #9 @11 RefTypeUse <Ivl:13 V19> LCL_VAR BB01 regmask=[r8] minReg=1 copy fixed>
<RefPosition #10 @12 RefTypeFixedReg <Reg:r8 > BB01 regmask=[r8] minReg=1>
<RefPosition #11 @12 RefTypeDef <Ivl:15> PUTARG_REG BB01 regmask=[r8] minReg=1 fixed>
<RefPosition #12 @15 RefTypeFixedReg <Reg:rcx> BB01 regmask=[rcx] minReg=1>
<RefPosition #13 @15 RefTypeUse <Ivl:0 V00> LCL_VAR BB01 regmask=[rcx] minReg=1 copy fixed>
<RefPosition #14 @16 RefTypeFixedReg <Reg:rcx> BB01 regmask=[rcx] minReg=1>
<RefPosition #15 @16 RefTypeDef <Ivl:16> PUTARG_REG BB01 regmask=[rcx] minReg=1 fixed>
<RefPosition #16 @19 RefTypeFixedReg <Reg:rdx> BB01 regmask=[rdx] minReg=1>
<RefPosition #17 @19 RefTypeUse <Ivl:1 V01> LCL_VAR BB01 regmask=[rdx] minReg=1 copy fixed>
<RefPosition #18 @20 RefTypeFixedReg <Reg:rdx> BB01 regmask=[rdx] minReg=1>
<RefPosition #19 @20 RefTypeDef <Ivl:17> PUTARG_REG BB01 regmask=[rdx] minReg=1 fixed>
<RefPosition #20 @21 RefTypeFixedReg <Reg:r8 > BB01 regmask=[r8] minReg=1>
<RefPosition #21 @21 RefTypeUse <Ivl:15> BB01 regmask=[r8] minReg=1 last fixed>
<RefPosition #22 @21 RefTypeFixedReg <Reg:rcx> BB01 regmask=[rcx] minReg=1>
<RefPosition #23 @21 RefTypeUse <Ivl:16> BB01 regmask=[rcx] minReg=1 last fixed>
<RefPosition #24 @21 RefTypeFixedReg <Reg:rdx> BB01 regmask=[rdx] minReg=1>
<RefPosition #25 @21 RefTypeUse <Ivl:17> BB01 regmask=[rdx] minReg=1 last fixed>
<RefPosition #26 @22 RefTypeKill <Reg:rax> BB01 regmask=[rax] minReg=1 last>
<RefPosition #27 @22 RefTypeKill <Reg:rcx> BB01 regmask=[rcx] minReg=1 last>
<RefPosition #28 @22 RefTypeKill <Reg:rdx> BB01 regmask=[rdx] minReg=1 last>
<RefPosition #29 @22 RefTypeKill <Reg:r8 > BB01 regmask=[r8] minReg=1 last>
<RefPosition #30 @22 RefTypeKill <Reg:r9 > BB01 regmask=[r9] minReg=1 last>
<RefPosition #31 @22 RefTypeKill <Reg:r10> BB01 regmask=[r10] minReg=1 last>
<RefPosition #32 @22 RefTypeKill <Reg:r11> BB01 regmask=[r11] minReg=1 last>
<RefPosition #33 @22 RefTypeFixedReg <Reg:rax> BB01 regmask=[rax] minReg=1>
<RefPosition #34 @22 RefTypeDef <Ivl:18> CALL BB01 regmask=[rax] minReg=1 fixed>
<RefPosition #35 @23 RefTypeUse <Ivl:18> BB01 regmask=[rax] minReg=1 last>
<RefPosition #36 @24 RefTypeDef <Ivl:8 V10> STORE_LCL_VAR BB01 regmask=[rbp] minReg=1>
<RefPosition #37 @27 RefTypeFixedReg <Reg:r9 > BB01 regmask=[r9] minReg=1>
<RefPosition #38 @27 RefTypeUse <Ivl:13 V19> LCL_VAR BB01 regmask=[r9] minReg=1 copy fixed>
<RefPosition #39 @28 RefTypeFixedReg <Reg:r9 > BB01 regmask=[r9] minReg=1>
<RefPosition #40 @28 RefTypeDef <Ivl:19> PUTARG_REG BB01 regmask=[r9] minReg=1 fixed>
<RefPosition #41 @31 RefTypeFixedReg <Reg:rdx> BB01 regmask=[rdx] minReg=1>
<RefPosition #42 @31 RefTypeUse <Ivl:0 V00> LCL_VAR BB01 regmask=[rdx] minReg=1 copy fixed>
<RefPosition #43 @32 RefTypeFixedReg <Reg:rdx> BB01 regmask=[rdx] minReg=1>
<RefPosition #44 @32 RefTypeDef <Ivl:20> PUTARG_REG BB01 regmask=[rdx] minReg=1 fixed>
<RefPosition #45 @35 RefTypeFixedReg <Reg:r8 > BB01 regmask=[r8] minReg=1>
<RefPosition #46 @35 RefTypeUse <Ivl:1 V01> LCL_VAR BB01 regmask=[r8] minReg=1 copy fixed>
<RefPosition #47 @36 RefTypeFixedReg <Reg:r8 > BB01 regmask=[r8] minReg=1>
<RefPosition #48 @36 RefTypeDef <Ivl:21> PUTARG_REG BB01 regmask=[r8] minReg=1 fixed>
<RefPosition #49 @38 RefTypeDef <Ivl:22> CNS_INT BB01 regmask=[rcx] minReg=1>
<RefPosition #50 @39 RefTypeFixedReg <Reg:rcx> BB01 regmask=[rcx] minReg=1>
<RefPosition #51 @39 RefTypeUse <Ivl:22> BB01 regmask=[rcx] minReg=1 last fixed>
<RefPosition #52 @40 RefTypeFixedReg <Reg:rcx> BB01 regmask=[rcx] minReg=1>
<RefPosition #53 @40 RefTypeDef <Ivl:23> PUTARG_REG BB01 regmask=[rcx] minReg=1 fixed>
<RefPosition #54 @41 RefTypeFixedReg <Reg:r9 > BB01 regmask=[r9] minReg=1>
<RefPosition #55 @41 RefTypeUse <Ivl:19> BB01 regmask=[r9] minReg=1 last fixed>
<RefPosition #56 @41 RefTypeFixedReg <Reg:rdx> BB01 regmask=[rdx] minReg=1>
<RefPosition #57 @41 RefTypeUse <Ivl:20> BB01 regmask=[rdx] minReg=1 last fixed>
<RefPosition #58 @41 RefTypeFixedReg <Reg:r8 > BB01 regmask=[r8] minReg=1>
<RefPosition #59 @41 RefTypeUse <Ivl:21> BB01 regmask=[r8] minReg=1 last fixed>
<RefPosition #60 @41 RefTypeFixedReg <Reg:rcx> BB01 regmask=[rcx] minReg=1>
<RefPosition #61 @41 RefTypeUse <Ivl:23> BB01 regmask=[rcx] minReg=1 last fixed>
<RefPosition #62 @42 RefTypeKill <Reg:rax> BB01 regmask=[rax] minReg=1 last>
<RefPosition #63 @42 RefTypeKill <Reg:rcx> BB01 regmask=[rcx] minReg=1 last>
<RefPosition #64 @42 RefTypeKill <Reg:rdx> BB01 regmask=[rdx] minReg=1 last>
<RefPosition #65 @42 RefTypeKill <Reg:r8 > BB01 regmask=[r8] minReg=1 last>
<RefPosition #66 @42 RefTypeKill <Reg:r9 > BB01 regmask=[r9] minReg=1 last>
<RefPosition #67 @42 RefTypeKill <Reg:r10> BB01 regmask=[r10] minReg=1 last>
<RefPosition #68 @42 RefTypeKill <Reg:r11> BB01 regmask=[r11] minReg=1 last>
<RefPosition #69 @42 RefTypeFixedReg <Reg:rax> BB01 regmask=[rax] minReg=1>
<RefPosition #70 @42 RefTypeDef <Ivl:24> CALL BB01 regmask=[rax] minReg=1 fixed>
<RefPosition #71 @43 RefTypeUse <Ivl:24> BB01 regmask=[rax] minReg=1 last>
<RefPosition #72 @44 RefTypeDef <Ivl:3 V03> STORE_LCL_VAR BB01 regmask=[r14] minReg=1>
<RefPosition #73 @53 RefTypeFixedReg <Reg:r9 > BB01 regmask=[r9] minReg=1>
<RefPosition #74 @53 RefTypeUse <Ivl:13 V19> LCL_VAR BB01 regmask=[r9] minReg=1 copy fixed>
<RefPosition #75 @54 RefTypeFixedReg <Reg:r9 > BB01 regmask=[r9] minReg=1>
<RefPosition #76 @54 RefTypeDef <Ivl:25> PUTARG_REG BB01 regmask=[r9] minReg=1 fixed>
<RefPosition #77 @56 RefTypeDef <Ivl:26> LCL_FLD BB01 regmask=[rcx] minReg=1>
<RefPosition #78 @57 RefTypeFixedReg <Reg:rcx> BB01 regmask=[rcx] minReg=1>
<RefPosition #79 @57 RefTypeUse <Ivl:26> BB01 regmask=[rcx] minReg=1 last fixed>
<RefPosition #80 @58 RefTypeFixedReg <Reg:rcx> BB01 regmask=[rcx] minReg=1>
<RefPosition #81 @58 RefTypeDef <Ivl:27> PUTARG_REG BB01 regmask=[rcx] minReg=1 fixed>
<RefPosition #82 @61 RefTypeFixedReg <Reg:rdx> BB01 regmask=[rdx] minReg=1>
<RefPosition #83 @61 RefTypeUse <Ivl:0 V00> LCL_VAR BB01 regmask=[rdx] minReg=1 copy fixed>
<RefPosition #84 @62 RefTypeFixedReg <Reg:rdx> BB01 regmask=[rdx] minReg=1>
<RefPosition #85 @62 RefTypeDef <Ivl:28> PUTARG_REG BB01 regmask=[rdx] minReg=1 fixed>
<RefPosition #86 @65 RefTypeFixedReg <Reg:r8 > BB01 regmask=[r8] minReg=1>
<RefPosition #87 @65 RefTypeUse <Ivl:1 V01> LCL_VAR BB01 regmask=[r8] minReg=1 copy fixed>
<RefPosition #88 @66 RefTypeFixedReg <Reg:r8 > BB01 regmask=[r8] minReg=1>
<RefPosition #89 @66 RefTypeDef <Ivl:29> PUTARG_REG BB01 regmask=[r8] minReg=1 fixed>
<RefPosition #90 @67 RefTypeFixedReg <Reg:r9 > BB01 regmask=[r9] minReg=1>
<RefPosition #91 @67 RefTypeUse <Ivl:25> BB01 regmask=[r9] minReg=1 last fixed>
<RefPosition #92 @67 RefTypeFixedReg <Reg:rcx> BB01 regmask=[rcx] minReg=1>
<RefPosition #93 @67 RefTypeUse <Ivl:27> BB01 regmask=[rcx] minReg=1 last fixed>
<RefPosition #94 @67 RefTypeFixedReg <Reg:rdx> BB01 regmask=[rdx] minReg=1>
<RefPosition #95 @67 RefTypeUse <Ivl:28> BB01 regmask=[rdx] minReg=1 last fixed>
<RefPosition #96 @67 RefTypeFixedReg <Reg:r8 > BB01 regmask=[r8] minReg=1>
<RefPosition #97 @67 RefTypeUse <Ivl:29> BB01 regmask=[r8] minReg=1 last fixed>
<RefPosition #98 @68 RefTypeKill <Reg:rax> BB01 regmask=[rax] minReg=1 last>
<RefPosition #99 @68 RefTypeKill <Reg:rcx> BB01 regmask=[rcx] minReg=1 last>
<RefPosition #100 @68 RefTypeKill <Reg:rdx> BB01 regmask=[rdx] minReg=1 last>
<RefPosition #101 @68 RefTypeKill <Reg:r8 > BB01 regmask=[r8] minReg=1 last>
<RefPosition #102 @68 RefTypeKill <Reg:r9 > BB01 regmask=[r9] minReg=1 last>
<RefPosition #103 @68 RefTypeKill <Reg:r10> BB01 regmask=[r10] minReg=1 last>
<RefPosition #104 @68 RefTypeKill <Reg:r11> BB01 regmask=[r11] minReg=1 last>
<RefPosition #105 @68 RefTypeFixedReg <Reg:rax> BB01 regmask=[rax] minReg=1>
<RefPosition #106 @68 RefTypeDef <Ivl:30> CALL BB01 regmask=[rax] minReg=1 fixed>
<RefPosition #107 @69 RefTypeUse <Ivl:30> BB01 regmask=[rax] minReg=1 last>
<RefPosition #108 @70 RefTypeDef <Ivl:4 V04> STORE_LCL_VAR BB01 regmask=[r15] minReg=1>
<RefPosition #109 @72 RefTypeDef <Ivl:31> CNS_INT BB01 regmask=[rcx] minReg=1>
<RefPosition #110 @73 RefTypeFixedReg <Reg:rcx> BB01 regmask=[rcx] minReg=1>
<RefPosition #111 @73 RefTypeUse <Ivl:31> BB01 regmask=[rcx] minReg=1 last fixed>
<RefPosition #112 @74 RefTypeFixedReg <Reg:rcx> BB01 regmask=[rcx] minReg=1>
<RefPosition #113 @74 RefTypeDef <Ivl:32> PUTARG_REG BB01 regmask=[rcx] minReg=1 fixed>
<RefPosition #114 @75 RefTypeFixedReg <Reg:rcx> BB01 regmask=[rcx] minReg=1>
<RefPosition #115 @75 RefTypeUse <Ivl:32> BB01 regmask=[rcx] minReg=1 last fixed>
<RefPosition #116 @76 RefTypeKill <Reg:rax> BB01 regmask=[rax] minReg=1 last>
<RefPosition #117 @76 RefTypeKill <Reg:rcx> BB01 regmask=[rcx] minReg=1 last>
<RefPosition #118 @76 RefTypeKill <Reg:rdx> BB01 regmask=[rdx] minReg=1 last>
<RefPosition #119 @76 RefTypeKill <Reg:r8 > BB01 regmask=[r8] minReg=1 last>
<RefPosition #120 @76 RefTypeKill <Reg:r9 > BB01 regmask=[r9] minReg=1 last>
<RefPosition #121 @76 RefTypeKill <Reg:r10> BB01 regmask=[r10] minReg=1 last>
<RefPosition #122 @76 RefTypeKill <Reg:r11> BB01 regmask=[r11] minReg=1 last>
<RefPosition #123 @76 RefTypeFixedReg <Reg:rax> BB01 regmask=[rax] minReg=1>
<RefPosition #124 @76 RefTypeDef <Ivl:33> CALL BB01 regmask=[rax] minReg=1 fixed>
<RefPosition #125 @77 RefTypeUse <Ivl:33> BB01 regmask=[rax] minReg=1 last>
<RefPosition #126 @78 RefTypeDef <Ivl:9 V11> STORE_LCL_VAR BB01 regmask=[rdx] minReg=1>
<RefPosition #127 @81 RefTypeUse <Ivl:13 V19> LCL_VAR BB01 regmask=[rbx] minReg=1>
<RefPosition #128 @85 RefTypeFixedReg <Reg:rdx> BB01 regmask=[rdx] minReg=1>
<RefPosition #129 @85 RefTypeUse <Ivl:9 V11> LCL_VAR BB01 regmask=[rdx] minReg=1 last fixed>
<RefPosition #130 @86 RefTypeFixedReg <Reg:rdx> BB01 regmask=[rdx] minReg=1>
<RefPosition #131 @86 RefTypeDef <Ivl:34> PUTARG_REG BB01 regmask=[rdx] minReg=1 fixed>
<RefPosition #132 @89 RefTypeFixedReg <Reg:r8 > BB01 regmask=[r8] minReg=1>
<RefPosition #133 @89 RefTypeUse <Ivl:0 V00> LCL_VAR BB01 regmask=[r8] minReg=1 copy fixed>
<RefPosition #134 @90 RefTypeFixedReg <Reg:r8 > BB01 regmask=[r8] minReg=1>
<RefPosition #135 @90 RefTypeDef <Ivl:35> PUTARG_REG BB01 regmask=[r8] minReg=1 fixed>
<RefPosition #136 @93 RefTypeFixedReg <Reg:r9 > BB01 regmask=[r9] minReg=1>
<RefPosition #137 @93 RefTypeUse <Ivl:1 V01> LCL_VAR BB01 regmask=[r9] minReg=1 copy fixed>
<RefPosition #138 @94 RefTypeFixedReg <Reg:r9 > BB01 regmask=[r9] minReg=1>
<RefPosition #139 @94 RefTypeDef <Ivl:36> PUTARG_REG BB01 regmask=[r9] minReg=1 fixed>
<RefPosition #140 @96 RefTypeDef <Ivl:37> CNS_INT BB01 regmask=[rcx] minReg=1>
<RefPosition #141 @97 RefTypeFixedReg <Reg:rcx> BB01 regmask=[rcx] minReg=1>
<RefPosition #142 @97 RefTypeUse <Ivl:37> BB01 regmask=[rcx] minReg=1 last fixed>
<RefPosition #143 @98 RefTypeFixedReg <Reg:rcx> BB01 regmask=[rcx] minReg=1>
<RefPosition #144 @98 RefTypeDef <Ivl:38> PUTARG_REG BB01 regmask=[rcx] minReg=1 fixed>
<RefPosition #145 @99 RefTypeFixedReg <Reg:rdx> BB01 regmask=[rdx] minReg=1>
<RefPosition #146 @99 RefTypeUse <Ivl:34> BB01 regmask=[rdx] minReg=1 last fixed>
<RefPosition #147 @99 RefTypeFixedReg <Reg:r8 > BB01 regmask=[r8] minReg=1>
<RefPosition #148 @99 RefTypeUse <Ivl:35> BB01 regmask=[r8] minReg=1 last fixed>
<RefPosition #149 @99 RefTypeFixedReg <Reg:r9 > BB01 regmask=[r9] minReg=1>
<RefPosition #150 @99 RefTypeUse <Ivl:36> BB01 regmask=[r9] minReg=1 last fixed>
<RefPosition #151 @99 RefTypeFixedReg <Reg:rcx> BB01 regmask=[rcx] minReg=1>
<RefPosition #152 @99 RefTypeUse <Ivl:38> BB01 regmask=[rcx] minReg=1 last fixed>
<RefPosition #153 @100 RefTypeKill <Reg:rax> BB01 regmask=[rax] minReg=1 last>
<RefPosition #154 @100 RefTypeKill <Reg:rcx> BB01 regmask=[rcx] minReg=1 last>
<RefPosition #155 @100 RefTypeKill <Reg:rdx> BB01 regmask=[rdx] minReg=1 last>
<RefPosition #156 @100 RefTypeKill <Reg:r8 > BB01 regmask=[r8] minReg=1 last>
<RefPosition #157 @100 RefTypeKill <Reg:r9 > BB01 regmask=[r9] minReg=1 last>
<RefPosition #158 @100 RefTypeKill <Reg:r10> BB01 regmask=[r10] minReg=1 last>
<RefPosition #159 @100 RefTypeKill <Reg:r11> BB01 regmask=[r11] minReg=1 last>
<RefPosition #160 @100 RefTypeFixedReg <Reg:rax> BB01 regmask=[rax] minReg=1>
<RefPosition #161 @100 RefTypeDef <Ivl:39> CALL BB01 regmask=[rax] minReg=1 fixed>
<RefPosition #162 @101 RefTypeUse <Ivl:39> BB01 regmask=[rax] minReg=1 last>
<RefPosition #163 @102 RefTypeDef <Ivl:5 V05> STORE_LCL_VAR BB01 regmask=[r12] minReg=1>
<RefPosition #164 @105 RefTypeFixedReg <Reg:r8 > BB01 regmask=[r8] minReg=1>
<RefPosition #165 @105 RefTypeUse <Ivl:13 V19> LCL_VAR BB01 regmask=[r8] minReg=1 copy fixed>
<RefPosition #166 @106 RefTypeFixedReg <Reg:r8 > BB01 regmask=[r8] minReg=1>
<RefPosition #167 @106 RefTypeDef <Ivl:40> PUTARG_REG BB01 regmask=[r8] minReg=1 fixed>
<RefPosition #168 @109 RefTypeFixedReg <Reg:rcx> BB01 regmask=[rcx] minReg=1>
<RefPosition #169 @109 RefTypeUse <Ivl:0 V00> LCL_VAR BB01 regmask=[rcx] minReg=1 copy fixed>
<RefPosition #170 @110 RefTypeFixedReg <Reg:rcx> BB01 regmask=[rcx] minReg=1>
<RefPosition #171 @110 RefTypeDef <Ivl:41> PUTARG_REG BB01 regmask=[rcx] minReg=1 fixed>
<RefPosition #172 @113 RefTypeFixedReg <Reg:rdx> BB01 regmask=[rdx] minReg=1>
<RefPosition #173 @113 RefTypeUse <Ivl:1 V01> LCL_VAR BB01 regmask=[rdx] minReg=1 copy fixed>
<RefPosition #174 @114 RefTypeFixedReg <Reg:rdx> BB01 regmask=[rdx] minReg=1>
<RefPosition #175 @114 RefTypeDef <Ivl:42> PUTARG_REG BB01 regmask=[rdx] minReg=1 fixed>
<RefPosition #176 @115 RefTypeFixedReg <Reg:r8 > BB01 regmask=[r8] minReg=1>
<RefPosition #177 @115 RefTypeUse <Ivl:40> BB01 regmask=[r8] minReg=1 last fixed>
<RefPosition #178 @115 RefTypeFixedReg <Reg:rcx> BB01 regmask=[rcx] minReg=1>
<RefPosition #179 @115 RefTypeUse <Ivl:41> BB01 regmask=[rcx] minReg=1 last fixed>
<RefPosition #180 @115 RefTypeFixedReg <Reg:rdx> BB01 regmask=[rdx] minReg=1>
<RefPosition #181 @115 RefTypeUse <Ivl:42> BB01 regmask=[rdx] minReg=1 last fixed>
<RefPosition #182 @116 RefTypeKill <Reg:rax> BB01 regmask=[rax] minReg=1 last>
<RefPosition #183 @116 RefTypeKill <Reg:rcx> BB01 regmask=[rcx] minReg=1 last>
<RefPosition #184 @116 RefTypeKill <Reg:rdx> BB01 regmask=[rdx] minReg=1 last>
<RefPosition #185 @116 RefTypeKill <Reg:r8 > BB01 regmask=[r8] minReg=1 last>
<RefPosition #186 @116 RefTypeKill <Reg:r9 > BB01 regmask=[r9] minReg=1 last>
<RefPosition #187 @116 RefTypeKill <Reg:r10> BB01 regmask=[r10] minReg=1 last>
<RefPosition #188 @116 RefTypeKill <Reg:r11> BB01 regmask=[r11] minReg=1 last>
<RefPosition #189 @116 RefTypeFixedReg <Reg:rax> BB01 regmask=[rax] minReg=1>
<RefPosition #190 @116 RefTypeDef <Ivl:43> CALL BB01 regmask=[rax] minReg=1 fixed>
<RefPosition #191 @117 RefTypeUse <Ivl:43> BB01 regmask=[rax] minReg=1 last>
<RefPosition #192 @118 RefTypeDef <Ivl:6 V06> STORE_LCL_VAR BB01 regmask=[rcx] minReg=1>
<RefPosition #193 @123 RefTypeUse <Ivl:0 V00> LCL_VAR BB01 regmask=[rsi] minReg=1>
<RefPosition #194 @123 RefTypeUse <Ivl:1 V01> LCL_VAR BB01 regmask=[rdi] minReg=1 last regOptional>
<RefPosition #195 @124 RefTypeDef <Ivl:44> ADD BB01 regmask=[rdi] minReg=1>
<RefPosition #196 @125 RefTypeUse <Ivl:44> BB01 regmask=[rdi] minReg=1 last>
<RefPosition #197 @126 RefTypeDef <Ivl:10 V13> STORE_LCL_VAR BB01 regmask=[rdi] minReg=1>
<RefPosition #198 @131 RefTypeUse <Ivl:10 V13> LCL_VAR BB01 regmask=[rdi] minReg=1 last regOptional>
<RefPosition #199 @131 RefTypeUse <Ivl:13 V19> LCL_VAR BB01 regmask=[rbx] minReg=1>
<RefPosition #200 @132 RefTypeDef <Ivl:45> MUL BB01 regmask=[rdi] minReg=1>
<RefPosition #201 @133 RefTypeUse <Ivl:45> BB01 regmask=[rdi] minReg=1 last>
<RefPosition #202 @134 RefTypeDef <Ivl:11 V14> STORE_LCL_VAR BB01 regmask=[rdi] minReg=1>
<RefPosition #203 @139 RefTypeUse <Ivl:0 V00> LCL_VAR BB01 regmask=[rsi] minReg=1 last regOptional>
<RefPosition #204 @139 RefTypeUse <Ivl:13 V19> LCL_VAR BB01 regmask=[rbx] minReg=1 last>
<RefPosition #205 @140 RefTypeDef <Ivl:46> MUL BB01 regmask=[rax] minReg=1>
<RefPosition #206 @141 RefTypeUse <Ivl:46> BB01 regmask=[rax] minReg=1 last>
<RefPosition #207 @142 RefTypeDef <Ivl:12 V15> STORE_LCL_VAR BB01 regmask=[rax] minReg=1>
<RefPosition #208 @149 RefTypeUse <Ivl:11 V14> LCL_VAR BB01 regmask=[rdi] minReg=1 last>
<RefPosition #209 @150 RefTypeDef <Ivl:47> RSH BB01 regmask=[rdi] minReg=1>
<RefPosition #210 @151 RefTypeFixedReg <Reg:rax> BB01 regmask=[rax] minReg=1>
<RefPosition #211 @151 RefTypeUse <Ivl:12 V15> LCL_VAR BB01 regmask=[rax] minReg=1 last fixed>
<RefPosition #212 @151 RefTypeUse <Ivl:47> BB01 regmask=[rdi] minReg=1 last delay regOptional>
<RefPosition #213 @152 RefTypeKill <Reg:rax> BB01 regmask=[rax] minReg=1 last>
<RefPosition #214 @152 RefTypeKill <Reg:rdx> BB01 regmask=[rdx] minReg=1 last>
<RefPosition #215 @152 RefTypeFixedReg <Reg:rax> BB01 regmask=[rax] minReg=1>
<RefPosition #216 @152 RefTypeDef <Ivl:48> DIV BB01 regmask=[rax] minReg=1 fixed>
<RefPosition #217 @153 RefTypeUse <Ivl:48> BB01 regmask=[rax] minReg=1 last>
<RefPosition #218 @154 RefTypeDef <Ivl:7 V07> STORE_LCL_VAR BB01 regmask=[rax] minReg=1>
<RefPosition #219 @159 RefTypeUse <Ivl:8 V10> LCL_VAR BB01 regmask=[rbp] minReg=1 last>
<RefPosition #220 @159 RefTypeUse <Ivl:3 V03> LCL_VAR BB01 regmask=[r14] minReg=1 last regOptional>
<RefPosition #221 @160 RefTypeDef <Ivl:49> ADD BB01 regmask=[rbp] minReg=1>
<RefPosition #222 @163 RefTypeUse <Ivl:49> BB01 regmask=[rbp] minReg=1 last>
<RefPosition #223 @163 RefTypeUse <Ivl:4 V04> LCL_VAR BB01 regmask=[r15] minReg=1 last regOptional>
<RefPosition #224 @164 RefTypeDef <Ivl:50> ADD BB01 regmask=[rbp] minReg=1>
<RefPosition #225 @167 RefTypeUse <Ivl:50> BB01 regmask=[rbp] minReg=1 last>
<RefPosition #226 @167 RefTypeUse <Ivl:5 V05> LCL_VAR BB01 regmask=[r12] minReg=1 last regOptional>
<RefPosition #227 @168 RefTypeDef <Ivl:51> ADD BB01 regmask=[rbp] minReg=1>
<RefPosition #228 @171 RefTypeUse <Ivl:51> BB01 regmask=[rbp] minReg=1 last>
<RefPosition #229 @171 RefTypeUse <Ivl:6 V06> LCL_VAR BB01 regmask=[rcx] minReg=1 last regOptional>
<RefPosition #230 @172 RefTypeDef <Ivl:52> ADD BB01 regmask=[rcx] minReg=1>
<RefPosition #231 @175 RefTypeUse <Ivl:52> BB01 regmask=[rcx] minReg=1 last>
<RefPosition #232 @175 RefTypeUse <Ivl:7 V07> LCL_VAR BB01 regmask=[rax] minReg=1 last regOptional>
<RefPosition #233 @176 RefTypeDef <Ivl:53> ADD BB01 regmask=[rax] minReg=1>
<RefPosition #234 @177 RefTypeFixedReg <Reg:rax> BB01 regmask=[rax] minReg=1>
<RefPosition #235 @177 RefTypeUse <Ivl:53> BB01 regmask=[rax] minReg=1 last fixed>
VAR REFPOSITIONS AFTER ALLOCATION
--- V00 (Interval 0)
<RefPosition #0 @0 RefTypeParamDef <Ivl:0 V00> BB00 regmask=[rsi] minReg=1 fixed regOptional>
<RefPosition #13 @15 RefTypeUse <Ivl:0 V00> LCL_VAR BB01 regmask=[rcx] minReg=1 copy fixed>
<RefPosition #42 @31 RefTypeUse <Ivl:0 V00> LCL_VAR BB01 regmask=[rdx] minReg=1 copy fixed>
<RefPosition #83 @61 RefTypeUse <Ivl:0 V00> LCL_VAR BB01 regmask=[rdx] minReg=1 copy fixed>
<RefPosition #133 @89 RefTypeUse <Ivl:0 V00> LCL_VAR BB01 regmask=[r8] minReg=1 copy fixed>
<RefPosition #169 @109 RefTypeUse <Ivl:0 V00> LCL_VAR BB01 regmask=[rcx] minReg=1 copy fixed>
<RefPosition #193 @123 RefTypeUse <Ivl:0 V00> LCL_VAR BB01 regmask=[rsi] minReg=1>
<RefPosition #203 @139 RefTypeUse <Ivl:0 V00> LCL_VAR BB01 regmask=[rsi] minReg=1 last regOptional>
--- V01 (Interval 1)
<RefPosition #1 @0 RefTypeParamDef <Ivl:1 V01> BB00 regmask=[rdi] minReg=1 fixed regOptional>
<RefPosition #17 @19 RefTypeUse <Ivl:1 V01> LCL_VAR BB01 regmask=[rdx] minReg=1 copy fixed>
<RefPosition #46 @35 RefTypeUse <Ivl:1 V01> LCL_VAR BB01 regmask=[r8] minReg=1 copy fixed>
<RefPosition #87 @65 RefTypeUse <Ivl:1 V01> LCL_VAR BB01 regmask=[r8] minReg=1 copy fixed>
<RefPosition #137 @93 RefTypeUse <Ivl:1 V01> LCL_VAR BB01 regmask=[r9] minReg=1 copy fixed>
<RefPosition #173 @113 RefTypeUse <Ivl:1 V01> LCL_VAR BB01 regmask=[rdx] minReg=1 copy fixed>
<RefPosition #194 @123 RefTypeUse <Ivl:1 V01> LCL_VAR BB01 regmask=[rdi] minReg=1 last regOptional>
--- V02 (Interval 2)
<RefPosition #2 @0 RefTypeParamDef <Ivl:2 V02> BB00 regmask=[r8] minReg=1 fixed regOptional>
<RefPosition #4 @5 RefTypeUse <Ivl:2 V02> LCL_VAR BB01 regmask=[r8] minReg=1 last>
--- V03 (Interval 3)
<RefPosition #72 @44 RefTypeDef <Ivl:3 V03> STORE_LCL_VAR BB01 regmask=[r14] minReg=1>
<RefPosition #220 @159 RefTypeUse <Ivl:3 V03> LCL_VAR BB01 regmask=[r14] minReg=1 last regOptional>
--- V04 (Interval 4)
<RefPosition #108 @70 RefTypeDef <Ivl:4 V04> STORE_LCL_VAR BB01 regmask=[r15] minReg=1>
<RefPosition #223 @163 RefTypeUse <Ivl:4 V04> LCL_VAR BB01 regmask=[r15] minReg=1 last regOptional>
--- V05 (Interval 5)
<RefPosition #163 @102 RefTypeDef <Ivl:5 V05> STORE_LCL_VAR BB01 regmask=[r12] minReg=1>
<RefPosition #226 @167 RefTypeUse <Ivl:5 V05> LCL_VAR BB01 regmask=[r12] minReg=1 last regOptional>
--- V06 (Interval 6)
<RefPosition #192 @118 RefTypeDef <Ivl:6 V06> STORE_LCL_VAR BB01 regmask=[rcx] minReg=1>
<RefPosition #229 @171 RefTypeUse <Ivl:6 V06> LCL_VAR BB01 regmask=[rcx] minReg=1 last regOptional>
--- V07 (Interval 7)
<RefPosition #218 @154 RefTypeDef <Ivl:7 V07> STORE_LCL_VAR BB01 regmask=[rax] minReg=1>
<RefPosition #232 @175 RefTypeUse <Ivl:7 V07> LCL_VAR BB01 regmask=[rax] minReg=1 last regOptional>
--- V08
--- V09
--- V10 (Interval 8)
<RefPosition #36 @24 RefTypeDef <Ivl:8 V10> STORE_LCL_VAR BB01 regmask=[rbp] minReg=1>
<RefPosition #219 @159 RefTypeUse <Ivl:8 V10> LCL_VAR BB01 regmask=[rbp] minReg=1 last>
--- V11 (Interval 9)
<RefPosition #126 @78 RefTypeDef <Ivl:9 V11> STORE_LCL_VAR BB01 regmask=[rdx] minReg=1>
<RefPosition #129 @85 RefTypeUse <Ivl:9 V11> LCL_VAR BB01 regmask=[rdx] minReg=1 last fixed>
--- V12
--- V13 (Interval 10)
<RefPosition #197 @126 RefTypeDef <Ivl:10 V13> STORE_LCL_VAR BB01 regmask=[rdi] minReg=1>
<RefPosition #198 @131 RefTypeUse <Ivl:10 V13> LCL_VAR BB01 regmask=[rdi] minReg=1 last regOptional>
--- V14 (Interval 11)
<RefPosition #202 @134 RefTypeDef <Ivl:11 V14> STORE_LCL_VAR BB01 regmask=[rdi] minReg=1>
<RefPosition #208 @149 RefTypeUse <Ivl:11 V14> LCL_VAR BB01 regmask=[rdi] minReg=1 last>
--- V15 (Interval 12)
<RefPosition #207 @142 RefTypeDef <Ivl:12 V15> STORE_LCL_VAR BB01 regmask=[rax] minReg=1>
<RefPosition #211 @151 RefTypeUse <Ivl:12 V15> LCL_VAR BB01 regmask=[rax] minReg=1 last fixed>
--- V16
--- V17
--- V18
--- V19 (Interval 13)
<RefPosition #7 @8 RefTypeDef <Ivl:13 V19> STORE_LCL_VAR BB01 regmask=[rbx] minReg=1>
<RefPosition #9 @11 RefTypeUse <Ivl:13 V19> LCL_VAR BB01 regmask=[r8] minReg=1 copy fixed>
<RefPosition #38 @27 RefTypeUse <Ivl:13 V19> LCL_VAR BB01 regmask=[r9] minReg=1 copy fixed>
<RefPosition #74 @53 RefTypeUse <Ivl:13 V19> LCL_VAR BB01 regmask=[r9] minReg=1 copy fixed>
<RefPosition #127 @81 RefTypeUse <Ivl:13 V19> LCL_VAR BB01 regmask=[rbx] minReg=1>
<RefPosition #165 @105 RefTypeUse <Ivl:13 V19> LCL_VAR BB01 regmask=[r8] minReg=1 copy fixed>
<RefPosition #199 @131 RefTypeUse <Ivl:13 V19> LCL_VAR BB01 regmask=[rbx] minReg=1>
<RefPosition #204 @139 RefTypeUse <Ivl:13 V19> LCL_VAR BB01 regmask=[rbx] minReg=1 last>
Active intervals at end of allocation:
-----------------------
RESOLVING BB BOUNDARIES
-----------------------
Resolution Candidates: {V00 V01 V02}
Has NoCritical Edges
Prior to Resolution
BB01 use def in out
{V00 V01 V02}
{V03 V04 V05 V06 V07 V08 V10 V11 V13 V14 V15 V19}
{V00 V01 V02}
{}
Var=Reg beg of BB01: V00=rsi V01=rdi V02=r8
Var=Reg end of BB01: none
RESOLVING EDGES
Set V00 argument initial register to rsi
Set V01 argument initial register to rdi
Set V02 argument initial register to r8
Trees after linear scan register allocator (LSRA)
-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..051) (return) i label target gcsafe newobj LIR
-----------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [000..051) (return), preds={} succs={}
N003 ( 2, 2) [000002] ------------ t2 = LCL_VAR int V02 arg2 u:1 r8 (last use) REG r8 $c0
/--* t2 int
N005 ( 3, 4) [000158] ------------ t158 = * CAST int <- ubyte <- int REG rbx $180
/--* t158 int
N007 ( 7, 7) [000189] DA---------- * STORE_LCL_VAR int V19 cse0 rbx REG rbx
N009 ( 3, 2) [000190] ------------ t190 = LCL_VAR int V19 cse0 rbx REG rbx $180
/--* t190 int
N011 (???,???) [000199] ------------ t199 = * PUTARG_REG int REG r8
N013 ( 1, 1) [000000] ------------ t0 = LCL_VAR int V00 arg0 u:1 rsi REG rsi $80
/--* t0 int
N015 (???,???) [000200] ------------ t200 = * PUTARG_REG int REG rcx
N017 ( 1, 1) [000001] ------------ t1 = LCL_VAR int V01 arg1 u:1 rdi REG rdi $81
/--* t1 int
N019 (???,???) [000201] ------------ t201 = * PUTARG_REG int REG rdx
/--* t199 int arg2 in r8
+--* t200 int arg0 in rcx
+--* t201 int arg1 in rdx
N021 ( 26, 19) [000003] --CXG------- t3 = * CALL int Test2.DoTestImpl1 REG rax $143
/--* t3 int
N023 ( 26, 19) [000011] DA-XG------- * STORE_LCL_VAR int V10 tmp1 d:2 rbp REG rbp
N025 ( 3, 2) [000192] ------------ t192 = LCL_VAR int V19 cse0 rbx REG rbx $180
/--* t192 int
N027 (???,???) [000202] ------------ t202 = * PUTARG_REG int REG r9
N029 ( 1, 1) [000005] ------------ t5 = LCL_VAR int V00 arg0 u:1 rsi REG rsi $80
/--* t5 int
N031 (???,???) [000203] ------------ t203 = * PUTARG_REG int REG rdx
N033 ( 1, 1) [000006] ------------ t6 = LCL_VAR int V01 arg1 u:1 rdi REG rdi $81
/--* t6 int
N035 (???,???) [000204] ------------ t204 = * PUTARG_REG int REG r8
N037 ( 3, 10) [000009] ------------ t9 = CNS_INT(h) long 0xd1ffab1e method REG rcx $240
/--* t9 long
N039 (???,???) [000205] ------------ t205 = * PUTARG_REG long REG rcx
/--* t202 int arg3 in r9
+--* t203 int arg1 in rdx
+--* t204 int arg2 in r8
+--* t205 long arg0 in rcx
N041 ( 22, 23) [000008] --CXG------- t8 = * CALL int Test2.DoTestImpl2 REG rax $148
/--* t8 int
N043 ( 26, 26) [000015] DA-XG------- * STORE_LCL_VAR int V03 loc0 d:2 r14 REG r14
N045 ( 1, 1) [000018] -c---------- t18 = CNS_INT int 0 REG NA $40
N047 ( 3, 2) [000016] Dc-----N---- t16 = LCL_VAR_ADDR byref V08 loc5 d:2 NA REG NA
/--* t16 byref
+--* t18 int
N049 (???,???) [000198] -A---------- * STOREIND byte REG NA
N051 ( 3, 2) [000193] ------------ t193 = LCL_VAR int V19 cse0 rbx REG rbx $180
/--* t193 int
N053 (???,???) [000206] ------------ t206 = * PUTARG_REG int REG r9
N055 ( 4, 5) [000020] ------------ t20 = LCL_FLD byte V08 loc5 u:2[+0] rcx (last use) REG rcx $301
/--* t20 byte
N057 (???,???) [000207] ------------ t207 = * PUTARG_REG int REG rcx
N059 ( 1, 1) [000021] ------------ t21 = LCL_VAR int V00 arg0 u:1 rsi REG rsi $80
/--* t21 int
N061 (???,???) [000208] ------------ t208 = * PUTARG_REG int REG rdx
N063 ( 1, 1) [000022] ------------ t22 = LCL_VAR int V01 arg1 u:1 rdi REG rdi $81
/--* t22 int
N065 (???,???) [000209] ------------ t209 = * PUTARG_REG int REG r8
/--* t206 int arg3 in r9
+--* t207 int arg0 in rcx
+--* t208 int arg1 in rdx
+--* t209 int arg2 in r8
N067 ( 23, 18) [000024] --CXG------- t24 = * CALL int Test2.DoTestImpl3 REG rax $14d
/--* t24 int
N069 ( 27, 21) [000029] DA-XG------- * STORE_LCL_VAR int V04 loc1 d:2 r15 REG r15
N071 ( 3, 10) [000030] ------------ t30 = CNS_INT(h) long 0xd1ffab1e method REG rcx $241
/--* t30 long
N073 (???,???) [000210] ------------ t210 = * PUTARG_REG long REG rcx
/--* t210 long arg0 in rcx
N075 ( 17, 16) [000031] --C--------- t31 = * CALL help ref HELPER.CORINFO_HELP_NEWSFAST REG rax $340
/--* t31 ref
N077 ( 17, 16) [000033] DA---------- * STORE_LCL_VAR ref V11 tmp2 d:2 rdx REG rdx
N079 ( 3, 2) [000194] ------------ t194 = LCL_VAR int V19 cse0 rbx REG rbx $180
/--* t194 int
N081 (???,???) [000211] ------------ * PUTARG_STK [+0x20] void REG NA
N083 ( 1, 1) [000036] ------------ t36 = LCL_VAR ref V11 tmp2 u:2 rdx (last use) REG rdx $340
/--* t36 ref
N085 (???,???) [000212] ------------ t212 = * PUTARG_REG ref REG rdx
N087 ( 1, 1) [000037] ------------ t37 = LCL_VAR int V00 arg0 u:1 rsi REG rsi $80
/--* t37 int
N089 (???,???) [000213] ------------ t213 = * PUTARG_REG int REG r8
N091 ( 1, 1) [000038] ------------ t38 = LCL_VAR int V01 arg1 u:1 rdi REG rdi $81
/--* t38 int
N093 (???,???) [000214] ------------ t214 = * PUTARG_REG int REG r9
N095 ( 3, 10) [000041] ------------ t41 = CNS_INT(h) long 0xd1ffab1e method REG rcx $242
/--* t41 long
N097 (???,???) [000215] ------------ t215 = * PUTARG_REG long REG rcx
/--* t212 ref arg1 in rdx
+--* t213 int arg2 in r8
+--* t214 int arg3 in r9
+--* t215 long arg0 in rcx
N099 ( 26, 24) [000040] --CXG------- t40 = * CALL int Test2.DoTestImpl4 REG rax $151
/--* t40 int
N101 ( 30, 27) [000044] DA-XG------- * STORE_LCL_VAR int V05 loc2 d:2 r12 REG r12
N103 ( 3, 2) [000195] ------------ t195 = LCL_VAR int V19 cse0 rbx REG rbx $180
/--* t195 int
N105 (???,???) [000216] ------------ t216 = * PUTARG_REG int REG r8
N107 ( 1, 1) [000045] ------------ t45 = LCL_VAR int V00 arg0 u:1 rsi REG rsi $80
/--* t45 int
N109 (???,???) [000217] ------------ t217 = * PUTARG_REG int REG rcx
N111 ( 1, 1) [000046] ------------ t46 = LCL_VAR int V01 arg1 u:1 rdi REG rdi $81
/--* t46 int
N113 (???,???) [000218] ------------ t218 = * PUTARG_REG int REG rdx
/--* t216 int arg2 in r8
+--* t217 int arg0 in rcx
+--* t218 int arg1 in rdx
N115 ( 19, 12) [000048] --CXG------- t48 = * CALL int Test2.DoTestImpl5 REG rax $156
/--* t48 int
N117 ( 23, 15) [000051] DA-XG------- * STORE_LCL_VAR int V06 loc3 d:2 rcx REG rcx
N119 ( 1, 1) [000052] ------------ t52 = LCL_VAR int V00 arg0 u:1 rsi REG rsi $80
N121 ( 1, 1) [000053] ------------ t53 = LCL_VAR int V01 arg1 u:1 rdi (last use) REG rdi $81
/--* t52 int
+--* t53 int
N123 ( 3, 3) [000140] ------------ t140 = * ADD int REG rdi $181
/--* t140 int
N125 ( 3, 3) [000114] DA---------- * STORE_LCL_VAR int V13 tmp4 d:2 rdi REG rdi
N127 ( 1, 1) [000115] ------------ t115 = LCL_VAR int V13 tmp4 u:2 rdi (last use) REG rdi $181
N129 ( 3, 2) [000196] ------------ t196 = LCL_VAR int V19 cse0 rbx REG rbx $180
/--* t115 int
+--* t196 int
N131 ( 8, 6) [000145] ------------ t145 = * MUL int REG rdi $182
/--* t145 int
N133 ( 8, 6) [000120] DA---------- * STORE_LCL_VAR int V14 tmp5 d:2 rdi REG rdi
N135 ( 1, 1) [000121] ------------ t121 = LCL_VAR int V00 arg0 u:1 rsi (last use) REG rsi $80
N137 ( 3, 2) [000197] ------------ t197 = LCL_VAR int V19 cse0 rbx (last use) REG rbx $180
/--* t121 int
+--* t197 int
N139 ( 8, 6) [000150] ------------ t150 = * MUL int REG rax $183
/--* t150 int
N141 ( 8, 6) [000131] DA---------- * STORE_LCL_VAR int V15 tmp6 d:2 rax REG rax
N143 ( 1, 1) [000132] ------------ t132 = LCL_VAR int V15 tmp6 u:2 rax (last use) REG rax $183
N145 ( 1, 1) [000127] ------------ t127 = LCL_VAR int V14 tmp5 u:2 rdi (last use) REG rdi $182
N147 ( 1, 1) [000152] -c---------- t152 = CNS_INT int 2 REG NA $42
/--* t127 int
+--* t152 int
N149 ( 3, 3) [000153] ------------ t153 = * RSH int REG rdi $184
/--* t132 int
+--* t153 int
N151 ( 24, 7) [000156] ---X-------- t156 = * DIV int REG rax $186
/--* t156 int
N153 ( 28, 10) [000058] DA-X-------- * STORE_LCL_VAR int V07 loc4 d:2 rax REG rax
N155 ( 1, 1) [000012] ------------ t12 = LCL_VAR int V10 tmp1 u:2 rbp (last use) REG rbp $143
N157 ( 3, 2) [000059] ------------ t59 = LCL_VAR int V03 loc0 u:2 r14 (last use) REG r14 $148
/--* t12 int
+--* t59 int
N159 ( 5, 4) [000060] ------------ t60 = * ADD int REG rbp $187
N161 ( 3, 2) [000061] ------------ t61 = LCL_VAR int V04 loc1 u:2 r15 (last use) REG r15 $14d
/--* t60 int
+--* t61 int
N163 ( 9, 7) [000062] ------------ t62 = * ADD int REG rbp $188
N165 ( 3, 2) [000063] ------------ t63 = LCL_VAR int V05 loc2 u:2 r12 (last use) REG r12 $151
/--* t62 int
+--* t63 int
N167 ( 13, 10) [000064] ------------ t64 = * ADD int REG rbp $189
N169 ( 3, 2) [000065] ------------ t65 = LCL_VAR int V06 loc3 u:2 rcx (last use) REG rcx $156
/--* t64 int
+--* t65 int
N171 ( 17, 13) [000066] ------------ t66 = * ADD int REG rcx $18a
N173 ( 3, 2) [000067] ------------ t67 = LCL_VAR int V07 loc4 u:2 rax (last use) REG rax $185
/--* t66 int
+--* t67 int
N175 ( 21, 16) [000068] ------------ t68 = * ADD int REG rax $18b
/--* t68 int
N177 ( 22, 17) [000069] ------------ * RETURN int REG NA $15c
-------------------------------------------------------------------------------------------------------------------
Final allocation
--------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+
Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |r12 |r14 |r15 |
--------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+
0.#0 V0 Parm Alloc rsi | | | | | |V0 a| | | | | | |
0.#1 V1 Parm Alloc rdi | | | | | |V0 a|V1 a| | | | | |
0.#2 V2 Parm Alloc r8 | | | | | |V0 a|V1 a|V2 a| | | | |
1.#3 BB1 PredBB0 | | | | | |V0 a|V1 a|V2 a| | | | |
5.#4 V2 Use * Keep r8 | | | | | |V0 a|V1 a|V2 i| | | | |
6.#5 I14 Def Alloc rbx | | | |I14a| |V0 a|V1 a| | | | | |
7.#6 I14 Use * Keep rbx | | | |I14i| |V0 a|V1 a| | | | | |
8.#7 V19 Def Alloc rbx | | | |V19a| |V0 a|V1 a| | | | | |
11.#8 r8 Fixd Keep r8 | | | |V19a| |V0 a|V1 a| | | | | |
11.#9 V19 Use Copy r8 | | | |V19a| |V0 a|V1 a|V19a| | | | |
12.#10 r8 Fixd Keep r8 | | | |V19a| |V0 a|V1 a| | | | | |
12.#11 I15 Def Alloc r8 | | | |V19a| |V0 a|V1 a|I15a| | | | |
15.#12 rcx Fixd Keep rcx | | | |V19a| |V0 a|V1 a|I15a| | | | |
15.#13 V0 Use Copy rcx | |V0 a| |V19a| |V0 a|V1 a|I15a| | | | |
16.#14 rcx Fixd Keep rcx | | | |V19a| |V0 a|V1 a|I15a| | | | |
16.#15 I16 Def Alloc rcx | |I16a| |V19a| |V0 a|V1 a|I15a| | | | |
19.#16 rdx Fixd Keep rdx | |I16a| |V19a| |V0 a|V1 a|I15a| | | | |
19.#17 V1 Use Copy rdx | |I16a|V1 a|V19a| |V0 a|V1 a|I15a| | | | |
20.#18 rdx Fixd Keep rdx | |I16a| |V19a| |V0 a|V1 a|I15a| | | | |
20.#19 I17 Def Alloc rdx | |I16a|I17a|V19a| |V0 a|V1 a|I15a| | | | |
21.#20 r8 Fixd Keep r8 | |I16a|I17a|V19a| |V0 a|V1 a|I15a| | | | |
21.#21 I15 Use * Keep r8 | |I16a|I17a|V19a| |V0 a|V1 a|I15i| | | | |
21.#22 rcx Fixd Keep rcx | |I16a|I17a|V19a| |V0 a|V1 a| | | | | |
21.#23 I16 Use * Keep rcx | |I16i|I17a|V19a| |V0 a|V1 a| | | | | |
21.#24 rdx Fixd Keep rdx | | |I17a|V19a| |V0 a|V1 a| | | | | |
21.#25 I17 Use * Keep rdx | | |I17i|V19a| |V0 a|V1 a| | | | | |
22.#26 rax Kill Keep rax | | | |V19a| |V0 a|V1 a| | | | | |
22.#27 rcx Kill Keep rcx | | | |V19a| |V0 a|V1 a| | | | | |
22.#28 rdx Kill Keep rdx | | | |V19a| |V0 a|V1 a| | | | | |
22.#29 r8 Kill Keep r8 | | | |V19a| |V0 a|V1 a| | | | | |
22.#30 r9 Kill Keep r9 | | | |V19a| |V0 a|V1 a| | | | | |
22.#31 r10 Kill Keep r10 | | | |V19a| |V0 a|V1 a| | | | | |
22.#32 r11 Kill Keep r11 | | | |V19a| |V0 a|V1 a| | | | | |
22.#33 rax Fixd Keep rax | | | |V19a| |V0 a|V1 a| | | | | |
22.#34 I18 Def Alloc rax |I18a| | |V19a| |V0 a|V1 a| | | | | |
23.#35 I18 Use * Keep rax |I18i| | |V19a| |V0 a|V1 a| | | | | |
24.#36 V10 Def Alloc rbp | | | |V19a|V10a|V0 a|V1 a| | | | | |
27.#37 r9 Fixd Keep r9 | | | |V19a|V10a|V0 a|V1 a| | | | | |
27.#38 V19 Use Copy r9 | | | |V19a|V10a|V0 a|V1 a| |V19a| | | |
28.#39 r9 Fixd Keep r9 | | | |V19a|V10a|V0 a|V1 a| | | | | |
28.#40 I19 Def Alloc r9 | | | |V19a|V10a|V0 a|V1 a| |I19a| | | |
31.#41 rdx Fixd Keep rdx | | | |V19a|V10a|V0 a|V1 a| |I19a| | | |
31.#42 V0 Use Copy rdx | | |V0 a|V19a|V10a|V0 a|V1 a| |I19a| | | |
32.#43 rdx Fixd Keep rdx | | | |V19a|V10a|V0 a|V1 a| |I19a| | | |
32.#44 I20 Def Alloc rdx | | |I20a|V19a|V10a|V0 a|V1 a| |I19a| | | |
35.#45 r8 Fixd Keep r8 | | |I20a|V19a|V10a|V0 a|V1 a| |I19a| | | |
35.#46 V1 Use Copy r8 | | |I20a|V19a|V10a|V0 a|V1 a|V1 a|I19a| | | |
36.#47 r8 Fixd Keep r8 | | |I20a|V19a|V10a|V0 a|V1 a| |I19a| | | |
36.#48 I21 Def Alloc r8 | | |I20a|V19a|V10a|V0 a|V1 a|I21a|I19a| | | |
38.#49 C22 Def Alloc rcx | |C22a|I20a|V19a|V10a|V0 a|V1 a|I21a|I19a| | | |
39.#50 rcx Fixd Keep rcx | |C22a|I20a|V19a|V10a|V0 a|V1 a|I21a|I19a| | | |
39.#51 C22 Use * Keep rcx | |C22i|I20a|V19a|V10a|V0 a|V1 a|I21a|I19a| | | |
40.#52 rcx Fixd Keep rcx | | |I20a|V19a|V10a|V0 a|V1 a|I21a|I19a| | | |
40.#53 I23 Def Alloc rcx | |I23a|I20a|V19a|V10a|V0 a|V1 a|I21a|I19a| | | |
41.#54 r9 Fixd Keep r9 | |I23a|I20a|V19a|V10a|V0 a|V1 a|I21a|I19a| | | |
41.#55 I19 Use * Keep r9 | |I23a|I20a|V19a|V10a|V0 a|V1 a|I21a|I19i| | | |
41.#56 rdx Fixd Keep rdx | |I23a|I20a|V19a|V10a|V0 a|V1 a|I21a| | | | |
41.#57 I20 Use * Keep rdx | |I23a|I20i|V19a|V10a|V0 a|V1 a|I21a| | | | |
41.#58 r8 Fixd Keep r8 | |I23a| |V19a|V10a|V0 a|V1 a|I21a| | | | |
41.#59 I21 Use * Keep r8 | |I23a| |V19a|V10a|V0 a|V1 a|I21i| | | | |
41.#60 rcx Fixd Keep rcx | |I23a| |V19a|V10a|V0 a|V1 a| | | | | |
41.#61 I23 Use * Keep rcx | |I23i| |V19a|V10a|V0 a|V1 a| | | | | |
42.#62 rax Kill Keep rax | | | |V19a|V10a|V0 a|V1 a| | | | | |
42.#63 rcx Kill Keep rcx | | | |V19a|V10a|V0 a|V1 a| | | | | |
42.#64 rdx Kill Keep rdx | | | |V19a|V10a|V0 a|V1 a| | | | | |
42.#65 r8 Kill Keep r8 | | | |V19a|V10a|V0 a|V1 a| | | | | |
42.#66 r9 Kill Keep r9 | | | |V19a|V10a|V0 a|V1 a| | | | | |
42.#67 r10 Kill Keep r10 | | | |V19a|V10a|V0 a|V1 a| | | | | |
42.#68 r11 Kill Keep r11 | | | |V19a|V10a|V0 a|V1 a| | | | | |
42.#69 rax Fixd Keep rax | | | |V19a|V10a|V0 a|V1 a| | | | | |
42.#70 I24 Def Alloc rax |I24a| | |V19a|V10a|V0 a|V1 a| | | | | |
43.#71 I24 Use * Keep rax |I24i| | |V19a|V10a|V0 a|V1 a| | | | | |
44.#72 V3 Def Alloc r14 | | | |V19a|V10a|V0 a|V1 a| | | |V3 a| |
53.#73 r9 Fixd Keep r9 | | | |V19a|V10a|V0 a|V1 a| | | |V3 a| |
--------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+
Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |r12 |r14 |r15 |
--------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+
53.#74 V19 Use Copy r9 | | | |V19a|V10a|V0 a|V1 a| |V19a| |V3 a| |
54.#75 r9 Fixd Keep r9 | | | |V19a|V10a|V0 a|V1 a| | | |V3 a| |
54.#76 I25 Def Alloc r9 | | | |V19a|V10a|V0 a|V1 a| |I25a| |V3 a| |
56.#77 I26 Def Alloc rcx | |I26a| |V19a|V10a|V0 a|V1 a| |I25a| |V3 a| |
57.#78 rcx Fixd Keep rcx | |I26a| |V19a|V10a|V0 a|V1 a| |I25a| |V3 a| |
57.#79 I26 Use * Keep rcx | |I26i| |V19a|V10a|V0 a|V1 a| |I25a| |V3 a| |
58.#80 rcx Fixd Keep rcx | | | |V19a|V10a|V0 a|V1 a| |I25a| |V3 a| |
58.#81 I27 Def Alloc rcx | |I27a| |V19a|V10a|V0 a|V1 a| |I25a| |V3 a| |
61.#82 rdx Fixd Keep rdx | |I27a| |V19a|V10a|V0 a|V1 a| |I25a| |V3 a| |
61.#83 V0 Use Copy rdx | |I27a|V0 a|V19a|V10a|V0 a|V1 a| |I25a| |V3 a| |
62.#84 rdx Fixd Keep rdx | |I27a| |V19a|V10a|V0 a|V1 a| |I25a| |V3 a| |
62.#85 I28 Def Alloc rdx | |I27a|I28a|V19a|V10a|V0 a|V1 a| |I25a| |V3 a| |
65.#86 r8 Fixd Keep r8 | |I27a|I28a|V19a|V10a|V0 a|V1 a| |I25a| |V3 a| |
65.#87 V1 Use Copy r8 | |I27a|I28a|V19a|V10a|V0 a|V1 a|V1 a|I25a| |V3 a| |
66.#88 r8 Fixd Keep r8 | |I27a|I28a|V19a|V10a|V0 a|V1 a| |I25a| |V3 a| |
66.#89 I29 Def Alloc r8 | |I27a|I28a|V19a|V10a|V0 a|V1 a|I29a|I25a| |V3 a| |
67.#90 r9 Fixd Keep r9 | |I27a|I28a|V19a|V10a|V0 a|V1 a|I29a|I25a| |V3 a| |
67.#91 I25 Use * Keep r9 | |I27a|I28a|V19a|V10a|V0 a|V1 a|I29a|I25i| |V3 a| |
67.#92 rcx Fixd Keep rcx | |I27a|I28a|V19a|V10a|V0 a|V1 a|I29a| | |V3 a| |
67.#93 I27 Use * Keep rcx | |I27i|I28a|V19a|V10a|V0 a|V1 a|I29a| | |V3 a| |
67.#94 rdx Fixd Keep rdx | | |I28a|V19a|V10a|V0 a|V1 a|I29a| | |V3 a| |
67.#95 I28 Use * Keep rdx | | |I28i|V19a|V10a|V0 a|V1 a|I29a| | |V3 a| |
67.#96 r8 Fixd Keep r8 | | | |V19a|V10a|V0 a|V1 a|I29a| | |V3 a| |
67.#97 I29 Use * Keep r8 | | | |V19a|V10a|V0 a|V1 a|I29i| | |V3 a| |
68.#98 rax Kill Keep rax | | | |V19a|V10a|V0 a|V1 a| | | |V3 a| |
68.#99 rcx Kill Keep rcx | | | |V19a|V10a|V0 a|V1 a| | | |V3 a| |
68.#100 rdx Kill Keep rdx | | | |V19a|V10a|V0 a|V1 a| | | |V3 a| |
68.#101 r8 Kill Keep r8 | | | |V19a|V10a|V0 a|V1 a| | | |V3 a| |
68.#102 r9 Kill Keep r9 | | | |V19a|V10a|V0 a|V1 a| | | |V3 a| |
68.#103 r10 Kill Keep r10 | | | |V19a|V10a|V0 a|V1 a| | | |V3 a| |
68.#104 r11 Kill Keep r11 | | | |V19a|V10a|V0 a|V1 a| | | |V3 a| |
68.#105 rax Fixd Keep rax | | | |V19a|V10a|V0 a|V1 a| | | |V3 a| |
68.#106 I30 Def Alloc rax |I30a| | |V19a|V10a|V0 a|V1 a| | | |V3 a| |
69.#107 I30 Use * Keep rax |I30i| | |V19a|V10a|V0 a|V1 a| | | |V3 a| |
70.#108 V4 Def Alloc r15 | | | |V19a|V10a|V0 a|V1 a| | | |V3 a|V4 a|
72.#109 C31 Def Alloc rcx | |C31a| |V19a|V10a|V0 a|V1 a| | | |V3 a|V4 a|
73.#110 rcx Fixd Keep rcx | |C31a| |V19a|V10a|V0 a|V1 a| | | |V3 a|V4 a|
73.#111 C31 Use * Keep rcx | |C31i| |V19a|V10a|V0 a|V1 a| | | |V3 a|V4 a|
74.#112 rcx Fixd Keep rcx | | | |V19a|V10a|V0 a|V1 a| | | |V3 a|V4 a|
74.#113 I32 Def Alloc rcx | |I32a| |V19a|V10a|V0 a|V1 a| | | |V3 a|V4 a|
75.#114 rcx Fixd Keep rcx | |I32a| |V19a|V10a|V0 a|V1 a| | | |V3 a|V4 a|
75.#115 I32 Use * Keep rcx | |I32i| |V19a|V10a|V0 a|V1 a| | | |V3 a|V4 a|
76.#116 rax Kill Keep rax | | | |V19a|V10a|V0 a|V1 a| | | |V3 a|V4 a|
76.#117 rcx Kill Keep rcx | | | |V19a|V10a|V0 a|V1 a| | | |V3 a|V4 a|
76.#118 rdx Kill Keep rdx | | | |V19a|V10a|V0 a|V1 a| | | |V3 a|V4 a|
76.#119 r8 Kill Keep r8 | | | |V19a|V10a|V0 a|V1 a| | | |V3 a|V4 a|
76.#120 r9 Kill Keep r9 | | | |V19a|V10a|V0 a|V1 a| | | |V3 a|V4 a|
76.#121 r10 Kill Keep r10 | | | |V19a|V10a|V0 a|V1 a| | | |V3 a|V4 a|
76.#122 r11 Kill Keep r11 | | | |V19a|V10a|V0 a|V1 a| | | |V3 a|V4 a|
76.#123 rax Fixd Keep rax | | | |V19a|V10a|V0 a|V1 a| | | |V3 a|V4 a|
76.#124 I33 Def Alloc rax |I33a| | |V19a|V10a|V0 a|V1 a| | | |V3 a|V4 a|
77.#125 I33 Use * Keep rax |I33i| | |V19a|V10a|V0 a|V1 a| | | |V3 a|V4 a|
78.#126 V11 Def Alloc rdx | | |V11a|V19a|V10a|V0 a|V1 a| | | |V3 a|V4 a|
81.#127 V19 Use Keep rbx | | |V11a|V19a|V10a|V0 a|V1 a| | | |V3 a|V4 a|
85.#128 rdx Fixd Keep rdx | | |V11a|V19a|V10a|V0 a|V1 a| | | |V3 a|V4 a|
85.#129 V11 Use * Keep rdx | | |V11i|V19a|V10a|V0 a|V1 a| | | |V3 a|V4 a|
86.#130 rdx Fixd Keep rdx | | | |V19a|V10a|V0 a|V1 a| | | |V3 a|V4 a|
86.#131 I34 Def Alloc rdx | | |I34a|V19a|V10a|V0 a|V1 a| | | |V3 a|V4 a|
89.#132 r8 Fixd Keep r8 | | |I34a|V19a|V10a|V0 a|V1 a| | | |V3 a|V4 a|
--------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+
Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |r12 |r14 |r15 |
--------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+
89.#133 V0 Use Copy r8 | | |I34a|V19a|V10a|V0 a|V1 a|V0 a| | |V3 a|V4 a|
90.#134 r8 Fixd Keep r8 | | |I34a|V19a|V10a|V0 a|V1 a| | | |V3 a|V4 a|
90.#135 I35 Def Alloc r8 | | |I34a|V19a|V10a|V0 a|V1 a|I35a| | |V3 a|V4 a|
93.#136 r9 Fixd Keep r9 | | |I34a|V19a|V10a|V0 a|V1 a|I35a| | |V3 a|V4 a|
93.#137 V1 Use Copy r9 | | |I34a|V19a|V10a|V0 a|V1 a|I35a|V1 a| |V3 a|V4 a|
94.#138 r9 Fixd Keep r9 | | |I34a|V19a|V10a|V0 a|V1 a|I35a| | |V3 a|V4 a|
94.#139 I36 Def Alloc r9 | | |I34a|V19a|V10a|V0 a|V1 a|I35a|I36a| |V3 a|V4 a|
96.#140 C37 Def Alloc rcx | |C37a|I34a|V19a|V10a|V0 a|V1 a|I35a|I36a| |V3 a|V4 a|
97.#141 rcx Fixd Keep rcx | |C37a|I34a|V19a|V10a|V0 a|V1 a|I35a|I36a| |V3 a|V4 a|
97.#142 C37 Use * Keep rcx | |C37i|I34a|V19a|V10a|V0 a|V1 a|I35a|I36a| |V3 a|V4 a|
98.#143 rcx Fixd Keep rcx | | |I34a|V19a|V10a|V0 a|V1 a|I35a|I36a| |V3 a|V4 a|
98.#144 I38 Def Alloc rcx | |I38a|I34a|V19a|V10a|V0 a|V1 a|I35a|I36a| |V3 a|V4 a|
99.#145 rdx Fixd Keep rdx | |I38a|I34a|V19a|V10a|V0 a|V1 a|I35a|I36a| |V3 a|V4 a|
99.#146 I34 Use * Keep rdx | |I38a|I34i|V19a|V10a|V0 a|V1 a|I35a|I36a| |V3 a|V4 a|
99.#147 r8 Fixd Keep r8 | |I38a| |V19a|V10a|V0 a|V1 a|I35a|I36a| |V3 a|V4 a|
99.#148 I35 Use * Keep r8 | |I38a| |V19a|V10a|V0 a|V1 a|I35i|I36a| |V3 a|V4 a|
99.#149 r9 Fixd Keep r9 | |I38a| |V19a|V10a|V0 a|V1 a| |I36a| |V3 a|V4 a|
99.#150 I36 Use * Keep r9 | |I38a| |V19a|V10a|V0 a|V1 a| |I36i| |V3 a|V4 a|
99.#151 rcx Fixd Keep rcx | |I38a| |V19a|V10a|V0 a|V1 a| | | |V3 a|V4 a|
99.#152 I38 Use * Keep rcx | |I38i| |V19a|V10a|V0 a|V1 a| | | |V3 a|V4 a|
100.#153 rax Kill Keep rax | | | |V19a|V10a|V0 a|V1 a| | | |V3 a|V4 a|
100.#154 rcx Kill Keep rcx | | | |V19a|V10a|V0 a|V1 a| | | |V3 a|V4 a|
100.#155 rdx Kill Keep rdx | | | |V19a|V10a|V0 a|V1 a| | | |V3 a|V4 a|
100.#156 r8 Kill Keep r8 | | | |V19a|V10a|V0 a|V1 a| | | |V3 a|V4 a|
100.#157 r9 Kill Keep r9 | | | |V19a|V10a|V0 a|V1 a| | | |V3 a|V4 a|
100.#158 r10 Kill Keep r10 | | | |V19a|V10a|V0 a|V1 a| | | |V3 a|V4 a|
100.#159 r11 Kill Keep r11 | | | |V19a|V10a|V0 a|V1 a| | | |V3 a|V4 a|
100.#160 rax Fixd Keep rax | | | |V19a|V10a|V0 a|V1 a| | | |V3 a|V4 a|
100.#161 I39 Def Alloc rax |I39a| | |V19a|V10a|V0 a|V1 a| | | |V3 a|V4 a|
101.#162 I39 Use * Keep rax |I39i| | |V19a|V10a|V0 a|V1 a| | | |V3 a|V4 a|
102.#163 V5 Def Alloc r12 | | | |V19a|V10a|V0 a|V1 a| | |V5 a|V3 a|V4 a|
105.#164 r8 Fixd Keep r8 | | | |V19a|V10a|V0 a|V1 a| | |V5 a|V3 a|V4 a|
105.#165 V19 Use Copy r8 | | | |V19a|V10a|V0 a|V1 a|V19a| |V5 a|V3 a|V4 a|
106.#166 r8 Fixd Keep r8 | | | |V19a|V10a|V0 a|V1 a| | |V5 a|V3 a|V4 a|
106.#167 I40 Def Alloc r8 | | | |V19a|V10a|V0 a|V1 a|I40a| |V5 a|V3 a|V4 a|
109.#168 rcx Fixd Keep rcx | | | |V19a|V10a|V0 a|V1 a|I40a| |V5 a|V3 a|V4 a|
109.#169 V0 Use Copy rcx | |V0 a| |V19a|V10a|V0 a|V1 a|I40a| |V5 a|V3 a|V4 a|
110.#170 rcx Fixd Keep rcx | | | |V19a|V10a|V0 a|V1 a|I40a| |V5 a|V3 a|V4 a|
110.#171 I41 Def Alloc rcx | |I41a| |V19a|V10a|V0 a|V1 a|I40a| |V5 a|V3 a|V4 a|
113.#172 rdx Fixd Keep rdx | |I41a| |V19a|V10a|V0 a|V1 a|I40a| |V5 a|V3 a|V4 a|
113.#173 V1 Use Copy rdx | |I41a|V1 a|V19a|V10a|V0 a|V1 a|I40a| |V5 a|V3 a|V4 a|
114.#174 rdx Fixd Keep rdx | |I41a| |V19a|V10a|V0 a|V1 a|I40a| |V5 a|V3 a|V4 a|
114.#175 I42 Def Alloc rdx | |I41a|I42a|V19a|V10a|V0 a|V1 a|I40a| |V5 a|V3 a|V4 a|
115.#176 r8 Fixd Keep r8 | |I41a|I42a|V19a|V10a|V0 a|V1 a|I40a| |V5 a|V3 a|V4 a|
115.#177 I40 Use * Keep r8 | |I41a|I42a|V19a|V10a|V0 a|V1 a|I40i| |V5 a|V3 a|V4 a|
115.#178 rcx Fixd Keep rcx | |I41a|I42a|V19a|V10a|V0 a|V1 a| | |V5 a|V3 a|V4 a|
115.#179 I41 Use * Keep rcx | |I41i|I42a|V19a|V10a|V0 a|V1 a| | |V5 a|V3 a|V4 a|
115.#180 rdx Fixd Keep rdx | | |I42a|V19a|V10a|V0 a|V1 a| | |V5 a|V3 a|V4 a|
115.#181 I42 Use * Keep rdx | | |I42i|V19a|V10a|V0 a|V1 a| | |V5 a|V3 a|V4 a|
116.#182 rax Kill Keep rax | | | |V19a|V10a|V0 a|V1 a| | |V5 a|V3 a|V4 a|
116.#183 rcx Kill Keep rcx | | | |V19a|V10a|V0 a|V1 a| | |V5 a|V3 a|V4 a|
116.#184 rdx Kill Keep rdx | | | |V19a|V10a|V0 a|V1 a| | |V5 a|V3 a|V4 a|
116.#185 r8 Kill Keep r8 | | | |V19a|V10a|V0 a|V1 a| | |V5 a|V3 a|V4 a|
116.#186 r9 Kill Keep r9 | | | |V19a|V10a|V0 a|V1 a| | |V5 a|V3 a|V4 a|
116.#187 r10 Kill Keep r10 | | | |V19a|V10a|V0 a|V1 a| | |V5 a|V3 a|V4 a|
116.#188 r11 Kill Keep r11 | | | |V19a|V10a|V0 a|V1 a| | |V5 a|V3 a|V4 a|
116.#189 rax Fixd Keep rax | | | |V19a|V10a|V0 a|V1 a| | |V5 a|V3 a|V4 a|
116.#190 I43 Def Alloc rax |I43a| | |V19a|V10a|V0 a|V1 a| | |V5 a|V3 a|V4 a|
117.#191 I43 Use * Keep rax |I43i| | |V19a|V10a|V0 a|V1 a| | |V5 a|V3 a|V4 a|
118.#192 V6 Def Alloc rcx | |V6 a| |V19a|V10a|V0 a|V1 a| | |V5 a|V3 a|V4 a|
123.#193 V0 Use Keep rsi | |V6 a| |V19a|V10a|V0 a|V1 a| | |V5 a|V3 a|V4 a|
123.#194 V1 Use * Keep rdi | |V6 a| |V19a|V10a|V0 a|V1 i| | |V5 a|V3 a|V4 a|
124.#195 I44 Def Alloc rdi | |V6 a| |V19a|V10a|V0 a|I44a| | |V5 a|V3 a|V4 a|
125.#196 I44 Use * Keep rdi | |V6 a| |V19a|V10a|V0 a|I44i| | |V5 a|V3 a|V4 a|
126.#197 V13 Def Alloc rdi | |V6 a| |V19a|V10a|V0 a|V13a| | |V5 a|V3 a|V4 a|
131.#198 V13 Use * Keep rdi | |V6 a| |V19a|V10a|V0 a|V13i| | |V5 a|V3 a|V4 a|
131.#199 V19 Use Keep rbx | |V6 a| |V19a|V10a|V0 a| | | |V5 a|V3 a|V4 a|
132.#200 I45 Def Alloc rdi | |V6 a| |V19a|V10a|V0 a|I45a| | |V5 a|V3 a|V4 a|
133.#201 I45 Use * Keep rdi | |V6 a| |V19a|V10a|V0 a|I45i| | |V5 a|V3 a|V4 a|
134.#202 V14 Def Alloc rdi | |V6 a| |V19a|V10a|V0 a|V14a| | |V5 a|V3 a|V4 a|
139.#203 V0 Use * Keep rsi | |V6 a| |V19a|V10a|V0 i|V14a| | |V5 a|V3 a|V4 a|
139.#204 V19 Use * Keep rbx | |V6 a| |V19i|V10a| |V14a| | |V5 a|V3 a|V4 a|
140.#205 I46 Def Alloc rax |I46a|V6 a| | |V10a| |V14a| | |V5 a|V3 a|V4 a|
141.#206 I46 Use * Keep rax |I46i|V6 a| | |V10a| |V14a| | |V5 a|V3 a|V4 a|
142.#207 V15 Def Alloc rax |V15a|V6 a| | |V10a| |V14a| | |V5 a|V3 a|V4 a|
149.#208 V14 Use * Keep rdi |V15a|V6 a| | |V10a| |V14i| | |V5 a|V3 a|V4 a|
150.#209 I47 Def Alloc rdi |V15a|V6 a| | |V10a| |I47a| | |V5 a|V3 a|V4 a|
151.#210 rax Fixd Keep rax |V15a|V6 a| | |V10a| |I47a| | |V5 a|V3 a|V4 a|
151.#211 V15 Use * Keep rax |V15i|V6 a| | |V10a| |I47a| | |V5 a|V3 a|V4 a|
151.#212 I47 Use *D Keep rdi | |V6 a| | |V10a| |I47i| | |V5 a|V3 a|V4 a|
152.#213 rax Kill Keep rax | |V6 a| | |V10a| | | | |V5 a|V3 a|V4 a|
152.#214 rdx Kill Keep rdx | |V6 a| | |V10a| | | | |V5 a|V3 a|V4 a|
152.#215 rax Fixd Keep rax | |V6 a| | |V10a| | | | |V5 a|V3 a|V4 a|
152.#216 I48 Def Alloc rax |I48a|V6 a| | |V10a| | | | |V5 a|V3 a|V4 a|
153.#217 I48 Use * Keep rax |I48i|V6 a| | |V10a| | | | |V5 a|V3 a|V4 a|
154.#218 V7 Def Alloc rax |V7 a|V6 a| | |V10a| | | | |V5 a|V3 a|V4 a|
159.#219 V10 Use * Keep rbp |V7 a|V6 a| | |V10i| | | | |V5 a|V3 a|V4 a|
159.#220 V3 Use * Keep r14 |V7 a|V6 a| | | | | | | |V5 a|V3 i|V4 a|
160.#221 I49 Def Alloc rbp |V7 a|V6 a| | |I49a| | | | |V5 a| |V4 a|
163.#222 I49 Use * Keep rbp |V7 a|V6 a| | |I49i| | | | |V5 a| |V4 a|
163.#223 V4 Use * Keep r15 |V7 a|V6 a| | | | | | | |V5 a| |V4 i|
164.#224 I50 Def Alloc rbp |V7 a|V6 a| | |I50a| | | | |V5 a| | |
167.#225 I50 Use * Keep rbp |V7 a|V6 a| | |I50i| | | | |V5 a| | |
167.#226 V5 Use * Keep r12 |V7 a|V6 a| | | | | | | |V5 i| | |
168.#227 I51 Def Alloc rbp |V7 a|V6 a| | |I51a| | | | | | | |
171.#228 I51 Use * Keep rbp |V7 a|V6 a| | |I51i| | | | | | | |
171.#229 V6 Use * Keep rcx |V7 a|V6 i| | | | | | | | | | |
172.#230 I52 Def Alloc rcx |V7 a|I52a| | | | | | | | | | |
175.#231 I52 Use * Keep rcx |V7 a|I52i| | | | | | | | | | |
175.#232 V7 Use * Keep rax |V7 i| | | | | | | | | | | |
176.#233 I53 Def Alloc rax |I53a| | | | | | | | | | | |
177.#234 rax Fixd Keep rax |I53a| | | | | | | | | | | |
177.#235 I53 Use * Keep rax |I53i| | | | | | | | | | | |
Recording the maximum number of concurrent spills:
----------
LSRA Stats
----------
Total Tracked Vars: 15
Total Reg Cand Vars: 14
Total number of Intervals: 53
Total number of RefPositions: 235
Total Spill Count: 0 Weighted: 0
Total CopyReg Count: 0 Weighted: 0
Total ResolutionMov Count: 0 Weighted: 0
Total number of split edges: 0
Total Number of spill temps created: 0
TUPLE STYLE DUMP WITH REGISTER ASSIGNMENTS
Incoming Parameters: V00(rcx=>rsi) V01(rdx=>rdi) V02(r8)
BB01 [000..051) (return), preds={} succs={}
=====
N003. V02(r8*)
N005. rbx = CAST ; r8*
* N007. V19(rbx); rbx
N009. V19(rbx)
N011. r8 = PUTARG_REG; rbx
N013. V00(rsi)
N015. rcx = PUTARG_REG; rsi
N017. V01(rdi)
N019. rdx = PUTARG_REG; rdi
N021. rax = CALL ; r8,rcx,rdx
* N023. V10(rbp); rax
N025. V19(rbx)
N027. r9 = PUTARG_REG; rbx
N029. V00(rsi)
N031. rdx = PUTARG_REG; rsi
N033. V01(rdi)
N035. r8 = PUTARG_REG; rdi
N037. rcx = CNS_INT(h) 0xd1ffab1e method
N039. rcx = PUTARG_REG; rcx
N041. rax = CALL ; r9,rdx,r8,rcx
* N043. V03(r14); rax
N045. CNS_INT 0
N047. LCL_VAR_ADDR V08 loc5 d:2 NA
N049. STOREIND
N051. V19(rbx)
N053. r9 = PUTARG_REG; rbx
N055. rcx* = V08 MEM
N057. rcx = PUTARG_REG; rcx*
N059. V00(rsi)
N061. rdx = PUTARG_REG; rsi
N063. V01(rdi)
N065. r8 = PUTARG_REG; rdi
N067. rax = CALL ; r9,rcx,rdx,r8
* N069. V04(r15); rax
N071. rcx = CNS_INT(h) 0xd1ffab1e method
N073. rcx = PUTARG_REG; rcx
N075. rax = CALL help; rcx
* N077. V11(rdx); rax
N079. V19(rbx)
N081. PUTARG_STK [+0x20]; rbx
N083. V11(rdx*)
N085. rdx = PUTARG_REG; rdx*
N087. V00(rsi)
N089. r8 = PUTARG_REG; rsi
N091. V01(rdi)
N093. r9 = PUTARG_REG; rdi
N095. rcx = CNS_INT(h) 0xd1ffab1e method
N097. rcx = PUTARG_REG; rcx
N099. rax = CALL ; rdx,r8,r9,rcx
* N101. V05(r12); rax
N103. V19(rbx)
N105. r8 = PUTARG_REG; rbx
N107. V00(rsi)
N109. rcx = PUTARG_REG; rsi
N111. V01(rdi)
N113. rdx = PUTARG_REG; rdi
N115. rax = CALL ; r8,rcx,rdx
* N117. V06(rcx); rax
N119. V00(rsi)
N121. V01(rdi*)
N123. rdi = ADD ; rsi,rdi*
* N125. V13(rdi); rdi
N127. V13(rdi*)
N129. V19(rbx)
N131. rdi = MUL ; rdi*,rbx
* N133. V14(rdi); rdi
N135. V00(rsi*)
N137. V19(rbx*)
N139. rax = MUL ; rsi*,rbx*
* N141. V15(rax); rax
N143. V15(rax*)
N145. V14(rdi*)
N147. CNS_INT 2
N149. rdi = RSH ; rdi*
N151. rax = DIV ; rax*,rdi
* N153. V07(rax); rax
N155. V10(rbp*)
N157. V03(r14*)
N159. rbp = ADD ; rbp*,r14*
N161. V04(r15*)
N163. rbp = ADD ; rbp,r15*
N165. V05(r12*)
N167. rbp = ADD ; rbp,r12*
N169. V06(rcx*)
N171. rcx = ADD ; rbp,rcx*
N173. V07(rax*)
N175. rax = ADD ; rcx,rax*
N177. RETURN ; rax
Var=Reg end of BB01: none
*************** In genGenerateCode()
-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..051) (return) i label target gcsafe newobj LIR
-----------------------------------------------------------------------------------------------------------------------------------------
*************** In fgDebugCheckBBlist
Finalizing stack frame
Recording Var Locations at start of BB01
V00(rsi) V01(rdi) V02(r8)
Modified regs: [rax rcx rdx rbx rbp rsi rdi r8-r12 r14-r15]
Callee-saved registers pushed: 7 [rbx rbp rsi rdi r12 r14-r15]
*************** In lvaAssignFrameOffsets(FINAL_FRAME_LAYOUT)
Assign V08 loc5, size=8, stkOffs=-0x48
Assign V09 OutArgs, size=40, stkOffs=-0x70
; Final local variable assignments
;
; V00 arg0 [V00,T00] ( 9, 9 ) int -> rsi
; V01 arg1 [V01,T01] ( 8, 8 ) int -> rdi
; V02 arg2 [V02,T03] ( 3, 3 ) ubyte -> r8
; V03 loc0 [V03,T08] ( 2, 2 ) int -> r14
; V04 loc1 [V04,T09] ( 2, 2 ) int -> r15
; V05 loc2 [V05,T10] ( 2, 2 ) int -> r12
; V06 loc3 [V06,T11] ( 2, 2 ) int -> rcx
; V07 loc4 [V07,T12] ( 2, 2 ) int -> rax
; V08 loc5 [V08,T13] ( 2, 2 ) struct ( 8) [rsp+0x28] do-not-enreg[SF] must-init ld-addr-op
; V09 OutArgs [V09 ] ( 1, 1 ) lclBlk (40) [rsp+0x00] "OutgoingArgSpace"
; V10 tmp1 [V10,T05] ( 2, 4 ) int -> rbp "impAppendStmt"
; V11 tmp2 [V11,T04] ( 2, 4 ) ref -> rdx class-hnd exact "NewObj constructor temp"
;* V12 tmp3 [V12 ] ( 0, 0 ) struct ( 8) zero-ref do-not-enreg[SF] ld-addr-op "Inline ldloca(s) first use temp"
; V13 tmp4 [V13,T06] ( 2, 4 ) int -> rdi "impAppendStmt"
; V14 tmp5 [V14,T14] ( 2, 2 ) int -> rdi "Inline stloc first use temp"
; V15 tmp6 [V15,T07] ( 2, 4 ) int -> rax "impAppendStmt"
;* V16 tmp7 [V16 ] ( 0, 0 ) int -> zero-ref "Inlining Arg"
;* V17 tmp8 [V17 ] ( 0, 0 ) int -> zero-ref "Inlining Arg"
;* V18 tmp9 [V18 ] ( 0, 0 ) int -> zero-ref "Inlining Arg"
; V19 cse0 [V19,T02] ( 8, 8 ) int -> rbx "ValNumCSE"
;
; Lcl frame size = 48
Setting stack level from -572662307 to 0
=============== Generating BB01 [000..051) (return), preds={} succs={} flags=0x00000000.408b0020: i label target gcsafe newobj LIR
BB01 IN (3)={V00 V01 V02} + ByrefExposed + GcHeap
OUT(0)={ }
Recording Var Locations at start of BB01
V00(rsi) V01(rdi) V02(r8)
Change life 0000000000000000 {} -> 000000000000000B {V00 V01 V02}
V00 in reg rsi is becoming live [------]
Live regs: 00000000 {} => 00000040 {rsi}
V01 in reg rdi is becoming live [------]
Live regs: 00000040 {rsi} => 000000C0 {rsi rdi}
V02 in reg r8 is becoming live [------]
Live regs: 000000C0 {rsi rdi} => 000001C0 {rsi rdi r8}
Live regs: (unchanged) 000001C0 {rsi rdi r8}
GC regs: (unchanged) 00000000 {}
Byref regs: (unchanged) 00000000 {}
L_M55298_BB01:
Label: IG02, GCvars=0000000000000000 {}, gcrefRegs=00000000 {}, byrefRegs=00000000 {}
Scope info: begin block BB01, IL range [000..051)
Scope info: open scopes =
0 (V00 arg0) [000..051)
1 (V01 arg1) [000..051)
2 (V02 arg2) [000..051)
Generating: N003 ( 2, 2) [000002] ------------ t2 = LCL_VAR int V02 arg2 u:1 r8 (last use) REG r8 $c0
/--* t2 int
Generating: N005 ( 3, 4) [000158] ------------ t158 = * CAST int <- ubyte <- int REG rbx $180
V02 in reg r8 is becoming dead [000002]
Live regs: 000001C0 {rsi rdi r8} => 000000C0 {rsi rdi}
Live vars: {V00 V01 V02} => {V00 V01}
IN0001: movzx rbx, r8b
/--* t158 int
Generating: N007 ( 7, 7) [000189] DA---------- * STORE_LCL_VAR int V19 cse0 rbx REG rbx
V19 in reg rbx is becoming live [000189]
Live regs: 000000C0 {rsi rdi} => 000000C8 {rbx rsi rdi}
Live vars: {V00 V01} => {V00 V01 V19}
Generating: N009 ( 3, 2) [000190] ------------ t190 = LCL_VAR int V19 cse0 rbx REG rbx $180
/--* t190 int
Generating: N011 (???,???) [000199] ------------ t199 = * PUTARG_REG int REG r8
IN0002: mov r8d, ebx
Generating: N013 ( 1, 1) [000000] ------------ t0 = LCL_VAR int V00 arg0 u:1 rsi REG rsi $80
/--* t0 int
Generating: N015 (???,???) [000200] ------------ t200 = * PUTARG_REG int REG rcx
IN0003: mov ecx, esi
Generating: N017 ( 1, 1) [000001] ------------ t1 = LCL_VAR int V01 arg1 u:1 rdi REG rdi $81
/--* t1 int
Generating: N019 (???,???) [000201] ------------ t201 = * PUTARG_REG int REG rdx
IN0004: mov edx, edi
/--* t199 int arg2 in r8
+--* t200 int arg0 in rcx
+--* t201 int arg1 in rdx
Generating: N021 ( 26, 19) [000003] --CXG------- t3 = * CALL int Test2.DoTestImpl1 REG rax $143
Call: GCvars=0000000000000000 {}, gcrefRegs=00000000 {}, byrefRegs=00000000 {}
IN0005: call Test2:DoTestImpl1(int,int,ubyte):int
/--* t3 int
Generating: N023 ( 26, 19) [000011] DA-XG------- * STORE_LCL_VAR int V10 tmp1 d:2 rbp REG rbp
IN0006: mov ebp, eax
V10 in reg rbp is becoming live [000011]
Live regs: 000000C8 {rbx rsi rdi} => 000000E8 {rbx rbp rsi rdi}
Live vars: {V00 V01 V19} => {V00 V01 V10 V19}
Generating: N025 ( 3, 2) [000192] ------------ t192 = LCL_VAR int V19 cse0 rbx REG rbx $180
/--* t192 int
Generating: N027 (???,???) [000202] ------------ t202 = * PUTARG_REG int REG r9
IN0007: mov r9d, ebx
Generating: N029 ( 1, 1) [000005] ------------ t5 = LCL_VAR int V00 arg0 u:1 rsi REG rsi $80
/--* t5 int
Generating: N031 (???,???) [000203] ------------ t203 = * PUTARG_REG int REG rdx
IN0008: mov edx, esi
Generating: N033 ( 1, 1) [000006] ------------ t6 = LCL_VAR int V01 arg1 u:1 rdi REG rdi $81
/--* t6 int
Generating: N035 (???,???) [000204] ------------ t204 = * PUTARG_REG int REG r8
IN0009: mov r8d, edi
Generating: N037 ( 3, 10) [000009] ------------ t9 = CNS_INT(h) long 0xd1ffab1e method REG rcx $240
IN000a: mov rcx, 0xD1FFAB1E
/--* t9 long
Generating: N039 (???,???) [000205] ------------ t205 = * PUTARG_REG long REG rcx
/--* t202 int arg3 in r9
+--* t203 int arg1 in rdx
+--* t204 int arg2 in r8
+--* t205 long arg0 in rcx
Generating: N041 ( 22, 23) [000008] --CXG------- t8 = * CALL int Test2.DoTestImpl2 REG rax $148
Call: GCvars=0000000000000000 {}, gcrefRegs=00000000 {}, byrefRegs=00000000 {}
IN000b: call Test2:DoTestImpl2(int,int,ubyte):int
/--* t8 int
Generating: N043 ( 26, 26) [000015] DA-XG------- * STORE_LCL_VAR int V03 loc0 d:2 r14 REG r14
IN000c: mov r14d, eax
V03 in reg r14 is becoming live [000015]
Live regs: 000000E8 {rbx rbp rsi rdi} => 000040E8 {rbx rbp rsi rdi r14}
Live vars: {V00 V01 V10 V19} => {V00 V01 V03 V10 V19}
Generating: N045 ( 1, 1) [000018] -c---------- t18 = CNS_INT int 0 REG NA $40
Generating: N047 ( 3, 2) [000016] Dc-----N---- t16 = LCL_VAR_ADDR byref V08 loc5 d:2 NA REG NA
/--* t16 byref
+--* t18 int
Generating: N049 (???,???) [000198] -A---------- * STOREIND byte REG NA
IN000d: mov byte ptr [V08 rsp+28H], 0
Generating: N051 ( 3, 2) [000193] ------------ t193 = LCL_VAR int V19 cse0 rbx REG rbx $180
/--* t193 int
Generating: N053 (???,???) [000206] ------------ t206 = * PUTARG_REG int REG r9
IN000e: mov r9d, ebx
Generating: N055 ( 4, 5) [000020] ------------ t20 = LCL_FLD byte V08 loc5 u:2[+0] rcx (last use) REG rcx $301
IN000f: movsx rcx, byte ptr [V08 rsp+28H]
/--* t20 byte
Generating: N057 (???,???) [000207] ------------ t207 = * PUTARG_REG int REG rcx
Generating: N059 ( 1, 1) [000021] ------------ t21 = LCL_VAR int V00 arg0 u:1 rsi REG rsi $80
/--* t21 int
Generating: N061 (???,???) [000208] ------------ t208 = * PUTARG_REG int REG rdx
IN0010: mov edx, esi
Generating: N063 ( 1, 1) [000022] ------------ t22 = LCL_VAR int V01 arg1 u:1 rdi REG rdi $81
/--* t22 int
Generating: N065 (???,???) [000209] ------------ t209 = * PUTARG_REG int REG r8
IN0011: mov r8d, edi
/--* t206 int arg3 in r9
+--* t207 int arg0 in rcx
+--* t208 int arg1 in rdx
+--* t209 int arg2 in r8
Generating: N067 ( 23, 18) [000024] --CXG------- t24 = * CALL int Test2.DoTestImpl3 REG rax $14d
Call: GCvars=0000000000000000 {}, gcrefRegs=00000000 {}, byrefRegs=00000000 {}
IN0012: call Test2:DoTestImpl3(struct,int,int,ubyte):int
/--* t24 int
Generating: N069 ( 27, 21) [000029] DA-XG------- * STORE_LCL_VAR int V04 loc1 d:2 r15 REG r15
IN0013: mov r15d, eax
V04 in reg r15 is becoming live [000029]
Live regs: 000040E8 {rbx rbp rsi rdi r14} => 0000C0E8 {rbx rbp rsi rdi r14 r15}
Live vars: {V00 V01 V03 V10 V19} => {V00 V01 V03 V04 V10 V19}
Generating: N071 ( 3, 10) [000030] ------------ t30 = CNS_INT(h) long 0xd1ffab1e method REG rcx $241
IN0014: mov rcx, 0xD1FFAB1E
/--* t30 long
Generating: N073 (???,???) [000210] ------------ t210 = * PUTARG_REG long REG rcx
/--* t210 long arg0 in rcx
Generating: N075 ( 17, 16) [000031] --C--------- t31 = * CALL help ref HELPER.CORINFO_HELP_NEWSFAST REG rax $340
Call: GCvars=0000000000000000 {}, gcrefRegs=00000000 {}, byrefRegs=00000000 {}
IN0015: call CORINFO_HELP_NEWSFAST
GC regs: 00000000 {} => 00000001 {rax}
/--* t31 ref
Generating: N077 ( 17, 16) [000033] DA---------- * STORE_LCL_VAR ref V11 tmp2 d:2 rdx REG rdx
GC regs: 00000001 {rax} => 00000000 {}
IN0016: mov rdx, rax
V11 in reg rdx is becoming live [000033]
Live regs: 0000C0E8 {rbx rbp rsi rdi r14 r15} => 0000C0EC {rdx rbx rbp rsi rdi r14 r15}
Live vars: {V00 V01 V03 V04 V10 V19} => {V00 V01 V03 V04 V10 V11 V19}
GC regs: 00000000 {} => 00000004 {rdx}
Generating: N079 ( 3, 2) [000194] ------------ t194 = LCL_VAR int V19 cse0 rbx REG rbx $180
/--* t194 int
Generating: N081 (???,???) [000211] ------------ * PUTARG_STK [+0x20] void REG NA
IN0017: mov dword ptr [V09+0x20 rsp+20H], ebx
Generating: N083 ( 1, 1) [000036] ------------ t36 = LCL_VAR ref V11 tmp2 u:2 rdx (last use) REG rdx $340
/--* t36 ref
Generating: N085 (???,???) [000212] ------------ t212 = * PUTARG_REG ref REG rdx
V11 in reg rdx is becoming dead [000036]
Live regs: 0000C0EC {rdx rbx rbp rsi rdi r14 r15} => 0000C0E8 {rbx rbp rsi rdi r14 r15}
Live vars: {V00 V01 V03 V04 V10 V11 V19} => {V00 V01 V03 V04 V10 V19}
GC regs: 00000004 {rdx} => 00000000 {}
GC regs: 00000000 {} => 00000004 {rdx}
Generating: N087 ( 1, 1) [000037] ------------ t37 = LCL_VAR int V00 arg0 u:1 rsi REG rsi $80
/--* t37 int
Generating: N089 (???,???) [000213] ------------ t213 = * PUTARG_REG int REG r8
IN0018: mov r8d, esi
Generating: N091 ( 1, 1) [000038] ------------ t38 = LCL_VAR int V01 arg1 u:1 rdi REG rdi $81
/--* t38 int
Generating: N093 (???,???) [000214] ------------ t214 = * PUTARG_REG int REG r9
IN0019: mov r9d, edi
Generating: N095 ( 3, 10) [000041] ------------ t41 = CNS_INT(h) long 0xd1ffab1e method REG rcx $242
IN001a: mov rcx, 0xD1FFAB1E
/--* t41 long
Generating: N097 (???,???) [000215] ------------ t215 = * PUTARG_REG long REG rcx
/--* t212 ref arg1 in rdx
+--* t213 int arg2 in r8
+--* t214 int arg3 in r9
+--* t215 long arg0 in rcx
Generating: N099 ( 26, 24) [000040] --CXG------- t40 = * CALL int Test2.DoTestImpl4 REG rax $151
GC regs: 00000004 {rdx} => 00000000 {}
Call: GCvars=0000000000000000 {}, gcrefRegs=00000000 {}, byrefRegs=00000000 {}
IN001b: call Test2:DoTestImpl4(ref,int,int,ubyte):int
/--* t40 int
Generating: N101 ( 30, 27) [000044] DA-XG------- * STORE_LCL_VAR int V05 loc2 d:2 r12 REG r12
IN001c: mov r12d, eax
V05 in reg r12 is becoming live [000044]
Live regs: 0000C0E8 {rbx rbp rsi rdi r14 r15} => 0000D0E8 {rbx rbp rsi rdi r12 r14 r15}
Live vars: {V00 V01 V03 V04 V10 V19} => {V00 V01 V03 V04 V05 V10 V19}
Generating: N103 ( 3, 2) [000195] ------------ t195 = LCL_VAR int V19 cse0 rbx REG rbx $180
/--* t195 int
Generating: N105 (???,???) [000216] ------------ t216 = * PUTARG_REG int REG r8
IN001d: mov r8d, ebx
Generating: N107 ( 1, 1) [000045] ------------ t45 = LCL_VAR int V00 arg0 u:1 rsi REG rsi $80
/--* t45 int
Generating: N109 (???,???) [000217] ------------ t217 = * PUTARG_REG int REG rcx
IN001e: mov ecx, esi
Generating: N111 ( 1, 1) [000046] ------------ t46 = LCL_VAR int V01 arg1 u:1 rdi REG rdi $81
/--* t46 int
Generating: N113 (???,???) [000218] ------------ t218 = * PUTARG_REG int REG rdx
IN001f: mov edx, edi
/--* t216 int arg2 in r8
+--* t217 int arg0 in rcx
+--* t218 int arg1 in rdx
Generating: N115 ( 19, 12) [000048] --CXG------- t48 = * CALL int Test2.DoTestImpl5 REG rax $156
Call: GCvars=0000000000000000 {}, gcrefRegs=00000000 {}, byrefRegs=00000000 {}
IN0020: call Test2:DoTestImpl5(int,int,ubyte):int
/--* t48 int
Generating: N117 ( 23, 15) [000051] DA-XG------- * STORE_LCL_VAR int V06 loc3 d:2 rcx REG rcx
IN0021: mov ecx, eax
V06 in reg rcx is becoming live [000051]
Live regs: 0000D0E8 {rbx rbp rsi rdi r12 r14 r15} => 0000D0EA {rcx rbx rbp rsi rdi r12 r14 r15}
Live vars: {V00 V01 V03 V04 V05 V10 V19} => {V00 V01 V03 V04 V05 V06 V10 V19}
Generating: N119 ( 1, 1) [000052] ------------ t52 = LCL_VAR int V00 arg0 u:1 rsi REG rsi $80
Generating: N121 ( 1, 1) [000053] ------------ t53 = LCL_VAR int V01 arg1 u:1 rdi (last use) REG rdi $81
/--* t52 int
+--* t53 int
Generating: N123 ( 3, 3) [000140] ------------ t140 = * ADD int REG rdi $181
V01 in reg rdi is becoming dead [000053]
Live regs: 0000D0EA {rcx rbx rbp rsi rdi r12 r14 r15} => 0000D06A {rcx rbx rbp rsi r12 r14 r15}
Live vars: {V00 V01 V03 V04 V05 V06 V10 V19} => {V00 V03 V04 V05 V06 V10 V19}
IN0022: add edi, esi
/--* t140 int
Generating: N125 ( 3, 3) [000114] DA---------- * STORE_LCL_VAR int V13 tmp4 d:2 rdi REG rdi
V13 in reg rdi is becoming live [000114]
Live regs: 0000D06A {rcx rbx rbp rsi r12 r14 r15} => 0000D0EA {rcx rbx rbp rsi rdi r12 r14 r15}
Live vars: {V00 V03 V04 V05 V06 V10 V19} => {V00 V03 V04 V05 V06 V10 V13 V19}
Generating: N127 ( 1, 1) [000115] ------------ t115 = LCL_VAR int V13 tmp4 u:2 rdi (last use) REG rdi $181
Generating: N129 ( 3, 2) [000196] ------------ t196 = LCL_VAR int V19 cse0 rbx REG rbx $180
/--* t115 int
+--* t196 int
Generating: N131 ( 8, 6) [000145] ------------ t145 = * MUL int REG rdi $182
V13 in reg rdi is becoming dead [000115]
Live regs: 0000D0EA {rcx rbx rbp rsi rdi r12 r14 r15} => 0000D06A {rcx rbx rbp rsi r12 r14 r15}
Live vars: {V00 V03 V04 V05 V06 V10 V13 V19} => {V00 V03 V04 V05 V06 V10 V19}
IN0023: imul edi, ebx
/--* t145 int
Generating: N133 ( 8, 6) [000120] DA---------- * STORE_LCL_VAR int V14 tmp5 d:2 rdi REG rdi
V14 in reg rdi is becoming live [000120]
Live regs: 0000D06A {rcx rbx rbp rsi r12 r14 r15} => 0000D0EA {rcx rbx rbp rsi rdi r12 r14 r15}
Live vars: {V00 V03 V04 V05 V06 V10 V19} => {V00 V03 V04 V05 V06 V10 V14 V19}
Generating: N135 ( 1, 1) [000121] ------------ t121 = LCL_VAR int V00 arg0 u:1 rsi (last use) REG rsi $80
Generating: N137 ( 3, 2) [000197] ------------ t197 = LCL_VAR int V19 cse0 rbx (last use) REG rbx $180
/--* t121 int
+--* t197 int
Generating: N139 ( 8, 6) [000150] ------------ t150 = * MUL int REG rax $183
V00 in reg rsi is becoming dead [000121]
Live regs: 0000D0EA {rcx rbx rbp rsi rdi r12 r14 r15} => 0000D0AA {rcx rbx rbp rdi r12 r14 r15}
Live vars: {V00 V03 V04 V05 V06 V10 V14 V19} => {V03 V04 V05 V06 V10 V14 V19}
V19 in reg rbx is becoming dead [000197]
Live regs: 0000D0AA {rcx rbx rbp rdi r12 r14 r15} => 0000D0A2 {rcx rbp rdi r12 r14 r15}
Live vars: {V03 V04 V05 V06 V10 V14 V19} => {V03 V04 V05 V06 V10 V14}
IN0024: mov eax, esi
IN0025: imul eax, ebx
/--* t150 int
Generating: N141 ( 8, 6) [000131] DA---------- * STORE_LCL_VAR int V15 tmp6 d:2 rax REG rax
V15 in reg rax is becoming live [000131]
Live regs: 0000D0A2 {rcx rbp rdi r12 r14 r15} => 0000D0A3 {rax rcx rbp rdi r12 r14 r15}
Live vars: {V03 V04 V05 V06 V10 V14} => {V03 V04 V05 V06 V10 V14 V15}
Generating: N143 ( 1, 1) [000132] ------------ t132 = LCL_VAR int V15 tmp6 u:2 rax (last use) REG rax $183
Generating: N145 ( 1, 1) [000127] ------------ t127 = LCL_VAR int V14 tmp5 u:2 rdi (last use) REG rdi $182
Generating: N147 ( 1, 1) [000152] -c---------- t152 = CNS_INT int 2 REG NA $42
/--* t127 int
+--* t152 int
Generating: N149 ( 3, 3) [000153] ------------ t153 = * RSH int REG rdi $184
V14 in reg rdi is becoming dead [000127]
Live regs: 0000D0A3 {rax rcx rbp rdi r12 r14 r15} => 0000D023 {rax rcx rbp r12 r14 r15}
Live vars: {V03 V04 V05 V06 V10 V14 V15} => {V03 V04 V05 V06 V10 V15}
IN0026: sar edi, 2
/--* t132 int
+--* t153 int
Generating: N151 ( 24, 7) [000156] ---X-------- t156 = * DIV int REG rax $186
V15 in reg rax is becoming dead [000132]
Live regs: 0000D023 {rax rcx rbp r12 r14 r15} => 0000D022 {rcx rbp r12 r14 r15}
Live vars: {V03 V04 V05 V06 V10 V15} => {V03 V04 V05 V06 V10}
IN0027: cdq
IN0028: idiv edx:eax, edi
/--* t156 int
Generating: N153 ( 28, 10) [000058] DA-X-------- * STORE_LCL_VAR int V07 loc4 d:2 rax REG rax
V07 in reg rax is becoming live [000058]
Live regs: 0000D022 {rcx rbp r12 r14 r15} => 0000D023 {rax rcx rbp r12 r14 r15}
Live vars: {V03 V04 V05 V06 V10} => {V03 V04 V05 V06 V07 V10}
Generating: N155 ( 1, 1) [000012] ------------ t12 = LCL_VAR int V10 tmp1 u:2 rbp (last use) REG rbp $143
Generating: N157 ( 3, 2) [000059] ------------ t59 = LCL_VAR int V03 loc0 u:2 r14 (last use) REG r14 $148
/--* t12 int
+--* t59 int
Generating: N159 ( 5, 4) [000060] ------------ t60 = * ADD int REG rbp $187
V10 in reg rbp is becoming dead [000012]
Live regs: 0000D023 {rax rcx rbp r12 r14 r15} => 0000D003 {rax rcx r12 r14 r15}
Live vars: {V03 V04 V05 V06 V07 V10} => {V03 V04 V05 V06 V07}
V03 in reg r14 is becoming dead [000059]
Live regs: 0000D003 {rax rcx r12 r14 r15} => 00009003 {rax rcx r12 r15}
Live vars: {V03 V04 V05 V06 V07} => {V04 V05 V06 V07}
IN0029: add ebp, r14d
Generating: N161 ( 3, 2) [000061] ------------ t61 = LCL_VAR int V04 loc1 u:2 r15 (last use) REG r15 $14d
/--* t60 int
+--* t61 int
Generating: N163 ( 9, 7) [000062] ------------ t62 = * ADD int REG rbp $188
V04 in reg r15 is becoming dead [000061]
Live regs: 00009003 {rax rcx r12 r15} => 00001003 {rax rcx r12}
Live vars: {V04 V05 V06 V07} => {V05 V06 V07}
IN002a: add ebp, r15d
Generating: N165 ( 3, 2) [000063] ------------ t63 = LCL_VAR int V05 loc2 u:2 r12 (last use) REG r12 $151
/--* t62 int
+--* t63 int
Generating: N167 ( 13, 10) [000064] ------------ t64 = * ADD int REG rbp $189
V05 in reg r12 is becoming dead [000063]
Live regs: 00001003 {rax rcx r12} => 00000003 {rax rcx}
Live vars: {V05 V06 V07} => {V06 V07}
IN002b: add ebp, r12d
Generating: N169 ( 3, 2) [000065] ------------ t65 = LCL_VAR int V06 loc3 u:2 rcx (last use) REG rcx $156
/--* t64 int
+--* t65 int
Generating: N171 ( 17, 13) [000066] ------------ t66 = * ADD int REG rcx $18a
V06 in reg rcx is becoming dead [000065]
Live regs: 00000003 {rax rcx} => 00000001 {rax}
Live vars: {V06 V07} => {V07}
IN002c: add ecx, ebp
Generating: N173 ( 3, 2) [000067] ------------ t67 = LCL_VAR int V07 loc4 u:2 rax (last use) REG rax $185
/--* t66 int
+--* t67 int
Generating: N175 ( 21, 16) [000068] ------------ t68 = * ADD int REG rax $18b
V07 in reg rax is becoming dead [000067]
Live regs: 00000001 {rax} => 00000000 {}
Live vars: {V07} => {}
IN002d: add eax, ecx
/--* t68 int
Generating: N177 ( 22, 17) [000069] ------------ * RETURN int REG NA $15c
Scope info: end block BB01, IL range [000..051)
Scope info: ending scope, LVnum=0 [000..051)
Scope info: ending scope, LVnum=1 [000..051)
Scope info: ending scope, LVnum=2 [000..051)
Scope info: ending scope, LVnum=3 [000..051)
Scope info: ending scope, LVnum=4 [000..051)
Scope info: ending scope, LVnum=5 [000..051)
Scope info: ending scope, LVnum=6 [000..051)
Scope info: ending scope, LVnum=7 [000..051)
Scope info: ending scope, LVnum=8 [000..051)
Scope info: open scopes =
<none>
Added IP mapping: EPILOG STACK_EMPTY (G_M55298_IG02,ins#45,ofs#160) label
Reserving epilog IG for block BB01
G_M55298_IG02: ; offs=000000H, funclet=00, bbWeight=1
*************** After placeholder IG creation
G_M55298_IG01: ; func=00, offs=000000H, size=0000H, bbWeight=1 , gcrefRegs=00000000 {} <-- Prolog IG
G_M55298_IG02: ; offs=000000H, size=00A0H, bbWeight=1 , gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref
G_M55298_IG03: ; epilog placeholder, next placeholder=<END>, BB01 [0000], epilog, emitadd <-- First placeholder <-- Last placeholder
; PrevGCVars=0000000000000000 {}, PrevGCrefRegs=00000000 {}, PrevByrefRegs=00000000 {}
; InitGCVars=0000000000000000 {}, InitGCrefRegs=00000000 {}, InitByrefRegs=00000000 {}
Liveness not changing: 0000000000000000 {}
# compCycleEstimate = 227, compSizeEstimate = 174 Test2:DoTest(int,int,ubyte):int
; Final local variable assignments
;
; V00 arg0 [V00,T00] ( 9, 9 ) int -> rsi
; V01 arg1 [V01,T01] ( 8, 8 ) int -> rdi
; V02 arg2 [V02,T03] ( 3, 3 ) ubyte -> r8
; V03 loc0 [V03,T08] ( 2, 2 ) int -> r14
; V04 loc1 [V04,T09] ( 2, 2 ) int -> r15
; V05 loc2 [V05,T10] ( 2, 2 ) int -> r12
; V06 loc3 [V06,T11] ( 2, 2 ) int -> rcx
; V07 loc4 [V07,T12] ( 2, 2 ) int -> rax
; V08 loc5 [V08,T13] ( 2, 2 ) struct ( 8) [rsp+0x28] do-not-enreg[SF] must-init ld-addr-op
; V09 OutArgs [V09 ] ( 1, 1 ) lclBlk (40) [rsp+0x00] "OutgoingArgSpace"
; V10 tmp1 [V10,T05] ( 2, 4 ) int -> rbp "impAppendStmt"
; V11 tmp2 [V11,T04] ( 2, 4 ) ref -> rdx class-hnd exact "NewObj constructor temp"
;* V12 tmp3 [V12 ] ( 0, 0 ) struct ( 8) zero-ref do-not-enreg[SF] ld-addr-op "Inline ldloca(s) first use temp"
; V13 tmp4 [V13,T06] ( 2, 4 ) int -> rdi "impAppendStmt"
; V14 tmp5 [V14,T14] ( 2, 2 ) int -> rdi "Inline stloc first use temp"
; V15 tmp6 [V15,T07] ( 2, 4 ) int -> rax "impAppendStmt"
;* V16 tmp7 [V16 ] ( 0, 0 ) int -> zero-ref "Inlining Arg"
;* V17 tmp8 [V17 ] ( 0, 0 ) int -> zero-ref "Inlining Arg"
;* V18 tmp9 [V18 ] ( 0, 0 ) int -> zero-ref "Inlining Arg"
; V19 cse0 [V19,T02] ( 8, 8 ) int -> rbx "ValNumCSE"
;
; Lcl frame size = 48
*************** Before prolog / epilog generation
G_M55298_IG01: ; func=00, offs=000000H, size=0000H, bbWeight=1 , gcrefRegs=00000000 {} <-- Prolog IG
G_M55298_IG02: ; offs=000000H, size=00A0H, bbWeight=1 , gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref
G_M55298_IG03: ; epilog placeholder, next placeholder=<END>, BB01 [0000], epilog, emitadd <-- First placeholder <-- Last placeholder
; PrevGCVars=0000000000000000 {}, PrevGCrefRegs=00000000 {}, PrevByrefRegs=00000000 {}
; InitGCVars=0000000000000000 {}, InitGCrefRegs=00000000 {}, InitByrefRegs=00000000 {}
Recording Var Locations at start of BB01
V00(rsi) V01(rdi) V02(r8)
*************** In genFnProlog()
Added IP mapping to front: PROLOG STACK_EMPTY (G_M55298_IG01,ins#0,ofs#0) label
__prolog:
Found 2 lvMustInit int-sized stack slots, frame offsets -40 through -48
IN002e: push r15
IN002f: push r14
IN0030: push r12
IN0031: push rdi
IN0032: push rsi
IN0033: push rbp
IN0034: push rbx
IN0035: sub rsp, 48
IN0036: xor rax, rax
IN0037: mov qword ptr [V08 rsp+28H], rax
*************** In genFnPrologCalleeRegArgs() for int regs
IN0038: mov esi, ecx
IN0039: mov edi, edx
*************** In genEnregisterIncomingStackArgs()
G_M55298_IG01: ; offs=000000H, funclet=00, bbWeight=1
*************** In genFnEpilog()
__epilog:
gcVarPtrSetCur=0000000000000000 {}, gcRegGCrefSetCur=00000000 {}, gcRegByrefSetCur=00000000 {}
IN003a: add rsp, 48
IN003b: pop rbx
IN003c: pop rbp
IN003d: pop rsi
IN003e: pop rdi
IN003f: pop r12
IN0040: pop r14
IN0041: pop r15
IN0042: ret
G_M55298_IG03: ; offs=0000A0H, funclet=00, bbWeight=1
0 prologs, 1 epilogs, 0 funclet prologs, 0 funclet epilogs
*************** After prolog / epilog generation
G_M55298_IG01: ; func=00, offs=000000H, size=0019H, bbWeight=1 , gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref, nogc <-- Prolog IG
G_M55298_IG02: ; offs=000019H, size=00A0H, bbWeight=1 , gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref
G_M55298_IG03: ; offs=0000B9H, size=000FH, bbWeight=1 , epilog, nogc, emitadd
*************** In emitJumpDistBind()
Hot code size = 0xC8 bytes
Cold code size = 0x0 bytes
reserveUnwindInfo(isFunclet=FALSE, isColdCode=FALSE, unwindSize=0x14)
*************** In emitEndCodeGen()
Converting emitMaxStackDepth from bytes (0) to elements (0)
***************************************************************************
Instructions as they come out of the scheduler
G_M55298_IG01: ; func=00, offs=000000H, size=0019H, bbWeight=1 , gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref, nogc <-- Prolog IG
IN002e: 000000 push r15
IN002f: 000002 push r14
IN0030: 000004 push r12
IN0031: 000006 push rdi
IN0032: 000007 push rsi
IN0033: 000008 push rbp
IN0034: 000009 push rbx
IN0035: 00000A sub rsp, 48
IN0036: 00000E xor rax, rax
IN0037: 000010 mov qword ptr [rsp+28H], rax
IN0038: 000015 mov esi, ecx
IN0039: 000017 mov edi, edx
G_M55298_IG02: ; func=00, offs=000019H, size=00A0H, bbWeight=1 , gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref
IN0001: 000019 movzx rbx, r8b
IN0002: 00001D mov r8d, ebx
IN0003: 000020 mov ecx, esi
IN0004: 000022 mov edx, edi
[D1FFAB1E] ptr arg pop 0
IN0005: 000024 call Test2:DoTestImpl1(int,int,ubyte):int
IN0006: 000029 mov ebp, eax
IN0007: 00002B mov r9d, ebx
IN0008: 00002E mov edx, esi
IN0009: 000030 mov r8d, edi
IN000a: 000033 mov rcx, 0xD1FFAB1E
[D1FFAB1E] ptr arg pop 0
IN000b: 00003D call Test2:DoTestImpl2(int,int,ubyte):int
IN000c: 000042 mov r14d, eax
IN000d: 000045 mov byte ptr [rsp+28H], 0
IN000e: 00004A mov r9d, ebx
IN000f: 00004D movsx rcx, byte ptr [rsp+28H]
IN0010: 000053 mov edx, esi
IN0011: 000055 mov r8d, edi
[D1FFAB1E] ptr arg pop 0
IN0012: 000058 call Test2:DoTestImpl3(struct,int,int,ubyte):int
IN0013: 00005D mov r15d, eax
IN0014: 000060 mov rcx, 0xD1FFAB1E
New gcrReg live regs=00000001 {rax}
gcrReg +[rax]
[D1FFAB1E] ptr arg pop 0
IN0015: 00006A call CORINFO_HELP_NEWSFAST
gcrReg +[rdx]
IN0016: 00006F mov rdx, rax
IN0017: 000072 mov dword ptr [rsp+20H], ebx
IN0018: 000076 mov r8d, esi
IN0019: 000079 mov r9d, edi
IN001a: 00007C mov rcx, 0xD1FFAB1E
New gcrReg live regs=00000000 {}
gcrReg -[rax]
gcrReg -[rdx]
[D1FFAB1E] ptr arg pop 0
IN001b: 000086 call Test2:DoTestImpl4(ref,int,int,ubyte):int
IN001c: 00008B mov r12d, eax
IN001d: 00008E mov r8d, ebx
IN001e: 000091 mov ecx, esi
IN001f: 000093 mov edx, edi
[D1FFAB1E] ptr arg pop 0
IN0020: 000095 call Test2:DoTestImpl5(int,int,ubyte):int
IN0021: 00009A mov ecx, eax
IN0022: 00009C add edi, esi
IN0023: 00009E imul edi, ebx
IN0024: 0000A1 mov eax, esi
IN0025: 0000A3 imul eax, ebx
IN0026: 0000A6 sar edi, 2
IN0027: 0000A9 cdq
IN0028: 0000AA idiv edx:eax, edi
IN0029: 0000AC add ebp, r14d
IN002a: 0000AF add ebp, r15d
IN002b: 0000B2 add ebp, r12d
IN002c: 0000B5 add ecx, ebp
IN002d: 0000B7 add eax, ecx
G_M55298_IG03: ; func=00, offs=0000B9H, size=000FH, bbWeight=1 , epilog, nogc, emitadd
IN003a: 0000B9 add rsp, 48
IN003b: 0000BD pop rbx
IN003c: 0000BE pop rbp
IN003d: 0000BF pop rsi
IN003e: 0000C0 pop rdi
IN003f: 0000C1 pop r12
IN0040: 0000C3 pop r14
IN0041: 0000C5 pop r15
IN0042: 0000C7 ret
Allocated method code size = 200 , actual size = 200
; Total bytes of code 200, prolog size 21, perf score 83.50, (MethodHash=8bafdb7c) for method Test2:DoTest(int,int,ubyte):int
; ============================================================
*************** After end code gen, before unwindEmit()
G_M55298_IG01: ; func=00, offs=000000H, size=0019H, bbWeight=1 , gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref, nogc <-- Prolog IG
IN002e: 000000 push r15
IN002f: 000002 push r14
IN0030: 000004 push r12
IN0031: 000006 push rdi
IN0032: 000007 push rsi
IN0033: 000008 push rbp
IN0034: 000009 push rbx
IN0035: 00000A sub rsp, 48
IN0036: 00000E xor rax, rax
IN0037: 000010 mov qword ptr [V08 rsp+28H], rax
IN0038: 000015 mov esi, ecx
IN0039: 000017 mov edi, edx
G_M55298_IG02: ; offs=000019H, size=00A0H, bbWeight=1 , gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref
IN0001: 000019 movzx rbx, r8b
IN0002: 00001D mov r8d, ebx
IN0003: 000020 mov ecx, esi
IN0004: 000022 mov edx, edi
IN0005: 000024 call Test2:DoTestImpl1(int,int,ubyte):int
IN0006: 000029 mov ebp, eax
IN0007: 00002B mov r9d, ebx
IN0008: 00002E mov edx, esi
IN0009: 000030 mov r8d, edi
IN000a: 000033 mov rcx, 0xD1FFAB1E
IN000b: 00003D call Test2:DoTestImpl2(int,int,ubyte):int
IN000c: 000042 mov r14d, eax
IN000d: 000045 mov byte ptr [V08 rsp+28H], 0
IN000e: 00004A mov r9d, ebx
IN000f: 00004D movsx rcx, byte ptr [V08 rsp+28H]
IN0010: 000053 mov edx, esi
IN0011: 000055 mov r8d, edi
IN0012: 000058 call Test2:DoTestImpl3(struct,int,int,ubyte):int
IN0013: 00005D mov r15d, eax
IN0014: 000060 mov rcx, 0xD1FFAB1E
IN0015: 00006A call CORINFO_HELP_NEWSFAST
IN0016: 00006F mov rdx, rax
IN0017: 000072 mov dword ptr [V09+0x20 rsp+20H], ebx
IN0018: 000076 mov r8d, esi
IN0019: 000079 mov r9d, edi
IN001a: 00007C mov rcx, 0xD1FFAB1E
IN001b: 000086 call Test2:DoTestImpl4(ref,int,int,ubyte):int
IN001c: 00008B mov r12d, eax
IN001d: 00008E mov r8d, ebx
IN001e: 000091 mov ecx, esi
IN001f: 000093 mov edx, edi
IN0020: 000095 call Test2:DoTestImpl5(int,int,ubyte):int
IN0021: 00009A mov ecx, eax
IN0022: 00009C add edi, esi
IN0023: 00009E imul edi, ebx
IN0024: 0000A1 mov eax, esi
IN0025: 0000A3 imul eax, ebx
IN0026: 0000A6 sar edi, 2
IN0027: 0000A9 cdq
IN0028: 0000AA idiv edx:eax, edi
IN0029: 0000AC add ebp, r14d
IN002a: 0000AF add ebp, r15d
IN002b: 0000B2 add ebp, r12d
IN002c: 0000B5 add ecx, ebp
IN002d: 0000B7 add eax, ecx
G_M55298_IG03: ; offs=0000B9H, size=000FH, bbWeight=1 , epilog, nogc, emitadd
IN003a: 0000B9 add rsp, 48
IN003b: 0000BD pop rbx
IN003c: 0000BE pop rbp
IN003d: 0000BF pop rsi
IN003e: 0000C0 pop rdi
IN003f: 0000C1 pop r12
IN0040: 0000C3 pop r14
IN0041: 0000C5 pop r15
IN0042: 0000C7 ret
Unwind Info:
>> Start offset : 0x000000 (not in unwind data)
>> End offset : 0xd1ffab1e (not in unwind data)
Version : 1
Flags : 0x00
SizeOfProlog : 0x0E
CountOfUnwindCodes: 8
FrameRegister : none (0)
FrameOffset : N/A (no FrameRegister) (Value=0)
UnwindCodes :
CodeOffset: 0x0E UnwindOp: UWOP_ALLOC_SMALL (2) OpInfo: 5 * 8 + 8 = 48 = 0x30
CodeOffset: 0x0A UnwindOp: UWOP_PUSH_NONVOL (0) OpInfo: rbx (3)
CodeOffset: 0x09 UnwindOp: UWOP_PUSH_NONVOL (0) OpInfo: rbp (5)
CodeOffset: 0x08 UnwindOp: UWOP_PUSH_NONVOL (0) OpInfo: rsi (6)
CodeOffset: 0x07 UnwindOp: UWOP_PUSH_NONVOL (0) OpInfo: rdi (7)
CodeOffset: 0x06 UnwindOp: UWOP_PUSH_NONVOL (0) OpInfo: r12 (12)
CodeOffset: 0x04 UnwindOp: UWOP_PUSH_NONVOL (0) OpInfo: r14 (14)
CodeOffset: 0x02 UnwindOp: UWOP_PUSH_NONVOL (0) OpInfo: r15 (15)
allocUnwindInfo(pHotCode=0x00000000D1FFAB1E, pColdCode=0x0000000000000000, startOffset=0x0, endOffset=0xc8, unwindSize=0x14, pUnwindBlock=0x00000000D1FFAB1E, funKind=0 (main function))
*************** In genIPmappingGen()
IP mapping count : 2
IL offs PROLOG : 0x00000000 ( STACK_EMPTY )
IL offs EPILOG : 0x000000B9 ( STACK_EMPTY )
*************** In genSetScopeInfo()
VarLocInfo count is 5
*************** Variable debug info
5 live ranges
0( UNKNOWN) : From 00000000h to 00000019h, in rcx
1( UNKNOWN) : From 00000000h to 00000019h, in rdx
2( UNKNOWN) : From 00000000h to 00000019h, in r8
1( UNKNOWN) : From 00000019h to 0000009Ch, in rdi
0( UNKNOWN) : From 00000019h to 000000A1h, in rsi
*************** In gcInfoBlockHdrSave()
Set code length to 200.
Set ReturnKind to Scalar.
Set Outgoing stack arg area size to 40.
Defining 6 call sites:
Offset 0x24, size 5.
Offset 0x3d, size 5.
Offset 0x58, size 5.
Offset 0x6a, size 5.
Offset 0x86, size 5.
Offset 0x95, size 5.
Method code size: 200
Allocations for Test2:DoTest(int,int,ubyte):int (MethodHash=8bafdb7c)
count: 2100, size: 167134, max = 3360
allocateMemory: 196608, nraUsed: 172912
Alloc'd bytes by kind:
kind | size | pct
---------------------+------------+--------
AssertionProp | 6460 | 3.87%
ASTNode | 31624 | 18.92%
InstDesc | 6048 | 3.62%
ImpStack | 384 | 0.23%
BasicBlock | 6040 | 3.61%
fgArgInfo | 1120 | 0.67%
fgArgInfoPtrArr | 256 | 0.15%
FlowList | 0 | 0.00%
TreeStatementList | 224 | 0.13%
SiScope | 528 | 0.32%
DominatorMemory | 48 | 0.03%
LSRA | 3224 | 1.93%
LSRA_Interval | 4752 | 2.84%
LSRA_RefPosition | 15104 | 9.04%
Reachability | 16 | 0.01%
SSA | 1488 | 0.89%
ValueNumber | 10346 | 6.19%
LvaTable | 5676 | 3.40%
UnwindInfo | 0 | 0.00%
hashBv | 128 | 0.08%
bitset | 408 | 0.24%
FixedBitVect | 164 | 0.10%
Generic | 4162 | 2.49%
LocalAddressVisitor | 0 | 0.00%
FieldSeqStore | 0 | 0.00%
ZeroOffsetFieldMap | 640 | 0.38%
ArrayInfoMap | 40 | 0.02%
MemoryPhiArg | 0 | 0.00%
CSE | 2096 | 1.25%
GC | 1598 | 0.96%
CorSig | 1872 | 1.12%
Inlining | 12160 | 7.28%
ArrayStack | 0 | 0.00%
DebugInfo | 512 | 0.31%
DebugOnly | 45543 | 27.25%
Codegen | 1128 | 0.67%
LoopOpt | 0 | 0.00%
LoopHoist | 0 | 0.00%
Unknown | 1289 | 0.77%
RangeCheck | 0 | 0.00%
CopyProp | 1984 | 1.19%
SideEffects | 0 | 0.00%
ObjectAllocator | 0 | 0.00%
VariableLiveRanges | 0 | 0.00%
ClassLayout | 72 | 0.04%
****** DONE compiling Test2:DoTest(int,int,ubyte):int
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