tb_led01.v

module tb_led01;
	reg	clk;
	reg	res;
	wire	led0;
	wire	led1;
	wire	led2;
	wire	led3;
	
	led01 led01(
		.clk(clk),
		.res(res),
		.led0(led0),
		.led1(led1),
		.led2(led2),
		.led3(led3)
		);
		
	always #10 clk = ~clk;
	
	initial begin
	
		#0 res = 1;
			clk = 0;
		
		#40 res = 0;
	
	end
	
endmodule