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module led01(
clk,
res,
led0,
led1,
led2,
led3);
input clk;
input res;
output reg led0;
output reg led1;
output reg led2;
output reg led3;
reg [11:0] count12bit;
reg [11:0] countlimit;
reg [3:0] led_reg;
//Clock delay
always @(posedge clk) begin
if (res == 1) begin
count12bit <= 0;
led_reg <= 0;
end
//Clock delay counter
if (res == 0) begin
if (count12bit == countlimit) begin
count12bit <= 0;
led0 <= led_reg[0];
led1 <= led_reg[1];
led2 <= led_reg[2];
led3 <= led_reg[3];
if (led_reg == 4'b1111) begin
led_reg <= 0;
end
led_reg <= led_reg + 1;
end
else begin
count12bit <= count12bit + 1;
end
end
end
initial begin
//Clock delay debug
countlimit <= 12'b000000000001;
//Clock delay Production
//countlimit = 12'b001111111111;
end
endmodule
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