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September 21, 2023 21:21
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import numpy as np | |
import pandas as pd | |
from matplotlib import pyplot as plt | |
import os | |
if not os.getenv("LAB_PATH"): | |
print("Set Lab Path\n") | |
exit(1) | |
datadir = os.getenv("LAB_PATH") + '/results/X86/run_micro' | |
def gem5GetStat(filename, stat): | |
filename = os.path.join(datadir, '', filename, 'stats.txt').replace('\\','/') | |
with open(filename) as f: | |
r = f.read() | |
if len(r) < 10: return 0.0 | |
if (r.find(stat) != -1) : | |
start = r.find(stat) + len(stat) + 1 | |
end = r.find('#', start) | |
print(r[start:end]) | |
return float(r[start:end]) | |
else: | |
return float(0.0) | |
all_arch = ['X86'] | |
plt_arch = ['X86'] | |
all_memory_models = ['SingleCycle', 'Inf', 'Slow'] | |
plt_memory_models = ['SingleCycle', 'Slow'] | |
all_gem5_cpus = ['Simple','DefaultO3','Minor4', 'O3_W2K', 'O3_W256'] | |
plt_gem5_cpus = ['Simple'] | |
benchmarks = ['CCa', 'CCl', 'DP1f', 'ED1', 'EI', 'MI'] | |
if len(plt_memory_models) > 1 and len(plt_gem5_cpus) > 1: | |
print("Cannot vary both CPU models and memory models") | |
exit(0) | |
rows = [] | |
for bm in benchmarks: | |
for cpu in plt_gem5_cpus: | |
for mem in plt_memory_models: | |
rows.append([bm,cpu,mem, | |
gem5GetStat(datadir+"/"+bm+"/"+cpu+"/"+mem, 'system.cpu.numCycles'), | |
gem5GetStat(datadir+"/"+bm+"/"+cpu+"/"+mem, 'sim_insts'), | |
gem5GetStat(datadir+"/"+bm+"/"+cpu+"/"+mem, 'sim_ops'), | |
gem5GetStat(datadir+"/"+bm+"/"+cpu+"/"+mem, 'sim_ticks')/1e9, | |
gem5GetStat(datadir+"/"+bm+"/"+cpu+"/"+mem, 'host_op_rate'), | |
gem5GetStat(datadir+"/"+bm+"/"+cpu+"/"+mem,'system.mem_ctrl.dram.avgMemAccLat'), | |
gem5GetStat(datadir+"/"+bm+"/"+cpu+"/"+mem,'system.mem_ctrl.dram.busUtil'), | |
gem5GetStat(datadir+"/"+bm+"/"+cpu+"/"+mem,'system.mem_ctrl.dram.bw_total::total'), | |
gem5GetStat(datadir+"/"+bm+"/"+cpu+"/"+mem,'system.mem_ctrl.dram.totBusLat'), | |
# memory with store | |
gem5GetStat(datadir+"/"+bm+"/"+cpu+"/"+mem,'system.mem_ctrl.dram.avgWrBW') | |
]) | |
df = pd.DataFrame(rows, columns=['benchmark','cpu', 'mem', 'cycles','instructions', 'Ops', 'Ticks','Host', 'avgmemaccesslatency','busutilit','bandwidthtotal','totalbuslatency', 'averagewritebandwidth']) | |
df['ipc'] = df['instructions']/df['cycles'] | |
df['cpi']= 1/df['ipc'] | |
print(df) | |
def draw_vertical_line(ax, xpos, ypos): | |
line = plt.Line2D([xpos, xpos], [ypos + .1, ypos], | |
transform=ax.transAxes, color='black', lw = 1) | |
line.set_clip_on(False) | |
ax.add_line(line) | |
def doplot_benchmarks(benchmarks,stat,norm=True): | |
fig = plt.figure() | |
ax = fig.add_subplot(1,1,1) | |
i = 0 | |
for bm in benchmarks: | |
base = df[(df['benchmark']==bm)][stat].iloc[0] if norm else 1 | |
models = plt_gem5_cpus if len(plt_memory_models) == 1 else plt_memory_models | |
for j,sys in enumerate(models): | |
if len(plt_memory_models) > 1: | |
d = df[(df['mem']==sys) & (df['benchmark']==bm)] | |
else: | |
d = df[(df['cpu']==sys) & (df['benchmark']==bm)] | |
print(d) | |
ax.bar(i, d[stat].iloc[0]/base, color='C'+str(j)) | |
i += 1 | |
i += 1 | |
for i,sys in enumerate(models): | |
plt.bar(0,0,color='C'+str(i), label=sys) | |
new_names = benchmarks | |
# Arranging ticks on the X axis | |
plt.xticks(np.arange(len(new_names))*(len(models)+1)+i/2, new_names, rotation=40, ha='right') | |
fig_size = plt.rcParams["figure.figsize"] | |
fig_size[0] = 10 | |
fig_size[1] = 5 | |
plt.rcParams["figure.figsize"] = fig_size | |
fig1 = doplot_benchmarks(benchmarks,"ipc",norm=False) | |
plt.ylabel('') | |
plt.legend(loc=2, prop={'size': 8}) | |
plt.title('1C vs Slow') | |
plt.tight_layout() | |
plt.savefig('1C_vs_Slow.png', format='png', dpi=600) |
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