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@iamgreaser
Created June 7, 2016 03:51
NIR (final form) for fragment shader:
shader: MESA_SHADER_FRAGMENT
name: GLSL7
inputs: 4
outputs: 4
uniforms: 0
shared: 0
decl_var shader_in INTERP_QUALIFIER_NONE vec4 VertexColor (VARYING_SLOT_VAR0, 0)
decl_var shader_out INTERP_QUALIFIER_NONE vec4 dp_FragColor (FRAG_RESULT_DATA0, 0)
decl_function main returning void
impl main {
block block_0:
/* preds: */
vec1 32 ssa_0 = load_const (0x00000000 /* 0.000000 */)
vec4 32 ssa_1 = intrinsic load_input (ssa_0) () (0) /* base=0 */ /* VertexColor */
intrinsic store_output (ssa_1, ssa_0) () (0, 15) /* base=0 */ /* wrmask=xyzw */ /* dp_FragColor */
/* succs: block_0 */
block block_0:
}
Native code for unnamed fragment shader GLSL7
SIMD8 shader: 5 instructions. 0 loops. 24 cycles. 0:0 spills:fills. Promoted 0 constants. Compacted 80 to 48 bytes (40%)
START B0
pln(8) m1<1>F g4<0,1,0>F g2<8,8,1>F { align1 1Q compacted };
pln(8) m2<1>F g4.4<0,1,0>F g2<8,8,1>F { align1 1Q compacted };
pln(8) m3<1>F g5<0,1,0>F g2<8,8,1>F { align1 1Q compacted };
pln(8) m4<1>F g5.4<0,1,0>F g2<8,8,1>F { align1 1Q compacted };
sendc(8) null<1>UW m1<8,8,1>F
render RT write SIMD8 LastRT Surface = 0 mlen 4 rlen 0 { align1 1Q EOT };
END B0
Native code for unnamed fragment shader GLSL7
SIMD16 shader: 5 instructions. 0 loops. 34 cycles. 0:0 spills:fills. Promoted 0 constants. Compacted 80 to 48 bytes (40%)
START B0
pln(16) m1<1>F g6<0,1,0>F g2<8,8,1>F { align1 1H compacted };
pln(16) m3<1>F g6.4<0,1,0>F g2<8,8,1>F { align1 1H compacted };
pln(16) m5<1>F g7<0,1,0>F g2<8,8,1>F { align1 1H compacted };
pln(16) m7<1>F g7.4<0,1,0>F g2<8,8,1>F { align1 1H compacted };
sendc(16) null<1>UW m1<8,8,1>F
render RT write SIMD16 LastRT Surface = 0 mlen 8 rlen 0 { align1 1H EOT };
END B0
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