blink.pcf

LOCATE COMP "CLK" SITE "A9";
IOBUF PORT "CLK" IO_TYPE=LVCMOS33;

LOCATE COMP "LED1" SITE "K4";
LOCATE COMP "LED2" SITE "M3";
LOCATE COMP "LED3" SITE "J3";

IOBUF PORT "LED1" IO_TYPE=LVCMOS33;
IOBUF PORT "LED2" IO_TYPE=LVCMOS33;
IOBUF PORT "LED3" IO_TYPE=LVCMOS33;



LOCATE COMP "LED4" SITE "L4";
IOBUF PORT "LED4" IO_TYPE=LVCMOS33;

blink.py

# Blink the three LEDs in a counting pattern.

from nmigen import Elaboratable, Signal, Module
from nmigen.build import Platform, Resource, Pins, Attrs
from nmigen_boards.orangecrab_r0_2 import OrangeCrabR0_2Platform


class Blink(Elaboratable):
    def __init__(self):
        self.count = Signal(32, reset=0)

    def elaborate(self, platform: Platform):
        m = Module()

        m.d.sync += self.count.eq(self.count + 1)
        rgb = platform.request('rgb_led', 0)
        red_led = rgb.r
        green_led = rgb.g
        blue_led = rgb.b
        extra_red = platform.request('extra_led', 0)

        m.d.comb += [
            red_led.o.eq(self.count[27]),
            green_led.o.eq(self.count[26]),
            blue_led.o.eq(self.count[25]),
            extra_red.o.eq(self.count[27]),
        ]

        return m



if __name__ == "__main__":
    platform = OrangeCrabR0_2Platform()
    platform.add_resources([
        Resource('extra_led', 0,
                 Pins("0", conn=("io", 0), dir="o"), Attrs(IO_TYPE="LVCMOS33"))
    ])
    platform.build(Blink(), do_program=True)

blink.v

/* Copyright 2020 Gregory Davill <greg.davill@gmail.com> */

/*
 *  Blink a LED on the OrangeCrab using verilog
 */

module top (
    input CLK,

	output LED1,
	output LED2,
	output LED3,
	output LED4
);
    reg [30:0] counter = 0;

	always @(posedge CLK) begin
		counter <= counter + 1;
	end

	assign LED1 = ~counter[26];
    assign LED2 = ~counter[27];
    assign LED3 = ~counter[28];
    assign LED4 = ~counter[29];
    

endmodule