Comportamental Type D FlipFlop (verilog)

TypeDFF

module foo
(
  input In,
  input Reset,
  input Clock,
  input Set,
  output reg D);

always @(posedge CLK)
begin
  if(!Reset)
    D <= 0;
  else if(Set)
    D <= 1;
  else
    D <= In;
end

endmodule