SECCON 2015 の Reverse Engineering Hardware 1 の回路を再現した

reverse_engineering_hardware_1.v

module blackbox(
	CLRn,
	CLK,
	DA,
	DB,
	X,
	LED );

	input	wire			CLRn;
	input	wire			CLK;
	input	wire			DA;
	input	wire			DB;
	output	wire	[5:0]	X;
	output	wire	[10:0]	LED;

	reg		QA;
	reg		QB;
	wire	QAn	= ~QA;
	wire	QBn	= ~QB;

	// 74HC74
	always @( posedge CLK or negedge CLRn ) begin
		if ( ~CLRn ) begin
			QA	<= 1'd0;
			QB	<= 1'd0;
		end else begin
			QA	<= DA;
			QB	<= DB;
		end
	end

	// ブレッドボードの上の方にある7つのdiode-transistor-logic
	wire	NOR[6:0];
	assign	NOR[0]	= ~( DA | QBn );		// 上段の一番左
	assign	NOR[1]	= ~( NOR[0] | QAn );
	assign	NOR[2]	= ~( DB | QB );
	assign	NOR[3]	= ~( QAn | QBn );
	assign	NOR[4]	= ~( NOR[3] | QAn );
	assign	NOR[5]	= ~( NOR[3] | QBn );	// 上段の一番右
	assign	NOR[6]	= ~( NOR[4] | NOR[5] );	// 一番右の下

	// ブレッドボードの上の方にある7つのLED
	assign	LED[0]		= ~NOR[0];	// 左側
	assign	LED[1]		= ~NOR[1];
	assign	LED[2]		= ~NOR[2];
	assign	LED[3]		= ~NOR[3];
	assign	LED[4]		= ~NOR[4];
	assign	LED[5]		= ~NOR[5];	// 右側
	assign	LED[6]		= ~NOR[6];	// その下

	// ブレッドボード左下の4つのLED
	assign	LED[7]		= DA;	// 一番左
	assign	LED[8]		= QA;
	assign	LED[9]		= DB;
	assign	LED[10]		= QB;	// 一番右

	// X6 - X1
	assign	X[5:0]		= {NOR[6],NOR[2],NOR[1],NOR[0],QB,QA};

endmodule



module main;

	reg				CLRn;
	reg				CLK;
	reg				DA;
	reg				DB;
	wire	[5:0]	X;
	wire	[10:0]	LED;

	blackbox blackbox_inst(
		.CLRn	(CLRn	),
		.CLK	(CLK	),
		.DA		(DA		),
		.DB		(DB		),
		.X		(X		),
		.LED	(LED	)
	);

	wire	[6:0]	ASCII;
	assign	ASCII[6:0]	= {1'd0,X[0],X[1],X[2],X[3],X[4],X[5]} + 7'd32;

	reg		[3:0]	i;
	reg		[6:0]	C;
	reg		[255:0]	STR;
	initial begin

		// 動画の再現
		CLK		= 1'd0;
		DA		= 1'd0;
		DB		= 1'd0;
		CLRn	= 1'd0;
		#1;
		CLRn	= 1'd1;
		DA		= 1'd0;
		DB		= 1'd1;
		#1;
		CLK 	= 1'd1;
		#1;
		CLK 	= 1'd0;
		DA		= 1'd1;
		DB		= 1'd1;
		#1;
		CLK 	= 1'd1;
		#1;
		CLK 	= 1'd0;
		DA		= 1'd0;
		DB		= 1'd0;
		#1;
		CLK 	= 1'd1;
		#1;

		// 問題の動作
		CLK		= 1'd0;
		DA		= 1'd0;
		DB		= 1'd0;
		CLRn	= 1'd0;
		C		= "@";
		#1;
		CLRn	= 1'd1;
		#1;
		STR = 0;

		for ( i = 4'd0 ; i < 4'd10 ; i = i + 4'd1 ) begin
			if ( C == "Y" ) begin
				DA = 1'd0;
				DB = 1'd1;
			end else begin
				DA = i[0];
				DB = i[1];
			end
			#1;
			C	= ASCII;
			STR = ( STR << 8 ) + C;
			#1;
			CLK	= 1'd1;
			#1;
			CLK	= 1'd0;
			#1;
			STR = ( STR << 8 ) + ASCII;
			#1;
		end

		$finish;
	end

	initial begin
		$dumpfile( "out.vcd" );
		$dumpvars( 0 , main );
	end

endmodule