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@ikwzm
Created April 27, 2013 07:40
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module gen_table_top (
input wire clk,
input wire [8:0] neigbors,
output reg result
);
reg [511:0] is_live_table;
reg [8:0] neigbors_r;
wire wdata;
function is_live;
input [8:0] n;
integer cnt;
begin
cnt = n[0] + n[1] + n[2] +n[3] +n[5] +n[6] +n[7] +n[8];
if (n[4] == 1)
is_live = (cnt == 2) || (cnt == 3);
else
is_live = (cnt == 3);
end
endfunction // is_live
initial begin :gen_is_live_table
integer i;
for (i = 0 ; i < 512 ; i = i+1)
is_live_table[i] = is_live(i);
end
assign wdata = is_live_table[neigbors_r];
always @(posedge clk) begin
neigbors_r <= neigbors;
result <= wdata;
end
endmodule
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