VHDL の２次元配列のサンプル

vec2.vhd

library ieee;
use     ieee.std_logic_1164.all;
package TYPES is
    constant WORD_BITS   :  integer := 8;
    subtype  WORD_TYPE   is std_logic_vector(WORD_BITS-1 downto 0);
    type     WORD_WINDOW is array(integer range <>, integer range <>) of WORD_TYPE;
end TYPES;
library ieee;
use     ieee.std_logic_1164.all;
use     ieee.numeric_std.all;
use     WORK.TYPES.all;
entity  VEC2 is
    port (
        A : in  WORD_WINDOW(0 to 3, 0 to 3);
        B : in  WORD_WINDOW(0 to 3, 0 to 3);
        O : out WORD_WINDOW(0 to 3, 0 to 3)
    );
end VEC2;
architecture RTL of VEC2 is
begin
    process(A,B) begin
        for x in 0 to 3 loop
            for y in 0 to 3 loop
                O(x,y) <= std_logic_vector(unsigned(A(x,y)) + unsigned(B(x,y)));
            end loop;
        end loop;
    end process;
end RTL;