フィボナッチをVHDLで書いてみた

fib.vhd

library ieee;
use     ieee.std_logic_1164.all;
use     ieee.numeric_std.all;
entity  FIB is
    port (
        CLK    : in  std_logic;
        RST    : in  std_logic;
        GO     : in  std_logic;
        N      : in  std_logic_vector( 7 downto 0);
        BUSY   : out std_logic;
        DONE   : out std_logic;
        O      : out std_logic_vector(31 downto 0)
    );
end     FIB;
architecture RTL of FIB is
    signal    curr_count  :  unsigned(N'length-1 downto 0);
    signal    last_count  :  unsigned(N'length-1 downto 0);
    signal    curr_value  :  unsigned(O'length-1 downto 0);
    signal    prev_value  :  unsigned(O'length-1 downto 0);
    signal    run         :  boolean;
begin
    process (CLK, RST) begin
        if (RST = '1') then
            run        <= FALSE;
            curr_count <= (others => '0');
            last_count <= (others => '0');
            curr_value <= (others => '0');
            prev_value <= (others => '0');
        elsif (CLK'event and CLK = '1') then
            if (run = FALSE) then
                if (GO = '1') then
                    run <= TRUE;
                    last_count <= unsigned(N);
                    curr_count <= to_unsigned(1, curr_count'length);
                    prev_value <= to_unsigned(0, curr_value'length);
                    if (unsigned(N) > 0) then
                        curr_value <= to_unsigned(1, curr_value'length);
                    else
                        curr_value <= to_unsigned(0, curr_value'length);
                    end if;
                end if;
            else
                if (curr_count < last_count) then
                    curr_count <= curr_count + 1;
                else
                    run <= FALSE;
                end if;
                prev_value <= curr_value;
                curr_value <= curr_value + prev_value;
            end if;
        end if;
    end process;
    BUSY <= '1' when (run = TRUE) else '0';
    DONE <= '1' when (run = TRUE and curr_count >= last_count) else '0';
    O    <= std_logic_vector(curr_value);
end RTL;

fib_tb.vhd

library ieee;
use     ieee.std_logic_1164.all;
use     ieee.numeric_std.all;
entity  FIB_TB is
end     FIB_TB;
architecture SIM of FIB_TB is
    component FIB
        port (
            CLK    : in  std_logic;
            RST    : in  std_logic;
            GO     : in  std_logic;
            N      : in  std_logic_vector( 7 downto 0);
            BUSY   : out std_logic;
            DONE   : out std_logic;
            O      : out std_logic_vector(31 downto 0)
        );
    end component;
    constant  PERIOD  :  time := 4 ns;
    signal    CLK     :  std_logic;
    signal    RST     :  std_logic;
    signal    GO      :  std_logic;
    signal    N       :  std_logic_vector( 7 downto 0);
    signal    BUSY    :  std_logic;
    signal    DONE    :  std_logic;
    signal    O       :  std_logic_vector(31 downto 0);
begin
    DUT : FIB port map (
        CLK    => CLK , 
        RST    => RST , 
        GO     => GO  , 
        N      => N   , 
        BUSY   => BUSY, 
        DONE   => DONE, 
        O      => O      
    );
    process begin
        RST <= '1';
        GO  <= '0';
        N   <= (others => '0');
        wait until (CLK'event and CLK = '1');
        wait until (CLK'event and CLK = '1');
        RST <= '0';
        wait until (CLK'event and CLK = '1');
        wait until (CLK'event and CLK = '1');
        GO  <= '1';
        N   <= std_logic_vector(to_unsigned(42, N'length));
        RUN_LOOP: loop
            wait until (CLK'event and CLK = '1');
            if (BUSY = '1') then
                GO <= '0';
            end if;
            if (DONE = '1') then
                exit RUN_LOOP;
            end if;
        end loop;
        assert (unsigned(O) = 267914296) report "Error"   severity FAILURE;
        assert (FALSE)                   report "Success" severity FAILURE;
    end process;
    process begin
        CLK <= '1'; wait for PERIOD/2;
        CLK <= '0'; wait for PERIOD/2;
    end process;
end SIM;