Skip to content

Instantly share code, notes, and snippets.

@ilebedev

ilebedev/freechips.rocketchip.system.rv64iamfd.v

Last active January 9, 2019 15:52
Show Gist options
  • Star 0 You must be signed in to star a gist
  • Fork 0 You must be signed in to fork a gist
  • Save ilebedev/91627c13847e41e22977c7f233774c2d to your computer and use it in GitHub Desktop.
Save ilebedev/91627c13847e41e22977c7f233774c2d to your computer and use it in GitHub Desktop.
Download ZIP
freechips.rocketchip.system.DefaultConfig.v
Raw
freechips.rocketchip.system.rv64iamfd.v
module ExampleRocketSystem( // @[:freechips.rocketchip.system.DefaultConfig.fir@214349.2]
input clock, // @[:freechips.rocketchip.system.DefaultConfig.fir@214350.4]
input reset, // @[:freechips.rocketchip.system.DefaultConfig.fir@214351.4]
output debug_clockeddmi_dmi_req_ready, // @[:freechips.rocketchip.system.DefaultConfig.fir@214353.4]
input debug_clockeddmi_dmi_req_valid, // @[:freechips.rocketchip.system.DefaultConfig.fir@214353.4]
input [6:0] debug_clockeddmi_dmi_req_bits_addr, // @[:freechips.rocketchip.system.DefaultConfig.fir@214353.4]
input [31:0] debug_clockeddmi_dmi_req_bits_data, // @[:freechips.rocketchip.system.DefaultConfig.fir@214353.4]
input [1:0] debug_clockeddmi_dmi_req_bits_op, // @[:freechips.rocketchip.system.DefaultConfig.fir@214353.4]
input debug_clockeddmi_dmi_resp_ready, // @[:freechips.rocketchip.system.DefaultConfig.fir@214353.4]
output debug_clockeddmi_dmi_resp_valid, // @[:freechips.rocketchip.system.DefaultConfig.fir@214353.4]
output [31:0] debug_clockeddmi_dmi_resp_bits_data, // @[:freechips.rocketchip.system.DefaultConfig.fir@214353.4]
output [1:0] debug_clockeddmi_dmi_resp_bits_resp, // @[:freechips.rocketchip.system.DefaultConfig.fir@214353.4]
input debug_clockeddmi_dmiClock, // @[:freechips.rocketchip.system.DefaultConfig.fir@214353.4]
input debug_clockeddmi_dmiReset, // @[:freechips.rocketchip.system.DefaultConfig.fir@214353.4]
output debug_ndreset, // @[:freechips.rocketchip.system.DefaultConfig.fir@214353.4]
output debug_dmactive, // @[:freechips.rocketchip.system.DefaultConfig.fir@214353.4]
input [1:0] interrupts, // @[:freechips.rocketchip.system.DefaultConfig.fir@214354.4]
input mem_axi4_0_aw_ready, // @[:freechips.rocketchip.system.DefaultConfig.fir@214355.4]
output mem_axi4_0_aw_valid, // @[:freechips.rocketchip.system.DefaultConfig.fir@214355.4]
output [3:0] mem_axi4_0_aw_bits_id, // @[:freechips.rocketchip.system.DefaultConfig.fir@214355.4]
output [31:0] mem_axi4_0_aw_bits_addr, // @[:freechips.rocketchip.system.DefaultConfig.fir@214355.4]
output [7:0] mem_axi4_0_aw_bits_len, // @[:freechips.rocketchip.system.DefaultConfig.fir@214355.4]
output [2:0] mem_axi4_0_aw_bits_size, // @[:freechips.rocketchip.system.DefaultConfig.fir@214355.4]
output [1:0] mem_axi4_0_aw_bits_burst, // @[:freechips.rocketchip.system.DefaultConfig.fir@214355.4]
output mem_axi4_0_aw_bits_lock, // @[:freechips.rocketchip.system.DefaultConfig.fir@214355.4]
output [3:0] mem_axi4_0_aw_bits_cache, // @[:freechips.rocketchip.system.DefaultConfig.fir@214355.4]
output [2:0] mem_axi4_0_aw_bits_prot, // @[:freechips.rocketchip.system.DefaultConfig.fir@214355.4]
output [3:0] mem_axi4_0_aw_bits_qos, // @[:freechips.rocketchip.system.DefaultConfig.fir@214355.4]
input mem_axi4_0_w_ready, // @[:freechips.rocketchip.system.DefaultConfig.fir@214355.4]
output mem_axi4_0_w_valid, // @[:freechips.rocketchip.system.DefaultConfig.fir@214355.4]
output [63:0] mem_axi4_0_w_bits_data, // @[:freechips.rocketchip.system.DefaultConfig.fir@214355.4]
output [7:0] mem_axi4_0_w_bits_strb, // @[:freechips.rocketchip.system.DefaultConfig.fir@214355.4]
output mem_axi4_0_w_bits_last, // @[:freechips.rocketchip.system.DefaultConfig.fir@214355.4]
output mem_axi4_0_b_ready, // @[:freechips.rocketchip.system.DefaultConfig.fir@214355.4]
input mem_axi4_0_b_valid, // @[:freechips.rocketchip.system.DefaultConfig.fir@214355.4]
input [3:0] mem_axi4_0_b_bits_id, // @[:freechips.rocketchip.system.DefaultConfig.fir@214355.4]
input [1:0] mem_axi4_0_b_bits_resp, // @[:freechips.rocketchip.system.DefaultConfig.fir@214355.4]
input mem_axi4_0_ar_ready, // @[:freechips.rocketchip.system.DefaultConfig.fir@214355.4]
output mem_axi4_0_ar_valid, // @[:freechips.rocketchip.system.DefaultConfig.fir@214355.4]
output [3:0] mem_axi4_0_ar_bits_id, // @[:freechips.rocketchip.system.DefaultConfig.fir@214355.4]
output [31:0] mem_axi4_0_ar_bits_addr, // @[:freechips.rocketchip.system.DefaultConfig.fir@214355.4]
output [7:0] mem_axi4_0_ar_bits_len, // @[:freechips.rocketchip.system.DefaultConfig.fir@214355.4]
output [2:0] mem_axi4_0_ar_bits_size, // @[:freechips.rocketchip.system.DefaultConfig.fir@214355.4]
output [1:0] mem_axi4_0_ar_bits_burst, // @[:freechips.rocketchip.system.DefaultConfig.fir@214355.4]
output mem_axi4_0_ar_bits_lock, // @[:freechips.rocketchip.system.DefaultConfig.fir@214355.4]
output [3:0] mem_axi4_0_ar_bits_cache, // @[:freechips.rocketchip.system.DefaultConfig.fir@214355.4]
output [2:0] mem_axi4_0_ar_bits_prot, // @[:freechips.rocketchip.system.DefaultConfig.fir@214355.4]
output [3:0] mem_axi4_0_ar_bits_qos, // @[:freechips.rocketchip.system.DefaultConfig.fir@214355.4]
output mem_axi4_0_r_ready, // @[:freechips.rocketchip.system.DefaultConfig.fir@214355.4]
input mem_axi4_0_r_valid, // @[:freechips.rocketchip.system.DefaultConfig.fir@214355.4]
input [3:0] mem_axi4_0_r_bits_id, // @[:freechips.rocketchip.system.DefaultConfig.fir@214355.4]
input [63:0] mem_axi4_0_r_bits_data, // @[:freechips.rocketchip.system.DefaultConfig.fir@214355.4]
input [1:0] mem_axi4_0_r_bits_resp, // @[:freechips.rocketchip.system.DefaultConfig.fir@214355.4]
input mem_axi4_0_r_bits_last, // @[:freechips.rocketchip.system.DefaultConfig.fir@214355.4]
input mmio_axi4_0_aw_ready, // @[:freechips.rocketchip.system.DefaultConfig.fir@214356.4]
output mmio_axi4_0_aw_valid, // @[:freechips.rocketchip.system.DefaultConfig.fir@214356.4]
output [3:0] mmio_axi4_0_aw_bits_id, // @[:freechips.rocketchip.system.DefaultConfig.fir@214356.4]
output [30:0] mmio_axi4_0_aw_bits_addr, // @[:freechips.rocketchip.system.DefaultConfig.fir@214356.4]
output [7:0] mmio_axi4_0_aw_bits_len, // @[:freechips.rocketchip.system.DefaultConfig.fir@214356.4]
output [2:0] mmio_axi4_0_aw_bits_size, // @[:freechips.rocketchip.system.DefaultConfig.fir@214356.4]
output [1:0] mmio_axi4_0_aw_bits_burst, // @[:freechips.rocketchip.system.DefaultConfig.fir@214356.4]
output mmio_axi4_0_aw_bits_lock, // @[:freechips.rocketchip.system.DefaultConfig.fir@214356.4]
output [3:0] mmio_axi4_0_aw_bits_cache, // @[:freechips.rocketchip.system.DefaultConfig.fir@214356.4]
output [2:0] mmio_axi4_0_aw_bits_prot, // @[:freechips.rocketchip.system.DefaultConfig.fir@214356.4]
output [3:0] mmio_axi4_0_aw_bits_qos, // @[:freechips.rocketchip.system.DefaultConfig.fir@214356.4]
input mmio_axi4_0_w_ready, // @[:freechips.rocketchip.system.DefaultConfig.fir@214356.4]
output mmio_axi4_0_w_valid, // @[:freechips.rocketchip.system.DefaultConfig.fir@214356.4]
output [63:0] mmio_axi4_0_w_bits_data, // @[:freechips.rocketchip.system.DefaultConfig.fir@214356.4]
output [7:0] mmio_axi4_0_w_bits_strb, // @[:freechips.rocketchip.system.DefaultConfig.fir@214356.4]
output mmio_axi4_0_w_bits_last, // @[:freechips.rocketchip.system.DefaultConfig.fir@214356.4]
output mmio_axi4_0_b_ready, // @[:freechips.rocketchip.system.DefaultConfig.fir@214356.4]
input mmio_axi4_0_b_valid, // @[:freechips.rocketchip.system.DefaultConfig.fir@214356.4]
input [3:0] mmio_axi4_0_b_bits_id, // @[:freechips.rocketchip.system.DefaultConfig.fir@214356.4]
input [1:0] mmio_axi4_0_b_bits_resp, // @[:freechips.rocketchip.system.DefaultConfig.fir@214356.4]
input mmio_axi4_0_ar_ready, // @[:freechips.rocketchip.system.DefaultConfig.fir@214356.4]
output mmio_axi4_0_ar_valid, // @[:freechips.rocketchip.system.DefaultConfig.fir@214356.4]
output [3:0] mmio_axi4_0_ar_bits_id, // @[:freechips.rocketchip.system.DefaultConfig.fir@214356.4]
output [30:0] mmio_axi4_0_ar_bits_addr, // @[:freechips.rocketchip.system.DefaultConfig.fir@214356.4]
output [7:0] mmio_axi4_0_ar_bits_len, // @[:freechips.rocketchip.system.DefaultConfig.fir@214356.4]
output [2:0] mmio_axi4_0_ar_bits_size, // @[:freechips.rocketchip.system.DefaultConfig.fir@214356.4]
output [1:0] mmio_axi4_0_ar_bits_burst, // @[:freechips.rocketchip.system.DefaultConfig.fir@214356.4]
output mmio_axi4_0_ar_bits_lock, // @[:freechips.rocketchip.system.DefaultConfig.fir@214356.4]
output [3:0] mmio_axi4_0_ar_bits_cache, // @[:freechips.rocketchip.system.DefaultConfig.fir@214356.4]
output [2:0] mmio_axi4_0_ar_bits_prot, // @[:freechips.rocketchip.system.DefaultConfig.fir@214356.4]
output [3:0] mmio_axi4_0_ar_bits_qos, // @[:freechips.rocketchip.system.DefaultConfig.fir@214356.4]
output mmio_axi4_0_r_ready, // @[:freechips.rocketchip.system.DefaultConfig.fir@214356.4]
input mmio_axi4_0_r_valid, // @[:freechips.rocketchip.system.DefaultConfig.fir@214356.4]
input [3:0] mmio_axi4_0_r_bits_id, // @[:freechips.rocketchip.system.DefaultConfig.fir@214356.4]
input [63:0] mmio_axi4_0_r_bits_data, // @[:freechips.rocketchip.system.DefaultConfig.fir@214356.4]
input [1:0] mmio_axi4_0_r_bits_resp, // @[:freechips.rocketchip.system.DefaultConfig.fir@214356.4]
input mmio_axi4_0_r_bits_last, // @[:freechips.rocketchip.system.DefaultConfig.fir@214356.4]
output l2_frontend_bus_axi4_0_aw_ready, // @[:freechips.rocketchip.system.DefaultConfig.fir@214357.4]
input l2_frontend_bus_axi4_0_aw_valid, // @[:freechips.rocketchip.system.DefaultConfig.fir@214357.4]
input [7:0] l2_frontend_bus_axi4_0_aw_bits_id, // @[:freechips.rocketchip.system.DefaultConfig.fir@214357.4]
input [31:0] l2_frontend_bus_axi4_0_aw_bits_addr, // @[:freechips.rocketchip.system.DefaultConfig.fir@214357.4]
input [7:0] l2_frontend_bus_axi4_0_aw_bits_len, // @[:freechips.rocketchip.system.DefaultConfig.fir@214357.4]
input [2:0] l2_frontend_bus_axi4_0_aw_bits_size, // @[:freechips.rocketchip.system.DefaultConfig.fir@214357.4]
input [1:0] l2_frontend_bus_axi4_0_aw_bits_burst, // @[:freechips.rocketchip.system.DefaultConfig.fir@214357.4]
input l2_frontend_bus_axi4_0_aw_bits_lock, // @[:freechips.rocketchip.system.DefaultConfig.fir@214357.4]
input [3:0] l2_frontend_bus_axi4_0_aw_bits_cache, // @[:freechips.rocketchip.system.DefaultConfig.fir@214357.4]
input [2:0] l2_frontend_bus_axi4_0_aw_bits_prot, // @[:freechips.rocketchip.system.DefaultConfig.fir@214357.4]
input [3:0] l2_frontend_bus_axi4_0_aw_bits_qos, // @[:freechips.rocketchip.system.DefaultConfig.fir@214357.4]
output l2_frontend_bus_axi4_0_w_ready, // @[:freechips.rocketchip.system.DefaultConfig.fir@214357.4]
input l2_frontend_bus_axi4_0_w_valid, // @[:freechips.rocketchip.system.DefaultConfig.fir@214357.4]
input [63:0] l2_frontend_bus_axi4_0_w_bits_data, // @[:freechips.rocketchip.system.DefaultConfig.fir@214357.4]
input [7:0] l2_frontend_bus_axi4_0_w_bits_strb, // @[:freechips.rocketchip.system.DefaultConfig.fir@214357.4]
input l2_frontend_bus_axi4_0_w_bits_last, // @[:freechips.rocketchip.system.DefaultConfig.fir@214357.4]
input l2_frontend_bus_axi4_0_b_ready, // @[:freechips.rocketchip.system.DefaultConfig.fir@214357.4]
output l2_frontend_bus_axi4_0_b_valid, // @[:freechips.rocketchip.system.DefaultConfig.fir@214357.4]
output [7:0] l2_frontend_bus_axi4_0_b_bits_id, // @[:freechips.rocketchip.system.DefaultConfig.fir@214357.4]
output [1:0] l2_frontend_bus_axi4_0_b_bits_resp, // @[:freechips.rocketchip.system.DefaultConfig.fir@214357.4]
output l2_frontend_bus_axi4_0_ar_ready, // @[:freechips.rocketchip.system.DefaultConfig.fir@214357.4]
input l2_frontend_bus_axi4_0_ar_valid, // @[:freechips.rocketchip.system.DefaultConfig.fir@214357.4]
input [7:0] l2_frontend_bus_axi4_0_ar_bits_id, // @[:freechips.rocketchip.system.DefaultConfig.fir@214357.4]
input [31:0] l2_frontend_bus_axi4_0_ar_bits_addr, // @[:freechips.rocketchip.system.DefaultConfig.fir@214357.4]
input [7:0] l2_frontend_bus_axi4_0_ar_bits_len, // @[:freechips.rocketchip.system.DefaultConfig.fir@214357.4]
input [2:0] l2_frontend_bus_axi4_0_ar_bits_size, // @[:freechips.rocketchip.system.DefaultConfig.fir@214357.4]
input [1:0] l2_frontend_bus_axi4_0_ar_bits_burst, // @[:freechips.rocketchip.system.DefaultConfig.fir@214357.4]
input l2_frontend_bus_axi4_0_ar_bits_lock, // @[:freechips.rocketchip.system.DefaultConfig.fir@214357.4]
input [3:0] l2_frontend_bus_axi4_0_ar_bits_cache, // @[:freechips.rocketchip.system.DefaultConfig.fir@214357.4]
input [2:0] l2_frontend_bus_axi4_0_ar_bits_prot, // @[:freechips.rocketchip.system.DefaultConfig.fir@214357.4]
input [3:0] l2_frontend_bus_axi4_0_ar_bits_qos, // @[:freechips.rocketchip.system.DefaultConfig.fir@214357.4]
input l2_frontend_bus_axi4_0_r_ready, // @[:freechips.rocketchip.system.DefaultConfig.fir@214357.4]
output l2_frontend_bus_axi4_0_r_valid, // @[:freechips.rocketchip.system.DefaultConfig.fir@214357.4]
output [7:0] l2_frontend_bus_axi4_0_r_bits_id, // @[:freechips.rocketchip.system.DefaultConfig.fir@214357.4]
output [63:0] l2_frontend_bus_axi4_0_r_bits_data, // @[:freechips.rocketchip.system.DefaultConfig.fir@214357.4]
output [1:0] l2_frontend_bus_axi4_0_r_bits_resp, // @[:freechips.rocketchip.system.DefaultConfig.fir@214357.4]
output l2_frontend_bus_axi4_0_r_bits_last // @[:freechips.rocketchip.system.DefaultConfig.fir@214357.4]
);
Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment