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imrehg/vab820-kernel.patch

Created July 15, 2014 07:47
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VIA VAB-820 patches to apply to the Freescale L3.0.35_4.1.0_130816 kernel
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vab820-kernel.patch
diff --git a/arch/arm/kernel/process.c b/arch/arm/kernel/process.c
index f818b4e..efe9b13 100644
--- a/arch/arm/kernel/process.c
+++ b/arch/arm/kernel/process.c
@@ -240,7 +240,10 @@ void machine_shutdown(void)
void machine_halt(void)
{
machine_shutdown();
- while (1);
+ //while (1);
+ //Peter edit for power off
+ if (pm_power_off)
+ pm_power_off();
}
void machine_power_off(void)
diff --git a/arch/arm/mach-mx6/board-mx6q_sabrelite.c b/arch/arm/mach-mx6/board-mx6q_sabrelite.c
index 1fe0f7b..b96abcb 100644
--- a/arch/arm/mach-mx6/board-mx6q_sabrelite.c
+++ b/arch/arm/mach-mx6/board-mx6q_sabrelite.c
@@ -74,6 +74,7 @@
#include "crm_regs.h"
#include "cpu_op-mx6.h"
+/*
#define MX6Q_SABRELITE_SD3_CD IMX_GPIO_NR(7, 0)
#define MX6Q_SABRELITE_SD3_WP IMX_GPIO_NR(7, 1)
#define MX6Q_SABRELITE_SD4_CD IMX_GPIO_NR(2, 6)
@@ -92,7 +93,8 @@
#define MX6Q_SABRELITE_VOL_DOWN_KEY IMX_GPIO_NR(4, 5)
#define MX6Q_SABRELITE_CSI0_RST IMX_GPIO_NR(1, 8)
#define MX6Q_SABRELITE_CSI0_PWN IMX_GPIO_NR(1, 6)
-
+*/
+//#ifdef CONFIG_MX6_ENET_IRQ_TO_GPIO
#define MX6_ENET_IRQ IMX_GPIO_NR(1, 6)
#define IOMUX_OBSRV_MUX1_OFFSET 0x3c
#define OBSRV_MUX1_MASK 0x3f
@@ -102,6 +104,46 @@
PAD_CTL_PUS_22K_UP | PAD_CTL_SPEED_MED | \
PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
+
+// (Sylvia) added
+#define MX6Q_SABRELITE_GPIO_1 IMX_GPIO_NR(1, 1)
+#define MX6Q_SABRELITE_GPIO_2 IMX_GPIO_NR(1, 2)
+#define MX6Q_SABRELITE_GPIO_4 IMX_GPIO_NR(1, 4)
+#define MX6Q_SABRELITE_GPIO_5 IMX_GPIO_NR(1, 5)
+#define MX6Q_SABRELITE_GPIO_7 IMX_GPIO_NR(1, 7)
+#define MX6Q_SABRELITE_GPIO_8 IMX_GPIO_NR(1, 8)
+#define MX6Q_SABRELITE_GPIO_9 IMX_GPIO_NR(1, 9)
+#define MX6Q_SABRELITE_CSI0_PWN IMX_GPIO_NR(1, 16)
+#define MX6Q_SABRELITE_CSI0_RST IMX_GPIO_NR(1, 17)
+#define MX6Q_SABRELITE_PCIE_CSI_PWN IMX_GPIO_NR(1, 19)
+#define MX6Q_SABRELITE_ENET_PHY_INT IMX_GPIO_NR(1, 28) // copied from boundary
+
+#define MX6Q_SABRELITE_SD2_CD IMX_GPIO_NR(2, 2)
+
+#define MX6Q_SABRELITE_USB_123_EN IMX_GPIO_NR(3, 0)
+#define MX6Q_SABRELITE_ECSPI1_CS1 IMX_GPIO_NR(3, 19) // ECSPI1_SS1 -> GPIO
+//#define MX6Q_SABRELITE_USB_OTG_OC IMX_GPIO_NR(3, 21)
+#define MX6Q_SABRELITE_USB_OTG_PWR IMX_GPIO_NR(3, 22) // USB_OTG_PWR -> GPIO (X : NO USE OTG POWER PIN)
+#define MX6Q_SABRELITE_LVDS_DE IMX_GPIO_NR(3, 28) // 0/X
+//#define MX6Q_SABRELITE_USB_123_OC IMX_GPIO_NR(3, 30)
+
+#define MX6Q_SABRELITE_GPIO_19_PLED IMX_GPIO_NR(4, 5)
+/* Ken modified for VAB820 RA PIN changed */
+//#define MX6Q_SABRELITE_PCIE_DIS_B IMX_GPIO_NR(4, 14)
+#define MX6Q_SABRELITE_PCIE_DIS_B IMX_GPIO_NR(4, 9)
+#define MX6Q_SABRELITE_ECSPI3_CS0 IMX_GPIO_NR(4, 24) // CSPI3_CS0 -> GPIO
+#define MX6Q_SABRELITE_ECSPI3_CS1 IMX_GPIO_NR(4, 25) // CSPI3_CS1 -> GPIO
+
+#define MX6Q_SABRELITE_PCIE_WAKE_B IMX_GPIO_NR(5, 20)
+
+#define MX6Q_SABRELITE_CAP_TCH_INT0 IMX_GPIO_NR(6, 8)
+#define MX6Q_SABRELITE_CABC_EN0 IMX_GPIO_NR(6, 15) // LVDS_EN
+
+#define MX6Q_SABRELITE_GPIO_16 IMX_GPIO_NR(7, 11)
+#define MX6Q_SABRELITE_PCIE_RST_B IMX_GPIO_NR(7, 12)
+#define MX6Q_SABRELITE_USB_HUB_RST_B IMX_GPIO_NR(7, 13)
+
+
void __init early_console_setup(unsigned long base, struct clk *clk);
static struct clk *sata_clk;
@@ -116,6 +158,184 @@ extern void (*put_cpu_regulator)(void);
static iomux_v3_cfg_t mx6q_sabrelite_pads[] = {
/* AUDMUX */
+ MX6Q_PAD_DISP0_DAT20__AUDMUX_AUD4_TXC,
+ MX6Q_PAD_DISP0_DAT21__AUDMUX_AUD4_TXD,
+ MX6Q_PAD_DISP0_DAT22__AUDMUX_AUD4_TXFS,
+ MX6Q_PAD_DISP0_DAT23__AUDMUX_AUD4_RXD,
+
+ /* CCM */
+ MX6Q_PAD_GPIO_0__CCM_CLKO, /* SGTL500 sys_mclk - GPIO_0_CLKO */
+
+ /* HDMI */
+ MX6Q_PAD_KEY_ROW2__HDMI_TX_CEC_LINE, // HDMI_CEC_IN
+
+ /* ECSPI1 */
+ // (Sylvia) added
+ MX6Q_PAD_EIM_D16__ECSPI1_SCLK,
+ MX6Q_PAD_EIM_D17__ECSPI1_MISO,
+ MX6Q_PAD_EIM_D18__ECSPI1_MOSI,
+ MX6Q_PAD_EIM_D19__GPIO_3_19, //MX6Q_PAD_EIM_D19__ECSPI1_SS1,
+ // (what's the diff between GPIO and ESCPI1_SS1???)
+ // both SDB and SabreLite choose GPIO rather then ECSPI1_SS1
+ /* ECSPI3 */
+ // (Sylvia) added
+ MX6Q_PAD_DISP0_DAT0__ECSPI3_SCLK,
+ MX6Q_PAD_DISP0_DAT1__ECSPI3_MOSI,
+ MX6Q_PAD_DISP0_DAT2__ECSPI3_MISO,
+ MX6Q_PAD_DISP0_DAT3__GPIO_4_24,
+ MX6Q_PAD_DISP0_DAT4__GPIO_4_25,
+
+
+#if 1 // VAB820
+ /* ENET */
+ MX6Q_PAD_RGMII_TXC__ENET_RGMII_TXC,
+ MX6Q_PAD_RGMII_TD0__ENET_RGMII_TD0,
+ MX6Q_PAD_RGMII_TD1__ENET_RGMII_TD1,
+ MX6Q_PAD_RGMII_TD2__ENET_RGMII_TD2,
+ MX6Q_PAD_RGMII_TD3__ENET_RGMII_TD3,
+ MX6Q_PAD_RGMII_TX_CTL__ENET_RGMII_TX_CTL,
+ MX6Q_PAD_RGMII_RXC__ENET_RGMII_RXC,
+ MX6Q_PAD_RGMII_RD0__ENET_RGMII_RD0,
+ MX6Q_PAD_RGMII_RD1__ENET_RGMII_RD1,
+ MX6Q_PAD_RGMII_RD2__ENET_RGMII_RD2,
+ MX6Q_PAD_RGMII_RD3__ENET_RGMII_RD3,
+ MX6Q_PAD_RGMII_RX_CTL__ENET_RGMII_RX_CTL,
+
+ MX6Q_PAD_ENET_MDIO__ENET_MDIO,
+ MX6Q_PAD_ENET_MDC__ENET_MDC,
+ MX6Q_PAD_ENET_REF_CLK__ENET_TX_CLK, // ENET_REF_CLK
+ MX6Q_PAD_ENET_TX_EN__GPIO_1_28, /* Micrel RGMII Phy Interrupt */ // RGMII_INT : ENET_TX_EN(ALT5)
+
+ // (Sylvia) added
+ MX6Q_PAD_ENET_CRS_DV__GPIO_1_25, // RGMII reset - RGMII_nRST : ENET_CRS_DV(ALT5)
+#endif
+
+ /* GPIO pins */ // (Sylvia) added
+ MX6Q_PAD_GPIO_1__GPIO_1_1, // GPIO1
+ MX6Q_PAD_GPIO_2__GPIO_1_2, // GPIO2
+ MX6Q_PAD_GPIO_4__GPIO_1_4, // GPIO4
+ MX6Q_PAD_GPIO_5__GPIO_1_5, // GPIO5
+ MX6Q_PAD_GPIO_7__GPIO_1_7, // GPIO7
+ MX6Q_PAD_GPIO_8__GPIO_1_8, // GPIO8
+ MX6Q_PAD_GPIO_9__GPIO_1_9, // GPIO9
+ MX6Q_PAD_GPIO_16__GPIO_7_11, // GPIO16
+
+
+ /* GPIO4 */ // (Sylvia) added
+ MX6Q_PAD_GPIO_19__GPIO_4_5, // GPIO_19_PLED : for LED turn off
+
+ /* I2C1 - ADV7180 */
+ MX6Q_PAD_CSI0_DAT8__I2C1_SDA,
+ MX6Q_PAD_CSI0_DAT9__I2C1_SCL,
+
+ /* I2C2 - HDMI, Audio */
+ MX6Q_PAD_KEY_COL3__I2C2_SCL,
+ MX6Q_PAD_KEY_ROW3__I2C2_SDA,
+
+ /* I2C3 - LVDS, PCIE, J7 */
+ MX6Q_PAD_GPIO_3__I2C3_SCL,
+ MX6Q_PAD_GPIO_6__I2C3_SDA,
+
+
+ /* CSI - ADV7180 */
+ // (Sylvia) added
+ MX6Q_PAD_CSI0_DAT12__IPU1_CSI0_D_12,
+ MX6Q_PAD_CSI0_DAT13__IPU1_CSI0_D_13,
+ MX6Q_PAD_CSI0_DAT14__IPU1_CSI0_D_14,
+ MX6Q_PAD_CSI0_DAT15__IPU1_CSI0_D_15,
+ MX6Q_PAD_CSI0_DAT16__IPU1_CSI0_D_16,
+ MX6Q_PAD_CSI0_DAT17__IPU1_CSI0_D_17,
+ MX6Q_PAD_CSI0_DAT18__IPU1_CSI0_D_18,
+ MX6Q_PAD_CSI0_DAT19__IPU1_CSI0_D_19,
+ MX6Q_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC,
+ MX6Q_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC,
+ MX6Q_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK,
+
+ MX6Q_PAD_SD1_DAT0__GPIO_1_16, // CSI0_PWN
+ MX6Q_PAD_SD1_DAT1__GPIO_1_17, // CSI0_RST_B
+
+
+
+ /* LVDS */
+ MX6Q_PAD_NANDF_ALE__GPIO_6_8, // CAP_TCH_INT0
+ MX6Q_PAD_NANDF_CS2__GPIO_6_15, // LVDS_EN
+ MX6Q_PAD_EIM_D28__GPIO_3_28, // LVDS_DE
+ MX6Q_PAD_DISP0_DAT9__PWM2_PWMO, // DISP0_CONTRAST : PWM2_OUT(ALT2)
+
+ /* PCIE */
+ MX6Q_PAD_GPIO_17__GPIO_7_12, /* PCIE_RST_B */
+ /* Ken modified for VAB820 RA PIN changed */
+ //MX6Q_PAD_KEY_COL4__GPIO_4_14, /* PCIE_DIS_B */
+ MX6Q_PAD_KEY_ROW1__GPIO_4_9, /* PCIE_DIS_B */
+ MX6Q_PAD_CSI0_DATA_EN__GPIO_5_20, // PCIE_WAKE_B
+ MX6Q_PAD_SD1_DAT2__GPIO_1_19, // CSI_PWN
+
+ /* UART1 */
+ // (Sylvia) added : DTE mode
+ MX6Q_PAD_SD3_DAT6__UART1_TXD, // IOMUX_PAD(0x0694, 0x02AC, 1, 0x0000, 0, 0)
+ MX6Q_PAD_SD3_DAT7__UART1_RXD, // IOMUX_PAD(0x0690, 0x02A8, 1, 0x0920, 2, 0) // assign RX => 2: SD3_DAT7
+ MX6Q_PAD_EIM_D20__UART1_CTS, // IOMUX_PAD(0x03B4, 0x00A0, 4, 0x0000, 0, 0)
+ MX6Q_PAD_SD3_DAT0__UART1_RTS, // IOMUX_PAD(0x06A8, 0x02C0, 1, 0x091C, 2, 0) // assign RTS => 2 : SD3_DAT0
+ //MX6Q_PAD_EIM_D24__UART1_DTR, // (Peter) modify for strange issue
+ MX6Q_PAD_EIM_D24__GPIO_3_24,
+ MX6Q_PAD_EIM_D25__UART1_DSR,
+ MX6Q_PAD_EIM_D23__UART1_DCD,
+ MX6Q_PAD_EIM_EB3__UART1_RI,
+
+ /* UART2 for debug */
+ // (Sylvia) added
+ MX6Q_PAD_EIM_D26__UART2_TXD,
+ MX6Q_PAD_EIM_D27__UART2_RXD,
+
+ /* USB OTG*/
+ MX6Q_PAD_ENET_RX_ER__ANATOP_USBOTG_ID, // USB_OTG_ID
+ MX6Q_PAD_EIM_D21__USBOH3_USBOTG_OC, //MX6Q_PAD_EIM_D21__GPIO_3_21, // USB_OTG_OC
+ MX6Q_PAD_EIM_D22__GPIO_3_22, // (Sylvia) why GPIO for power pin???
+ //(Sylvia) added
+ //MX6Q_PAD_EIM_D22__USBOH3_USBOTG_PWR, // USB_OTG_PWR_EN // should it be defined as GPIO ??? (ref to SabreLite)
+
+ /* USB */
+ MX6Q_PAD_EIM_D30__USBOH3_USBH1_OC, // MX6Q_PAD_EIM_D30__GPIO_3_30, // USB_123_OC
+ MX6Q_PAD_EIM_DA0__GPIO_3_0, // USB_123_EN (0:enable 1:disable)
+ MX6Q_PAD_GPIO_18__GPIO_7_13, // USB_HUB_RESET_B
+
+ /* USDHC2 - Micro SD */
+ MX6Q_PAD_SD2_CLK__USDHC2_CLK,
+ MX6Q_PAD_SD2_CMD__USDHC2_CMD,
+ MX6Q_PAD_SD2_DAT0__USDHC2_DAT0,
+ MX6Q_PAD_SD2_DAT1__USDHC2_DAT1,
+ MX6Q_PAD_SD2_DAT2__USDHC2_DAT2,
+ MX6Q_PAD_SD2_DAT3__USDHC2_DAT3,
+ MX6Q_PAD_NANDF_D2__GPIO_2_2, /* SD2_CD */
+
+ /* USDHC4 */
+ MX6Q_PAD_SD4_CLK__USDHC4_CLK_50MHZ,
+ MX6Q_PAD_SD4_CMD__USDHC4_CMD_50MHZ,
+ MX6Q_PAD_SD4_DAT0__USDHC4_DAT0_50MHZ,
+ MX6Q_PAD_SD4_DAT1__USDHC4_DAT1_50MHZ,
+ MX6Q_PAD_SD4_DAT2__USDHC4_DAT2_50MHZ,
+ MX6Q_PAD_SD4_DAT3__USDHC4_DAT3_50MHZ,
+ MX6Q_PAD_SD4_DAT4__USDHC4_DAT4_50MHZ,
+ MX6Q_PAD_SD4_DAT5__USDHC4_DAT5_50MHZ,
+ MX6Q_PAD_SD4_DAT6__USDHC4_DAT6_50MHZ,
+ MX6Q_PAD_SD4_DAT7__USDHC4_DAT7_50MHZ,
+
+ /* WDOG-1 */
+ MX6Q_PAD_DISP0_DAT8__WDOG1_WDOG_B,
+
+ /* Ken added CAN1, CAN2 for VAB820 RA */
+ /* CAN1 */
+ MX6Q_PAD_SD3_CMD__CAN1_TXCAN,
+ MX6Q_PAD_SD3_CLK__CAN1_RXCAN,
+ /* CAN2 */
+ MX6Q_PAD_KEY_COL4__CAN2_TXCAN,
+ MX6Q_PAD_KEY_ROW4__CAN2_RXCAN,
+
+};
+
+#if 0
+static iomux_v3_cfg_t mx6q_sabrelite_pads[] = {
+ /* AUDMUX */
MX6Q_PAD_SD2_DAT0__AUDMUX_AUD4_RXD,
MX6Q_PAD_SD2_DAT3__AUDMUX_AUD4_TXC,
MX6Q_PAD_SD2_DAT2__AUDMUX_AUD4_TXD,
@@ -308,8 +528,25 @@ static iomux_v3_cfg_t mx6q_sabrelite_pads[] = {
MX6Q_PAD_NANDF_D6__GPIO_2_6, /* J20 - SD4_CD */
MX6Q_PAD_NANDF_D7__GPIO_2_7, /* SD4_WP */
};
+#endif
static iomux_v3_cfg_t mx6q_sabrelite_csi0_sensor_pads[] = {
+ MX6Q_PAD_CSI0_DAT12__IPU1_CSI0_D_12,
+ MX6Q_PAD_CSI0_DAT13__IPU1_CSI0_D_13,
+ MX6Q_PAD_CSI0_DAT14__IPU1_CSI0_D_14,
+ MX6Q_PAD_CSI0_DAT15__IPU1_CSI0_D_15,
+ MX6Q_PAD_CSI0_DAT16__IPU1_CSI0_D_16,
+ MX6Q_PAD_CSI0_DAT17__IPU1_CSI0_D_17,
+ MX6Q_PAD_CSI0_DAT18__IPU1_CSI0_D_18,
+ MX6Q_PAD_CSI0_DAT19__IPU1_CSI0_D_19,
+ MX6Q_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC,
+ MX6Q_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC,
+ MX6Q_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK,
+
+ MX6Q_PAD_SD1_DAT0__GPIO_1_16, // CSI0_PWN
+ MX6Q_PAD_SD1_DAT1__GPIO_1_17, // CSI0_RST_B
+
+#if 0 // (Sylvia) marked
/* IPU1 Camera */
MX6Q_PAD_CSI0_DAT8__IPU1_CSI0_D_8,
MX6Q_PAD_CSI0_DAT9__IPU1_CSI0_D_9,
@@ -331,6 +568,7 @@ static iomux_v3_cfg_t mx6q_sabrelite_csi0_sensor_pads[] = {
MX6Q_PAD_SD1_DAT0__GPIO_1_16, /* J5 - Camera GP */
MX6Q_PAD_NANDF_D5__GPIO_2_5, /* J16 - MIPI GP */
MX6Q_PAD_NANDF_WP_B__GPIO_6_9, /* J16 - MIPI GP */
+#endif
};
static iomux_v3_cfg_t mx6q_sabrelite_hdmi_ddc_pads[] = {
@@ -353,9 +591,10 @@ mx6q_sd##id##_##speed##mhz[] = { \
MX6Q_PAD_SD##id##_DAT3__USDHC##id##_DAT3_##speed##MHZ, \
}
-static iomux_v3_cfg_t MX6Q_USDHC_PAD_SETTING(3, 50);
-static iomux_v3_cfg_t MX6Q_USDHC_PAD_SETTING(3, 100);
-static iomux_v3_cfg_t MX6Q_USDHC_PAD_SETTING(3, 200);
+// (Sylvia) marked
+//static iomux_v3_cfg_t MX6Q_USDHC_PAD_SETTING(3, 50);
+//static iomux_v3_cfg_t MX6Q_USDHC_PAD_SETTING(3, 100);
+//static iomux_v3_cfg_t MX6Q_USDHC_PAD_SETTING(3, 200);
static iomux_v3_cfg_t MX6Q_USDHC_PAD_SETTING(4, 50);
static iomux_v3_cfg_t MX6Q_USDHC_PAD_SETTING(4, 100);
static iomux_v3_cfg_t MX6Q_USDHC_PAD_SETTING(4, 200);
@@ -380,6 +619,7 @@ static int plt_sd_pad_change(unsigned int index, int clock)
u32 sd_pads_50mhz_cnt;
switch (index) {
+#if 0 // (Sylvia) marked
case 2:
sd_pads_200mhz = mx6q_sd3_200mhz;
sd_pads_100mhz = mx6q_sd3_100mhz;
@@ -389,6 +629,7 @@ static int plt_sd_pad_change(unsigned int index, int clock)
sd_pads_100mhz_cnt = ARRAY_SIZE(mx6q_sd3_100mhz);
sd_pads_50mhz_cnt = ARRAY_SIZE(mx6q_sd3_50mhz);
break;
+#endif
case 3:
sd_pads_200mhz = mx6q_sd4_200mhz;
sd_pads_100mhz = mx6q_sd4_100mhz;
@@ -427,18 +668,35 @@ static int plt_sd_pad_change(unsigned int index, int clock)
}
}
+// (Sylvia) added
+static const struct esdhc_platform_data mx6q_sabrelite_sd2_data __initconst = {
+ .cd_gpio = MX6Q_SABRELITE_SD2_CD,
+ .wp_gpio = -1,//MX6Q_SABRELITE_SD2_WP,
+ .support_8bit = 0,
+ .keep_power_at_suspend = 1,
+ //.platform_pad_change = plt_sd_pad_change,
+ .cd_type = ESDHC_CD_GPIO,
+ //.delay_line = 0,
+};
+#if 0
static const struct esdhc_platform_data mx6q_sabrelite_sd3_data __initconst = {
.cd_gpio = MX6Q_SABRELITE_SD3_CD,
.wp_gpio = MX6Q_SABRELITE_SD3_WP,
.keep_power_at_suspend = 1,
.platform_pad_change = plt_sd_pad_change,
};
+#endif
static const struct esdhc_platform_data mx6q_sabrelite_sd4_data __initconst = {
- .cd_gpio = MX6Q_SABRELITE_SD4_CD,
- .wp_gpio = MX6Q_SABRELITE_SD4_WP,
+ .always_present = 1,
.keep_power_at_suspend = 1,
- .platform_pad_change = plt_sd_pad_change,
+ .support_8bit = 1,
+ // (Sylvia) marked
+ //.cd_gpio = -1,//MX6Q_SABRELITE_SD4_CD,
+ //.wp_gpio = -1,//MX6Q_SABRELITE_SD4_WP,
+ //.platform_pad_change = plt_sd_pad_change,
+ .delay_line = 0,
+ .cd_type = ESDHC_CD_PERMANENT,
};
static const struct anatop_thermal_platform_data
@@ -446,26 +704,173 @@ static const struct anatop_thermal_platform_data
.name = "anatop_thermal",
};
+//(Peter) Fix DTE mode hang issue
+static const struct imxuart_platform_data mx6_vab820_uart1_data __initconst = {
+ .flags = IMXUART_HAVE_RTSCTS | IMXUART_USE_DCEDTE | IMXUART_SDMA,
+ .dma_req_rx = MX6Q_DMA_REQ_UART1_RX,
+ .dma_req_tx = MX6Q_DMA_REQ_UART1_TX,
+};
+
static inline void mx6q_sabrelite_init_uart(void)
{
- imx6q_add_imx_uart(0, NULL);
+ imx6q_add_imx_uart(0, &mx6_vab820_uart1_data);
imx6q_add_imx_uart(1, NULL);
}
-static int mx6q_sabrelite_fec_phy_init(struct phy_device *phydev)
+// must set 0 or !0
+#define FEC_DBG_INFO 0
+
+static void print_ksz9021_dbg_info(struct phy_device *phydev)
{
- /* prefer master mode, disable 1000 Base-T capable */
- phy_write(phydev, 0x9, 0x1c00);
+ int i = 0;
+ printk("<1>[IEEE Defined]\n");
+ for(i = 0; i <= 0xf; i++){
+ printk("<1> Reg %d: 0x%x", i, phy_read(phydev, i));
+ }
+ printk("<1>\n[Vendor]\n");
+
+ for(i = 0x11; i <= 0x1f; i++){
+ printk("<1> Reg %d: 0x%x", i, phy_read(phydev, i));
+ }
+
+ printk("<1>\n[Extended]\n");
+ for(i = 256; i <= 261; i++){
+ phy_write(phydev, 0x0b, i);
+ printk("<1> Reg %d: 0x%x", i, phy_read(phydev, 13));
+ }
+
+ printk("<1>================= Peter FEC DBG END ==================\n");
+}
+static void print_ksz9031_dbg_info(struct phy_device *phydev)
+{
+ int i = 0;
+ printk("<1>[IEEE Defined]\n");
+ for(i = 0; i <= 0xf; i++){
+ printk("<1> Reg %d: 0x%x", i, phy_read(phydev, i));
+ }
+ printk("<1>\n[Vendor]\n");
+
+ for(i = 0x11; i <= 0x1f; i++){
+ printk("<1> Reg %d: 0x%x", i, phy_read(phydev, i));
+ }
+
+ printk("<1>\n[MMD]\n");
+
+ //MMD 1h
+ phy_write(phydev, 0xd, 0x1);
+ phy_write(phydev, 0xe, 0x5a);
+ phy_write(phydev, 0xd, 0x4001);
+ printk("<1> MMD 1 R 5Ah: 0x%x\n", phy_read(phydev, 0xe));
+
+ //MMD 2h
+ phy_write(phydev, 0xd, 0x2);
+ phy_write(phydev, 0xe, 0x0);
+ phy_write(phydev, 0xd, 0x8002);
+ for(i = 0; i <= 0x2b; i++){
+ printk("<1> MMD 2 R %xh: 0x%x", i, phy_read(phydev, 0xe));
+ }
+
+ //MMD 3h
+ phy_write(phydev, 0xd, 0x3);
+ phy_write(phydev, 0xe, 0x0);
+ phy_write(phydev, 0xd, 0x8003);
+ for(i = 0; i <= 0x1; i++){
+ printk("<1> MMD 3 R %xh: 0x%x", i, phy_read(phydev, 0xe));
+ }
+
+ //MMD 7h
+ phy_write(phydev, 0xd, 0x7);
+ phy_write(phydev, 0xe, 0x3c);
+ phy_write(phydev, 0xd, 0x4007);
+ printk("<1> MMD 7 R 3Ch: 0x%x\n", phy_read(phydev, 0xe));
+ phy_write(phydev, 0xd, 0x7);
+ phy_write(phydev, 0xe, 0x3d);
+ phy_write(phydev, 0xd, 0x4007);
+ printk("<1> MMD 7 R 3Dh: 0x%x\n", phy_read(phydev, 0xe));
+
+ //MMD 1Ch
+ phy_write(phydev, 0xd, 0x1c);
+ phy_write(phydev, 0xe, 0x4);
+ phy_write(phydev, 0xd, 0x401c);
+ printk("<1> MMD 1C R 4h: 0x%x\n", phy_read(phydev, 0xe));
+ phy_write(phydev, 0xd, 0x1c);
+ phy_write(phydev, 0xe, 0x23);
+ phy_write(phydev, 0xd, 0x401c);
+ printk("<1> MMD 1C R 23h: 0x%x\n", phy_read(phydev, 0xe));
+
+ printk("<1>================= Peter FEC DBG END ==================\n");
+}
+
+static void init_ksz9031(struct phy_device *phydev)
+{
+ printk("init_KSZ9031()\n");
+ /* min rx data delay */
+ if ( 1 ) {
+ phy_write(phydev, 0xd, 0x2);
+ phy_write(phydev, 0xe, 0x5);
+ phy_write(phydev, 0xd, 0x4002);
+ phy_write(phydev, 0xe, 0x0);
+ }
+ // (Sylvia) min tx data delay
+ if ( 1 ) {
+ phy_write(phydev, 0xd, 0x2);
+ phy_write(phydev, 0xe, 0x6);
+ phy_write(phydev, 0xd, 0x4002);
+ phy_write(phydev, 0xe, 0x0);
+ }
+ /* max rx/tx clock delay, min rx/tx control delay */
+ phy_write(phydev, 0xd, 0x2);
+ phy_write(phydev, 0xe, 0x4);
+ phy_write(phydev, 0xd, 0x4002);
+ phy_write(phydev, 0xe, 0x0);
+
+ phy_write(phydev, 0xd, 0x2);
+ phy_write(phydev, 0xe, 0x8);
+ phy_write(phydev, 0xd, 0x4002);
+ phy_write(phydev, 0xe, 0x3ff); //0x1ff);
+ //phy_write(phydev, 0xe, 0x3e0); // rx=0
+ //phy_write(phydev, 0xe, 0x3e8); // rx=8
+ //phy_write(phydev, 0xe, 0x3f0); // rx=0x10
+ //phy_write(phydev, 0xe, 0x3f8); // rx=0x18
+
+ if ( FEC_DBG_INFO ) {
+ print_ksz9031_dbg_info(phydev);
+ }
+}
+
+static void init_ksz9021(struct phy_device *phydev)
+{
+ printk("init_KSZ9021()\n");
/* min rx data delay */
phy_write(phydev, 0x0b, 0x8105);
phy_write(phydev, 0x0c, 0x0000);
+ phy_write(phydev, 0x0b, 0x8106);
+ phy_write(phydev, 0x0c, 0x0000);
+
/* max rx/tx clock delay, min rx/tx control delay */
phy_write(phydev, 0x0b, 0x8104);
phy_write(phydev, 0x0c, 0xf0f0);
phy_write(phydev, 0x0b, 0x104);
+ if ( FEC_DBG_INFO ) {
+ print_ksz9021_dbg_info(phydev);
+ }
+}
+
+static int mx6q_sabrelite_fec_phy_init(struct phy_device *phydev)
+{
+ /* prefer master mode, disable 1000 Base-T capable */
+ phy_write(phydev, 0x9, 0x1c00);
+
+ if ( 0x11 == (0xff & phy_read(phydev, 0x03)) ) {
+ init_ksz9021(phydev);
+ }
+ else {
+ init_ksz9031(phydev);
+ }
+
return 0;
}
@@ -475,34 +880,48 @@ static struct fec_platform_data fec_data __initdata = {
.gpio_irq = MX6_ENET_IRQ,
};
-static int mx6q_sabrelite_spi_cs[] = {
+
+static int mx6q_sabrelite_spi_cs1[] = {
MX6Q_SABRELITE_ECSPI1_CS1,
};
-static const struct spi_imx_master mx6q_sabrelite_spi_data __initconst = {
- .chipselect = mx6q_sabrelite_spi_cs,
- .num_chipselect = ARRAY_SIZE(mx6q_sabrelite_spi_cs),
+static const struct spi_imx_master mx6q_sabrelite_spi_data1 __initconst = {
+ .chipselect = mx6q_sabrelite_spi_cs1,
+ .num_chipselect = ARRAY_SIZE(mx6q_sabrelite_spi_cs1),
+};
+
+static int mx6q_sabrelite_spi_cs3[] = {
+ MX6Q_SABRELITE_ECSPI3_CS0,
+ MX6Q_SABRELITE_ECSPI3_CS1,
+};
+
+static const struct spi_imx_master mx6q_sabrelite_spi_data3 __initconst = {
+ .chipselect = mx6q_sabrelite_spi_cs3,
+ .num_chipselect = ARRAY_SIZE(mx6q_sabrelite_spi_cs3),
};
#if defined(CONFIG_MTD_M25P80) || defined(CONFIG_MTD_M25P80_MODULE)
+/*
static struct mtd_partition imx6_sabrelite_spi_nor_partitions[] = {
+
{
.name = "bootloader",
.offset = 0,
.size = 0x00100000,
},
+
{
.name = "kernel",
.offset = MTDPART_OFS_APPEND,
.size = MTDPART_SIZ_FULL,
},
};
-
+*/
static struct flash_platform_data imx6_sabrelite__spi_flash_data = {
.name = "m25p80",
- .parts = imx6_sabrelite_spi_nor_partitions,
- .nr_parts = ARRAY_SIZE(imx6_sabrelite_spi_nor_partitions),
- .type = "sst25vf016b",
+// .parts = imx6_sabrelite_spi_nor_partitions,
+// .nr_parts = ARRAY_SIZE(imx6_sabrelite_spi_nor_partitions),
+ .type = "sst25vf032b", //"sst25vf016b",
};
#endif
@@ -511,10 +930,24 @@ static struct spi_board_info imx6_sabrelite_spi_nor_device[] __initdata = {
{
.modalias = "m25p80",
.max_speed_hz = 20000000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0,
+ .bus_num = 0, // ECSPI1=0
.chip_select = 0,
.platform_data = &imx6_sabrelite__spi_flash_data,
},
+ {
+ .modalias = "m25p80",
+ .max_speed_hz = 20000000, /* max spi clock (SCK) speed in HZ */
+ .bus_num = 2, // ECSPI3=2
+ .chip_select = 0,
+ .platform_data = &imx6_sabrelite__spi_flash_data,
+ },
+ {
+ .modalias = "m25p80",
+ .max_speed_hz = 20000000, /* max spi clock (SCK) speed in HZ */
+ .bus_num = 2, // ECSPI3=2
+ .chip_select = 1,
+ .platform_data = &imx6_sabrelite__spi_flash_data,
+ },
#endif
};
@@ -575,12 +1008,14 @@ static struct imxi2c_platform_data mx6q_sabrelite_i2c_data = {
.bitrate = 100000,
};
+#if 0 //(Sylvia) marked
static struct i2c_board_info mxc_i2c0_board_info[] __initdata = {
{
I2C_BOARD_INFO("sgtl5000", 0x0a),
},
};
-
+#endif
+#if 0 //(Sylvia) marked
static void mx6q_csi0_cam_powerdown(int powerdown)
{
if (powerdown)
@@ -590,18 +1025,13 @@ static void mx6q_csi0_cam_powerdown(int powerdown)
msleep(2);
}
+#endif
static void mx6q_csi0_io_init(void)
{
mxc_iomux_v3_setup_multiple_pads(mx6q_sabrelite_csi0_sensor_pads,
ARRAY_SIZE(mx6q_sabrelite_csi0_sensor_pads));
- /* Camera power down */
- gpio_request(MX6Q_SABRELITE_CSI0_PWN, "cam-pwdn");
- gpio_direction_output(MX6Q_SABRELITE_CSI0_PWN, 1);
- msleep(1);
- gpio_set_value(MX6Q_SABRELITE_CSI0_PWN, 0);
-
/* Camera reset */
gpio_request(MX6Q_SABRELITE_CSI0_RST, "cam-reset");
gpio_direction_output(MX6Q_SABRELITE_CSI0_RST, 1);
@@ -610,6 +1040,13 @@ static void mx6q_csi0_io_init(void)
msleep(1);
gpio_set_value(MX6Q_SABRELITE_CSI0_RST, 1);
+ /* Camera power down */
+ gpio_request(MX6Q_SABRELITE_CSI0_PWN, "cam-pwdn");
+ gpio_direction_output(MX6Q_SABRELITE_CSI0_PWN, 1);
+ //msleep(1);
+ //gpio_set_value(MX6Q_SABRELITE_CSI0_PWN, 0);
+ gpio_set_value(MX6Q_SABRELITE_CSI0_PWN, 1);
+
/* For MX6Q GPR1 bit19 and bit20 meaning:
* Bit19: 0 - Enable mipi to IPU1 CSI0
* virtual channel is fixed to 0
@@ -625,6 +1062,30 @@ static void mx6q_csi0_io_init(void)
mxc_iomux_set_gpr_register(1, 19, 1, 1);
}
+// (Sylvia) copy from board-mx6q_sabreauto.c
+static void adv7180_pwdn(int powdn)
+{ // (Sylvia) copied from mx6q_csi0_cam_powerdown()
+ if (powdn)
+ gpio_set_value(MX6Q_SABRELITE_CSI0_PWN, 1);
+ else
+ gpio_set_value(MX6Q_SABRELITE_CSI0_PWN, 0);
+
+ msleep(2);
+}
+
+// (Sylvia) copy from board-mx6q_sabreauto.c
+static struct fsl_mxc_tvin_platform_data adv7180_data = {
+ .dvddio_reg = NULL,
+ .dvdd_reg = NULL,
+ .avdd_reg = NULL,
+ .pvdd_reg = NULL,
+ .pwdn = adv7180_pwdn,
+ .reset = NULL,
+ .cvbs = true,
+ .io_init = mx6q_csi0_io_init,
+};
+
+#if 0 // (Sylvia) marked
static struct fsl_mxc_camera_platform_data camera_data = {
.mclk = 24000000,
.mclk_source = 0,
@@ -632,36 +1093,63 @@ static struct fsl_mxc_camera_platform_data camera_data = {
.io_init = mx6q_csi0_io_init,
.pwdn = mx6q_csi0_cam_powerdown,
};
+#endif
+
+static struct i2c_board_info mxc_i2c0_board_info[] __initdata = {
+
+ { // (Sylvia) copy from board-mx6q_sabreauto.c
+ I2C_BOARD_INFO("adv7180", 0x21),
+ .platform_data = (void *)&adv7180_data,
+ },
+
+};
static struct i2c_board_info mxc_i2c1_board_info[] __initdata = {
{
I2C_BOARD_INFO("mxc_hdmi_i2c", 0x50),
},
- {
+/* {
I2C_BOARD_INFO("ov564x", 0x3c),
.platform_data = (void *)&camera_data,
- },
+ },*/
};
static struct i2c_board_info mxc_i2c2_board_info[] __initdata = {
- {
+/* {
I2C_BOARD_INFO("egalax_ts", 0x4),
.irq = gpio_to_irq(MX6Q_SABRELITE_CAP_TCH_INT1),
+ },*/
+ { // (Sylvia) modified - LVDS
+ I2C_BOARD_INFO("egalax_ts", 0x4),
+ //.irq = gpio_to_irq(SABRESD_CAP_TCH_INT1),
+ .irq = gpio_to_irq(MX6Q_SABRELITE_CAP_TCH_INT0),
+ },
+ { // (Sylvia) added
+ I2C_BOARD_INFO("sgtl5000", 0x0a),
},
};
static void imx6q_sabrelite_usbotg_vbus(bool on)
{
+ // (Sylvia) USB_OTG_PWR is not used in VAB-820.
if (on)
gpio_set_value(MX6Q_SABRELITE_USB_OTG_PWR, 1);
else
gpio_set_value(MX6Q_SABRELITE_USB_OTG_PWR, 0);
}
+static void imx6q_sabrelite_usbhost1_vbus(bool on)
+{
+ if (on)
+ gpio_set_value_cansleep(MX6Q_SABRELITE_USB_123_EN, 0);
+ else
+ gpio_set_value_cansleep(MX6Q_SABRELITE_USB_123_EN, 1);
+}
+
static void __init imx6q_sabrelite_init_usb(void)
{
int ret = 0;
-
+#if 0
imx_otg_base = MX6_IO_ADDRESS(MX6Q_USB_OTG_BASE_ADDR);
/* disable external charger detect,
* or it will affect signal quality at dp .
@@ -676,6 +1164,69 @@ static void __init imx6q_sabrelite_init_usb(void)
mxc_iomux_set_gpr_register(1, 13, 1, 1);
mx6_set_otghost_vbus_func(imx6q_sabrelite_usbotg_vbus);
+#endif
+
+ // (Sylvia) added : copied from board-mx6q_sabresd.c
+ imx_otg_base = MX6_IO_ADDRESS(MX6Q_USB_OTG_BASE_ADDR);
+ /* disable external charger detect,
+ * or it will affect signal quality at dp .
+ */
+#if 0
+ ret = gpio_request(MX6Q_SABRELITE_USB_OTG_PWR, "usb-pwr");
+ if (ret) {
+ pr_err("failed to get GPIO SABRESD_USB_OTG_PWR: %d\n",
+ ret);
+ return;
+ }
+ gpio_direction_output(MX6Q_SABRELITE_USB_OTG_PWR, 0);
+#endif
+
+
+#if 1
+ /* keep USB host1 VBUS always on */
+ ret = gpio_request(MX6Q_SABRELITE_USB_123_EN, "usb-h1-pwr");
+ if (ret) {
+ pr_err("failed to get GPIO SABRESD_USB_H1_PWR: %d\n",
+ ret);
+ return;
+ }
+ gpio_direction_output(MX6Q_SABRELITE_USB_123_EN, 1);
+#endif
+#if 0
+ // (Sylvia) added : setup OC
+ ret = gpio_request(MX6Q_SABRELITE_USB_OTG_OC, "otg-oc");
+ if (ret) {
+ printk(KERN_ERR"failed to get GPIO MX6Q_SABRELITE_USB_OTG_OC:"
+ " %d\n", ret);
+ return;
+ }
+ gpio_direction_input(MX6Q_SABRELITE_USB_OTG_OC);
+
+ ret = gpio_request(MX6Q_SABRELITE_USB_123_OC, "usbh1-oc");
+ if (ret) {
+ printk(KERN_ERR"failed to get MX6Q_SABRELITE_USB_123_OC:"
+ " %d\n", ret);
+ return;
+ }
+ gpio_direction_input(MX6Q_SABRELITE_USB_123_OC);
+
+#endif
+
+#if 1
+ if (board_is_mx6_reva())
+ mxc_iomux_set_gpr_register(1, 13, 1, 1); // base = 0x020E0000
+ // base + group(1) *4 = 0x020E0004 = IOMUXC_GPR1
+ // start_bits =13 => USB_OTG_ID_SEL
+ // num_bits = 1
+ // value = 1 => selects GPIO_1
+ else
+ mxc_iomux_set_gpr_register(1, 13, 1, 0);
+#endif
+
+ //mx6_set_otghost_vbus_func(imx6q_sabresd_usbotg_vbus); // OTG-PWR-enable decided by OTG ID
+
+ gpio_set_value_cansleep(MX6Q_SABRELITE_USB_123_EN, 0);
+ mx6_set_host1_vbus_func(imx6q_sabrelite_usbhost1_vbus);
}
/* HW Initialization, if return 0, initialization is successful. */
@@ -763,25 +1314,43 @@ static struct ahci_platform_data mx6q_sabrelite_sata_data = {
};
#endif
+/* Ken modified, doesn't need gpio flow control */
static struct gpio mx6q_sabrelite_flexcan_gpios[] = {
- { MX6Q_SABRELITE_CAN1_EN, GPIOF_OUT_INIT_LOW, "flexcan1-en" },
- { MX6Q_SABRELITE_CAN1_STBY, GPIOF_OUT_INIT_LOW, "flexcan1-stby" },
+ //{ MX6Q_SABRELITE_CAN1_EN, GPIOF_OUT_INIT_LOW, "flexcan1-en" },
+ //{ MX6Q_SABRELITE_CAN1_STBY, GPIOF_OUT_INIT_LOW, "flexcan1-stby" },
};
static void mx6q_sabrelite_flexcan0_switch(int enable)
{
- if (enable) {
- gpio_set_value(MX6Q_SABRELITE_CAN1_EN, 1);
- gpio_set_value(MX6Q_SABRELITE_CAN1_STBY, 1);
- } else {
- gpio_set_value(MX6Q_SABRELITE_CAN1_EN, 0);
- gpio_set_value(MX6Q_SABRELITE_CAN1_STBY, 0);
- }
+ if (enable) {
+ //gpio_set_value(MX6Q_SABRELITE_CAN1_EN, 1);
+ //gpio_set_value(MX6Q_SABRELITE_CAN1_STBY, 1);
+ } else {
+ //gpio_set_value(MX6Q_SABRELITE_CAN1_EN, 0);
+ //gpio_set_value(MX6Q_SABRELITE_CAN1_STBY, 0);
+ }
}
+static void mx6q_sabrelite_flexcan1_switch(int enable)
+{
+ if (enable) {
+ //gpio_set_value(MX6Q_SABRELITE_CAN1_EN, 1);
+ //gpio_set_value(MX6Q_SABRELITE_CAN1_STBY, 1);
+ } else {
+ //gpio_set_value(MX6Q_SABRELITE_CAN1_EN, 0);
+ //gpio_set_value(MX6Q_SABRELITE_CAN1_STBY, 0);
+ }
+}
+
+
static const struct flexcan_platform_data
- mx6q_sabrelite_flexcan0_pdata __initconst = {
- .transceiver_switch = mx6q_sabrelite_flexcan0_switch,
+ mx6q_sabrelite_flexcan0_pdata __initconst = {
+ .transceiver_switch = mx6q_sabrelite_flexcan0_switch,
+};
+
+static const struct flexcan_platform_data
+ mx6q_sabrelite_flexcan1_pdata __initconst = {
+ .transceiver_switch = mx6q_sabrelite_flexcan1_switch,
};
static struct viv_gpu_platform_data imx6q_gpu_pdata __initdata = {
@@ -793,9 +1362,16 @@ static struct imx_asrc_platform_data imx_asrc_data = {
.clk_map_ver = 2,
};
+/* Modified by VIA Embedded(SH)
+ * For RadnR dual display, we need to setup 2 fb devices for display(fb0 and fb2) at least.
+ * Do not care about the values, suhc as disp_dev = "lcd",mode_str = "LDB-XGA", we
+ * will re-set it in uboot if we want to enable 'hdmi' or 'ldb' or both.
+ * On VAB820, there are only two outputs, hdmi and lvds(dual channel), so fb0 and fb2 are enough.
+ */
+
static struct ipuv3_fb_platform_data sabrelite_fb_data[] = {
{ /*fb0*/
- .disp_dev = "ldb",
+ .disp_dev = "lcd",
.interface_pix_fmt = IPU_PIX_FMT_RGB666,
.mode_str = "LDB-XGA",
.default_bpp = 16,
@@ -807,13 +1383,13 @@ static struct ipuv3_fb_platform_data sabrelite_fb_data[] = {
.default_bpp = 16,
.int_clk = false,
}, {
- .disp_dev = "ldb",
+ .disp_dev = "lcd",
.interface_pix_fmt = IPU_PIX_FMT_RGB666,
.mode_str = "LDB-SVGA",
.default_bpp = 16,
.int_clk = false,
}, {
- .disp_dev = "ldb",
+ .disp_dev = "lcd",
.interface_pix_fmt = IPU_PIX_FMT_RGB666,
.mode_str = "LDB-VGA",
.default_bpp = 16,
@@ -938,7 +1514,7 @@ static const struct pm_platform_data mx6q_sabrelite_pm_data __initconst = {
.suspend_exit = sabrelite_suspend_exit,
};
-#if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE)
+#if 0 //defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE)
#define GPIO_BUTTON(gpio_num, ev_code, act_low, descr, wake) \
{ \
.gpio = gpio_num, \
@@ -977,11 +1553,12 @@ static void __init sabrelite_add_device_buttons(void)
platform_device_register(&sabrelite_button_device);
}
#else
-static void __init sabrelite_add_device_buttons(void) {}
+//static void __init sabrelite_add_device_buttons(void) {}
#endif
static struct regulator_consumer_supply sabrelite_vmmc_consumers[] = {
- REGULATOR_SUPPLY("vmmc", "sdhci-esdhc-imx.2"),
+ REGULATOR_SUPPLY("vmmc", "sdhci-esdhc-imx.1"),
+ //REGULATOR_SUPPLY("vmmc", "sdhci-esdhc-imx.2"),
REGULATOR_SUPPLY("vmmc", "sdhci-esdhc-imx.3"),
};
@@ -1009,17 +1586,17 @@ static struct platform_device sabrelite_vmmc_reg_devices = {
static struct regulator_consumer_supply sgtl5000_sabrelite_consumer_vdda = {
.supply = "VDDA",
- .dev_name = "0-000a",
+ .dev_name = "2-000a", //"0-000a", // (Sylvia) modified for VAB-820, on which sgtl5000 is linked to I2C3
};
static struct regulator_consumer_supply sgtl5000_sabrelite_consumer_vddio = {
.supply = "VDDIO",
- .dev_name = "0-000a",
+ .dev_name = "2-000a", //"0-000a",
};
static struct regulator_consumer_supply sgtl5000_sabrelite_consumer_vddd = {
.supply = "VDDD",
- .dev_name = "0-000a",
+ .dev_name = "2-000a", //"0-000a",
};
static struct regulator_init_data sgtl5000_sabrelite_vdda_reg_initdata = {
@@ -1039,7 +1616,7 @@ static struct regulator_init_data sgtl5000_sabrelite_vddd_reg_initdata = {
static struct fixed_voltage_config sgtl5000_sabrelite_vdda_reg_config = {
.supply_name = "VDDA",
- .microvolts = 2500000,
+ .microvolts = 3300000, //2500000, (Sylvia) modified for VAB-820 VDDA = 3.3V
.gpio = -1,
.init_data = &sgtl5000_sabrelite_vdda_reg_initdata,
};
@@ -1098,7 +1675,7 @@ static int imx6q_init_audio(void)
}
static struct platform_pwm_backlight_data mx6_sabrelite_pwm_backlight_data = {
- .pwm_id = 3,
+ .pwm_id = 1, //3, (Sylvia) modified for VAB-820
.max_brightness = 255,
.dft_brightness = 128,
.pwm_period_ns = 50000,
@@ -1128,12 +1705,22 @@ static struct mxc_dvfs_platform_data sabrelite_dvfscore_data = {
.dncnt_val = 10,
.delay_time = 80,
};
-
+// steven
+static u32 s_vab820_ram_size = SZ_1G;
static void __init fixup_mxc_board(struct machine_desc *desc, struct tag *tags,
char **cmdline, struct meminfo *mi)
{
+ // steven
+ struct tag *mem_tag = 0;
+ for_each_tag(mem_tag, tags) {
+ if (mem_tag->hdr.tag == ATAG_MEM) {
+ s_vab820_ram_size = mem_tag->u.mem.size;
+ break;
+ }
+ }
}
+#if 1 //enable mipi_csi2 related code to make adv7180 capture workable.
static struct mipi_csi2_platform_data mipi_csi2_pdata = {
.ipu_id = 0,
.csi_id = 0,
@@ -1142,6 +1729,7 @@ static struct mipi_csi2_platform_data mipi_csi2_pdata = {
.dphy_clk = "mipi_pllref_clk",
.pixel_clk = "emi_clk",
};
+#endif
static int __init caam_setup(char *__unused)
{
@@ -1150,6 +1738,37 @@ static int __init caam_setup(char *__unused)
}
early_param("caam", caam_setup);
+static void turnoff_power_led(void)
+{
+ gpio_request(MX6Q_SABRELITE_GPIO_19_PLED, "power-led");
+ gpio_direction_output(MX6Q_SABRELITE_GPIO_19_PLED, 1);
+ gpio_set_value(MX6Q_SABRELITE_GPIO_19_PLED, 0);
+}
+
+//Peter added for power down
+static void turnoff_hdmi(void)
+{
+ void __iomem *mx6_pwr_off = MX6_IO_ADDRESS(0x20c8130);
+ u32 value;
+ value = readl(mx6_pwr_off);
+ writel(value & 0xfffffffe , mx6_pwr_off);
+
+}
+
+static void mx6_poweroff(void)
+{
+ turnoff_power_led();
+ turnoff_hdmi();
+}
+
+// (Sylvia) added PCIE
+static const struct imx_pcie_platform_data mx6_sabrelite_pcie_data __initconst = {
+ .pcie_pwr_en = MX6Q_SABRELITE_PCIE_CSI_PWN,
+ .pcie_rst = MX6Q_SABRELITE_PCIE_RST_B,
+ .pcie_wake_up = MX6Q_SABRELITE_PCIE_WAKE_B,
+ .pcie_dis = MX6Q_SABRELITE_PCIE_DIS_B,
+};
+
/*!
* Board specific initialization.
*/
@@ -1164,7 +1783,7 @@ static void __init mx6_sabrelite_board_init(void)
mxc_iomux_v3_setup_multiple_pads(mx6q_sabrelite_pads,
ARRAY_SIZE(mx6q_sabrelite_pads));
-
+#if 0
if (enet_to_gpio_6) {
iomux_v3_cfg_t enet_gpio_pad =
MX6Q_PAD_GPIO_6__ENET_IRQ_TO_GPIO_6;
@@ -1175,8 +1794,8 @@ static void __init mx6_sabrelite_board_init(void)
MX6Q_PAD_GPIO_6__GPIO_1_6;
mxc_iomux_v3_setup_pad(camera_gpio_pad);
}
-
-#ifdef CONFIG_FEC_1588
+#endif
+#if 0 //#ifdef CONFIG_FEC_1588
/* Set GPIO_16 input for IEEE-1588 ts_clk and RMII reference clock
* For MX6 GPR1 bit21 meaning:
* Bit21: 0 - GPIO_16 pad output
@@ -1212,10 +1831,16 @@ static void __init mx6_sabrelite_board_init(void)
imx6q_add_v4l2_capture(0, &capture_data[0]);
- imx6q_add_v4l2_capture(1, &capture_data[1]);
+ //Disable the empty CSI device register to avoid the warning message of "V4L capture slave device not found".
+ //imx6q_add_v4l2_capture(1, &capture_data[1]);
+
+ //enable mipi_csi2 related code to make adv7180 capture workable.
imx6q_add_mipi_csi2(&mipi_csi2_pdata);
imx6q_add_imx_snvs_rtc();
+ //Peter added for power down
+ pm_power_off = mx6_poweroff;
+
if (1 == caam_enabled)
imx6q_add_imx_caam();
@@ -1230,7 +1855,8 @@ static void __init mx6_sabrelite_board_init(void)
ARRAY_SIZE(mxc_i2c2_board_info));
/* SPI */
- imx6q_add_ecspi(0, &mx6q_sabrelite_spi_data);
+ imx6q_add_ecspi(0, &mx6q_sabrelite_spi_data1);
+ imx6q_add_ecspi(2, &mx6q_sabrelite_spi_data3);
spi_device_init();
imx6q_add_mxc_hdmi(&hdmi_data);
@@ -1247,11 +1873,14 @@ static void __init mx6_sabrelite_board_init(void)
imx6_init_fec(fec_data);
imx6q_add_pm_imx(0, &mx6q_sabrelite_pm_data);
+ // (Sylvia) modified
+ //imx6q_add_sdhci_usdhc_imx(2, &mx6q_sabrelite_sd3_data);
imx6q_add_sdhci_usdhc_imx(3, &mx6q_sabrelite_sd4_data);
- imx6q_add_sdhci_usdhc_imx(2, &mx6q_sabrelite_sd3_data);
+ imx6q_add_sdhci_usdhc_imx(1, &mx6q_sabrelite_sd2_data);
imx_add_viv_gpu(&imx6_gpu_data, &imx6q_gpu_pdata);
imx6q_sabrelite_init_usb();
+#if 0 // (Sylvia) marked
if (cpu_is_mx6q()) {
#ifdef CONFIG_SATA_AHCI_PLATFORM
imx6q_add_ahci(0, &mx6q_sabrelite_sata_data);
@@ -1260,6 +1889,7 @@ static void __init mx6_sabrelite_board_init(void)
(void __iomem *)ioremap(MX6Q_SATA_BASE_ADDR, SZ_4K));
#endif
}
+#endif
imx6q_add_vpu();
imx6q_init_audio();
platform_device_register(&sabrelite_vmmc_reg_devices);
@@ -1267,14 +1897,28 @@ static void __init mx6_sabrelite_board_init(void)
imx_asrc_data.asrc_audio_clk = clk_get(NULL, "asrc_serial_clk");
imx6q_add_asrc(&imx_asrc_data);
+
/* release USB Hub reset */
- gpio_set_value(MX6Q_SABRELITE_USB_HUB_RESET, 1);
+ // (Sylvia) modified
+ //gpio_set_value(MX6Q_SABRELITE_USB_HUB_RESET, 1);
+ //gpio_set_value(MX6Q_SABRELITE_USB_HUB_RST_B, 1);
+ gpio_request(MX6Q_SABRELITE_USB_HUB_RST_B, "usbhub-reset");
+ gpio_direction_output(MX6Q_SABRELITE_USB_HUB_RST_B, 1);
+ gpio_set_value(MX6Q_SABRELITE_USB_HUB_RST_B, 0);
+ msleep(1);
+ gpio_set_value(MX6Q_SABRELITE_USB_HUB_RST_B, 1);
+
+
+ //(Peter) add for UART1 DTR pin
+ gpio_set_value(IMX_GPIO_NR(3, 24), 0);
- imx6q_add_mxc_pwm(0);
+ // (Sylvia) modified : VAB-820 uses only PWM2 (MX6Q_PAD_DISP0_DAT9__PWM2_PWMO)
+ //imx6q_add_mxc_pwm(0);
imx6q_add_mxc_pwm(1);
- imx6q_add_mxc_pwm(2);
- imx6q_add_mxc_pwm(3);
- imx6q_add_mxc_pwm_backlight(3, &mx6_sabrelite_pwm_backlight_data);
+ //imx6q_add_mxc_pwm(2);
+ //imx6q_add_mxc_pwm(3);
+ imx6q_add_mxc_pwm_backlight(1, &mx6_sabrelite_pwm_backlight_data);
+ //imx6q_add_mxc_pwm_backlight(3, &mx6_sabrelite_pwm_backlight_data);
imx6q_add_otp();
imx6q_add_viim();
@@ -1283,17 +1927,21 @@ static void __init mx6_sabrelite_board_init(void)
imx6q_add_dvfs_core(&sabrelite_dvfscore_data);
- sabrelite_add_device_buttons();
+ //(Sylvia) marked
+ //sabrelite_add_device_buttons();
imx6q_add_hdmi_soc();
imx6q_add_hdmi_soc_dai();
- ret = gpio_request_array(mx6q_sabrelite_flexcan_gpios,
- ARRAY_SIZE(mx6q_sabrelite_flexcan_gpios));
- if (ret)
- pr_err("failed to request flexcan1-gpios: %d\n", ret);
- else
- imx6q_add_flexcan0(&mx6q_sabrelite_flexcan0_pdata);
+ /* Ken modified */
+ ret = gpio_request_array(mx6q_sabrelite_flexcan_gpios,
+ ARRAY_SIZE(mx6q_sabrelite_flexcan_gpios));
+ if (ret)
+ pr_err("failed to request flexcan1-gpios: %d\n", ret);
+ else {
+ imx6q_add_flexcan0(&mx6q_sabrelite_flexcan0_pdata);
+ imx6q_add_flexcan1(&mx6q_sabrelite_flexcan1_pdata);
+ }
clko2 = clk_get(NULL, "clko2_clk");
if (IS_ERR(clko2))
@@ -1309,9 +1957,14 @@ static void __init mx6_sabrelite_board_init(void)
clk_enable(clko2);
imx6q_add_busfreq();
+ // (Sylvia) added
+ imx6q_add_pcie(&mx6_sabrelite_pcie_data);
+
imx6q_add_perfmon(0);
imx6q_add_perfmon(1);
imx6q_add_perfmon(2);
+
+ printk("VAB-820......\n");
}
extern void __iomem *twd_base;
@@ -1338,15 +1991,17 @@ static void __init mx6q_sabrelite_reserve(void)
#if defined(CONFIG_MXC_GPU_VIV) || defined(CONFIG_MXC_GPU_VIV_MODULE)
if (imx6q_gpu_pdata.reserved_mem_size) {
+ // steven
phys = memblock_alloc_base(imx6q_gpu_pdata.reserved_mem_size,
- SZ_4K, SZ_1G);
+ SZ_4K, s_vab820_ram_size);
memblock_remove(phys, imx6q_gpu_pdata.reserved_mem_size);
imx6q_gpu_pdata.reserved_mem_base = phys;
}
#endif
if (vout_mem.res_msize) {
+ // steven: SZ_1G -> s_vab820_ram_size
phys = memblock_alloc_base(vout_mem.res_msize,
- SZ_4K, SZ_1G);
+ SZ_4K, s_vab820_ram_size);
memblock_remove(phys, vout_mem.res_msize);
vout_mem.res_mbase = phys;
}
@@ -1354,9 +2009,9 @@ static void __init mx6q_sabrelite_reserve(void)
}
/*
- * initialize __mach_desc_MX6Q_SABRELITE data structure.
+ * initialize __mach_desc_MX6Q_VAB820 data structure.
*/
-MACHINE_START(MX6Q_SABRELITE, "Freescale i.MX 6Quad Sabre-Lite Board")
+MACHINE_START(MX6Q_SABRELITE, "Freescale i.MX 6Quad VAB-820 Board")
/* Maintainer: Freescale Semiconductor, Inc. */
.boot_params = MX6_PHYS_OFFSET + 0x100,
.fixup = fixup_mxc_board,
diff --git a/arch/arm/plat-mxc/include/mach/iomux-mx6q.h b/arch/arm/plat-mxc/include/mach/iomux-mx6q.h
index 16cd87f..0923500 100644
--- a/arch/arm/plat-mxc/include/mach/iomux-mx6q.h
+++ b/arch/arm/plat-mxc/include/mach/iomux-mx6q.h
@@ -37,6 +37,11 @@
PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
+//Peter added for VAB-820 DTE mode
+#define MX6Q_UART_RTSDTR_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
+ PAD_CTL_PUS_100K_DOWN | PAD_CTL_SPEED_MED | \
+ PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
+
#define MX6Q_USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | \
PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
@@ -3038,6 +3043,10 @@
IOMUX_PAD(0x06A8, 0x02C0, 0, 0x0000, 0, 0)
#define _MX6Q_PAD_SD3_DAT0__UART1_CTS \
IOMUX_PAD(0x06A8, 0x02C0, 1, 0x091C, 2, 0)
+
+#define _MX6Q_PAD_SD3_DAT0__UART1_RTS \
+ IOMUX_PAD(0x06A8, 0x02C0, 1, 0x091C, 2, 0) // (Sylvia) added
+
#define _MX6Q_PAD_SD3_DAT0__CAN2_TXCAN \
IOMUX_PAD(0x06A8, 0x02C0, 2, 0x0000, 0, 0)
#define _MX6Q_PAD_SD3_DAT0__USBOH3_UH3_DFD_OUT_6 \
@@ -4079,8 +4088,10 @@
(_MX6Q_PAD_EIM_D24__GPIO_3_24 | MUX_PAD_CTRL(MX6Q_HIGH_DRV))
#define MX6Q_PAD_EIM_D24__AUDMUX_AUD5_RXFS \
(_MX6Q_PAD_EIM_D24__AUDMUX_AUD5_RXFS | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+// (Peter) modify for voltage issue
#define MX6Q_PAD_EIM_D24__UART1_DTR \
- (_MX6Q_PAD_EIM_D24__UART1_DTR | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
+ (_MX6Q_PAD_EIM_D24__UART1_DTR | MUX_PAD_CTRL(MX6Q_UART_RTSDTR_PAD_CTRL))
#define MX6Q_PAD_EIM_D25__WEIM_WEIM_D_25 \
(_MX6Q_PAD_EIM_D25__WEIM_WEIM_D_25 | MUX_PAD_CTRL(MX6Q_WEIM_NOR_PAD_CTRL))
@@ -6676,6 +6687,8 @@
(_MX6Q_PAD_SD3_DAT0__USDHC3_DAT0 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL_200MHZ))
#define MX6Q_PAD_SD3_DAT0__UART1_CTS \
(_MX6Q_PAD_SD3_DAT0__UART1_CTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
+#define MX6Q_PAD_SD3_DAT0__UART1_RTS \
+ (_MX6Q_PAD_SD3_DAT0__UART1_RTS | MUX_PAD_CTRL(MX6Q_UART_RTSDTR_PAD_CTRL)) // (Sylvia) added; Peter edit for 1.6V issue
#define MX6Q_PAD_SD3_DAT0__CAN2_TXCAN \
(_MX6Q_PAD_SD3_DAT0__CAN2_TXCAN | MUX_PAD_CTRL(NO_PAD_CTRL))
#define MX6Q_PAD_SD3_DAT0__USBOH3_UH3_DFD_OUT_6 \
diff --git a/drivers/media/video/mxc/capture/adv7180.c b/drivers/media/video/mxc/capture/adv7180.c
index 3c12fdc..bff1506 100644
--- a/drivers/media/video/mxc/capture/adv7180.c
+++ b/drivers/media/video/mxc/capture/adv7180.c
@@ -41,6 +41,7 @@ static struct fsl_mxc_tvin_platform_data *tvin_plat;
extern void gpio_sensor_active(void);
extern void gpio_sensor_inactive(void);
+static void adv7180_hard_reset(bool cvbs);
static int adv7180_probe(struct i2c_client *adapter,
const struct i2c_device_id *id);
static int adv7180_detach(struct i2c_client *client);
@@ -187,8 +188,10 @@ static inline int adv7180_read(u8 reg)
int val;
val = i2c_smbus_read_byte_data(adv7180_data.sen.i2c_client, reg);
if (val < 0) {
- dev_dbg(&adv7180_data.sen.i2c_client->dev,
- "%s:read reg error: reg=%2x\n", __func__, reg);
+ /* dev_dbg(&adv7180_data.sen.i2c_client->dev,
+ "%s:read reg error: reg=%2x\n", __func__, reg); */
+ dev_err(&adv7180_data.sen.i2c_client->dev,
+ "%s:read reg error: reg=%2x, return val=%d\n", __func__, reg, val);
return -1;
}
return val;
@@ -401,6 +404,28 @@ static int ioctl_s_parm(struct v4l2_int_device *s, struct v4l2_streamparm *a)
switch (a->type) {
/* These are all the possible cases. */
case V4L2_BUF_TYPE_VIDEO_CAPTURE:
+ // Added By Dylan
+ //Just take advantage of this standard ioctl func as s_input ioctl
+ //Select input from CVBS or S-Video
+ switch (a->parm.raw_data[0]) {
+ case 1:
+ /* CVBS input on ANT3 */
+ //insel = true;
+ //adv7180_hard_reset(insel);
+ adv7180_write_reg(ADV7180_INPUT_CTL, 0x04);
+ pr_err ("ADV7180: Set input to CVBS\n");
+ break;
+ case 2:
+ /* S-Video input, Y on ANT1, C on ANT2 */
+ //insel = false;
+ //adv7180_hard_reset(insel);
+ adv7180_write_reg(ADV7180_INPUT_CTL, 0x06);
+ pr_err ("ADV7180: Set input to S-Video\n");
+ break;
+ default:
+ pr_err("ADV7180: Unkown input select, set nothing\n");
+ break;
+ }
case V4L2_BUF_TYPE_VIDEO_OUTPUT:
case V4L2_BUF_TYPE_VIDEO_OVERLAY:
case V4L2_BUF_TYPE_VBI_CAPTURE:
@@ -808,13 +833,21 @@ static void adv7180_hard_reset(bool cvbs)
if (cvbs) {
/* Set CVBS input on AIN1 */
- adv7180_write_reg(ADV7180_INPUT_CTL, 0x00);
+ //adv7180_write_reg(ADV7180_INPUT_CTL, 0x00);
+
+ /* (Sylvia) added : Set CVBS input on AIN3 */
+ adv7180_write_reg(ADV7180_INPUT_CTL, 0x04);
+ adv7180_write_reg(0x27, 0x58);
} else {
/*
* Set YPbPr input on AIN1,4,5 and normal
* operations(autodection of all stds).
*/
- adv7180_write_reg(ADV7180_INPUT_CTL, 0x09);
+ //adv7180_write_reg(ADV7180_INPUT_CTL, 0x09);
+
+ /* (Sylvia) added : Set Y/C input on AIN1,2 and normal */
+ adv7180_write_reg(ADV7180_INPUT_CTL, 0x06);
+ adv7180_write_reg(0x27, 0x69);
}
/* Datasheet recommends */
@@ -852,7 +885,7 @@ static void adv7180_hard_reset(bool cvbs)
adv7180_write_reg(0x24, 0x00);
adv7180_write_reg(0x25, 0x00);
adv7180_write_reg(0x26, 0x00);
- adv7180_write_reg(0x27, 0x58);
+ //adv7180_write_reg(0x27, 0x58); // (Sylvia) marked
adv7180_write_reg(0x28, 0x00);
adv7180_write_reg(0x29, 0x00);
adv7180_write_reg(0x2A, 0x00);
@@ -1081,7 +1114,7 @@ static int adv7180_probe(struct i2c_client *client,
int ret = 0;
tvin_plat = client->dev.platform_data;
- printk(KERN_ERR"DBG sensor data is at %p\n", &adv7180_data);
+ printk(KERN_ERR"DBG adv7180 sensor data is at %p\n", &adv7180_data);
pr_debug("In adv7180_probe\n");
diff --git a/drivers/media/video/mxc/capture/mxc_v4l2_capture.c b/drivers/media/video/mxc/capture/mxc_v4l2_capture.c
index 9130388..08c2b5f 100644
--- a/drivers/media/video/mxc/capture/mxc_v4l2_capture.c
+++ b/drivers/media/video/mxc/capture/mxc_v4l2_capture.c
@@ -48,7 +48,7 @@ static int video_nr = -1;
/*! This data is used for the output to the display. */
#define MXC_V4L2_CAPTURE_NUM_OUTPUTS 6
-#define MXC_V4L2_CAPTURE_NUM_INPUTS 2
+#define MXC_V4L2_CAPTURE_NUM_INPUTS 3
static struct v4l2_output mxc_capture_outputs[MXC_V4L2_CAPTURE_NUM_OUTPUTS] = {
{
.index = 0,
@@ -112,7 +112,16 @@ static struct v4l2_input mxc_capture_inputs[MXC_V4L2_CAPTURE_NUM_INPUTS] = {
},
{
.index = 1,
- .name = "CSI MEM",
+ .name = "CVBS",//changed by Dylan, default "CSI MEM"
+ .type = V4L2_INPUT_TYPE_CAMERA,
+ .audioset = 0,
+ .tuner = 0,
+ .std = V4L2_STD_UNKNOWN,
+ .status = V4L2_IN_ST_NO_POWER,
+ },
+ { //Added by Dylan, add S-Video input
+ .index = 2,
+ .name = "S-VIDEO",
.type = V4L2_INPUT_TYPE_CAMERA,
.audioset = 0,
.tuner = 0,
@@ -805,11 +814,19 @@ static int mxc_v4l2_s_fmt(cam_data *cam, struct v4l2_format *f)
* Force the capture window resolution to be crop bounds
* for CSI MEM input mode.
*/
- if (strcmp(mxc_capture_inputs[cam->current_input].name,
+
+ /* if (strcmp(mxc_capture_inputs[cam->current_input].name,
"CSI MEM") == 0) {
f->fmt.pix.width = cam->crop_current.width;
f->fmt.pix.height = cam->crop_current.height;
+ } */
+
+ if (strcmp(mxc_capture_inputs[cam->current_input].name,"CVBS") == 0 ||
+ strcmp(mxc_capture_inputs[cam->current_input].name,"S-VIDEO") == 0 ) {
+ f->fmt.pix.width = cam->crop_current.width;
+ f->fmt.pix.height = cam->crop_current.height;
}
+ pr_err("In MVX: current input index is %d, current height is %d\n",cam->current_input,cam->crop_current.width);
if (cam->rotation >= IPU_ROTATE_90_RIGHT) {
height = &f->fmt.pix.width;
@@ -1579,7 +1596,12 @@ static int mxc_v4l_open(struct file *file)
cam->low_power == false);
if (strcmp(mxc_capture_inputs[cam->current_input].name,
- "CSI MEM") == 0) {
+ "CVBS") == 0) {
+#if defined(CONFIG_MXC_IPU_CSI_ENC) || defined(CONFIG_MXC_IPU_CSI_ENC_MODULE)
+ err = csi_enc_select(cam);
+#endif
+ } else if (strcmp(mxc_capture_inputs[cam->current_input].name,
+ "S-VIDEO") == 0) {
#if defined(CONFIG_MXC_IPU_CSI_ENC) || defined(CONFIG_MXC_IPU_CSI_ENC_MODULE)
err = csi_enc_select(cam);
#endif
@@ -1737,7 +1759,12 @@ static int mxc_v4l_close(struct file *file)
pr_debug("mxc_v4l_close: release resource\n");
if (strcmp(mxc_capture_inputs[cam->current_input].name,
- "CSI MEM") == 0) {
+ "CVBS") == 0) {
+#if defined(CONFIG_MXC_IPU_CSI_ENC) || defined(CONFIG_MXC_IPU_CSI_ENC_MODULE)
+ err |= csi_enc_deselect(cam);
+#endif
+ } else if (strcmp(mxc_capture_inputs[cam->current_input].name,
+ "S-VIDEO") == 0) {
#if defined(CONFIG_MXC_IPU_CSI_ENC) || defined(CONFIG_MXC_IPU_CSI_ENC_MODULE)
err |= csi_enc_deselect(cam);
#endif
@@ -1869,6 +1896,7 @@ static long mxc_v4l_do_ioctl(struct file *file,
unsigned int ioctlnr, void *arg)
{
struct video_device *dev = video_devdata(file);
+ struct v4l2_streamparm inparm;
cam_data *cam = video_get_drvdata(dev);
int retval = 0;
unsigned long lock_flags;
@@ -2213,7 +2241,12 @@ static long mxc_v4l_do_ioctl(struct file *file,
case VIDIOC_ENUMSTD: {
struct v4l2_standard *e = arg;
pr_debug(" case VIDIOC_ENUMSTD\n");
- *e = cam->standard;
+
+ // (Sylvia) add index check to prevent gstreamer-properties tool from infinite loops.
+ if (e->index > 0)
+ retval = -EINVAL;
+ else
+ *e = cam->standard;
break;
}
@@ -2304,8 +2337,22 @@ static long mxc_v4l_do_ioctl(struct file *file,
V4L2_IN_ST_NO_POWER;
}
- if (strcmp(mxc_capture_inputs[*index].name, "CSI MEM") == 0) {
+ if (strcmp(mxc_capture_inputs[*index].name, "CVBS") == 0) {
+#if defined(CONFIG_MXC_IPU_CSI_ENC) || defined(CONFIG_MXC_IPU_CSI_ENC_MODULE)
+ pr_err ("MXC V4L2 Capture: Choose capture input CVBS\n");
+ inparm.type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
+ inparm.parm.raw_data[0] = 1; //input select flag of adv7180
+ vidioc_int_s_parm(cam->sensor, &inparm);
+ retval = csi_enc_select(cam);
+ if (retval)
+ break;
+#endif
+ } else if (strcmp(mxc_capture_inputs[*index].name,"S-VIDEO") == 0){
#if defined(CONFIG_MXC_IPU_CSI_ENC) || defined(CONFIG_MXC_IPU_CSI_ENC_MODULE)
+ pr_err ("MXC V4L2 Capture: Choose capture input S-Video\n");
+ inparm.type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
+ inparm.parm.raw_data[0] = 2; //input select flag of adv7180
+ vidioc_int_s_parm(cam->sensor, &inparm);
retval = csi_enc_select(cam);
if (retval)
break;
diff --git a/drivers/media/video/mxc/capture/mxc_v4l2_capture.h b/drivers/media/video/mxc/capture/mxc_v4l2_capture.h
index 7edb8d6..eed2558 100644
--- a/drivers/media/video/mxc/capture/mxc_v4l2_capture.h
+++ b/drivers/media/video/mxc/capture/mxc_v4l2_capture.h
@@ -41,7 +41,7 @@
#include <media/v4l2-int-device.h>
-#define FRAME_NUM 10
+#define FRAME_NUM 30
/*!
* v4l2 frame structure.
diff --git a/drivers/net/can/flexcan.c b/drivers/net/can/flexcan.c
index d3b1342..f3123ef 100644
--- a/drivers/net/can/flexcan.c
+++ b/drivers/net/can/flexcan.c
@@ -287,6 +287,8 @@ static int flexcan_start_xmit(struct sk_buff *skb, struct net_device *dev)
const struct flexcan_priv *priv = netdev_priv(dev);
struct flexcan_regs __iomem *regs = priv->base;
struct can_frame *cf = (struct can_frame *)skb->data;
+ //Ken add net_device_stats
+ struct net_device_stats *stats = &dev->stats;
u32 can_id;
u32 ctrl = FLEXCAN_MB_CNT_CODE(0xc) | (cf->can_dlc << 16);
@@ -314,7 +316,8 @@ static int flexcan_start_xmit(struct sk_buff *skb, struct net_device *dev)
writel(data, &regs->cantxfg[FLEXCAN_TX_BUF_ID].data[1]);
}
- can_put_echo_skb(skb, dev, 0);
+ // Ken marked
+ //can_put_echo_skb(skb, dev, 0);
writel(can_id, &regs->cantxfg[FLEXCAN_TX_BUF_ID].can_id);
writel(ctrl, &regs->cantxfg[FLEXCAN_TX_BUF_ID].can_ctrl);
@@ -324,6 +327,10 @@ static int flexcan_start_xmit(struct sk_buff *skb, struct net_device *dev)
writel(0x0, &regs->cantxfg[FLEXCAN_RESERVED_BUF_ID].can_ctrl);
}
+ /* Ken add tx packet count */
+ stats->tx_bytes += cf->can_dlc;
+ stats->tx_packets++;
+
return NETDEV_TX_OK;
}
@@ -591,7 +598,8 @@ static int flexcan_poll(struct napi_struct *napi, int quota)
static irqreturn_t flexcan_irq(int irq, void *dev_id)
{
struct net_device *dev = dev_id;
- struct net_device_stats *stats = &dev->stats;
+ // Ken modify
+ //struct net_device_stats *stats = &dev->stats;
struct flexcan_priv *priv = netdev_priv(dev);
struct flexcan_regs __iomem *regs = priv->base;
u32 reg_iflag1, reg_esr;
@@ -635,8 +643,10 @@ static irqreturn_t flexcan_irq(int irq, void *dev_id)
/* transmission complete interrupt */
if (reg_iflag1 & (1 << FLEXCAN_TX_BUF_ID)) {
- stats->tx_bytes += can_get_echo_skb(dev, 0);
- stats->tx_packets++;
+ /* Ken modify that disable can_get_echo_skb and
+ stats->tx* counters in flexcan_start_xmit() */
+ //stats->tx_bytes += can_get_echo_skb(dev, 0);
+ //stats->tx_packets++;
writel((1 << FLEXCAN_TX_BUF_ID), &regs->iflag1);
netif_wake_queue(dev);
}
diff --git a/drivers/net/fec.c b/drivers/net/fec.c
index 71e0abc..7fb96ec 100755
--- a/drivers/net/fec.c
+++ b/drivers/net/fec.c
@@ -1082,9 +1082,10 @@ static int fec_enet_mii_probe(struct net_device *ndev)
}
/* mask with MAC supported features */
- if (cpu_is_mx6q() || cpu_is_mx6dl())
- phy_dev->supported &= PHY_GBIT_FEATURES;
- else
+ if (cpu_is_mx6q() || cpu_is_mx6dl()) {
+ // steven: support SUPPORTED_Pause
+ phy_dev->supported &= PHY_GBIT_FEATURES | SUPPORTED_Pause;
+ } else
phy_dev->supported &= PHY_BASIC_FEATURES;
/* enable phy pause frame for any platform */
@@ -1668,6 +1669,11 @@ fec_restart(struct net_device *dev, int duplex)
writel(OPT_FRAME_SIZE | 0x06, fep->hwp + FEC_R_CNTRL);
writel(0x0, fep->hwp + FEC_X_CNTRL);
}
+
+ // steven: Frame Truncation Length
+ #define FEC_FTRL 0x1b0
+ writel(PKT_MAXBUF_SIZE, fep->hwp + FEC_FTRL);
+
fep->full_duplex = duplex;
/* Set MII speed */
diff --git a/drivers/net/phy/micrel.c b/drivers/net/phy/micrel.c
index 80747d2..e8087b7 100644
--- a/drivers/net/phy/micrel.c
+++ b/drivers/net/phy/micrel.c
@@ -187,6 +187,21 @@ static struct phy_driver ksz9021_driver = {
.driver = { .owner = THIS_MODULE, },
};
+static struct phy_driver ksz9031_driver = {
+ .phy_id = PHY_ID_KSZ9031,
+ .phy_id_mask = 0x00ffffff,
+ .name = "Micrel KSZ9031 Gigabit PHY",
+ .features = (PHY_GBIT_FEATURES | SUPPORTED_Pause
+ | SUPPORTED_Asym_Pause),
+ .flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
+ .config_init = kszphy_config_init,
+ .config_aneg = genphy_config_aneg,
+ .read_status = genphy_read_status,
+ .ack_interrupt = kszphy_ack_interrupt,
+ .config_intr = ksz9021_config_intr,
+ .driver = { .owner = THIS_MODULE, },
+};
+
static int __init ksphy_init(void)
{
int ret;
@@ -209,8 +224,14 @@ static int __init ksphy_init(void)
if (ret)
goto err5;
+ ret = phy_driver_register(&ksz9031_driver);
+ if (ret)
+ goto err6;
+
return 0;
+err6:
+ phy_driver_unregister(&ksz9031_driver);
err5:
phy_driver_unregister(&ks8041_driver);
err4:
@@ -228,6 +249,7 @@ static void __exit ksphy_exit(void)
phy_driver_unregister(&ks8001_driver);
phy_driver_unregister(&ks8737_driver);
phy_driver_unregister(&ksz9021_driver);
+ phy_driver_unregister(&ksz9031_driver);
phy_driver_unregister(&ks8041_driver);
phy_driver_unregister(&ks8051_driver);
}
@@ -241,6 +263,7 @@ MODULE_LICENSE("GPL");
static struct mdio_device_id __maybe_unused micrel_tbl[] = {
{ PHY_ID_KSZ9021, 0x00ffffff },
+ { PHY_ID_KSZ9031, 0x00ffffff },
{ PHY_ID_KS8001, 0x00ffffff },
{ PHY_ID_KS8737, 0x00ffffff },
{ PHY_ID_KS8041, 0x00ffffff },
diff --git a/drivers/tty/serial/imx.c b/drivers/tty/serial/imx.c
index a512a76..a04f339 100644
--- a/drivers/tty/serial/imx.c
+++ b/drivers/tty/serial/imx.c
@@ -1215,7 +1215,7 @@ imx_set_termios(struct uart_port *port, struct ktermios *termios,
{
struct imx_port *sport = (struct imx_port *)port;
unsigned long flags;
- unsigned int ucr2, old_ucr1, old_txrxen, baud, quot;
+ unsigned int ucr2, old_ucr1, old_ucr3, old_txrxen, baud, quot;
unsigned int old_csize = old ? old->c_cflag & CSIZE : CS8;
unsigned int div, ufcr;
unsigned long num, denom;
@@ -1306,6 +1306,11 @@ imx_set_termios(struct uart_port *port, struct ktermios *termios,
writel(old_ucr1 & ~(UCR1_TXMPTYEN | UCR1_RRDYEN | UCR1_RTSDEN),
sport->port.membase + UCR1);
+ //(Peter)
+ //Disable RI and DCD
+ old_ucr3 = readl(sport->port.membase + UCR3);
+ writel(old_ucr3 & ~(UCR3_RI | UCR3_DCD), sport->port.membase + UCR3);
+
while ( !(readl(sport->port.membase + USR2) & USR2_TXDC))
barrier();
@@ -1579,6 +1584,9 @@ imx_console_write(struct console *co, const char *s, unsigned int count)
writel(old_ucr.ucr2 | UCR2_TXEN, sport->port.membase + UCR2);
+ //(Peter) Disable RI
+ //writel(old_ucr.ucr3 & 0xeff, sport->port.membase + UCR3);
+
uart_console_write(&sport->port, s, count, imx_console_putchar);
/*
diff --git a/drivers/usb/serial/option.c b/drivers/usb/serial/option.c
index cbe3451..77a6474 100644
--- a/drivers/usb/serial/option.c
+++ b/drivers/usb/serial/option.c
@@ -683,6 +683,7 @@ static const struct usb_device_id option_ids[] = {
{ USB_DEVICE_AND_INTERFACE_INFO(HUAWEI_VENDOR_ID, HUAWEI_PRODUCT_E353, 0xff, 0x02, 0x01) }, /* E398 3G Modem */
{ USB_DEVICE_AND_INTERFACE_INFO(HUAWEI_VENDOR_ID, HUAWEI_PRODUCT_E353, 0xff, 0x02, 0x02) }, /* E398 3G PC UI Interface */
{ USB_DEVICE_AND_INTERFACE_INFO(HUAWEI_VENDOR_ID, HUAWEI_PRODUCT_E353, 0xff, 0x02, 0x03) }, /* E398 3G Application Interface */
+ { USB_DEVICE(0x1546, 0x1102) }, // (Sylvia) add U-Blox AG
{ USB_DEVICE(NOVATELWIRELESS_VENDOR_ID, NOVATELWIRELESS_PRODUCT_V640) },
{ USB_DEVICE(NOVATELWIRELESS_VENDOR_ID, NOVATELWIRELESS_PRODUCT_V620) },
{ USB_DEVICE(NOVATELWIRELESS_VENDOR_ID, NOVATELWIRELESS_PRODUCT_V740) },
diff --git a/drivers/video/mxc/ldb.c b/drivers/video/mxc/ldb.c
index 19de5c5..2111680 100644
--- a/drivers/video/mxc/ldb.c
+++ b/drivers/video/mxc/ldb.c
@@ -38,6 +38,8 @@
#include <linux/fsl_devices.h>
#include <mach/hardware.h>
#include <mach/clock.h>
+#include <linux/gpio.h>
+#include <linux/delay.h>
#include "mxc_dispdrv.h"
#define DISPDRV_LDB "ldb"
@@ -77,6 +79,8 @@
#define LDB_CH0_MODE_DISABLE 0x0
#define LDB_SPLIT_MODE_EN 0x00000010
+#define IMX_GPIO_NR(bank, nr) (((bank) - 1) * 32 + (nr))
+#define MX6Q_SABRELITE_GPIO6_15 IMX_GPIO_NR(6, 15)
struct ldb_data {
struct platform_device *pdev;
@@ -102,6 +106,8 @@ struct ldb_data {
};
static int g_ldb_mode;
+static __iomem *lvdsen_reg_base1 = 0;
+static int __ldb_current_status = -1;
static struct fb_videomode ldb_modedb[] = {
{
@@ -128,6 +134,22 @@ static struct fb_videomode ldb_modedb[] = {
0,
FB_VMODE_NONINTERLACED,
FB_MODE_IS_DETAILED,},
+ {
+ "LDB-SXGA", 60, 1280, 1024, KHZ2PICOS(108000),
+ 248, 48,
+ 38, 1,
+ 112, 3,
+ 0,
+ FB_VMODE_NONINTERLACED,
+ FB_MODE_IS_DETAILED,},
+ {
+ "LDB-WSXGA+", 60, 1680, 1050, KHZ2PICOS(146250),
+ 280, 104,
+ 30, 3,
+ 176, 6,
+ 0,
+ FB_VMODE_NONINTERLACED,
+ FB_MODE_IS_DETAILED,},
};
static int ldb_modedb_sz = ARRAY_SIZE(ldb_modedb);
@@ -316,6 +338,36 @@ int ldb_fb_event(struct notifier_block *nb, unsigned long val, void *v)
clk_enable(ldb->setting[index].ldb_di_clk);
ldb->setting[index].clk_en = true;
}
+
+ /* Pull up the LVDS_EN (Backlight) */
+ /* We need to keep the same logic as mxcfb_blank. If current status is already UNBLANK
+ * Some utilitys, such as x11perf, will call FB_BLANK_UNBLANK after they draw one frame,
+ * in this case, if we still go on setting, the screen will have twinkle¡C
+ */
+ if (lvdsen_reg_base1 && (__ldb_current_status != FB_BLANK_UNBLANK)){
+ // Select mux mode: ALT5 mux port: GPIO[15] of instance: gpio6
+ int reg_val = 0;
+ reg_val = readl(lvdsen_reg_base1);
+ reg_val &= 0xfffffff8;
+ reg_val |= 0x5; // [2:0] = 101;
+ writel(reg_val, lvdsen_reg_base1);
+
+ // Set GPIO6[15] to high
+ {
+ gpio_request(MX6Q_SABRELITE_GPIO6_15, "gpio6_15");
+ gpio_direction_output(MX6Q_SABRELITE_GPIO6_15, 1);
+ msleep(100);
+
+ // Sometis, the LVDS panel can not be lighted after reboot, but can be actived in user space
+ // by operating the sysfs node, so we did the same action as user space did.
+ gpio_set_value(MX6Q_SABRELITE_GPIO6_15, 0);
+ msleep(200);
+ gpio_set_value(MX6Q_SABRELITE_GPIO6_15, 1);
+
+ // If do not release it, user space can not operate gpio by sysfs.
+ gpio_free(MX6Q_SABRELITE_GPIO6_15);
+ }
+ }
} else {
if (ldb->setting[index].clk_en) {
clk_disable(ldb->setting[index].ldb_di_clk);
@@ -328,6 +380,7 @@ int ldb_fb_event(struct notifier_block *nb, unsigned long val, void *v)
readl(ldb->control_reg));
}
}
+ __ldb_current_status = *((int *)event->data); // Save the blank status
break;
}
case FB_EVENT_SUSPEND:
@@ -817,6 +870,13 @@ static int ldb_probe(struct platform_device *pdev)
dev_set_drvdata(&pdev->dev, ldb);
+ // Remap for seting NANDF_CS2 to work as GPIO6[15];
+ lvdsen_reg_base1 = ioremap(0x020e02ec, 4);
+ if (lvdsen_reg_base1 == NULL) {
+ printk("%s %d: ioremap for lvds_en failed!\n", __FUNCTION__,__LINE__);
+ goto alloc_failed;
+ }
+
alloc_failed:
return ret;
}
diff --git a/drivers/video/mxc/mxc_ipuv3_fb.c b/drivers/video/mxc/mxc_ipuv3_fb.c
index 4c98d51..8b5c374 100644
--- a/drivers/video/mxc/mxc_ipuv3_fb.c
+++ b/drivers/video/mxc/mxc_ipuv3_fb.c
@@ -47,6 +47,7 @@
#include <linux/uaccess.h>
#include <linux/fsl_devices.h>
#include <asm/mach-types.h>
+#include <linux/delay.h>
#include <mach/ipu-v3.h>
#include "mxc_dispdrv.h"
@@ -2280,6 +2281,38 @@ static int mxcfb_probe(struct platform_device *pdev)
/* Do not clear the fb content drawn in bootloader. */
if (!mxcfbi->late_init)
memset(fbi->screen_base, 0, fbi->fix.smem_len);
+ } else {
+#if 0
+ if (num_registered_fb == 0) {// For fb0
+ fbi->fix.smem_len = 32*1024*1024; // Set to 32M default, will modify it for dual display RADNR
+ fbi->screen_base = dma_alloc_writecombine(fbi->device,
+ fbi->fix.smem_len,
+ (dma_addr_t *)&fbi->fix.smem_start,
+ GFP_DMA | GFP_KERNEL);
+ if (fbi->screen_base == 0){
+ dev_err(fbi->device, "Unable to allocate 32M framebuffer memory for fb0 in probe by dma_alloc_writecombine\n");
+ fbi->fix.smem_start = 0;
+ fbi->fix.smem_len = 0;
+ } else {
+ dev_dbg(fbi->device, "allocated fb @ paddr=0x%08X, size=%d.\n",
+ (uint32_t) fbi->fix.smem_start, fbi->fix.smem_len);
+
+ fbi->screen_size = fbi->fix.smem_len;
+ /* Clear the screen */
+ memset((char *)fbi->screen_base, 0, fbi->fix.smem_len);
+ //TODO: set the virtualX and virtual Y to be the size of virtual screen in X window.
+ }
+ }else if (num_registered_fb == 2) {
+ //TODO: We do not need to alloc new memory for fb2, just use the same memory as fb0
+
+ fbi->fix.smem_len = registered_fb[0]->fix.smem_len;
+ fbi->fix.smem_start = registered_fb[0]->fix.smem_start;
+ fbi->screen_base = registered_fb[0]->screen_base;
+ fbi->screen_size = registered_fb[0]->screen_size;
+ //TODO: set the virtualX and virtual Y to be the size of virtual screen in X window.
+
+ }
+#endif
}
mxcfbi->ipu = ipu_get_soc(mxcfbi->ipu_id);
@@ -2356,6 +2389,11 @@ static int mxcfb_probe(struct platform_device *pdev)
" device propety\n", ret);
#ifdef CONFIG_LOGO
+ /*
+ * We need to wait HDMI to be inited well, otherwise the boot logo will not be shown.
+ */
+ if (!strncmp(plat_data->disp_dev, "hdmi", 4))
+ msleep(500);
fb_prepare_logo(fbi, 0);
fb_show_logo(fbi, 0);
#endif
diff --git a/include/linux/micrel_phy.h b/include/linux/micrel_phy.h
index dd8da34..3222193 100644
--- a/include/linux/micrel_phy.h
+++ b/include/linux/micrel_phy.h
@@ -4,6 +4,7 @@
#define MICREL_PHY_ID_MASK 0x00fffff0
#define PHY_ID_KSZ9021 0x00221611
+#define PHY_ID_KSZ9031 0x00221621
#define PHY_ID_KS8737 0x00221720
#define PHY_ID_KS8041 0x00221510
#define PHY_ID_KS8051 0x00221550
diff --git a/sound/soc/codecs/sgtl5000.c b/sound/soc/codecs/sgtl5000.c
index fd05514..b5564ed 100644
--- a/sound/soc/codecs/sgtl5000.c
+++ b/sound/soc/codecs/sgtl5000.c
@@ -600,9 +600,9 @@ static const struct snd_kcontrol_new sgtl5000_snd_controls[] = {
headphone_volume),
SOC_SINGLE("Headphone Playback ZC Switch", SGTL5000_CHIP_ANA_CTRL,
5, 1, 0),
-
+ // steven: 2bit=0~3, 4-->3
SOC_SINGLE_TLV("Mic Volume", SGTL5000_CHIP_MIC_CTRL,
- 0, 4, 0, mic_gain_tlv),
+ 0, 3, 0, mic_gain_tlv),
/* Bass Enhance enable */
SOC_SINGLE("Bass Enable", SGTL5000_DAP_BASS_ENHANCE,
diff --git a/sound/soc/imx/imx-sgtl5000.c b/sound/soc/imx/imx-sgtl5000.c
index 9325dc8..6fc7fda 100644
--- a/sound/soc/imx/imx-sgtl5000.c
+++ b/sound/soc/imx/imx-sgtl5000.c
@@ -364,7 +364,8 @@ static int __init imx_sgtl5000_init(void)
return -ENOMEM;
if (machine_is_mx35_3ds() || machine_is_mx6q_sabrelite())
- imx_sgtl5000_dai[0].codec_name = "sgtl5000.0-000a";
+ // (Sylvia) modified for VAB-820, on which sgtl5000 is linked to I2C3
+ imx_sgtl5000_dai[0].codec_name = "sgtl5000.2-000a"; //"sgtl5000.0-000a";
else
imx_sgtl5000_dai[0].codec_name = "sgtl5000.1-000a";
Raw
vab820-uboot.patch
diff --git a/board/freescale/mx6q_sabrelite/flash_header.S b/board/freescale/mx6q_sabrelite/flash_header.S
index ee6298f..27488de 100644
--- a/board/freescale/mx6q_sabrelite/flash_header.S
+++ b/board/freescale/mx6q_sabrelite/flash_header.S
@@ -25,6 +25,13 @@
# error "Must define the offset of flash header"
#endif
+// steven: use flash plug_in
+#define CONFIG_FLASH_PLUG_IN
+// steven: if not define CONFIG_FLASH_PLUG_IN, can define VAB820_2G or not
+//#define VAB820_2G
+
+#ifndef CONFIG_FLASH_PLUG_IN
+
#define CPU_2_BE_32(l) \
((((l) & 0x000000FF) << 24) | \
(((l) & 0x0000FF00) << 8) | \
@@ -56,56 +63,208 @@ plugin: .word 0x0
dcd_hdr: .word 0x40D802D2 /* Tag=0xD2, Len=90*8 + 4 + 4, Ver=0x40 */
write_dcd_cmd: .word 0x04D402CC /* Tag=0xCC, Len=90*8 + 4, Param=0x04 */
-/* DCD */
-MXC_DCD_ITEM(1, IOMUXC_BASE_ADDR + 0x5a8, 0x00000030)
-MXC_DCD_ITEM(2, IOMUXC_BASE_ADDR + 0x5b0, 0x00000030)
-MXC_DCD_ITEM(3, IOMUXC_BASE_ADDR + 0x524, 0x00000030)
-MXC_DCD_ITEM(4, IOMUXC_BASE_ADDR + 0x51c, 0x00000030)
+#ifdef VAB820_2G
+
+
+
+
+
+#define VAB820_SDQSx 0x00000028
+MXC_DCD_ITEM(1, IOMUXC_BASE_ADDR + 0x5a8, VAB820_SDQSx)
+MXC_DCD_ITEM(2, IOMUXC_BASE_ADDR + 0x5b0, VAB820_SDQSx)
+MXC_DCD_ITEM(3, IOMUXC_BASE_ADDR + 0x524, VAB820_SDQSx)
+MXC_DCD_ITEM(4, IOMUXC_BASE_ADDR + 0x51c, VAB820_SDQSx)
+MXC_DCD_ITEM(5, IOMUXC_BASE_ADDR + 0x518, VAB820_SDQSx)
+MXC_DCD_ITEM(6, IOMUXC_BASE_ADDR + 0x50c, VAB820_SDQSx)
+MXC_DCD_ITEM(7, IOMUXC_BASE_ADDR + 0x5b8, VAB820_SDQSx)
+MXC_DCD_ITEM(8, IOMUXC_BASE_ADDR + 0x5c0, VAB820_SDQSx)
+#define VAB820_DQM 0x00000028
+MXC_DCD_ITEM(9, IOMUXC_BASE_ADDR + 0x5ac, VAB820_DQM)
+MXC_DCD_ITEM(10, IOMUXC_BASE_ADDR + 0x5b4, VAB820_DQM)
+MXC_DCD_ITEM(11, IOMUXC_BASE_ADDR + 0x528, VAB820_DQM)
+MXC_DCD_ITEM(12, IOMUXC_BASE_ADDR + 0x520, VAB820_DQM)
+MXC_DCD_ITEM(13, IOMUXC_BASE_ADDR + 0x514, VAB820_DQM)
+MXC_DCD_ITEM(14, IOMUXC_BASE_ADDR + 0x510, VAB820_DQM)
+MXC_DCD_ITEM(15, IOMUXC_BASE_ADDR + 0x5bc, VAB820_DQM)
+MXC_DCD_ITEM(16, IOMUXC_BASE_ADDR + 0x5c4, VAB820_DQM)
+// CAS
+MXC_DCD_ITEM(17, IOMUXC_BASE_ADDR + 0x56c, 0x00000028)
+// RAS
+MXC_DCD_ITEM(18, IOMUXC_BASE_ADDR + 0x578, 0x00000028)
+#define VAB820_SDCLKx 0x00000028
+MXC_DCD_ITEM(19, IOMUXC_BASE_ADDR + 0x588, VAB820_SDCLKx)
+MXC_DCD_ITEM(20, IOMUXC_BASE_ADDR + 0x594, VAB820_SDCLKx)
+MXC_DCD_ITEM(21, IOMUXC_BASE_ADDR + 0x57c, 0x00000028)
+MXC_DCD_ITEM(22, IOMUXC_BASE_ADDR + 0x590, 0x00003000)
+MXC_DCD_ITEM(23, IOMUXC_BASE_ADDR + 0x598, 0x00003000)
+MXC_DCD_ITEM(24, IOMUXC_BASE_ADDR + 0x58c, 0x00000000)
+#define VAB820_SDODTx 0x00000028
+MXC_DCD_ITEM(25, IOMUXC_BASE_ADDR + 0x59c, VAB820_SDODTx)
+MXC_DCD_ITEM(26, IOMUXC_BASE_ADDR + 0x5a0, VAB820_SDODTx)
+#define VAB820_BxDS 0x28
+MXC_DCD_ITEM(27, IOMUXC_BASE_ADDR + 0x784, VAB820_BxDS)
+MXC_DCD_ITEM(28, IOMUXC_BASE_ADDR + 0x788, VAB820_BxDS)
+MXC_DCD_ITEM(29, IOMUXC_BASE_ADDR + 0x794, VAB820_BxDS)
+MXC_DCD_ITEM(30, IOMUXC_BASE_ADDR + 0x79c, VAB820_BxDS)
+MXC_DCD_ITEM(31, IOMUXC_BASE_ADDR + 0x7a0, VAB820_BxDS)
+MXC_DCD_ITEM(32, IOMUXC_BASE_ADDR + 0x7a4, VAB820_BxDS)
+MXC_DCD_ITEM(33, IOMUXC_BASE_ADDR + 0x7a8, VAB820_BxDS)
+MXC_DCD_ITEM(34, IOMUXC_BASE_ADDR + 0x748, VAB820_BxDS)
+#define VAB820_ADD_CTL_DS 0x00000028
+MXC_DCD_ITEM(35, IOMUXC_BASE_ADDR + 0x74c, VAB820_ADD_CTL_DS)
+MXC_DCD_ITEM(36, IOMUXC_BASE_ADDR + 0x750, 0x00020000)
+MXC_DCD_ITEM(37, IOMUXC_BASE_ADDR + 0x758, 0x00000000)
+MXC_DCD_ITEM(38, IOMUXC_BASE_ADDR + 0x774, 0x00020000)
+MXC_DCD_ITEM(39, IOMUXC_BASE_ADDR + 0x78c, VAB820_ADD_CTL_DS)
+MXC_DCD_ITEM(40, IOMUXC_BASE_ADDR + 0x798, 0x000C0000)
+
+MXC_DCD_ITEM(41, MMDC_P0_BASE_ADDR + 0x81c, 0x33333333)
+MXC_DCD_ITEM(42, MMDC_P0_BASE_ADDR + 0x820, 0x33333333)
+MXC_DCD_ITEM(43, MMDC_P0_BASE_ADDR + 0x824, 0x33333333)
+MXC_DCD_ITEM(44, MMDC_P0_BASE_ADDR + 0x828, 0x33333333)
+
+MXC_DCD_ITEM(45, MMDC_P1_BASE_ADDR + 0x81c, 0x33333333)
+MXC_DCD_ITEM(46, MMDC_P1_BASE_ADDR + 0x820, 0x33333333)
+MXC_DCD_ITEM(47, MMDC_P1_BASE_ADDR + 0x824, 0x33333333)
+MXC_DCD_ITEM(48, MMDC_P1_BASE_ADDR + 0x828, 0x33333333)
+// MDMISC
+MXC_DCD_ITEM(49, MMDC_P0_BASE_ADDR + 0x018, 0x00081740)
+
+MXC_DCD_ITEM(50, MMDC_P0_BASE_ADDR + 0x01c, 0x00008000)
+// MDCFG0
+MXC_DCD_ITEM(51, MMDC_P0_BASE_ADDR + 0x00c, 0x898E7955)
+// MDCFG1
+MXC_DCD_ITEM(52, MMDC_P0_BASE_ADDR + 0x010, 0xFF328F64)
+// MDCFG2
+MXC_DCD_ITEM(53, MMDC_P0_BASE_ADDR + 0x014, 0x01FF00DB)
+MXC_DCD_ITEM(54, MMDC_P0_BASE_ADDR + 0x02c, 0x000026D2)
+// MDOR
+MXC_DCD_ITEM(55, MMDC_P0_BASE_ADDR + 0x030, 0x008E1023)
+MXC_DCD_ITEM(56, MMDC_P0_BASE_ADDR + 0x008, 0x09444040)
+// MDPDC
+MXC_DCD_ITEM(57, MMDC_P0_BASE_ADDR + 0x004, 0x00020036)
+// MDASP
+MXC_DCD_ITEM(58, MMDC_P0_BASE_ADDR + 0x040, 0x00000047)
+// MDCTL
+MXC_DCD_ITEM(59, MMDC_P0_BASE_ADDR + 0x000, 0x841A0000)
+// MR2
+MXC_DCD_ITEM(60, MMDC_P0_BASE_ADDR + 0x01c, 0x04088032)
+MXC_DCD_ITEM(61, MMDC_P0_BASE_ADDR + 0x01c, 0x0408803A)
+// MR3
+MXC_DCD_ITEM(62, MMDC_P0_BASE_ADDR + 0x01c, 0x00008033)
+MXC_DCD_ITEM(63, MMDC_P0_BASE_ADDR + 0x01c, 0x0000803B)
+// MR1
+MXC_DCD_ITEM(64, MMDC_P0_BASE_ADDR + 0x01c, 0x00428031)
+MXC_DCD_ITEM(65, MMDC_P0_BASE_ADDR + 0x01c, 0x00428039)
+// MR0
+MXC_DCD_ITEM(66, MMDC_P0_BASE_ADDR + 0x01c, 0x09408030)
+MXC_DCD_ITEM(67, MMDC_P0_BASE_ADDR + 0x01c, 0x09408038)
+// ZQ calibration
+MXC_DCD_ITEM(68, MMDC_P0_BASE_ADDR + 0x01c, 0x04008040)
+MXC_DCD_ITEM(69, MMDC_P0_BASE_ADDR + 0x01c, 0x04008048)
+// ZQ
+MXC_DCD_ITEM(70, MMDC_P0_BASE_ADDR + 0x800, 0xA1390003)
+MXC_DCD_ITEM(71, MMDC_P1_BASE_ADDR + 0x800, 0xA1390003)
+//// final DDR setup
+// MMDC0_MDREF
+MXC_DCD_ITEM(72, MMDC_P0_BASE_ADDR + 0x020, 0x00005800)
+// MPODTCTRL
+MXC_DCD_ITEM(73, MMDC_P0_BASE_ADDR + 0x818, 0x00000007)
+MXC_DCD_ITEM(74, MMDC_P1_BASE_ADDR + 0x818, 0x00000007)
+//Read DQS Gating calibration
+MXC_DCD_ITEM(75, MMDC_P0_BASE_ADDR + 0x83c, 0x03200338)
+MXC_DCD_ITEM(76, MMDC_P0_BASE_ADDR + 0x840, 0x024A0314)
+MXC_DCD_ITEM(77, MMDC_P1_BASE_ADDR + 0x83c, 0x03280340)
+MXC_DCD_ITEM(78, MMDC_P1_BASE_ADDR + 0x840, 0x03280270)
+//Read calibration
+MXC_DCD_ITEM(79, MMDC_P0_BASE_ADDR + 0x848, 0x342C3232)
+MXC_DCD_ITEM(80, MMDC_P1_BASE_ADDR + 0x848, 0x342E283A)
+//Write calibration
+MXC_DCD_ITEM(81, MMDC_P0_BASE_ADDR + 0x850, 0x3E363C34)
+MXC_DCD_ITEM(82, MMDC_P1_BASE_ADDR + 0x850, 0x44344636)
+// MPWLDECTRLx
+MXC_DCD_ITEM(83, MMDC_P0_BASE_ADDR + 0x80c, 0x00190019)
+MXC_DCD_ITEM(84, MMDC_P0_BASE_ADDR + 0x810, 0x001F001D)
+MXC_DCD_ITEM(85, MMDC_P1_BASE_ADDR + 0x80c, 0x0015001F)
+MXC_DCD_ITEM(86, MMDC_P1_BASE_ADDR + 0x810, 0x00110026)
+// MPMUR0
+MXC_DCD_ITEM(87, MMDC_P0_BASE_ADDR + 0x8b8, 0x00000800)
+MXC_DCD_ITEM(88, MMDC_P1_BASE_ADDR + 0x8b8, 0x00000800)
+
+MXC_DCD_ITEM(89, MMDC_P0_BASE_ADDR + 0x01c, 0x00000000)
+MXC_DCD_ITEM(90, MMDC_P0_BASE_ADDR + 0x404, 0x00011006)
+
+
-MXC_DCD_ITEM(5, IOMUXC_BASE_ADDR + 0x518, 0x00000030)
-MXC_DCD_ITEM(6, IOMUXC_BASE_ADDR + 0x50c, 0x00000030)
-MXC_DCD_ITEM(7, IOMUXC_BASE_ADDR + 0x5b8, 0x00000030)
-MXC_DCD_ITEM(8, IOMUXC_BASE_ADDR + 0x5c0, 0x00000030)
-MXC_DCD_ITEM(9, IOMUXC_BASE_ADDR + 0x5ac, 0x00020030)
-MXC_DCD_ITEM(10, IOMUXC_BASE_ADDR + 0x5b4, 0x00020030)
-MXC_DCD_ITEM(11, IOMUXC_BASE_ADDR + 0x528, 0x00020030)
-MXC_DCD_ITEM(12, IOMUXC_BASE_ADDR + 0x520, 0x00020030)
-MXC_DCD_ITEM(13, IOMUXC_BASE_ADDR + 0x514, 0x00020030)
-MXC_DCD_ITEM(14, IOMUXC_BASE_ADDR + 0x510, 0x00020030)
-MXC_DCD_ITEM(15, IOMUXC_BASE_ADDR + 0x5bc, 0x00020030)
-MXC_DCD_ITEM(16, IOMUXC_BASE_ADDR + 0x5c4, 0x00020030)
+#else
-MXC_DCD_ITEM(17, IOMUXC_BASE_ADDR + 0x56c, 0x00020030)
-MXC_DCD_ITEM(18, IOMUXC_BASE_ADDR + 0x578, 0x00020030)
-MXC_DCD_ITEM(19, IOMUXC_BASE_ADDR + 0x588, 0x00020030)
-MXC_DCD_ITEM(20, IOMUXC_BASE_ADDR + 0x594, 0x00020030)
-MXC_DCD_ITEM(21, IOMUXC_BASE_ADDR + 0x57c, 0x00020030)
+
+
+
+// Ken modified Nanya 1G registers based on VAB-820 R.1
+
+#define VAB820_SDQSx 0x00000028
+MXC_DCD_ITEM(1, IOMUXC_BASE_ADDR + 0x5a8, VAB820_SDQSx)
+MXC_DCD_ITEM(2, IOMUXC_BASE_ADDR + 0x5b0, VAB820_SDQSx)
+MXC_DCD_ITEM(3, IOMUXC_BASE_ADDR + 0x524, VAB820_SDQSx)
+MXC_DCD_ITEM(4, IOMUXC_BASE_ADDR + 0x51c, VAB820_SDQSx)
+
+MXC_DCD_ITEM(5, IOMUXC_BASE_ADDR + 0x518, VAB820_SDQSx)
+MXC_DCD_ITEM(6, IOMUXC_BASE_ADDR + 0x50c, VAB820_SDQSx)
+MXC_DCD_ITEM(7, IOMUXC_BASE_ADDR + 0x5b8, VAB820_SDQSx)
+MXC_DCD_ITEM(8, IOMUXC_BASE_ADDR + 0x5c0, VAB820_SDQSx)
+
+#define VAB820_DQM 0x00000028
+MXC_DCD_ITEM(9, IOMUXC_BASE_ADDR + 0x5ac, VAB820_DQM)
+MXC_DCD_ITEM(10, IOMUXC_BASE_ADDR + 0x5b4, VAB820_DQM)
+MXC_DCD_ITEM(11, IOMUXC_BASE_ADDR + 0x528, VAB820_DQM)
+MXC_DCD_ITEM(12, IOMUXC_BASE_ADDR + 0x520, VAB820_DQM)
+
+MXC_DCD_ITEM(13, IOMUXC_BASE_ADDR + 0x514, VAB820_DQM)
+MXC_DCD_ITEM(14, IOMUXC_BASE_ADDR + 0x510, VAB820_DQM)
+MXC_DCD_ITEM(15, IOMUXC_BASE_ADDR + 0x5bc, VAB820_DQM)
+MXC_DCD_ITEM(16, IOMUXC_BASE_ADDR + 0x5c4, VAB820_DQM)
+
+MXC_DCD_ITEM(17, IOMUXC_BASE_ADDR + 0x56c, 0x00000028)
+MXC_DCD_ITEM(18, IOMUXC_BASE_ADDR + 0x578, 0x00000028)
+
+#define VAB820_SDCLKx 0x00000028
+MXC_DCD_ITEM(19, IOMUXC_BASE_ADDR + 0x588, VAB820_SDCLKx)
+MXC_DCD_ITEM(20, IOMUXC_BASE_ADDR + 0x594, VAB820_SDCLKx)
+
+// unknow register
+MXC_DCD_ITEM(21, IOMUXC_BASE_ADDR + 0x57c, 0x00000028)
MXC_DCD_ITEM(22, IOMUXC_BASE_ADDR + 0x590, 0x00003000)
MXC_DCD_ITEM(23, IOMUXC_BASE_ADDR + 0x598, 0x00003000)
MXC_DCD_ITEM(24, IOMUXC_BASE_ADDR + 0x58c, 0x00000000)
-MXC_DCD_ITEM(25, IOMUXC_BASE_ADDR + 0x59c, 0x00003030)
-MXC_DCD_ITEM(26, IOMUXC_BASE_ADDR + 0x5a0, 0x00003030)
-MXC_DCD_ITEM(27, IOMUXC_BASE_ADDR + 0x784, 0x00000030)
-MXC_DCD_ITEM(28, IOMUXC_BASE_ADDR + 0x788, 0x00000030)
+#define VAB820_SDODTx 0x00000028
+MXC_DCD_ITEM(25, IOMUXC_BASE_ADDR + 0x59c, VAB820_SDODTx)
+MXC_DCD_ITEM(26, IOMUXC_BASE_ADDR + 0x5a0, VAB820_SDODTx)
+
+#define VAB820_BxDS 0x28
+MXC_DCD_ITEM(27, IOMUXC_BASE_ADDR + 0x784, VAB820_BxDS)
+MXC_DCD_ITEM(28, IOMUXC_BASE_ADDR + 0x788, VAB820_BxDS)
+
+MXC_DCD_ITEM(29, IOMUXC_BASE_ADDR + 0x794, VAB820_BxDS)
+MXC_DCD_ITEM(30, IOMUXC_BASE_ADDR + 0x79c, VAB820_BxDS)
+MXC_DCD_ITEM(31, IOMUXC_BASE_ADDR + 0x7a0, VAB820_BxDS)
+MXC_DCD_ITEM(32, IOMUXC_BASE_ADDR + 0x7a4, VAB820_BxDS)
-MXC_DCD_ITEM(29, IOMUXC_BASE_ADDR + 0x794, 0x00000030)
-MXC_DCD_ITEM(30, IOMUXC_BASE_ADDR + 0x79c, 0x00000030)
-MXC_DCD_ITEM(31, IOMUXC_BASE_ADDR + 0x7a0, 0x00000030)
-MXC_DCD_ITEM(32, IOMUXC_BASE_ADDR + 0x7a4, 0x00000030)
+MXC_DCD_ITEM(33, IOMUXC_BASE_ADDR + 0x7a8, VAB820_BxDS)
+MXC_DCD_ITEM(34, IOMUXC_BASE_ADDR + 0x748, VAB820_BxDS)
-MXC_DCD_ITEM(33, IOMUXC_BASE_ADDR + 0x7a8, 0x00000030)
-MXC_DCD_ITEM(34, IOMUXC_BASE_ADDR + 0x748, 0x00000030)
-MXC_DCD_ITEM(35, IOMUXC_BASE_ADDR + 0x74c, 0x00000030)
+#define VAB820_ADD_CTL_DS 0x00000028
+MXC_DCD_ITEM(35, IOMUXC_BASE_ADDR + 0x74c, VAB820_ADD_CTL_DS)
MXC_DCD_ITEM(36, IOMUXC_BASE_ADDR + 0x750, 0x00020000)
MXC_DCD_ITEM(37, IOMUXC_BASE_ADDR + 0x758, 0x00000000)
MXC_DCD_ITEM(38, IOMUXC_BASE_ADDR + 0x774, 0x00020000)
-MXC_DCD_ITEM(39, IOMUXC_BASE_ADDR + 0x78c, 0x00000030)
+MXC_DCD_ITEM(39, IOMUXC_BASE_ADDR + 0x78c, VAB820_ADD_CTL_DS)
MXC_DCD_ITEM(40, IOMUXC_BASE_ADDR + 0x798, 0x000C0000)
MXC_DCD_ITEM(41, MMDC_P0_BASE_ADDR + 0x81c, 0x33333333)
@@ -118,56 +277,478 @@ MXC_DCD_ITEM(46, MMDC_P1_BASE_ADDR + 0x820, 0x33333333)
MXC_DCD_ITEM(47, MMDC_P1_BASE_ADDR + 0x824, 0x33333333)
MXC_DCD_ITEM(48, MMDC_P1_BASE_ADDR + 0x828, 0x33333333)
-MXC_DCD_ITEM(49, MMDC_P0_BASE_ADDR + 0x018, 0x00081740)
+MXC_DCD_ITEM(49, MMDC_P0_BASE_ADDR + 0x018, 0x00001740)
MXC_DCD_ITEM(50, MMDC_P0_BASE_ADDR + 0x01c, 0x00008000)
-MXC_DCD_ITEM(51, MMDC_P0_BASE_ADDR + 0x00c, 0x555A7975)
-MXC_DCD_ITEM(52, MMDC_P0_BASE_ADDR + 0x010, 0xFF538E64)
+MXC_DCD_ITEM(51, MMDC_P0_BASE_ADDR + 0x00c, 0x54597974)
+MXC_DCD_ITEM(52, MMDC_P0_BASE_ADDR + 0x010, 0xDB538F64)
MXC_DCD_ITEM(53, MMDC_P0_BASE_ADDR + 0x014, 0x01FF00DB)
MXC_DCD_ITEM(54, MMDC_P0_BASE_ADDR + 0x02c, 0x000026D2)
-
-MXC_DCD_ITEM(55, MMDC_P0_BASE_ADDR + 0x030, 0x005B0E21)
+// MDOR
+MXC_DCD_ITEM(55, MMDC_P0_BASE_ADDR + 0x030, 0x00591023)
MXC_DCD_ITEM(56, MMDC_P0_BASE_ADDR + 0x008, 0x09444040)
-MXC_DCD_ITEM(57, MMDC_P0_BASE_ADDR + 0x004, 0x00025576)
+// MDPDC
+MXC_DCD_ITEM(57, MMDC_P0_BASE_ADDR + 0x004, 0x00020036)
+// MDASP CS0_END
MXC_DCD_ITEM(58, MMDC_P0_BASE_ADDR + 0x040, 0x00000027)
+// MDCTL
MXC_DCD_ITEM(59, MMDC_P0_BASE_ADDR + 0x000, 0x831A0000)
+// MR2
+MXC_DCD_ITEM(60, MMDC_P0_BASE_ADDR + 0x01c, 0x02088032)
+MXC_DCD_ITEM(61, MMDC_P0_BASE_ADDR + 0x01c, 0x0288803A)
+// MR3
+MXC_DCD_ITEM(62, MMDC_P0_BASE_ADDR + 0x01c, 0x00008033)
+MXC_DCD_ITEM(63, MMDC_P0_BASE_ADDR + 0x01c, 0x0000803B)
+// MR1
+MXC_DCD_ITEM(64, MMDC_P0_BASE_ADDR + 0x01c, 0x00048031)
+MXC_DCD_ITEM(65, MMDC_P0_BASE_ADDR + 0x01c, 0x00048039)
+// MR0
+MXC_DCD_ITEM(66, MMDC_P0_BASE_ADDR + 0x01c, 0x09308030)
+MXC_DCD_ITEM(67, MMDC_P0_BASE_ADDR + 0x01c, 0x09308038)
+// ZQ calibration
+MXC_DCD_ITEM(68, MMDC_P0_BASE_ADDR + 0x01c, 0x04008040)
+MXC_DCD_ITEM(69, MMDC_P0_BASE_ADDR + 0x01c, 0x04008048)
+// ZQ
+MXC_DCD_ITEM(70, MMDC_P0_BASE_ADDR + 0x800, 0xA1380003)
+MXC_DCD_ITEM(71, MMDC_P1_BASE_ADDR + 0x800, 0xA1380003)
+//// final DDR setup
+// MMDC0_MDREF
+MXC_DCD_ITEM(72, MMDC_P0_BASE_ADDR + 0x020, 0x00007800)
+// MPODTCTRL
+MXC_DCD_ITEM(73, MMDC_P0_BASE_ADDR + 0x818, 0x00022227)
+MXC_DCD_ITEM(74, MMDC_P1_BASE_ADDR + 0x818, 0x00022227)
+//Read DQS Gating calibration
+MXC_DCD_ITEM(75, MMDC_P0_BASE_ADDR + 0x83c, 0x03340348)
+MXC_DCD_ITEM(76, MMDC_P0_BASE_ADDR + 0x840, 0x0236032C)
+MXC_DCD_ITEM(77, MMDC_P1_BASE_ADDR + 0x83c, 0x03340344)
+MXC_DCD_ITEM(78, MMDC_P1_BASE_ADDR + 0x840, 0x032C0300)
+//Read calibration
+MXC_DCD_ITEM(79, MMDC_P0_BASE_ADDR + 0x848, 0x32282E30)
+MXC_DCD_ITEM(80, MMDC_P1_BASE_ADDR + 0x848, 0x302A283A)
+//Write calibration
+MXC_DCD_ITEM(81, MMDC_P0_BASE_ADDR + 0x850, 0x3A363E38)
+MXC_DCD_ITEM(82, MMDC_P1_BASE_ADDR + 0x850, 0x40303E36)
+// MPWLDECTRLx
+MXC_DCD_ITEM(83, MMDC_P0_BASE_ADDR + 0x80c, 0x001C0013)
+MXC_DCD_ITEM(84, MMDC_P0_BASE_ADDR + 0x810, 0x0022001C)
+MXC_DCD_ITEM(85, MMDC_P1_BASE_ADDR + 0x80c, 0x00160025)
+MXC_DCD_ITEM(86, MMDC_P1_BASE_ADDR + 0x810, 0x000C001C)
+// MPMUR0
+MXC_DCD_ITEM(87, MMDC_P0_BASE_ADDR + 0x8b8, 0x00000800)
+MXC_DCD_ITEM(88, MMDC_P1_BASE_ADDR + 0x8b8, 0x00000800)
+
+MXC_DCD_ITEM(89, MMDC_P0_BASE_ADDR + 0x01c, 0x00000000)
+MXC_DCD_ITEM(90, MMDC_P0_BASE_ADDR + 0x404, 0x00011006)
+
+
+
+#endif
+
+#else
+
+
+#define ROM_API_TABLE_BASE_ADDR (0x000000C0)
+#define ROM_API_HWCNFG_SETUP_OFFSET (0x08)
+#define IRAM_FREE_START 0x00907000
+
+#define MXC_DCD_ITEM(i, addr, val) \
+ ldr r1, =val; \
+ ldr r0, =addr; \
+ str r1, [r0];
+
+
+
+.section ".text.flasheader", "x"
+origin:
+ b _start
+ .org CONFIG_FLASH_HEADER_OFFSET
+
+/* First IVT to copy the plugin that initializes the system into OCRAM */
+ivt_header: .long 0x402000D1 /*Tag=0xD1, Len=0x0020, Ver=0x40 */
+app_code_jump_v: .long IRAM_FREE_START + (plugin_start - origin) /* Plugin entry point, address after the second IVT table */
+reserv1: .long 0x0
+dcd_ptr: .long 0x0
+boot_data_ptr: .long IRAM_FREE_START + (boot_data - origin) /*0x00907420*/
+self_ptr: .long IRAM_FREE_START + (ivt_header - origin)
+app_code_csf: .long 0x0
+reserv2: .long 0x0
+
+boot_data: .long IRAM_FREE_START
+image_len: .long 16*1024 /* plugin can be upto 16KB in size */
+plugin: .long 0x1 /* Enable plugin flag */
+
+/* Second IVT to give entry point into the bootloader copied to DDR */
+ivt2_header: .long 0x402000D1 /*Tag=0xD1, Len=0x0020, Ver=0x40 */
+app2_code_jump_v: .long _start /* Entry point for uboot */
+reserv3: .long 0x0
+dcd2_ptr: .long 0x0
+boot_data2_ptr: .long boot_data2
+self_ptr2: .long ivt2_header
+app_code_csf2: .long 0x0
+reserv4: .long 0x0
+
+boot_data2: .long TEXT_BASE
+image_len2: .long _end_of_copy - TEXT_BASE + CONFIG_FLASH_HEADER_OFFSET
+plugin2: .long 0x0
+
+/* Here starts the plugin code */
+plugin_start:
+/* Save the return address and the function arguments */
+ push {r0-r4, lr}
+
+
+// CCM_BASE_ADDR = 0x020C4000
+//DDR clk
+ ldr r0, =CCM_BASE_ADDR
+ ldr r1, =0x00020324
+ str r1, [r0, #0x018]
+
+// vab820
+ ldr r0, =0x20e02fc
+ ldr r1, =0x05
+ str r1, [r0]
+ ldr r0, =0x20a0004
+ ldr r1, =0x00
+ str r1, [r0]
+ ldr r0, =0x20a0008
+ ldr r1, [r0]
+ and r1, #1
+ cmp r1, #0
+ bne Label_vab820_1
+
+
+
+// =============================================2GB start
+
+#define VAB820_SDQSx 0x00000028
+MXC_DCD_ITEM(1, IOMUXC_BASE_ADDR + 0x5a8, VAB820_SDQSx)
+MXC_DCD_ITEM(2, IOMUXC_BASE_ADDR + 0x5b0, VAB820_SDQSx)
+MXC_DCD_ITEM(3, IOMUXC_BASE_ADDR + 0x524, VAB820_SDQSx)
+MXC_DCD_ITEM(4, IOMUXC_BASE_ADDR + 0x51c, VAB820_SDQSx)
+MXC_DCD_ITEM(5, IOMUXC_BASE_ADDR + 0x518, VAB820_SDQSx)
+MXC_DCD_ITEM(6, IOMUXC_BASE_ADDR + 0x50c, VAB820_SDQSx)
+MXC_DCD_ITEM(7, IOMUXC_BASE_ADDR + 0x5b8, VAB820_SDQSx)
+MXC_DCD_ITEM(8, IOMUXC_BASE_ADDR + 0x5c0, VAB820_SDQSx)
+#define VAB820_DQM 0x00000028
+MXC_DCD_ITEM(9, IOMUXC_BASE_ADDR + 0x5ac, VAB820_DQM)
+MXC_DCD_ITEM(10, IOMUXC_BASE_ADDR + 0x5b4, VAB820_DQM)
+MXC_DCD_ITEM(11, IOMUXC_BASE_ADDR + 0x528, VAB820_DQM)
+MXC_DCD_ITEM(12, IOMUXC_BASE_ADDR + 0x520, VAB820_DQM)
+MXC_DCD_ITEM(13, IOMUXC_BASE_ADDR + 0x514, VAB820_DQM)
+MXC_DCD_ITEM(14, IOMUXC_BASE_ADDR + 0x510, VAB820_DQM)
+MXC_DCD_ITEM(15, IOMUXC_BASE_ADDR + 0x5bc, VAB820_DQM)
+MXC_DCD_ITEM(16, IOMUXC_BASE_ADDR + 0x5c4, VAB820_DQM)
+// CAS
+MXC_DCD_ITEM(17, IOMUXC_BASE_ADDR + 0x56c, 0x00000028)
+// RAS
+MXC_DCD_ITEM(18, IOMUXC_BASE_ADDR + 0x578, 0x00000028)
+#define VAB820_SDCLKx 0x00000028
+MXC_DCD_ITEM(19, IOMUXC_BASE_ADDR + 0x588, VAB820_SDCLKx)
+MXC_DCD_ITEM(20, IOMUXC_BASE_ADDR + 0x594, VAB820_SDCLKx)
+MXC_DCD_ITEM(21, IOMUXC_BASE_ADDR + 0x57c, 0x00000028)
+MXC_DCD_ITEM(22, IOMUXC_BASE_ADDR + 0x590, 0x00003000)
+MXC_DCD_ITEM(23, IOMUXC_BASE_ADDR + 0x598, 0x00003000)
+MXC_DCD_ITEM(24, IOMUXC_BASE_ADDR + 0x58c, 0x00000000)
+#define VAB820_SDODTx 0x00000028
+MXC_DCD_ITEM(25, IOMUXC_BASE_ADDR + 0x59c, VAB820_SDODTx)
+MXC_DCD_ITEM(26, IOMUXC_BASE_ADDR + 0x5a0, VAB820_SDODTx)
+#define VAB820_BxDS 0x28
+MXC_DCD_ITEM(27, IOMUXC_BASE_ADDR + 0x784, VAB820_BxDS)
+MXC_DCD_ITEM(28, IOMUXC_BASE_ADDR + 0x788, VAB820_BxDS)
+MXC_DCD_ITEM(29, IOMUXC_BASE_ADDR + 0x794, VAB820_BxDS)
+MXC_DCD_ITEM(30, IOMUXC_BASE_ADDR + 0x79c, VAB820_BxDS)
+MXC_DCD_ITEM(31, IOMUXC_BASE_ADDR + 0x7a0, VAB820_BxDS)
+MXC_DCD_ITEM(32, IOMUXC_BASE_ADDR + 0x7a4, VAB820_BxDS)
+MXC_DCD_ITEM(33, IOMUXC_BASE_ADDR + 0x7a8, VAB820_BxDS)
+MXC_DCD_ITEM(34, IOMUXC_BASE_ADDR + 0x748, VAB820_BxDS)
+#define VAB820_ADD_CTL_DS 0x00000028
+MXC_DCD_ITEM(35, IOMUXC_BASE_ADDR + 0x74c, VAB820_ADD_CTL_DS)
+MXC_DCD_ITEM(36, IOMUXC_BASE_ADDR + 0x750, 0x00020000)
+MXC_DCD_ITEM(37, IOMUXC_BASE_ADDR + 0x758, 0x00000000)
+MXC_DCD_ITEM(38, IOMUXC_BASE_ADDR + 0x774, 0x00020000)
+MXC_DCD_ITEM(39, IOMUXC_BASE_ADDR + 0x78c, VAB820_ADD_CTL_DS)
+MXC_DCD_ITEM(40, IOMUXC_BASE_ADDR + 0x798, 0x000C0000)
+
+MXC_DCD_ITEM(41, MMDC_P0_BASE_ADDR + 0x81c, 0x33333333)
+MXC_DCD_ITEM(42, MMDC_P0_BASE_ADDR + 0x820, 0x33333333)
+MXC_DCD_ITEM(43, MMDC_P0_BASE_ADDR + 0x824, 0x33333333)
+MXC_DCD_ITEM(44, MMDC_P0_BASE_ADDR + 0x828, 0x33333333)
+MXC_DCD_ITEM(45, MMDC_P1_BASE_ADDR + 0x81c, 0x33333333)
+MXC_DCD_ITEM(46, MMDC_P1_BASE_ADDR + 0x820, 0x33333333)
+MXC_DCD_ITEM(47, MMDC_P1_BASE_ADDR + 0x824, 0x33333333)
+MXC_DCD_ITEM(48, MMDC_P1_BASE_ADDR + 0x828, 0x33333333)
+// MDMISC
+MXC_DCD_ITEM(49, MMDC_P0_BASE_ADDR + 0x018, 0x00081740)
+
+MXC_DCD_ITEM(50, MMDC_P0_BASE_ADDR + 0x01c, 0x00008000)
+// MDCFG0
+MXC_DCD_ITEM(51, MMDC_P0_BASE_ADDR + 0x00c, 0x898E7955)
+// MDCFG1
+MXC_DCD_ITEM(52, MMDC_P0_BASE_ADDR + 0x010, 0xFF328F64)
+// MDCFG2
+MXC_DCD_ITEM(53, MMDC_P0_BASE_ADDR + 0x014, 0x01FF00DB)
+MXC_DCD_ITEM(54, MMDC_P0_BASE_ADDR + 0x02c, 0x000026D2)
+// MDOR
+MXC_DCD_ITEM(55, MMDC_P0_BASE_ADDR + 0x030, 0x008E1023)
+MXC_DCD_ITEM(56, MMDC_P0_BASE_ADDR + 0x008, 0x09444040)
+// MDPDC
+MXC_DCD_ITEM(57, MMDC_P0_BASE_ADDR + 0x004, 0x00020036)
+// MDASP
+MXC_DCD_ITEM(58, MMDC_P0_BASE_ADDR + 0x040, 0x00000047)
+// MDCTL
+MXC_DCD_ITEM(59, MMDC_P0_BASE_ADDR + 0x000, 0x841A0000)
+// MR2
MXC_DCD_ITEM(60, MMDC_P0_BASE_ADDR + 0x01c, 0x04088032)
MXC_DCD_ITEM(61, MMDC_P0_BASE_ADDR + 0x01c, 0x0408803A)
+// MR3
MXC_DCD_ITEM(62, MMDC_P0_BASE_ADDR + 0x01c, 0x00008033)
MXC_DCD_ITEM(63, MMDC_P0_BASE_ADDR + 0x01c, 0x0000803B)
+// MR1
MXC_DCD_ITEM(64, MMDC_P0_BASE_ADDR + 0x01c, 0x00428031)
MXC_DCD_ITEM(65, MMDC_P0_BASE_ADDR + 0x01c, 0x00428039)
+// MR0
MXC_DCD_ITEM(66, MMDC_P0_BASE_ADDR + 0x01c, 0x09408030)
MXC_DCD_ITEM(67, MMDC_P0_BASE_ADDR + 0x01c, 0x09408038)
-
+// ZQ calibration
MXC_DCD_ITEM(68, MMDC_P0_BASE_ADDR + 0x01c, 0x04008040)
MXC_DCD_ITEM(69, MMDC_P0_BASE_ADDR + 0x01c, 0x04008048)
+// ZQ
MXC_DCD_ITEM(70, MMDC_P0_BASE_ADDR + 0x800, 0xA1380003)
MXC_DCD_ITEM(71, MMDC_P1_BASE_ADDR + 0x800, 0xA1380003)
+//// final DDR setup
+// MMDC0_MDREF
MXC_DCD_ITEM(72, MMDC_P0_BASE_ADDR + 0x020, 0x00005800)
+// MPODTCTRL
MXC_DCD_ITEM(73, MMDC_P0_BASE_ADDR + 0x818, 0x00000007)
MXC_DCD_ITEM(74, MMDC_P1_BASE_ADDR + 0x818, 0x00000007)
+//Read DQS Gating calibration
+MXC_DCD_ITEM(75, MMDC_P0_BASE_ADDR + 0x83c, 0x03200338)
+MXC_DCD_ITEM(76, MMDC_P0_BASE_ADDR + 0x840, 0x024A0314)
+MXC_DCD_ITEM(77, MMDC_P1_BASE_ADDR + 0x83c, 0x03280340)
+MXC_DCD_ITEM(78, MMDC_P1_BASE_ADDR + 0x840, 0x03280270)
+//Read calibration
+MXC_DCD_ITEM(79, MMDC_P0_BASE_ADDR + 0x848, 0x342C3232)
+MXC_DCD_ITEM(80, MMDC_P1_BASE_ADDR + 0x848, 0x342E283A)
+//Write calibration
+MXC_DCD_ITEM(81, MMDC_P0_BASE_ADDR + 0x850, 0x3E363C34)
+MXC_DCD_ITEM(82, MMDC_P1_BASE_ADDR + 0x850, 0x44344636)
+// MPWLDECTRLx
+MXC_DCD_ITEM(83, MMDC_P0_BASE_ADDR + 0x80c, 0x00190019)
+MXC_DCD_ITEM(84, MMDC_P0_BASE_ADDR + 0x810, 0x001F001D)
+MXC_DCD_ITEM(85, MMDC_P1_BASE_ADDR + 0x80c, 0x0015001F)
+MXC_DCD_ITEM(86, MMDC_P1_BASE_ADDR + 0x810, 0x00110026)
+// MPMUR0
+MXC_DCD_ITEM(87, MMDC_P0_BASE_ADDR + 0x8b8, 0x00000800)
+MXC_DCD_ITEM(88, MMDC_P1_BASE_ADDR + 0x8b8, 0x00000800)
+
+MXC_DCD_ITEM(89, MMDC_P0_BASE_ADDR + 0x01c, 0x00000000)
+MXC_DCD_ITEM(90, MMDC_P0_BASE_ADDR + 0x404, 0x00011006)
+
+// =============================================2GB end
+ b Label_vab820_2
+
+
+
+
+Label_vab820_1:
+// =============================================1GB start
+// Ken modified Nanya 1G registers based on VAB-820 R.1
+
+#define VAB820_SDQSx 0x00000028
+MXC_DCD_ITEM(1, IOMUXC_BASE_ADDR + 0x5a8, VAB820_SDQSx)
+MXC_DCD_ITEM(2, IOMUXC_BASE_ADDR + 0x5b0, VAB820_SDQSx)
+MXC_DCD_ITEM(3, IOMUXC_BASE_ADDR + 0x524, VAB820_SDQSx)
+MXC_DCD_ITEM(4, IOMUXC_BASE_ADDR + 0x51c, VAB820_SDQSx)
+
+MXC_DCD_ITEM(5, IOMUXC_BASE_ADDR + 0x518, VAB820_SDQSx)
+MXC_DCD_ITEM(6, IOMUXC_BASE_ADDR + 0x50c, VAB820_SDQSx)
+MXC_DCD_ITEM(7, IOMUXC_BASE_ADDR + 0x5b8, VAB820_SDQSx)
+MXC_DCD_ITEM(8, IOMUXC_BASE_ADDR + 0x5c0, VAB820_SDQSx)
+
+#define VAB820_DQM 0x00000028
+MXC_DCD_ITEM(9, IOMUXC_BASE_ADDR + 0x5ac, VAB820_DQM)
+MXC_DCD_ITEM(10, IOMUXC_BASE_ADDR + 0x5b4, VAB820_DQM)
+MXC_DCD_ITEM(11, IOMUXC_BASE_ADDR + 0x528, VAB820_DQM)
+MXC_DCD_ITEM(12, IOMUXC_BASE_ADDR + 0x520, VAB820_DQM)
+
+MXC_DCD_ITEM(13, IOMUXC_BASE_ADDR + 0x514, VAB820_DQM)
+MXC_DCD_ITEM(14, IOMUXC_BASE_ADDR + 0x510, VAB820_DQM)
+MXC_DCD_ITEM(15, IOMUXC_BASE_ADDR + 0x5bc, VAB820_DQM)
+MXC_DCD_ITEM(16, IOMUXC_BASE_ADDR + 0x5c4, VAB820_DQM)
+
+MXC_DCD_ITEM(17, IOMUXC_BASE_ADDR + 0x56c, 0x00000028)
+MXC_DCD_ITEM(18, IOMUXC_BASE_ADDR + 0x578, 0x00000028)
+
+#define VAB820_SDCLKx 0x00000028
+MXC_DCD_ITEM(19, IOMUXC_BASE_ADDR + 0x588, VAB820_SDCLKx)
+MXC_DCD_ITEM(20, IOMUXC_BASE_ADDR + 0x594, VAB820_SDCLKx)
+
+// unknow register
+MXC_DCD_ITEM(21, IOMUXC_BASE_ADDR + 0x57c, 0x00000028)
+MXC_DCD_ITEM(22, IOMUXC_BASE_ADDR + 0x590, 0x00003000)
+MXC_DCD_ITEM(23, IOMUXC_BASE_ADDR + 0x598, 0x00003000)
+MXC_DCD_ITEM(24, IOMUXC_BASE_ADDR + 0x58c, 0x00000000)
+
+#define VAB820_SDODTx 0x00000028
+MXC_DCD_ITEM(25, IOMUXC_BASE_ADDR + 0x59c, VAB820_SDODTx)
+MXC_DCD_ITEM(26, IOMUXC_BASE_ADDR + 0x5a0, VAB820_SDODTx)
+
+#define VAB820_BxDS 0x28
+MXC_DCD_ITEM(27, IOMUXC_BASE_ADDR + 0x784, VAB820_BxDS)
+MXC_DCD_ITEM(28, IOMUXC_BASE_ADDR + 0x788, VAB820_BxDS)
+
+MXC_DCD_ITEM(29, IOMUXC_BASE_ADDR + 0x794, VAB820_BxDS)
+MXC_DCD_ITEM(30, IOMUXC_BASE_ADDR + 0x79c, VAB820_BxDS)
+MXC_DCD_ITEM(31, IOMUXC_BASE_ADDR + 0x7a0, VAB820_BxDS)
+MXC_DCD_ITEM(32, IOMUXC_BASE_ADDR + 0x7a4, VAB820_BxDS)
+
+MXC_DCD_ITEM(33, IOMUXC_BASE_ADDR + 0x7a8, VAB820_BxDS)
+MXC_DCD_ITEM(34, IOMUXC_BASE_ADDR + 0x748, VAB820_BxDS)
+
+#define VAB820_ADD_CTL_DS 0x00000028
+MXC_DCD_ITEM(35, IOMUXC_BASE_ADDR + 0x74c, VAB820_ADD_CTL_DS)
+MXC_DCD_ITEM(36, IOMUXC_BASE_ADDR + 0x750, 0x00020000)
-MXC_DCD_ITEM(75, MMDC_P0_BASE_ADDR + 0x83c, 0x434B0350)
-MXC_DCD_ITEM(76, MMDC_P0_BASE_ADDR + 0x840, 0x034C0359)
-MXC_DCD_ITEM(77, MMDC_P1_BASE_ADDR + 0x83c, 0x434B0350)
-MXC_DCD_ITEM(78, MMDC_P1_BASE_ADDR + 0x840, 0x03650348)
-MXC_DCD_ITEM(79, MMDC_P0_BASE_ADDR + 0x848, 0x4436383B)
-MXC_DCD_ITEM(80, MMDC_P1_BASE_ADDR + 0x848, 0x39393341)
-MXC_DCD_ITEM(81, MMDC_P0_BASE_ADDR + 0x850, 0x35373933)
-MXC_DCD_ITEM(82, MMDC_P1_BASE_ADDR + 0x850, 0x48254A36)
+MXC_DCD_ITEM(37, IOMUXC_BASE_ADDR + 0x758, 0x00000000)
+MXC_DCD_ITEM(38, IOMUXC_BASE_ADDR + 0x774, 0x00020000)
+MXC_DCD_ITEM(39, IOMUXC_BASE_ADDR + 0x78c, VAB820_ADD_CTL_DS)
+MXC_DCD_ITEM(40, IOMUXC_BASE_ADDR + 0x798, 0x000C0000)
+
+MXC_DCD_ITEM(41, MMDC_P0_BASE_ADDR + 0x81c, 0x33333333)
+MXC_DCD_ITEM(42, MMDC_P0_BASE_ADDR + 0x820, 0x33333333)
+MXC_DCD_ITEM(43, MMDC_P0_BASE_ADDR + 0x824, 0x33333333)
+MXC_DCD_ITEM(44, MMDC_P0_BASE_ADDR + 0x828, 0x33333333)
-MXC_DCD_ITEM(83, MMDC_P0_BASE_ADDR + 0x80c, 0x001F001F)
-MXC_DCD_ITEM(84, MMDC_P0_BASE_ADDR + 0x810, 0x001F001F)
+MXC_DCD_ITEM(45, MMDC_P1_BASE_ADDR + 0x81c, 0x33333333)
+MXC_DCD_ITEM(46, MMDC_P1_BASE_ADDR + 0x820, 0x33333333)
+MXC_DCD_ITEM(47, MMDC_P1_BASE_ADDR + 0x824, 0x33333333)
+MXC_DCD_ITEM(48, MMDC_P1_BASE_ADDR + 0x828, 0x33333333)
-MXC_DCD_ITEM(85, MMDC_P1_BASE_ADDR + 0x80c, 0x00440044)
-MXC_DCD_ITEM(86, MMDC_P1_BASE_ADDR + 0x810, 0x00440044)
+MXC_DCD_ITEM(49, MMDC_P0_BASE_ADDR + 0x018, 0x00001740)
+MXC_DCD_ITEM(50, MMDC_P0_BASE_ADDR + 0x01c, 0x00008000)
+MXC_DCD_ITEM(51, MMDC_P0_BASE_ADDR + 0x00c, 0x54597974)
+MXC_DCD_ITEM(52, MMDC_P0_BASE_ADDR + 0x010, 0xDB538F64)
+MXC_DCD_ITEM(53, MMDC_P0_BASE_ADDR + 0x014, 0x01FF00DB)
+MXC_DCD_ITEM(54, MMDC_P0_BASE_ADDR + 0x02c, 0x000026D2)
+// MDOR
+MXC_DCD_ITEM(55, MMDC_P0_BASE_ADDR + 0x030, 0x00591023)
+MXC_DCD_ITEM(56, MMDC_P0_BASE_ADDR + 0x008, 0x09444040)
+// MDPDC
+MXC_DCD_ITEM(57, MMDC_P0_BASE_ADDR + 0x004, 0x00020036)
+// MDASP CS0_END
+MXC_DCD_ITEM(58, MMDC_P0_BASE_ADDR + 0x040, 0x00000027)
+// MDCTL
+MXC_DCD_ITEM(59, MMDC_P0_BASE_ADDR + 0x000, 0x831A0000)
+// MR2
+MXC_DCD_ITEM(60, MMDC_P0_BASE_ADDR + 0x01c, 0x02088032)
+MXC_DCD_ITEM(61, MMDC_P0_BASE_ADDR + 0x01c, 0x0288803A)
+// MR3
+MXC_DCD_ITEM(62, MMDC_P0_BASE_ADDR + 0x01c, 0x00008033)
+MXC_DCD_ITEM(63, MMDC_P0_BASE_ADDR + 0x01c, 0x0000803B)
+// MR1
+MXC_DCD_ITEM(64, MMDC_P0_BASE_ADDR + 0x01c, 0x00048031)
+MXC_DCD_ITEM(65, MMDC_P0_BASE_ADDR + 0x01c, 0x00048039)
+// MR0
+MXC_DCD_ITEM(66, MMDC_P0_BASE_ADDR + 0x01c, 0x09308030)
+MXC_DCD_ITEM(67, MMDC_P0_BASE_ADDR + 0x01c, 0x09308038)
+// ZQ calibration
+MXC_DCD_ITEM(68, MMDC_P0_BASE_ADDR + 0x01c, 0x04008040)
+MXC_DCD_ITEM(69, MMDC_P0_BASE_ADDR + 0x01c, 0x04008048)
+// ZQ
+MXC_DCD_ITEM(70, MMDC_P0_BASE_ADDR + 0x800, 0xA1380003)
+MXC_DCD_ITEM(71, MMDC_P1_BASE_ADDR + 0x800, 0xA1380003)
+//// final DDR setup
+// MMDC0_MDREF
+MXC_DCD_ITEM(72, MMDC_P0_BASE_ADDR + 0x020, 0x00007800)
+// MPODTCTRL
+MXC_DCD_ITEM(73, MMDC_P0_BASE_ADDR + 0x818, 0x00022227)
+MXC_DCD_ITEM(74, MMDC_P1_BASE_ADDR + 0x818, 0x00022227)
+//Read DQS Gating calibration
+MXC_DCD_ITEM(75, MMDC_P0_BASE_ADDR + 0x83c, 0x03340348)
+MXC_DCD_ITEM(76, MMDC_P0_BASE_ADDR + 0x840, 0x0236032C)
+MXC_DCD_ITEM(77, MMDC_P1_BASE_ADDR + 0x83c, 0x03340344)
+MXC_DCD_ITEM(78, MMDC_P1_BASE_ADDR + 0x840, 0x032C0300)
+//Read calibration
+MXC_DCD_ITEM(79, MMDC_P0_BASE_ADDR + 0x848, 0x32282E30)
+MXC_DCD_ITEM(80, MMDC_P1_BASE_ADDR + 0x848, 0x302A283A)
+//Write calibration
+MXC_DCD_ITEM(81, MMDC_P0_BASE_ADDR + 0x850, 0x3A363E38)
+MXC_DCD_ITEM(82, MMDC_P1_BASE_ADDR + 0x850, 0x40303E36)
+// MPWLDECTRLx
+MXC_DCD_ITEM(83, MMDC_P0_BASE_ADDR + 0x80c, 0x001C0013)
+MXC_DCD_ITEM(84, MMDC_P0_BASE_ADDR + 0x810, 0x0022001C)
+MXC_DCD_ITEM(85, MMDC_P1_BASE_ADDR + 0x80c, 0x00160025)
+MXC_DCD_ITEM(86, MMDC_P1_BASE_ADDR + 0x810, 0x000C001C)
+// MPMUR0
MXC_DCD_ITEM(87, MMDC_P0_BASE_ADDR + 0x8b8, 0x00000800)
MXC_DCD_ITEM(88, MMDC_P1_BASE_ADDR + 0x8b8, 0x00000800)
MXC_DCD_ITEM(89, MMDC_P0_BASE_ADDR + 0x01c, 0x00000000)
MXC_DCD_ITEM(90, MMDC_P0_BASE_ADDR + 0x404, 0x00011006)
+// =============================================1GB end
+
+
+
+
+
+
+Label_vab820_2:
+/*
+ The following is to fill in those arguments for this ROM function
+ pu_irom_hwcnfg_setup(void **start, size_t *bytes, const void *boot_data)
+
+ This function is used to copy data from the storage media into DDR.
+
+ start - Initial (possibly partial) image load address on entry. Final
+ image load address on exit.
+ bytes - Initial (possibly partial) image size on entry. Final image size
+ on exit.
+ boot_data - Initial @ref ivt Boot Data load address.
+*/
+ adr r0, DDR_DEST_ADDR
+ adr r1, COPY_SIZE
+ adr r2, BOOT_DATA
+
+/*
+ * check the _pu_irom_api_table for the address
+ * pu_irom_hwcnfg_setup is in 0x1fb5 ERIC : < what is the address in Rigel >
+ */
+before_calling_rom___pu_irom_hwcnfg_setup:
+ ldr r3, =ROM_API_TABLE_BASE_ADDR
+ ldr r4, [r3, #ROM_API_HWCNFG_SETUP_OFFSET]
+ blx r4
+after_calling_rom___pu_irom_hwcnfg_setup:
+
+/* To return to ROM from plugin, we need to fill in these argument.
+ * Here is what need to do:
+ * Need to construct the paramters for this function before return to ROM:
+ * plugin_download(void **start, size_t *bytes, UINT32 *ivt_offset)
+ */
+ pop {r0-r4, lr}
+ ldr r5, DDR_DEST_ADDR
+ str r5, [r0]
+ ldr r5, COPY_SIZE
+ str r5, [r1]
+ mov r5, #0x400 /* Point to the second IVT table at offset 0x42C */
+ add r5, r5, #0x2C
+ str r5, [r2]
+ mov r0, #1
+
+ bx lr /* return back to ROM code */
+
+DDR_DEST_ADDR: .word TEXT_BASE
+COPY_SIZE: .word _end_of_copy - TEXT_BASE + CONFIG_FLASH_HEADER_OFFSET
+BOOT_DATA: .word TEXT_BASE
+ .word _end_of_copy - TEXT_BASE + CONFIG_FLASH_HEADER_OFFSET
+ .word 0
+/*********************************************************************/
+
+
+
#endif
+
+#endif
+
diff --git a/board/freescale/mx6q_sabrelite/mx6q_sabrelite.c b/board/freescale/mx6q_sabrelite/mx6q_sabrelite.c
index 1b0679d..dbc65d8 100644
--- a/board/freescale/mx6q_sabrelite/mx6q_sabrelite.c
+++ b/board/freescale/mx6q_sabrelite/mx6q_sabrelite.c
@@ -99,10 +99,17 @@ static inline void setup_boot_device(void)
boot_dev = SATA_BOOT;
break;
case 0x3:
+// steven
+ if (bt_mem_type)
+ boot_dev = I2C_BOOT;
+ else
+ boot_dev = SPI_NOR_BOOT;
+#if 0
if (bt_mem_type)
boot_dev = SPI_NOR_BOOT;
else
boot_dev = I2C_BOOT;
+#endif
break;
case 0x4:
case 0x5:
@@ -174,8 +181,13 @@ void board_mmu_init(void)
int dram_init(void)
{
+ // Steven
+ ulong nRamSize = (1u * 1024 * 1024 * 1024);
+ u32 reg = readl(GPIO2_BASE_ADDR + GPIO_PSR);
+
+ if (!(reg&0x01)) { nRamSize = (2u * 1024 * 1024 * 1024); }
gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
- gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
+ gd->bd->bi_dram[0].size = nRamSize;
return 0;
}
@@ -314,7 +326,8 @@ int board_eth_init(bd_t *bis)
#ifdef CONFIG_CMD_MMC
struct fsl_esdhc_cfg usdhc_cfg[2] = {
- {USDHC3_BASE_ADDR, 1, 1, 1},
+// steven: USDHC3_BASE_ADDR -> USDHC2_BASE_ADDR
+ {USDHC2_BASE_ADDR, 1, 1, 1},
{USDHC4_BASE_ADDR, 1, 1, 1},
};
@@ -352,6 +365,11 @@ iomux_v3_cfg_t mx6q_usdhc4_pads[] = {
MX6Q_PAD_SD4_DAT1__USDHC4_DAT1,
MX6Q_PAD_SD4_DAT2__USDHC4_DAT2,
MX6Q_PAD_SD4_DAT3__USDHC4_DAT3,
+// steven
+ MX6Q_PAD_SD4_DAT4__USDHC4_DAT4,
+ MX6Q_PAD_SD4_DAT5__USDHC4_DAT5,
+ MX6Q_PAD_SD4_DAT6__USDHC4_DAT6,
+ MX6Q_PAD_SD4_DAT7__USDHC4_DAT7,
};
int usdhc_gpio_init(bd_t *bis)
@@ -362,10 +380,11 @@ int usdhc_gpio_init(bd_t *bis)
for (index = 0; index < CONFIG_SYS_FSL_USDHC_NUM; index++) {
switch (index) {
case 0:
- mxc_iomux_v3_setup_multiple_pads(mx6q_usdhc3_pads,
+ // steven: mx6q_usdhc3_pads -> mx6q_usdhc2_pads
+ mxc_iomux_v3_setup_multiple_pads(mx6q_usdhc2_pads,
sizeof
- (mx6q_usdhc3_pads) /
- sizeof(mx6q_usdhc3_pads
+ (mx6q_usdhc2_pads) /
+ sizeof(mx6q_usdhc2_pads
[0]));
break;
case 1:
@@ -434,6 +453,9 @@ int board_init(void)
#ifdef CONFIG_I2C_MXC
setup_i2c(CONFIG_SYS_I2C_PORT);
#endif
+// steven
+ /* Switch to 1GHZ */
+ clk_config(CONFIG_REF_CLK_FREQ, 1000, CPU_CLK);
return 0;
}
@@ -489,8 +511,8 @@ iomux_v3_cfg_t enet_pads[] = {
MX6Q_PAD_RGMII_RD3__GPIO_6_29,
/* pin 33 - 1 - (CLK125_EN) 125Mhz clockout enabled */
MX6Q_PAD_RGMII_RX_CTL__GPIO_6_24,
- MX6Q_PAD_GPIO_0__CCM_CLKO,
- MX6Q_PAD_GPIO_3__CCM_CLKO2,
+ //MX6Q_PAD_GPIO_0__CCM_CLKO,
+ //MX6Q_PAD_GPIO_3__CCM_CLKO2,
MX6Q_PAD_ENET_REF_CLK__ENET_TX_CLK,
};
@@ -550,12 +572,22 @@ int mx6_rgmii_rework(char *devname, int phy_addr)
void enet_board_init(void)
{
+ // steven: vab820 enet's reset pin is the same as sabresd
+ unsigned int reg;
iomux_v3_cfg_t enet_reset =
+ (_MX6Q_PAD_ENET_CRS_DV__GPIO_1_25 & ~MUX_PAD_CTRL_MASK)
+ | MUX_PAD_CTRL(0x88);
+
+/* iomux_v3_cfg_t enet_reset =
(MX6Q_PAD_EIM_D23__GPIO_3_23 &
~MUX_PAD_CTRL_MASK) | MUX_PAD_CTRL(0x48);
+*/
+
+ /* phy reset: gpio1-25 */
+ // gpio1_25 to low
+ set_gpio_output_val(GPIO1_BASE_ADDR, (1 << 25), 0);
+ //set_gpio_output_val(GPIO3_BASE_ADDR, (1 << 23), 0);
- /* phy reset: gpio3-23 */
- set_gpio_output_val(GPIO3_BASE_ADDR, (1 << 23), 0);
set_gpio_output_val(GPIO6_BASE_ADDR, (1 << 30),
(CONFIG_FEC0_PHY_ADDR >> 2));
set_gpio_output_val(GPIO6_BASE_ADDR, (1 << 25), 1);
@@ -567,14 +599,20 @@ void enet_board_init(void)
set_gpio_output_val(GPIO6_BASE_ADDR, (1 << 24), 1);
udelay(500);
- set_gpio_output_val(GPIO3_BASE_ADDR, (1 << 23), 1);
+
+ // gpio1_25 to high
+ set_gpio_output_val(GPIO1_BASE_ADDR, (1 << 25), 1);
+ //set_gpio_output_val(GPIO3_BASE_ADDR, (1 << 23), 1);
+
mxc_iomux_v3_setup_multiple_pads(enet_pads_final,
ARRAY_SIZE(enet_pads_final));
}
int checkboard(void)
{
- printf("Board: MX6Q-SABRELITE:[ ");
+ //Steven
+ //printf("Board: MX6Q-SABRELITE:[ ");
+ printf("Board: MX6Q-VAB820:[ ");
switch (__REG(SRC_BASE_ADDR + 0x8)) {
case 0x0001:
diff --git a/drivers/net/mxc_fec.c b/drivers/net/mxc_fec.c
index 212abb7..ce7f617 100644
--- a/drivers/net/mxc_fec.c
+++ b/drivers/net/mxc_fec.c
@@ -286,6 +286,9 @@ static int mxc_fec_mii_read(char *devname, unsigned char addr,
return -1;
info = dev->priv;
fecp = (fec_t *) (info->iobase);
+// steven
+ fec_reset(dev);
+ mxc_fec_mii_init(fecp);
return __fec_mii_read(fecp, addr, reg, value);
}
@@ -299,6 +302,9 @@ static int mxc_fec_mii_write(char *devname, unsigned char addr,
return -1;
info = dev->priv;
fecp = (fec_t *) (info->iobase);
+// steven
+ fec_reset(dev);
+ mxc_fec_mii_init(fecp);
return __fec_mii_write(fecp, addr, reg, value);
}
diff --git a/include/configs/mx6q_sabrelite.h b/include/configs/mx6q_sabrelite.h
index b692c87..99a9fd2 100644
--- a/include/configs/mx6q_sabrelite.h
+++ b/include/configs/mx6q_sabrelite.h
@@ -24,6 +24,10 @@
#include <asm/arch/mx6.h>
+// steven
+//#define VAB820_FACTORY
+
+
/* High Level Configuration Options */
#define CONFIG_ARMV7 /* This is armv7 Cortex-A9 CPU core */
#define CONFIG_MXC
@@ -115,37 +119,45 @@
#define CONFIG_LOADADDR 0x10800000 /* loadaddr env var */
#define CONFIG_RD_LOADADDR 0x11000000
+// Steven
+#ifdef VAB820_FACTORY
#define CONFIG_EXTRA_ENV_SETTINGS \
"netdev=eth0\0" \
"ethprime=FEC0\0" \
"ethaddr=00:01:02:03:04:05\0" \
"uboot=u-boot.bin\0" \
"kernel=uImage\0" \
- "bootargs=console=ttymxc1,115200\0" \
- "bootargs_base=setenv bootargs console=ttymxc1,115200\0" \
- "bootargs_nfs=setenv bootargs ${bootargs} root=/dev/nfs " \
- "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp " \
- "video=mxcfb0:dev=ldb,LDB-XGA,if=RGB666\0" \
- "bootcmd_net=dhcp; run bootargs_base bootargs_nfs;bootm\0" \
- "bootargs_mmc=setenv bootargs ${bootargs} " \
- "root=/dev/mmcblk0p1 rootwait rw " \
- "video=mxcfb0:dev=ldb,LDB-XGA,if=RGB666 " \
- "video=mxcfb0:dev=hdmi,1920x1080M@60,if=RGB24\0" \
- "bootcmd_mmc=run bootargs_base bootargs_mmc;mmc dev 1;" \
- "mmc read ${loadaddr} 0x800 0x2000;bootm\0" \
- "bootcmd=run bootcmd_mmc\0" \
- "clearenv=sf probe 1 && sf erase 0xc0000 0x2000 && " \
- "echo restored environment to factory default\0" \
- "upgradeu=for disk in 0 1 ; do mmc dev ${disk} ;" \
- "for fs in fat ext2 ; do " \
- "${fs}load mmc ${disk}:1 10008000 " \
- "/6q_upgrade && " \
- "source 10008000 ; " \
- "done ; " \
- "done\0" \
- "bootfile=_BOOT_FILE_PATH_IN_TFTP_\0" \
- "nfsroot=_ROOTFS_PATH_IN_NFS_\0"
-
+ "vkernel=/boot/uImage.vab820\0" \
+ "hdmi=video=mxcfb0:dev=hdmi,1920x1080M@60,bpp=32\0"\
+ "hdmilvds=video=mxcfb0:dev=hdmi,1920x1080@60,bpp=32 video=mxcfb1:dev=ldb,LDB-SXGA,if=RGB24 ldb=spl0\0"\
+ "bootargs_base=setenv bootargs console=ttymxc1,115200 ${hdmilvds} console=tty1,115200\0"\
+ "viewsfenv=sf probe 1 ; sf read 0x10800000 0xc0000 0x2000 ; md 0x10800000\0" \
+ "clearsfenv=sf probe 1 ; sf erase 0xc0000 0x2000 ; echo flash environment.\0" \
+ "bootargs_mmc=setenv bootargs ${bootargs} root=/dev/mmcblk0p1 rootwait rw\0" \
+ "bootcmd_mmc=run bootargs_base bootargs_mmc; mmc dev 1; ext2load mmc 1:1 $loadaddr $vkernel && bootm\0" \
+ "bootargs_sd=setenv bootargs ${bootargs} root=/dev/mmcblk1p1 rootwait rw\0" \
+ "bootcmd_sd=run bootargs_base bootargs_sd; mmc dev 0; ext2load mmc 0:1 $loadaddr $vkernel && bootm\0" \
+ "bootcmd=run bootcmd_sd\0"
+#else
+// steven: default config
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "netdev=eth0\0" \
+ "ethprime=FEC0\0" \
+ "ethaddr=00:01:02:03:04:05\0" \
+ "uboot=u-boot.bin\0" \
+ "kernel=uImage\0" \
+ "vkernel=/boot/uImage.vab820\0" \
+ "hdmi=video=mxcfb0:dev=hdmi,1920x1080M@60,bpp=32\0"\
+ "lvds=video=mxcfb0:dev=ldb,LDB-WSXGA+,if=RGB24 ldb=spl0\0"\
+ "bootargs_base=setenv bootargs console=ttymxc1,115200 ${hdmi} console=tty1,115200\0"\
+ "viewsfenv=sf probe 1 ; sf read 0x10800000 0xc0000 0x2000 ; md 0x10800000\0" \
+ "clearsfenv=sf probe 1 ; sf erase 0xc0000 0x2000 ; echo flash environment.\0" \
+ "bootargs_mmc=setenv bootargs ${bootargs} root=/dev/mmcblk0p1 rootwait rw\0" \
+ "bootcmd_mmc=run bootargs_base bootargs_mmc; mmc dev 1; ext2load mmc 1:1 $loadaddr $vkernel && bootm\0" \
+ "bootargs_sd=setenv bootargs ${bootargs} root=/dev/mmcblk1p1 rootwait rw\0" \
+ "bootcmd_sd=run bootargs_base bootargs_sd; mmc dev 0; ext2load mmc 0:1 $loadaddr $vkernel && bootm\0" \
+ "bootcmd=run bootcmd_mmc\0"
+#endif
#define CONFIG_ARP_TIMEOUT 200UL
@@ -153,7 +165,9 @@
* Miscellaneous configurable options
*/
#define CONFIG_SYS_LONGHELP /* undef to save memory */
-#define CONFIG_SYS_PROMPT "MX6Q SABRELITE U-Boot > "
+// Steven
+#define CONFIG_SYS_PROMPT "MX6Q VAB820 U-Boot > "
+
#define CONFIG_AUTO_COMPLETE
#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
/* Print Buffer Size */
@@ -284,9 +298,10 @@
*/
#define CONFIG_NR_DRAM_BANKS 1
#define PHYS_SDRAM_1 CSD0_DDR_BASE_ADDR
-#define PHYS_SDRAM_1_SIZE (1u * 1024 * 1024 * 1024)
-#define iomem_valid_addr(addr, size) \
- (addr >= PHYS_SDRAM_1 && addr <= (PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE))
+// Steven: DON'T access more than 1GB address on uboot
+#define PHYS_SDRAM_1_SIZE (2u * 1024 * 1024 * 1024)
+//#define iomem_valid_addr(addr, size) \
+// (addr >= PHYS_SDRAM_1 && addr <= (PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE))
/*-----------------------------------------------------------------------
* FLASH and environment organization
@@ -294,9 +309,12 @@
#define CONFIG_SYS_NO_FLASH
/* Monitor at beginning of flash */
-/* #define CONFIG_FSL_ENV_IN_MMC */
/* #define CONFIG_FSL_ENV_IN_SATA */
-#define CONFIG_FSL_ENV_IN_SF
+#ifdef VAB820_FACTORY
+ #define CONFIG_FSL_ENV_IN_MMC
+#else
+ #define CONFIG_FSL_ENV_IN_SF
+#endif
#define CONFIG_ENV_SECT_SIZE (8 * 1024)
#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
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