yosys.log

yosys.log

 /----------------------------------------------------------------------------\
 |                                                                            |
 |  yosys -- Yosys Open SYnthesis Suite                                       |
 |                                                                            |
 |  Copyright (C) 2012 - 2020  Claire Wolf <claire@symbioticeda.com>          |
 |                                                                            |
 |  Permission to use, copy, modify, and/or distribute this software for any  |
 |  purpose with or without fee is hereby granted, provided that the above    |
 |  copyright notice and this permission notice appear in all copies.         |
 |                                                                            |
 |  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES  |
 |  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF          |
 |  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR   |
 |  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES    |
 |  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN     |
 |  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF   |
 |  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.            |
 |                                                                            |
 \----------------------------------------------------------------------------/

 Yosys 0.9+1706 (git sha1 590d8ecc, clang 6.0.0-1ubuntu2 -fPIC -Os)


-- Running command `tcl fusesoc_utils_blinky_0.tcl' --
[TCL: yosys -import] Command name collision: found pre-existing command `cd' -> skip.
[TCL: yosys -import] Command name collision: found pre-existing command `eval' -> skip.
[TCL: yosys -import] Command name collision: found pre-existing command `exec' -> skip.
[TCL: yosys -import] Command name collision: found pre-existing command `read' -> skip.
[TCL: yosys -import] Command name collision: found pre-existing command `trace' -> skip.

1. Executing Verilog-2005 frontend: ../src/fusesoc_utils_blinky_0/blinky.v
Parsing Verilog input from `../src/fusesoc_utils_blinky_0/blinky.v' to AST representation.
Storing AST representation for module `$abstract\blinky'.
Successfully finished Verilog frontend.
Warning: Selection "$abstractlinky" did not match any module.

2. Executing SYNTH_ICE40 pass.

2.1. Executing Verilog-2005 frontend: /usr/local/bin/../share/yosys/ice40/cells_sim.v
Parsing Verilog input from `/usr/local/bin/../share/yosys/ice40/cells_sim.v' to AST representation.
Generating RTLIL representation for module `\SB_IO'.
Generating RTLIL representation for module `\SB_GB_IO'.
Generating RTLIL representation for module `\SB_GB'.
Generating RTLIL representation for module `\SB_LUT4'.
Generating RTLIL representation for module `\SB_CARRY'.
Generating RTLIL representation for module `\SB_DFF'.
Generating RTLIL representation for module `\SB_DFFE'.
Generating RTLIL representation for module `\SB_DFFSR'.
Generating RTLIL representation for module `\SB_DFFR'.
Generating RTLIL representation for module `\SB_DFFSS'.
Generating RTLIL representation for module `\SB_DFFS'.
Generating RTLIL representation for module `\SB_DFFESR'.
Generating RTLIL representation for module `\SB_DFFER'.
Generating RTLIL representation for module `\SB_DFFESS'.
Generating RTLIL representation for module `\SB_DFFES'.
Generating RTLIL representation for module `\SB_DFFN'.
Generating RTLIL representation for module `\SB_DFFNE'.
Generating RTLIL representation for module `\SB_DFFNSR'.
Generating RTLIL representation for module `\SB_DFFNR'.
Generating RTLIL representation for module `\SB_DFFNSS'.
Generating RTLIL representation for module `\SB_DFFNS'.
Generating RTLIL representation for module `\SB_DFFNESR'.
Generating RTLIL representation for module `\SB_DFFNER'.
Generating RTLIL representation for module `\SB_DFFNESS'.
Generating RTLIL representation for module `\SB_DFFNES'.
Generating RTLIL representation for module `\SB_RAM40_4K'.
Generating RTLIL representation for module `\SB_RAM40_4KNR'.
Generating RTLIL representation for module `\SB_RAM40_4KNW'.
Generating RTLIL representation for module `\SB_RAM40_4KNRNW'.
Generating RTLIL representation for module `\ICESTORM_LC'.
Generating RTLIL representation for module `\SB_PLL40_CORE'.
Generating RTLIL representation for module `\SB_PLL40_PAD'.
Generating RTLIL representation for module `\SB_PLL40_2_PAD'.
Generating RTLIL representation for module `\SB_PLL40_2F_CORE'.
Generating RTLIL representation for module `\SB_PLL40_2F_PAD'.
Generating RTLIL representation for module `\SB_WARMBOOT'.
Generating RTLIL representation for module `\SB_SPRAM256KA'.
Generating RTLIL representation for module `\SB_HFOSC'.
Generating RTLIL representation for module `\SB_LFOSC'.
Generating RTLIL representation for module `\SB_RGBA_DRV'.
Generating RTLIL representation for module `\SB_LED_DRV_CUR'.
Generating RTLIL representation for module `\SB_RGB_DRV'.
Generating RTLIL representation for module `\SB_I2C'.
Generating RTLIL representation for module `\SB_SPI'.
Generating RTLIL representation for module `\SB_LEDDA_IP'.
Generating RTLIL representation for module `\SB_FILTER_50NS'.
Generating RTLIL representation for module `\SB_IO_I3C'.
Generating RTLIL representation for module `\SB_IO_OD'.
Generating RTLIL representation for module `\SB_MAC16'.
Generating RTLIL representation for module `\ICESTORM_RAM'.
Successfully finished Verilog frontend.

2.2. Executing HIERARCHY pass (managing design hierarchy).

2.3. Executing AST frontend in derive mode using pre-parsed AST for module `\blinky'.
Generating RTLIL representation for module `\blinky'.

2.3.1. Analyzing design hierarchy..
Top module:  \blinky

2.3.2. Analyzing design hierarchy..
Top module:  \blinky
Removing unused module `$abstract\blinky'.
Removed 1 unused modules.

2.4. Executing PROC pass (convert processes to netlists).

2.4.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Removing empty process `blinky.$proc$../src/fusesoc_utils_blinky_0/blinky.v:6$346'.
Cleaned up 0 empty switches.

2.4.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Removed a total of 0 dead cases.

2.4.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 0 redundant assignments.
Promoted 1 assignment to connection.

2.4.4. Executing PROC_INIT pass (extract init attributes).
Found init rule in `\blinky.$proc$../src/fusesoc_utils_blinky_0/blinky.v:0$345'.
  Set init value: \q = 1'0

2.4.5. Executing PROC_ARST pass (detect async resets in processes).

2.4.6. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `\blinky.$proc$../src/fusesoc_utils_blinky_0/blinky.v:0$345'.
Creating decoders for process `\blinky.$proc$../src/fusesoc_utils_blinky_0/blinky.v:8$341'.
     1/1: $0\q[0:0]

2.4.7. Executing PROC_DLATCH pass (convert process syncs to latches).

2.4.8. Executing PROC_DFF pass (convert process syncs to FFs).
Creating register for signal `\blinky.\q' using process `\blinky.$proc$../src/fusesoc_utils_blinky_0/blinky.v:8$341'.
  created $dff cell `$procdff$349' with positive edge clock.

2.4.9. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Removing empty process `blinky.$proc$../src/fusesoc_utils_blinky_0/blinky.v:0$345'.
Found and cleaned up 1 empty switch in `\blinky.$proc$../src/fusesoc_utils_blinky_0/blinky.v:8$341'.
Removing empty process `blinky.$proc$../src/fusesoc_utils_blinky_0/blinky.v:8$341'.
Cleaned up 1 empty switch.

2.5. Executing FLATTEN pass (flatten design).
No more expansions possible.

2.6. Executing TRIBUF pass.

2.7. Executing DEMINOUT pass (demote inout ports to input or output).

2.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module blinky.
<suppressed ~4 debug messages>

2.9. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \blinky..
Removed 1 unused cells and 8 unused wires.
<suppressed ~3 debug messages>

2.10. Executing CHECK pass (checking for obvious problems).
checking module blinky..
found and reported 0 problems.

2.11. Executing OPT pass (performing simple optimizations).

2.11.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module blinky.

2.11.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\blinky'.
Removed a total of 0 cells.

2.11.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \blinky..
  Creating internal representation of mux trees.
  No muxes found in this module.
Removed 0 multiplexer ports.

2.11.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \blinky.
Performed a total of 0 changes.

2.11.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\blinky'.
Removed a total of 0 cells.

2.11.6. Executing OPT_RMDFF pass (remove dff with constant values).
Removing $procdff$349 ($dff) from module blinky.
Replaced 1 DFF cells.

2.11.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \blinky..

2.11.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module blinky.

2.11.9. Rerunning OPT passes. (Maybe there is more to do..)

2.11.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \blinky..
  Creating internal representation of mux trees.
  No muxes found in this module.
Removed 0 multiplexer ports.

2.11.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \blinky.
Performed a total of 0 changes.

2.11.12. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\blinky'.
Removed a total of 0 cells.

2.11.13. Executing OPT_RMDFF pass (remove dff with constant values).

2.11.14. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \blinky..

2.11.15. Executing OPT_EXPR pass (perform const folding).
Optimizing module blinky.

2.11.16. Finished OPT passes. (There is nothing left to do.)

2.12. Executing WREDUCE pass (reducing word size of cells).

2.13. Executing PEEPOPT pass (run peephole optimizers).

2.14. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \blinky..

2.15. Executing SHARE pass (SAT-based resource sharing).

2.16. Executing TECHMAP pass (map to technology primitives).

2.16.1. Executing Verilog-2005 frontend: /usr/local/bin/../share/yosys/cmp2lut.v
Parsing Verilog input from `/usr/local/bin/../share/yosys/cmp2lut.v' to AST representation.
Generating RTLIL representation for module `\_90_lut_cmp_'.
Successfully finished Verilog frontend.

2.16.2. Continuing TECHMAP pass.
No more expansions possible.

2.17. Executing OPT_EXPR pass (perform const folding).
Optimizing module blinky.

2.18. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \blinky..

2.19. Executing ALUMACC pass (create $alu and $macc cells).
Extracting $alu and $macc cells in module blinky:
  created 0 $alu and 0 $macc cells.

2.20. Executing OPT pass (performing simple optimizations).

2.20.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module blinky.

2.20.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\blinky'.
Removed a total of 0 cells.

2.20.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \blinky..
  Creating internal representation of mux trees.
  No muxes found in this module.
Removed 0 multiplexer ports.

2.20.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \blinky.
Performed a total of 0 changes.

2.20.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\blinky'.
Removed a total of 0 cells.

2.20.6. Executing OPT_RMDFF pass (remove dff with constant values).

2.20.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \blinky..

2.20.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module blinky.

2.20.9. Finished OPT passes. (There is nothing left to do.)

2.21. Executing FSM pass (extract and optimize FSM).

2.21.1. Executing FSM_DETECT pass (finding FSMs in design).

2.21.2. Executing FSM_EXTRACT pass (extracting FSM from design).

2.21.3. Executing FSM_OPT pass (simple optimizations of FSMs).

2.21.4. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \blinky..

2.21.5. Executing FSM_OPT pass (simple optimizations of FSMs).

2.21.6. Executing FSM_RECODE pass (re-assigning FSM state encoding).

2.21.7. Executing FSM_INFO pass (dumping all available information on FSM cells).

2.21.8. Executing FSM_MAP pass (mapping FSMs to basic logic).

2.22. Executing OPT pass (performing simple optimizations).

2.22.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module blinky.

2.22.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\blinky'.
Removed a total of 0 cells.

2.22.3. Executing OPT_RMDFF pass (remove dff with constant values).

2.22.4. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \blinky..

2.22.5. Finished fast OPT passes.

2.23. Executing MEMORY pass.

2.23.1. Executing OPT_MEM pass (optimize memories).
Performed a total of 0 transformations.

2.23.2. Executing MEMORY_DFF pass (merging $dff cells to $memrd and $memwr).

2.23.3. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \blinky..

2.23.4. Executing MEMORY_SHARE pass (consolidating $memrd/$memwr cells).

2.23.5. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \blinky..

2.23.6. Executing MEMORY_COLLECT pass (generating $mem cells).

2.24. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \blinky..

2.25. Executing MEMORY_BRAM pass (mapping $mem cells to block memories).

2.26. Executing TECHMAP pass (map to technology primitives).

2.26.1. Executing Verilog-2005 frontend: /usr/local/bin/../share/yosys/ice40/brams_map.v
Parsing Verilog input from `/usr/local/bin/../share/yosys/ice40/brams_map.v' to AST representation.
Generating RTLIL representation for module `\$__ICE40_RAM4K'.
Generating RTLIL representation for module `\$__ICE40_RAM4K_M0'.
Generating RTLIL representation for module `\$__ICE40_RAM4K_M123'.
Successfully finished Verilog frontend.

2.26.2. Continuing TECHMAP pass.
No more expansions possible.

2.27. Executing ICE40_BRAMINIT pass.

2.28. Executing OPT pass (performing simple optimizations).

2.28.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module blinky.

2.28.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\blinky'.
Removed a total of 0 cells.

2.28.3. Executing OPT_RMDFF pass (remove dff with constant values).

2.28.4. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \blinky..

2.28.5. Finished fast OPT passes.

2.29. Executing MEMORY_MAP pass (converting $mem cells to logic and flip-flops).

2.30. Executing OPT pass (performing simple optimizations).

2.30.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module blinky.

2.30.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\blinky'.
Removed a total of 0 cells.

2.30.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \blinky..
  Creating internal representation of mux trees.
  No muxes found in this module.
Removed 0 multiplexer ports.

2.30.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \blinky.
Performed a total of 0 changes.

2.30.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\blinky'.
Removed a total of 0 cells.

2.30.6. Executing OPT_RMDFF pass (remove dff with constant values).

2.30.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \blinky..

2.30.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module blinky.

2.30.9. Finished OPT passes. (There is nothing left to do.)

2.31. Executing ICE40_WRAPCARRY pass (wrap carries).

2.32. Executing TECHMAP pass (map to technology primitives).

2.32.1. Executing Verilog-2005 frontend: /usr/local/bin/../share/yosys/techmap.v
Parsing Verilog input from `/usr/local/bin/../share/yosys/techmap.v' to AST representation.
Generating RTLIL representation for module `\_90_simplemap_bool_ops'.
Generating RTLIL representation for module `\_90_simplemap_reduce_ops'.
Generating RTLIL representation for module `\_90_simplemap_logic_ops'.
Generating RTLIL representation for module `\_90_simplemap_compare_ops'.
Generating RTLIL representation for module `\_90_simplemap_various'.
Generating RTLIL representation for module `\_90_simplemap_registers'.
Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'.
Generating RTLIL representation for module `\_90_shift_shiftx'.
Generating RTLIL representation for module `\_90_fa'.
Generating RTLIL representation for module `\_90_lcu'.
Generating RTLIL representation for module `\_90_alu'.
Generating RTLIL representation for module `\_90_macc'.
Generating RTLIL representation for module `\_90_alumacc'.
Generating RTLIL representation for module `\$__div_mod_u'.
Generating RTLIL representation for module `\$__div_mod'.
Generating RTLIL representation for module `\_90_div'.
Generating RTLIL representation for module `\_90_mod'.
Generating RTLIL representation for module `\_90_pow'.
Generating RTLIL representation for module `\_90_pmux'.
Generating RTLIL representation for module `\_90_lut'.
Successfully finished Verilog frontend.

2.32.2. Executing Verilog-2005 frontend: /usr/local/bin/../share/yosys/ice40/arith_map.v
Parsing Verilog input from `/usr/local/bin/../share/yosys/ice40/arith_map.v' to AST representation.
Generating RTLIL representation for module `\_80_ice40_alu'.
Successfully finished Verilog frontend.

2.32.3. Continuing TECHMAP pass.
No more expansions possible.

2.33. Executing OPT pass (performing simple optimizations).

2.33.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module blinky.

2.33.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\blinky'.
Removed a total of 0 cells.

2.33.3. Executing OPT_RMDFF pass (remove dff with constant values).

2.33.4. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \blinky..

2.33.5. Finished fast OPT passes.

2.34. Executing ICE40_OPT pass (performing simple optimizations).

2.34.1. Running ICE40 specific optimizations.

2.34.2. Executing OPT_EXPR pass (perform const folding).
Optimizing module blinky.

2.34.3. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\blinky'.
Removed a total of 0 cells.

2.34.4. Executing OPT_RMDFF pass (remove dff with constant values).

2.34.5. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \blinky..

2.34.6. Finished OPT passes. (There is nothing left to do.)

2.35. Executing DFFSR2DFF pass (mapping DFFSR cells to simpler FFs).

2.36. Executing DFF2DFFE pass (transform $dff to $dffe where applicable).
Selected cell types for direct conversion:
  $_DFF_PP1_ -> $__DFFE_PP1
  $_DFF_PP0_ -> $__DFFE_PP0
  $_DFF_PN1_ -> $__DFFE_PN1
  $_DFF_PN0_ -> $__DFFE_PN0
  $_DFF_NP1_ -> $__DFFE_NP1
  $_DFF_NP0_ -> $__DFFE_NP0
  $_DFF_NN1_ -> $__DFFE_NN1
  $_DFF_NN0_ -> $__DFFE_NN0
  $_DFF_N_ -> $_DFFE_NP_
  $_DFF_P_ -> $_DFFE_PP_
Transforming FF to FF+Enable cells in module blinky:

2.37. Executing TECHMAP pass (map to technology primitives).

2.37.1. Executing Verilog-2005 frontend: /usr/local/bin/../share/yosys/ice40/cells_map.v
Parsing Verilog input from `/usr/local/bin/../share/yosys/ice40/cells_map.v' to AST representation.
Generating RTLIL representation for module `\$_DFF_N_'.
Generating RTLIL representation for module `\$_DFF_P_'.
Generating RTLIL representation for module `\$_DFFE_NN_'.
Generating RTLIL representation for module `\$_DFFE_PN_'.
Generating RTLIL representation for module `\$_DFFE_NP_'.
Generating RTLIL representation for module `\$_DFFE_PP_'.
Generating RTLIL representation for module `\$_DFF_NN0_'.
Generating RTLIL representation for module `\$_DFF_NN1_'.
Generating RTLIL representation for module `\$_DFF_PN0_'.
Generating RTLIL representation for module `\$_DFF_PN1_'.
Generating RTLIL representation for module `\$_DFF_NP0_'.
Generating RTLIL representation for module `\$_DFF_NP1_'.
Generating RTLIL representation for module `\$_DFF_PP0_'.
Generating RTLIL representation for module `\$_DFF_PP1_'.
Generating RTLIL representation for module `\$__DFFE_NN0'.
Generating RTLIL representation for module `\$__DFFE_NN1'.
Generating RTLIL representation for module `\$__DFFE_PN0'.
Generating RTLIL representation for module `\$__DFFE_PN1'.
Generating RTLIL representation for module `\$__DFFE_NP0'.
Generating RTLIL representation for module `\$__DFFE_NP1'.
Generating RTLIL representation for module `\$__DFFE_PP0'.
Generating RTLIL representation for module `\$__DFFE_PP1'.
Successfully finished Verilog frontend.

2.37.2. Continuing TECHMAP pass.
No more expansions possible.

2.38. Executing OPT_EXPR pass (perform const folding).
Optimizing module blinky.

2.39. Executing SIMPLEMAP pass (map simple cells to gate primitives).

2.40. Executing ICE40_FFINIT pass (implement FF init values).
Handling FF init values in blinky.

2.41. Executing ICE40_FFSSR pass (merge synchronous set/reset into FF cells).
Merging set/reset $_MUX_ cells into SB_FFs in blinky.

2.42. Executing ICE40_OPT pass (performing simple optimizations).

2.42.1. Running ICE40 specific optimizations.

2.42.2. Executing OPT_EXPR pass (perform const folding).
Optimizing module blinky.

2.42.3. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\blinky'.
Removed a total of 0 cells.

2.42.4. Executing OPT_RMDFF pass (remove dff with constant values).

2.42.5. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \blinky..

2.42.6. Finished OPT passes. (There is nothing left to do.)

2.43. Executing TECHMAP pass (map to technology primitives).

2.43.1. Executing Verilog-2005 frontend: /usr/local/bin/../share/yosys/ice40/latches_map.v
Parsing Verilog input from `/usr/local/bin/../share/yosys/ice40/latches_map.v' to AST representation.
Generating RTLIL representation for module `\$_DLATCH_N_'.
Generating RTLIL representation for module `\$_DLATCH_P_'.
Successfully finished Verilog frontend.

2.43.2. Continuing TECHMAP pass.
No more expansions possible.

2.44. Executing ABC pass (technology mapping using ABC).

2.44.1. Extracting gate netlist of module `\blinky' to `<abc-temp-dir>/input.blif'..
Extracted 0 gates and 0 wires to a netlist network with 0 inputs and 0 outputs.
Don't call ABC as there is nothing to map.
Removing temp directory.

2.45. Executing ICE40_WRAPCARRY pass (wrap carries).

2.46. Executing TECHMAP pass (map to technology primitives).

2.46.1. Executing Verilog-2005 frontend: /usr/local/bin/../share/yosys/ice40/cells_map.v
Parsing Verilog input from `/usr/local/bin/../share/yosys/ice40/cells_map.v' to AST representation.
Generating RTLIL representation for module `\$_DFF_N_'.
Generating RTLIL representation for module `\$_DFF_P_'.
Generating RTLIL representation for module `\$_DFFE_NN_'.
Generating RTLIL representation for module `\$_DFFE_PN_'.
Generating RTLIL representation for module `\$_DFFE_NP_'.
Generating RTLIL representation for module `\$_DFFE_PP_'.
Generating RTLIL representation for module `\$_DFF_NN0_'.
Generating RTLIL representation for module `\$_DFF_NN1_'.
Generating RTLIL representation for module `\$_DFF_PN0_'.
Generating RTLIL representation for module `\$_DFF_PN1_'.
Generating RTLIL representation for module `\$_DFF_NP0_'.
Generating RTLIL representation for module `\$_DFF_NP1_'.
Generating RTLIL representation for module `\$_DFF_PP0_'.
Generating RTLIL representation for module `\$_DFF_PP1_'.
Generating RTLIL representation for module `\$__DFFE_NN0'.
Generating RTLIL representation for module `\$__DFFE_NN1'.
Generating RTLIL representation for module `\$__DFFE_PN0'.
Generating RTLIL representation for module `\$__DFFE_PN1'.
Generating RTLIL representation for module `\$__DFFE_NP0'.
Generating RTLIL representation for module `\$__DFFE_NP1'.
Generating RTLIL representation for module `\$__DFFE_PP0'.
Generating RTLIL representation for module `\$__DFFE_PP1'.
Successfully finished Verilog frontend.

2.46.2. Continuing TECHMAP pass.
No more expansions possible.

2.47. Executing OPT_LUT pass (optimize LUTs).
Discovering LUTs.
Number of LUTs:        0

Eliminating LUTs.
Number of LUTs:        0

Combining LUTs.
Number of LUTs:        0

Eliminated 0 LUTs.
Combined 0 LUTs.

2.48. Executing TECHMAP pass (map to technology primitives).

2.48.1. Executing Verilog-2005 frontend: /usr/local/bin/../share/yosys/ice40/cells_map.v
Parsing Verilog input from `/usr/local/bin/../share/yosys/ice40/cells_map.v' to AST representation.
Generating RTLIL representation for module `\$_DFF_N_'.
Generating RTLIL representation for module `\$_DFF_P_'.
Generating RTLIL representation for module `\$_DFFE_NN_'.
Generating RTLIL representation for module `\$_DFFE_PN_'.
Generating RTLIL representation for module `\$_DFFE_NP_'.
Generating RTLIL representation for module `\$_DFFE_PP_'.
Generating RTLIL representation for module `\$_DFF_NN0_'.
Generating RTLIL representation for module `\$_DFF_NN1_'.
Generating RTLIL representation for module `\$_DFF_PN0_'.
Generating RTLIL representation for module `\$_DFF_PN1_'.
Generating RTLIL representation for module `\$_DFF_NP0_'.
Generating RTLIL representation for module `\$_DFF_NP1_'.
Generating RTLIL representation for module `\$_DFF_PP0_'.
Generating RTLIL representation for module `\$_DFF_PP1_'.
Generating RTLIL representation for module `\$__DFFE_NN0'.
Generating RTLIL representation for module `\$__DFFE_NN1'.
Generating RTLIL representation for module `\$__DFFE_PN0'.
Generating RTLIL representation for module `\$__DFFE_PN1'.
Generating RTLIL representation for module `\$__DFFE_NP0'.
Generating RTLIL representation for module `\$__DFFE_NP1'.
Generating RTLIL representation for module `\$__DFFE_PP0'.
Generating RTLIL representation for module `\$__DFFE_PP1'.
Generating RTLIL representation for module `\$lut'.
Successfully finished Verilog frontend.

2.48.2. Continuing TECHMAP pass.
No more expansions possible.

2.49. Executing AUTONAME pass.

2.50. Executing HIERARCHY pass (managing design hierarchy).

2.50.1. Analyzing design hierarchy..
Top module:  \blinky

2.50.2. Analyzing design hierarchy..
Top module:  \blinky
Removed 0 unused modules.

2.51. Printing statistics.

=== blinky ===

   Number of wires:                  2
   Number of wire bits:              2
   Number of public wires:           2
   Number of public wire bits:       2
   Number of memories:               0
   Number of memory bits:            0
   Number of processes:              0
   Number of cells:                  0

2.52. Executing CHECK pass (checking for obvious problems).
checking module blinky..
found and reported 0 problems.

3. Executing BLIF backend.

4. Executing JSON backend.

Warnings: 1 unique messages, 1 total
End of script. Logfile hash: c149a61816, CPU: user 0.26s system 0.01s, MEM: 53.23 MB peak
Yosys 0.9+1706 (git sha1 590d8ecc, clang 6.0.0-1ubuntu2 -fPIC -Os)
Time spent: 47% 12x read_verilog (0 sec), 12% 1x synth_ice40 (0 sec), ...