uboot-sunxi

arch/arm/mach-sunxi/board.c
s_init(void)
board_init_f(ulong dummy)
reset_cpu(ulong addr)
enable_caches(void)

arch/arm/mach-sunxi/clock.c
clock_init(void)
clock_twi_onoff(int port, int state)

arch/arm/mach-sunxi/clock_sun4i.c
clock_init_safe(void)
clock_init_uart(void)
clock_twi_onoff(int port, int state)
clock_set_pll1(unsigned int hz)
clock_set_pll3(unsigned int clk)
clock_get_pll3(void)
clock_get_pll5p(void)
clock_get_pll6(void)
clock_set_de_mod_clock(u32 *clk_cfg, unsigned int hz)

arch/arm/mach-sunxi/cpu_info.c
print_cpuinfo(void)

arm/mach-sunxi/dram_helpers.c
mctl_await_completion(u32 *reg, u32 mask, u32 val)
mctl_mem_matches(u32 offset)

arch/arm/mach-sunxi/dram_sun4i.c
await_bits_clear(u32 *reg, u32 mask)
await_bits_set(u32 *reg, u32 mask)
mctl_ddr3_reset(void)
mctl_set_drive(void)
mctl_itm_disable(void)
mctl_itm_enable(void)
mctl_itm_reset(void)
mctl_enable_dll0(u32 phase)
mctl_get_number_of_lanes(void)
mctl_enable_dllx(u32 phase)
mctl_configure_hostport(void)
mctl_setup_dram_clock(u32 clk, u32 mbus_clk)
mctl_set_dqs_gating_delay(int rank, u32 dqs_gating_delay)
dramc_scan_readpipe(void)
dramc_clock_output_en(u32 on)
dramc_set_autorefresh_cycle(u32 clk, u32 density)
ddr3_write_recovery(u32 clk)
mctl_disable_power_save(void)
mctl_set_cke_delay(void)
mctl_ddr3_initialize(void)
mctl_set_impedance(u32 zq, bool odt_en)
dramc_init_helper(struct dram_para *para)
dramc_init(struct dram_para *para)

arch/arm/mach-sunxi/pinmux.c
sunxi_gpio_set_cfgbank(struct sunxi_gpio *pio, int bank_offset, u32 val)
void sunxi_gpio_set_cfgpin(u32 pin, u32 val)
int sunxi_gpio_get_cfgbank(struct sunxi_gpio *pio, int bank_offset)
sunxi_gpio_get_cfgpin(u32 pin)
sunxi_gpio_set_drv(u32 pin, u32 val)
sunxi_gpio_set_pull(u32 pin, u32 val)

arch/arm/mach-sunxi/prcm.c
prcm_apb0_enable(u32 flags)
prcm_apb0_disable(u32 flags)