OpenOCD Target configuration for NXP LPC1549
# NXP LPC1549 (based on lpc1xxx.cfg) | |
set _CHIPNAME lpc1549 | |
set _WORKAREASIZE 0x9000 | |
set _CHIPSERIES lpc1500 | |
set _BANKSIZE 0x40000 | |
source [find target/swj-dp.tcl] | |
if { [info exists CCLK] } { | |
# Allow user override | |
set _CCLK $CCLK | |
} else { | |
set _CCLK 12000 | |
} | |
if { [info exists CPUTAPID] } { | |
# Allow user override | |
set _CPUTAPID $CPUTAPID | |
} else { | |
if { [using_jtag] } { | |
set _CPUTAPID 0x4ba00477 | |
} { | |
set _CPUTAPID 0x2ba01477 | |
} | |
} | |
swj_newdap $_CHIPNAME cpu -irlen 4 -expected-id $_CPUTAPID | |
set _TARGETNAME $_CHIPNAME.cpu | |
target create $_TARGETNAME cortex_m -chain-position $_TARGETNAME | |
$_TARGETNAME configure -work-area-phys 0x02000000 -work-area-size $_WORKAREASIZE | |
set _FLASHNAME $_CHIPNAME.flash | |
flash bank $_FLASHNAME lpc2000 0x0 $_BANKSIZE 0 0 $_TARGETNAME \ | |
lpc1500 $_CCLK calc_checksum | |
$_TARGETNAME configure -event reset-init { | |
mww 0x40074000 0x02 | |
} | |
adapter_khz 4000 | |
# delays on reset lines | |
adapter_nsrst_delay 200 | |
if {[using_jtag]} { | |
jtag_ntrst_delay 200 | |
} | |
# LPC13xx/LPC15xx/LPC17xx (Cortex M3 core) support SYSRESETREQ | |
if {![using_hla]} { | |
# if srst is not fitted use SYSRESETREQ to perform a soft reset | |
cortex_m reset_config sysresetreq | |
} |
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