lpddr4_h618_21_10_23

gistfile1.txt

From bb043903189cd76d534227d3c9c002290d1cb8f9 Mon Sep 17 00:00:00 2001
From: iuncuim <iuncuim@gmail.com>
Date: Sat, 21 Oct 2023 11:13:29 +0300
Subject: [PATCH] Update dram_sun50i_h616.c

---
 arch/arm/mach-sunxi/dram_sun50i_h616.c | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/arch/arm/mach-sunxi/dram_sun50i_h616.c b/arch/arm/mach-sunxi/dram_sun50i_h616.c
index 034ad1ae3d..ddccd0bac3 100644
--- a/arch/arm/mach-sunxi/dram_sun50i_h616.c
+++ b/arch/arm/mach-sunxi/dram_sun50i_h616.c
@@ -588,6 +588,8 @@ static void mctl_phy_bit_delay_compensation(const struct dram_para *para)
 		clrbits_le32(SUNXI_DRAM_PHY0_BASE + 0x60, 1);
 		setbits_le32(SUNXI_DRAM_PHY0_BASE + 8, 8);
 		clrbits_le32(SUNXI_DRAM_PHY0_BASE + 0x190, 0x10);
+		if (para->type == SUNXI_DRAM_TYPE_LPDDR4)
+			clrbits_le32(SUNXI_DRAM_PHY0_BASE + 0x4, 0x80);
 
 		if (para->tpr10 & BIT(30))
 			val = para->tpr11 & 0x3f;
@@ -1151,12 +1153,10 @@ static bool mctl_ctrl_init(const struct dram_para *para,
 
 	clrsetbits_le32(&mctl_com->unk_0x500, BIT(24), 0x200);
 	writel(0x8000, &mctl_ctl->clken);
-
+	setbits_le32(&mctl_com->unk_0x008, 0xff00);
+	
 	if (para->type == SUNXI_DRAM_TYPE_LPDDR4)
 		writel(1, SUNXI_DRAM_COM_BASE + 0x50);
-
-	setbits_le32(&mctl_com->unk_0x008, 0xff00);
-
 	clrsetbits_le32(&mctl_ctl->sched[0], 0xff00, 0x3000);
 
 	writel(0, &mctl_ctl->hwlpctl);
-- 
2.42.0