Created
December 23, 2024 05:23
cpu_sun55i_a523.h
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/* | |
* (C) Copyright 2017 Icenowy Zheng <icenowy@aosc.io> | |
* | |
* SPDX-License-Identifier: GPL-2.0+ | |
*/ | |
#ifndef _SUNXI_CPU_SUN55I_A523_H | |
#define _SUNXI_CPU_SUN55I_A523_H | |
#define SUNXI_SRAMC_BASE 0x00040000 | |
#define SUNXI_CCM_BASE 0x02001000 | |
/* SID address space starts at 0x03006000, but e-fuse is at offset 0x200 */ | |
#define SUNXI_SIDC_BASE 0x03006000 | |
#define SUNXI_SID_BASE 0x03006200 | |
#define SUNXI_TIMER_BASE 0x03008000 | |
#define SUNXI_GIC400_BASE 0x03400000 | |
#define SUNXI_NFC_BASE 0x04011000 | |
#define SUNXI_MMC0_BASE 0x04020000 | |
#define SUNXI_MMC1_BASE 0x04021000 | |
#define SUNXI_MMC2_BASE 0x04022000 | |
#define SUNXI_DRAM_COM_BASE 0x03120000 | |
#define SUNXI_DRAM_CTL0_BASE 0x03130000 | |
#define SUNXI_DRAM_PHY0_BASE 0x03140000 | |
#define SUNXI_TWI0_BASE 0x02502000 | |
#define SUNXI_TWI1_BASE 0x02502400 | |
#define SUNXI_TWI2_BASE 0x02502800 | |
#define SUNXI_TWI3_BASE 0x02502C00 | |
#define SUNXI_TWI4_BASE 0x02503000 | |
#define SUNXI_TWI5_BASE 0x02503400 | |
#define SUNXI_HDMI_BASE 0x05520000 | |
#define SUNXI_RTC_BASE 0x07090000 | |
#define SUNXI_R_CPUCFG_BASE 0x07000400 | |
#define SUNXI_PRCM_BASE 0x07010000 | |
#define SUNXI_R_WDOG_BASE 0x07020400 | |
#define SUNXI_R_TWI_BASE 0x07081400 | |
#ifndef __ASSEMBLY__ | |
void sunxi_board_init(void); | |
void sunxi_reset(void); | |
int sunxi_get_sid(unsigned int *sid); | |
#endif | |
#endif /* _SUNXI_CPU_SUN55I_H */ |
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