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LC-3 Assembly Language definition for customasm
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#once | |
; LC3 Instruction Set Assembly for customasm (https://github.com/hlorenzi/customasm) | |
; | |
; References: | |
; Patt, Yale N.; Patel, Sanjay (2003). Introduction to Computing Systems: | |
; From Bits and Gates to C and Beyond. New York, NY: McGraw-Hill Higher | |
; Education. ISBN 0-07-246750-9. | |
#bankdef lc3_bank | |
{ | |
#bits 16 ; (Addresable) Word-size | |
#addr 0x3000 ; Starting logical address | |
#addr_end 0x10000 ; Ending logical address (exclusive) | |
#outp 0 | |
} | |
#subruledef lc3_reg | |
{ | |
R{n: u3} => n`3 | |
} | |
; (Only for 9-bit offsets) | |
#subruledef lc3_label | |
{ | |
{addr} => | |
{ | |
offset = addr - ($ + 1) | |
assert(offset <= 255) | |
assert(offset >= -256) | |
offset | |
} | |
} | |
#ruledef lc3 | |
{ | |
; Addition | |
ADD {dr: lc3_reg}, {sr1: lc3_reg}, {sr2: lc3_reg} => 0b0001 @ dr @ sr1 @ 0b000 @ sr2 | |
ADD {dr: lc3_reg}, {sr1: lc3_reg}, {imm: s5} => 0b0001 @ dr @ sr1 @ 0b1 @ imm | |
; Bit-wise Logical And | |
AND {dr: lc3_reg}, {sr1: lc3_reg}, {sr2: lc3_reg} => 0b0101 @ dr @ sr1 @ 0b000 @ sr2 | |
AND {dr: lc3_reg}, {sr1: lc3_reg}, {imm: s5} => 0b0101 @ dr @ sr1 @ 0b1 @ imm | |
; Conditional Branch instructions | |
BR {offset: lc3_label} => 0b0000 @ 0b000 @ offset`9 | |
BRn {offset: lc3_label} => 0b0000 @ 0b100 @ offset`9 | |
BRz {offset: lc3_label} => 0b0000 @ 0b010 @ offset`9 | |
BRp {offset: lc3_label} => 0b0000 @ 0b001 @ offset`9 | |
BRzp {offset: lc3_label} => 0b0000 @ 0b011 @ offset`9 | |
BRnp {offset: lc3_label} => 0b0000 @ 0b101 @ offset`9 | |
BRnz {offset: lc3_label} => 0b0000 @ 0b110 @ offset`9 | |
BRnzp {offset: lc3_label} => 0b0000 @ 0b111 @ offset`9 | |
; Jump / Return from Subroutine | |
JMP {BaseR: lc3_reg} => 0b1100 @ 0b000 @ BaseR @ 0`6 | |
RET => asm { JMP R7 } | |
; Jump to Subroutine | |
JSR {label} => | |
{ | |
offset = label - ($ + 1) | |
assert(offset <= 1023) | |
assert(offset >= -1024) | |
0b0100 @ 0b1 @ offset`11 | |
} | |
JSRR {BaseR: lc3_reg} => 0b0100 @ 0b0 @ 0b00 @ BaseR @ 0`6 | |
; Load instrutions | |
LD {dr: lc3_reg}, {offset: lc3_label} => 0b0010 @ dr @ offset`9 | |
LDI {dr: lc3_reg}, {offset: lc3_label} => 0b1010 @ dr @ offset`9 | |
LDR {dr: lc3_reg} , {BaseR: lc3_reg}, {offset: s6} => 0b0110 @ dr @ BaseR @ offset | |
; Load Effective Address | |
LEA {dr: lc3_reg}, {offset: lc3_label} => 0b1110 @ dr @ offset`9 | |
; Bit-Wise Complement | |
NOT {dr: lc3_reg}, {sr: lc3_reg} => 0b1001 @ dr @ sr @ 0b111111 | |
; Return from Trap or Interrupt | |
RTI => 0b1000 @ 0`12 | |
; Store instructions | |
ST {sr: lc3_reg}, {offset: lc3_label} => 0b0011 @ sr @ offset`9 | |
STI {sr: lc3_reg}, {offset: lc3_label} => 0b1011 @ sr @ offset`9 | |
STR {sr: lc3_reg}, {BaseR: lc3_reg}, {offset: s6} => 0b0111 @ sr @ BaseR @ offset | |
; System Call | |
TRAP {trapvect: u8} => 0b1111 @ 0b0000 @ trapvect`8 | |
; Trap Service Routines (specific aliases for TRAP) | |
GETC => asm { TRAP 0x20 } | |
OUT => asm { TRAP 0x21 } | |
PUTS => asm { TRAP 0x22 } | |
IN => asm { TRAP 0x23 } | |
PUTSP => asm { TRAP 0x24 } | |
HALT => asm { TRAP 0x25 } | |
} | |
; STRINGZ - Null-terminated string as 16-bit big-endian words | |
; | |
; --- Example usage --- | |
; | |
; alias: | |
; #d STRINGZ("my_string") | |
; | |
#fn STRINGZ(param) => utf16be(param) @ 0x0000 | |
; FILL - Fill next word with value (truncating!) | |
; | |
; --- Example usage --- | |
; | |
; six: | |
; #d FILL(6) | |
; #d16 0x0006 ; Alternative | |
; | |
#fn FILL(value) => value`16 |
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