change.diff

diff --git a/src/main/scala/chisel3/experimental/conversions/package.scala b/src/main/scala/chisel3/experimental/conversions/package.scala
index c52fd1fe..7f1102f5 100644
--- a/src/main/scala/chisel3/experimental/conversions/package.scala
+++ b/src/main/scala/chisel3/experimental/conversions/package.scala
@@ -69,12 +69,16 @@ package object conversions {
     }
   }
 
-  /** Implicit conversion between `(A, B)` and `HWTuple2[A, B]` */
-  implicit def tuple2hwtuple[T1 : DataProduct, T2 : DataProduct, V1 <: Data, V2 <: Data](
-    tup: (T1, T2)
-  )(
-    implicit v1: DataView[T1, V1], v2: DataView[T2, V2]
-  ): HWTuple2[V1, V2] = {
-    tup.viewAs[HWTuple2[V1, V2]]
+//  /** Implicit conversion between `(A, B)` and `HWTuple2[A, B]` */
+//  implicit def tuple2hwtuple[T1 : DataProduct, T2 : DataProduct, V1 <: Data, V2 <: Data](
+//    tup: (T1, T2)
+//  )(
+//    implicit v1: DataView[T1, V1], v2: DataView[T2, V2]
+//  ): HWTuple2[V1, V2] = {
+//    tup.viewAs[HWTuple2[V1, V2]]
+//  }
+
+  implicit class CanConvertToData[A : DataProduct](a: A) {
+    def asData[B <: Data](implicit dataview: DataView[A, B]): B = a.viewAs[B]
   }
 }
diff --git a/src/test/scala/chiselTests/experimental/DataView.scala b/src/test/scala/chiselTests/experimental/DataView.scala
index 918c0c54..005bc3d1 100644
--- a/src/test/scala/chiselTests/experimental/DataView.scala
+++ b/src/test/scala/chiselTests/experimental/DataView.scala
@@ -270,7 +270,7 @@ class DataViewSpec extends ChiselFlatSpec {
       val a, b, c, d = IO(Input(UInt(8.W)))
       val sel = IO(Input(Bool()))
       val y, z = IO(Output(UInt(8.W)))
-      (y, z) := Mux(sel, (a, b), (c, d))
+      (y, z).asData := Mux(sel, (a, b).asData, (c, d).asData)
     }
     // Verilog instead of CHIRRTL because the optimizations make it much prettier
     val verilog = ChiselStage.emitVerilog(new MyModule)
@@ -282,7 +282,7 @@ class DataViewSpec extends ChiselFlatSpec {
     class MyModule extends Module {
       val a, b, c, d = IO(Input(UInt(8.W)))
       val w, x, y, z = IO(Output(UInt(8.W)))
-      ((w, x), (y, z)) := ((a, b), (c, d))
+      ((w, x), (y, z)).asData := ((a, b), (c, d)).asData
     }
     val chirrtl = ChiselStage.emitChirrtl(new MyModule)
     chirrtl should include ("w <= a")
@@ -314,7 +314,7 @@ class DataViewSpec extends ChiselFlatSpec {
       // A little annoying that we need the type annotation on VecInit to get the implicit conversion to work
       // Note that one can just use the Seq on the RHS so there is an alternative (may lack discoverability)
       // We could also overload `VecInit` instead of relying on the implicit conversion
-      Seq((w, x), (y, z)) := VecInit[HWTuple2[UInt, UInt]]((a, b), (c, d))
+      Seq((w, x), (y, z)).asData := VecInit((a, b).asData, (c, d).asData)
     }
     val verilog = ChiselStage.emitVerilog(new MyModule)
     verilog should include ("assign w = a;")
@@ -334,8 +334,8 @@ class DataViewSpec extends ChiselFlatSpec {
 
       // Dynamic indexing is more of a "generator" in Chisel3 than an individual node
       val selected = Seq((a, b), (c, d)).apply(idx)
-      selected := (inA, inB)
-      (outA, outB) := selected
+      selected := (inA, inB).asData
+      (outA, outB).asData := selected
     }
     (the [InvalidViewException] thrownBy {
       ChiselStage.emitChirrtl(new MyModule)
diff --git a/src/test/scala/chiselTests/experimental/DataViewTargetSpec.scala b/src/test/scala/chiselTests/experimental/DataViewTargetSpec.scala
index a17b0f40..2e91d5df 100644
--- a/src/test/scala/chiselTests/experimental/DataViewTargetSpec.scala
+++ b/src/test/scala/chiselTests/experimental/DataViewTargetSpec.scala
@@ -134,15 +134,15 @@ class DataViewTargetSpec extends ChiselFlatSpec {
     // Note that each use of a Tuple as Data causes an implicit conversion creating a View
     class MyChild extends Module {
       val io = IO(new MyBundle)
-      (io.c, io.d) := (io.a, io.b)
+      (io.c, io.d).asData := (io.a, io.b).asData
       // The type annotations create the views via the implicit conversion
-      val view1: Data = (io.a, io.b)
-      val view2: Data = (io.c, io.d)
+      val view1: Data = (io.a, io.b).asData
+      val view2: Data = (io.c, io.d).asData
       mark(view1, 0)
       mark(view2, 1)
       markAbs(view1, 2)
       markAbs(view2, 3)
-      mark((io.b, io.d), 4) // Mix it up for fun
+      mark((io.b, io.d).asData, 4) // Mix it up for fun
     }
     class MyParent extends Module {
       val io = IO(new MyBundle)