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jacktasia/A systemverilog dumb-jump test

Last active May 12, 2018 15:29
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A systemverilog dumb-jump test
Raw
f1.sv
class foo;
some_package::some_class some_class_inst;
endclass
Raw
f2.sv
package some_package;
`include "some_class.sv"
endpackage
Raw
f3.sv
class some_class;
//class stuff
end class
Raw
Makefile
# dummy file so dumb-jump counts this a project
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