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jitdump.txt
****** START compiling Program:Main() (MethodHash=bef6ec1b)
Generating code for Unix x64
OPTIONS: compCodeOpt = BLENDED_CODE
OPTIONS: compDbgCode = false
OPTIONS: compDbgInfo = true
OPTIONS: compDbgEnC = false
OPTIONS: compProcedureSplitting = false
OPTIONS: compProcedureSplittingEH = false
OPTIONS: Stack probing is DISABLED
IL to import:
IL_0000 17 ldc.i4.1
IL_0001 12 00 ldloca.s 0x0
IL_0003 fe 15 02 00 00 02 initobj 0x2000002
IL_0009 06 ldloc.0
IL_000a 73 01 00 00 06 newobj 0x6000001
IL_000f 73 02 00 00 06 newobj 0x6000002
IL_0014 7b 04 00 00 04 ldfld 0x4000004
IL_0019 7b 01 00 00 04 ldfld 0x4000001
IL_001e 28 04 00 00 06 call 0x6000004
IL_0023 28 0b 00 00 0a call 0xA00000B
IL_0028 2a ret
lvaGrabTemp returning 1 (V01 tmp0) (a long lifetime temp) called for OutgoingArgSpace.
; Initial local variable assignments
;
; V00 loc0 struct ( 8)
; V01 OutArgs lclBlk (na)
*************** In compInitDebuggingInfo() for Program:Main()
getVars() returned cVars = 0, extendOthers = true
info.compVarScopesCount = 1
VarNum LVNum Name Beg End
0: 00h 00h V00 loc0 000h 029h
info.compStmtOffsetsCount = 0
info.compStmtOffsetsImplicit = 0005h ( STACK_EMPTY CALL_SITE )
*************** In fgFindBasicBlocks() for Program:Main()
Jump targets:
none
New Basic Block BB01 [0000] created.
BB01 [000..029)
IL Code Size,Instr 41, 11, Basic Block count 1, Local Variable Num,Ref count 2, 2 for method Program:Main()
OPTIONS: opts.MinOpts() == false
Basic block list for 'Program:Main()'
--------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd weight [IL range] [jump] [EH region] [flags]
--------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..029) (return)
--------------------------------------------------------------------------------------------------------------------------------------
*************** In impImport() for Program:Main()
impImportBlockPending for BB01
Importing BB01 (PC=000) of 'Program:Main()'
[ 0] 0 (0x000) ldc.i4.1 1
[ 1] 1 (0x001) ldloca.s 0
[ 2] 3 (0x003) initobj 02000002
[000006] ------------ ▌ STMT void (IL 0x000... ???)
[000004] ------------ │ ┌──▌ CNS_INT int 0
[000005] IA------R--- └──▌ ASG struct (init)
[000002] D------N---- └──▌ LCL_VAR struct V00 loc0
[ 1] 9 (0x009) ldloc.0
[ 2] 10 (0x00a) newobj
lvaGrabTemp returning 2 (V02 tmp1) called for NewObj constructor temp.
[000011] ------------ ▌ STMT void (IL ???... ???)
[000009] ------------ │ ┌──▌ CNS_INT int 0
[000010] IA------R--- └──▌ ASG struct (init)
[000008] D------N---- └──▌ LCL_VAR struct V02 tmp1
06000001
In Compiler::impImportCall: opcode is newobj, kind=0, callRetType is void, structSize is 0
Calling impNormStructVal on:
[000007] ------------ ▌ LCL_VAR struct V00 loc0
resulting tree:
[000016] x----------- ▌ OBJ(1) struct
[000015] L----------- └──▌ ADDR byref
[000007] ------------ └──▌ LCL_VAR struct V00 loc0
[000019] ------------ ▌ STMT void (IL ???... ???)
[000014] I-C-G------- └──▌ CALL void S3..ctor (exactContextHnd=0x00007F8FCABF5909)
[000013] L----------- this in rdi ├──▌ ADDR byref
[000012] ------------ │ └──▌ LCL_VAR struct V02 tmp1
[000001] ------------ arg1 ├──▌ CNS_INT int 1
[000016] x----------- arg2 └──▌ OBJ(1) struct
[000015] L----------- └──▌ ADDR byref
[000007] ------------ └──▌ LCL_VAR struct V00 loc0
[ 1] 15 (0x00f) newobj
lvaGrabTemp returning 3 (V03 tmp2) called for NewObj constructor temp.
[000024] ------------ ▌ STMT void (IL 0x00F... ???)
[000022] ------------ │ ┌──▌ CNS_INT int 0
[000023] IA------R--- └──▌ ASG struct (init)
[000021] D------N---- └──▌ LCL_VAR struct V03 tmp2
06000002
In Compiler::impImportCall: opcode is newobj, kind=0, callRetType is void, structSize is 0
Calling impNormStructVal on:
[000020] ------------ ▌ LCL_VAR struct V02 tmp1
resulting tree:
[000029] x----------- ▌ OBJ(24) struct
[000028] L----------- └──▌ ADDR byref
[000020] ------------ └──▌ LCL_VAR struct V02 tmp1
[000031] ------------ ▌ STMT void (IL ???... ???)
[000027] I-C-G------- └──▌ CALL void S5..ctor (exactContextHnd=0x00007F8FCABF5AA9)
[000026] L----------- this in rdi ├──▌ ADDR byref
[000025] ------------ │ └──▌ LCL_VAR struct V03 tmp2
[000029] x----------- arg1 └──▌ OBJ(24) struct
[000028] L----------- └──▌ ADDR byref
[000020] ------------ └──▌ LCL_VAR struct V02 tmp1
[ 1] 20 (0x014) ldfld 04000004
[ 1] 25 (0x019) ldfld 04000001
[ 1] 30 (0x01e) call 06000004
In Compiler::impImportCall: opcode is call, kind=0, callRetType is void, structSize is 0
INLINER: during 'impMarkInlineCandidate' result 'failed this callee' reason 'noinline per IL/cached result' for 'Program:Main()' calling 'Program:M()'
INLINER: during 'impMarkInlineCandidate' result 'failed this callee' reason 'noinline per IL/cached result'
lvaGrabTemp returning 4 (V04 tmp3) called for impAppendStmt.
[000041] ------------ ▌ STMT void (IL 0x014... ???)
[000036] ----G------- │ ┌──▌ FIELD int F1
[000035] ------------ │ │ └──▌ ADDR byref
[000034] ------------ │ │ └──▌ FIELD struct F0
[000033] L----------- │ │ └──▌ ADDR byref
[000032] ------------ │ │ └──▌ LCL_VAR struct V03 tmp2
[000040] -A--G------- └──▌ ASG int
[000039] D------N---- └──▌ LCL_VAR int V04 tmp3
[000038] ------------ ▌ STMT void (IL 0x014... ???)
[000037] --C-G------- └──▌ CALL void Program.M
[ 1] 35 (0x023) call 0A00000B (Implicit Tail call: prefixFlags |= PREFIX_TAILCALL_IMPLICIT)
In Compiler::impImportCall: opcode is call, kind=0, callRetType is void, structSize is 0
info.compCompHnd->canTailCall returned false for call [000043]
INLINER: during 'impMarkInlineCandidate' result 'failed this callee' reason 'noinline per IL/cached result' for 'Program:Main()' calling 'System.Console:WriteLine(int)'
INLINER: during 'impMarkInlineCandidate' result 'failed this callee' reason 'noinline per IL/cached result'
[000045] ------------ ▌ STMT void (IL 0x023... ???)
[000043] --C-G------- └──▌ CALL void System.Console.WriteLine
[000042] ------------ arg0 └──▌ LCL_VAR int V04 tmp3
[ 0] 40 (0x028) ret
[000047] ------------ ▌ STMT void (IL 0x028... ???)
[000046] ------------ └──▌ RETURN void
New BlockSet epoch 1, # of blocks (including unused BB00): 2, bitset array size: 1 (short)
*************** In fgMorph()
*************** In fgDebugCheckBBlist
*************** In fgInline()
Expanding INLINE_CANDIDATE in statement [000019] in BB01:
[000019] ------------ ▌ STMT void (IL ???... ???)
[000014] I-C-G------- └──▌ CALL void S3..ctor (exactContextHnd=0x00007F8FCABF5909)
[000013] L----------- this in rdi ├──▌ ADDR byref
[000012] ------------ │ └──▌ LCL_VAR struct V02 tmp1
[000001] ------------ arg1 ├──▌ CNS_INT int 1
[000016] x----------- arg2 └──▌ OBJ(1) struct
[000015] L----------- └──▌ ADDR byref
[000007] ------------ └──▌ LCL_VAR struct V00 loc0
thisArg: is a constant is byref to a struct local
[000013] L----------- ▌ ADDR byref
[000012] ------------ └──▌ LCL_VAR struct V02 tmp1
Argument #1: is a constant
[000001] ------------ ▌ CNS_INT int 1
Argument #2: has caller local ref
[000016] x----------- ▌ OBJ(1) struct
[000015] L----------- └──▌ ADDR byref
[000007] ------------ └──▌ LCL_VAR struct V00 loc0
INLINER: inlineInfo.tokenLookupContextHandle for S3:.ctor(int,struct):this set to 0x00007F8FCABF5909:
Invoking compiler for the inlinee method S3:.ctor(int,struct):this :
IL to import:
IL_0000 02 ldarg.0
IL_0001 fe 15 03 00 00 02 initobj 0x2000003
IL_0007 02 ldarg.0
IL_0008 03 ldarg.1
IL_0009 7d 01 00 00 04 stfld 0x4000001
IL_000e 02 ldarg.0
IL_000f 04 ldarg.2
IL_0010 7d 03 00 00 04 stfld 0x4000003
IL_0015 2a ret
INLINER impTokenLookupContextHandle for S3:.ctor(int,struct):this is 0x00007F8FCABF5909.
*************** In fgFindBasicBlocks() for S3:.ctor(int,struct):this
weight= 10 : state 3 [ ldarg.0 ]
weight= 55 : state 180 [ initobj ]
weight= 69 : state 226 [ ldarg.0 -> ldarg.1 -> stfld ]
weight= 98 : state 228 [ ldarg.0 -> ldarg.2 -> stfld ]
weight= 19 : state 42 [ ret ]
multiplier in instance constructors increased to 1.5.
Inline candidate is mostly loads and stores. Multiplier increased to 4.5.
Inline candidate callsite is boring. Multiplier increased to 5.8.
calleeNativeSizeEstimate=251
callsiteNativeSizeEstimate=145
benefit multiplier=5.8
threshold=841
Native estimate for function size is within threshold for inlining 25.1 <= 84.1 (multiplier = 5.8)
Jump targets:
none
New Basic Block BB02 [0001] created.
BB02 [000..016)
Basic block list for 'S3:.ctor(int,struct):this'
--------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd weight [IL range] [jump] [EH region] [flags]
--------------------------------------------------------------------------------------------------------------------------------------
BB02 [0001] 1 1 [000..016) (return)
--------------------------------------------------------------------------------------------------------------------------------------
*************** In impImport() for S3:.ctor(int,struct):this
impImportBlockPending for BB02
Importing BB02 (PC=000) of 'S3:.ctor(int,struct):this'
[ 0] 0 (0x000) ldarg.0
[ 1] 1 (0x001) initobj 02000003
[000053] ------------ ▌ STMT void
[000051] ------------ │ ┌──▌ CNS_INT int 0
[000052] IA------R--- └──▌ ASG struct (init)
[000050] D------N---- └──▌ LCL_VAR struct V02 tmp1
[ 0] 7 (0x007) ldarg.0
[ 1] 8 (0x008) ldarg.1
[ 2] 9 (0x009) stfld 04000001
[000059] ------------ ▌ STMT void
[000056] ------------ │ ┌──▌ CNS_INT int 1
[000058] -A---------- └──▌ ASG int
[000057] -------N---- └──▌ FIELD int F1
[000054] L----------- └──▌ ADDR byref
[000055] ------------ └──▌ LCL_VAR struct V02 tmp1
[ 0] 14 (0x00e) ldarg.0
[ 1] 15 (0x00f) ldarg.2
lvaGrabTemp returning 5 (V05 tmp4) called for Inlining Arg.
[ 2] 16 (0x010) stfld 04000003
[000067] ------------ ▌ STMT void
[000062] ------------ │ ┌──▌ LCL_VAR struct V05 tmp4
[000066] -A------R--- └──▌ ASG struct (copy)
[000065] ------------ └──▌ BLK(1) struct
[000064] ------------ └──▌ ADDR byref
[000063] ------------ └──▌ FIELD struct F6
[000060] L----------- └──▌ ADDR byref
[000061] ------------ └──▌ LCL_VAR struct V02 tmp1
[ 0] 21 (0x015) ret
----------- Statements (and blocks) added due to the inlining of call [000014] -----------
Arguments setup:
[000071] ------------ ▌ STMT void (IL ???... ???)
[000016] x----------- │ ┌──▌ OBJ(1) struct
[000015] L----------- │ │ └──▌ ADDR byref
[000007] ------------ │ │ └──▌ LCL_VAR struct V00 loc0
[000070] -A------R--- └──▌ ASG struct (copy)
[000068] D----------- └──▌ LCL_VAR struct V05 tmp4
Inlinee method body:
[000053] ------------ ▌ STMT void (IL ???... ???)
[000051] ------------ │ ┌──▌ CNS_INT int 0
[000052] IA------R--- └──▌ ASG struct (init)
[000050] D------N---- └──▌ LCL_VAR struct V02 tmp1
[000059] ------------ ▌ STMT void (IL ???... ???)
[000056] ------------ │ ┌──▌ CNS_INT int 1
[000058] -A---------- └──▌ ASG int
[000057] -------N---- └──▌ FIELD int F1
[000054] L----------- └──▌ ADDR byref
[000055] ------------ └──▌ LCL_VAR struct V02 tmp1
[000067] ------------ ▌ STMT void (IL ???... ???)
[000062] ------------ │ ┌──▌ LCL_VAR struct V05 tmp4
[000066] -A------R--- └──▌ ASG struct (copy)
[000065] ------------ └──▌ BLK(1) struct
[000064] ------------ └──▌ ADDR byref
[000063] ------------ └──▌ FIELD struct F6
[000060] L----------- └──▌ ADDR byref
[000061] ------------ └──▌ LCL_VAR struct V02 tmp1
fgInlineAppendStatements: no gc ref inline locals.
Successfully inlined S3:.ctor(int,struct):this (22 IL bytes) (depth 1) [profitable inline]
--------------------------------------------------------------------------------------------
INLINER: during 'fgInline' result 'success' reason 'profitable inline' for 'Program:Main()' calling 'S3:.ctor(int,struct):this'
INLINER: during 'fgInline' result 'success' reason 'profitable inline'
Expanding INLINE_CANDIDATE in statement [000031] in BB01:
[000031] ------------ ▌ STMT void (IL ???... ???)
[000027] I-C-G------- └──▌ CALL void S5..ctor (exactContextHnd=0x00007F8FCABF5AA9)
[000026] L----------- this in rdi ├──▌ ADDR byref
[000025] ------------ │ └──▌ LCL_VAR struct V03 tmp2
[000029] x----------- arg1 └──▌ OBJ(24) struct
[000028] L----------- └──▌ ADDR byref
[000020] ------------ └──▌ LCL_VAR struct V02 tmp1
thisArg: is a constant is byref to a struct local
[000026] L----------- ▌ ADDR byref
[000025] ------------ └──▌ LCL_VAR struct V03 tmp2
Argument #1:
[000029] x----------- ▌ OBJ(24) struct
[000028] L----------- └──▌ ADDR byref
[000020] ------------ └──▌ LCL_VAR struct V02 tmp1
INLINER: inlineInfo.tokenLookupContextHandle for S5:.ctor(struct):this set to 0x00007F8FCABF5AA9:
Invoking compiler for the inlinee method S5:.ctor(struct):this :
IL to import:
IL_0000 02 ldarg.0
IL_0001 fe 15 04 00 00 02 initobj 0x2000004
IL_0007 02 ldarg.0
IL_0008 03 ldarg.1
IL_0009 7d 04 00 00 04 stfld 0x4000004
IL_000e 2a ret
INLINER impTokenLookupContextHandle for S5:.ctor(struct):this is 0x00007F8FCABF5AA9.
*************** In fgFindBasicBlocks() for S5:.ctor(struct):this
Jump targets:
none
New Basic Block BB03 [0002] created.
BB03 [000..00F)
Basic block list for 'S5:.ctor(struct):this'
--------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd weight [IL range] [jump] [EH region] [flags]
--------------------------------------------------------------------------------------------------------------------------------------
BB03 [0002] 1 1 [000..00F) (return)
--------------------------------------------------------------------------------------------------------------------------------------
*************** In impImport() for S5:.ctor(struct):this
impImportBlockPending for BB03
Importing BB03 (PC=000) of 'S5:.ctor(struct):this'
[ 0] 0 (0x000) ldarg.0
[ 1] 1 (0x001) initobj 02000004
[000078] ------------ ▌ STMT void
[000076] ------------ │ ┌──▌ CNS_INT int 0
[000077] IA------R--- └──▌ ASG struct (init)
[000075] D------N---- └──▌ LCL_VAR struct V03 tmp2
[ 0] 7 (0x007) ldarg.0
[ 1] 8 (0x008) ldarg.1
lvaGrabTemp returning 6 (V06 tmp5) called for Inlining Arg.
[ 2] 9 (0x009) stfld 04000004
[000086] ------------ ▌ STMT void
[000081] ------------ │ ┌──▌ LCL_VAR struct V06 tmp5
[000085] -A------R--- └──▌ ASG struct (copy)
[000084] ------------ └──▌ BLK(24) struct
[000083] ------------ └──▌ ADDR byref
[000082] ------------ └──▌ FIELD struct F0
[000079] L----------- └──▌ ADDR byref
[000080] ------------ └──▌ LCL_VAR struct V03 tmp2
[ 0] 14 (0x00e) ret
----------- Statements (and blocks) added due to the inlining of call [000027] -----------
Arguments setup:
[000090] ------------ ▌ STMT void (IL ???... ???)
[000029] x----------- │ ┌──▌ OBJ(24) struct
[000028] L----------- │ │ └──▌ ADDR byref
[000020] ------------ │ │ └──▌ LCL_VAR struct V02 tmp1
[000089] -A------R--- └──▌ ASG struct (copy)
[000087] D----------- └──▌ LCL_VAR struct V06 tmp5
Inlinee method body:
[000078] ------------ ▌ STMT void (IL ???... ???)
[000076] ------------ │ ┌──▌ CNS_INT int 0
[000077] IA------R--- └──▌ ASG struct (init)
[000075] D------N---- └──▌ LCL_VAR struct V03 tmp2
[000086] ------------ ▌ STMT void (IL ???... ???)
[000081] ------------ │ ┌──▌ LCL_VAR struct V06 tmp5
[000085] -A------R--- └──▌ ASG struct (copy)
[000084] ------------ └──▌ BLK(24) struct
[000083] ------------ └──▌ ADDR byref
[000082] ------------ └──▌ FIELD struct F0
[000079] L----------- └──▌ ADDR byref
[000080] ------------ └──▌ LCL_VAR struct V03 tmp2
fgInlineAppendStatements: no gc ref inline locals.
Successfully inlined S5:.ctor(struct):this (15 IL bytes) (depth 1) [below ALWAYS_INLINE size]
--------------------------------------------------------------------------------------------
INLINER: during 'fgInline' result 'success' reason 'below ALWAYS_INLINE size' for 'Program:Main()' calling 'S5:.ctor(struct):this'
INLINER: during 'fgInline' result 'success' reason 'below ALWAYS_INLINE size'
*************** After fgInline()
--------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd weight [IL range] [jump] [EH region] [flags]
--------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..029) (return) i
--------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [000..029) (return), preds={} succs={}
***** BB01, stmt 1
[000006] ------------ ▌ STMT void (IL 0x000...0x004)
[000004] ------------ │ ┌──▌ CNS_INT int 0
[000005] IA------R--- └──▌ ASG struct (init)
[000002] D------N---- └──▌ LCL_VAR struct V00 loc0
***** BB01, stmt 2
[000011] ------------ ▌ STMT void (IL ???...0x028)
[000009] ------------ │ ┌──▌ CNS_INT int 0
[000010] IA------R--- └──▌ ASG struct (init)
[000008] D------N---- └──▌ LCL_VAR struct V02 tmp1
***** BB01, stmt 3
[000071] ------------ ▌ STMT void (IL ???... ???)
[000016] x----------- │ ┌──▌ OBJ(1) struct
[000015] L----------- │ │ └──▌ ADDR byref
[000007] ------------ │ │ └──▌ LCL_VAR struct V00 loc0
[000070] -A------R--- └──▌ ASG struct (copy)
[000068] D----------- └──▌ LCL_VAR struct V05 tmp4
***** BB01, stmt 4
[000053] ------------ ▌ STMT void (IL ???... ???)
[000051] ------------ │ ┌──▌ CNS_INT int 0
[000052] IA------R--- └──▌ ASG struct (init)
[000050] D------N---- └──▌ LCL_VAR struct V02 tmp1
***** BB01, stmt 5
[000059] ------------ ▌ STMT void (IL ???... ???)
[000056] ------------ │ ┌──▌ CNS_INT int 1
[000058] -A---------- └──▌ ASG int
[000057] -------N---- └──▌ FIELD int F1
[000054] L----------- └──▌ ADDR byref
[000055] ------------ └──▌ LCL_VAR struct V02 tmp1
***** BB01, stmt 6
[000067] ------------ ▌ STMT void (IL ???... ???)
[000062] ------------ │ ┌──▌ LCL_VAR struct V05 tmp4
[000066] -A------R--- └──▌ ASG struct (copy)
[000065] ------------ └──▌ BLK(1) struct
[000064] ------------ └──▌ ADDR byref
[000063] ------------ └──▌ FIELD struct F6
[000060] L----------- └──▌ ADDR byref
[000061] ------------ └──▌ LCL_VAR struct V02 tmp1
***** BB01, stmt 7
[000024] ------------ ▌ STMT void (IL 0x00F... ???)
[000022] ------------ │ ┌──▌ CNS_INT int 0
[000023] IA------R--- └──▌ ASG struct (init)
[000021] D------N---- └──▌ LCL_VAR struct V03 tmp2
***** BB01, stmt 8
[000090] ------------ ▌ STMT void (IL ???... ???)
[000029] x----------- │ ┌──▌ OBJ(24) struct
[000028] L----------- │ │ └──▌ ADDR byref
[000020] ------------ │ │ └──▌ LCL_VAR struct V02 tmp1
[000089] -A------R--- └──▌ ASG struct (copy)
[000087] D----------- └──▌ LCL_VAR struct V06 tmp5
***** BB01, stmt 9
[000078] ------------ ▌ STMT void (IL ???... ???)
[000076] ------------ │ ┌──▌ CNS_INT int 0
[000077] IA------R--- └──▌ ASG struct (init)
[000075] D------N---- └──▌ LCL_VAR struct V03 tmp2
***** BB01, stmt 10
[000086] ------------ ▌ STMT void (IL ???... ???)
[000081] ------------ │ ┌──▌ LCL_VAR struct V06 tmp5
[000085] -A------R--- └──▌ ASG struct (copy)
[000084] ------------ └──▌ BLK(24) struct
[000083] ------------ └──▌ ADDR byref
[000082] ------------ └──▌ FIELD struct F0
[000079] L----------- └──▌ ADDR byref
[000080] ------------ └──▌ LCL_VAR struct V03 tmp2
***** BB01, stmt 11
[000041] ------------ ▌ STMT void (IL 0x014... ???)
[000036] ----G------- │ ┌──▌ FIELD int F1
[000035] ------------ │ │ └──▌ ADDR byref
[000034] ------------ │ │ └──▌ FIELD struct F0
[000033] L----------- │ │ └──▌ ADDR byref
[000032] ------------ │ │ └──▌ LCL_VAR struct V03 tmp2
[000040] -A--G------- └──▌ ASG int
[000039] D------N---- └──▌ LCL_VAR int V04 tmp3
***** BB01, stmt 12
[000038] ------------ ▌ STMT void (IL 0x014... ???)
[000037] --C-G------- └──▌ CALL void Program.M
***** BB01, stmt 13
[000045] ------------ ▌ STMT void (IL 0x023... ???)
[000043] --C-G------- └──▌ CALL void System.Console.WriteLine
[000042] ------------ arg0 └──▌ LCL_VAR int V04 tmp3
***** BB01, stmt 14
[000047] ------------ ▌ STMT void (IL 0x028... ???)
[000046] ------------ └──▌ RETURN void
-------------------------------------------------------------------------------------------------------------------
*************** Exception Handling table is empty
**************** Inline Tree
Inlines into 06000003 Program:Main()
[1 IL=0010 TR=000014 06000001] [profitable inline] S3:.ctor(int,struct):this
[2 IL=0015 TR=000027 06000002] [below ALWAYS_INLINE size] S5:.ctor(struct):this
[0 IL=0030 TR=000037 06000004] [FAILED: noinline per IL/cached result] Program:M()
[0 IL=0035 TR=000043 06000081] [FAILED: noinline per IL/cached result] System.Console:WriteLine(int)
Budget: initialTime=183, finalTime=229, initialBudget=1830, currentBudget=1830
Budget: initialSize=1066, finalSize=1172
*************** After fgAddInternal()
--------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd weight [IL range] [jump] [EH region] [flags]
--------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..029) (return) i
--------------------------------------------------------------------------------------------------------------------------------------
*************** Exception Handling table is empty
*************** In fgDebugCheckBBlist
*************** In fgRemoveEmptyTry()
No EH in this method, nothing to remove.
*************** In fgRemoveEmptyFinally()
No EH in this method, nothing to remove.
*************** In fgMergeFinallyChains()
No EH in this method, nothing to merge.
*************** In fgCloneFinally()
No EH in this method, no cloning.
*************** In fgPromoteStructs()
lvaTable before fgPromoteStructs
; Initial local variable assignments
;
; V00 loc0 struct ( 8) ld-addr-op
; V01 OutArgs lclBlk (na)
; V02 tmp1 struct (24)
; V03 tmp2 struct (24)
; V04 tmp3 int
; V05 tmp4 struct ( 8)
; V06 tmp5 struct (24)
lvaTable after fgPromoteStructs
; Initial local variable assignments
;
; V00 loc0 struct ( 8) ld-addr-op
; V01 OutArgs lclBlk (na)
; V02 tmp1 struct (24)
; V03 tmp2 struct (24)
; V04 tmp3 int
; V05 tmp4 struct ( 8)
; V06 tmp5 struct (24)
*************** In fgMarkAddressExposedLocals()
*************** In fgMorphBlocks()
Morphing BB01 of 'Program:Main()'
fgMorphTree BB01, stmt 1 (before)
[000004] ------------ ┌──▌ CNS_INT int 0
[000005] IA------R--- ▌ ASG struct (init)
[000002] D------N---- └──▌ LCL_VAR struct V00 loc0
fgMorphInitBlock:
Local V00 should not be enregistered because: was accessed as a local field
fgMorphOneAsgBlock (after):
[000004] -----+------ ┌──▌ CNS_INT int 0
[000005] -A---------- ▌ ASG byte
[000093] x------N---- └──▌ IND byte
[000092] L----------- └──▌ ADDR byref
[000002] D----+-N---- └──▌ LCL_VAR struct V00 loc0
using oneAsgTree.
fgMorphTree BB01, stmt 1 (after)
[000004] -----+------ ┌──▌ CNS_INT int 0
[000005] -A---+------ ▌ ASG byte
[000093] x------N---- └──▌ IND byte
[000092] L----------- └──▌ ADDR byref
[000002] D----+-N---- └──▌ LCL_VAR struct V00 loc0
fgMorphTree BB01, stmt 2 (before)
[000009] ------------ ┌──▌ CNS_INT int 0
[000010] IA------R--- ▌ ASG struct (init)
[000008] D------N---- └──▌ LCL_VAR struct V02 tmp1
fgMorphInitBlock: this requires an InitBlock.
Local V02 should not be enregistered because: written in a block op
GenTreeNode creates assertion:
[000010] IA------R--- ▌ ASG struct (init)
In BB01 New Local Constant Assertion: V02 == 0 index=#01, mask=0000000000000001
fgMorphTree BB01, stmt 3 (before)
[000016] x----------- ┌──▌ OBJ(1) struct
[000015] L----------- │ └──▌ ADDR byref
[000007] ------------ │ └──▌ LCL_VAR struct V00 loc0
[000070] -A------R--- ▌ ASG struct (copy)
[000068] D----------- └──▌ LCL_VAR struct V05 tmp4
fgMorphCopyBlock:
Local V05 should not be enregistered because: was accessed as a local field
Local V00 should not be enregistered because: it is address exposed
fgMorphOneAsgBlock (after):
[000016] x----+------ ┌──▌ IND byte
[000015] L----+------ │ └──▌ ADDR byref
[000007] -----+-N---- │ └──▌ LCL_VAR struct(AX) V00 loc0
[000070] -A---------- ▌ ASG byte
[000095] x------N---- └──▌ IND byte
[000094] L----------- └──▌ ADDR byref
[000068] D----+-N---- └──▌ LCL_VAR struct V05 tmp4
using oneAsgTree.
fgMorphCopyBlock (after):
[000016] x----+------ ┌──▌ IND byte
[000015] L----+------ │ └──▌ ADDR byref
[000007] -----+-N---- │ └──▌ LCL_VAR struct(AX) V00 loc0
[000070] -A---------- ▌ ASG byte
[000095] x------N---- └──▌ IND byte
[000094] L----------- └──▌ ADDR byref
[000068] D----+-N---- └──▌ LCL_VAR struct V05 tmp4
fgMorphTree BB01, stmt 3 (after)
[000016] x----+------ ┌──▌ IND byte
[000015] L----+------ │ └──▌ ADDR byref
[000007] -----+-N---- │ └──▌ LCL_VAR struct(AX) V00 loc0
[000070] -A---+------ ▌ ASG byte
[000095] x------N---- └──▌ IND byte
[000094] L----------- └──▌ ADDR byref
[000068] D----+-N---- └──▌ LCL_VAR struct V05 tmp4
fgMorphTree BB01, stmt 4 (before)
[000051] ------------ ┌──▌ CNS_INT int 0
[000052] IA------R--- ▌ ASG struct (init)
[000050] D------N---- └──▌ LCL_VAR struct V02 tmp1
fgMorphInitBlock:
The assignment [000052] using V02 removes: Constant Assertion: V02 == 0
this requires an InitBlock.
Local V02 should not be enregistered because: written in a block op
GenTreeNode creates assertion:
[000052] IA------R--- ▌ ASG struct (init)
In BB01 New Local Constant Assertion: V02 == 0 index=#01, mask=0000000000000001
fgMorphTree BB01, stmt 5 (before)
[000056] ------------ ┌──▌ CNS_INT int 1
[000058] -A---------- ▌ ASG int
[000057] -------N---- └──▌ FIELD int F1
[000054] L----------- └──▌ ADDR byref
[000055] ------------ └──▌ LCL_VAR struct V02 tmp1
Local V02 should not be enregistered because: was accessed as a local field
The assignment [000058] using V02 removes: Constant Assertion: V02 == 0
fgMorphTree BB01, stmt 5 (after)
[000056] -----+------ ┌──▌ CNS_INT int 1
[000058] -A---+------ ▌ ASG int
[000055] U----+-N---- └──▌ LCL_FLD int V02 tmp1 [+0] Fseq[F1]
fgMorphTree BB01, stmt 6 (before)
[000062] ------------ ┌──▌ LCL_VAR struct V05 tmp4
[000066] -A------R--- ▌ ASG struct (copy)
[000065] ------------ └──▌ BLK(1) struct
[000064] ------------ └──▌ ADDR byref
[000063] ------------ └──▌ FIELD struct F6
[000060] L----------- └──▌ ADDR byref
[000061] ------------ └──▌ LCL_VAR struct V02 tmp1
Local V02 should not be enregistered because: was accessed as a local field
fgMorphCopyBlock:
Local V05 should not be enregistered because: it is address exposed
fgMorphOneAsgBlock (after):
[000099] x----------- ┌──▌ IND byte
[000098] L----------- │ └──▌ ADDR byref
[000062] -----+------ │ └──▌ LCL_VAR struct(AX) V05 tmp4
[000066] -A--G------- ▌ ASG byte
[000065] *---G+-N---- └──▌ IND byte
[000064] -----+------ └──▌ ADDR byref
[000061] U----+-N---- └──▌ LCL_FLD struct V02 tmp1 [+16] Fseq[F6]
using oneAsgTree.
fgMorphCopyBlock (after):
[000099] x----------- ┌──▌ IND byte
[000098] L----------- │ └──▌ ADDR byref
[000062] -----+------ │ └──▌ LCL_VAR struct(AX) V05 tmp4
[000066] -A--G------- ▌ ASG byte
[000065] *---G+-N---- └──▌ IND byte
[000064] -----+------ └──▌ ADDR byref
[000061] U----+-N---- └──▌ LCL_FLD struct V02 tmp1 [+16] Fseq[F6]
fgMorphTree BB01, stmt 6 (after)
[000099] x----------- ┌──▌ IND byte
[000098] L----------- │ └──▌ ADDR byref
[000062] -----+------ │ └──▌ LCL_VAR struct(AX) V05 tmp4
[000066] -A--G+------ ▌ ASG byte
[000065] *---G+-N---- └──▌ IND byte
[000064] -----+------ └──▌ ADDR byref
[000061] U----+-N---- └──▌ LCL_FLD struct V02 tmp1 [+16] Fseq[F6]
fgMorphTree BB01, stmt 7 (before)
[000022] ------------ ┌──▌ CNS_INT int 0
[000023] IA------R--- ▌ ASG struct (init)
[000021] D------N---- └──▌ LCL_VAR struct V03 tmp2
fgMorphInitBlock: this requires an InitBlock.
Local V03 should not be enregistered because: written in a block op
GenTreeNode creates assertion:
[000023] IA------R--- ▌ ASG struct (init)
In BB01 New Local Constant Assertion: V03 == 0 index=#01, mask=0000000000000001
fgMorphTree BB01, stmt 8 (before)
[000029] x----------- ┌──▌ OBJ(24) struct
[000028] L----------- │ └──▌ ADDR byref
[000020] ------------ │ └──▌ LCL_VAR struct V02 tmp1
[000089] -A------R--- ▌ ASG struct (copy)
[000087] D----------- └──▌ LCL_VAR struct V06 tmp5
fgMorphCopyBlock:block assignment to morph:
[000029] x----+------ ┌──▌ OBJ(24) struct
[000028] L----+------ │ └──▌ ADDR byref
[000020] -----+-N---- │ └──▌ LCL_VAR struct V02 tmp1
[000089] -A------R--- ▌ ASG struct (copy)
[000087] D----+-N---- └──▌ LCL_VAR struct V06 tmp5
with no promoted structs this requires a CopyBlock.
Local V06 should not be enregistered because: written in a block op
Local V02 should not be enregistered because: written in a block op
Replacing block node [000029] with lclVar V02
GenTreeNode creates assertion:
[000089] -A------R--- ▌ ASG struct (copy)
In BB01 New Local Copy Assertion: V06 == V02 index=#02, mask=0000000000000002
fgMorphTree BB01, stmt 8 (after)
[000020] -----+-N---- ┌──▌ LCL_VAR struct V02 tmp1
[000089] -A---+--R--- ▌ ASG struct (copy)
[000087] D----+-N---- └──▌ LCL_VAR struct V06 tmp5
fgMorphTree BB01, stmt 9 (before)
[000076] ------------ ┌──▌ CNS_INT int 0
[000077] IA------R--- ▌ ASG struct (init)
[000075] D------N---- └──▌ LCL_VAR struct V03 tmp2
fgMorphInitBlock:
The assignment [000077] using V03 removes: Constant Assertion: V03 == 0
this requires an InitBlock.
Local V03 should not be enregistered because: written in a block op
GenTreeNode creates assertion:
[000077] IA------R--- ▌ ASG struct (init)
In BB01 New Local Constant Assertion: V03 == 0 index=#02, mask=0000000000000002
fgMorphTree BB01, stmt 10 (before)
[000081] ------------ ┌──▌ LCL_VAR struct V06 tmp5
[000085] -A------R--- ▌ ASG struct (copy)
[000084] ------------ └──▌ BLK(24) struct
[000083] ------------ └──▌ ADDR byref
[000082] ------------ └──▌ FIELD struct F0
[000079] L----------- └──▌ ADDR byref
[000080] ------------ └──▌ LCL_VAR struct V03 tmp2
Local V03 should not be enregistered because: was accessed as a local field
The assignment [000084] using V03 removes: Constant Assertion: V03 == 0
Assertion prop in BB01:
Copy Assertion: V06 == V02 index=#01, mask=0000000000000001
[000081] ------------ ▌ LCL_VAR struct V02 tmp1
fgMorphCopyBlock:block assignment to morph:
[000081] -----+------ ┌──▌ LCL_VAR struct V02 tmp1
[000085] -A------R--- ▌ ASG struct (copy)
[000084] x----+------ └──▌ BLK(24) struct
[000083] -----+------ └──▌ ADDR byref
[000080] D----+-N---- └──▌ LCL_FLD struct V03 tmp2 [+0] Fseq[F0]
with no promoted structs this requires a CopyBlock.
Local V03 should not be enregistered because: written in a block op
Local V02 should not be enregistered because: written in a block op
fgMorphTree BB01, stmt 10 (after)
[000081] -----+------ ┌──▌ LCL_VAR struct V02 tmp1
[000085] -A---+--R--- ▌ ASG struct (copy)
[000084] x----+------ └──▌ BLK(24) struct
[000083] -----+------ └──▌ ADDR byref
[000080] D----+-N---- └──▌ LCL_FLD struct V03 tmp2 [+0] Fseq[F0]
fgMorphTree BB01, stmt 11 (before)
[000036] ----G------- ┌──▌ FIELD int F1
[000035] ------------ │ └──▌ ADDR byref
[000034] ------------ │ └──▌ FIELD struct F0
[000033] L----------- │ └──▌ ADDR byref
[000032] ------------ │ └──▌ LCL_VAR struct V03 tmp2
[000040] -A--G------- ▌ ASG int
[000039] D------N---- └──▌ LCL_VAR int V04 tmp3
Local V03 should not be enregistered because: was accessed as a local field
GenTreeNode creates assertion:
[000040] -A--G------- ▌ ASG int
In BB01 New Local Subrange Assertion: V04 in [-2147483648..2147483647] index=#02, mask=0000000000000002
fgMorphTree BB01, stmt 11 (after)
[000032] -----+------ ┌──▌ LCL_FLD int V03 tmp2 [+0] Fseq[F0, F1]
[000040] -A--G+------ ▌ ASG int
[000039] D----+-N---- └──▌ LCL_VAR int V04 tmp3
fgMorphTree BB01, stmt 12 (before)
[000037] --C-G------- ▌ CALL void Program.M
argSlots=0, preallocatedArgCount=0, nextSlotNum=0, outgoingArgSpaceSize=0
fgMorphTree BB01, stmt 13 (before)
[000043] --C-G------- ▌ CALL void System.Console.WriteLine
[000042] ------------ arg0 └──▌ LCL_VAR int V04 tmp3
argSlots=1, preallocatedArgCount=0, nextSlotNum=0, outgoingArgSpaceSize=0
Sorting the arguments:
Deferred argument ('rdi'):
[000042] -----+------ ▌ LCL_VAR int V04 tmp3
Replaced with placeholder node:
[000100] ----------L- ▌ ARGPLACE int
Shuffled argument table: rdi
fgArgTabEntry[arg 0 42.LCL_VAR, 1 reg: rdi, align=1, lateArgInx=0, processed]
fgMorphTree BB01, stmt 13 (after)
[000043] --CXG+------ ▌ CALL void System.Console.WriteLine
[000042] -----+------ arg0 in rdi └──▌ LCL_VAR int V04 tmp3
fgMorphTree BB01, stmt 14 (before)
[000046] ------------ ▌ RETURN void
Renumbering the basic blocks for fgComputePred
*************** Before renumbering the basic blocks
--------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd weight [IL range] [jump] [EH region] [flags]
--------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..029) (return) i gcsafe
--------------------------------------------------------------------------------------------------------------------------------------
*************** Exception Handling table is empty
*************** After renumbering the basic blocks
=============== No blocks renumbered!
New BlockSet epoch 2, # of blocks (including unused BB00): 2, bitset array size: 1 (short)
*************** In fgComputePreds()
--------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd weight [IL range] [jump] [EH region] [flags]
--------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..029) (return) i gcsafe
--------------------------------------------------------------------------------------------------------------------------------------
*************** After fgComputePreds()
--------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
--------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..029) (return) i label target gcsafe
--------------------------------------------------------------------------------------------------------------------------------------
*************** In fgComputeEdgeWeights()
fgComputeEdgeWeights() we do not have any profile data so we are not using the edge weights
--------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
--------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..029) (return) i label target gcsafe
--------------------------------------------------------------------------------------------------------------------------------------
fgComputeEdgeWeights() was able to compute exact edge weights for all of the 0 edges, using 1 passes.
*************** In fgCreateFunclets()
After fgCreateFunclets()
--------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
--------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..029) (return) i label target gcsafe
--------------------------------------------------------------------------------------------------------------------------------------
*************** Exception Handling table is empty
*************** In fgDebugCheckBBlist
*************** In optOptimizeLayout()
*************** Exception Handling table is empty
*************** In fgDebugCheckBBlist
*************** In fgUpdateFlowGraph()
Before updating the flow graph:
--------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
--------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..029) (return) i label target gcsafe
--------------------------------------------------------------------------------------------------------------------------------------
*************** In fgDebugCheckBBlist
*************** In fgUpdateFlowGraph()
Before updating the flow graph:
--------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
--------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..029) (return) i label target gcsafe
--------------------------------------------------------------------------------------------------------------------------------------
*************** In fgDebugCheckBBlist
*************** In fgComputeReachability
*************** In fgDebugCheckBBlist
Renumbering the basic blocks for fgComputeReachability pass #1
*************** Before renumbering the basic blocks
--------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
--------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..029) (return) i label target gcsafe
--------------------------------------------------------------------------------------------------------------------------------------
*************** Exception Handling table is empty
*************** After renumbering the basic blocks
=============== No blocks renumbered!
Enter blocks: BB01
After computing reachability sets:
------------------------------------------------
BBnum Reachable by
------------------------------------------------
BB01 : BB01
After computing reachability:
--------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
--------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..029) (return) i label target gcsafe
--------------------------------------------------------------------------------------------------------------------------------------
*************** In fgDebugCheckBBlist
*************** In fgComputeDoms
*************** In fgDebugCheckBBlist
Dominator computation start blocks (those blocks with no incoming edges):
BB01
------------------------------------------------
BBnum Dominated by
------------------------------------------------
BB01: BB01
Inside fgBuildDomTree
After computing the Dominance Tree:
*************** In Allocate Objects
Trees before Allocate Objects
--------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
--------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..029) (return) i label target gcsafe
--------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [000..029) (return), preds={} succs={}
***** BB01, stmt 1
[000006] ------------ ▌ STMT void (IL 0x000...0x004)
[000004] -----+------ │ ┌──▌ CNS_INT int 0
[000005] -A---+------ └──▌ ASG byte
[000093] x------N---- └──▌ IND byte
[000092] L----------- └──▌ ADDR byref
[000002] D----+-N---- └──▌ LCL_VAR struct(AX) V00 loc0
***** BB01, stmt 2
[000011] ------------ ▌ STMT void (IL ???...0x028)
[000009] -----+------ │ ┌──▌ CNS_INT int 0
[000010] IA---+--R--- └──▌ ASG struct (init)
[000008] D----+-N---- └──▌ LCL_VAR struct V02 tmp1
***** BB01, stmt 3
[000071] ------------ ▌ STMT void (IL ???... ???)
[000016] x----+------ │ ┌──▌ IND byte
[000015] L----+------ │ │ └──▌ ADDR byref
[000007] -----+-N---- │ │ └──▌ LCL_VAR struct(AX) V00 loc0
[000070] -A---+------ └──▌ ASG byte
[000095] x------N---- └──▌ IND byte
[000094] L----------- └──▌ ADDR byref
[000068] D----+-N---- └──▌ LCL_VAR struct(AX) V05 tmp4
***** BB01, stmt 4
[000053] ------------ ▌ STMT void (IL ???... ???)
[000051] -----+------ │ ┌──▌ CNS_INT int 0
[000052] IA---+--R--- └──▌ ASG struct (init)
[000050] D----+-N---- └──▌ LCL_VAR struct V02 tmp1
***** BB01, stmt 5
[000059] ------------ ▌ STMT void (IL ???... ???)
[000056] -----+------ │ ┌──▌ CNS_INT int 1
[000058] -A---+------ └──▌ ASG int
[000055] U----+-N---- └──▌ LCL_FLD int V02 tmp1 [+0] Fseq[F1]
***** BB01, stmt 6
[000067] ------------ ▌ STMT void (IL ???... ???)
[000099] x----------- │ ┌──▌ IND byte
[000098] L----------- │ │ └──▌ ADDR byref
[000062] -----+------ │ │ └──▌ LCL_VAR struct(AX) V05 tmp4
[000066] -A--G+------ └──▌ ASG byte
[000065] *---G+-N---- └──▌ IND byte
[000064] -----+------ └──▌ ADDR byref
[000061] U----+-N---- └──▌ LCL_FLD struct V02 tmp1 [+16] Fseq[F6]
***** BB01, stmt 7
[000024] ------------ ▌ STMT void (IL 0x00F... ???)
[000022] -----+------ │ ┌──▌ CNS_INT int 0
[000023] IA---+--R--- └──▌ ASG struct (init)
[000021] D----+-N---- └──▌ LCL_VAR struct V03 tmp2
***** BB01, stmt 8
[000090] ------------ ▌ STMT void (IL ???... ???)
[000020] -----+-N---- │ ┌──▌ LCL_VAR struct V02 tmp1
[000089] -A---+--R--- └──▌ ASG struct (copy)
[000087] D----+-N---- └──▌ LCL_VAR struct V06 tmp5
***** BB01, stmt 9
[000078] ------------ ▌ STMT void (IL ???... ???)
[000076] -----+------ │ ┌──▌ CNS_INT int 0
[000077] IA---+--R--- └──▌ ASG struct (init)
[000075] D----+-N---- └──▌ LCL_VAR struct V03 tmp2
***** BB01, stmt 10
[000086] ------------ ▌ STMT void (IL ???... ???)
[000081] -----+------ │ ┌──▌ LCL_VAR struct V02 tmp1
[000085] -A---+--R--- └──▌ ASG struct (copy)
[000084] x----+------ └──▌ BLK(24) struct
[000083] -----+------ └──▌ ADDR byref
[000080] D----+-N---- └──▌ LCL_FLD struct V03 tmp2 [+0] Fseq[F0]
***** BB01, stmt 11
[000041] ------------ ▌ STMT void (IL 0x014... ???)
[000032] -----+------ │ ┌──▌ LCL_FLD int V03 tmp2 [+0] Fseq[F0, F1]
[000040] -A--G+------ └──▌ ASG int
[000039] D----+-N---- └──▌ LCL_VAR int V04 tmp3
***** BB01, stmt 12
[000038] ------------ ▌ STMT void (IL 0x014... ???)
[000037] --CXG+------ └──▌ CALL void Program.M
***** BB01, stmt 13
[000045] ------------ ▌ STMT void (IL 0x023... ???)
[000043] --CXG+------ └──▌ CALL void System.Console.WriteLine
[000042] -----+------ arg0 in rdi └──▌ LCL_VAR int V04 tmp3
***** BB01, stmt 14
[000047] ------------ ▌ STMT void (IL 0x028... ???)
[000046] -----+------ └──▌ RETURN void
-------------------------------------------------------------------------------------------------------------------
*************** Exiting Allocate Objects
Trees after Allocate Objects
--------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
--------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..029) (return) i label target gcsafe
--------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [000..029) (return), preds={} succs={}
***** BB01, stmt 1
[000006] ------------ ▌ STMT void (IL 0x000...0x004)
[000004] -----+------ │ ┌──▌ CNS_INT int 0
[000005] -A---+------ └──▌ ASG byte
[000093] x------N---- └──▌ IND byte
[000092] L----------- └──▌ ADDR byref
[000002] D----+-N---- └──▌ LCL_VAR struct(AX) V00 loc0
***** BB01, stmt 2
[000011] ------------ ▌ STMT void (IL ???...0x028)
[000009] -----+------ │ ┌──▌ CNS_INT int 0
[000010] IA---+--R--- └──▌ ASG struct (init)
[000008] D----+-N---- └──▌ LCL_VAR struct V02 tmp1
***** BB01, stmt 3
[000071] ------------ ▌ STMT void (IL ???... ???)
[000016] x----+------ │ ┌──▌ IND byte
[000015] L----+------ │ │ └──▌ ADDR byref
[000007] -----+-N---- │ │ └──▌ LCL_VAR struct(AX) V00 loc0
[000070] -A---+------ └──▌ ASG byte
[000095] x------N---- └──▌ IND byte
[000094] L----------- └──▌ ADDR byref
[000068] D----+-N---- └──▌ LCL_VAR struct(AX) V05 tmp4
***** BB01, stmt 4
[000053] ------------ ▌ STMT void (IL ???... ???)
[000051] -----+------ │ ┌──▌ CNS_INT int 0
[000052] IA---+--R--- └──▌ ASG struct (init)
[000050] D----+-N---- └──▌ LCL_VAR struct V02 tmp1
***** BB01, stmt 5
[000059] ------------ ▌ STMT void (IL ???... ???)
[000056] -----+------ │ ┌──▌ CNS_INT int 1
[000058] -A---+------ └──▌ ASG int
[000055] U----+-N---- └──▌ LCL_FLD int V02 tmp1 [+0] Fseq[F1]
***** BB01, stmt 6
[000067] ------------ ▌ STMT void (IL ???... ???)
[000099] x----------- │ ┌──▌ IND byte
[000098] L----------- │ │ └──▌ ADDR byref
[000062] -----+------ │ │ └──▌ LCL_VAR struct(AX) V05 tmp4
[000066] -A--G+------ └──▌ ASG byte
[000065] *---G+-N---- └──▌ IND byte
[000064] -----+------ └──▌ ADDR byref
[000061] U----+-N---- └──▌ LCL_FLD struct V02 tmp1 [+16] Fseq[F6]
***** BB01, stmt 7
[000024] ------------ ▌ STMT void (IL 0x00F... ???)
[000022] -----+------ │ ┌──▌ CNS_INT int 0
[000023] IA---+--R--- └──▌ ASG struct (init)
[000021] D----+-N---- └──▌ LCL_VAR struct V03 tmp2
***** BB01, stmt 8
[000090] ------------ ▌ STMT void (IL ???... ???)
[000020] -----+-N---- │ ┌──▌ LCL_VAR struct V02 tmp1
[000089] -A---+--R--- └──▌ ASG struct (copy)
[000087] D----+-N---- └──▌ LCL_VAR struct V06 tmp5
***** BB01, stmt 9
[000078] ------------ ▌ STMT void (IL ???... ???)
[000076] -----+------ │ ┌──▌ CNS_INT int 0
[000077] IA---+--R--- └──▌ ASG struct (init)
[000075] D----+-N---- └──▌ LCL_VAR struct V03 tmp2
***** BB01, stmt 10
[000086] ------------ ▌ STMT void (IL ???... ???)
[000081] -----+------ │ ┌──▌ LCL_VAR struct V02 tmp1
[000085] -A---+--R--- └──▌ ASG struct (copy)
[000084] x----+------ └──▌ BLK(24) struct
[000083] -----+------ └──▌ ADDR byref
[000080] D----+-N---- └──▌ LCL_FLD struct V03 tmp2 [+0] Fseq[F0]
***** BB01, stmt 11
[000041] ------------ ▌ STMT void (IL 0x014... ???)
[000032] -----+------ │ ┌──▌ LCL_FLD int V03 tmp2 [+0] Fseq[F0, F1]
[000040] -A--G+------ └──▌ ASG int
[000039] D----+-N---- └──▌ LCL_VAR int V04 tmp3
***** BB01, stmt 12
[000038] ------------ ▌ STMT void (IL 0x014... ???)
[000037] --CXG+------ └──▌ CALL void Program.M
***** BB01, stmt 13
[000045] ------------ ▌ STMT void (IL 0x023... ???)
[000043] --CXG+------ └──▌ CALL void System.Console.WriteLine
[000042] -----+------ arg0 in rdi └──▌ LCL_VAR int V04 tmp3
***** BB01, stmt 14
[000047] ------------ ▌ STMT void (IL 0x028... ???)
[000046] -----+------ └──▌ RETURN void
-------------------------------------------------------------------------------------------------------------------
*************** In fgDebugCheckBBlist
*************** In optOptimizeLoops()
*************** In fgDebugCheckBBlist
*************** In optCloneLoops()
*************** In lvaMarkLocalVars()
*** marking local variables in block BB01 (weight=1 )
[000006] ------------ ▌ STMT void (IL 0x000...0x004)
[000004] -----+------ │ ┌──▌ CNS_INT int 0
[000005] -A---+------ └──▌ ASG byte
[000093] x------N---- └──▌ IND byte
[000092] L----------- └──▌ ADDR byref
[000002] D----+-N---- └──▌ LCL_VAR struct(AX) V00 loc0
New refCnts for V00: refCnt = 1, refCntWtd = 1
[000011] ------------ ▌ STMT void (IL ???...0x028)
[000009] -----+------ │ ┌──▌ CNS_INT int 0
[000010] IA---+--R--- └──▌ ASG struct (init)
[000008] D----+-N---- └──▌ LCL_VAR struct V02 tmp1
New refCnts for V02: refCnt = 1, refCntWtd = 2
[000071] ------------ ▌ STMT void (IL ???... ???)
[000016] x----+------ │ ┌──▌ IND byte
[000015] L----+------ │ │ └──▌ ADDR byref
[000007] -----+-N---- │ │ └──▌ LCL_VAR struct(AX) V00 loc0
[000070] -A---+------ └──▌ ASG byte
[000095] x------N---- └──▌ IND byte
[000094] L----------- └──▌ ADDR byref
[000068] D----+-N---- └──▌ LCL_VAR struct(AX) V05 tmp4
New refCnts for V05: refCnt = 1, refCntWtd = 2
New refCnts for V00: refCnt = 2, refCntWtd = 2
[000053] ------------ ▌ STMT void (IL ???... ???)
[000051] -----+------ │ ┌──▌ CNS_INT int 0
[000052] IA---+--R--- └──▌ ASG struct (init)
[000050] D----+-N---- └──▌ LCL_VAR struct V02 tmp1
New refCnts for V02: refCnt = 2, refCntWtd = 4
[000059] ------------ ▌ STMT void (IL ???... ???)
[000056] -----+------ │ ┌──▌ CNS_INT int 1
[000058] -A---+------ └──▌ ASG int
[000055] U----+-N---- └──▌ LCL_FLD int V02 tmp1 [+0] Fseq[F1]
New refCnts for V02: refCnt = 3, refCntWtd = 6
[000067] ------------ ▌ STMT void (IL ???... ???)
[000099] x----------- │ ┌──▌ IND byte
[000098] L----------- │ │ └──▌ ADDR byref
[000062] -----+------ │ │ └──▌ LCL_VAR struct(AX) V05 tmp4
[000066] -A--G+------ └──▌ ASG byte
[000065] *---G+-N---- └──▌ IND byte
[000064] -----+------ └──▌ ADDR byref
[000061] U----+-N---- └──▌ LCL_FLD struct V02 tmp1 [+16] Fseq[F6]
New refCnts for V02: refCnt = 4, refCntWtd = 8
New refCnts for V05: refCnt = 2, refCntWtd = 4
[000024] ------------ ▌ STMT void (IL 0x00F... ???)
[000022] -----+------ │ ┌──▌ CNS_INT int 0
[000023] IA---+--R--- └──▌ ASG struct (init)
[000021] D----+-N---- └──▌ LCL_VAR struct V03 tmp2
New refCnts for V03: refCnt = 1, refCntWtd = 2
[000090] ------------ ▌ STMT void (IL ???... ???)
[000020] -----+-N---- │ ┌──▌ LCL_VAR struct V02 tmp1
[000089] -A---+--R--- └──▌ ASG struct (copy)
[000087] D----+-N---- └──▌ LCL_VAR struct V06 tmp5
New refCnts for V06: refCnt = 1, refCntWtd = 2
New refCnts for V02: refCnt = 5, refCntWtd = 10
[000078] ------------ ▌ STMT void (IL ???... ???)
[000076] -----+------ │ ┌──▌ CNS_INT int 0
[000077] IA---+--R--- └──▌ ASG struct (init)
[000075] D----+-N---- └──▌ LCL_VAR struct V03 tmp2
New refCnts for V03: refCnt = 2, refCntWtd = 4
[000086] ------------ ▌ STMT void (IL ???... ???)
[000081] -----+------ │ ┌──▌ LCL_VAR struct V02 tmp1
[000085] -A---+--R--- └──▌ ASG struct (copy)
[000084] x----+------ └──▌ BLK(24) struct
[000083] -----+------ └──▌ ADDR byref
[000080] D----+-N---- └──▌ LCL_FLD struct V03 tmp2 [+0] Fseq[F0]
New refCnts for V03: refCnt = 3, refCntWtd = 6
New refCnts for V02: refCnt = 6, refCntWtd = 12
[000041] ------------ ▌ STMT void (IL 0x014... ???)
[000032] -----+------ │ ┌──▌ LCL_FLD int V03 tmp2 [+0] Fseq[F0, F1]
[000040] -A--G+------ └──▌ ASG int
[000039] D----+-N---- └──▌ LCL_VAR int V04 tmp3
New refCnts for V04: refCnt = 1, refCntWtd = 2
New refCnts for V03: refCnt = 4, refCntWtd = 8
[000038] ------------ ▌ STMT void (IL 0x014... ???)
[000037] --CXG+------ └──▌ CALL void Program.M
[000045] ------------ ▌ STMT void (IL 0x023... ???)
[000043] --CXG+------ └──▌ CALL void System.Console.WriteLine
[000042] -----+------ arg0 in rdi └──▌ LCL_VAR int V04 tmp3
New refCnts for V04: refCnt = 2, refCntWtd = 4
[000047] ------------ ▌ STMT void (IL 0x028... ???)
[000046] -----+------ └──▌ RETURN void
*************** In optAddCopies()
Local V02 should not be enregistered because: it is a struct
Local V03 should not be enregistered because: it is a struct
Local V06 should not be enregistered because: it is a struct
refCnt table for 'Main':
V02 tmp1 [struct]: refCnt = 6, refCntWtd = 12
V03 tmp2 [struct]: refCnt = 4, refCntWtd = 8
V04 tmp3 [ int]: refCnt = 2, refCntWtd = 4
V06 tmp5 [struct]: refCnt = 1, refCntWtd = 2
V05 tmp4 [struct]: refCnt = 2, refCntWtd = 4
V00 loc0 [struct]: refCnt = 2, refCntWtd = 2
V01 OutArgs [lclBlk]: refCnt = 1, refCntWtd = 1
*************** In optOptimizeBools()
*************** In fgDebugCheckBBlist
*************** In fgFindOperOrder()
*************** In fgSetBlockOrder()
The biggest BB has 7 tree nodes
--------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
--------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..029) (return) i label target gcsafe
--------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [000..029) (return), preds={} succs={}
***** BB01, stmt 1
( 9, 8) [000006] ------------ ▌ STMT void (IL 0x000...0x004)
N001 ( 1, 1) [000004] ------------ │ ┌──▌ CNS_INT int 0
N005 ( 9, 8) [000005] -A------R--- └──▌ ASG byte
N004 ( 7, 6) [000093] x------N---- └──▌ IND byte
N003 ( 3, 3) [000092] L----------- └──▌ ADDR byref
N002 ( 3, 2) [000002] D------N---- └──▌ LCL_VAR struct(AX) V00 loc0
***** BB01, stmt 2
( 5, 4) [000011] ------------ ▌ STMT void (IL ???...0x028)
N001 ( 1, 1) [000009] ------------ │ ┌──▌ CNS_INT int 0
N003 ( 5, 4) [000010] IA------R--- └──▌ ASG struct (init)
N002 ( 3, 2) [000008] D------N---- └──▌ LCL_VAR struct V02 tmp1
***** BB01, stmt 3
( 15, 13) [000071] ------------ ▌ STMT void (IL ???... ???)
N003 ( 7, 6) [000016] x----------- │ ┌──▌ IND byte
N002 ( 3, 3) [000015] L----------- │ │ └──▌ ADDR byref
N001 ( 3, 2) [000007] -------N---- │ │ └──▌ LCL_VAR struct(AX) V00 loc0
N007 ( 15, 13) [000070] -A------R--- └──▌ ASG byte
N006 ( 7, 6) [000095] x------N---- └──▌ IND byte
N005 ( 3, 3) [000094] L----------- └──▌ ADDR byref
N004 ( 3, 2) [000068] D------N---- └──▌ LCL_VAR struct(AX) V05 tmp4
***** BB01, stmt 4
( 5, 4) [000053] ------------ ▌ STMT void (IL ???... ???)
N001 ( 1, 1) [000051] ------------ │ ┌──▌ CNS_INT int 0
N003 ( 5, 4) [000052] IA------R--- └──▌ ASG struct (init)
N002 ( 3, 2) [000050] D------N---- └──▌ LCL_VAR struct V02 tmp1
***** BB01, stmt 5
( 5, 6) [000059] ------------ ▌ STMT void (IL ???... ???)
N001 ( 1, 1) [000056] ------------ │ ┌──▌ CNS_INT int 1
N003 ( 5, 6) [000058] -A------R--- └──▌ ASG int
N002 ( 3, 4) [000055] U------N---- └──▌ LCL_FLD int V02 tmp1 [+0] Fseq[F1]
***** BB01, stmt 6
( 15, 15) [000067] ------------ ▌ STMT void (IL ???... ???)
N003 ( 7, 6) [000099] x----------- │ ┌──▌ IND byte
N002 ( 3, 3) [000098] L----------- │ │ └──▌ ADDR byref
N001 ( 3, 2) [000062] ------------ │ │ └──▌ LCL_VAR struct(AX) V05 tmp4
N007 ( 15, 15) [000066] -A--G---R--- └──▌ ASG byte
N006 ( 7, 8) [000065] *---G--N---- └──▌ IND byte
N005 ( 3, 5) [000064] ------------ └──▌ ADDR byref
N004 ( 3, 4) [000061] U------N---- └──▌ LCL_FLD struct V02 tmp1 [+16] Fseq[F6]
***** BB01, stmt 7
( 5, 4) [000024] ------------ ▌ STMT void (IL 0x00F... ???)
N001 ( 1, 1) [000022] ------------ │ ┌──▌ CNS_INT int 0
N003 ( 5, 4) [000023] IA------R--- └──▌ ASG struct (init)
N002 ( 3, 2) [000021] D------N---- └──▌ LCL_VAR struct V03 tmp2
***** BB01, stmt 8
( 7, 5) [000090] ------------ ▌ STMT void (IL ???... ???)
N001 ( 3, 2) [000020] -------N---- │ ┌──▌ LCL_VAR struct V02 tmp1
N003 ( 7, 5) [000089] -A------R--- └──▌ ASG struct (copy)
N002 ( 3, 2) [000087] D------N---- └──▌ LCL_VAR struct V06 tmp5
***** BB01, stmt 9
( 5, 4) [000078] ------------ ▌ STMT void (IL ???... ???)
N001 ( 1, 1) [000076] ------------ │ ┌──▌ CNS_INT int 0
N003 ( 5, 4) [000077] IA------R--- └──▌ ASG struct (init)
N002 ( 3, 2) [000075] D------N---- └──▌ LCL_VAR struct V03 tmp2
***** BB01, stmt 10
( 10, 10) [000086] ------------ ▌ STMT void (IL ???... ???)
N001 ( 3, 2) [000081] ------------ │ ┌──▌ LCL_VAR struct V02 tmp1
N005 ( 10, 10) [000085] -A------R--- └──▌ ASG struct (copy)
N004 ( 6, 7) [000084] x----------- └──▌ BLK(24) struct
N003 ( 3, 5) [000083] ------------ └──▌ ADDR byref
N002 ( 3, 4) [000080] D------N---- └──▌ LCL_FLD struct V03 tmp2 [+0] Fseq[F0]
***** BB01, stmt 11
( 3, 4) [000041] ------------ ▌ STMT void (IL 0x014... ???)
N001 ( 3, 4) [000032] ------------ │ ┌──▌ LCL_FLD int V03 tmp2 [+0] Fseq[F0, F1]
N003 ( 3, 4) [000040] -A--G---R--- └──▌ ASG int
N002 ( 1, 1) [000039] D------N---- └──▌ LCL_VAR int V04 tmp3
***** BB01, stmt 12
( 14, 5) [000038] ------------ ▌ STMT void (IL 0x014... ???)
N001 ( 14, 5) [000037] --CXG------- └──▌ CALL void Program.M
***** BB01, stmt 13
( 15, 7) [000045] ------------ ▌ STMT void (IL 0x023... ???)
N005 ( 15, 7) [000043] --CXG------- └──▌ CALL void System.Console.WriteLine
N003 ( 1, 1) [000042] ------------ arg0 in rdi └──▌ LCL_VAR int V04 tmp3
***** BB01, stmt 14
( 0, 0) [000047] ------------ ▌ STMT void (IL 0x028... ???)
N001 ( 0, 0) [000046] ------------ └──▌ RETURN void
-------------------------------------------------------------------------------------------------------------------
*************** In SsaBuilder::Build()
[SsaBuilder] Max block count is 2.
--------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
--------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..029) (return) i label target gcsafe
--------------------------------------------------------------------------------------------------------------------------------------
*************** Exception Handling table is empty
[SsaBuilder] Topologically sorted the graph.
[SsaBuilder::ComputeImmediateDom]
*************** In SsaBuilder::ComputeDominators(BasicBlock** postOrder, int count, ...)
*************** In SsaBuilder::InsertPhiFunctions()
*************** In fgLocalVarLiveness()
*************** In fgPerBlockLocalVarLiveness()
BB01 USE(0)={ } + ByrefExposed + GcHeap
DEF(4)={V02 V03 V04 V06} + ByrefExposed* + GcHeap*
** Memory liveness computed, GcHeap states and ByrefExposed states diverge
*************** In fgInterBlockLocalVarLiveness()
BB liveness after fgLiveVarAnalysis():
BB01 IN (0)={} + ByrefExposed + GcHeap
OUT(0)={}
top level assign
removing stmt with no side effects
Removing statement [000078] in BB01 as useless:
( 5, 4) [000078] ------------ ▌ STMT void (IL ???... ???)
N001 ( 1, 1) [000076] ------------ │ ┌──▌ CNS_INT int 0
N003 ( 5, 4) [000077] IA------R--- └──▌ ASG struct (init)
N002 ( 3, 2) [000075] D------N---- └──▌ LCL_VAR struct V03 tmp2
New refCnts for V03: refCnt = 3, refCntWtd = 6
top level assign
removing stmt with no side effects
Removing statement [000090] in BB01 as useless:
( 7, 5) [000090] ------------ ▌ STMT void (IL ???... ???)
N001 ( 3, 2) [000020] -------N---- │ ┌──▌ LCL_VAR struct V02 tmp1
N003 ( 7, 5) [000089] -A------R--- └──▌ ASG struct (copy)
N002 ( 3, 2) [000087] D------N---- └──▌ LCL_VAR struct V06 tmp5
New refCnts for V06: refCnt = 0, refCntWtd = 0
New refCnts for V02: refCnt = 5, refCntWtd = 10
top level assign
removing stmt with no side effects
Removing statement [000024] in BB01 as useless:
( 5, 4) [000024] ------------ ▌ STMT void (IL 0x00F... ???)
N001 ( 1, 1) [000022] ------------ │ ┌──▌ CNS_INT int 0
N003 ( 5, 4) [000023] IA------R--- └──▌ ASG struct (init)
N002 ( 3, 2) [000021] D------N---- └──▌ LCL_VAR struct V03 tmp2
New refCnts for V03: refCnt = 2, refCntWtd = 4
top level assign
removing stmt with no side effects
Removing statement [000011] in BB01 as useless:
( 5, 4) [000011] ------------ ▌ STMT void (IL ???...0x028)
N001 ( 1, 1) [000009] ------------ │ ┌──▌ CNS_INT int 0
N003 ( 5, 4) [000010] IA------R--- └──▌ ASG struct (init)
N002 ( 3, 2) [000008] D------N---- └──▌ LCL_VAR struct V02 tmp1
New refCnts for V02: refCnt = 4, refCntWtd = 8
In fgLocalVarLiveness, setting lvaSortAgain back to false (set during dead-code removal)
Inserting phi functions:
*************** In SsaBuilder::RenameVariables()
After fgSsaBuild:
--------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
--------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..029) (return) i label target gcsafe
--------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [000..029) (return), preds={} succs={}
***** BB01, stmt 1
( 9, 8) [000006] ------------ ▌ STMT void (IL 0x000...0x004)
N001 ( 1, 1) [000004] ------------ │ ┌──▌ CNS_INT int 0
N005 ( 9, 8) [000005] -A------R--- └──▌ ASG byte
N004 ( 7, 6) [000093] x------N---- └──▌ IND byte
N003 ( 3, 3) [000092] L----------- └──▌ ADDR byref
N002 ( 3, 2) [000002] D------N---- └──▌ LCL_VAR struct(AX) V00 loc0
***** BB01, stmt 2
( 15, 13) [000071] ------------ ▌ STMT void (IL ???... ???)
N003 ( 7, 6) [000016] x----------- │ ┌──▌ IND byte
N002 ( 3, 3) [000015] L----------- │ │ └──▌ ADDR byref
N001 ( 3, 2) [000007] -------N---- │ │ └──▌ LCL_VAR struct(AX) V00 loc0
N007 ( 15, 13) [000070] -A------R--- └──▌ ASG byte
N006 ( 7, 6) [000095] x------N---- └──▌ IND byte
N005 ( 3, 3) [000094] L----------- └──▌ ADDR byref
N004 ( 3, 2) [000068] D------N---- └──▌ LCL_VAR struct(AX) V05 tmp4
***** BB01, stmt 3
( 5, 4) [000053] ------------ ▌ STMT void (IL ???... ???)
N001 ( 1, 1) [000051] ------------ │ ┌──▌ CNS_INT int 0
N003 ( 5, 4) [000052] IA------R--- └──▌ ASG struct (init)
N002 ( 3, 2) [000050] D------N---- └──▌ LCL_VAR struct V02 tmp1 d:3
***** BB01, stmt 4
( 5, 6) [000059] ------------ ▌ STMT void (IL ???... ???)
N001 ( 1, 1) [000056] ------------ │ ┌──▌ CNS_INT int 1
N003 ( 5, 6) [000058] -A------R--- └──▌ ASG int
N002 ( 3, 4) [000055] U------N---- └──▌ LCL_FLD int V02 tmp1 ud:3->4[+0] Fseq[F1]
***** BB01, stmt 5
( 15, 15) [000067] ------------ ▌ STMT void (IL ???... ???)
N003 ( 7, 6) [000099] x----------- │ ┌──▌ IND byte
N002 ( 3, 3) [000098] L----------- │ │ └──▌ ADDR byref
N001 ( 3, 2) [000062] ------------ │ │ └──▌ LCL_VAR struct(AX) V05 tmp4
N007 ( 15, 15) [000066] -A--G---R--- └──▌ ASG byte
N006 ( 7, 8) [000065] *---G--N---- └──▌ IND byte
N005 ( 3, 5) [000064] ------------ └──▌ ADDR byref
N004 ( 3, 4) [000061] U------N---- └──▌ LCL_FLD struct V02 tmp1 ud:4->5[+16] Fseq[F6]
***** BB01, stmt 6
( 10, 10) [000086] ------------ ▌ STMT void (IL ???... ???)
N001 ( 3, 2) [000081] ------------ │ ┌──▌ LCL_VAR struct V02 tmp1 u:5 (last use)
N005 ( 10, 10) [000085] -A------R--- └──▌ ASG struct (copy)
N004 ( 6, 7) [000084] x----------- └──▌ BLK(24) struct
N003 ( 3, 5) [000083] ------------ └──▌ ADDR byref
N002 ( 3, 4) [000080] D------N---- └──▌ LCL_FLD struct V03 tmp2 d:3[+0] Fseq[F0]
***** BB01, stmt 7
( 3, 4) [000041] ------------ ▌ STMT void (IL 0x014... ???)
N001 ( 3, 4) [000032] ------------ │ ┌──▌ LCL_FLD int V03 tmp2 u:3[+0] Fseq[F0, F1] (last use)
N003 ( 3, 4) [000040] -A--G---R--- └──▌ ASG int
N002 ( 1, 1) [000039] D------N---- └──▌ LCL_VAR int V04 tmp3 d:3
***** BB01, stmt 8
( 14, 5) [000038] ------------ ▌ STMT void (IL 0x014... ???)
N001 ( 14, 5) [000037] --CXG------- └──▌ CALL void Program.M
***** BB01, stmt 9
( 15, 7) [000045] ------------ ▌ STMT void (IL 0x023... ???)
N005 ( 15, 7) [000043] --CXG------- └──▌ CALL void System.Console.WriteLine
N003 ( 1, 1) [000042] ------------ arg0 in rdi └──▌ LCL_VAR int V04 tmp3 u:3 (last use)
***** BB01, stmt 10
( 0, 0) [000047] ------------ ▌ STMT void (IL 0x028... ???)
N001 ( 0, 0) [000046] ------------ └──▌ RETURN void
-------------------------------------------------------------------------------------------------------------------
*************** In optEarlyProp()
*************** In fgValueNumber()
Memory Initial Value in BB01 is: $c0
The SSA definition for ByrefExposed (#2) at start of BB01 is $c0 {InitVal($81)}
The SSA definition for GcHeap (#2) at start of BB01 is $c0 {InitVal($81)}
***** BB01, stmt 1 (before)
N001 ( 1, 1) [000004] ------------ ┌──▌ CNS_INT int 0
N005 ( 9, 8) [000005] -A------R--- ▌ ASG byte
N004 ( 7, 6) [000093] x------N---- └──▌ IND byte
N003 ( 3, 3) [000092] L----------- └──▌ ADDR byref
N002 ( 3, 2) [000002] D------N---- └──▌ LCL_VAR struct(AX) V00 loc0
N001 [000004] CNS_INT 0 => $80 {IntCns 0}
N003 [000092] ADDR => $100 {100}
VNForCastOper(byte) is $82
fgCurMemoryVN[ByrefExposed] assigned by PtrToLoc indir at [000005] to VN: $41.
N005 [000005] ASG => $VN.Void
***** BB01, stmt 1 (after)
N001 ( 1, 1) [000004] ------------ ┌──▌ CNS_INT int 0 $80
N005 ( 9, 8) [000005] -A------R--- ▌ ASG byte $VN.Void
N004 ( 7, 6) [000093] x------N---- └──▌ IND byte $80
N003 ( 3, 3) [000092] L----------- └──▌ ADDR byref $100
N002 ( 3, 2) [000002] D------N---- └──▌ LCL_VAR struct(AX) V00 loc0
---------
***** BB01, stmt 2 (before)
N003 ( 7, 6) [000016] x----------- ┌──▌ IND byte
N002 ( 3, 3) [000015] L----------- │ └──▌ ADDR byref
N001 ( 3, 2) [000007] -------N---- │ └──▌ LCL_VAR struct(AX) V00 loc0
N007 ( 15, 13) [000070] -A------R--- ▌ ASG byte
N006 ( 7, 6) [000095] x------N---- └──▌ IND byte
N005 ( 3, 3) [000094] L----------- └──▌ ADDR byref
N004 ( 3, 2) [000068] D------N---- └──▌ LCL_VAR struct(AX) V05 tmp4
N001 [000007] LCL_VAR V00 loc0 => $180 {ByrefExposedLoad($83, $140, $41)}
N002 [000015] ADDR => $101 {101}
N003 [000016] IND => <l:$1c0 {ByrefExposedLoad($84, $101, $41)}, c:$200 {200}>
N005 [000094] ADDR => $102 {102}
fgCurMemoryVN[ByrefExposed] assigned by PtrToLoc indir at [000070] to VN: $42.
N007 [000070] ASG => $VN.Void
***** BB01, stmt 2 (after)
N003 ( 7, 6) [000016] x----------- ┌──▌ IND byte <l:$1c0, c:$200>
N002 ( 3, 3) [000015] L----------- │ └──▌ ADDR byref $101
N001 ( 3, 2) [000007] -------N---- │ └──▌ LCL_VAR struct(AX) V00 loc0 $180
N007 ( 15, 13) [000070] -A------R--- ▌ ASG byte $VN.Void
N006 ( 7, 6) [000095] x------N---- └──▌ IND byte <l:$1c0, c:$200>
N005 ( 3, 3) [000094] L----------- └──▌ ADDR byref $102
N004 ( 3, 2) [000068] D------N---- └──▌ LCL_VAR struct(AX) V05 tmp4
---------
***** BB01, stmt 3 (before)
N001 ( 1, 1) [000051] ------------ ┌──▌ CNS_INT int 0
N003 ( 5, 4) [000052] IA------R--- ▌ ASG struct (init)
N002 ( 3, 2) [000050] D------N---- └──▌ LCL_VAR struct V02 tmp1 d:3
N001 [000051] CNS_INT 0 => $80 {IntCns 0}
N003 [000052] ASG V02/3 => $VN.ZeroMap
N003 [000052] ASG => $VN.Void
***** BB01, stmt 3 (after)
N001 ( 1, 1) [000051] ------------ ┌──▌ CNS_INT int 0 $80
N003 ( 5, 4) [000052] IA------R--- ▌ ASG struct (init) $VN.Void
N002 ( 3, 2) [000050] D------N---- └──▌ LCL_VAR struct V02 tmp1 d:3
---------
***** BB01, stmt 4 (before)
N001 ( 1, 1) [000056] ------------ ┌──▌ CNS_INT int 1
N003 ( 5, 6) [000058] -A------R--- ▌ ASG int
N002 ( 3, 4) [000055] U------N---- └──▌ LCL_FLD int V02 tmp1 ud:3->4[+0] Fseq[F1]
N001 [000056] CNS_INT 1 => $85 {IntCns 1}
VNApplySelectors:
VNForHandle(Fseq[F1]) is $280, fieldType is int
VNForMapSelect($1, $280):int returns $80 {IntCns 0}
VNApplySelectors:
VNForHandle(Fseq[F1]) is $280, fieldType is int
VNForMapSelect($1, $280):int returns $80 {IntCns 0}
N002 [000055] LCL_FLD V02 tmp1 ud:3->4[+0] Fseq[F1] => $80 {IntCns 0}
fieldHnd $280 is {Hnd const: 0x00007F8FCABF5828}
fieldSeq $2c0 is {F1}
VNForMapStore($1, $280, $85):int returns $300 {$VN.ZeroMap[$280 := $85]}
fieldHnd $280 is {Hnd const: 0x00007F8FCABF5828}
fieldSeq $2c0 is {F1}
VNForMapStore($1, $280, $85):int returns $300 {$VN.ZeroMap[$280 := $85]}
N002 [000055] LCL_FLD V02 tmp1 ud:3->4[+0] Fseq[F1] => $300 {$VN.ZeroMap[$280 := $85]}
N003 [000058] ASG => $85 {IntCns 1}
***** BB01, stmt 4 (after)
N001 ( 1, 1) [000056] ------------ ┌──▌ CNS_INT int 1 $85
N003 ( 5, 6) [000058] -A------R--- ▌ ASG int $85
N002 ( 3, 4) [000055] U------N---- └──▌ LCL_FLD int V02 tmp1 ud:3->4[+0] Fseq[F1] $300
---------
***** BB01, stmt 5 (before)
N003 ( 7, 6) [000099] x----------- ┌──▌ IND byte
N002 ( 3, 3) [000098] L----------- │ └──▌ ADDR byref
N001 ( 3, 2) [000062] ------------ │ └──▌ LCL_VAR struct(AX) V05 tmp4
N007 ( 15, 15) [000066] -A--G---R--- ▌ ASG byte
N006 ( 7, 8) [000065] *---G--N---- └──▌ IND byte
N005 ( 3, 5) [000064] ------------ └──▌ ADDR byref
N004 ( 3, 4) [000061] U------N---- └──▌ LCL_FLD struct V02 tmp1 ud:4->5[+16] Fseq[F6]
N001 [000062] LCL_VAR V05 tmp4 => $181 {ByrefExposedLoad($83, $141, $42)}
N002 [000098] ADDR => $103 {103}
N003 [000099] IND => <l:$1c1 {ByrefExposedLoad($84, $103, $42)}, c:$201 {201}>
VNApplySelectors:
VNForHandle(Fseq[F6]) is $281, fieldType is struct, size = 1
AX2: $281 != $280 ==> select([$300]store($1, $280, $85), $281) ==> select($1, $281).
VNForMapSelect($300, $281):struct returns $VN.ZeroMap
*** Mismatched types in VNApplySelectorsTypeCheck (indType is TYP_STRUCT)
VNApplySelectors:
VNForHandle(Fseq[F6]) is $281, fieldType is struct, size = 1
AX2: $281 != $280 ==> select([$300]store($1, $280, $85), $281) ==> select($1, $281).
VNForMapSelect($300, $281):struct returns $VN.ZeroMap
*** Mismatched types in VNApplySelectorsTypeCheck (indType is TYP_STRUCT)
N004 [000061] LCL_FLD V02 tmp1 ud:4->5[+16] Fseq[F6] => <l:$340 {340}, c:$341 {341}>
fieldHnd $281 is {Hnd const: 0x00007F8FCABF5858}
fieldSeq $2c1 is {F6}
N005 [000064] ADDR => $142 {PtrToLoc($87, $2c1)}
fieldHnd $281 is {Hnd const: 0x00007F8FCABF5858}
fieldSeq $2c1 is {F6}
VNForMapStore($300, $281, $1c1):struct returns $182 {$300[$281 := $1c1]}
fieldHnd $281 is {Hnd const: 0x00007F8FCABF5858}
fieldSeq $2c1 is {F6}
VNForMapStore($300, $281, $201):struct returns $183 {$300[$281 := $201]}
Tree [000066] assigned VN to local var V02/5: VN <l:$182 {$300[$281 := $1c1]}, c:$183 {$300[$281 := $201]}>
N007 [000066] ASG => $VN.Void
***** BB01, stmt 5 (after)
N003 ( 7, 6) [000099] x----------- ┌──▌ IND byte <l:$1c1, c:$201>
N002 ( 3, 3) [000098] L----------- │ └──▌ ADDR byref $103
N001 ( 3, 2) [000062] ------------ │ └──▌ LCL_VAR struct(AX) V05 tmp4 $181
N007 ( 15, 15) [000066] -A--G---R--- ▌ ASG byte $VN.Void
N006 ( 7, 8) [000065] *---G--N---- └──▌ IND byte <l:$1c1, c:$201>
N005 ( 3, 5) [000064] ------------ └──▌ ADDR byref $142
N004 ( 3, 4) [000061] U------N---- └──▌ LCL_FLD struct V02 tmp1 ud:4->5[+16] Fseq[F6] <l:$340, c:$341>
---------
***** BB01, stmt 6 (before)
N001 ( 3, 2) [000081] ------------ ┌──▌ LCL_VAR struct V02 tmp1 u:5 (last use)
N005 ( 10, 10) [000085] -A------R--- ▌ ASG struct (copy)
N004 ( 6, 7) [000084] x----------- └──▌ BLK(24) struct
N003 ( 3, 5) [000083] ------------ └──▌ ADDR byref
N002 ( 3, 4) [000080] D------N---- └──▌ LCL_FLD struct V03 tmp2 d:3[+0] Fseq[F0]
N001 [000081] LCL_VAR V02 tmp1 u:5 (last use) => <l:$182 {$300[$281 := $1c1]}, c:$183 {$300[$281 := $201]}>
fieldHnd $282 is {Hnd const: 0x00007F8FCABF59F8}
fieldSeq $2c2 is {F0}
N003 [000083] ADDR => $143 {PtrToLoc($84, $2c2)}
Tree [000085] assigned VN to local var V03/3: <l:$182 {$300[$281 := $1c1]}, c:$183 {$300[$281 := $201]}>
N005 [000085] ASG => $VN.Void
***** BB01, stmt 6 (after)
N001 ( 3, 2) [000081] ------------ ┌──▌ LCL_VAR struct V02 tmp1 u:5 (last use) <l:$182, c:$183>
N005 ( 10, 10) [000085] -A------R--- ▌ ASG struct (copy) $VN.Void
N004 ( 6, 7) [000084] x----------- └──▌ BLK(24) struct
N003 ( 3, 5) [000083] ------------ └──▌ ADDR byref $143
N002 ( 3, 4) [000080] D------N---- └──▌ LCL_FLD struct V03 tmp2 d:3[+0] Fseq[F0]
---------
***** BB01, stmt 7 (before)
N001 ( 3, 4) [000032] ------------ ┌──▌ LCL_FLD int V03 tmp2 u:3[+0] Fseq[F0, F1] (last use)
N003 ( 3, 4) [000040] -A--G---R--- ▌ ASG int
N002 ( 1, 1) [000039] D------N---- └──▌ LCL_VAR int V04 tmp3 d:3
VNApplySelectors:
VNForHandle(Fseq[F0]) is $282, fieldType is struct, size = 24
AX2: $282 != $281 ==> select([$182]store($300, $281, $1c1), $282) ==> select($300, $282).
AX2: $282 != $280 ==> select([$300]store($1, $280, $85), $282) ==> select($1, $282).
VNForMapSelect($182, $282):struct returns $VN.ZeroMap
VNApplySelectors:
VNForHandle(Fseq[F1]) is $280, fieldType is int
VNForMapSelect($1, $280):int returns $80 {IntCns 0}
VNApplySelectors:
VNForHandle(Fseq[F0]) is $282, fieldType is struct, size = 24
AX2: $282 != $281 ==> select([$183]store($300, $281, $201), $282) ==> select($300, $282).
AX2: $282 != $280 ==> select([$300]store($1, $280, $85), $282) ==> select($1, $282).
VNForMapSelect($183, $282):struct returns $VN.ZeroMap
VNApplySelectors:
VNForHandle(Fseq[F1]) is $280, fieldType is int
VNForMapSelect($1, $280):int returns $80 {IntCns 0}
N001 [000032] LCL_FLD V03 tmp2 u:3[+0] Fseq[F0, F1] (last use) => $80 {IntCns 0}
N002 [000039] LCL_VAR V04 tmp3 d:3 => $80 {IntCns 0}
N003 [000040] ASG => $80 {IntCns 0}
***** BB01, stmt 7 (after)
N001 ( 3, 4) [000032] ------------ ┌──▌ LCL_FLD int V03 tmp2 u:3[+0] Fseq[F0, F1] (last use) $80
N003 ( 3, 4) [000040] -A--G---R--- ▌ ASG int $80
N002 ( 1, 1) [000039] D------N---- └──▌ LCL_VAR int V04 tmp3 d:3 $80
---------
***** BB01, stmt 8 (before)
N001 ( 14, 5) [000037] --CXG------- ▌ CALL void Program.M
fgCurMemoryVN[GcHeap] assigned by CALL at [000037] to VN: $3c0.
N001 [000037] CALL => $VN.Void
***** BB01, stmt 8 (after)
N001 ( 14, 5) [000037] --CXG------- ▌ CALL void Program.M $VN.Void
---------
***** BB01, stmt 9 (before)
N005 ( 15, 7) [000043] --CXG------- ▌ CALL void System.Console.WriteLine
N003 ( 1, 1) [000042] ------------ arg0 in rdi └──▌ LCL_VAR int V04 tmp3 u:3 (last use)
N001 [000100] ARGPLACE => $381 {381}
N002 [000044] LIST => $400 {LIST($381, $0)}
N003 [000042] LCL_VAR V04 tmp3 u:3 (last use) => $80 {IntCns 0}
N004 [000101] LIST => $401 {LIST($80, $0)}
VN of ARGPLACE tree [000100] updated to $80 {IntCns 0}
N002 [000044] LIST => $401 {LIST($80, $0)}
fgCurMemoryVN[GcHeap] assigned by CALL at [000043] to VN: $3c1.
N005 [000043] CALL => $VN.Void
***** BB01, stmt 9 (after)
N005 ( 15, 7) [000043] --CXG------- ▌ CALL void System.Console.WriteLine $VN.Void
N003 ( 1, 1) [000042] ------------ arg0 in rdi └──▌ LCL_VAR int V04 tmp3 u:3 (last use) $80
---------
***** BB01, stmt 10 (before)
N001 ( 0, 0) [000046] ------------ ▌ RETURN void
N001 [000046] RETURN => $440 {440}
***** BB01, stmt 10 (after)
N001 ( 0, 0) [000046] ------------ ▌ RETURN void $440
finish(BB01).
*************** In optVnCopyProp()
*************** In SsaBuilder::ComputeDominators(Compiler*, ...)
Copy Assertion for BB01
curSsaName stack: { }
Live vars: {} => {V02}
Live vars: {V02} => {}
Live vars: {} => {V03}
Live vars: {V03} => {}
Live vars: {} => {V04}
Live vars: {V04} => {}
*************** In optOptimizeCSEs()
Blocks/Trees at start of optOptimizeCSE phase
--------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
--------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..029) (return) i label target gcsafe
--------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [000..029) (return), preds={} succs={}
***** BB01, stmt 1
( 9, 8) [000006] ------------ ▌ STMT void (IL 0x000...0x004)
N001 ( 1, 1) [000004] ------------ │ ┌──▌ CNS_INT int 0 $80
N005 ( 9, 8) [000005] -A------R--- └──▌ ASG byte $VN.Void
N004 ( 7, 6) [000093] x------N---- └──▌ IND byte $80
N003 ( 3, 3) [000092] L----------- └──▌ ADDR byref $100
N002 ( 3, 2) [000002] D------N---- └──▌ LCL_VAR struct(AX) V00 loc0
***** BB01, stmt 2
( 15, 13) [000071] ------------ ▌ STMT void (IL ???... ???)
N003 ( 7, 6) [000016] x----------- │ ┌──▌ IND byte <l:$1c0, c:$200>
N002 ( 3, 3) [000015] L----------- │ │ └──▌ ADDR byref $101
N001 ( 3, 2) [000007] -------N---- │ │ └──▌ LCL_VAR struct(AX) V00 loc0 $180
N007 ( 15, 13) [000070] -A------R--- └──▌ ASG byte $VN.Void
N006 ( 7, 6) [000095] x------N---- └──▌ IND byte <l:$1c0, c:$200>
N005 ( 3, 3) [000094] L----------- └──▌ ADDR byref $102
N004 ( 3, 2) [000068] D------N---- └──▌ LCL_VAR struct(AX) V05 tmp4
***** BB01, stmt 3
( 5, 4) [000053] ------------ ▌ STMT void (IL ???... ???)
N001 ( 1, 1) [000051] ------------ │ ┌──▌ CNS_INT int 0 $80
N003 ( 5, 4) [000052] IA------R--- └──▌ ASG struct (init) $VN.Void
N002 ( 3, 2) [000050] D------N---- └──▌ LCL_VAR struct V02 tmp1 d:3
***** BB01, stmt 4
( 5, 6) [000059] ------------ ▌ STMT void (IL ???... ???)
N001 ( 1, 1) [000056] ------------ │ ┌──▌ CNS_INT int 1 $85
N003 ( 5, 6) [000058] -A------R--- └──▌ ASG int $85
N002 ( 3, 4) [000055] U------N---- └──▌ LCL_FLD int V02 tmp1 ud:3->4[+0] Fseq[F1] $300
***** BB01, stmt 5
( 15, 15) [000067] ------------ ▌ STMT void (IL ???... ???)
N003 ( 7, 6) [000099] x----------- │ ┌──▌ IND byte <l:$1c1, c:$201>
N002 ( 3, 3) [000098] L----------- │ │ └──▌ ADDR byref $103
N001 ( 3, 2) [000062] ------------ │ │ └──▌ LCL_VAR struct(AX) V05 tmp4 $181
N007 ( 15, 15) [000066] -A--G---R--- └──▌ ASG byte $VN.Void
N006 ( 7, 8) [000065] *---G--N---- └──▌ IND byte <l:$1c1, c:$201>
N005 ( 3, 5) [000064] ------------ └──▌ ADDR byref $142
N004 ( 3, 4) [000061] U------N---- └──▌ LCL_FLD struct V02 tmp1 ud:4->5[+16] Fseq[F6] <l:$340, c:$341>
***** BB01, stmt 6
( 10, 10) [000086] ------------ ▌ STMT void (IL ???... ???)
N001 ( 3, 2) [000081] ------------ │ ┌──▌ LCL_VAR struct V02 tmp1 u:5 (last use) <l:$182, c:$183>
N005 ( 10, 10) [000085] -A------R--- └──▌ ASG struct (copy) $VN.Void
N004 ( 6, 7) [000084] x----------- └──▌ BLK(24) struct
N003 ( 3, 5) [000083] ------------ └──▌ ADDR byref $143
N002 ( 3, 4) [000080] D------N---- └──▌ LCL_FLD struct V03 tmp2 d:3[+0] Fseq[F0]
***** BB01, stmt 7
( 3, 4) [000041] ------------ ▌ STMT void (IL 0x014... ???)
N001 ( 3, 4) [000032] ------------ │ ┌──▌ LCL_FLD int V03 tmp2 u:3[+0] Fseq[F0, F1] (last use) $80
N003 ( 3, 4) [000040] -A--G---R--- └──▌ ASG int $80
N002 ( 1, 1) [000039] D------N---- └──▌ LCL_VAR int V04 tmp3 d:3 $80
***** BB01, stmt 8
( 14, 5) [000038] ------------ ▌ STMT void (IL 0x014... ???)
N001 ( 14, 5) [000037] --CXG------- └──▌ CALL void Program.M $VN.Void
***** BB01, stmt 9
( 15, 7) [000045] ------------ ▌ STMT void (IL 0x023... ???)
N005 ( 15, 7) [000043] --CXG------- └──▌ CALL void System.Console.WriteLine $VN.Void
N003 ( 1, 1) [000042] ------------ arg0 in rdi └──▌ LCL_VAR int V04 tmp3 u:3 (last use) $80
***** BB01, stmt 10
( 0, 0) [000047] ------------ ▌ STMT void (IL 0x028... ???)
N001 ( 0, 0) [000046] ------------ └──▌ RETURN void $440
-------------------------------------------------------------------------------------------------------------------
*************** In optOptimizeValnumCSEs()
*************** In optAssertionPropMain()
Blocks/Trees at start of phase
--------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
--------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..029) (return) i label target gcsafe
--------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [000..029) (return), preds={} succs={}
***** BB01, stmt 1
( 9, 8) [000006] ------------ ▌ STMT void (IL 0x000...0x004)
N001 ( 1, 1) [000004] ------------ │ ┌──▌ CNS_INT int 0 $80
N005 ( 9, 8) [000005] -A------R--- └──▌ ASG byte $VN.Void
N004 ( 7, 6) [000093] x------N---- └──▌ IND byte $80
N003 ( 3, 3) [000092] L----------- └──▌ ADDR byref $100
N002 ( 3, 2) [000002] D------N---- └──▌ LCL_VAR struct(AX) V00 loc0
***** BB01, stmt 2
( 15, 13) [000071] ------------ ▌ STMT void (IL ???... ???)
N003 ( 7, 6) [000016] x----------- │ ┌──▌ IND byte <l:$1c0, c:$200>
N002 ( 3, 3) [000015] L----------- │ │ └──▌ ADDR byref $101
N001 ( 3, 2) [000007] -------N---- │ │ └──▌ LCL_VAR struct(AX) V00 loc0 $180
N007 ( 15, 13) [000070] -A------R--- └──▌ ASG byte $VN.Void
N006 ( 7, 6) [000095] x------N---- └──▌ IND byte <l:$1c0, c:$200>
N005 ( 3, 3) [000094] L----------- └──▌ ADDR byref $102
N004 ( 3, 2) [000068] D------N---- └──▌ LCL_VAR struct(AX) V05 tmp4
***** BB01, stmt 3
( 5, 4) [000053] ------------ ▌ STMT void (IL ???... ???)
N001 ( 1, 1) [000051] ------------ │ ┌──▌ CNS_INT int 0 $80
N003 ( 5, 4) [000052] IA------R--- └──▌ ASG struct (init) $VN.Void
N002 ( 3, 2) [000050] D------N---- └──▌ LCL_VAR struct V02 tmp1 d:3
***** BB01, stmt 4
( 5, 6) [000059] ------------ ▌ STMT void (IL ???... ???)
N001 ( 1, 1) [000056] ------------ │ ┌──▌ CNS_INT int 1 $85
N003 ( 5, 6) [000058] -A------R--- └──▌ ASG int $85
N002 ( 3, 4) [000055] U------N---- └──▌ LCL_FLD int V02 tmp1 ud:3->4[+0] Fseq[F1] $300
***** BB01, stmt 5
( 15, 15) [000067] ------------ ▌ STMT void (IL ???... ???)
N003 ( 7, 6) [000099] x----------- │ ┌──▌ IND byte <l:$1c1, c:$201>
N002 ( 3, 3) [000098] L----------- │ │ └──▌ ADDR byref $103
N001 ( 3, 2) [000062] ------------ │ │ └──▌ LCL_VAR struct(AX) V05 tmp4 $181
N007 ( 15, 15) [000066] -A--G---R--- └──▌ ASG byte $VN.Void
N006 ( 7, 8) [000065] *---G--N---- └──▌ IND byte <l:$1c1, c:$201>
N005 ( 3, 5) [000064] ------------ └──▌ ADDR byref $142
N004 ( 3, 4) [000061] U------N---- └──▌ LCL_FLD struct V02 tmp1 ud:4->5[+16] Fseq[F6] <l:$340, c:$341>
***** BB01, stmt 6
( 10, 10) [000086] ------------ ▌ STMT void (IL ???... ???)
N001 ( 3, 2) [000081] ------------ │ ┌──▌ LCL_VAR struct V02 tmp1 u:5 (last use) <l:$182, c:$183>
N005 ( 10, 10) [000085] -A------R--- └──▌ ASG struct (copy) $VN.Void
N004 ( 6, 7) [000084] x----------- └──▌ BLK(24) struct
N003 ( 3, 5) [000083] ------------ └──▌ ADDR byref $143
N002 ( 3, 4) [000080] D------N---- └──▌ LCL_FLD struct V03 tmp2 d:3[+0] Fseq[F0]
***** BB01, stmt 7
( 3, 4) [000041] ------------ ▌ STMT void (IL 0x014... ???)
N001 ( 3, 4) [000032] ------------ │ ┌──▌ LCL_FLD int V03 tmp2 u:3[+0] Fseq[F0, F1] (last use) $80
N003 ( 3, 4) [000040] -A--G---R--- └──▌ ASG int $80
N002 ( 1, 1) [000039] D------N---- └──▌ LCL_VAR int V04 tmp3 d:3 $80
***** BB01, stmt 8
( 14, 5) [000038] ------------ ▌ STMT void (IL 0x014... ???)
N001 ( 14, 5) [000037] --CXG------- └──▌ CALL void Program.M $VN.Void
***** BB01, stmt 9
( 15, 7) [000045] ------------ ▌ STMT void (IL 0x023... ???)
N005 ( 15, 7) [000043] --CXG------- └──▌ CALL void System.Console.WriteLine $VN.Void
N003 ( 1, 1) [000042] ------------ arg0 in rdi └──▌ LCL_VAR int V04 tmp3 u:3 (last use) $80
***** BB01, stmt 10
( 0, 0) [000047] ------------ ▌ STMT void (IL 0x028... ???)
N001 ( 0, 0) [000046] ------------ └──▌ RETURN void $440
-------------------------------------------------------------------------------------------------------------------
New refCnts for V04: refCnt = 1, refCntWtd = 2
After constant propagation on [000042]:
( 15, 7) [000045] ------------ ▌ STMT void (IL 0x023... ???)
N005 ( 15, 7) [000043] --CXG------- └──▌ CALL void System.Console.WriteLine $VN.Void
N003 ( 1, 1) [000042] ------------ arg0 in rdi └──▌ CNS_INT int 0 $80
argSlots=1, preallocatedArgCount=0, nextSlotNum=0, outgoingArgSpaceSize=0
fgArgTabEntry[arg 0 42.CNS_INT, 1 reg: rdi, align=1, lateArgInx=0, processed]
optVNAssertionPropCurStmt morphed tree:
N005 ( 15, 7) [000043] --CXG------- ▌ CALL void System.Console.WriteLine $VN.Void
N003 ( 1, 1) [000042] ------------ arg0 in rdi └──▌ CNS_INT int 0 $80
*************** In OptimizeRangeChecks()
Blocks/trees before phase
--------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
--------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..029) (return) i label target gcsafe
--------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [000..029) (return), preds={} succs={}
***** BB01, stmt 1
( 9, 8) [000006] ------------ ▌ STMT void (IL 0x000...0x004)
N001 ( 1, 1) [000004] ------------ │ ┌──▌ CNS_INT int 0 $80
N005 ( 9, 8) [000005] -A------R--- └──▌ ASG byte $VN.Void
N004 ( 7, 6) [000093] x------N---- └──▌ IND byte $80
N003 ( 3, 3) [000092] L----------- └──▌ ADDR byref $100
N002 ( 3, 2) [000002] D------N---- └──▌ LCL_VAR struct(AX) V00 loc0
***** BB01, stmt 2
( 15, 13) [000071] ------------ ▌ STMT void (IL ???... ???)
N003 ( 7, 6) [000016] x----------- │ ┌──▌ IND byte <l:$1c0, c:$200>
N002 ( 3, 3) [000015] L----------- │ │ └──▌ ADDR byref $101
N001 ( 3, 2) [000007] -------N---- │ │ └──▌ LCL_VAR struct(AX) V00 loc0 $180
N007 ( 15, 13) [000070] -A------R--- └──▌ ASG byte $VN.Void
N006 ( 7, 6) [000095] x------N---- └──▌ IND byte <l:$1c0, c:$200>
N005 ( 3, 3) [000094] L----------- └──▌ ADDR byref $102
N004 ( 3, 2) [000068] D------N---- └──▌ LCL_VAR struct(AX) V05 tmp4
***** BB01, stmt 3
( 5, 4) [000053] ------------ ▌ STMT void (IL ???... ???)
N001 ( 1, 1) [000051] ------------ │ ┌──▌ CNS_INT int 0 $80
N003 ( 5, 4) [000052] IA------R--- └──▌ ASG struct (init) $VN.Void
N002 ( 3, 2) [000050] D------N---- └──▌ LCL_VAR struct V02 tmp1 d:3
***** BB01, stmt 4
( 5, 6) [000059] ------------ ▌ STMT void (IL ???... ???)
N001 ( 1, 1) [000056] ------------ │ ┌──▌ CNS_INT int 1 $85
N003 ( 5, 6) [000058] -A------R--- └──▌ ASG int $85
N002 ( 3, 4) [000055] U------N---- └──▌ LCL_FLD int V02 tmp1 ud:3->4[+0] Fseq[F1] $300
***** BB01, stmt 5
( 15, 15) [000067] ------------ ▌ STMT void (IL ???... ???)
N003 ( 7, 6) [000099] x----------- │ ┌──▌ IND byte <l:$1c1, c:$201>
N002 ( 3, 3) [000098] L----------- │ │ └──▌ ADDR byref $103
N001 ( 3, 2) [000062] ------------ │ │ └──▌ LCL_VAR struct(AX) V05 tmp4 $181
N007 ( 15, 15) [000066] -A--G---R--- └──▌ ASG byte $VN.Void
N006 ( 7, 8) [000065] *---G--N---- └──▌ IND byte <l:$1c1, c:$201>
N005 ( 3, 5) [000064] ------------ └──▌ ADDR byref $142
N004 ( 3, 4) [000061] U------N---- └──▌ LCL_FLD struct V02 tmp1 ud:4->5[+16] Fseq[F6] <l:$340, c:$341>
***** BB01, stmt 6
( 10, 10) [000086] ------------ ▌ STMT void (IL ???... ???)
N001 ( 3, 2) [000081] ------------ │ ┌──▌ LCL_VAR struct V02 tmp1 u:5 (last use) <l:$182, c:$183>
N005 ( 10, 10) [000085] -A------R--- └──▌ ASG struct (copy) $VN.Void
N004 ( 6, 7) [000084] x----------- └──▌ BLK(24) struct
N003 ( 3, 5) [000083] ------------ └──▌ ADDR byref $143
N002 ( 3, 4) [000080] D------N---- └──▌ LCL_FLD struct V03 tmp2 d:3[+0] Fseq[F0]
***** BB01, stmt 7
( 3, 4) [000041] ------------ ▌ STMT void (IL 0x014... ???)
N001 ( 3, 4) [000032] ------------ │ ┌──▌ LCL_FLD int V03 tmp2 u:3[+0] Fseq[F0, F1] (last use) $80
N003 ( 3, 4) [000040] -A--G---R--- └──▌ ASG int $80
N002 ( 1, 1) [000039] D------N---- └──▌ LCL_VAR int V04 tmp3 d:3 $80
***** BB01, stmt 8
( 14, 5) [000038] ------------ ▌ STMT void (IL 0x014... ???)
N001 ( 14, 5) [000037] --CXG------- └──▌ CALL void Program.M $VN.Void
***** BB01, stmt 9
( 15, 7) [000045] ------------ ▌ STMT void (IL 0x023... ???)
N005 ( 15, 7) [000043] --CXG------- └──▌ CALL void System.Console.WriteLine $VN.Void
N003 ( 1, 1) [000042] ------------ arg0 in rdi └──▌ CNS_INT int 0 $80
***** BB01, stmt 10
( 0, 0) [000047] ------------ ▌ STMT void (IL 0x028... ???)
N001 ( 0, 0) [000046] ------------ └──▌ RETURN void $440
-------------------------------------------------------------------------------------------------------------------
*************** In fgDetermineFirstColdBlock()
No procedure splitting will be done for this method
*************** In IR Rationalize
Trees before IR Rationalize
--------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
--------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..029) (return) i label target gcsafe
--------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [000..029) (return), preds={} succs={}
***** BB01, stmt 1
( 9, 8) [000006] ------------ ▌ STMT void (IL 0x000...0x004)
N001 ( 1, 1) [000004] ------------ │ ┌──▌ CNS_INT int 0 $80
N005 ( 9, 8) [000005] -A------R--- └──▌ ASG byte $VN.Void
N004 ( 7, 6) [000093] x------N---- └──▌ IND byte $80
N003 ( 3, 3) [000092] L----------- └──▌ ADDR byref $100
N002 ( 3, 2) [000002] D------N---- └──▌ LCL_VAR struct(AX) V00 loc0
***** BB01, stmt 2
( 15, 13) [000071] ------------ ▌ STMT void (IL ???... ???)
N003 ( 7, 6) [000016] x----------- │ ┌──▌ IND byte <l:$1c0, c:$200>
N002 ( 3, 3) [000015] L----------- │ │ └──▌ ADDR byref $101
N001 ( 3, 2) [000007] -------N---- │ │ └──▌ LCL_VAR struct(AX) V00 loc0 $180
N007 ( 15, 13) [000070] -A------R--- └──▌ ASG byte $VN.Void
N006 ( 7, 6) [000095] x------N---- └──▌ IND byte <l:$1c0, c:$200>
N005 ( 3, 3) [000094] L----------- └──▌ ADDR byref $102
N004 ( 3, 2) [000068] D------N---- └──▌ LCL_VAR struct(AX) V05 tmp4
***** BB01, stmt 3
( 5, 4) [000053] ------------ ▌ STMT void (IL ???... ???)
N001 ( 1, 1) [000051] ------------ │ ┌──▌ CNS_INT int 0 $80
N003 ( 5, 4) [000052] IA------R--- └──▌ ASG struct (init) $VN.Void
N002 ( 3, 2) [000050] D------N---- └──▌ LCL_VAR struct V02 tmp1 d:3
***** BB01, stmt 4
( 5, 6) [000059] ------------ ▌ STMT void (IL ???... ???)
N001 ( 1, 1) [000056] ------------ │ ┌──▌ CNS_INT int 1 $85
N003 ( 5, 6) [000058] -A------R--- └──▌ ASG int $85
N002 ( 3, 4) [000055] U------N---- └──▌ LCL_FLD int V02 tmp1 ud:3->4[+0] Fseq[F1] $300
***** BB01, stmt 5
( 15, 15) [000067] ------------ ▌ STMT void (IL ???... ???)
N003 ( 7, 6) [000099] x----------- │ ┌──▌ IND byte <l:$1c1, c:$201>
N002 ( 3, 3) [000098] L----------- │ │ └──▌ ADDR byref $103
N001 ( 3, 2) [000062] ------------ │ │ └──▌ LCL_VAR struct(AX) V05 tmp4 $181
N007 ( 15, 15) [000066] -A--G---R--- └──▌ ASG byte $VN.Void
N006 ( 7, 8) [000065] *---G--N---- └──▌ IND byte <l:$1c1, c:$201>
N005 ( 3, 5) [000064] ------------ └──▌ ADDR byref $142
N004 ( 3, 4) [000061] U------N---- └──▌ LCL_FLD struct V02 tmp1 ud:4->5[+16] Fseq[F6] <l:$340, c:$341>
***** BB01, stmt 6
( 10, 10) [000086] ------------ ▌ STMT void (IL ???... ???)
N001 ( 3, 2) [000081] ------------ │ ┌──▌ LCL_VAR struct V02 tmp1 u:5 (last use) <l:$182, c:$183>
N005 ( 10, 10) [000085] -A------R--- └──▌ ASG struct (copy) $VN.Void
N004 ( 6, 7) [000084] x----------- └──▌ BLK(24) struct
N003 ( 3, 5) [000083] ------------ └──▌ ADDR byref $143
N002 ( 3, 4) [000080] D------N---- └──▌ LCL_FLD struct V03 tmp2 d:3[+0] Fseq[F0]
***** BB01, stmt 7
( 3, 4) [000041] ------------ ▌ STMT void (IL 0x014... ???)
N001 ( 3, 4) [000032] ------------ │ ┌──▌ LCL_FLD int V03 tmp2 u:3[+0] Fseq[F0, F1] (last use) $80
N003 ( 3, 4) [000040] -A--G---R--- └──▌ ASG int $80
N002 ( 1, 1) [000039] D------N---- └──▌ LCL_VAR int V04 tmp3 d:3 $80
***** BB01, stmt 8
( 14, 5) [000038] ------------ ▌ STMT void (IL 0x014... ???)
N001 ( 14, 5) [000037] --CXG------- └──▌ CALL void Program.M $VN.Void
***** BB01, stmt 9
( 15, 7) [000045] ------------ ▌ STMT void (IL 0x023... ???)
N005 ( 15, 7) [000043] --CXG------- └──▌ CALL void System.Console.WriteLine $VN.Void
N003 ( 1, 1) [000042] ------------ arg0 in rdi └──▌ CNS_INT int 0 $80
***** BB01, stmt 10
( 0, 0) [000047] ------------ ▌ STMT void (IL 0x028... ???)
N001 ( 0, 0) [000046] ------------ └──▌ RETURN void $440
-------------------------------------------------------------------------------------------------------------------
Rewriting GT_ADDR(GT_LCL_VAR) to GT_LCL_VAR_ADDR:
N002 ( 3, 2) [000002] D------N---- t2 = LCL_VAR_ADDR byref V00 loc0
Rewriting GT_ADDR(GT_LCL_VAR) to GT_LCL_VAR_ADDR:
N001 ( 3, 2) [000007] -------N---- t7 = LCL_VAR_ADDR byref V00 loc0
Rewriting GT_ADDR(GT_LCL_VAR) to GT_LCL_VAR_ADDR:
N004 ( 3, 2) [000068] D------N---- t68 = LCL_VAR_ADDR byref V05 tmp4
After transforming local struct assignment into a block op:
N001 ( 1, 1) [000051] ------------ t51 = CNS_INT int 0 $80
N002 ( 3, 2) [000050] D------N---- t50 = LCL_VAR_ADDR byref V02 tmp1 d:3
┌──▌ t50 byref
├──▌ t51 int
[000104] -A---------- ▌ STORE_BLK(24) struct (init)
rewriting asg(LCL_FLD, X) to STORE_LCL_FLD(X)
N003 ( 5, 6) [000058] UA---------- ▌ STORE_LCL_FLD int V02 tmp1 ud:3->0[+0] Fseq[F1]
Rewriting GT_ADDR(GT_LCL_VAR) to GT_LCL_VAR_ADDR:
N001 ( 3, 2) [000062] ------------ t62 = LCL_VAR_ADDR byref V05 tmp4
Rewriting GT_ADDR(GT_LCL_FLD) to GT_LCL_FLD_ADDR:
N004 ( 3, 4) [000061] U------N---- t61 = LCL_FLD_ADDR byref V02 tmp1 ud:4->5[+16] Fseq[F6]
Rewriting GT_ADDR(GT_LCL_FLD) to GT_LCL_FLD_ADDR:
N002 ( 3, 4) [000080] D------N---- t80 = LCL_FLD_ADDR byref V03 tmp2 d:3[+0] Fseq[F0]
Rewriting GT_ASG(BLK(X), Y) to STORE_BLK(X,Y):
N001 ( 3, 2) [000081] ------------ t81 = LCL_VAR struct V02 tmp1 u:5 (last use) <l:$182, c:$183>
N002 ( 3, 4) [000080] D------N---- t80 = LCL_FLD_ADDR byref V03 tmp2 d:3[+0] Fseq[F0]
┌──▌ t80 byref
├──▌ t81 struct
N004 ( 6, 7) [000084] xA---------- ▌ STORE_BLK(24) struct (copy)
rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X)
N003 ( 3, 4) [000040] DA--G------- ▌ STORE_LCL_VAR int V04 tmp3 d:3
*************** Exiting IR Rationalize
Trees after IR Rationalize
--------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
--------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..029) (return) i label target gcsafe LIR
--------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [000..029) (return), preds={} succs={}
( 9, 8) [000006] ------------ IL_OFFSET void IL offset: 0x0
N001 ( 1, 1) [000004] ------------ t4 = CNS_INT int 0 $80
N002 ( 3, 2) [000002] D------N---- t2 = LCL_VAR_ADDR byref V00 loc0
┌──▌ t2 byref
├──▌ t4 int
[000102] -A---------- ▌ STOREIND byte
N001 ( 3, 2) [000007] -------N---- t7 = LCL_VAR_ADDR byref V00 loc0
┌──▌ t7 byref
N003 ( 7, 6) [000016] x----------- t16 = ▌ IND byte <l:$1c0, c:$200>
N004 ( 3, 2) [000068] D------N---- t68 = LCL_VAR_ADDR byref V05 tmp4
┌──▌ t68 byref
├──▌ t16 byte
[000103] -A---------- ▌ STOREIND byte
N001 ( 1, 1) [000051] ------------ t51 = CNS_INT int 0 $80
N002 ( 3, 2) [000050] D------N---- t50 = LCL_VAR_ADDR byref V02 tmp1 d:3
┌──▌ t50 byref
├──▌ t51 int
[000104] -A---------- ▌ STORE_BLK(24) struct (init)
N001 ( 1, 1) [000056] ------------ t56 = CNS_INT int 1 $85
┌──▌ t56 int
N003 ( 5, 6) [000058] UA---------- ▌ STORE_LCL_FLD int V02 tmp1 ud:3->0[+0] Fseq[F1]
N001 ( 3, 2) [000062] ------------ t62 = LCL_VAR_ADDR byref V05 tmp4
┌──▌ t62 byref
N003 ( 7, 6) [000099] x----------- t99 = ▌ IND byte <l:$1c1, c:$201>
N004 ( 3, 4) [000061] U------N---- t61 = LCL_FLD_ADDR byref V02 tmp1 ud:4->5[+16] Fseq[F6]
┌──▌ t61 byref
├──▌ t99 byte
[000105] -A--G------- ▌ STOREIND byte
N001 ( 3, 2) [000081] ------------ t81 = LCL_VAR struct V02 tmp1 u:5 (last use) <l:$182, c:$183>
N002 ( 3, 4) [000080] D------N---- t80 = LCL_FLD_ADDR byref V03 tmp2 d:3[+0] Fseq[F0]
┌──▌ t80 byref
├──▌ t81 struct
N004 ( 6, 7) [000084] xA---------- ▌ STORE_BLK(24) struct (copy)
( 3, 4) [000041] ------------ IL_OFFSET void IL offset: 0x14
N001 ( 3, 4) [000032] ------------ t32 = LCL_FLD int V03 tmp2 u:3[+0] Fseq[F0, F1] (last use) $80
┌──▌ t32 int
N003 ( 3, 4) [000040] DA--G------- ▌ STORE_LCL_VAR int V04 tmp3 d:3
( 14, 5) [000038] ------------ IL_OFFSET void IL offset: 0x14
N001 ( 14, 5) [000037] --CXG------- CALL void Program.M $VN.Void
( 15, 7) [000045] ------------ IL_OFFSET void IL offset: 0x23
N003 ( 1, 1) [000042] ------------ t42 = CNS_INT int 0 $80
┌──▌ t42 int arg0 in rdi
N005 ( 15, 7) [000043] --CXG------- ▌ CALL void System.Console.WriteLine $VN.Void
( 0, 0) [000047] ------------ IL_OFFSET void IL offset: 0x28
N001 ( 0, 0) [000046] ------------ RETURN void $440
-------------------------------------------------------------------------------------------------------------------
*************** In fgDebugCheckBBlist
outgoingArgSpaceSize 0 sufficient for call [000037], which needs 0
outgoingArgSpaceSize 0 sufficient for call [000043], which needs 0
*************** In fgDebugCheckBBlist
*************** In Lowering
Trees before Lowering
--------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
--------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..029) (return) i label target gcsafe LIR
--------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [000..029) (return), preds={} succs={}
( 9, 8) [000006] ------------ IL_OFFSET void IL offset: 0x0
N001 ( 1, 1) [000004] ------------ t4 = CNS_INT int 0 $80
N002 ( 3, 2) [000002] D------N---- t2 = LCL_VAR_ADDR byref V00 loc0
┌──▌ t2 byref
├──▌ t4 int
[000102] -A---------- ▌ STOREIND byte
N001 ( 3, 2) [000007] -------N---- t7 = LCL_VAR_ADDR byref V00 loc0
┌──▌ t7 byref
N003 ( 7, 6) [000016] x----------- t16 = ▌ IND byte <l:$1c0, c:$200>
N004 ( 3, 2) [000068] D------N---- t68 = LCL_VAR_ADDR byref V05 tmp4
┌──▌ t68 byref
├──▌ t16 byte
[000103] -A---------- ▌ STOREIND byte
N001 ( 1, 1) [000051] ------------ t51 = CNS_INT int 0 $80
N002 ( 3, 2) [000050] D------N---- t50 = LCL_VAR_ADDR byref V02 tmp1 d:3
┌──▌ t50 byref
├──▌ t51 int
[000104] -A---------- ▌ STORE_BLK(24) struct (init)
N001 ( 1, 1) [000056] ------------ t56 = CNS_INT int 1 $85
┌──▌ t56 int
N003 ( 5, 6) [000058] UA---------- ▌ STORE_LCL_FLD int V02 tmp1 ud:3->0[+0] Fseq[F1]
N001 ( 3, 2) [000062] ------------ t62 = LCL_VAR_ADDR byref V05 tmp4
┌──▌ t62 byref
N003 ( 7, 6) [000099] x----------- t99 = ▌ IND byte <l:$1c1, c:$201>
N004 ( 3, 4) [000061] U------N---- t61 = LCL_FLD_ADDR byref V02 tmp1 ud:4->5[+16] Fseq[F6]
┌──▌ t61 byref
├──▌ t99 byte
[000105] -A--G------- ▌ STOREIND byte
N001 ( 3, 2) [000081] ------------ t81 = LCL_VAR struct V02 tmp1 u:5 (last use) <l:$182, c:$183>
N002 ( 3, 4) [000080] D------N---- t80 = LCL_FLD_ADDR byref V03 tmp2 d:3[+0] Fseq[F0]
┌──▌ t80 byref
├──▌ t81 struct
N004 ( 6, 7) [000084] xA---------- ▌ STORE_BLK(24) struct (copy)
( 3, 4) [000041] ------------ IL_OFFSET void IL offset: 0x14
N001 ( 3, 4) [000032] ------------ t32 = LCL_FLD int V03 tmp2 u:3[+0] Fseq[F0, F1] (last use) $80
┌──▌ t32 int
N003 ( 3, 4) [000040] DA--G------- ▌ STORE_LCL_VAR int V04 tmp3 d:3
( 14, 5) [000038] ------------ IL_OFFSET void IL offset: 0x14
N001 ( 14, 5) [000037] --CXG------- CALL void Program.M $VN.Void
( 15, 7) [000045] ------------ IL_OFFSET void IL offset: 0x23
N003 ( 1, 1) [000042] ------------ t42 = CNS_INT int 0 $80
┌──▌ t42 int arg0 in rdi
N005 ( 15, 7) [000043] --CXG------- ▌ CALL void System.Console.WriteLine $VN.Void
( 0, 0) [000047] ------------ IL_OFFSET void IL offset: 0x28
N001 ( 0, 0) [000046] ------------ RETURN void $440
-------------------------------------------------------------------------------------------------------------------
No addressing mode:
N002 ( 3, 2) [000002] D------N---- ▌ LCL_VAR_ADDR byref V00 loc0
Lower of StoreInd didn't mark the node as self contained for reason: 4
N001 ( 1, 1) [000004] ------------ t4 = CNS_INT int 0 $80
N002 ( 3, 2) [000002] D------N---- t2 = LCL_VAR_ADDR byref V00 loc0
┌──▌ t2 byref
├──▌ t4 int
[000102] -A---------- ▌ STOREIND byte
No addressing mode:
N001 ( 3, 2) [000007] -------N---- ▌ LCL_VAR_ADDR byref V00 loc0
No addressing mode:
N004 ( 3, 2) [000068] D------N---- ▌ LCL_VAR_ADDR byref V05 tmp4
Lower of StoreInd didn't mark the node as self contained for reason: 4
N001 ( 3, 2) [000007] -c-----N---- t7 = LCL_VAR_ADDR byref V00 loc0
┌──▌ t7 byref
N003 ( 7, 6) [000016] x----------- t16 = ▌ IND byte <l:$1c0, c:$200>
N004 ( 3, 2) [000068] D------N---- t68 = LCL_VAR_ADDR byref V05 tmp4
┌──▌ t68 byref
├──▌ t16 byte
[000103] -A---------- ▌ STOREIND byte
No addressing mode:
N001 ( 3, 2) [000062] ------------ ▌ LCL_VAR_ADDR byref V05 tmp4
No addressing mode:
N004 ( 3, 4) [000061] U------N---- ▌ LCL_FLD_ADDR byref V02 tmp1 ud:4->5[+16] Fseq[F6]
Lower of StoreInd didn't mark the node as self contained for reason: 3
N001 ( 3, 2) [000062] -c---------- t62 = LCL_VAR_ADDR byref V05 tmp4
┌──▌ t62 byref
N003 ( 7, 6) [000099] x----------- t99 = ▌ IND byte <l:$1c1, c:$201>
N004 ( 3, 4) [000061] U------N---- t61 = LCL_FLD_ADDR byref V02 tmp1 ud:4->5[+16] Fseq[F6]
┌──▌ t61 byref
├──▌ t99 byte
[000105] -A--G------- ▌ STOREIND byte
lowering call (before):
N001 ( 14, 5) [000037] --CXG------- CALL void Program.M $VN.Void
objp:
======
args:
======
late:
======
lowering call (after):
N001 ( 14, 5) [000037] --CXG------- CALL void Program.M $VN.Void
lowering call (before):
N003 ( 1, 1) [000042] ------------ t42 = CNS_INT int 0 $80
┌──▌ t42 int arg0 in rdi
N005 ( 15, 7) [000043] --CXG------- ▌ CALL void System.Console.WriteLine $VN.Void
objp:
======
args:
======
lowering arg : N001 ( 0, 0) [000100] ----------L- ▌ ARGPLACE int $80
late:
======
lowering arg : N003 ( 1, 1) [000042] ------------ ▌ CNS_INT int 0 $80
new node is : [000106] ------------ ▌ PUTARG_REG int REG rdi
lowering call (after):
N003 ( 1, 1) [000042] ------------ t42 = CNS_INT int 0 $80
┌──▌ t42 int
[000106] ------------ t106 = ▌ PUTARG_REG int REG rdi
┌──▌ t106 int arg0 in rdi
N005 ( 15, 7) [000043] --CXG------- ▌ CALL void System.Console.WriteLine $VN.Void
lowering GT_RETURN
N001 ( 0, 0) [000046] ------------ ▌ RETURN void $440
============Lower has completed modifying nodes.
--------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
--------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..029) (return) i label target gcsafe LIR
--------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [000..029) (return), preds={} succs={}
( 9, 8) [000006] ------------ IL_OFFSET void IL offset: 0x0
N001 ( 1, 1) [000004] -c---------- t4 = CNS_INT int 0 $80
N002 ( 3, 2) [000002] Dc-----N---- t2 = LCL_VAR_ADDR byref V00 loc0
┌──▌ t2 byref
├──▌ t4 int
[000102] -A---------- ▌ STOREIND byte
N001 ( 3, 2) [000007] -c-----N---- t7 = LCL_VAR_ADDR byref V00 loc0
┌──▌ t7 byref
N003 ( 7, 6) [000016] x----------- t16 = ▌ IND byte <l:$1c0, c:$200>
N004 ( 3, 2) [000068] Dc-----N---- t68 = LCL_VAR_ADDR byref V05 tmp4
┌──▌ t68 byref
├──▌ t16 byte
[000103] -A---------- ▌ STOREIND byte
N001 ( 1, 1) [000051] ------------ t51 = CNS_INT long 0 $80
N002 ( 3, 2) [000050] D------N---- t50 = LCL_VAR_ADDR byref V02 tmp1 d:3
┌──▌ t50 byref
├──▌ t51 long
[000104] -A---------- ▌ STORE_BLK(24) struct (init) (Unroll)
N001 ( 1, 1) [000056] -c---------- t56 = CNS_INT int 1 $85
┌──▌ t56 int
N003 ( 5, 6) [000058] UA---------- ▌ STORE_LCL_FLD int V02 tmp1 ud:3->0[+0] Fseq[F1]
N001 ( 3, 2) [000062] -c---------- t62 = LCL_VAR_ADDR byref V05 tmp4
┌──▌ t62 byref
N003 ( 7, 6) [000099] x----------- t99 = ▌ IND byte <l:$1c1, c:$201>
N004 ( 3, 4) [000061] U------N---- t61 = LCL_FLD_ADDR byref V02 tmp1 ud:4->5[+16] Fseq[F6]
┌──▌ t61 byref
├──▌ t99 byte
[000105] -A--G------- ▌ STOREIND byte
N001 ( 3, 2) [000081] -c---------- t81 = LCL_VAR struct V02 tmp1 u:5 (last use) <l:$182, c:$183>
N002 ( 3, 4) [000080] Dc-----N---- t80 = LCL_FLD_ADDR byref V03 tmp2 d:3[+0] Fseq[F0]
┌──▌ t80 byref
├──▌ t81 struct
N004 ( 6, 7) [000084] xA---------- ▌ STORE_BLK(24) struct (copy) (Unroll)
( 3, 4) [000041] ------------ IL_OFFSET void IL offset: 0x14
N001 ( 3, 4) [000032] ------------ t32 = LCL_FLD int V03 tmp2 u:3[+0] Fseq[F0, F1] (last use) $80
┌──▌ t32 int
N003 ( 3, 4) [000040] DA--G------- ▌ STORE_LCL_VAR int V04 tmp3 d:3
( 14, 5) [000038] ------------ IL_OFFSET void IL offset: 0x14
N001 ( 14, 5) [000037] --CXG------- CALL void Program.M $VN.Void
( 15, 7) [000045] ------------ IL_OFFSET void IL offset: 0x23
N003 ( 1, 1) [000042] ------------ t42 = CNS_INT int 0 $80
┌──▌ t42 int
[000106] ------------ t106 = ▌ PUTARG_REG int REG rdi
┌──▌ t106 int arg0 in rdi
N005 ( 15, 7) [000043] --CXG------- ▌ CALL void System.Console.WriteLine $VN.Void
( 0, 0) [000047] ------------ IL_OFFSET void IL offset: 0x28
N001 ( 0, 0) [000046] ------------ RETURN void $440
-------------------------------------------------------------------------------------------------------------------
*************** In fgLocalVarLiveness()
; Initial local variable assignments
;
; V00 loc0 struct ( 8) do-not-enreg[XSF] addr-exposed ld-addr-op
; V01 OutArgs lclBlk ( 0)
; V02 tmp1 struct (24) do-not-enreg[SFB]
; V03 tmp2 struct (24) do-not-enreg[SFB]
; V04 tmp3 int
; V05 tmp4 struct ( 8) do-not-enreg[XSF] addr-exposed
; V06 tmp5 struct (24) do-not-enreg[SB]
In fgLocalVarLivenessInit, sorting locals
Local V02 should not be enregistered because: it is a struct
Local V03 should not be enregistered because: it is a struct
Local V06 should not be enregistered because: it is a struct
refCnt table for 'Main':
V02 tmp1 [struct]: refCnt = 4, refCntWtd = 8
V03 tmp2 [struct]: refCnt = 2, refCntWtd = 4
V04 tmp3 [ int]: refCnt = 1, refCntWtd = 2
V05 tmp4 [struct]: refCnt = 2, refCntWtd = 4
V00 loc0 [struct]: refCnt = 2, refCntWtd = 2
V01 OutArgs [lclBlk]: refCnt = 1, refCntWtd = 1
*************** In fgPerBlockLocalVarLiveness()
BB01 USE(0)={ } + ByrefExposed + GcHeap
DEF(3)={V02 V03 V04} + ByrefExposed* + GcHeap*
** Memory liveness computed, GcHeap states and ByrefExposed states diverge
*************** In fgInterBlockLocalVarLiveness()
BB liveness after fgLiveVarAnalysis():
BB01 IN (0)={} + ByrefExposed + GcHeap
OUT(0)={}
Removing dead store:
N003 ( 3, 4) [000040] DA--G------- ▌ STORE_LCL_VAR int V04 tmp3 d:3 (last use)
New refCnts for V04: refCnt = 0, refCntWtd = 0
Removing dead LclVar use:
N001 ( 3, 4) [000032] ------------ ▌ LCL_FLD int V03 tmp2 u:3[+0] Fseq[F0, F1] (last use) $80
New refCnts for V03: refCnt = 1, refCntWtd = 2
In fgLocalVarLiveness, setting lvaSortAgain back to false (set during dead-code removal)
*************** In fgUpdateFlowGraph()
Before updating the flow graph:
--------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
--------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..029) (return) i label target gcsafe LIR
--------------------------------------------------------------------------------------------------------------------------------------
*************** In fgDebugCheckBBlist
Liveness pass finished after lowering, IR:
lvasortagain = 0
--------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
--------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..029) (return) i label target gcsafe LIR
--------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [000..029) (return), preds={} succs={}
( 9, 8) [000006] ------------ IL_OFFSET void IL offset: 0x0
N001 ( 1, 1) [000004] -c---------- t4 = CNS_INT int 0 $80
N002 ( 3, 2) [000002] Dc-----N---- t2 = LCL_VAR_ADDR byref V00 loc0
┌──▌ t2 byref
├──▌ t4 int
[000102] -A---------- ▌ STOREIND byte
N001 ( 3, 2) [000007] -c-----N---- t7 = LCL_VAR_ADDR byref V00 loc0
┌──▌ t7 byref
N003 ( 7, 6) [000016] x----------- t16 = ▌ IND byte <l:$1c0, c:$200>
N004 ( 3, 2) [000068] Dc-----N---- t68 = LCL_VAR_ADDR byref V05 tmp4
┌──▌ t68 byref
├──▌ t16 byte
[000103] -A---------- ▌ STOREIND byte
N001 ( 1, 1) [000051] ------------ t51 = CNS_INT long 0 $80
N002 ( 3, 2) [000050] D------N---- t50 = LCL_VAR_ADDR byref V02 tmp1 d:3
┌──▌ t50 byref
├──▌ t51 long
[000104] -A---------- ▌ STORE_BLK(24) struct (init) (Unroll)
N001 ( 1, 1) [000056] -c---------- t56 = CNS_INT int 1 $85
┌──▌ t56 int
N003 ( 5, 6) [000058] UA---------- ▌ STORE_LCL_FLD int V02 tmp1 ud:3->0[+0] Fseq[F1]
N001 ( 3, 2) [000062] -c---------- t62 = LCL_VAR_ADDR byref V05 tmp4
┌──▌ t62 byref
N003 ( 7, 6) [000099] x----------- t99 = ▌ IND byte <l:$1c1, c:$201>
N004 ( 3, 4) [000061] U------N---- t61 = LCL_FLD_ADDR byref V02 tmp1 ud:4->5[+16] Fseq[F6]
┌──▌ t61 byref
├──▌ t99 byte
[000105] -A--G------- ▌ STOREIND byte
N001 ( 3, 2) [000081] -c---------- t81 = LCL_VAR struct V02 tmp1 u:5 (last use) <l:$182, c:$183>
N002 ( 3, 4) [000080] Dc-----N---- t80 = LCL_FLD_ADDR byref V03 tmp2 d:3[+0] Fseq[F0] (last use)
┌──▌ t80 byref
├──▌ t81 struct
N004 ( 6, 7) [000084] xA---------- ▌ STORE_BLK(24) struct (copy) (Unroll)
( 3, 4) [000041] ------------ IL_OFFSET void IL offset: 0x14
( 14, 5) [000038] ------------ IL_OFFSET void IL offset: 0x14
N001 ( 14, 5) [000037] --CXG------- CALL void Program.M $VN.Void
( 15, 7) [000045] ------------ IL_OFFSET void IL offset: 0x23
N003 ( 1, 1) [000042] ------------ t42 = CNS_INT int 0 $80
┌──▌ t42 int
[000106] ------------ t106 = ▌ PUTARG_REG int REG rdi
┌──▌ t106 int arg0 in rdi
N005 ( 15, 7) [000043] --CXG------- ▌ CALL void System.Console.WriteLine $VN.Void
( 0, 0) [000047] ------------ IL_OFFSET void IL offset: 0x28
N001 ( 0, 0) [000046] ------------ RETURN void $440
-------------------------------------------------------------------------------------------------------------------
*************** Exiting Lowering
Trees after Lowering
--------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
--------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..029) (return) i label target gcsafe LIR
--------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [000..029) (return), preds={} succs={}
( 9, 8) [000006] ------------ IL_OFFSET void IL offset: 0x0
N001 ( 1, 1) [000004] -c---------- t4 = CNS_INT int 0 $80
N002 ( 3, 2) [000002] Dc-----N---- t2 = LCL_VAR_ADDR byref V00 loc0
┌──▌ t2 byref
├──▌ t4 int
[000102] -A---------- ▌ STOREIND byte
N001 ( 3, 2) [000007] -c-----N---- t7 = LCL_VAR_ADDR byref V00 loc0
┌──▌ t7 byref
N003 ( 7, 6) [000016] x----------- t16 = ▌ IND byte <l:$1c0, c:$200>
N004 ( 3, 2) [000068] Dc-----N---- t68 = LCL_VAR_ADDR byref V05 tmp4
┌──▌ t68 byref
├──▌ t16 byte
[000103] -A---------- ▌ STOREIND byte
N001 ( 1, 1) [000051] ------------ t51 = CNS_INT long 0 $80
N002 ( 3, 2) [000050] D------N---- t50 = LCL_VAR_ADDR byref V02 tmp1 d:3
┌──▌ t50 byref
├──▌ t51 long
[000104] -A---------- ▌ STORE_BLK(24) struct (init) (Unroll)
N001 ( 1, 1) [000056] -c---------- t56 = CNS_INT int 1 $85
┌──▌ t56 int
N003 ( 5, 6) [000058] UA---------- ▌ STORE_LCL_FLD int V02 tmp1 ud:3->0[+0] Fseq[F1]
N001 ( 3, 2) [000062] -c---------- t62 = LCL_VAR_ADDR byref V05 tmp4
┌──▌ t62 byref
N003 ( 7, 6) [000099] x----------- t99 = ▌ IND byte <l:$1c1, c:$201>
N004 ( 3, 4) [000061] U------N---- t61 = LCL_FLD_ADDR byref V02 tmp1 ud:4->5[+16] Fseq[F6]
┌──▌ t61 byref
├──▌ t99 byte
[000105] -A--G------- ▌ STOREIND byte
N001 ( 3, 2) [000081] -c---------- t81 = LCL_VAR struct V02 tmp1 u:5 (last use) <l:$182, c:$183>
N002 ( 3, 4) [000080] Dc-----N---- t80 = LCL_FLD_ADDR byref V03 tmp2 d:3[+0] Fseq[F0] (last use)
┌──▌ t80 byref
├──▌ t81 struct
N004 ( 6, 7) [000084] xA---------- ▌ STORE_BLK(24) struct (copy) (Unroll)
( 3, 4) [000041] ------------ IL_OFFSET void IL offset: 0x14
( 14, 5) [000038] ------------ IL_OFFSET void IL offset: 0x14
N001 ( 14, 5) [000037] --CXG------- CALL void Program.M $VN.Void
( 15, 7) [000045] ------------ IL_OFFSET void IL offset: 0x23
N003 ( 1, 1) [000042] ------------ t42 = CNS_INT int 0 $80
┌──▌ t42 int
[000106] ------------ t106 = ▌ PUTARG_REG int REG rdi
┌──▌ t106 int arg0 in rdi
N005 ( 15, 7) [000043] --CXG------- ▌ CALL void System.Console.WriteLine $VN.Void
( 0, 0) [000047] ------------ IL_OFFSET void IL offset: 0x28
N001 ( 0, 0) [000046] ------------ RETURN void $440
-------------------------------------------------------------------------------------------------------------------
*************** In fgDebugCheckBBlist
*************** In StackLevelSetter
Trees before StackLevelSetter
--------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
--------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..029) (return) i label target gcsafe LIR
--------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [000..029) (return), preds={} succs={}
( 9, 8) [000006] ------------ IL_OFFSET void IL offset: 0x0
N001 ( 1, 1) [000004] -c---------- t4 = CNS_INT int 0 $80
N002 ( 3, 2) [000002] Dc-----N---- t2 = LCL_VAR_ADDR byref V00 loc0
┌──▌ t2 byref
├──▌ t4 int
[000102] -A---------- ▌ STOREIND byte
N001 ( 3, 2) [000007] -c-----N---- t7 = LCL_VAR_ADDR byref V00 loc0
┌──▌ t7 byref
N003 ( 7, 6) [000016] x----------- t16 = ▌ IND byte <l:$1c0, c:$200>
N004 ( 3, 2) [000068] Dc-----N---- t68 = LCL_VAR_ADDR byref V05 tmp4
┌──▌ t68 byref
├──▌ t16 byte
[000103] -A---------- ▌ STOREIND byte
N001 ( 1, 1) [000051] ------------ t51 = CNS_INT long 0 $80
N002 ( 3, 2) [000050] D------N---- t50 = LCL_VAR_ADDR byref V02 tmp1 d:3
┌──▌ t50 byref
├──▌ t51 long
[000104] -A---------- ▌ STORE_BLK(24) struct (init) (Unroll)
N001 ( 1, 1) [000056] -c---------- t56 = CNS_INT int 1 $85
┌──▌ t56 int
N003 ( 5, 6) [000058] UA---------- ▌ STORE_LCL_FLD int V02 tmp1 ud:3->0[+0] Fseq[F1]
N001 ( 3, 2) [000062] -c---------- t62 = LCL_VAR_ADDR byref V05 tmp4
┌──▌ t62 byref
N003 ( 7, 6) [000099] x----------- t99 = ▌ IND byte <l:$1c1, c:$201>
N004 ( 3, 4) [000061] U------N---- t61 = LCL_FLD_ADDR byref V02 tmp1 ud:4->5[+16] Fseq[F6]
┌──▌ t61 byref
├──▌ t99 byte
[000105] -A--G------- ▌ STOREIND byte
N001 ( 3, 2) [000081] -c---------- t81 = LCL_VAR struct V02 tmp1 u:5 (last use) <l:$182, c:$183>
N002 ( 3, 4) [000080] Dc-----N---- t80 = LCL_FLD_ADDR byref V03 tmp2 d:3[+0] Fseq[F0] (last use)
┌──▌ t80 byref
├──▌ t81 struct
N004 ( 6, 7) [000084] xA---------- ▌ STORE_BLK(24) struct (copy) (Unroll)
( 3, 4) [000041] ------------ IL_OFFSET void IL offset: 0x14
( 14, 5) [000038] ------------ IL_OFFSET void IL offset: 0x14
N001 ( 14, 5) [000037] --CXG------- CALL void Program.M $VN.Void
( 15, 7) [000045] ------------ IL_OFFSET void IL offset: 0x23
N003 ( 1, 1) [000042] ------------ t42 = CNS_INT int 0 $80
┌──▌ t42 int
[000106] ------------ t106 = ▌ PUTARG_REG int REG rdi
┌──▌ t106 int arg0 in rdi
N005 ( 15, 7) [000043] --CXG------- ▌ CALL void System.Console.WriteLine $VN.Void
( 0, 0) [000047] ------------ IL_OFFSET void IL offset: 0x28
N001 ( 0, 0) [000046] ------------ RETURN void $440
-------------------------------------------------------------------------------------------------------------------
*************** Exiting StackLevelSetter
Trees after StackLevelSetter
--------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
--------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..029) (return) i label target gcsafe LIR
--------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [000..029) (return), preds={} succs={}
( 9, 8) [000006] ------------ IL_OFFSET void IL offset: 0x0
N001 ( 1, 1) [000004] -c---------- t4 = CNS_INT int 0 $80
N002 ( 3, 2) [000002] Dc-----N---- t2 = LCL_VAR_ADDR byref V00 loc0
┌──▌ t2 byref
├──▌ t4 int
[000102] -A---------- ▌ STOREIND byte
N001 ( 3, 2) [000007] -c-----N---- t7 = LCL_VAR_ADDR byref V00 loc0
┌──▌ t7 byref
N003 ( 7, 6) [000016] x----------- t16 = ▌ IND byte <l:$1c0, c:$200>
N004 ( 3, 2) [000068] Dc-----N---- t68 = LCL_VAR_ADDR byref V05 tmp4
┌──▌ t68 byref
├──▌ t16 byte
[000103] -A---------- ▌ STOREIND byte
N001 ( 1, 1) [000051] ------------ t51 = CNS_INT long 0 $80
N002 ( 3, 2) [000050] D------N---- t50 = LCL_VAR_ADDR byref V02 tmp1 d:3
┌──▌ t50 byref
├──▌ t51 long
[000104] -A---------- ▌ STORE_BLK(24) struct (init) (Unroll)
N001 ( 1, 1) [000056] -c---------- t56 = CNS_INT int 1 $85
┌──▌ t56 int
N003 ( 5, 6) [000058] UA---------- ▌ STORE_LCL_FLD int V02 tmp1 ud:3->0[+0] Fseq[F1]
N001 ( 3, 2) [000062] -c---------- t62 = LCL_VAR_ADDR byref V05 tmp4
┌──▌ t62 byref
N003 ( 7, 6) [000099] x----------- t99 = ▌ IND byte <l:$1c1, c:$201>
N004 ( 3, 4) [000061] U------N---- t61 = LCL_FLD_ADDR byref V02 tmp1 ud:4->5[+16] Fseq[F6]
┌──▌ t61 byref
├──▌ t99 byte
[000105] -A--G------- ▌ STOREIND byte
N001 ( 3, 2) [000081] -c---------- t81 = LCL_VAR struct V02 tmp1 u:5 (last use) <l:$182, c:$183>
N002 ( 3, 4) [000080] Dc-----N---- t80 = LCL_FLD_ADDR byref V03 tmp2 d:3[+0] Fseq[F0] (last use)
┌──▌ t80 byref
├──▌ t81 struct
N004 ( 6, 7) [000084] xA---------- ▌ STORE_BLK(24) struct (copy) (Unroll)
( 3, 4) [000041] ------------ IL_OFFSET void IL offset: 0x14
( 14, 5) [000038] ------------ IL_OFFSET void IL offset: 0x14
N001 ( 14, 5) [000037] --CXG------- CALL void Program.M $VN.Void
( 15, 7) [000045] ------------ IL_OFFSET void IL offset: 0x23
N003 ( 1, 1) [000042] ------------ t42 = CNS_INT int 0 $80
┌──▌ t42 int
[000106] ------------ t106 = ▌ PUTARG_REG int REG rdi
┌──▌ t106 int arg0 in rdi
N005 ( 15, 7) [000043] --CXG------- ▌ CALL void System.Console.WriteLine $VN.Void
( 0, 0) [000047] ------------ IL_OFFSET void IL offset: 0x28
N001 ( 0, 0) [000046] ------------ RETURN void $440
-------------------------------------------------------------------------------------------------------------------
*************** In fgDebugCheckBBlist
Clearing modified regs.
buildIntervals ========
-----------------
LIVENESS:
-----------------
BB01 use def in out
{}
{V02 V03 V04}
{}
{}
Local V02 should not be enregistered because: it is a struct
Local V03 should not be enregistered because: it is a struct
FP callee save candidate vars: None
floatVarCount = 0; hasLoops = 0, singleExit = 1
; Decided to create an EBP based frame for ETW stackwalking (Call Count)
TUPLE STYLE DUMP BEFORE LSRA
LSRA Block Sequence: BB01( 1 )
BB01 [000..029) (return), preds={} succs={}
=====
N000. IL_OFFSET IL offset: 0x0
N001. CNS_INT 0
N002. LCL_VAR_ADDR V00 loc0
N000. STOREIND
N001. LCL_VAR_ADDR V00 loc0
N003. t16 = IND
N004. LCL_VAR_ADDR V05 tmp4
N000. STOREIND ; t16
N001. t51 = CNS_INT 0
N002. t50 = LCL_VAR_ADDR V02 tmp1 d:3
N000. STORE_BLK(24); t50,t51
N001. CNS_INT 1
N003. V02 MEM
N001. LCL_VAR_ADDR V05 tmp4
N003. t99 = IND
N004. t61 = LCL_FLD_ADDR V02 tmp1 ud:4->5[+16] Fseq[F6]
N000. STOREIND ; t61,t99
N001. V02 MEM
N002. LCL_FLD_ADDR V03 tmp2 d:3[+0] Fseq[F0] (last use)
N004. STORE_BLK(24)
N000. IL_OFFSET IL offset: 0x14
N000. IL_OFFSET IL offset: 0x14
N001. CALL
N000. IL_OFFSET IL offset: 0x23
N003. t42 = CNS_INT 0
N000. t106 = PUTARG_REG; t42
N005. CALL ; t106
N000. IL_OFFSET IL offset: 0x28
N001. RETURN
buildIntervals second part ========
NEW BLOCK BB01
<RefPosition #0 @1 RefTypeBB BB01 regmask=[] minReg=1>
DefList: { }
N003 ( 9, 8) [000006] ------------ ▌ IL_OFFSET void IL offset: 0x0 REG NA
+<TreeNodeInfo 0=0 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 0 produce=0
DefList: { }
N005 ( 1, 1) [000004] -c---------- ▌ CNS_INT int 0 REG NA $80
Contained
DefList: { }
N007 ( 3, 2) [000002] Dc-----N---- ▌ LCL_VAR_ADDR byref V00 loc0 NA REG NA
Contained
DefList: { }
N009 (???,???) [000102] -A---------- ▌ STOREIND byte REG NA
+<TreeNodeInfo 0=0 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 0 produce=0
DefList: { }
N011 ( 3, 2) [000007] -c-----N---- ▌ LCL_VAR_ADDR byref V00 loc0 NA REG NA
Contained
DefList: { }
N013 ( 7, 6) [000016] x----------- ▌ IND byte REG NA <l:$1c0, c:$200>
Interval 0: RefPositions {} physReg:NA Preferences=[allInt]
<RefPosition #1 @14 RefTypeDef <Ivl:0> IND BB01 regmask=[allInt] minReg=1>
+<TreeNodeInfo 1=0 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 0 produce=1
DefList: { N013.t16. IND }
N015 ( 3, 2) [000068] Dc-----N---- ▌ LCL_VAR_ADDR byref V05 tmp4 NA REG NA
Contained
DefList: { N013.t16. IND }
N017 (???,???) [000103] -A---------- ▌ STOREIND byte REG NA
<RefPosition #2 @17 RefTypeUse <Ivl:0> BB01 regmask=[allInt] minReg=1 last>
+<TreeNodeInfo 0=1 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 1 produce=0
DefList: { }
N019 ( 1, 1) [000051] ------------ ▌ CNS_INT long 0 REG NA $80
Interval 1: RefPositions {} physReg:NA Preferences=[allInt]
<RefPosition #3 @20 RefTypeDef <Ivl:1> CNS_INT BB01 regmask=[allInt] minReg=1>
+<TreeNodeInfo 1=0 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 0 produce=1
DefList: { N019.t51. CNS_INT }
N021 ( 3, 2) [000050] D------N---- ▌ LCL_VAR_ADDR byref V02 tmp1 d:3 NA REG NA
Interval 2: RefPositions {} physReg:NA Preferences=[allInt]
<RefPosition #4 @22 RefTypeDef <Ivl:2> LCL_VAR_ADDR BB01 regmask=[allInt] minReg=1>
+<TreeNodeInfo 1=0 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 0 produce=1
DefList: { N019.t51. CNS_INT; N021.t50. LCL_VAR_ADDR }
N023 (???,???) [000104] -A---------- ▌ STORE_BLK(24) struct (init) (Unroll) REG NA
Interval 3: RefPositions {} physReg:NA Preferences=[allFloat]
<RefPosition #5 @23 RefTypeDef <Ivl:3 internal> STORE_BLK BB01 regmask=[allFloat] minReg=1>
<RefPosition #6 @23 RefTypeUse <Ivl:2> BB01 regmask=[allInt] minReg=1 last>
<RefPosition #7 @23 RefTypeUse <Ivl:1> BB01 regmask=[allInt] minReg=1 last>
<RefPosition #8 @23 RefTypeUse <Ivl:3 internal> STORE_BLK BB01 regmask=[allFloat] minReg=1 last>
+<TreeNodeInfo 0=2 0i 1f src=[allInt] int=[allFloat] dst=[allInt] I>[--]
consume= 2 produce=0
DefList: { }
N025 ( 1, 1) [000056] -c---------- ▌ CNS_INT int 1 REG NA $85
Contained
DefList: { }
N027 ( 5, 6) [000058] UA---------- ▌ STORE_LCL_FLD int V02 tmp1 ud:3->0[+0] Fseq[F1] NA REG NA
+<TreeNodeInfo 0=0 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 0 produce=0
DefList: { }
N029 ( 3, 2) [000062] -c---------- ▌ LCL_VAR_ADDR byref V05 tmp4 NA REG NA
Contained
DefList: { }
N031 ( 7, 6) [000099] x----------- ▌ IND byte REG NA <l:$1c1, c:$201>
Interval 4: RefPositions {} physReg:NA Preferences=[allInt]
<RefPosition #9 @32 RefTypeDef <Ivl:4> IND BB01 regmask=[allInt] minReg=1>
+<TreeNodeInfo 1=0 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 0 produce=1
DefList: { N031.t99. IND }
N033 ( 3, 4) [000061] U------N---- ▌ LCL_FLD_ADDR byref V02 tmp1 ud:4->5[+16] Fseq[F6] NA REG NA
Interval 5: RefPositions {} physReg:NA Preferences=[allInt]
<RefPosition #10 @34 RefTypeDef <Ivl:5> LCL_FLD_ADDR BB01 regmask=[allInt] minReg=1>
+<TreeNodeInfo 1=0 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 0 produce=1
DefList: { N031.t99. IND; N033.t61. LCL_FLD_ADDR }
N035 (???,???) [000105] -A--G------- ▌ STOREIND byte REG NA
<RefPosition #11 @35 RefTypeUse <Ivl:5> BB01 regmask=[allInt] minReg=1 last>
<RefPosition #12 @35 RefTypeUse <Ivl:4> BB01 regmask=[allInt] minReg=1 last>
+<TreeNodeInfo 0=2 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 2 produce=0
DefList: { }
N037 ( 3, 2) [000081] -c---------- ▌ LCL_VAR struct V02 tmp1 u:5 NA (last use) REG NA <l:$182, c:$183>
Contained
DefList: { }
N039 ( 3, 4) [000080] Dc-----N---- ▌ LCL_FLD_ADDR byref V03 tmp2 d:3[+0] Fseq[F0] NA (last use) REG NA
Contained
DefList: { }
N041 ( 6, 7) [000084] xA---------- ▌ STORE_BLK(24) struct (copy) (Unroll) REG NA
Interval 6: RefPositions {} physReg:NA Preferences=[allInt]
<RefPosition #13 @41 RefTypeDef <Ivl:6 internal> STORE_BLK BB01 regmask=[allInt] minReg=1>
Interval 7: RefPositions {} physReg:NA Preferences=[allFloat]
<RefPosition #14 @41 RefTypeDef <Ivl:7 internal> STORE_BLK BB01 regmask=[allFloat] minReg=1>
<RefPosition #15 @41 RefTypeUse <Ivl:6 internal> STORE_BLK BB01 regmask=[allInt] minReg=1 last>
<RefPosition #16 @41 RefTypeUse <Ivl:7 internal> STORE_BLK BB01 regmask=[allFloat] minReg=1 last>
+<TreeNodeInfo 0=0 1i 1f src=[allInt] int=[rax rcx rdx rbx rsi rdi r8-r15 mm0-mm15] dst=[allInt] I>[--]
consume= 0 produce=0
DefList: { }
N043 ( 3, 4) [000041] ------------ ▌ IL_OFFSET void IL offset: 0x14 REG NA
+<TreeNodeInfo 0=0 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 0 produce=0
DefList: { }
N045 ( 14, 5) [000038] ------------ ▌ IL_OFFSET void IL offset: 0x14 REG NA
+<TreeNodeInfo 0=0 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 0 produce=0
DefList: { }
N047 ( 14, 5) [000037] --CXG------- ▌ CALL void Program.M $VN.Void
<RefPosition #17 @48 RefTypeKill <Reg:rax> BB01 regmask=[rax] minReg=1>
<RefPosition #18 @48 RefTypeKill <Reg:rcx> BB01 regmask=[rcx] minReg=1>
<RefPosition #19 @48 RefTypeKill <Reg:rdx> BB01 regmask=[rdx] minReg=1>
<RefPosition #20 @48 RefTypeKill <Reg:rsi> BB01 regmask=[rsi] minReg=1>
<RefPosition #21 @48 RefTypeKill <Reg:rdi> BB01 regmask=[rdi] minReg=1>
<RefPosition #22 @48 RefTypeKill <Reg:r8 > BB01 regmask=[r8] minReg=1>
<RefPosition #23 @48 RefTypeKill <Reg:r9 > BB01 regmask=[r9] minReg=1>
<RefPosition #24 @48 RefTypeKill <Reg:r10> BB01 regmask=[r10] minReg=1>
<RefPosition #25 @48 RefTypeKill <Reg:r11> BB01 regmask=[r11] minReg=1>
+<TreeNodeInfo 0=0 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 0 produce=0
DefList: { }
N049 ( 15, 7) [000045] ------------ ▌ IL_OFFSET void IL offset: 0x23 REG NA
+<TreeNodeInfo 0=0 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 0 produce=0
DefList: { }
N051 ( 1, 1) [000042] ------------ ▌ CNS_INT int 0 REG NA $80
Interval 8: RefPositions {} physReg:NA Preferences=[allInt]
<RefPosition #26 @52 RefTypeDef <Ivl:8> CNS_INT BB01 regmask=[allInt] minReg=1>
+<TreeNodeInfo 1=0 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 0 produce=1
DefList: { N051.t42. CNS_INT }
N053 (???,???) [000106] ------------ ▌ PUTARG_REG int REG rdi
<RefPosition #27 @53 RefTypeFixedReg <Reg:rdi> BB01 regmask=[rdi] minReg=1>
<RefPosition #28 @53 RefTypeUse <Ivl:8> BB01 regmask=[rdi] minReg=1 last fixed>
Interval 9: RefPositions {} physReg:NA Preferences=[allInt]
<RefPosition #29 @54 RefTypeFixedReg <Reg:rdi> BB01 regmask=[rdi] minReg=1>
<RefPosition #30 @54 RefTypeDef <Ivl:9> PUTARG_REG BB01 regmask=[rdi] minReg=1 fixed>
+<TreeNodeInfo 1=1 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 1 produce=1
DefList: { N053.t106. PUTARG_REG }
N055 ( 15, 7) [000043] --CXG------- ▌ CALL void System.Console.WriteLine $VN.Void
<RefPosition #31 @55 RefTypeFixedReg <Reg:rdi> BB01 regmask=[rdi] minReg=1>
<RefPosition #32 @55 RefTypeUse <Ivl:9> BB01 regmask=[rdi] minReg=1 last fixed>
<RefPosition #33 @56 RefTypeKill <Reg:rax> BB01 regmask=[rax] minReg=1>
<RefPosition #34 @56 RefTypeKill <Reg:rcx> BB01 regmask=[rcx] minReg=1>
<RefPosition #35 @56 RefTypeKill <Reg:rdx> BB01 regmask=[rdx] minReg=1>
<RefPosition #36 @56 RefTypeKill <Reg:rsi> BB01 regmask=[rsi] minReg=1>
<RefPosition #37 @56 RefTypeKill <Reg:rdi> BB01 regmask=[rdi] minReg=1>
<RefPosition #38 @56 RefTypeKill <Reg:r8 > BB01 regmask=[r8] minReg=1>
<RefPosition #39 @56 RefTypeKill <Reg:r9 > BB01 regmask=[r9] minReg=1>
<RefPosition #40 @56 RefTypeKill <Reg:r10> BB01 regmask=[r10] minReg=1>
<RefPosition #41 @56 RefTypeKill <Reg:r11> BB01 regmask=[r11] minReg=1>
+<TreeNodeInfo 0=1 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 1 produce=0
DefList: { }
N057 ( 0, 0) [000047] ------------ ▌ IL_OFFSET void IL offset: 0x28 REG NA
+<TreeNodeInfo 0=0 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 0 produce=0
DefList: { }
N059 ( 0, 0) [000046] ------------ ▌ RETURN void REG NA $440
+<TreeNodeInfo 0=0 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 0 produce=0
CHECKING LAST USES for block 1, liveout={}
==============================
use: {}
def: {V02 V03 V04}
Linear scan intervals BEFORE VALIDATING INTERVALS:
Interval 0: RefPositions {#1@14 #2@17} physReg:NA Preferences=[allInt]
Interval 1: (constant) RefPositions {#3@20 #7@23} physReg:NA Preferences=[allInt]
Interval 2: RefPositions {#4@22 #6@23} physReg:NA Preferences=[allInt]
Interval 3: (INTERNAL) RefPositions {#5@23 #8@23} physReg:NA Preferences=[allFloat]
Interval 4: RefPositions {#9@32 #12@35} physReg:NA Preferences=[allInt]
Interval 5: RefPositions {#10@34 #11@35} physReg:NA Preferences=[allInt]
Interval 6: (INTERNAL) RefPositions {#13@41 #15@41} physReg:NA Preferences=[allInt]
Interval 7: (INTERNAL) RefPositions {#14@41 #16@41} physReg:NA Preferences=[allFloat]
Interval 8: (constant) RefPositions {#26@52 #28@53} physReg:NA Preferences=[rdi]
Interval 9: RefPositions {#30@54 #32@55} physReg:NA Preferences=[rdi]
------------
REFPOSITIONS BEFORE VALIDATING INTERVALS:
------------
<RefPosition #0 @1 RefTypeBB BB01 regmask=[] minReg=1>
<RefPosition #1 @14 RefTypeDef <Ivl:0> IND BB01 regmask=[allInt] minReg=1>
<RefPosition #2 @17 RefTypeUse <Ivl:0> BB01 regmask=[allInt] minReg=1 last>
<RefPosition #3 @20 RefTypeDef <Ivl:1> CNS_INT BB01 regmask=[allInt] minReg=1>
<RefPosition #4 @22 RefTypeDef <Ivl:2> LCL_VAR_ADDR BB01 regmask=[allInt] minReg=1>
<RefPosition #5 @23 RefTypeDef <Ivl:3 internal> STORE_BLK BB01 regmask=[allFloat] minReg=1>
<RefPosition #6 @23 RefTypeUse <Ivl:2> BB01 regmask=[allInt] minReg=1 last>
<RefPosition #7 @23 RefTypeUse <Ivl:1> BB01 regmask=[allInt] minReg=1 last>
<RefPosition #8 @23 RefTypeUse <Ivl:3 internal> STORE_BLK BB01 regmask=[allFloat] minReg=1 last>
<RefPosition #9 @32 RefTypeDef <Ivl:4> IND BB01 regmask=[allInt] minReg=1>
<RefPosition #10 @34 RefTypeDef <Ivl:5> LCL_FLD_ADDR BB01 regmask=[allInt] minReg=1>
<RefPosition #11 @35 RefTypeUse <Ivl:5> BB01 regmask=[allInt] minReg=1 last>
<RefPosition #12 @35 RefTypeUse <Ivl:4> BB01 regmask=[allInt] minReg=1 last>
<RefPosition #13 @41 RefTypeDef <Ivl:6 internal> STORE_BLK BB01 regmask=[allInt] minReg=1>
<RefPosition #14 @41 RefTypeDef <Ivl:7 internal> STORE_BLK BB01 regmask=[allFloat] minReg=1>
<RefPosition #15 @41 RefTypeUse <Ivl:6 internal> STORE_BLK BB01 regmask=[allInt] minReg=1 last>
<RefPosition #16 @41 RefTypeUse <Ivl:7 internal> STORE_BLK BB01 regmask=[allFloat] minReg=1 last>
<RefPosition #17 @48 RefTypeKill <Reg:rax> BB01 regmask=[rax] minReg=1 last>
<RefPosition #18 @48 RefTypeKill <Reg:rcx> BB01 regmask=[rcx] minReg=1 last>
<RefPosition #19 @48 RefTypeKill <Reg:rdx> BB01 regmask=[rdx] minReg=1 last>
<RefPosition #20 @48 RefTypeKill <Reg:rsi> BB01 regmask=[rsi] minReg=1 last>
<RefPosition #21 @48 RefTypeKill <Reg:rdi> BB01 regmask=[rdi] minReg=1 last>
<RefPosition #22 @48 RefTypeKill <Reg:r8 > BB01 regmask=[r8] minReg=1 last>
<RefPosition #23 @48 RefTypeKill <Reg:r9 > BB01 regmask=[r9] minReg=1 last>
<RefPosition #24 @48 RefTypeKill <Reg:r10> BB01 regmask=[r10] minReg=1 last>
<RefPosition #25 @48 RefTypeKill <Reg:r11> BB01 regmask=[r11] minReg=1 last>
<RefPosition #26 @52 RefTypeDef <Ivl:8> CNS_INT BB01 regmask=[rdi] minReg=1>
<RefPosition #27 @53 RefTypeFixedReg <Reg:rdi> BB01 regmask=[rdi] minReg=1>
<RefPosition #28 @53 RefTypeUse <Ivl:8> BB01 regmask=[rdi] minReg=1 last fixed>
<RefPosition #29 @54 RefTypeFixedReg <Reg:rdi> BB01 regmask=[rdi] minReg=1>
<RefPosition #30 @54 RefTypeDef <Ivl:9> PUTARG_REG BB01 regmask=[rdi] minReg=1 fixed>
<RefPosition #31 @55 RefTypeFixedReg <Reg:rdi> BB01 regmask=[rdi] minReg=1>
<RefPosition #32 @55 RefTypeUse <Ivl:9> BB01 regmask=[rdi] minReg=1 last fixed>
<RefPosition #33 @56 RefTypeKill <Reg:rax> BB01 regmask=[rax] minReg=1 last>
<RefPosition #34 @56 RefTypeKill <Reg:rcx> BB01 regmask=[rcx] minReg=1 last>
<RefPosition #35 @56 RefTypeKill <Reg:rdx> BB01 regmask=[rdx] minReg=1 last>
<RefPosition #36 @56 RefTypeKill <Reg:rsi> BB01 regmask=[rsi] minReg=1 last>
<RefPosition #37 @56 RefTypeKill <Reg:rdi> BB01 regmask=[rdi] minReg=1 last>
<RefPosition #38 @56 RefTypeKill <Reg:r8 > BB01 regmask=[r8] minReg=1 last>
<RefPosition #39 @56 RefTypeKill <Reg:r9 > BB01 regmask=[r9] minReg=1 last>
<RefPosition #40 @56 RefTypeKill <Reg:r10> BB01 regmask=[r10] minReg=1 last>
<RefPosition #41 @56 RefTypeKill <Reg:r11> BB01 regmask=[r11] minReg=1 last>
TUPLE STYLE DUMP WITH REF POSITIONS
Incoming Parameters:
BB01 [000..029) (return), preds={} succs={}
=====
N003. IL_OFFSET IL offset: 0x0 REG NA
N005. CNS_INT 0 REG NA
N007. LCL_VAR_ADDR V00 loc0 NA REG NA
N009. STOREIND
N011. LCL_VAR_ADDR V00 loc0 NA REG NA
N013. IND
Def:<I0>(#1)
N015. LCL_VAR_ADDR V05 tmp4 NA REG NA
N017. STOREIND
Use:<I0>(#2) *
N019. CNS_INT 0 REG NA
Def:<I1>(#3)
N021. LCL_VAR_ADDR V02 tmp1 d:3 NA REG NA
Def:<I2>(#4)
N023. STORE_BLK(24)
Def:<T3>(#5)
Use:<I2>(#6) *
Use:<I1>(#7) *
Use:<T3>(#8) *
N025. CNS_INT 1 REG NA
N027. V02 MEM
N029. LCL_VAR_ADDR V05 tmp4 NA REG NA
N031. IND
Def:<I4>(#9)
N033. LCL_FLD_ADDR V02 tmp1 ud:4->5[+16] Fseq[F6] NA REG NA
Def:<I5>(#10)
N035. STOREIND
Use:<I5>(#11) *
Use:<I4>(#12) *
N037. V02 MEM
N039. LCL_FLD_ADDR V03 tmp2 d:3[+0] Fseq[F0] NA (last use) REG NA
N041. STORE_BLK(24)
Def:<T6>(#13)
Def:<T7>(#14)
Use:<T6>(#15) *
Use:<T7>(#16) *
N043. IL_OFFSET IL offset: 0x14 REG NA
N045. IL_OFFSET IL offset: 0x14 REG NA
N047. CALL
Kill: rax rcx rdx rsi rdi r8 r9 r10 r11
N049. IL_OFFSET IL offset: 0x23 REG NA
N051. CNS_INT 0 REG NA
Def:<I8>(#26)
N053. PUTARG_REG
Use:<I8>(#28) Fixed:rdi(#27) *
Def:<I9>(#30) rdi
N055. CALL
Use:<I9>(#32) Fixed:rdi(#31) *
Kill: rax rcx rdx rsi rdi r8 r9 r10 r11
N057. IL_OFFSET IL offset: 0x28 REG NA
N059. RETURN
Linear scan intervals after buildIntervals:
Interval 0: RefPositions {#1@14 #2@17} physReg:NA Preferences=[allInt]
Interval 1: (constant) RefPositions {#3@20 #7@23} physReg:NA Preferences=[allInt]
Interval 2: RefPositions {#4@22 #6@23} physReg:NA Preferences=[allInt]
Interval 3: (INTERNAL) RefPositions {#5@23 #8@23} physReg:NA Preferences=[allFloat]
Interval 4: RefPositions {#9@32 #12@35} physReg:NA Preferences=[allInt]
Interval 5: RefPositions {#10@34 #11@35} physReg:NA Preferences=[allInt]
Interval 6: (INTERNAL) RefPositions {#13@41 #15@41} physReg:NA Preferences=[allInt]
Interval 7: (INTERNAL) RefPositions {#14@41 #16@41} physReg:NA Preferences=[allFloat]
Interval 8: (constant) RefPositions {#26@52 #28@53} physReg:NA Preferences=[rdi]
Interval 9: RefPositions {#30@54 #32@55} physReg:NA Preferences=[rdi]
*************** In LinearScan::allocateRegisters()
Linear scan intervals before allocateRegisters:
Interval 0: RefPositions {#1@14 #2@17} physReg:NA Preferences=[allInt]
Interval 1: (constant) RefPositions {#3@20 #7@23} physReg:NA Preferences=[allInt]
Interval 2: RefPositions {#4@22 #6@23} physReg:NA Preferences=[allInt]
Interval 3: (INTERNAL) RefPositions {#5@23 #8@23} physReg:NA Preferences=[allFloat]
Interval 4: RefPositions {#9@32 #12@35} physReg:NA Preferences=[allInt]
Interval 5: RefPositions {#10@34 #11@35} physReg:NA Preferences=[allInt]
Interval 6: (INTERNAL) RefPositions {#13@41 #15@41} physReg:NA Preferences=[allInt]
Interval 7: (INTERNAL) RefPositions {#14@41 #16@41} physReg:NA Preferences=[allFloat]
Interval 8: (constant) RefPositions {#26@52 #28@53} physReg:NA Preferences=[rdi]
Interval 9: RefPositions {#30@54 #32@55} physReg:NA Preferences=[rdi]
------------
REFPOSITIONS BEFORE ALLOCATION:
------------
<RefPosition #0 @1 RefTypeBB BB01 regmask=[] minReg=1>
<RefPosition #1 @14 RefTypeDef <Ivl:0> IND BB01 regmask=[allInt] minReg=1>
<RefPosition #2 @17 RefTypeUse <Ivl:0> BB01 regmask=[allInt] minReg=1 last>
<RefPosition #3 @20 RefTypeDef <Ivl:1> CNS_INT BB01 regmask=[allInt] minReg=1>
<RefPosition #4 @22 RefTypeDef <Ivl:2> LCL_VAR_ADDR BB01 regmask=[allInt] minReg=1>
<RefPosition #5 @23 RefTypeDef <Ivl:3 internal> STORE_BLK BB01 regmask=[allFloat] minReg=1>
<RefPosition #6 @23 RefTypeUse <Ivl:2> BB01 regmask=[allInt] minReg=1 last>
<RefPosition #7 @23 RefTypeUse <Ivl:1> BB01 regmask=[allInt] minReg=1 last>
<RefPosition #8 @23 RefTypeUse <Ivl:3 internal> STORE_BLK BB01 regmask=[allFloat] minReg=1 last>
<RefPosition #9 @32 RefTypeDef <Ivl:4> IND BB01 regmask=[allInt] minReg=1>
<RefPosition #10 @34 RefTypeDef <Ivl:5> LCL_FLD_ADDR BB01 regmask=[allInt] minReg=1>
<RefPosition #11 @35 RefTypeUse <Ivl:5> BB01 regmask=[allInt] minReg=1 last>
<RefPosition #12 @35 RefTypeUse <Ivl:4> BB01 regmask=[allInt] minReg=1 last>
<RefPosition #13 @41 RefTypeDef <Ivl:6 internal> STORE_BLK BB01 regmask=[allInt] minReg=1>
<RefPosition #14 @41 RefTypeDef <Ivl:7 internal> STORE_BLK BB01 regmask=[allFloat] minReg=1>
<RefPosition #15 @41 RefTypeUse <Ivl:6 internal> STORE_BLK BB01 regmask=[allInt] minReg=1 last>
<RefPosition #16 @41 RefTypeUse <Ivl:7 internal> STORE_BLK BB01 regmask=[allFloat] minReg=1 last>
<RefPosition #17 @48 RefTypeKill <Reg:rax> BB01 regmask=[rax] minReg=1 last>
<RefPosition #18 @48 RefTypeKill <Reg:rcx> BB01 regmask=[rcx] minReg=1 last>
<RefPosition #19 @48 RefTypeKill <Reg:rdx> BB01 regmask=[rdx] minReg=1 last>
<RefPosition #20 @48 RefTypeKill <Reg:rsi> BB01 regmask=[rsi] minReg=1 last>
<RefPosition #21 @48 RefTypeKill <Reg:rdi> BB01 regmask=[rdi] minReg=1 last>
<RefPosition #22 @48 RefTypeKill <Reg:r8 > BB01 regmask=[r8] minReg=1 last>
<RefPosition #23 @48 RefTypeKill <Reg:r9 > BB01 regmask=[r9] minReg=1 last>
<RefPosition #24 @48 RefTypeKill <Reg:r10> BB01 regmask=[r10] minReg=1 last>
<RefPosition #25 @48 RefTypeKill <Reg:r11> BB01 regmask=[r11] minReg=1 last>
<RefPosition #26 @52 RefTypeDef <Ivl:8> CNS_INT BB01 regmask=[rdi] minReg=1>
<RefPosition #27 @53 RefTypeFixedReg <Reg:rdi> BB01 regmask=[rdi] minReg=1>
<RefPosition #28 @53 RefTypeUse <Ivl:8> BB01 regmask=[rdi] minReg=1 last fixed>
<RefPosition #29 @54 RefTypeFixedReg <Reg:rdi> BB01 regmask=[rdi] minReg=1>
<RefPosition #30 @54 RefTypeDef <Ivl:9> PUTARG_REG BB01 regmask=[rdi] minReg=1 fixed>
<RefPosition #31 @55 RefTypeFixedReg <Reg:rdi> BB01 regmask=[rdi] minReg=1>
<RefPosition #32 @55 RefTypeUse <Ivl:9> BB01 regmask=[rdi] minReg=1 last fixed>
<RefPosition #33 @56 RefTypeKill <Reg:rax> BB01 regmask=[rax] minReg=1 last>
<RefPosition #34 @56 RefTypeKill <Reg:rcx> BB01 regmask=[rcx] minReg=1 last>
<RefPosition #35 @56 RefTypeKill <Reg:rdx> BB01 regmask=[rdx] minReg=1 last>
<RefPosition #36 @56 RefTypeKill <Reg:rsi> BB01 regmask=[rsi] minReg=1 last>
<RefPosition #37 @56 RefTypeKill <Reg:rdi> BB01 regmask=[rdi] minReg=1 last>
<RefPosition #38 @56 RefTypeKill <Reg:r8 > BB01 regmask=[r8] minReg=1 last>
<RefPosition #39 @56 RefTypeKill <Reg:r9 > BB01 regmask=[r9] minReg=1 last>
<RefPosition #40 @56 RefTypeKill <Reg:r10> BB01 regmask=[r10] minReg=1 last>
<RefPosition #41 @56 RefTypeKill <Reg:r11> BB01 regmask=[r11] minReg=1 last>
VAR REFPOSITIONS BEFORE ALLOCATION
--- V00
--- V01
--- V02
--- V03
--- V04
--- V05
--- V06
Allocating Registers
--------------------
The following table has one or more rows for each RefPosition that is handled during allocation.
The first column provides the basic information about the RefPosition, with its type (e.g. Def,
Use, Fixd) followed by a '*' if it is a last use, and a 'D' if it is delayRegFree, and then the
action taken during allocation (e.g. Alloc a new register, or Keep an existing one).
The subsequent columns show the Interval occupying each register, if any, followed by 'a' if it is
active, and 'i'if it is inactive. Columns are only printed up to the last modifed register, which
may increase during allocation, in which case additional columns will appear. Registers which are
not marked modified have ---- in their column.
──────────────────────────────┼────┼────┼────┼────┼────┤
LocRP# Name Type Action Reg │rax │rcx │rbx │r12 │r13 │
──────────────────────────────┼────┼────┼────┼────┼────┤
│ │ │ │ │ │
1.#0 BB1 PredBB0 │ │ │ │ │ │
14.#1 I0 Def Alloc rax │I0 a│ │ │ │ │
17.#2 I0 Use * Keep rax │I0 a│ │ │ │ │
20.#3 C1 Def Alloc rax │C1 a│ │ │ │ │
──────────────────────────────┼────┼────┼────┼────┼────┼────┤
LocRP# Name Type Action Reg │rax │rcx │rbx │rdi │r12 │r13 │
──────────────────────────────┼────┼────┼────┼────┼────┼────┤
22.#4 I2 Def Alloc rdi │C1 a│ │ │I2 a│ │ │
23.#5 I3 Def Alloc mm0 │C1 a│ │ │I2 a│ │ │
23.#6 I2 Use * Keep rdi │C1 a│ │ │I2 a│ │ │
23.#7 C1 Use * Keep rax │C1 a│ │ │I2 a│ │ │
23.#8 I3 Use * Keep mm0 │C1 a│ │ │I2 a│ │ │
32.#9 I4 Def Alloc rax │I4 a│ │ │ │ │ │
34.#10 I5 Def Alloc rdi │I4 a│ │ │I5 a│ │ │
35.#11 I5 Use * Keep rdi │I4 a│ │ │I5 a│ │ │
35.#12 I4 Use * Keep rax │I4 a│ │ │I5 a│ │ │
41.#13 I6 Def Alloc rax │I6 a│ │ │ │ │ │
41.#14 I7 Def Alloc mm0 │I6 a│ │ │ │ │ │
41.#15 I6 Use * Keep rax │I6 a│ │ │ │ │ │
41.#16 I7 Use * Keep mm0 │I6 a│ │ │ │ │ │
48.#17 rax Kill Keep rax │ │ │ │ │ │ │
48.#18 rcx Kill Keep rcx │ │ │ │ │ │ │
48.#19 rdx Kill Keep rdx │ │ │ │ │ │ │
48.#20 rsi Kill Keep rsi │ │ │ │ │ │ │
48.#21 rdi Kill Keep rdi │ │ │ │ │ │ │
48.#22 r8 Kill Keep r8 │ │ │ │ │ │ │
48.#23 r9 Kill Keep r9 │ │ │ │ │ │ │
48.#24 r10 Kill Keep r10 │ │ │ │ │ │ │
48.#25 r11 Kill Keep r11 │ │ │ │ │ │ │
52.#26 C8 Def Alloc rdi │ │ │ │C8 a│ │ │
53.#27 rdi Fixd Keep rdi │ │ │ │C8 a│ │ │
53.#28 C8 Use * Keep rdi │ │ │ │C8 a│ │ │
54.#29 rdi Fixd Keep rdi │ │ │ │ │ │ │
54.#30 I9 Def Alloc rdi │ │ │ │I9 a│ │ │
55.#31 rdi Fixd Keep rdi │ │ │ │I9 a│ │ │
55.#32 I9 Use * Keep rdi │ │ │ │I9 a│ │ │
56.#33 rax Kill Keep rax │ │ │ │ │ │ │
56.#34 rcx Kill Keep rcx │ │ │ │ │ │ │
56.#35 rdx Kill Keep rdx │ │ │ │ │ │ │
56.#36 rsi Kill Keep rsi │ │ │ │ │ │ │
56.#37 rdi Kill Keep rdi │ │ │ │ │ │ │
56.#38 r8 Kill Keep r8 │ │ │ │ │ │ │
56.#39 r9 Kill Keep r9 │ │ │ │ │ │ │
56.#40 r10 Kill Keep r10 │ │ │ │ │ │ │
56.#41 r11 Kill Keep r11 │ │ │ │ │ │ │
------------
REFPOSITIONS AFTER ALLOCATION:
------------
<RefPosition #0 @1 RefTypeBB BB01 regmask=[] minReg=1>
<RefPosition #1 @14 RefTypeDef <Ivl:0> IND BB01 regmask=[rax] minReg=1>
<RefPosition #2 @17 RefTypeUse <Ivl:0> BB01 regmask=[rax] minReg=1 last>
<RefPosition #3 @20 RefTypeDef <Ivl:1> CNS_INT BB01 regmask=[rax] minReg=1>
<RefPosition #4 @22 RefTypeDef <Ivl:2> LCL_VAR_ADDR BB01 regmask=[rdi] minReg=1>
<RefPosition #5 @23 RefTypeDef <Ivl:3 internal> STORE_BLK BB01 regmask=[mm0] minReg=1>
<RefPosition #6 @23 RefTypeUse <Ivl:2> BB01 regmask=[rdi] minReg=1 last>
<RefPosition #7 @23 RefTypeUse <Ivl:1> BB01 regmask=[rax] minReg=1 last>
<RefPosition #8 @23 RefTypeUse <Ivl:3 internal> STORE_BLK BB01 regmask=[mm0] minReg=1 last>
<RefPosition #9 @32 RefTypeDef <Ivl:4> IND BB01 regmask=[rax] minReg=1>
<RefPosition #10 @34 RefTypeDef <Ivl:5> LCL_FLD_ADDR BB01 regmask=[rdi] minReg=1>
<RefPosition #11 @35 RefTypeUse <Ivl:5> BB01 regmask=[rdi] minReg=1 last>
<RefPosition #12 @35 RefTypeUse <Ivl:4> BB01 regmask=[rax] minReg=1 last>
<RefPosition #13 @41 RefTypeDef <Ivl:6 internal> STORE_BLK BB01 regmask=[rax] minReg=1>
<RefPosition #14 @41 RefTypeDef <Ivl:7 internal> STORE_BLK BB01 regmask=[mm0] minReg=1>
<RefPosition #15 @41 RefTypeUse <Ivl:6 internal> STORE_BLK BB01 regmask=[rax] minReg=1 last>
<RefPosition #16 @41 RefTypeUse <Ivl:7 internal> STORE_BLK BB01 regmask=[mm0] minReg=1 last>
<RefPosition #17 @48 RefTypeKill <Reg:rax> BB01 regmask=[rax] minReg=1 last>
<RefPosition #18 @48 RefTypeKill <Reg:rcx> BB01 regmask=[rcx] minReg=1 last>
<RefPosition #19 @48 RefTypeKill <Reg:rdx> BB01 regmask=[rdx] minReg=1 last>
<RefPosition #20 @48 RefTypeKill <Reg:rsi> BB01 regmask=[rsi] minReg=1 last>
<RefPosition #21 @48 RefTypeKill <Reg:rdi> BB01 regmask=[rdi] minReg=1 last>
<RefPosition #22 @48 RefTypeKill <Reg:r8 > BB01 regmask=[r8] minReg=1 last>
<RefPosition #23 @48 RefTypeKill <Reg:r9 > BB01 regmask=[r9] minReg=1 last>
<RefPosition #24 @48 RefTypeKill <Reg:r10> BB01 regmask=[r10] minReg=1 last>
<RefPosition #25 @48 RefTypeKill <Reg:r11> BB01 regmask=[r11] minReg=1 last>
<RefPosition #26 @52 RefTypeDef <Ivl:8> CNS_INT BB01 regmask=[rdi] minReg=1>
<RefPosition #27 @53 RefTypeFixedReg <Reg:rdi> BB01 regmask=[rdi] minReg=1>
<RefPosition #28 @53 RefTypeUse <Ivl:8> BB01 regmask=[rdi] minReg=1 last fixed>
<RefPosition #29 @54 RefTypeFixedReg <Reg:rdi> BB01 regmask=[rdi] minReg=1>
<RefPosition #30 @54 RefTypeDef <Ivl:9> PUTARG_REG BB01 regmask=[rdi] minReg=1 fixed>
<RefPosition #31 @55 RefTypeFixedReg <Reg:rdi> BB01 regmask=[rdi] minReg=1>
<RefPosition #32 @55 RefTypeUse <Ivl:9> BB01 regmask=[rdi] minReg=1 last fixed>
<RefPosition #33 @56 RefTypeKill <Reg:rax> BB01 regmask=[rax] minReg=1 last>
<RefPosition #34 @56 RefTypeKill <Reg:rcx> BB01 regmask=[rcx] minReg=1 last>
<RefPosition #35 @56 RefTypeKill <Reg:rdx> BB01 regmask=[rdx] minReg=1 last>
<RefPosition #36 @56 RefTypeKill <Reg:rsi> BB01 regmask=[rsi] minReg=1 last>
<RefPosition #37 @56 RefTypeKill <Reg:rdi> BB01 regmask=[rdi] minReg=1 last>
<RefPosition #38 @56 RefTypeKill <Reg:r8 > BB01 regmask=[r8] minReg=1 last>
<RefPosition #39 @56 RefTypeKill <Reg:r9 > BB01 regmask=[r9] minReg=1 last>
<RefPosition #40 @56 RefTypeKill <Reg:r10> BB01 regmask=[r10] minReg=1 last>
<RefPosition #41 @56 RefTypeKill <Reg:r11> BB01 regmask=[r11] minReg=1 last>
VAR REFPOSITIONS AFTER ALLOCATION
--- V00
--- V01
--- V02
--- V03
--- V04
--- V05
--- V06
Active intervals at end of allocation:
-----------------------
RESOLVING BB BOUNDARIES
-----------------------
Resolution Candidates: {}
Has NoCritical Edges
Prior to Resolution
BB01 use def in out
{}
{V02 V03 V04}
{}
{}
Var=Reg beg of BB01: none
Var=Reg end of BB01: none
RESOLVING EDGES
Trees after linear scan register allocator (LSRA)
--------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
--------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..029) (return) i label target gcsafe LIR
--------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [000..029) (return), preds={} succs={}
N003 ( 9, 8) [000006] ------------ IL_OFFSET void IL offset: 0x0 REG NA
N005 ( 1, 1) [000004] -c---------- t4 = CNS_INT int 0 REG NA $80
N007 ( 3, 2) [000002] Dc-----N---- t2 = LCL_VAR_ADDR byref V00 loc0 NA REG NA
┌──▌ t2 byref
├──▌ t4 int
N009 (???,???) [000102] -A---------- ▌ STOREIND byte REG NA
N011 ( 3, 2) [000007] -c-----N---- t7 = LCL_VAR_ADDR byref V00 loc0 NA REG NA
┌──▌ t7 byref
N013 ( 7, 6) [000016] x----------- t16 = ▌ IND byte REG rax <l:$1c0, c:$200>
N015 ( 3, 2) [000068] Dc-----N---- t68 = LCL_VAR_ADDR byref V05 tmp4 NA REG NA
┌──▌ t68 byref
├──▌ t16 byte
N017 (???,???) [000103] -A---------- ▌ STOREIND byte REG NA
N019 ( 1, 1) [000051] ------------ t51 = CNS_INT long 0 REG rax $80
N021 ( 3, 2) [000050] D------N---- t50 = LCL_VAR_ADDR byref V02 tmp1 d:3 rdi REG rdi
┌──▌ t50 byref
├──▌ t51 long
N023 (???,???) [000104] -A---------- ▌ STORE_BLK(24) struct (init) (Unroll) REG NA
N025 ( 1, 1) [000056] -c---------- t56 = CNS_INT int 1 REG NA $85
┌──▌ t56 int
N027 ( 5, 6) [000058] UA---------- ▌ STORE_LCL_FLD int V02 tmp1 ud:3->0[+0] Fseq[F1] NA REG NA
N029 ( 3, 2) [000062] -c---------- t62 = LCL_VAR_ADDR byref V05 tmp4 NA REG NA
┌──▌ t62 byref
N031 ( 7, 6) [000099] x----------- t99 = ▌ IND byte REG rax <l:$1c1, c:$201>
N033 ( 3, 4) [000061] U------N---- t61 = LCL_FLD_ADDR byref V02 tmp1 ud:4->5[+16] Fseq[F6] rdi REG rdi
┌──▌ t61 byref
├──▌ t99 byte
N035 (???,???) [000105] -A--G------- ▌ STOREIND byte REG NA
N037 ( 3, 2) [000081] -c---------- t81 = LCL_VAR struct V02 tmp1 u:5 NA (last use) REG NA <l:$182, c:$183>
N039 ( 3, 4) [000080] Dc-----N---- t80 = LCL_FLD_ADDR byref V03 tmp2 d:3[+0] Fseq[F0] NA (last use) REG NA
┌──▌ t80 byref
├──▌ t81 struct
N041 ( 6, 7) [000084] xA---------- ▌ STORE_BLK(24) struct (copy) (Unroll) REG NA
N043 ( 3, 4) [000041] ------------ IL_OFFSET void IL offset: 0x14 REG NA
N045 ( 14, 5) [000038] ------------ IL_OFFSET void IL offset: 0x14 REG NA
N047 ( 14, 5) [000037] --CXG------- CALL void Program.M $VN.Void
N049 ( 15, 7) [000045] ------------ IL_OFFSET void IL offset: 0x23 REG NA
N051 ( 1, 1) [000042] ------------ t42 = CNS_INT int 0 REG rdi $80
┌──▌ t42 int
N053 (???,???) [000106] ------------ t106 = ▌ PUTARG_REG int REG rdi
┌──▌ t106 int arg0 in rdi
N055 ( 15, 7) [000043] --CXG------- ▌ CALL void System.Console.WriteLine $VN.Void
N057 ( 0, 0) [000047] ------------ IL_OFFSET void IL offset: 0x28 REG NA
N059 ( 0, 0) [000046] ------------ RETURN void REG NA $440
-------------------------------------------------------------------------------------------------------------------
Final allocation
──────────────────────────────┼────┼────┼────┼────┼────┼────┤
LocRP# Name Type Action Reg │rax │rcx │rbx │rdi │r12 │r13 │
──────────────────────────────┼────┼────┼────┼────┼────┼────┤
1.#0 BB1 PredBB0 │ │ │ │ │ │ │
14.#1 I0 Def Alloc rax │I0 a│ │ │ │ │ │
17.#2 I0 Use * Keep rax │I0 i│ │ │ │ │ │
20.#3 C1 Def Alloc rax │C1 a│ │ │ │ │ │
22.#4 I2 Def Alloc rdi │C1 a│ │ │I2 a│ │ │
23.#5 I3 Def Alloc mm0 │C1 a│ │ │I2 a│ │ │
23.#6 I2 Use * Keep rdi │C1 a│ │ │I2 i│ │ │
23.#7 C1 Use * Keep rax │C1 i│ │ │ │ │ │
23.#8 I3 Use * Keep mm0 │ │ │ │ │ │ │
32.#9 I4 Def Alloc rax │I4 a│ │ │ │ │ │
34.#10 I5 Def Alloc rdi │I4 a│ │ │I5 a│ │ │
35.#11 I5 Use * Keep rdi │I4 a│ │ │I5 i│ │ │
35.#12 I4 Use * Keep rax │I4 i│ │ │ │ │ │
41.#13 I6 Def Alloc rax │I6 a│ │ │ │ │ │
41.#14 I7 Def Alloc mm0 │I6 a│ │ │ │ │ │
41.#15 I6 Use * Keep rax │I6 i│ │ │ │ │ │
41.#16 I7 Use * Keep mm0 │ │ │ │ │ │ │
48.#17 rax Kill Keep rax │ │ │ │ │ │ │
48.#18 rcx Kill Keep rcx │ │ │ │ │ │ │
48.#19 rdx Kill Keep rdx │ │ │ │ │ │ │
48.#20 rsi Kill Keep rsi │ │ │ │ │ │ │
48.#21 rdi Kill Keep rdi │ │ │ │ │ │ │
48.#22 r8 Kill Keep r8 │ │ │ │ │ │ │
48.#23 r9 Kill Keep r9 │ │ │ │ │ │ │
48.#24 r10 Kill Keep r10 │ │ │ │ │ │ │
48.#25 r11 Kill Keep r11 │ │ │ │ │ │ │
52.#26 C8 Def Alloc rdi │ │ │ │C8 a│ │ │
53.#27 rdi Fixd Keep rdi │ │ │ │C8 a│ │ │
53.#28 C8 Use * Keep rdi │ │ │ │C8 i│ │ │
54.#29 rdi Fixd Keep rdi │ │ │ │ │ │ │
54.#30 I9 Def Alloc rdi │ │ │ │I9 a│ │ │
55.#31 rdi Fixd Keep rdi │ │ │ │I9 a│ │ │
55.#32 I9 Use * Keep rdi │ │ │ │I9 i│ │ │
56.#33 rax Kill Keep rax │ │ │ │ │ │ │
56.#34 rcx Kill Keep rcx │ │ │ │ │ │ │
56.#35 rdx Kill Keep rdx │ │ │ │ │ │ │
56.#36 rsi Kill Keep rsi │ │ │ │ │ │ │
56.#37 rdi Kill Keep rdi │ │ │ │ │ │ │
56.#38 r8 Kill Keep r8 │ │ │ │ │ │ │
56.#39 r9 Kill Keep r9 │ │ │ │ │ │ │
56.#40 r10 Kill Keep r10 │ │ │ │ │ │ │
56.#41 r11 Kill Keep r11 │ │ │ │ │ │ │
Recording the maximum number of concurrent spills:
----------
LSRA Stats
----------
Total Tracked Vars: 3
Total Reg Cand Vars: 0
Total number of Intervals: 9
Total number of RefPositions: 41
Total Spill Count: 0 Weighted: 0
Total CopyReg Count: 0 Weighted: 0
Total ResolutionMov Count: 0 Weighted: 0
Total number of split edges: 0
Total Number of spill temps created: 0
TUPLE STYLE DUMP WITH REGISTER ASSIGNMENTS
Incoming Parameters:
BB01 [000..029) (return), preds={} succs={}
=====
N003. IL_OFFSET IL offset: 0x0 REG NA
N005. CNS_INT 0 REG NA
N007. LCL_VAR_ADDR V00 loc0 NA REG NA
N009. STOREIND
N011. LCL_VAR_ADDR V00 loc0 NA REG NA
N013. rax = IND
N015. LCL_VAR_ADDR V05 tmp4 NA REG NA
N017. STOREIND ; rax
N019. rax = CNS_INT 0 REG rax
N021. rdi = LCL_VAR_ADDR V02 tmp1 d:3 rdi REG rdi
N023. STORE_BLK(24); rdi,rax
N025. CNS_INT 1 REG NA
N027. V02 MEM
N029. LCL_VAR_ADDR V05 tmp4 NA REG NA
N031. rax = IND
N033. rdi = LCL_FLD_ADDR V02 tmp1 ud:4->5[+16] Fseq[F6] rdi REG rdi
N035. STOREIND ; rdi,rax
N037. V02 MEM
N039. LCL_FLD_ADDR V03 tmp2 d:3[+0] Fseq[F0] NA (last use) REG NA
N041. STORE_BLK(24)
N043. IL_OFFSET IL offset: 0x14 REG NA
N045. IL_OFFSET IL offset: 0x14 REG NA
N047. CALL
N049. IL_OFFSET IL offset: 0x23 REG NA
N051. rdi = CNS_INT 0 REG rdi
N053. rdi = PUTARG_REG; rdi
N055. CALL ; rdi
N057. IL_OFFSET IL offset: 0x28 REG NA
N059. RETURN
Var=Reg end of BB01: none
*************** In genGenerateCode()
--------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
--------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..029) (return) i label target gcsafe LIR
--------------------------------------------------------------------------------------------------------------------------------------
*************** In fgDebugCheckBBlist
Finalizing stack frame
Recording Var Locations at start of BB01
<none>
Modified regs: [rax rcx rdx rsi rdi r8-r11 mm0]
Callee-saved registers pushed: 0 []
*************** In lvaAssignFrameOffsets(FINAL_FRAME_LAYOUT)
Assign V00 loc0, size=8, stkOffs=-0x18
Assign V02 tmp1, size=24, stkOffs=-0x30
Assign V03 tmp2, size=24, stkOffs=-0x48
Assign V05 tmp4, size=8, stkOffs=-0x50
; Final local variable assignments
;
; V00 loc0 [V00 ] ( 2, 2 ) struct ( 8) [rbp-0x08] do-not-enreg[XSF] must-init addr-exposed ld-addr-op
;# V01 OutArgs [V01 ] ( 1, 1 ) lclBlk ( 0) [rsp+0x00]
; V02 tmp1 [V02,T00] ( 4, 8 ) struct (24) [rbp-0x20] do-not-enreg[SFB]
; V03 tmp2 [V03,T01] ( 1, 2 ) struct (24) [rbp-0x38] do-not-enreg[SFB]
;* V04 tmp3 [V04,T02] ( 0, 0 ) int -> zero-ref
; V05 tmp4 [V05 ] ( 2, 4 ) struct ( 8) [rbp-0x40] do-not-enreg[XSF] addr-exposed
;* V06 tmp5 [V06 ] ( 0, 0 ) struct (24) zero-ref do-not-enreg[SB]
;
; Lcl frame size = 64
=============== Generating BB01 [000..029) (return), preds={} succs={} flags=0x00000000.400b0020: i label target gcsafe LIR
BB01 IN (0)={} + ByrefExposed + GcHeap
OUT(0)={}
Recording Var Locations at start of BB01
<none>
Liveness not changing: 0000000000000000 {}
Live regs: (unchanged) 00000000 {}
GC regs: (unchanged) 00000000 {}
Byref regs: (unchanged) 00000000 {}
L_M11705_BB01:
Label: IG02, GCvars=0000000000000000 {}, gcrefRegs=00000000 {}, byrefRegs=00000000 {}
Setting stack level from -572662307 to 0
Scope info: begin block BB01, IL range [000..029)
Scope info: open scopes =
<none>
Added IP mapping: 0x0000 STACK_EMPTY (G_M11705_IG02,ins#0,ofs#0) label
Generating: N003 ( 9, 8) [000006] ------------ IL_OFFSET void IL offset: 0x0 REG NA
Generating: N005 ( 1, 1) [000004] -c---------- t4 = CNS_INT int 0 REG NA $80
Generating: N007 ( 3, 2) [000002] Dc-----N---- t2 = LCL_VAR_ADDR byref V00 loc0 NA REG NA
┌──▌ t2 byref
├──▌ t4 int
Generating: N009 (???,???) [000102] -A---------- ▌ STOREIND byte REG NA
IN0001: mov byte ptr [V00 rbp-08H], 0
Generating: N011 ( 3, 2) [000007] -c-----N---- t7 = LCL_VAR_ADDR byref V00 loc0 NA REG NA
┌──▌ t7 byref
Generating: N013 ( 7, 6) [000016] x----------- t16 = ▌ IND byte REG rax <l:$1c0, c:$200>
IN0002: movsx rax, byte ptr [V00 rbp-08H]
Generating: N015 ( 3, 2) [000068] Dc-----N---- t68 = LCL_VAR_ADDR byref V05 tmp4 NA REG NA
┌──▌ t68 byref
├──▌ t16 byte
Generating: N017 (???,???) [000103] -A---------- ▌ STOREIND byte REG NA
IN0003: mov byte ptr [V05 rbp-40H], al
Generating: N019 ( 1, 1) [000051] ------------ t51 = CNS_INT long 0 REG rax $80
IN0004: xor rax, rax
Generating: N021 ( 3, 2) [000050] D------N---- t50 = LCL_VAR_ADDR byref V02 tmp1 d:3 rdi REG rdi
IN0005: lea rdi, bword ptr [V02 rbp-20H]
Byref regs: 00000000 {} => 00000080 {rdi}
┌──▌ t50 byref
├──▌ t51 long
Generating: N023 (???,???) [000104] -A---------- ▌ STORE_BLK(24) struct (init) (Unroll) REG NA
Byref regs: 00000080 {rdi} => 00000000 {}
IN0006: vxorps xmm0, xmm0
IN0007: vmovdqu qword ptr [rdi], xmm0
IN0008: mov qword ptr [rdi+16], rax
Generating: N025 ( 1, 1) [000056] -c---------- t56 = CNS_INT int 1 REG NA $85
┌──▌ t56 int
Generating: N027 ( 5, 6) [000058] UA---------- ▌ STORE_LCL_FLD int V02 tmp1 ud:3->0[+0] Fseq[F1] NA REG NA
IN0009: mov dword ptr [V02 rbp-20H], 1
Generating: N029 ( 3, 2) [000062] -c---------- t62 = LCL_VAR_ADDR byref V05 tmp4 NA REG NA
┌──▌ t62 byref
Generating: N031 ( 7, 6) [000099] x----------- t99 = ▌ IND byte REG rax <l:$1c1, c:$201>
IN000a: movsx rax, byte ptr [V05 rbp-40H]
Generating: N033 ( 3, 4) [000061] U------N---- t61 = LCL_FLD_ADDR byref V02 tmp1 ud:4->5[+16] Fseq[F6] rdi REG rdi
IN000b: lea rdi, bword ptr [V02+0x10 rbp-10H]
Byref regs: 00000000 {} => 00000080 {rdi}
┌──▌ t61 byref
├──▌ t99 byte
Generating: N035 (???,???) [000105] -A--G------- ▌ STOREIND byte REG NA
Byref regs: 00000080 {rdi} => 00000000 {}
IN000c: mov byte ptr [rdi], al
Generating: N037 ( 3, 2) [000081] -c---------- t81 = LCL_VAR struct V02 tmp1 u:5 NA (last use) REG NA <l:$182, c:$183>
Generating: N039 ( 3, 4) [000080] Dc-----N---- t80 = LCL_FLD_ADDR byref V03 tmp2 d:3[+0] Fseq[F0] NA (last use) REG NA
┌──▌ t80 byref
├──▌ t81 struct
Generating: N041 ( 6, 7) [000084] xA---------- ▌ STORE_BLK(24) struct (copy) (Unroll) REG NA
IN000d: vmovdqu xmm0, qword ptr [V02 rbp-20H]
IN000e: vmovdqu qword ptr [V03 rbp-38H], xmm0
IN000f: mov rax, qword ptr [V02+0x10 rbp-10H]
IN0010: mov qword ptr [V03+0x10 rbp-28H], rax
Added IP mapping: 0x0014 (G_M11705_IG02,ins#16,ofs#70)
Generating: N043 ( 3, 4) [000041] ------------ IL_OFFSET void IL offset: 0x14 REG NA
genIPmappingAdd: ignoring duplicate IL offset 0x80000014
Generating: N045 ( 14, 5) [000038] ------------ IL_OFFSET void IL offset: 0x14 REG NA
Generating: N047 ( 14, 5) [000037] --CXG------- CALL void Program.M $VN.Void
Call: GCvars=0000000000000000 {}, gcrefRegs=00000000 {}, byrefRegs=00000000 {}
IN0011: call Program:M()
Added IP mapping: 0x0023 (G_M11705_IG02,ins#17,ofs#75)
Generating: N049 ( 15, 7) [000045] ------------ IL_OFFSET void IL offset: 0x23 REG NA
Generating: N051 ( 1, 1) [000042] ------------ t42 = CNS_INT int 0 REG rdi $80
IN0012: xor edi, edi
┌──▌ t42 int
Generating: N053 (???,???) [000106] ------------ t106 = ▌ PUTARG_REG int REG rdi
┌──▌ t106 int arg0 in rdi
Generating: N055 ( 15, 7) [000043] --CXG------- ▌ CALL void System.Console.WriteLine $VN.Void
Call: GCvars=0000000000000000 {}, gcrefRegs=00000000 {}, byrefRegs=00000000 {}
IN0013: call System.Console:WriteLine(int)
Added IP mapping: 0x0028 STACK_EMPTY (G_M11705_IG02,ins#19,ofs#82)
Generating: N057 ( 0, 0) [000047] ------------ IL_OFFSET void IL offset: 0x28 REG NA
Generating: N059 ( 0, 0) [000046] ------------ RETURN void REG NA $440
Scope info: end block BB01, IL range [000..029)
Scope info: ending scope, LVnum=0 [000..029)
Scope info: open scopes =
<none>
Added IP mapping: EPILOG STACK_EMPTY (G_M11705_IG02,ins#19,ofs#82) label
Reserving epilog IG for block BB01
IN0014: nop
G_M11705_IG02: ; offs=000000H, funclet=00
*************** After placeholder IG creation
G_M11705_IG01: ; func=00, offs=000000H, size=0000H, gcrefRegs=00000000 {} <-- Prolog IG
G_M11705_IG02: ; offs=000000H, size=0053H, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref
G_M11705_IG03: ; epilog placeholder, next placeholder=<END>, BB01 [0000], epilog, emitadd <-- First placeholder <-- Last placeholder
; PrevGCVars=0000000000000000 {}, PrevGCrefRegs=00000000 {}, PrevByrefRegs=00000000 {}
; InitGCVars=0000000000000000 {}, InitGCrefRegs=00000000 {}, InitByrefRegs=00000000 {}
Liveness not changing: 0000000000000000 {}
# compCycleEstimate = 91, compSizeEstimate = 72 Program:Main()
; Final local variable assignments
;
; V00 loc0 [V00 ] ( 2, 2 ) struct ( 8) [rbp-0x08] do-not-enreg[XSF] must-init addr-exposed ld-addr-op
;# V01 OutArgs [V01 ] ( 1, 1 ) lclBlk ( 0) [rsp+0x00]
; V02 tmp1 [V02,T00] ( 4, 8 ) struct (24) [rbp-0x20] do-not-enreg[SFB]
; V03 tmp2 [V03,T01] ( 1, 2 ) struct (24) [rbp-0x38] do-not-enreg[SFB]
;* V04 tmp3 [V04,T02] ( 0, 0 ) int -> zero-ref
; V05 tmp4 [V05 ] ( 2, 4 ) struct ( 8) [rbp-0x40] do-not-enreg[XSF] addr-exposed
;* V06 tmp5 [V06 ] ( 0, 0 ) struct (24) zero-ref do-not-enreg[SB]
;
; Lcl frame size = 64
*************** Before prolog / epilog generation
G_M11705_IG01: ; func=00, offs=000000H, size=0000H, gcrefRegs=00000000 {} <-- Prolog IG
G_M11705_IG02: ; offs=000000H, size=0053H, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref
G_M11705_IG03: ; epilog placeholder, next placeholder=<END>, BB01 [0000], epilog, emitadd <-- First placeholder <-- Last placeholder
; PrevGCVars=0000000000000000 {}, PrevGCrefRegs=00000000 {}, PrevByrefRegs=00000000 {}
; InitGCVars=0000000000000000 {}, InitGCrefRegs=00000000 {}, InitByrefRegs=00000000 {}
Recording Var Locations at start of BB01
<none>
*************** In genFnProlog()
Added IP mapping to front: PROLOG STACK_EMPTY (G_M11705_IG01,ins#0,ofs#0) label
__prolog:
Found 2 lvMustInit stk vars, frame offsets 8 through 0
IN0015: push rbp
IN0016: sub rsp, 64
IN0017: vzeroupper
IN0018: lea rbp, [rsp+40H]
IN0019: xor rax, rax
IN001a: mov qword ptr [V00 rbp-08H], rax
*************** In genClearStackVec3ArgUpperBits()
*************** In genEnregisterIncomingStackArgs()
G_M11705_IG01: ; offs=000000H, funclet=00
*************** In genFnEpilog()
__epilog:
gcVarPtrSetCur=0000000000000000 {}, gcRegGCrefSetCur=00000000 {}, gcRegByrefSetCur=00000000 {}
IN001b: lea rsp, [rbp]
IN001c: pop rbp
IN001d: ret
G_M11705_IG03: ; offs=000053H, funclet=00
0 prologs, 1 epilogs, 0 funclet prologs, 0 funclet epilogs
*************** After prolog / epilog generation
G_M11705_IG01: ; func=00, offs=000000H, size=0013H, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref, nogc <-- Prolog IG
G_M11705_IG02: ; offs=000013H, size=0053H, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref
G_M11705_IG03: ; offs=000066H, size=0006H, epilog, nogc, emitadd
*************** In emitJumpDistBind()
Hot code size = 0x6C bytes
Cold code size = 0x0 bytes
reserveUnwindInfo(isFunclet=FALSE, isColdCode=FALSE, unwindSize=0x8)
*************** In emitEndCodeGen()
Converting emitMaxStackDepth from bytes (0) to elements (0)
***************************************************************************
Instructions as they come out of the scheduler
G_M11705_IG01: ; func=00, offs=000000H, size=0013H, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref, nogc <-- Prolog IG
IN0015: 000000 55 push rbp
IN0016: 000001 4883EC40 sub rsp, 64
IN0017: 000005 C5F877 vzeroupper
IN0018: 000008 488D6C2440 lea rbp, [rsp+40H]
IN0019: 00000D 33C0 xor rax, rax
IN001a: 00000F 488945F8 mov qword ptr [rbp-08H], rax
G_M11705_IG02: ; func=00, offs=000013H, size=0053H, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref
IN0001: 000013 C645F800 mov byte ptr [rbp-08H], 0
IN0002: 000017 480FBE45F8 movsx rax, byte ptr [rbp-08H]
IN0003: 00001C 8845C0 mov byte ptr [rbp-40H], al
IN0004: 00001F 33C0 xor rax, rax
byrReg +[rdi]
IN0005: 000021 488D7DE0 lea rdi, bword ptr [rbp-20H]
IN0006: 000025 C4E17857C0 vxorps xmm0, xmm0
IN0007: 00002A C4E17A7F07 vmovdqu qword ptr [rdi], xmm0
IN0008: 00002F 48894710 mov qword ptr [rdi+16], rax
IN0009: 000033 C745E001000000 mov dword ptr [rbp-20H], 1
IN000a: 00003A 480FBE45C0 movsx rax, byte ptr [rbp-40H]
IN000b: 00003F 488D7DF0 lea rdi, bword ptr [rbp-10H]
IN000c: 000043 8807 mov byte ptr [rdi], al
IN000d: 000045 C4E17A6F45E0 vmovdqu xmm0, qword ptr [rbp-20H]
IN000e: 00004B C4E17A7F45C8 vmovdqu qword ptr [rbp-38H], xmm0
IN000f: 000051 488B45F0 mov rax, qword ptr [rbp-10H]
IN0010: 000055 488945D8 mov qword ptr [rbp-28H], rax
New byrReg live regs=00000000 {}
; Call at 0059 [stk=0], GCvars=none, gcrefRegs=00000000 {}, byrefRegs=00000000 {}
IN0011: 000059 E8A2FBFFFF call Program:M()
IN0012: 00005E 33FF xor edi, edi
; Call at 0060 [stk=0], GCvars=none, gcrefRegs=00000000 {}, byrefRegs=00000000 {}
IN0013: 000060 E80BFCFFFF call System.Console:WriteLine(int)
IN0014: 000065 90 nop
G_M11705_IG03: ; func=00, offs=000066H, size=0006H, epilog, nogc, emitadd
IN001b: 000066 488D6500 lea rsp, [rbp]
IN001c: 00006A 5D pop rbp
IN001d: 00006B C3 ret
Allocated method code size = 108 , actual size = 108
*************** After end code gen, before unwindEmit()
G_M11705_IG01: ; func=00, offs=000000H, size=0013H, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref, nogc <-- Prolog IG
IN0015: 000000 push rbp
IN0016: 000001 sub rsp, 64
IN0017: 000005 vzeroupper
IN0018: 000008 lea rbp, [rsp+40H]
IN0019: 00000D xor rax, rax
IN001a: 00000F mov qword ptr [V00 rbp-08H], rax
G_M11705_IG02: ; offs=000013H, size=0053H, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref
IN0001: 000013 mov byte ptr [V00 rbp-08H], 0
IN0002: 000017 movsx rax, byte ptr [V00 rbp-08H]
IN0003: 00001C mov byte ptr [V05 rbp-40H], al
IN0004: 00001F xor rax, rax
IN0005: 000021 lea rdi, bword ptr [V02 rbp-20H]
IN0006: 000025 vxorps xmm0, xmm0
IN0007: 00002A vmovdqu qword ptr [rdi], xmm0
IN0008: 00002F mov qword ptr [rdi+16], rax
IN0009: 000033 mov dword ptr [V02 rbp-20H], 1
IN000a: 00003A movsx rax, byte ptr [V05 rbp-40H]
IN000b: 00003F lea rdi, bword ptr [V02+0x10 rbp-10H]
IN000c: 000043 mov byte ptr [rdi], al
IN000d: 000045 vmovdqu xmm0, qword ptr [V02 rbp-20H]
IN000e: 00004B vmovdqu qword ptr [V03 rbp-38H], xmm0
IN000f: 000051 mov rax, qword ptr [V02+0x10 rbp-10H]
IN0010: 000055 mov qword ptr [V03+0x10 rbp-28H], rax
IN0011: 000059 call Program:M()
IN0012: 00005E xor edi, edi
IN0013: 000060 call System.Console:WriteLine(int)
IN0014: 000065 nop
G_M11705_IG03: ; offs=000066H, size=0006H, epilog, nogc, emitadd
IN001b: 000066 lea rsp, [rbp]
IN001c: 00006A pop rbp
IN001d: 00006B ret
Unwind Info:
>> Start offset : 0x000000 (not in unwind data)
>> End offset : 0x00006c (not in unwind data)
Version : 1
Flags : 0x00
SizeOfProlog : 0x05
CountOfUnwindCodes: 2
FrameRegister : none (0)
FrameOffset : N/A (no FrameRegister) (Value=0)
UnwindCodes :
CodeOffset: 0x05 UnwindOp: UWOP_ALLOC_SMALL (2) OpInfo: 7 * 8 + 8 = 64 = 0x40
CodeOffset: 0x01 UnwindOp: UWOP_PUSH_NONVOL (0) OpInfo: rbp (5)
allocUnwindInfo(pHotCode=0x00007F8FCC2B21C0, pColdCode=0x0000000000000000, startOffset=0x0, endOffset=0x6c, unwindSize=0x8, pUnwindBlock=0x00000000022B7CA0, funKind=0 (main function))
*************** In genIPmappingGen()
IP mapping count : 6
IL offs PROLOG : 0x00000000 ( STACK_EMPTY )
IL offs 0x0000 : 0x00000013 ( STACK_EMPTY )
IL offs 0x0014 : 0x00000059
IL offs 0x0023 : 0x0000005E
IL offs 0x0028 : 0x00000065 ( STACK_EMPTY )
IL offs EPILOG : 0x00000065 ( STACK_EMPTY )
*************** In genSetScopeInfo()
VarLocInfo count is 0
*************** Variable debug info
0 vars
*************** In gcInfoBlockHdrSave()
Set code length to 108.
Set ReturnKind to Scalar.
Set stack base register to rbp.
Set Outgoing stack arg area size to 0.
Defining 2 call sites:
Offset 0x59, size 5.
Offset 0x60, size 5.
Method code size: 108
Allocations for Program:Main() (MethodHash=bef6ec1b)
count: 724, size: 69163, max = 3072
allocateMemory: 131072, nraUsed: 98000
Alloc'd bytes by kind:
kind | size | pct
---------------------+------------+--------
AssertionProp | 6460 | 9.34%
ASTNode | 10256 | 14.83%
InstDesc | 3688 | 5.33%
ImpStack | 0 | 0.00%
BasicBlock | 864 | 1.25%
fgArgInfo | 64 | 0.09%
fgArgInfoPtrArr | 8 | 0.01%
FlowList | 0 | 0.00%
TreeStatementList | 0 | 0.00%
SiScope | 0 | 0.00%
FlatFPStateX87 | 0 | 0.00%
DominatorMemory | 48 | 0.07%
LSRA | 3044 | 4.40%
LSRA_Interval | 800 | 1.16%
LSRA_RefPosition | 2688 | 3.89%
Reachability | 16 | 0.02%
SSA | 1380 | 2.00%
ValueNumber | 12714 | 18.38%
LvaTable | 2290
5 | 3.32%
UnwindInfo | 0 | 0.00%
hashBv | 40 | 0.06%
bitset | 216 | 0.31%
FixedBitVect | 0 | 0.00%
Generic | 1176 | 1.70%
IndirAssignMap | 0 | 0.00%
FieldSeqStore | 336 | 0.49%
ZeroOffsetFieldMap | 224 | 0.32%
ArrayInfoMap | 112 | 0.16%
MemoryPhiArg | 0 | 0.00%
CSE | 1184 | 1.71%
GC | 1338 | 1.93%
CorSig | 208 | 0.30%
Inlining | 1872 | 2.71%
ArrayStack | 0 | 0.00%
DebugInfo | 288 | 0.42%
DebugOnly | 17089 | 24.71%
Codegen | 0 | 0.00%
LoopOpt | 0 | 0.00%
LoopHoist | 0 | 0.00%
Unknown | 187 | 0.27%
RangeCheck | 0 | 0.00%
CopyProp | 568 | 0.82%
****** DONE compiling Program:Main()
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