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dump.txt
****** START compiling Program:M0() (MethodHash=c22fa56d)
Generating code for Windows x64
OPTIONS: compCodeOpt = BLENDED_CODE
OPTIONS: compDbgCode = false
OPTIONS: compDbgInfo = true
OPTIONS: compDbgEnC = false
OPTIONS: compProcedureSplitting = false
OPTIONS: compProcedureSplittingEH = false
OPTIONS: Stack probing is DISABLED
IL to import:
IL_0000 7e 05 00 00 04 ldsfld 0x4000005
IL_0005 7b 02 00 00 04 ldfld 0x4000002
IL_000a 7e 05 00 00 04 ldsfld 0x4000005
IL_000f 7b 01 00 00 04 ldfld 0x4000001
IL_0014 fe 04 clt
IL_0016 7e 05 00 00 04 ldsfld 0x4000005
IL_001b 7b 03 00 00 04 ldfld 0x4000003
IL_0020 7e 05 00 00 04 ldsfld 0x4000005
IL_0025 7b 03 00 00 04 ldfld 0x4000003
IL_002a fe 01 ceq
IL_002c 16 ldc.i4.0
IL_002d fe 01 ceq
IL_002f 61 xor
IL_0030 2c 14 brfalse.s 20 (IL_0046)
IL_0032 7e 05 00 00 04 ldsfld 0x4000005
IL_0037 7e 05 00 00 04 ldsfld 0x4000005
IL_003c 7b 02 00 00 04 ldfld 0x4000002
IL_0041 7d 02 00 00 04 stfld 0x4000002
IL_0046 2a ret
lvaGrabTemp returning 0 (V00 tmp0) (a long lifetime temp) called for OutgoingArgSpace.
; Initial local variable assignments
;
; V00 OutArgs lclBlk (na)
*************** In compInitDebuggingInfo() for Program:M0()
getVars() returned cVars = 0, extendOthers = true
info.compStmtOffsetsCount = 0
info.compStmtOffsetsImplicit = 0005h ( STACK_EMPTY CALL_SITE )
*************** In fgFindBasicBlocks() for Program:M0()
Jump targets:
IL_0046
New Basic Block BB01 [0000] created.
BB01 [000..032)
New Basic Block BB02 [0001] created.
BB02 [032..046)
New Basic Block BB03 [0002] created.
BB03 [046..047)
IL Code Size,Instr 71, 19, Basic Block count 3, Local Variable Num,Ref count 1, 0 for method Program:M0()
OPTIONS: opts.MinOpts() == false
Basic block list for 'Program:M0()'
--------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd weight [IL range] [jump] [EH region] [flags]
--------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..032)-> BB03 ( cond )
BB02 [0001] 1 1 [032..046)
BB03 [0002] 2 1 [046..047) (return)
--------------------------------------------------------------------------------------------------------------------------------------
*************** In impImport() for Program:M0()
impImportBlockPending for BB01
Importing BB01 (PC=000) of 'Program:M0()'
[ 0] 0 (0x000) ldsfld 04000005
[ 1] 5 (0x005) ldfld 04000002
[ 1] 10 (0x00a) ldsfld 04000005
[ 2] 15 (0x00f) ldfld 04000001
[ 2] 20 (0x014) clt
[ 1] 22 (0x016) ldsfld 04000005
[ 2] 27 (0x01b) ldfld 04000003
[ 2] 32 (0x020) ldsfld 04000005
[ 3] 37 (0x025) ldfld 04000003
[ 3] 42 (0x02a) ceq
[ 2] 44 (0x02c) ldc.i4.0 0
[ 3] 45 (0x02d) ceq
[ 2] 47 (0x02f) xor
[ 1] 48 (0x030) brfalse.s
[000017] ------------ * STMT void (IL 0x000... ???)
[000016] ---XG------- \--* JTRUE void
[000014] ------------ | /--* CNS_INT int 0
[000015] ---XG------- \--* EQ int
[000011] ------------ | /--* CNS_INT int 0
[000012] ---XG------- | /--* EQ int
[000009] ---XG------- | | | /--* FIELD int F8
[000008] ----G------- | | | | \--* FIELD ref s_1
[000010] ---XG------- | | \--* EQ int
[000007] ---XG------- | | \--* FIELD int F8
[000006] ----G------- | | \--* FIELD ref s_1
[000013] ---XG------- \--* XOR int
[000004] ---XG------- | /--* FIELD byte F0
[000003] ----G------- | | \--* FIELD ref s_1
[000005] ---XG------- \--* LT int
[000002] ---XG------- \--* FIELD ushort F7
[000001] ----G------- \--* FIELD ref s_1
impImportBlockPending for BB02
impImportBlockPending for BB03
Importing BB03 (PC=070) of 'Program:M0()'
[ 0] 70 (0x046) ret
[000020] ------------ * STMT void (IL 0x046... ???)
[000019] ------------ \--* RETURN void
Importing BB02 (PC=050) of 'Program:M0()'
[ 0] 50 (0x032) ldsfld 04000005
[ 1] 55 (0x037) ldsfld 04000005
[ 2] 60 (0x03c) ldfld 04000002
[ 2] 65 (0x041) stfld 04000002
[000027] ------------ * STMT void (IL 0x032... ???)
[000024] ---XG------- | /--* FIELD ushort F7
[000023] ----G------- | | \--* FIELD ref s_1
[000026] -A-XG------- \--* ASG ushort
[000025] ---XG--N---- \--* FIELD ushort F7
[000022] ----G------- \--* FIELD ref s_1
impImportBlockPending for BB03
New BlockSet epoch 1, # of blocks (including unused BB00): 4, bitset array size: 1 (short)
*************** In fgMorph()
*************** In fgDebugCheckBBlist
*************** In fgInline()
*************** After fgInline()
--------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd weight [IL range] [jump] [EH region] [flags]
--------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..032)-> BB03 ( cond ) i
BB02 [0001] 1 1 [032..046) i
BB03 [0002] 2 1 [046..047) (return) i
--------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [000..032) -> BB03 (cond), preds={} succs={BB02,BB03}
***** BB01, stmt 1
[000017] ------------ * STMT void (IL 0x000...0x030)
[000016] ---XG------- \--* JTRUE void
[000014] ------------ | /--* CNS_INT int 0
[000015] ---XG------- \--* EQ int
[000011] ------------ | /--* CNS_INT int 0
[000012] ---XG------- | /--* EQ int
[000009] ---XG------- | | | /--* FIELD int F8
[000008] ----G------- | | | | \--* FIELD ref s_1
[000010] ---XG------- | | \--* EQ int
[000007] ---XG------- | | \--* FIELD int F8
[000006] ----G------- | | \--* FIELD ref s_1
[000013] ---XG------- \--* XOR int
[000004] ---XG------- | /--* FIELD byte F0
[000003] ----G------- | | \--* FIELD ref s_1
[000005] ---XG------- \--* LT int
[000002] ---XG------- \--* FIELD ushort F7
[000001] ----G------- \--* FIELD ref s_1
------------ BB02 [032..046), preds={} succs={BB03}
***** BB02, stmt 2
[000027] ------------ * STMT void (IL 0x032...0x041)
[000024] ---XG------- | /--* FIELD ushort F7
[000023] ----G------- | | \--* FIELD ref s_1
[000026] -A-XG------- \--* ASG ushort
[000025] ---XG--N---- \--* FIELD ushort F7
[000022] ----G------- \--* FIELD ref s_1
------------ BB03 [046..047) (return), preds={} succs={}
***** BB03, stmt 3
[000020] ------------ * STMT void (IL 0x046...0x046)
[000019] ------------ \--* RETURN void
-------------------------------------------------------------------------------------------------------------------
*************** Exception Handling table is empty
**************** Inline Tree
Inlines into 06000003 Program:M0()
Budget: initialTime=273, finalTime=273, initialBudget=2730, currentBudget=2730
Budget: initialSize=1750, finalSize=1750
*************** After fgAddInternal()
--------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd weight [IL range] [jump] [EH region] [flags]
--------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..032)-> BB03 ( cond ) i
BB02 [0001] 1 1 [032..046) i
BB03 [0002] 2 1 [046..047) (return) i
--------------------------------------------------------------------------------------------------------------------------------------
*************** Exception Handling table is empty
*************** In fgDebugCheckBBlist
*************** In fgRemoveEmptyTry()
No EH in this method, nothing to remove.
*************** In fgRemoveEmptyFinally()
No EH in this method, nothing to remove.
*************** In fgMergeFinallyChains()
No EH in this method, nothing to merge.
*************** In fgCloneFinally()
No EH in this method, no cloning.
*************** In fgMarkImplicitByRefs()
*************** In fgPromoteStructs()
lvaTable before fgPromoteStructs
; Initial local variable assignments
;
; V00 OutArgs lclBlk (na)
lvaTable after fgPromoteStructs
; Initial local variable assignments
;
; V00 OutArgs lclBlk (na)
*************** In fgMarkAddressExposedLocals()
*************** In fgRetypeImplicitByRefArgs()
*************** In fgMorphBlocks()
Morphing BB01 of 'Program:M0()'
fgMorphTree BB01, stmt 1 (before)
[000016] ---XG------- * JTRUE void
[000014] ------------ | /--* CNS_INT int 0
[000015] ---XG------- \--* EQ int
[000011] ------------ | /--* CNS_INT int 0
[000012] ---XG------- | /--* EQ int
[000009] ---XG------- | | | /--* FIELD int F8
[000008] ----G------- | | | | \--* FIELD ref s_1
[000010] ---XG------- | | \--* EQ int
[000007] ---XG------- | | \--* FIELD int F8
[000006] ----G------- | | \--* FIELD ref s_1
[000013] ---XG------- \--* XOR int
[000004] ---XG------- | /--* FIELD byte F0
[000003] ----G------- | | \--* FIELD ref s_1
[000005] ---XG------- \--* LT int
[000002] ---XG------- \--* FIELD ushort F7
[000001] ----G------- \--* FIELD ref s_1
fgMorphTree BB01, stmt 1 (after)
[000016] ---XG+------ * JTRUE void
[000014] -----+------ | /--* CNS_INT int 0
[000015] J--XG+-N---- \--* EQ int
[000009] ---XG+------ | /--* IND int
[000037] -----+------ | | | /--* CNS_INT long 8 field offset Fseq[F8]
[000038] ----G+------ | | \--* ADD byref
[000008] x---G+------ | | \--* IND ref
[000039] -----+------ | | \--* CNS_INT(h) long 0x1c4f1e92978 static Fseq[s_1]
[000010] ---XG+------ | /--* NE int
[000007] ---XG+------ | | \--* IND int
[000034] -----+------ | | | /--* CNS_INT long 8 field offset Fseq[F8]
[000035] ----G+------ | | \--* ADD byref
[000006] x---G+------ | | \--* IND ref
[000036] -----+------ | | \--* CNS_INT(h) long 0x1c4f1e92978 static Fseq[s_1]
[000013] ---XG+------ \--* XOR int
[000004] ---XG+------ | /--* IND byte
[000031] -----+------ | | | /--* CNS_INT long 14 field offset Fseq[F0]
[000032] ----G+------ | | \--* ADD byref
[000003] x---G+------ | | \--* IND ref
[000033] -----+------ | | \--* CNS_INT(h) long 0x1c4f1e92978 static Fseq[s_1]
[000005] ---XG+------ \--* LT int
[000002] ---XG+------ \--* IND ushort
[000028] -----+------ | /--* CNS_INT long 12 field offset Fseq[F7]
[000029] ----G+------ \--* ADD byref
[000001] x---G+------ \--* IND ref
[000030] -----+------ \--* CNS_INT(h) long 0x1c4f1e92978 static Fseq[s_1]
Morphing BB02 of 'Program:M0()'
fgMorphTree BB02, stmt 2 (before)
[000024] ---XG------- /--* FIELD ushort F7
[000023] ----G------- | \--* FIELD ref s_1
[000026] -A-XG------- * ASG ushort
[000025] ---XG--N---- \--* FIELD ushort F7
[000022] ----G------- \--* FIELD ref s_1
fgMorphTree BB02, stmt 2 (after)
[000024] ---XG+------ /--* IND ushort
[000043] -----+------ | | /--* CNS_INT long 12 field offset Fseq[F7]
[000044] ----G+------ | \--* ADD byref
[000023] x---G+------ | \--* IND ref
[000045] -----+------ | \--* CNS_INT(h) long 0x1c4f1e92978 static Fseq[s_1]
[000026] -A-XG+------ * ASG ushort
[000025] ---XG+-N---- \--* IND ushort
[000040] -----+------ | /--* CNS_INT long 12 field offset Fseq[F7]
[000041] ----G+------ \--* ADD byref
[000022] x---G+------ \--* IND ref
[000042] -----+------ \--* CNS_INT(h) long 0x1c4f1e92978 static Fseq[s_1]
Morphing BB03 of 'Program:M0()'
fgMorphTree BB03, stmt 3 (before)
[000019] ------------ * RETURN void
Renumbering the basic blocks for fgComputePred
*************** Before renumbering the basic blocks
--------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd weight [IL range] [jump] [EH region] [flags]
--------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..032)-> BB03 ( cond ) i
BB02 [0001] 1 1 [032..046) i
BB03 [0002] 2 1 [046..047) (return) i
--------------------------------------------------------------------------------------------------------------------------------------
*************** Exception Handling table is empty
*************** After renumbering the basic blocks
=============== No blocks renumbered!
*************** In fgComputePreds()
--------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd weight [IL range] [jump] [EH region] [flags]
--------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..032)-> BB03 ( cond ) i
BB02 [0001] 1 1 [032..046) i
BB03 [0002] 2 1 [046..047) (return) i
--------------------------------------------------------------------------------------------------------------------------------------
*************** After fgComputePreds()
--------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
--------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..032)-> BB03 ( cond ) i label target
BB02 [0001] 1 BB01 1 [032..046) i
BB03 [0002] 2 BB01,BB02 1 [046..047) (return) i label target
--------------------------------------------------------------------------------------------------------------------------------------
*************** In fgComputeEdgeWeights()
fgComputeEdgeWeights() we do not have any profile data so we are not using the edge weights
--------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
--------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..032)-> BB03 ( cond ) i label target
BB02 [0001] 1 BB01 1 [032..046) i
BB03 [0002] 2 BB01,BB02 1 [046..047) (return) i label target
--------------------------------------------------------------------------------------------------------------------------------------
fgComputeEdgeWeights() was able to compute exact edge weights for all of the 3 edges, using 1 passes.
Edge weights into BB02 :BB01 (100)
Edge weights into BB03 :BB01 (0), BB02 (100)
*************** In fgCreateFunclets()
After fgCreateFunclets()
--------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
--------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..032)-> BB03 ( cond ) i label target
BB02 [0001] 1 BB01 1 [032..046) i
BB03 [0002] 2 BB01,BB02 1 [046..047) (return) i label target
--------------------------------------------------------------------------------------------------------------------------------------
*************** Exception Handling table is empty
*************** In fgDebugCheckBBlist
*************** In optOptimizeLayout()
*************** Exception Handling table is empty
*************** In fgDebugCheckBBlist
*************** In fgUpdateFlowGraph()
Before updating the flow graph:
--------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
--------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..032)-> BB03 ( cond ) i label target
BB02 [0001] 1 BB01 1 [032..046) i
BB03 [0002] 2 BB01,BB02 1 [046..047) (return) i label target
--------------------------------------------------------------------------------------------------------------------------------------
*************** In fgDebugCheckBBlist
*************** In fgExpandRarelyRunBlocks()
*************** In fgReorderBlocks()
Initial BasicBlocks
--------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
--------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..032)-> BB03 ( cond ) i label target
BB02 [0001] 1 BB01 1 [032..046) i
BB03 [0002] 2 BB01,BB02 1 [046..047) (return) i label target
--------------------------------------------------------------------------------------------------------------------------------------
*************** In fgUpdateFlowGraph()
Before updating the flow graph:
--------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
--------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..032)-> BB03 ( cond ) i label target
BB02 [0001] 1 BB01 1 [032..046) i
BB03 [0002] 2 BB01,BB02 1 [046..047) (return) i label target
--------------------------------------------------------------------------------------------------------------------------------------
*************** In fgDebugCheckBBlist
*************** In fgComputeReachability
*************** In fgDebugCheckBBlist
Renumbering the basic blocks for fgComputeReachability pass #1
*************** Before renumbering the basic blocks
--------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
--------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..032)-> BB03 ( cond ) i label target
BB02 [0001] 1 BB01 1 [032..046) i
BB03 [0002] 2 BB01,BB02 1 [046..047) (return) i label target
--------------------------------------------------------------------------------------------------------------------------------------
*************** Exception Handling table is empty
*************** After renumbering the basic blocks
=============== No blocks renumbered!
Enter blocks: BB01
After computing reachability sets:
------------------------------------------------
BBnum Reachable by
------------------------------------------------
BB01 : BB01
BB02 : BB01 BB02
BB03 : BB01 BB02 BB03
After computing reachability:
--------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
--------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..032)-> BB03 ( cond ) i label target
BB02 [0001] 1 BB01 1 [032..046) i
BB03 [0002] 2 BB01,BB02 1 [046..047) (return) i label target
--------------------------------------------------------------------------------------------------------------------------------------
*************** In fgDebugCheckBBlist
*************** In fgComputeDoms
*************** In fgDebugCheckBBlist
Dominator computation start blocks (those blocks with no incoming edges):
BB01
------------------------------------------------
BBnum Dominated by
------------------------------------------------
BB01: BB01
BB02: BB02 BB01
BB03: BB03 BB01
Inside fgBuildDomTree
After computing the Dominance Tree:
BB01 : BB03 BB02
*************** In Allocate Objects
Trees before Allocate Objects
--------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
--------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..032)-> BB03 ( cond ) i label target
BB02 [0001] 1 BB01 1 [032..046) i
BB03 [0002] 2 BB01,BB02 1 [046..047) (return) i label target
--------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [000..032) -> BB03 (cond), preds={} succs={BB02,BB03}
***** BB01, stmt 1
[000017] ------------ * STMT void (IL 0x000...0x030)
[000016] ---XG+------ \--* JTRUE void
[000014] -----+------ | /--* CNS_INT int 0
[000015] J--XG+-N---- \--* EQ int
[000009] ---XG+------ | /--* IND int
[000037] -----+------ | | | /--* CNS_INT long 8 field offset Fseq[F8]
[000038] ----G+------ | | \--* ADD byref
[000008] x---G+------ | | \--* IND ref
[000039] -----+------ | | \--* CNS_INT(h) long 0x1c4f1e92978 static Fseq[s_1]
[000010] ---XG+------ | /--* NE int
[000007] ---XG+------ | | \--* IND int
[000034] -----+------ | | | /--* CNS_INT long 8 field offset Fseq[F8]
[000035] ----G+------ | | \--* ADD byref
[000006] x---G+------ | | \--* IND ref
[000036] -----+------ | | \--* CNS_INT(h) long 0x1c4f1e92978 static Fseq[s_1]
[000013] ---XG+------ \--* XOR int
[000004] ---XG+------ | /--* IND byte
[000031] -----+------ | | | /--* CNS_INT long 14 field offset Fseq[F0]
[000032] ----G+------ | | \--* ADD byref
[000003] x---G+------ | | \--* IND ref
[000033] -----+------ | | \--* CNS_INT(h) long 0x1c4f1e92978 static Fseq[s_1]
[000005] ---XG+------ \--* LT int
[000002] ---XG+------ \--* IND ushort
[000028] -----+------ | /--* CNS_INT long 12 field offset Fseq[F7]
[000029] ----G+------ \--* ADD byref
[000001] x---G+------ \--* IND ref
[000030] -----+------ \--* CNS_INT(h) long 0x1c4f1e92978 static Fseq[s_1]
------------ BB02 [032..046), preds={BB01} succs={BB03}
***** BB02, stmt 2
[000027] ------------ * STMT void (IL 0x032...0x041)
[000024] ---XG+------ | /--* IND ushort
[000043] -----+------ | | | /--* CNS_INT long 12 field offset Fseq[F7]
[000044] ----G+------ | | \--* ADD byref
[000023] x---G+------ | | \--* IND ref
[000045] -----+------ | | \--* CNS_INT(h) long 0x1c4f1e92978 static Fseq[s_1]
[000026] -A-XG+------ \--* ASG ushort
[000025] ---XG+-N---- \--* IND ushort
[000040] -----+------ | /--* CNS_INT long 12 field offset Fseq[F7]
[000041] ----G+------ \--* ADD byref
[000022] x---G+------ \--* IND ref
[000042] -----+------ \--* CNS_INT(h) long 0x1c4f1e92978 static Fseq[s_1]
------------ BB03 [046..047) (return), preds={BB01,BB02} succs={}
***** BB03, stmt 3
[000020] ------------ * STMT void (IL 0x046...0x046)
[000019] -----+------ \--* RETURN void
-------------------------------------------------------------------------------------------------------------------
*************** Exiting Allocate Objects
Trees after Allocate Objects
--------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
--------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..032)-> BB03 ( cond ) i label target
BB02 [0001] 1 BB01 1 [032..046) i
BB03 [0002] 2 BB01,BB02 1 [046..047) (return) i label target
--------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [000..032) -> BB03 (cond), preds={} succs={BB02,BB03}
***** BB01, stmt 1
[000017] ------------ * STMT void (IL 0x000...0x030)
[000016] ---XG+------ \--* JTRUE void
[000014] -----+------ | /--* CNS_INT int 0
[000015] J--XG+-N---- \--* EQ int
[000009] ---XG+------ | /--* IND int
[000037] -----+------ | | | /--* CNS_INT long 8 field offset Fseq[F8]
[000038] ----G+------ | | \--* ADD byref
[000008] x---G+------ | | \--* IND ref
[000039] -----+------ | | \--* CNS_INT(h) long 0x1c4f1e92978 static Fseq[s_1]
[000010] ---XG+------ | /--* NE int
[000007] ---XG+------ | | \--* IND int
[000034] -----+------ | | | /--* CNS_INT long 8 field offset Fseq[F8]
[000035] ----G+------ | | \--* ADD byref
[000006] x---G+------ | | \--* IND ref
[000036] -----+------ | | \--* CNS_INT(h) long 0x1c4f1e92978 static Fseq[s_1]
[000013] ---XG+------ \--* XOR int
[000004] ---XG+------ | /--* IND byte
[000031] -----+------ | | | /--* CNS_INT long 14 field offset Fseq[F0]
[000032] ----G+------ | | \--* ADD byref
[000003] x---G+------ | | \--* IND ref
[000033] -----+------ | | \--* CNS_INT(h) long 0x1c4f1e92978 static Fseq[s_1]
[000005] ---XG+------ \--* LT int
[000002] ---XG+------ \--* IND ushort
[000028] -----+------ | /--* CNS_INT long 12 field offset Fseq[F7]
[000029] ----G+------ \--* ADD byref
[000001] x---G+------ \--* IND ref
[000030] -----+------ \--* CNS_INT(h) long 0x1c4f1e92978 static Fseq[s_1]
------------ BB02 [032..046), preds={BB01} succs={BB03}
***** BB02, stmt 2
[000027] ------------ * STMT void (IL 0x032...0x041)
[000024] ---XG+------ | /--* IND ushort
[000043] -----+------ | | | /--* CNS_INT long 12 field offset Fseq[F7]
[000044] ----G+------ | | \--* ADD byref
[000023] x---G+------ | | \--* IND ref
[000045] -----+------ | | \--* CNS_INT(h) long 0x1c4f1e92978 static Fseq[s_1]
[000026] -A-XG+------ \--* ASG ushort
[000025] ---XG+-N---- \--* IND ushort
[000040] -----+------ | /--* CNS_INT long 12 field offset Fseq[F7]
[000041] ----G+------ \--* ADD byref
[000022] x---G+------ \--* IND ref
[000042] -----+------ \--* CNS_INT(h) long 0x1c4f1e92978 static Fseq[s_1]
------------ BB03 [046..047) (return), preds={BB01,BB02} succs={}
***** BB03, stmt 3
[000020] ------------ * STMT void (IL 0x046...0x046)
[000019] -----+------ \--* RETURN void
-------------------------------------------------------------------------------------------------------------------
*************** In fgDebugCheckBBlist
*************** In optOptimizeLoops()
After optSetBlockWeights:
--------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
--------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..032)-> BB03 ( cond ) i label target
BB02 [0001] 1 BB01 0.50 [032..046) i
BB03 [0002] 2 BB01,BB02 1 [046..047) (return) i label target
--------------------------------------------------------------------------------------------------------------------------------------
*************** In fgDebugCheckBBlist
*************** In optCloneLoops()
*************** In lvaMarkLocalVars()
*** marking local variables in block BB01 (weight=1 )
[000017] ------------ * STMT void (IL 0x000...0x030)
[000016] ---XG+------ \--* JTRUE void
[000014] -----+------ | /--* CNS_INT int 0
[000015] J--XG+-N---- \--* EQ int
[000009] ---XG+------ | /--* IND int
[000037] -----+------ | | | /--* CNS_INT long 8 field offset Fseq[F8]
[000038] ----G+------ | | \--* ADD byref
[000008] x---G+------ | | \--* IND ref
[000039] -----+------ | | \--* CNS_INT(h) long 0x1c4f1e92978 static Fseq[s_1]
[000010] ---XG+------ | /--* NE int
[000007] ---XG+------ | | \--* IND int
[000034] -----+------ | | | /--* CNS_INT long 8 field offset Fseq[F8]
[000035] ----G+------ | | \--* ADD byref
[000006] x---G+------ | | \--* IND ref
[000036] -----+------ | | \--* CNS_INT(h) long 0x1c4f1e92978 static Fseq[s_1]
[000013] ---XG+------ \--* XOR int
[000004] ---XG+------ | /--* IND byte
[000031] -----+------ | | | /--* CNS_INT long 14 field offset Fseq[F0]
[000032] ----G+------ | | \--* ADD byref
[000003] x---G+------ | | \--* IND ref
[000033] -----+------ | | \--* CNS_INT(h) long 0x1c4f1e92978 static Fseq[s_1]
[000005] ---XG+------ \--* LT int
[000002] ---XG+------ \--* IND ushort
[000028] -----+------ | /--* CNS_INT long 12 field offset Fseq[F7]
[000029] ----G+------ \--* ADD byref
[000001] x---G+------ \--* IND ref
[000030] -----+------ \--* CNS_INT(h) long 0x1c4f1e92978 static Fseq[s_1]
*** marking local variables in block BB02 (weight=0.50)
[000027] ------------ * STMT void (IL 0x032...0x041)
[000024] ---XG+------ | /--* IND ushort
[000043] -----+------ | | | /--* CNS_INT long 12 field offset Fseq[F7]
[000044] ----G+------ | | \--* ADD byref
[000023] x---G+------ | | \--* IND ref
[000045] -----+------ | | \--* CNS_INT(h) long 0x1c4f1e92978 static Fseq[s_1]
[000026] -A-XG+------ \--* ASG ushort
[000025] ---XG+-N---- \--* IND ushort
[000040] -----+------ | /--* CNS_INT long 12 field offset Fseq[F7]
[000041] ----G+------ \--* ADD byref
[000022] x---G+------ \--* IND ref
[000042] -----+------ \--* CNS_INT(h) long 0x1c4f1e92978 static Fseq[s_1]
*** marking local variables in block BB03 (weight=1 )
[000020] ------------ * STMT void (IL 0x046...0x046)
[000019] -----+------ \--* RETURN void
*************** In optAddCopies()
refCnt table for 'M0':
V00 OutArgs [lclBlk]: refCnt = 1, refCntWtd = 1
*************** In optOptimizeBools()
*************** In fgDebugCheckBBlist
*************** In fgFindOperOrder()
*************** In fgSetBlockOrder()
The biggest BB has 26 tree nodes
--------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
--------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..032)-> BB03 ( cond ) i label target
BB02 [0001] 1 BB01 0.50 [032..046) i
BB03 [0002] 2 BB01,BB02 1 [046..047) (return) i label target
--------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [000..032) -> BB03 (cond), preds={} succs={BB02,BB03}
***** BB01, stmt 1
( 47, 69) [000017] ------------ * STMT void (IL 0x000...0x030)
N026 ( 47, 69) [000016] ---XG------- \--* JTRUE void
N024 ( 1, 1) [000014] ------------ | /--* CNS_INT int 0
N025 ( 45, 67) [000015] J--XG--N---- \--* EQ int
N021 ( 8, 15) [000009] ---XG------- | /--* IND int
N019 ( 1, 1) [000037] ------------ | | | /--* CNS_INT long 8 field offset Fseq[F8]
N020 ( 6, 13) [000038] ----G--N---- | | \--* ADD byref
N018 ( 5, 12) [000008] x---G------- | | \--* IND ref
N017 ( 3, 10) [000039] ------------ | | \--* CNS_INT(h) long 0x1c4f1e92978 static Fseq[s_1]
N022 ( 20, 31) [000010] ---XG------- | /--* NE int
N016 ( 8, 15) [000007] ---XG------- | | \--* IND int
N014 ( 1, 1) [000034] ------------ | | | /--* CNS_INT long 8 field offset Fseq[F8]
N015 ( 6, 13) [000035] ----G--N---- | | \--* ADD byref
N013 ( 5, 12) [000006] x---G------- | | \--* IND ref
N012 ( 3, 10) [000036] ------------ | | \--* CNS_INT(h) long 0x1c4f1e92978 static Fseq[s_1]
N023 ( 43, 65) [000013] ---XG------- \--* XOR int
N010 ( 9, 16) [000004] ---XG------- | /--* IND byte
N008 ( 1, 1) [000031] ------------ | | | /--* CNS_INT long 14 field offset Fseq[F0]
N009 ( 6, 13) [000032] ----G--N---- | | \--* ADD byref
N007 ( 5, 12) [000003] x---G------- | | \--* IND ref
N006 ( 3, 10) [000033] ------------ | | \--* CNS_INT(h) long 0x1c4f1e92978 static Fseq[s_1]
N011 ( 22, 33) [000005] ---XG------- \--* LT int
N005 ( 9, 16) [000002] ---XG------- \--* IND ushort
N003 ( 1, 1) [000028] ------------ | /--* CNS_INT long 12 field offset Fseq[F7]
N004 ( 6, 13) [000029] ----G--N---- \--* ADD byref
N002 ( 5, 12) [000001] x---G------- \--* IND ref
N001 ( 3, 10) [000030] ------------ \--* CNS_INT(h) long 0x1c4f1e92978 static Fseq[s_1]
------------ BB02 [032..046), preds={BB01} succs={BB03}
***** BB02, stmt 2
( 19, 33) [000027] ------------ * STMT void (IL 0x032...0x041)
N010 ( 9, 16) [000024] ---XG------- | /--* IND ushort
N008 ( 1, 1) [000043] ------------ | | | /--* CNS_INT long 12 field offset Fseq[F7]
N009 ( 6, 13) [000044] ----G--N---- | | \--* ADD byref
N007 ( 5, 12) [000023] x---G------- | | \--* IND ref
N006 ( 3, 10) [000045] ------------ | | \--* CNS_INT(h) long 0x1c4f1e92978 static Fseq[s_1]
N011 ( 19, 33) [000026] -A-XG------- \--* ASG ushort
N005 ( 9, 16) [000025] ---XG--N---- \--* IND ushort
N003 ( 1, 1) [000040] ------------ | /--* CNS_INT long 12 field offset Fseq[F7]
N004 ( 6, 13) [000041] ----G--N---- \--* ADD byref
N002 ( 5, 12) [000022] x---G------- \--* IND ref
N001 ( 3, 10) [000042] ------------ \--* CNS_INT(h) long 0x1c4f1e92978 static Fseq[s_1]
------------ BB03 [046..047) (return), preds={BB01,BB02} succs={}
***** BB03, stmt 3
( 0, 0) [000020] ------------ * STMT void (IL 0x046...0x046)
N001 ( 0, 0) [000019] ------------ \--* RETURN void
-------------------------------------------------------------------------------------------------------------------
*************** In SsaBuilder::Build()
[SsaBuilder] Max block count is 4.
--------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
--------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..032)-> BB03 ( cond ) i label target
BB02 [0001] 1 BB01 0.50 [032..046) i
BB03 [0002] 2 BB01,BB02 1 [046..047) (return) i label target
--------------------------------------------------------------------------------------------------------------------------------------
*************** Exception Handling table is empty
[SsaBuilder] Topologically sorted the graph.
[SsaBuilder::ComputeImmediateDom]
*************** In SsaBuilder::ComputeDominators(BasicBlock** postOrder, int count, ...)
*************** In SsaBuilder::InsertPhiFunctions()
*************** In fgLocalVarLiveness()
*************** In fgPerBlockLocalVarLiveness()
BB01 USE(0)={} + ByrefExposed + GcHeap
DEF(0)={}
BB02 USE(0)={} + ByrefExposed + GcHeap
DEF(0)={} + ByrefExposed + GcHeap
BB03 USE(0)={}
DEF(0)={}
** Memory liveness computed, GcHeap states and ByrefExposed states match
*************** In fgInterBlockLocalVarLiveness()
BB liveness after fgLiveVarAnalysis():
BB01 IN (0)={} + ByrefExposed + GcHeap
OUT(0)={} + ByrefExposed + GcHeap
BB02 IN (0)={} + ByrefExposed + GcHeap
OUT(0)={}
BB03 IN (0)={}
OUT(0)={}
Inserting phi functions:
*************** In SsaBuilder::RenameVariables()
After fgSsaBuild:
--------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
--------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..032)-> BB03 ( cond ) i label target
BB02 [0001] 1 BB01 0.50 [032..046) i
BB03 [0002] 2 BB01,BB02 1 [046..047) (return) i label target
--------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [000..032) -> BB03 (cond), preds={} succs={BB02,BB03}
***** BB01, stmt 1
( 47, 69) [000017] ------------ * STMT void (IL 0x000...0x030)
N026 ( 47, 69) [000016] ---XG------- \--* JTRUE void
N024 ( 1, 1) [000014] ------------ | /--* CNS_INT int 0
N025 ( 45, 67) [000015] J--XG--N---- \--* EQ int
N021 ( 8, 15) [000009] ---XG------- | /--* IND int
N019 ( 1, 1) [000037] ------------ | | | /--* CNS_INT long 8 field offset Fseq[F8]
N020 ( 6, 13) [000038] ----G--N---- | | \--* ADD byref
N018 ( 5, 12) [000008] x---G------- | | \--* IND ref
N017 ( 3, 10) [000039] ------------ | | \--* CNS_INT(h) long 0x1c4f1e92978 static Fseq[s_1]
N022 ( 20, 31) [000010] ---XG------- | /--* NE int
N016 ( 8, 15) [000007] ---XG------- | | \--* IND int
N014 ( 1, 1) [000034] ------------ | | | /--* CNS_INT long 8 field offset Fseq[F8]
N015 ( 6, 13) [000035] ----G--N---- | | \--* ADD byref
N013 ( 5, 12) [000006] x---G------- | | \--* IND ref
N012 ( 3, 10) [000036] ------------ | | \--* CNS_INT(h) long 0x1c4f1e92978 static Fseq[s_1]
N023 ( 43, 65) [000013] ---XG------- \--* XOR int
N010 ( 9, 16) [000004] ---XG------- | /--* IND byte
N008 ( 1, 1) [000031] ------------ | | | /--* CNS_INT long 14 field offset Fseq[F0]
N009 ( 6, 13) [000032] ----G--N---- | | \--* ADD byref
N007 ( 5, 12) [000003] x---G------- | | \--* IND ref
N006 ( 3, 10) [000033] ------------ | | \--* CNS_INT(h) long 0x1c4f1e92978 static Fseq[s_1]
N011 ( 22, 33) [000005] ---XG------- \--* LT int
N005 ( 9, 16) [000002] ---XG------- \--* IND ushort
N003 ( 1, 1) [000028] ------------ | /--* CNS_INT long 12 field offset Fseq[F7]
N004 ( 6, 13) [000029] ----G--N---- \--* ADD byref
N002 ( 5, 12) [000001] x---G------- \--* IND ref
N001 ( 3, 10) [000030] ------------ \--* CNS_INT(h) long 0x1c4f1e92978 static Fseq[s_1]
------------ BB02 [032..046), preds={BB01} succs={BB03}
***** BB02, stmt 2
( 19, 33) [000027] ------------ * STMT void (IL 0x032...0x041)
N010 ( 9, 16) [000024] ---XG------- | /--* IND ushort
N008 ( 1, 1) [000043] ------------ | | | /--* CNS_INT long 12 field offset Fseq[F7]
N009 ( 6, 13) [000044] ----G--N---- | | \--* ADD byref
N007 ( 5, 12) [000023] x---G------- | | \--* IND ref
N006 ( 3, 10) [000045] ------------ | | \--* CNS_INT(h) long 0x1c4f1e92978 static Fseq[s_1]
N011 ( 19, 33) [000026] -A-XG------- \--* ASG ushort
N005 ( 9, 16) [000025] ---XG--N---- \--* IND ushort
N003 ( 1, 1) [000040] ------------ | /--* CNS_INT long 12 field offset Fseq[F7]
N004 ( 6, 13) [000041] ----G--N---- \--* ADD byref
N002 ( 5, 12) [000022] x---G------- \--* IND ref
N001 ( 3, 10) [000042] ------------ \--* CNS_INT(h) long 0x1c4f1e92978 static Fseq[s_1]
------------ BB03 [046..047) (return), preds={BB01,BB02} succs={}
***** BB03, stmt 3
( 0, 0) [000020] ------------ * STMT void (IL 0x046...0x046)
N001 ( 0, 0) [000019] ------------ \--* RETURN void
-------------------------------------------------------------------------------------------------------------------
*************** In optEarlyProp()
*************** In fgValueNumber()
Memory Initial Value in BB01 is: $c0
The SSA definition for ByrefExposed (#2) at start of BB01 is $c0 {InitVal($80)}
The SSA definition for GcHeap (#2) at start of BB01 is $c0 {InitVal($80)}
***** BB01, stmt 1 (before)
N026 ( 47, 69) [000016] ---XG------- * JTRUE void
N024 ( 1, 1) [000014] ------------ | /--* CNS_INT int 0
N025 ( 45, 67) [000015] J--XG--N---- \--* EQ int
N021 ( 8, 15) [000009] ---XG------- | /--* IND int
N019 ( 1, 1) [000037] ------------ | | | /--* CNS_INT long 8 field offset Fseq[F8]
N020 ( 6, 13) [000038] ----G--N---- | | \--* ADD byref
N018 ( 5, 12) [000008] x---G------- | | \--* IND ref
N017 ( 3, 10) [000039] ------------ | | \--* CNS_INT(h) long 0x1c4f1e92978 static Fseq[s_1]
N022 ( 20, 31) [000010] ---XG------- | /--* NE int
N016 ( 8, 15) [000007] ---XG------- | | \--* IND int
N014 ( 1, 1) [000034] ------------ | | | /--* CNS_INT long 8 field offset Fseq[F8]
N015 ( 6, 13) [000035] ----G--N---- | | \--* ADD byref
N013 ( 5, 12) [000006] x---G------- | | \--* IND ref
N012 ( 3, 10) [000036] ------------ | | \--* CNS_INT(h) long 0x1c4f1e92978 static Fseq[s_1]
N023 ( 43, 65) [000013] ---XG------- \--* XOR int
N010 ( 9, 16) [000004] ---XG------- | /--* IND byte
N008 ( 1, 1) [000031] ------------ | | | /--* CNS_INT long 14 field offset Fseq[F0]
N009 ( 6, 13) [000032] ----G--N---- | | \--* ADD byref
N007 ( 5, 12) [000003] x---G------- | | \--* IND ref
N006 ( 3, 10) [000033] ------------ | | \--* CNS_INT(h) long 0x1c4f1e92978 static Fseq[s_1]
N011 ( 22, 33) [000005] ---XG------- \--* LT int
N005 ( 9, 16) [000002] ---XG------- \--* IND ushort
N003 ( 1, 1) [000028] ------------ | /--* CNS_INT long 12 field offset Fseq[F7]
N004 ( 6, 13) [000029] ----G--N---- \--* ADD byref
N002 ( 5, 12) [000001] x---G------- \--* IND ref
N001 ( 3, 10) [000030] ------------ \--* CNS_INT(h) long 0x1c4f1e92978 static Fseq[s_1]
N001 [000030] CNS_INT(h) 0x1c4f1e92978 static Fseq[s_1] => $100 {Hnd const: 0x000001C4F1E92978}
N002 [000001] IND => <l:$140 {ByrefExposedLoad($81, $100, $c0)}, c:$180 {180}>
N003 [000028] CNS_INT 12 field offset Fseq[F7] => $1c0 {LngCns: 12}
N004 [000029] ADD => <l:$201 {ADD($140, $1c0)}, c:$200 {ADD($180, $1c0)}>
VNApplySelectors:
VNForHandle(Fseq[F7]) is $101, fieldType is ushort
VNForMapSelect($c0, $101):ushort returns $240 {$c0[$101]}
VNForMapSelect($240, $140):ushort returns $241 {$240[$140]}
N005 [000002] IND => <l:$241 {$240[$140]}, c:$280 {280}>
N006 [000033] CNS_INT(h) 0x1c4f1e92978 static Fseq[s_1] => $100 {Hnd const: 0x000001C4F1E92978}
N007 [000003] IND => <l:$140 {ByrefExposedLoad($81, $100, $c0)}, c:$181 {181}>
N008 [000031] CNS_INT 14 field offset Fseq[F0] => $1c1 {LngCns: 14}
N009 [000032] ADD => <l:$203 {ADD($140, $1c1)}, c:$202 {ADD($181, $1c1)}>
VNApplySelectors:
VNForHandle(Fseq[F0]) is $102, fieldType is byte
VNForMapSelect($c0, $102):byte returns $2c0 {$c0[$102]}
VNForMapSelect($2c0, $140):byte returns $2c1 {$2c0[$140]}
N010 [000004] IND => <l:$2c1 {$2c0[$140]}, c:$300 {300}>
N011 [000005] LT => <l:$341 {LT($241, $2c1)}, c:$340 {LT($280, $300)}>
N012 [000036] CNS_INT(h) 0x1c4f1e92978 static Fseq[s_1] => $100 {Hnd const: 0x000001C4F1E92978}
N013 [000006] IND => <l:$140 {ByrefExposedLoad($81, $100, $c0)}, c:$182 {182}>
N014 [000034] CNS_INT 8 field offset Fseq[F8] => $1c2 {LngCns: 8}
N015 [000035] ADD => <l:$205 {ADD($140, $1c2)}, c:$204 {ADD($182, $1c2)}>
VNApplySelectors:
VNForHandle(Fseq[F8]) is $103, fieldType is int
VNForMapSelect($c0, $103):int returns $342 {$c0[$103]}
VNForMapSelect($342, $140):int returns $343 {$342[$140]}
N016 [000007] IND => <l:$343 {$342[$140]}, c:$380 {380}>
N017 [000039] CNS_INT(h) 0x1c4f1e92978 static Fseq[s_1] => $100 {Hnd const: 0x000001C4F1E92978}
N018 [000008] IND => <l:$140 {ByrefExposedLoad($81, $100, $c0)}, c:$183 {183}>
N019 [000037] CNS_INT 8 field offset Fseq[F8] => $1c2 {LngCns: 8}
N020 [000038] ADD => <l:$205 {ADD($140, $1c2)}, c:$206 {ADD($183, $1c2)}>
VNApplySelectors:
VNForHandle(Fseq[F8]) is $103, fieldType is int
VNForMapSelect($c0, $103):int returns $342 {$c0[$103]}
VNForMapSelect($342, $140):int returns $343 {$342[$140]}
N021 [000009] IND => <l:$343 {$342[$140]}, c:$381 {381}>
N022 [000010] NE => <l:$82 {IntCns 0}, c:$344 {NE($380, $381)}>
N023 [000013] XOR => <l:$341 {LT($241, $2c1)}, c:$345 {XOR($340, $344)}>
N024 [000014] CNS_INT 0 => $82 {IntCns 0}
N025 [000015] EQ => <l:$347 {EQ($341, $82)}, c:$346 {EQ($345, $82)}>
***** BB01, stmt 1 (after)
N026 ( 47, 69) [000016] ---XG------- * JTRUE void
N024 ( 1, 1) [000014] ------------ | /--* CNS_INT int 0 $82
N025 ( 45, 67) [000015] J--XG--N---- \--* EQ int <l:$347, c:$346>
N021 ( 8, 15) [000009] ---XG------- | /--* IND int <l:$343, c:$381>
N019 ( 1, 1) [000037] ------------ | | | /--* CNS_INT long 8 field offset Fseq[F8] $1c2
N020 ( 6, 13) [000038] ----G--N---- | | \--* ADD byref <l:$205, c:$206>
N018 ( 5, 12) [000008] x---G------- | | \--* IND ref <l:$140, c:$183>
N017 ( 3, 10) [000039] ------------ | | \--* CNS_INT(h) long 0x1c4f1e92978 static Fseq[s_1] $100
N022 ( 20, 31) [000010] ---XG------- | /--* NE int <l:$82, c:$344>
N016 ( 8, 15) [000007] ---XG------- | | \--* IND int <l:$343, c:$380>
N014 ( 1, 1) [000034] ------------ | | | /--* CNS_INT long 8 field offset Fseq[F8] $1c2
N015 ( 6, 13) [000035] ----G--N---- | | \--* ADD byref <l:$205, c:$204>
N013 ( 5, 12) [000006] x---G------- | | \--* IND ref <l:$140, c:$182>
N012 ( 3, 10) [000036] ------------ | | \--* CNS_INT(h) long 0x1c4f1e92978 static Fseq[s_1] $100
N023 ( 43, 65) [000013] ---XG------- \--* XOR int <l:$341, c:$345>
N010 ( 9, 16) [000004] ---XG------- | /--* IND byte <l:$2c1, c:$300>
N008 ( 1, 1) [000031] ------------ | | | /--* CNS_INT long 14 field offset Fseq[F0] $1c1
N009 ( 6, 13) [000032] ----G--N---- | | \--* ADD byref <l:$203, c:$202>
N007 ( 5, 12) [000003] x---G------- | | \--* IND ref <l:$140, c:$181>
N006 ( 3, 10) [000033] ------------ | | \--* CNS_INT(h) long 0x1c4f1e92978 static Fseq[s_1] $100
N011 ( 22, 33) [000005] ---XG------- \--* LT int <l:$341, c:$340>
N005 ( 9, 16) [000002] ---XG------- \--* IND ushort <l:$241, c:$280>
N003 ( 1, 1) [000028] ------------ | /--* CNS_INT long 12 field offset Fseq[F7] $1c0
N004 ( 6, 13) [000029] ----G--N---- \--* ADD byref <l:$201, c:$200>
N002 ( 5, 12) [000001] x---G------- \--* IND ref <l:$140, c:$180>
N001 ( 3, 10) [000030] ------------ \--* CNS_INT(h) long 0x1c4f1e92978 static Fseq[s_1] $100
finish(BB01).
Succ(BB02).
Not yet completed.
All preds complete, adding to allDone.
Succ(BB03).
Not yet completed.
Not all preds complete Adding to notallDone, if necessary...
Was necessary.
The SSA definition for ByrefExposed (#2) at start of BB02 is $c0 {InitVal($80)}
The SSA definition for GcHeap (#2) at start of BB02 is $c0 {InitVal($80)}
***** BB02, stmt 2 (before)
N010 ( 9, 16) [000024] ---XG------- /--* IND ushort
N008 ( 1, 1) [000043] ------------ | | /--* CNS_INT long 12 field offset Fseq[F7]
N009 ( 6, 13) [000044] ----G--N---- | \--* ADD byref
N007 ( 5, 12) [000023] x---G------- | \--* IND ref
N006 ( 3, 10) [000045] ------------ | \--* CNS_INT(h) long 0x1c4f1e92978 static Fseq[s_1]
N011 ( 19, 33) [000026] -A-XG------- * ASG ushort
N005 ( 9, 16) [000025] ---XG--N---- \--* IND ushort
N003 ( 1, 1) [000040] ------------ | /--* CNS_INT long 12 field offset Fseq[F7]
N004 ( 6, 13) [000041] ----G--N---- \--* ADD byref
N002 ( 5, 12) [000022] x---G------- \--* IND ref
N001 ( 3, 10) [000042] ------------ \--* CNS_INT(h) long 0x1c4f1e92978 static Fseq[s_1]
N001 [000042] CNS_INT(h) 0x1c4f1e92978 static Fseq[s_1] => $100 {Hnd const: 0x000001C4F1E92978}
N002 [000022] IND => <l:$140 {ByrefExposedLoad($81, $100, $c0)}, c:$184 {184}>
N003 [000040] CNS_INT 12 field offset Fseq[F7] => $1c0 {LngCns: 12}
N004 [000041] ADD => <l:$201 {ADD($140, $1c0)}, c:$207 {ADD($184, $1c0)}>
N006 [000045] CNS_INT(h) 0x1c4f1e92978 static Fseq[s_1] => $100 {Hnd const: 0x000001C4F1E92978}
N007 [000023] IND => <l:$140 {ByrefExposedLoad($81, $100, $c0)}, c:$185 {185}>
N008 [000043] CNS_INT 12 field offset Fseq[F7] => $1c0 {LngCns: 12}
N009 [000044] ADD => <l:$201 {ADD($140, $1c0)}, c:$208 {ADD($185, $1c0)}>
VNApplySelectors:
VNForHandle(Fseq[F7]) is $101, fieldType is ushort
VNForMapSelect($c0, $101):ushort returns $240 {$c0[$101]}
VNForMapSelect($240, $140):ushort returns $241 {$240[$140]}
N010 [000024] IND => <l:$241 {$240[$140]}, c:$281 {281}>
VNApplySelectors:
VNForHandle(Fseq[F7]) is $101, fieldType is ushort
VNForMapSelect($c0, $101):ushort returns $240 {$c0[$101]}
VNForMapSelect($240, $140):ushort returns $241 {$240[$140]}
VNForMapStore($240, $140, $241):ushort returns $3c0 {$240[$140 := $241]}
fgCurMemoryVN assigned:
fieldHnd $101 is {Hnd const: 0x00007FFDF9AD5500}
fieldSeq $400 is {F7}
VNForMapStore($c0, $101, $3c0):ushort returns $3c1 {$c0[$101 := $3c0]}
fgCurMemoryVN[GcHeap] assigned by StoreField at [000026] to VN: $3c1.
N011 [000026] ASG => $VN.Void
***** BB02, stmt 2 (after)
N010 ( 9, 16) [000024] ---XG------- /--* IND ushort <l:$241, c:$281>
N008 ( 1, 1) [000043] ------------ | | /--* CNS_INT long 12 field offset Fseq[F7] $1c0
N009 ( 6, 13) [000044] ----G--N---- | \--* ADD byref <l:$201, c:$208>
N007 ( 5, 12) [000023] x---G------- | \--* IND ref <l:$140, c:$185>
N006 ( 3, 10) [000045] ------------ | \--* CNS_INT(h) long 0x1c4f1e92978 static Fseq[s_1] $100
N011 ( 19, 33) [000026] -A-XG------- * ASG ushort $VN.Void
N005 ( 9, 16) [000025] ---XG--N---- \--* IND ushort $241
N003 ( 1, 1) [000040] ------------ | /--* CNS_INT long 12 field offset Fseq[F7] $1c0
N004 ( 6, 13) [000041] ----G--N---- \--* ADD byref <l:$201, c:$207>
N002 ( 5, 12) [000022] x---G------- \--* IND ref <l:$140, c:$184>
N001 ( 3, 10) [000042] ------------ \--* CNS_INT(h) long 0x1c4f1e92978 static Fseq[s_1] $100
finish(BB02).
Succ(BB03).
Not yet completed.
All preds complete, adding to allDone.
The SSA definition for ByrefExposed (#2) at start of BB03 is $c0 {InitVal($80)}
The SSA definition for GcHeap (#2) at start of BB03 is $c0 {InitVal($80)}
***** BB03, stmt 3 (before)
N001 ( 0, 0) [000019] ------------ * RETURN void
N001 [000019] RETURN => $440 {440}
***** BB03, stmt 3 (after)
N001 ( 0, 0) [000019] ------------ * RETURN void $440
finish(BB03).
*************** In optVnCopyProp()
*************** In SsaBuilder::ComputeDominators(Compiler*, ...)
Copy Assertion for BB01
curSsaName stack: { }
Copy Assertion for BB03
curSsaName stack: { }
Copy Assertion for BB02
curSsaName stack: { }
*************** In optOptimizeCSEs()
Blocks/Trees at start of optOptimizeCSE phase
--------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
--------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..032)-> BB03 ( cond ) i label target
BB02 [0001] 1 BB01 0.50 [032..046) i
BB03 [0002] 2 BB01,BB02 1 [046..047) (return) i label target
--------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [000..032) -> BB03 (cond), preds={} succs={BB02,BB03}
***** BB01, stmt 1
( 47, 69) [000017] ------------ * STMT void (IL 0x000...0x030)
N026 ( 47, 69) [000016] ---XG------- \--* JTRUE void
N024 ( 1, 1) [000014] ------------ | /--* CNS_INT int 0 $82
N025 ( 45, 67) [000015] J--XG--N---- \--* EQ int <l:$347, c:$346>
N021 ( 8, 15) [000009] ---XG------- | /--* IND int <l:$343, c:$381>
N019 ( 1, 1) [000037] ------------ | | | /--* CNS_INT long 8 field offset Fseq[F8] $1c2
N020 ( 6, 13) [000038] ----G--N---- | | \--* ADD byref <l:$205, c:$206>
N018 ( 5, 12) [000008] x---G------- | | \--* IND ref <l:$140, c:$183>
N017 ( 3, 10) [000039] ------------ | | \--* CNS_INT(h) long 0x1c4f1e92978 static Fseq[s_1] $100
N022 ( 20, 31) [000010] ---XG------- | /--* NE int <l:$82, c:$344>
N016 ( 8, 15) [000007] ---XG------- | | \--* IND int <l:$343, c:$380>
N014 ( 1, 1) [000034] ------------ | | | /--* CNS_INT long 8 field offset Fseq[F8] $1c2
N015 ( 6, 13) [000035] ----G--N---- | | \--* ADD byref <l:$205, c:$204>
N013 ( 5, 12) [000006] x---G------- | | \--* IND ref <l:$140, c:$182>
N012 ( 3, 10) [000036] ------------ | | \--* CNS_INT(h) long 0x1c4f1e92978 static Fseq[s_1] $100
N023 ( 43, 65) [000013] ---XG------- \--* XOR int <l:$341, c:$345>
N010 ( 9, 16) [000004] ---XG------- | /--* IND byte <l:$2c1, c:$300>
N008 ( 1, 1) [000031] ------------ | | | /--* CNS_INT long 14 field offset Fseq[F0] $1c1
N009 ( 6, 13) [000032] ----G--N---- | | \--* ADD byref <l:$203, c:$202>
N007 ( 5, 12) [000003] x---G------- | | \--* IND ref <l:$140, c:$181>
N006 ( 3, 10) [000033] ------------ | | \--* CNS_INT(h) long 0x1c4f1e92978 static Fseq[s_1] $100
N011 ( 22, 33) [000005] ---XG------- \--* LT int <l:$341, c:$340>
N005 ( 9, 16) [000002] ---XG------- \--* IND ushort <l:$241, c:$280>
N003 ( 1, 1) [000028] ------------ | /--* CNS_INT long 12 field offset Fseq[F7] $1c0
N004 ( 6, 13) [000029] ----G--N---- \--* ADD byref <l:$201, c:$200>
N002 ( 5, 12) [000001] x---G------- \--* IND ref <l:$140, c:$180>
N001 ( 3, 10) [000030] ------------ \--* CNS_INT(h) long 0x1c4f1e92978 static Fseq[s_1] $100
------------ BB02 [032..046), preds={BB01} succs={BB03}
***** BB02, stmt 2
( 19, 33) [000027] ------------ * STMT void (IL 0x032...0x041)
N010 ( 9, 16) [000024] ---XG------- | /--* IND ushort <l:$241, c:$281>
N008 ( 1, 1) [000043] ------------ | | | /--* CNS_INT long 12 field offset Fseq[F7] $1c0
N009 ( 6, 13) [000044] ----G--N---- | | \--* ADD byref <l:$201, c:$208>
N007 ( 5, 12) [000023] x---G------- | | \--* IND ref <l:$140, c:$185>
N006 ( 3, 10) [000045] ------------ | | \--* CNS_INT(h) long 0x1c4f1e92978 static Fseq[s_1] $100
N011 ( 19, 33) [000026] -A-XG------- \--* ASG ushort $VN.Void
N005 ( 9, 16) [000025] ---XG--N---- \--* IND ushort $241
N003 ( 1, 1) [000040] ------------ | /--* CNS_INT long 12 field offset Fseq[F7] $1c0
N004 ( 6, 13) [000041] ----G--N---- \--* ADD byref <l:$201, c:$207>
N002 ( 5, 12) [000022] x---G------- \--* IND ref <l:$140, c:$184>
N001 ( 3, 10) [000042] ------------ \--* CNS_INT(h) long 0x1c4f1e92978 static Fseq[s_1] $100
------------ BB03 [046..047) (return), preds={BB01,BB02} succs={}
***** BB03, stmt 3
( 0, 0) [000020] ------------ * STMT void (IL 0x046...0x046)
N001 ( 0, 0) [000019] ------------ \--* RETURN void $440
-------------------------------------------------------------------------------------------------------------------
*************** In optOptimizeValnumCSEs()
CSE candidate #01, vn=$140 cseMask=0000000000000001 in BB01, [cost= 5, size=12]:
N007 ( 5, 12) CSE #01 (use)[000003] x---G------- * IND ref <l:$140, c:$181>
N006 ( 3, 10) [000033] ------------ \--* CNS_INT(h) long 0x1c4f1e92978 static Fseq[s_1] $100
CSE candidate #02, vn=$343 cseMask=0000000000000002 in BB01, [cost= 8, size=15]:
N021 ( 8, 15) CSE #02 (use)[000009] ---XG------- * IND int <l:$343, c:$381>
N019 ( 1, 1) [000037] ------------ | /--* CNS_INT long 8 field offset Fseq[F8] $1c2
N020 ( 6, 13) [000038] ----G--N---- \--* ADD byref <l:$205, c:$206>
N018 ( 5, 12) CSE #01 (use)[000008] x---G------- \--* IND ref <l:$140, c:$183>
N017 ( 3, 10) [000039] ------------ \--* CNS_INT(h) long 0x1c4f1e92978 static Fseq[s_1] $100
CSE candidate #03, vn=$341 cseMask=0000000000000004 in BB01, [cost=43, size=65]:
N021 ( 8, 15) CSE #02 (use)[000009] ---XG------- /--* IND int <l:$343, c:$381>
N019 ( 1, 1) [000037] ------------ | | /--* CNS_INT long 8 field offset Fseq[F8] $1c2
N020 ( 6, 13) [000038] ----G--N---- | \--* ADD byref <l:$205, c:$206>
N018 ( 5, 12) CSE #01 (use)[000008] x---G------- | \--* IND ref <l:$140, c:$183>
N017 ( 3, 10) [000039] ------------ | \--* CNS_INT(h) long 0x1c4f1e92978 static Fseq[s_1] $100
N022 ( 20, 31) [000010] ---XG------- /--* NE int <l:$82, c:$344>
N016 ( 8, 15) CSE #02 (use)[000007] ---XG------- | \--* IND int <l:$343, c:$380>
N014 ( 1, 1) [000034] ------------ | | /--* CNS_INT long 8 field offset Fseq[F8] $1c2
N015 ( 6, 13) [000035] ----G--N---- | \--* ADD byref <l:$205, c:$204>
N013 ( 5, 12) CSE #01 (use)[000006] x---G------- | \--* IND ref <l:$140, c:$182>
N012 ( 3, 10) [000036] ------------ | \--* CNS_INT(h) long 0x1c4f1e92978 static Fseq[s_1] $100
N023 ( 43, 65) CSE #03 (use)[000013] ---XG------- * XOR int <l:$341, c:$345>
N010 ( 9, 16) [000004] ---XG------- | /--* IND byte <l:$2c1, c:$300>
N008 ( 1, 1) [000031] ------------ | | | /--* CNS_INT long 14 field offset Fseq[F0] $1c1
N009 ( 6, 13) [000032] ----G--N---- | | \--* ADD byref <l:$203, c:$202>
N007 ( 5, 12) CSE #01 (use)[000003] x---G------- | | \--* IND ref <l:$140, c:$181>
N006 ( 3, 10) [000033] ------------ | | \--* CNS_INT(h) long 0x1c4f1e92978 static Fseq[s_1] $100
N011 ( 22, 33) CSE #03 (use)[000005] ---XG------- \--* LT int <l:$341, c:$340>
N005 ( 9, 16) [000002] ---XG------- \--* IND ushort <l:$241, c:$280>
N003 ( 1, 1) [000028] ------------ | /--* CNS_INT long 12 field offset Fseq[F7] $1c0
N004 ( 6, 13) [000029] ----G--N---- \--* ADD byref <l:$201, c:$200>
N002 ( 5, 12) CSE #01 (use)[000001] x---G------- \--* IND ref <l:$140, c:$180>
N001 ( 3, 10) [000030] ------------ \--* CNS_INT(h) long 0x1c4f1e92978 static Fseq[s_1] $100
CSE candidate #04, vn=$241 cseMask=0000000000000008 in BB02, [cost= 9, size=16]:
N010 ( 9, 16) CSE #04 (use)[000024] ---XG------- * IND ushort <l:$241, c:$281>
N008 ( 1, 1) [000043] ------------ | /--* CNS_INT long 12 field offset Fseq[F7] $1c0
N009 ( 6, 13) [000044] ----G--N---- \--* ADD byref <l:$201, c:$208>
N007 ( 5, 12) CSE #01 (use)[000023] x---G------- \--* IND ref <l:$140, c:$185>
N006 ( 3, 10) [000045] ------------ \--* CNS_INT(h) long 0x1c4f1e92978 static Fseq[s_1] $100
Blocks that generate CSE def/uses
BB01 cseGen = 000000000000000F
BB02 cseGen = 0000000000000009
After performing DataFlow for ValnumCSE's
BB01 cseIn = 0000000000000000 cseOut = 000000000000000F
BB02 cseIn = 000000000000000F cseOut = 000000000000000F
BB03 cseIn = 000000000000000F cseOut = 000000000000000F
Labeling the CSEs with Use/Def information
BB01 [000001] Def of CSE #01 [weight=1 ]
BB01 [000002] Def of CSE #04 [weight=1 ]
BB01 [000003] Use of CSE #01 [weight=1 ]
BB01 [000005] Def of CSE #03 [weight=1 ]
BB01 [000006] Use of CSE #01 [weight=1 ]
BB01 [000007] Def of CSE #02 [weight=1 ]
BB01 [000008] Use of CSE #01 [weight=1 ]
BB01 [000009] Use of CSE #02 [weight=1 ]
BB01 [000013] Use of CSE #03 [weight=1 ]
BB02 [000022] Use of CSE #01 [weight=0.50]
BB02 [000023] Use of CSE #01 [weight=0.50]
BB02 [000024] Use of CSE #04 [weight=0.50]
************ Trees at start of optValnumCSE_Heuristic()
------------ BB01 [000..032) -> BB03 (cond), preds={} succs={BB02,BB03}
***** BB01, stmt 1
( 47, 69) [000017] ------------ * STMT void (IL 0x000...0x030)
N026 ( 47, 69) [000016] ---XG------- \--* JTRUE void
N024 ( 1, 1) [000014] ------------ | /--* CNS_INT int 0 $82
N025 ( 45, 67) [000015] J--XG--N---- \--* EQ int <l:$347, c:$346>
N021 ( 8, 15) CSE #02 (use)[000009] ---XG------- | /--* IND int <l:$343, c:$381>
N019 ( 1, 1) [000037] ------------ | | | /--* CNS_INT long 8 field offset Fseq[F8] $1c2
N020 ( 6, 13) [000038] ----G--N---- | | \--* ADD byref <l:$205, c:$206>
N018 ( 5, 12) CSE #01 (use)[000008] x---G------- | | \--* IND ref <l:$140, c:$183>
N017 ( 3, 10) [000039] ------------ | | \--* CNS_INT(h) long 0x1c4f1e92978 static Fseq[s_1] $100
N022 ( 20, 31) [000010] ---XG------- | /--* NE int <l:$82, c:$344>
N016 ( 8, 15) CSE #02 (def)[000007] ---XG------- | | \--* IND int <l:$343, c:$380>
N014 ( 1, 1) [000034] ------------ | | | /--* CNS_INT long 8 field offset Fseq[F8] $1c2
N015 ( 6, 13) [000035] ----G--N---- | | \--* ADD byref <l:$205, c:$204>
N013 ( 5, 12) CSE #01 (use)[000006] x---G------- | | \--* IND ref <l:$140, c:$182>
N012 ( 3, 10) [000036] ------------ | | \--* CNS_INT(h) long 0x1c4f1e92978 static Fseq[s_1] $100
N023 ( 43, 65) CSE #03 (use)[000013] ---XG------- \--* XOR int <l:$341, c:$345>
N010 ( 9, 16) [000004] ---XG------- | /--* IND byte <l:$2c1, c:$300>
N008 ( 1, 1) [000031] ------------ | | | /--* CNS_INT long 14 field offset Fseq[F0] $1c1
N009 ( 6, 13) [000032] ----G--N---- | | \--* ADD byref <l:$203, c:$202>
N007 ( 5, 12) CSE #01 (use)[000003] x---G------- | | \--* IND ref <l:$140, c:$181>
N006 ( 3, 10) [000033] ------------ | | \--* CNS_INT(h) long 0x1c4f1e92978 static Fseq[s_1] $100
N011 ( 22, 33) CSE #03 (def)[000005] ---XG------- \--* LT int <l:$341, c:$340>
N005 ( 9, 16) CSE #04 (def)[000002] ---XG------- \--* IND ushort <l:$241, c:$280>
N003 ( 1, 1) [000028] ------------ | /--* CNS_INT long 12 field offset Fseq[F7] $1c0
N004 ( 6, 13) [000029] ----G--N---- \--* ADD byref <l:$201, c:$200>
N002 ( 5, 12) CSE #01 (def)[000001] x---G------- \--* IND ref <l:$140, c:$180>
N001 ( 3, 10) [000030] ------------ \--* CNS_INT(h) long 0x1c4f1e92978 static Fseq[s_1] $100
------------ BB02 [032..046), preds={BB01} succs={BB03}
***** BB02, stmt 2
( 19, 33) [000027] ------------ * STMT void (IL 0x032...0x041)
N010 ( 9, 16) CSE #04 (use)[000024] ---XG------- | /--* IND ushort <l:$241, c:$281>
N008 ( 1, 1) [000043] ------------ | | | /--* CNS_INT long 12 field offset Fseq[F7] $1c0
N009 ( 6, 13) [000044] ----G--N---- | | \--* ADD byref <l:$201, c:$208>
N007 ( 5, 12) CSE #01 (use)[000023] x---G------- | | \--* IND ref <l:$140, c:$185>
N006 ( 3, 10) [000045] ------------ | | \--* CNS_INT(h) long 0x1c4f1e92978 static Fseq[s_1] $100
N011 ( 19, 33) [000026] -A-XG------- \--* ASG ushort $VN.Void
N005 ( 9, 16) [000025] ---XG--N---- \--* IND ushort $241
N003 ( 1, 1) [000040] ------------ | /--* CNS_INT long 12 field offset Fseq[F7] $1c0
N004 ( 6, 13) [000041] ----G--N---- \--* ADD byref <l:$201, c:$207>
N002 ( 5, 12) CSE #01 (use)[000022] x---G------- \--* IND ref <l:$140, c:$184>
N001 ( 3, 10) [000042] ------------ \--* CNS_INT(h) long 0x1c4f1e92978 static Fseq[s_1] $100
------------ BB03 [046..047) (return), preds={BB01,BB02} succs={}
***** BB03, stmt 3
( 0, 0) [000020] ------------ * STMT void (IL 0x046...0x046)
N001 ( 0, 0) [000019] ------------ \--* RETURN void $440
-------------------------------------------------------------------------------------------------------------------
Aggressive CSE Promotion cutoff is 100
Moderate CSE Promotion cutoff is 50
Framesize estimate is 0x0000
We have a small frame
Sorted CSE candidates:
CSE #03,cseMask=0000000000000004,useCnt=1: [def=100, use=100] :: N011 ( 22, 33) CSE #03 (def)[000005] ---XG------- * LT int <l:$341, c:$340>
CSE #04,cseMask=0000000000000008,useCnt=1: [def=100, use= 50] :: N005 ( 9, 16) CSE #04 (def)[000002] ---XG------- * IND ushort <l:$241, c:$280>
CSE #02,cseMask=0000000000000002,useCnt=1: [def=100, use=100] :: N016 ( 8, 15) CSE #02 (def)[000007] ---XG------- * IND int <l:$343, c:$380>
CSE #01,cseMask=0000000000000001,useCnt=5: [def=100, use=400] :: N002 ( 5, 12) CSE #01 (def)[000001] x---G------- * IND ref <l:$140, c:$180>
Considering CSE #03 [def=100, use=100, cost=22] CSE Expression:
N010 ( 9, 16) [000004] ---XG------- /--* IND byte <l:$2c1, c:$300>
N008 ( 1, 1) [000031] ------------ | | /--* CNS_INT long 14 field offset Fseq[F0] $1c1
N009 ( 6, 13) [000032] ----G--N---- | \--* ADD byref <l:$203, c:$202>
N007 ( 5, 12) CSE #01 (use)[000003] x---G------- | \--* IND ref <l:$140, c:$181>
N006 ( 3, 10) [000033] ------------ | \--* CNS_INT(h) long 0x1c4f1e92978 static Fseq[s_1] $100
N011 ( 22, 33) CSE #03 (def)[000005] ---XG------- * LT int <l:$341, c:$340>
N005 ( 9, 16) CSE #04 (def)[000002] ---XG------- \--* IND ushort <l:$241, c:$280>
N003 ( 1, 1) [000028] ------------ | /--* CNS_INT long 12 field offset Fseq[F7] $1c0
N004 ( 6, 13) [000029] ----G--N---- \--* ADD byref <l:$201, c:$200>
N002 ( 5, 12) CSE #01 (def)[000001] x---G------- \--* IND ref <l:$140, c:$180>
N001 ( 3, 10) [000030] ------------ \--* CNS_INT(h) long 0x1c4f1e92978 static Fseq[s_1] $100
Aggressive CSE Promotion (300 >= 100)
cseRefCnt=300, aggressiveRefCnt=100, moderateRefCnt=50
defCnt=100, useCnt=100, cost=22, size=33
def_cost=1, use_cost=1, extra_no_cost=64, extra_yes_cost=0
CSE cost savings check (2264 >= 200) passes
Promoting CSE:
lvaGrabTemp returning 1 (V01 rat0) (a long lifetime temp) called for ValNumCSE.
CSE #03 def at [000005] replaced in BB01 with def of V01
New refCnts for V01: refCnt = 1, refCntWtd = 1
New refCnts for V01: refCnt = 2, refCntWtd = 2
New refCnts for V01: refCnt = 3, refCntWtd = 3
New refCnts for V01: refCnt = 4, refCntWtd = 4
optValnumCSE morphed tree:
N030 ( 48, 70) [000016] -A-XG------- * JTRUE void
N028 ( 1, 1) [000014] ------------ | /--* CNS_INT int 0 $82
N029 ( 46, 68) [000015] JA-XG--N---- \--* EQ int <l:$347, c:$346>
N025 ( 8, 15) CSE #02 (use)[000009] ---XG------- | /--* IND int <l:$343, c:$381>
N023 ( 1, 1) [000037] ------------ | | | /--* CNS_INT long 8 field offset Fseq[F8] $1c2
N024 ( 6, 13) [000038] ----G--N---- | | \--* ADD byref <l:$205, c:$206>
N022 ( 5, 12) CSE #01 (use)[000008] x---G------- | | \--* IND ref <l:$140, c:$183>
N021 ( 3, 10) [000039] ------------ | | \--* CNS_INT(h) long 0x1c4f1e92978 static Fseq[s_1] $100
N026 ( 20, 31) [000010] ---XG------- | /--* NE int <l:$82, c:$344>
N020 ( 8, 15) CSE #02 (def)[000007] ---XG------- | | \--* IND int <l:$343, c:$380>
N018 ( 1, 1) [000034] ------------ | | | /--* CNS_INT long 8 field offset Fseq[F8] $1c2
N019 ( 6, 13) [000035] ----G--N---- | | \--* ADD byref <l:$205, c:$204>
N017 ( 5, 12) CSE #01 (use)[000006] x---G------- | | \--* IND ref <l:$140, c:$182>
N016 ( 3, 10) [000036] ------------ | | \--* CNS_INT(h) long 0x1c4f1e92978 static Fseq[s_1] $100
N027 ( 44, 66) CSE #03 (use)[000013] -A-XG------- \--* XOR int <l:$341, c:$345>
N014 ( 1, 1) [000048] ------------ | /--* LCL_VAR int V01 cse0 <l:$341, c:$340>
N015 ( 23, 34) [000049] -A-XG------- \--* COMMA int <l:$341, c:$340>
N010 ( 9, 16) [000004] ---XG------- | /--* IND byte <l:$2c1, c:$300>
N008 ( 1, 1) [000031] ------------ | | | /--* CNS_INT long 14 field offset Fseq[F0] $1c1
N009 ( 6, 13) [000032] ----G--N---- | | \--* ADD byref <l:$203, c:$202>
N007 ( 5, 12) CSE #01 (use)[000003] x---G------- | | \--* IND ref <l:$140, c:$181>
N006 ( 3, 10) [000033] ------------ | | \--* CNS_INT(h) long 0x1c4f1e92978 static Fseq[s_1] $100
N011 ( 22, 33) [000005] ---XG------- | /--* LT int <l:$341, c:$340>
N005 ( 9, 16) CSE #04 (def)[000002] ---XG------- | | \--* IND ushort <l:$241, c:$280>
N003 ( 1, 1) [000028] ------------ | | | /--* CNS_INT long 12 field offset Fseq[F7] $1c0
N004 ( 6, 13) [000029] ----G--N---- | | \--* ADD byref <l:$201, c:$200>
N002 ( 5, 12) CSE #01 (def)[000001] x---G------- | | \--* IND ref <l:$140, c:$180>
N001 ( 3, 10) [000030] ------------ | | \--* CNS_INT(h) long 0x1c4f1e92978 static Fseq[s_1] $100
N013 ( 22, 33) [000047] -A-XG---R--- \--* ASG int $VN.Void
N012 ( 1, 1) [000046] D------N---- \--* LCL_VAR int V01 cse0 <l:$341, c:$340>
Working on the replacement of the CSE #03 use at [000013] in BB01
This CSE use has persistent side effects. Extracted side effects...
N010 ( 9, 16) [000004] ---XG------- /--* IND byte <l:$2c1, c:$300>
N008 ( 1, 1) [000031] ------------ | | /--* CNS_INT long 14 field offset Fseq[F0] $1c1
N009 ( 6, 13) [000032] ----G--N---- | \--* ADD byref <l:$203, c:$202>
N007 ( 5, 12) CSE #01 (use)[000003] x---G------- | \--* IND ref <l:$140, c:$181>
N006 ( 3, 10) [000033] ------------ | \--* CNS_INT(h) long 0x1c4f1e92978 static Fseq[s_1] $100
N011 ( 22, 33) [000005] ---XG------- /--* LT int <l:$341, c:$340>
N005 ( 9, 16) CSE #04 (def)[000002] ---XG------- | \--* IND ushort <l:$241, c:$280>
N003 ( 1, 1) [000028] ------------ | | /--* CNS_INT long 12 field offset Fseq[F7] $1c0
N004 ( 6, 13) [000029] ----G--N---- | \--* ADD byref <l:$201, c:$200>
N002 ( 5, 12) CSE #01 (def)[000001] x---G------- | \--* IND ref <l:$140, c:$180>
N001 ( 3, 10) [000030] ------------ | \--* CNS_INT(h) long 0x1c4f1e92978 static Fseq[s_1] $100
N013 ( 22, 33) [000047] -A-XG---R--- * ASG int $VN.Void
N012 ( 1, 1) [000046] D------N---- \--* LCL_VAR int V01 cse0 <l:$341, c:$340>
New refCnts for V01: refCnt = 3, refCntWtd = 3
Preserving the CSE def #02 at [000007] because it is nested inside a CSE use
Unmark CSE use #02 at [000009]: 1 -> 0
Unmark CSE use #01 at [000008]: 5 -> 4
CSE #00 use at [000013] replaced in BB01 with temp use.
This CSE use has side effects and/or nested CSE defs. The sideEffectList:
N010 ( 9, 16) [000004] ---XG------- /--* IND byte <l:$2c1, c:$300>
N008 ( 1, 1) [000031] ------------ | | /--* CNS_INT long 14 field offset Fseq[F0] $1c1
N009 ( 6, 13) [000032] ----G--N---- | \--* ADD byref <l:$203, c:$202>
N007 ( 5, 12) CSE #01 (use)[000003] x---G------- | \--* IND ref <l:$140, c:$181>
N006 ( 3, 10) [000033] ------------ | \--* CNS_INT(h) long 0x1c4f1e92978 static Fseq[s_1] $100
N011 ( 22, 33) [000005] ---XG------- /--* LT int <l:$341, c:$340>
N005 ( 9, 16) CSE #04 (def)[000002] ---XG------- | \--* IND ushort <l:$241, c:$280>
N003 ( 1, 1) [000028] ------------ | | /--* CNS_INT long 12 field offset Fseq[F7] $1c0
N004 ( 6, 13) [000029] ----G--N---- | \--* ADD byref <l:$201, c:$200>
N002 ( 5, 12) CSE #01 (def)[000001] x---G------- | \--* IND ref <l:$140, c:$180>
N001 ( 3, 10) [000030] ------------ | \--* CNS_INT(h) long 0x1c4f1e92978 static Fseq[s_1] $100
N013 ( 22, 33) [000047] -A-XG---R--- /--* ASG int $VN.Void
N012 ( 1, 1) [000046] D------N---- | \--* LCL_VAR int V01 cse0 <l:$341, c:$340>
[000051] -A-XG------- * COMMA void $VN.Void
N020 ( 8, 15) CSE #02 (def)[000007] ---XG------- \--* IND int <l:$343, c:$380>
N018 ( 1, 1) [000034] ------------ | /--* CNS_INT long 8 field offset Fseq[F8] $1c2
N019 ( 6, 13) [000035] ----G--N---- \--* ADD byref <l:$205, c:$204>
N017 ( 5, 12) CSE #01 (use)[000006] x---G------- \--* IND ref <l:$140, c:$182>
N016 ( 3, 10) [000036] ------------ \--* CNS_INT(h) long 0x1c4f1e92978 static Fseq[s_1] $100
New refCnts for V01: refCnt = 4, refCntWtd = 4
New refCnts for V01: refCnt = 5, refCntWtd = 5
New refCnts for V01: refCnt = 6, refCntWtd = 6
optValnumCSE morphed tree:
N024 ( 35, 53) [000016] -A-XG------- * JTRUE void
N022 ( 1, 1) [000014] ------------ | /--* CNS_INT int 0 $82
N023 ( 33, 51) [000015] JA-XG--N---- \--* EQ int <l:$347, c:$346>
N020 ( 1, 1) [000050] ------------ | /--* LCL_VAR int V01 cse0 <l:$341, c:$340>
N021 ( 31, 49) [000052] -A-XG------- \--* COMMA int <l:$341, c:$340>
N015 ( 9, 16) [000004] ---XG------- | /--* IND byte <l:$2c1, c:$300>
N013 ( 1, 1) [000031] ------------ | | | /--* CNS_INT long 14 field offset Fseq[F0] $1c1
N014 ( 6, 13) [000032] ----G--N---- | | \--* ADD byref <l:$203, c:$202>
N012 ( 5, 12) CSE #01 (use)[000003] x---G------- | | \--* IND ref <l:$140, c:$181>
N011 ( 3, 10) [000033] ------------ | | \--* CNS_INT(h) long 0x1c4f1e92978 static Fseq[s_1] $100
N016 ( 22, 33) [000005] ---XG------- | /--* LT int <l:$341, c:$340>
N010 ( 9, 16) CSE #04 (def)[000002] ---XG------- | | \--* IND ushort <l:$241, c:$280>
N008 ( 1, 1) [000028] ------------ | | | /--* CNS_INT long 12 field offset Fseq[F7] $1c0
N009 ( 6, 13) [000029] ----G--N---- | | \--* ADD byref <l:$201, c:$200>
N007 ( 5, 12) CSE #01 (def)[000001] x---G------- | | \--* IND ref <l:$140, c:$180>
N006 ( 3, 10) [000030] ------------ | | \--* CNS_INT(h) long 0x1c4f1e92978 static Fseq[s_1] $100
N018 ( 22, 33) [000047] -A-XG---R--- | /--* ASG int $VN.Void
N017 ( 1, 1) [000046] D------N---- | | \--* LCL_VAR int V01 cse0 <l:$341, c:$340>
N019 ( 30, 48) [000051] -A-XG------- \--* COMMA void $VN.Void
N005 ( 8, 15) CSE #02 (def)[000007] ---XG------- \--* IND int <l:$343, c:$380>
N003 ( 1, 1) [000034] ------------ | /--* CNS_INT long 8 field offset Fseq[F8] $1c2
N004 ( 6, 13) [000035] ----G--N---- \--* ADD byref <l:$205, c:$204>
N002 ( 5, 12) CSE #01 (use)[000006] x---G------- \--* IND ref <l:$140, c:$182>
N001 ( 3, 10) [000036] ------------ \--* CNS_INT(h) long 0x1c4f1e92978 static Fseq[s_1] $100
Considering CSE #04 [def=100, use=50, cost= 9] CSE Expression:
N010 ( 9, 16) CSE #04 (def)[000002] ---XG------- * IND ushort <l:$241, c:$280>
N008 ( 1, 1) [000028] ------------ | /--* CNS_INT long 12 field offset Fseq[F7] $1c0
N009 ( 6, 13) [000029] ----G--N---- \--* ADD byref <l:$201, c:$200>
N007 ( 5, 12) CSE #01 (def)[000001] x---G------- \--* IND ref <l:$140, c:$180>
N006 ( 3, 10) [000030] ------------ \--* CNS_INT(h) long 0x1c4f1e92978 static Fseq[s_1] $100
Aggressive CSE Promotion (250 >= 100)
cseRefCnt=250, aggressiveRefCnt=100, moderateRefCnt=50
defCnt=100, useCnt=50, cost=9, size=16
def_cost=1, use_cost=1, extra_no_cost=30, extra_yes_cost=0
CSE cost savings check (480 >= 150) passes
Promoting CSE:
lvaGrabTemp returning 2 (V02 rat0) (a long lifetime temp) called for ValNumCSE.
CSE #04 def at [000002] replaced in BB01 with def of V02
New refCnts for V02: refCnt = 1, refCntWtd = 1
New refCnts for V02: refCnt = 2, refCntWtd = 2
New refCnts for V01: refCnt = 7, refCntWtd = 7
New refCnts for V02: refCnt = 3, refCntWtd = 3
New refCnts for V02: refCnt = 4, refCntWtd = 4
New refCnts for V01: refCnt = 8, refCntWtd = 8
optValnumCSE morphed tree:
N028 ( 36, 54) [000016] -A-XG------- * JTRUE void
N026 ( 1, 1) [000014] ------------ | /--* CNS_INT int 0 $82
N027 ( 34, 52) [000015] JA-XG--N---- \--* EQ int <l:$347, c:$346>
N024 ( 1, 1) [000050] ------------ | /--* LCL_VAR int V01 cse0 <l:$341, c:$340>
N025 ( 32, 50) [000052] -A-XG------- \--* COMMA int <l:$341, c:$340>
N019 ( 9, 16) [000004] ---XG------- | /--* IND byte <l:$2c1, c:$300>
N017 ( 1, 1) [000031] ------------ | | | /--* CNS_INT long 14 field offset Fseq[F0] $1c1
N018 ( 6, 13) [000032] ----G--N---- | | \--* ADD byref <l:$203, c:$202>
N016 ( 5, 12) CSE #01 (use)[000003] x---G------- | | \--* IND ref <l:$140, c:$181>
N015 ( 3, 10) [000033] ------------ | | \--* CNS_INT(h) long 0x1c4f1e92978 static Fseq[s_1] $100
N020 ( 23, 34) [000005] -A-XG------- | /--* LT int <l:$341, c:$340>
N013 ( 1, 1) [000055] ------------ | | | /--* LCL_VAR int V02 cse1 <l:$241, c:$280>
N014 ( 10, 17) [000056] -A-XG------- | | \--* COMMA int <l:$241, c:$280>
N010 ( 9, 16) [000002] ---XG------- | | | /--* IND ushort <l:$241, c:$280>
N008 ( 1, 1) [000028] ------------ | | | | | /--* CNS_INT long 12 field offset Fseq[F7] $1c0
N009 ( 6, 13) [000029] ----G--N---- | | | | \--* ADD byref <l:$201, c:$200>
N007 ( 5, 12) CSE #01 (def)[000001] x---G------- | | | | \--* IND ref <l:$140, c:$180>
N006 ( 3, 10) [000030] ------------ | | | | \--* CNS_INT(h) long 0x1c4f1e92978 static Fseq[s_1] $100
N012 ( 9, 16) [000054] -A-XG---R--- | | \--* ASG int $VN.Void
N011 ( 1, 1) [000053] D------N---- | | \--* LCL_VAR int V02 cse1 <l:$241, c:$280>
N022 ( 23, 34) [000047] -A-XG---R--- | /--* ASG int $VN.Void
N021 ( 1, 1) [000046] D------N---- | | \--* LCL_VAR int V01 cse0 <l:$341, c:$340>
N023 ( 31, 49) [000051] -A-XG------- \--* COMMA void $VN.Void
N005 ( 8, 15) CSE #02 (def)[000007] ---XG------- \--* IND int <l:$343, c:$380>
N003 ( 1, 1) [000034] ------------ | /--* CNS_INT long 8 field offset Fseq[F8] $1c2
N004 ( 6, 13) [000035] ----G--N---- \--* ADD byref <l:$205, c:$204>
N002 ( 5, 12) CSE #01 (use)[000006] x---G------- \--* IND ref <l:$140, c:$182>
N001 ( 3, 10) [000036] ------------ \--* CNS_INT(h) long 0x1c4f1e92978 static Fseq[s_1] $100
Working on the replacement of the CSE #04 use at [000024] in BB02
Unmark CSE use #01 at [000023]: 4 -> 3
CSE #00 use at [000024] replaced in BB02 with temp use.
New refCnts for V02: refCnt = 5, refCntWtd = 4.50
New refCnts for V02: refCnt = 6, refCntWtd = 5
optValnumCSE morphed tree:
N006 ( 1, 1) [000057] ------------ /--* LCL_VAR int V02 cse1 <l:$241, c:$280>
N007 ( 11, 18) [000026] -A-XG------- * ASG ushort $VN.Void
N005 ( 9, 16) [000025] ---XG--N---- \--* IND ushort $241
N003 ( 1, 1) [000040] ------------ | /--* CNS_INT long 12 field offset Fseq[F7] $1c0
N004 ( 6, 13) [000041] ----G--N---- \--* ADD byref <l:$201, c:$207>
N002 ( 5, 12) CSE #01 (use)[000022] x---G------- \--* IND ref <l:$140, c:$184>
N001 ( 3, 10) [000042] ------------ \--* CNS_INT(h) long 0x1c4f1e92978 static Fseq[s_1] $100
Skipped CSE #02 because use count is 0
Considering CSE #01 [def=100, use=250, cost= 5] CSE Expression:
N007 ( 5, 12) CSE #01 (def)[000001] x---G------- * IND ref <l:$140, c:$180>
N006 ( 3, 10) [000030] ------------ \--* CNS_INT(h) long 0x1c4f1e92978 static Fseq[s_1] $100
Aggressive CSE Promotion (450 >= 100)
cseRefCnt=450, aggressiveRefCnt=100, moderateRefCnt=50
defCnt=100, useCnt=250, cost=5, size=12
def_cost=1, use_cost=1, extra_no_cost=66, extra_yes_cost=0
CSE cost savings check (1316 >= 350) passes
Promoting CSE:
lvaGrabTemp returning 3 (V03 rat0) (a long lifetime temp) called for ValNumCSE.
CSE #01 def at [000001] replaced in BB01 with def of V03
New refCnts for V03: refCnt = 1, refCntWtd = 1
New refCnts for V03: refCnt = 2, refCntWtd = 2
New refCnts for V01: refCnt = 9, refCntWtd = 9
New refCnts for V02: refCnt = 7, refCntWtd = 6
New refCnts for V03: refCnt = 3, refCntWtd = 3
New refCnts for V03: refCnt = 4, refCntWtd = 4
New refCnts for V02: refCnt = 8, refCntWtd = 7
New refCnts for V01: refCnt = 10, refCntWtd = 10
optValnumCSE morphed tree:
N032 ( 37, 55) [000016] -A-XG------- * JTRUE void
N030 ( 1, 1) [000014] ------------ | /--* CNS_INT int 0 $82
N031 ( 35, 53) [000015] JA-XG--N---- \--* EQ int <l:$347, c:$346>
N028 ( 1, 1) [000050] ------------ | /--* LCL_VAR int V01 cse0 <l:$341, c:$340>
N029 ( 33, 51) [000052] -A-XG------- \--* COMMA int <l:$341, c:$340>
N023 ( 9, 16) [000004] ---XG------- | /--* IND byte <l:$2c1, c:$300>
N021 ( 1, 1) [000031] ------------ | | | /--* CNS_INT long 14 field offset Fseq[F0] $1c1
N022 ( 6, 13) [000032] ----G--N---- | | \--* ADD byref <l:$203, c:$202>
N020 ( 5, 12) CSE #01 (use)[000003] x---G------- | | \--* IND ref <l:$140, c:$181>
N019 ( 3, 10) [000033] ------------ | | \--* CNS_INT(h) long 0x1c4f1e92978 static Fseq[s_1] $100
N024 ( 24, 35) [000005] -A-XG------- | /--* LT int <l:$341, c:$340>
N017 ( 1, 1) [000055] ------------ | | | /--* LCL_VAR int V02 cse1 <l:$241, c:$280>
N018 ( 11, 18) [000056] -A-XG------- | | \--* COMMA int <l:$241, c:$280>
N014 ( 10, 17) [000002] -A-XG------- | | | /--* IND ushort <l:$241, c:$280>
N012 ( 1, 1) [000028] ------------ | | | | | /--* CNS_INT long 12 field offset Fseq[F7] $1c0
N013 ( 7, 14) [000029] -A--G--N---- | | | | \--* ADD byref <l:$201, c:$200>
N010 ( 1, 1) [000060] ------------ | | | | | /--* LCL_VAR ref V03 cse2 <l:$140, c:$180>
N011 ( 6, 13) [000061] -A--G------- | | | | \--* COMMA ref <l:$140, c:$180>
N007 ( 5, 12) [000001] x---G------- | | | | | /--* IND ref <l:$140, c:$180>
N006 ( 3, 10) [000030] ------------ | | | | | | \--* CNS_INT(h) long 0x1c4f1e92978 static Fseq[s_1] $100
N009 ( 5, 12) [000059] -A--G---R--- | | | | \--* ASG ref $VN.Void
N008 ( 1, 1) [000058] D------N---- | | | | \--* LCL_VAR ref V03 cse2 <l:$140, c:$180>
N016 ( 10, 17) [000054] -A-XG---R--- | | \--* ASG int $VN.Void
N015 ( 1, 1) [000053] D------N---- | | \--* LCL_VAR int V02 cse1 <l:$241, c:$280>
N026 ( 24, 35) [000047] -A-XG---R--- | /--* ASG int $VN.Void
N025 ( 1, 1) [000046] D------N---- | | \--* LCL_VAR int V01 cse0 <l:$341, c:$340>
N027 ( 32, 50) [000051] -A-XG------- \--* COMMA void $VN.Void
N005 ( 8, 15) CSE #02 (def)[000007] ---XG------- \--* IND int <l:$343, c:$380>
N003 ( 1, 1) [000034] ------------ | /--* CNS_INT long 8 field offset Fseq[F8] $1c2
N004 ( 6, 13) [000035] ----G--N---- \--* ADD byref <l:$205, c:$204>
N002 ( 5, 12) CSE #01 (use)[000006] x---G------- \--* IND ref <l:$140, c:$182>
N001 ( 3, 10) [000036] ------------ \--* CNS_INT(h) long 0x1c4f1e92978 static Fseq[s_1] $100
Working on the replacement of the CSE #01 use at [000003] in BB01
CSE #00 use at [000003] replaced in BB01 with temp use.
New refCnts for V03: refCnt = 5, refCntWtd = 5
New refCnts for V01: refCnt = 11, refCntWtd = 11
New refCnts for V02: refCnt = 9, refCntWtd = 8
New refCnts for V03: refCnt = 6, refCntWtd = 6
New refCnts for V03: refCnt = 7, refCntWtd = 7
New refCnts for V02: refCnt = 10, refCntWtd = 9
New refCnts for V03: refCnt = 8, refCntWtd = 8
New refCnts for V01: refCnt = 12, refCntWtd = 12
optValnumCSE morphed tree:
N031 ( 33, 44) [000016] -A-XG------- * JTRUE void
N029 ( 1, 1) [000014] ------------ | /--* CNS_INT int 0 $82
N030 ( 31, 42) [000015] JA-XG--N---- \--* EQ int <l:$347, c:$346>
N027 ( 1, 1) [000050] ------------ | /--* LCL_VAR int V01 cse0 <l:$341, c:$340>
N028 ( 29, 40) [000052] -A-XG------- \--* COMMA int <l:$341, c:$340>
N022 ( 5, 5) [000004] ---XG------- | /--* IND byte <l:$2c1, c:$300>
N020 ( 1, 1) [000031] ------------ | | | /--* CNS_INT long 14 field offset Fseq[F0] $1c1
N021 ( 2, 2) [000032] ----G--N---- | | \--* ADD byref <l:$203, c:$202>
N019 ( 1, 1) [000062] ------------ | | \--* LCL_VAR ref V03 cse2 <l:$140, c:$180>
N023 ( 20, 24) [000005] -A-XG------- | /--* LT int <l:$341, c:$340>
N017 ( 1, 1) [000055] ------------ | | | /--* LCL_VAR int V02 cse1 <l:$241, c:$280>
N018 ( 11, 18) [000056] -A-XG------- | | \--* COMMA int <l:$241, c:$280>
N014 ( 10, 17) [000002] -A-XG------- | | | /--* IND ushort <l:$241, c:$280>
N012 ( 1, 1) [000028] ------------ | | | | | /--* CNS_INT long 12 field offset Fseq[F7] $1c0
N013 ( 7, 14) [000029] -A--G--N---- | | | | \--* ADD byref <l:$201, c:$200>
N010 ( 1, 1) [000060] ------------ | | | | | /--* LCL_VAR ref V03 cse2 <l:$140, c:$180>
N011 ( 6, 13) [000061] -A--G------- | | | | \--* COMMA ref <l:$140, c:$180>
N007 ( 5, 12) [000001] x---G------- | | | | | /--* IND ref <l:$140, c:$180>
N006 ( 3, 10) [000030] ------------ | | | | | | \--* CNS_INT(h) long 0x1c4f1e92978 static Fseq[s_1] $100
N009 ( 5, 12) [000059] -A--G---R--- | | | | \--* ASG ref $VN.Void
N008 ( 1, 1) [000058] D------N---- | | | | \--* LCL_VAR ref V03 cse2 <l:$140, c:$180>
N016 ( 10, 17) [000054] -A-XG---R--- | | \--* ASG int $VN.Void
N015 ( 1, 1) [000053] D------N---- | | \--* LCL_VAR int V02 cse1 <l:$241, c:$280>
N025 ( 20, 24) [000047] -A-XG---R--- | /--* ASG int $VN.Void
N024 ( 1, 1) [000046] D------N---- | | \--* LCL_VAR int V01 cse0 <l:$341, c:$340>
N026 ( 28, 39) [000051] -A-XG------- \--* COMMA void $VN.Void
N005 ( 8, 15) CSE #02 (def)[000007] ---XG------- \--* IND int <l:$343, c:$380>
N003 ( 1, 1) [000034] ------------ | /--* CNS_INT long 8 field offset Fseq[F8] $1c2
N004 ( 6, 13) [000035] ----G--N---- \--* ADD byref <l:$205, c:$204>
N002 ( 5, 12) CSE #01 (use)[000006] x---G------- \--* IND ref <l:$140, c:$182>
N001 ( 3, 10) [000036] ------------ \--* CNS_INT(h) long 0x1c4f1e92978 static Fseq[s_1] $100
Working on the replacement of the CSE #01 use at [000006] in BB01
CSE #00 use at [000006] replaced in BB01 with temp use.
New refCnts for V03: refCnt = 9, refCntWtd = 9
New refCnts for V03: refCnt = 10, refCntWtd = 10
New refCnts for V01: refCnt = 13, refCntWtd = 13
New refCnts for V02: refCnt = 11, refCntWtd = 10
New refCnts for V03: refCnt = 11, refCntWtd = 11
New refCnts for V03: refCnt = 12, refCntWtd = 12
New refCnts for V02: refCnt = 12, refCntWtd = 11
New refCnts for V03: refCnt = 13, refCntWtd = 13
New refCnts for V01: refCnt = 14, refCntWtd = 14
optValnumCSE morphed tree:
N030 ( 29, 33) [000016] -A-XG------- * JTRUE void
N028 ( 1, 1) [000014] ------------ | /--* CNS_INT int 0 $82
N029 ( 27, 31) [000015] JA-XG--N---- \--* EQ int <l:$347, c:$346>
N026 ( 1, 1) [000050] ------------ | /--* LCL_VAR int V01 cse0 <l:$341, c:$340>
N027 ( 25, 29) [000052] -A-XG------- \--* COMMA int <l:$341, c:$340>
N021 ( 5, 5) [000004] ---XG------- | /--* IND byte <l:$2c1, c:$300>
N019 ( 1, 1) [000031] ------------ | | | /--* CNS_INT long 14 field offset Fseq[F0] $1c1
N020 ( 2, 2) [000032] ----G--N---- | | \--* ADD byref <l:$203, c:$202>
N018 ( 1, 1) [000062] ------------ | | \--* LCL_VAR ref V03 cse2 <l:$140, c:$180>
N022 ( 20, 24) [000005] -A-XG------- | /--* LT int <l:$341, c:$340>
N016 ( 1, 1) [000055] ------------ | | | /--* LCL_VAR int V02 cse1 <l:$241, c:$280>
N017 ( 11, 18) [000056] -A-XG------- | | \--* COMMA int <l:$241, c:$280>
N013 ( 10, 17) [000002] -A-XG------- | | | /--* IND ushort <l:$241, c:$280>
N011 ( 1, 1) [000028] ------------ | | | | | /--* CNS_INT long 12 field offset Fseq[F7] $1c0
N012 ( 7, 14) [000029] -A--G--N---- | | | | \--* ADD byref <l:$201, c:$200>
N009 ( 1, 1) [000060] ------------ | | | | | /--* LCL_VAR ref V03 cse2 <l:$140, c:$180>
N010 ( 6, 13) [000061] -A--G------- | | | | \--* COMMA ref <l:$140, c:$180>
N006 ( 5, 12) [000001] x---G------- | | | | | /--* IND ref <l:$140, c:$180>
N005 ( 3, 10) [000030] ------------ | | | | | | \--* CNS_INT(h) long 0x1c4f1e92978 static Fseq[s_1] $100
N008 ( 5, 12) [000059] -A--G---R--- | | | | \--* ASG ref $VN.Void
N007 ( 1, 1) [000058] D------N---- | | | | \--* LCL_VAR ref V03 cse2 <l:$140, c:$180>
N015 ( 10, 17) [000054] -A-XG---R--- | | \--* ASG int $VN.Void
N014 ( 1, 1) [000053] D------N---- | | \--* LCL_VAR int V02 cse1 <l:$241, c:$280>
N024 ( 20, 24) [000047] -A-XG---R--- | /--* ASG int $VN.Void
N023 ( 1, 1) [000046] D------N---- | | \--* LCL_VAR int V01 cse0 <l:$341, c:$340>
N025 ( 24, 28) [000051] -A-XG------- \--* COMMA void $VN.Void
N004 ( 4, 4) CSE #02 (def)[000007] ---XG------- \--* IND int <l:$343, c:$380>
N002 ( 1, 1) [000034] ------------ | /--* CNS_INT long 8 field offset Fseq[F8] $1c2
N003 ( 2, 2) [000035] ----G--N---- \--* ADD byref <l:$205, c:$204>
N001 ( 1, 1) [000063] ------------ \--* LCL_VAR ref V03 cse2 <l:$140, c:$180>
Working on the replacement of the CSE #01 use at [000022] in BB02
CSE #00 use at [000022] replaced in BB02 with temp use.
New refCnts for V03: refCnt = 14, refCntWtd = 13.50
New refCnts for V03: refCnt = 15, refCntWtd = 14
New refCnts for V02: refCnt = 13, refCntWtd = 11.50
optValnumCSE morphed tree:
N005 ( 1, 1) [000057] ------------ /--* LCL_VAR int V02 cse1 <l:$241, c:$280>
N006 ( 7, 7) [000026] -A-XG------- * ASG ushort $VN.Void
N004 ( 5, 5) [000025] ---XG--N---- \--* IND ushort $241
N002 ( 1, 1) [000040] ------------ | /--* CNS_INT long 12 field offset Fseq[F7] $1c0
N003 ( 2, 2) [000041] ----G--N---- \--* ADD byref <l:$201, c:$207>
N001 ( 1, 1) [000064] ------------ \--* LCL_VAR ref V03 cse2 <l:$140, c:$180>
*************** In optAssertionPropMain()
Blocks/Trees at start of phase
--------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
--------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..032)-> BB03 ( cond ) i label target
BB02 [0001] 1 BB01 0.50 [032..046) i
BB03 [0002] 2 BB01,BB02 1 [046..047) (return) i label target
--------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [000..032) -> BB03 (cond), preds={} succs={BB02,BB03}
***** BB01, stmt 1
( 29, 33) [000017] ------------ * STMT void (IL 0x000...0x030)
N030 ( 29, 33) [000016] -A-XG------- \--* JTRUE void
N028 ( 1, 1) [000014] ------------ | /--* CNS_INT int 0 $82
N029 ( 27, 31) [000015] JA-XG--N---- \--* EQ int <l:$347, c:$346>
N026 ( 1, 1) [000050] ------------ | /--* LCL_VAR int V01 cse0 <l:$341, c:$340>
N027 ( 25, 29) [000052] -A-XG------- \--* COMMA int <l:$341, c:$340>
N021 ( 5, 5) [000004] ---XG------- | /--* IND byte <l:$2c1, c:$300>
N019 ( 1, 1) [000031] ------------ | | | /--* CNS_INT long 14 field offset Fseq[F0] $1c1
N020 ( 2, 2) [000032] ----G--N---- | | \--* ADD byref <l:$203, c:$202>
N018 ( 1, 1) [000062] ------------ | | \--* LCL_VAR ref V03 cse2 <l:$140, c:$180>
N022 ( 20, 24) [000005] -A-XG------- | /--* LT int <l:$341, c:$340>
N016 ( 1, 1) [000055] ------------ | | | /--* LCL_VAR int V02 cse1 <l:$241, c:$280>
N017 ( 11, 18) [000056] -A-XG------- | | \--* COMMA int <l:$241, c:$280>
N013 ( 10, 17) [000002] -A-XG------- | | | /--* IND ushort <l:$241, c:$280>
N011 ( 1, 1) [000028] ------------ | | | | | /--* CNS_INT long 12 field offset Fseq[F7] $1c0
N012 ( 7, 14) [000029] -A--G--N---- | | | | \--* ADD byref <l:$201, c:$200>
N009 ( 1, 1) [000060] ------------ | | | | | /--* LCL_VAR ref V03 cse2 <l:$140, c:$180>
N010 ( 6, 13) [000061] -A--G------- | | | | \--* COMMA ref <l:$140, c:$180>
N006 ( 5, 12) [000001] x---G------- | | | | | /--* IND ref <l:$140, c:$180>
N005 ( 3, 10) [000030] ------------ | | | | | | \--* CNS_INT(h) long 0x1c4f1e92978 static Fseq[s_1] $100
N008 ( 5, 12) [000059] -A--G---R--- | | | | \--* ASG ref $VN.Void
N007 ( 1, 1) [000058] D------N---- | | | | \--* LCL_VAR ref V03 cse2 <l:$140, c:$180>
N015 ( 10, 17) [000054] -A-XG---R--- | | \--* ASG int $VN.Void
N014 ( 1, 1) [000053] D------N---- | | \--* LCL_VAR int V02 cse1 <l:$241, c:$280>
N024 ( 20, 24) [000047] -A-XG---R--- | /--* ASG int $VN.Void
N023 ( 1, 1) [000046] D------N---- | | \--* LCL_VAR int V01 cse0 <l:$341, c:$340>
N025 ( 24, 28) [000051] -A-XG------- \--* COMMA void $VN.Void
N004 ( 4, 4) [000007] ---XG------- \--* IND int <l:$343, c:$380>
N002 ( 1, 1) [000034] ------------ | /--* CNS_INT long 8 field offset Fseq[F8] $1c2
N003 ( 2, 2) [000035] ----G--N---- \--* ADD byref <l:$205, c:$204>
N001 ( 1, 1) [000063] ------------ \--* LCL_VAR ref V03 cse2 <l:$140, c:$180>
------------ BB02 [032..046), preds={BB01} succs={BB03}
***** BB02, stmt 2
( 7, 7) [000027] ------------ * STMT void (IL 0x032...0x041)
N005 ( 1, 1) [000057] ------------ | /--* LCL_VAR int V02 cse1 <l:$241, c:$280>
N006 ( 7, 7) [000026] -A-XG------- \--* ASG ushort $VN.Void
N004 ( 5, 5) [000025] ---XG--N---- \--* IND ushort $241
N002 ( 1, 1) [000040] ------------ | /--* CNS_INT long 12 field offset Fseq[F7] $1c0
N003 ( 2, 2) [000041] ----G--N---- \--* ADD byref <l:$201, c:$207>
N001 ( 1, 1) [000064] ------------ \--* LCL_VAR ref V03 cse2 <l:$140, c:$180>
------------ BB03 [046..047) (return), preds={BB01,BB02} succs={}
***** BB03, stmt 3
( 0, 0) [000020] ------------ * STMT void (IL 0x046...0x046)
N001 ( 0, 0) [000019] ------------ \--* RETURN void $440
-------------------------------------------------------------------------------------------------------------------
*************** In OptimizeRangeChecks()
Blocks/trees before phase
--------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
--------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..032)-> BB03 ( cond ) i label target
BB02 [0001] 1 BB01 0.50 [032..046) i
BB03 [0002] 2 BB01,BB02 1 [046..047) (return) i label target
--------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [000..032) -> BB03 (cond), preds={} succs={BB02,BB03}
***** BB01, stmt 1
( 29, 33) [000017] ------------ * STMT void (IL 0x000...0x030)
N030 ( 29, 33) [000016] -A-XG------- \--* JTRUE void
N028 ( 1, 1) [000014] ------------ | /--* CNS_INT int 0 $82
N029 ( 27, 31) [000015] JA-XG--N---- \--* EQ int <l:$347, c:$346>
N026 ( 1, 1) [000050] ------------ | /--* LCL_VAR int V01 cse0 <l:$341, c:$340>
N027 ( 25, 29) [000052] -A-XG------- \--* COMMA int <l:$341, c:$340>
N021 ( 5, 5) [000004] ---XG------- | /--* IND byte <l:$2c1, c:$300>
N019 ( 1, 1) [000031] ------------ | | | /--* CNS_INT long 14 field offset Fseq[F0] $1c1
N020 ( 2, 2) [000032] ----G--N---- | | \--* ADD byref <l:$203, c:$202>
N018 ( 1, 1) [000062] ------------ | | \--* LCL_VAR ref V03 cse2 <l:$140, c:$180>
N022 ( 20, 24) [000005] -A-XG------- | /--* LT int <l:$341, c:$340>
N016 ( 1, 1) [000055] ------------ | | | /--* LCL_VAR int V02 cse1 <l:$241, c:$280>
N017 ( 11, 18) [000056] -A-XG------- | | \--* COMMA int <l:$241, c:$280>
N013 ( 10, 17) [000002] -A-XG------- | | | /--* IND ushort <l:$241, c:$280>
N011 ( 1, 1) [000028] ------------ | | | | | /--* CNS_INT long 12 field offset Fseq[F7] $1c0
N012 ( 7, 14) [000029] -A--G--N---- | | | | \--* ADD byref <l:$201, c:$200>
N009 ( 1, 1) [000060] ------------ | | | | | /--* LCL_VAR ref V03 cse2 <l:$140, c:$180>
N010 ( 6, 13) [000061] -A--G------- | | | | \--* COMMA ref <l:$140, c:$180>
N006 ( 5, 12) [000001] x---G------- | | | | | /--* IND ref <l:$140, c:$180>
N005 ( 3, 10) [000030] ------------ | | | | | | \--* CNS_INT(h) long 0x1c4f1e92978 static Fseq[s_1] $100
N008 ( 5, 12) [000059] -A--G---R--- | | | | \--* ASG ref $VN.Void
N007 ( 1, 1) [000058] D------N---- | | | | \--* LCL_VAR ref V03 cse2 <l:$140, c:$180>
N015 ( 10, 17) [000054] -A-XG---R--- | | \--* ASG int $VN.Void
N014 ( 1, 1) [000053] D------N---- | | \--* LCL_VAR int V02 cse1 <l:$241, c:$280>
N024 ( 20, 24) [000047] -A-XG---R--- | /--* ASG int $VN.Void
N023 ( 1, 1) [000046] D------N---- | | \--* LCL_VAR int V01 cse0 <l:$341, c:$340>
N025 ( 24, 28) [000051] -A-XG------- \--* COMMA void $VN.Void
N004 ( 4, 4) [000007] ---XG------- \--* IND int <l:$343, c:$380>
N002 ( 1, 1) [000034] ------------ | /--* CNS_INT long 8 field offset Fseq[F8] $1c2
N003 ( 2, 2) [000035] ----G--N---- \--* ADD byref <l:$205, c:$204>
N001 ( 1, 1) [000063] ------------ \--* LCL_VAR ref V03 cse2 <l:$140, c:$180>
------------ BB02 [032..046), preds={BB01} succs={BB03}
***** BB02, stmt 2
( 7, 7) [000027] ------------ * STMT void (IL 0x032...0x041)
N005 ( 1, 1) [000057] ------------ | /--* LCL_VAR int V02 cse1 <l:$241, c:$280>
N006 ( 7, 7) [000026] -A-XG------- \--* ASG ushort $VN.Void
N004 ( 5, 5) [000025] ---XG--N---- \--* IND ushort $241
N002 ( 1, 1) [000040] ------------ | /--* CNS_INT long 12 field offset Fseq[F7] $1c0
N003 ( 2, 2) [000041] ----G--N---- \--* ADD byref <l:$201, c:$207>
N001 ( 1, 1) [000064] ------------ \--* LCL_VAR ref V03 cse2 <l:$140, c:$180>
------------ BB03 [046..047) (return), preds={BB01,BB02} succs={}
***** BB03, stmt 3
( 0, 0) [000020] ------------ * STMT void (IL 0x046...0x046)
N001 ( 0, 0) [000019] ------------ \--* RETURN void $440
-------------------------------------------------------------------------------------------------------------------
*************** In fgDetermineFirstColdBlock()
No procedure splitting will be done for this method
*************** In IR Rationalize
Trees before IR Rationalize
--------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
--------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..032)-> BB03 ( cond ) i label target
BB02 [0001] 1 BB01 0.50 [032..046) i
BB03 [0002] 2 BB01,BB02 1 [046..047) (return) i label target
--------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [000..032) -> BB03 (cond), preds={} succs={BB02,BB03}
***** BB01, stmt 1
( 29, 33) [000017] ------------ * STMT void (IL 0x000...0x030)
N030 ( 29, 33) [000016] -A-XG------- \--* JTRUE void
N028 ( 1, 1) [000014] ------------ | /--* CNS_INT int 0 $82
N029 ( 27, 31) [000015] JA-XG--N---- \--* EQ int <l:$347, c:$346>
N026 ( 1, 1) [000050] ------------ | /--* LCL_VAR int V01 cse0 <l:$341, c:$340>
N027 ( 25, 29) [000052] -A-XG------- \--* COMMA int <l:$341, c:$340>
N021 ( 5, 5) [000004] ---XG------- | /--* IND byte <l:$2c1, c:$300>
N019 ( 1, 1) [000031] ------------ | | | /--* CNS_INT long 14 field offset Fseq[F0] $1c1
N020 ( 2, 2) [000032] ----G--N---- | | \--* ADD byref <l:$203, c:$202>
N018 ( 1, 1) [000062] ------------ | | \--* LCL_VAR ref V03 cse2 <l:$140, c:$180>
N022 ( 20, 24) [000005] -A-XG------- | /--* LT int <l:$341, c:$340>
N016 ( 1, 1) [000055] ------------ | | | /--* LCL_VAR int V02 cse1 <l:$241, c:$280>
N017 ( 11, 18) [000056] -A-XG------- | | \--* COMMA int <l:$241, c:$280>
N013 ( 10, 17) [000002] -A-XG------- | | | /--* IND ushort <l:$241, c:$280>
N011 ( 1, 1) [000028] ------------ | | | | | /--* CNS_INT long 12 field offset Fseq[F7] $1c0
N012 ( 7, 14) [000029] -A--G--N---- | | | | \--* ADD byref <l:$201, c:$200>
N009 ( 1, 1) [000060] ------------ | | | | | /--* LCL_VAR ref V03 cse2 <l:$140, c:$180>
N010 ( 6, 13) [000061] -A--G------- | | | | \--* COMMA ref <l:$140, c:$180>
N006 ( 5, 12) [000001] x---G------- | | | | | /--* IND ref <l:$140, c:$180>
N005 ( 3, 10) [000030] ------------ | | | | | | \--* CNS_INT(h) long 0x1c4f1e92978 static Fseq[s_1] $100
N008 ( 5, 12) [000059] -A--G---R--- | | | | \--* ASG ref $VN.Void
N007 ( 1, 1) [000058] D------N---- | | | | \--* LCL_VAR ref V03 cse2 <l:$140, c:$180>
N015 ( 10, 17) [000054] -A-XG---R--- | | \--* ASG int $VN.Void
N014 ( 1, 1) [000053] D------N---- | | \--* LCL_VAR int V02 cse1 <l:$241, c:$280>
N024 ( 20, 24) [000047] -A-XG---R--- | /--* ASG int $VN.Void
N023 ( 1, 1) [000046] D------N---- | | \--* LCL_VAR int V01 cse0 <l:$341, c:$340>
N025 ( 24, 28) [000051] -A-XG------- \--* COMMA void $VN.Void
N004 ( 4, 4) [000007] ---XG------- \--* IND int <l:$343, c:$380>
N002 ( 1, 1) [000034] ------------ | /--* CNS_INT long 8 field offset Fseq[F8] $1c2
N003 ( 2, 2) [000035] ----G--N---- \--* ADD byref <l:$205, c:$204>
N001 ( 1, 1) [000063] ------------ \--* LCL_VAR ref V03 cse2 <l:$140, c:$180>
------------ BB02 [032..046), preds={BB01} succs={BB03}
***** BB02, stmt 2
( 7, 7) [000027] ------------ * STMT void (IL 0x032...0x041)
N005 ( 1, 1) [000057] ------------ | /--* LCL_VAR int V02 cse1 <l:$241, c:$280>
N006 ( 7, 7) [000026] -A-XG------- \--* ASG ushort $VN.Void
N004 ( 5, 5) [000025] ---XG--N---- \--* IND ushort $241
N002 ( 1, 1) [000040] ------------ | /--* CNS_INT long 12 field offset Fseq[F7] $1c0
N003 ( 2, 2) [000041] ----G--N---- \--* ADD byref <l:$201, c:$207>
N001 ( 1, 1) [000064] ------------ \--* LCL_VAR ref V03 cse2 <l:$140, c:$180>
------------ BB03 [046..047) (return), preds={BB01,BB02} succs={}
***** BB03, stmt 3
( 0, 0) [000020] ------------ * STMT void (IL 0x046...0x046)
N001 ( 0, 0) [000019] ------------ \--* RETURN void $440
-------------------------------------------------------------------------------------------------------------------
rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X)
N008 ( 5, 12) [000059] DA--G------- * STORE_LCL_VAR ref V03 cse2
rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X)
N015 ( 10, 17) [000054] DA-XG------- * STORE_LCL_VAR int V02 cse1
rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X)
N024 ( 20, 24) [000047] DA-XG------- * STORE_LCL_VAR int V01 cse0
*************** Exiting IR Rationalize
Trees after IR Rationalize
--------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
--------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..032)-> BB03 ( cond ) i label target LIR
BB02 [0001] 1 BB01 0.50 [032..046) i LIR
BB03 [0002] 2 BB01,BB02 1 [046..047) (return) i label target LIR
--------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [000..032) -> BB03 (cond), preds={} succs={BB02,BB03}
( 29, 33) [000017] ------------ IL_OFFSET void IL offset: 0x0
N001 ( 1, 1) [000063] ------------ t63 = LCL_VAR ref V03 cse2 <l:$140, c:$180>
N002 ( 1, 1) [000034] ------------ t34 = CNS_INT long 8 field offset Fseq[F8] $1c2
/--* t63 ref
+--* t34 long
N003 ( 2, 2) [000035] ----G--N---- t35 = * ADD byref <l:$205, c:$204>
/--* t35 byref
N004 ( 4, 4) [000007] ---XG------- t7 = * IND int <l:$343, c:$380>
N005 ( 3, 10) [000030] ------------ t30 = CNS_INT(h) long 0x1c4f1e92978 static Fseq[s_1] $100
/--* t30 long
N006 ( 5, 12) [000001] x---G------- t1 = * IND ref <l:$140, c:$180>
/--* t1 ref
N008 ( 5, 12) [000059] DA--G------- * STORE_LCL_VAR ref V03 cse2
N009 ( 1, 1) [000060] ------------ t60 = LCL_VAR ref V03 cse2 <l:$140, c:$180>
N011 ( 1, 1) [000028] ------------ t28 = CNS_INT long 12 field offset Fseq[F7] $1c0
/--* t60 ref
+--* t28 long
N012 ( 7, 14) [000029] ----G--N---- t29 = * ADD byref <l:$201, c:$200>
/--* t29 byref
N013 ( 10, 17) [000002] ---XG------- t2 = * IND ushort <l:$241, c:$280>
/--* t2 ushort
N015 ( 10, 17) [000054] DA-XG------- * STORE_LCL_VAR int V02 cse1
N016 ( 1, 1) [000055] ------------ t55 = LCL_VAR int V02 cse1 <l:$241, c:$280>
N018 ( 1, 1) [000062] ------------ t62 = LCL_VAR ref V03 cse2 <l:$140, c:$180>
N019 ( 1, 1) [000031] ------------ t31 = CNS_INT long 14 field offset Fseq[F0] $1c1
/--* t62 ref
+--* t31 long
N020 ( 2, 2) [000032] ----G--N---- t32 = * ADD byref <l:$203, c:$202>
/--* t32 byref
N021 ( 5, 5) [000004] ---XG------- t4 = * IND byte <l:$2c1, c:$300>
/--* t55 int
+--* t4 byte
N022 ( 20, 24) [000005] ---XG------- t5 = * LT int <l:$341, c:$340>
/--* t5 int
N024 ( 20, 24) [000047] DA-XG------- * STORE_LCL_VAR int V01 cse0
N026 ( 1, 1) [000050] ------------ t50 = LCL_VAR int V01 cse0 <l:$341, c:$340>
N028 ( 1, 1) [000014] ------------ t14 = CNS_INT int 0 $82
/--* t50 int
+--* t14 int
N029 ( 27, 31) [000015] J--XG--N---- t15 = * EQ int <l:$347, c:$346>
/--* t15 int
N030 ( 29, 33) [000016] ---XG------- * JTRUE void
------------ BB02 [032..046), preds={BB01} succs={BB03}
( 7, 7) [000027] ------------ IL_OFFSET void IL offset: 0x32
N001 ( 1, 1) [000064] ------------ t64 = LCL_VAR ref V03 cse2 <l:$140, c:$180>
N002 ( 1, 1) [000040] ------------ t40 = CNS_INT long 12 field offset Fseq[F7] $1c0
/--* t64 ref
+--* t40 long
N003 ( 2, 2) [000041] ----G--N---- t41 = * ADD byref <l:$201, c:$207>
N005 ( 1, 1) [000057] ------------ t57 = LCL_VAR int V02 cse1 <l:$241, c:$280>
/--* t41 byref
+--* t57 int
[000065] -A-XG------- * STOREIND ushort
------------ BB03 [046..047) (return), preds={BB01,BB02} succs={}
( 0, 0) [000020] ------------ IL_OFFSET void IL offset: 0x46
N001 ( 0, 0) [000019] ------------ RETURN void $440
-------------------------------------------------------------------------------------------------------------------
*************** In fgDebugCheckBBlist
*************** In fgDebugCheckBBlist
*************** In Lowering
Trees before Lowering
--------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
--------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..032)-> BB03 ( cond ) i label target LIR
BB02 [0001] 1 BB01 0.50 [032..046) i LIR
BB03 [0002] 2 BB01,BB02 1 [046..047) (return) i label target LIR
--------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [000..032) -> BB03 (cond), preds={} succs={BB02,BB03}
( 29, 33) [000017] ------------ IL_OFFSET void IL offset: 0x0
N001 ( 1, 1) [000063] ------------ t63 = LCL_VAR ref V03 cse2 <l:$140, c:$180>
N002 ( 1, 1) [000034] ------------ t34 = CNS_INT long 8 field offset Fseq[F8] $1c2
/--* t63 ref
+--* t34 long
N003 ( 2, 2) [000035] ----G--N---- t35 = * ADD byref <l:$205, c:$204>
/--* t35 byref
N004 ( 4, 4) [000007] ---XG------- t7 = * IND int <l:$343, c:$380>
N005 ( 3, 10) [000030] ------------ t30 = CNS_INT(h) long 0x1c4f1e92978 static Fseq[s_1] $100
/--* t30 long
N006 ( 5, 12) [000001] x---G------- t1 = * IND ref <l:$140, c:$180>
/--* t1 ref
N008 ( 5, 12) [000059] DA--G------- * STORE_LCL_VAR ref V03 cse2
N009 ( 1, 1) [000060] ------------ t60 = LCL_VAR ref V03 cse2 <l:$140, c:$180>
N011 ( 1, 1) [000028] ------------ t28 = CNS_INT long 12 field offset Fseq[F7] $1c0
/--* t60 ref
+--* t28 long
N012 ( 7, 14) [000029] ----G--N---- t29 = * ADD byref <l:$201, c:$200>
/--* t29 byref
N013 ( 10, 17) [000002] ---XG------- t2 = * IND ushort <l:$241, c:$280>
/--* t2 ushort
N015 ( 10, 17) [000054] DA-XG------- * STORE_LCL_VAR int V02 cse1
N016 ( 1, 1) [000055] ------------ t55 = LCL_VAR int V02 cse1 <l:$241, c:$280>
N018 ( 1, 1) [000062] ------------ t62 = LCL_VAR ref V03 cse2 <l:$140, c:$180>
N019 ( 1, 1) [000031] ------------ t31 = CNS_INT long 14 field offset Fseq[F0] $1c1
/--* t62 ref
+--* t31 long
N020 ( 2, 2) [000032] ----G--N---- t32 = * ADD byref <l:$203, c:$202>
/--* t32 byref
N021 ( 5, 5) [000004] ---XG------- t4 = * IND byte <l:$2c1, c:$300>
/--* t55 int
+--* t4 byte
N022 ( 20, 24) [000005] ---XG------- t5 = * LT int <l:$341, c:$340>
/--* t5 int
N024 ( 20, 24) [000047] DA-XG------- * STORE_LCL_VAR int V01 cse0
N026 ( 1, 1) [000050] ------------ t50 = LCL_VAR int V01 cse0 <l:$341, c:$340>
N028 ( 1, 1) [000014] ------------ t14 = CNS_INT int 0 $82
/--* t50 int
+--* t14 int
N029 ( 27, 31) [000015] J--XG--N---- t15 = * EQ int <l:$347, c:$346>
/--* t15 int
N030 ( 29, 33) [000016] ---XG------- * JTRUE void
------------ BB02 [032..046), preds={BB01} succs={BB03}
( 7, 7) [000027] ------------ IL_OFFSET void IL offset: 0x32
N001 ( 1, 1) [000064] ------------ t64 = LCL_VAR ref V03 cse2 <l:$140, c:$180>
N002 ( 1, 1) [000040] ------------ t40 = CNS_INT long 12 field offset Fseq[F7] $1c0
/--* t64 ref
+--* t40 long
N003 ( 2, 2) [000041] ----G--N---- t41 = * ADD byref <l:$201, c:$207>
N005 ( 1, 1) [000057] ------------ t57 = LCL_VAR int V02 cse1 <l:$241, c:$280>
/--* t41 byref
+--* t57 int
[000065] -A-XG------- * STOREIND ushort
------------ BB03 [046..047) (return), preds={BB01,BB02} succs={}
( 0, 0) [000020] ------------ IL_OFFSET void IL offset: 0x46
N001 ( 0, 0) [000019] ------------ RETURN void $440
-------------------------------------------------------------------------------------------------------------------
Addressing mode:
Base
N001 ( 1, 1) [000063] ------------ * LCL_VAR ref V03 cse2 <l:$140, c:$180>
+ 8
New addressing mode node:
[000066] ------------ * LEA(b+8) byref
No addressing mode:
N005 ( 3, 10) [000030] ------------ * CNS_INT(h) long 0x1c4f1e92978 static Fseq[s_1] $100
Addressing mode:
Base
N009 ( 1, 1) [000060] ------------ * LCL_VAR ref V03 cse2 <l:$140, c:$180>
+ 12
New addressing mode node:
[000067] ------------ * LEA(b+12) byref
Addressing mode:
Base
N018 ( 1, 1) [000062] ------------ * LCL_VAR ref V03 cse2 <l:$140, c:$180>
+ 14
New addressing mode node:
[000068] ------------ * LEA(b+14) byref
Addressing mode:
Base
N001 ( 1, 1) [000064] ------------ * LCL_VAR ref V03 cse2 <l:$140, c:$180>
+ 12
New addressing mode node:
[000069] ------------ * LEA(b+12) byref
Lower of StoreInd didn't mark the node as self contained for reason: 4
N001 ( 1, 1) [000064] ------------ t64 = LCL_VAR ref V03 cse2 <l:$140, c:$180>
/--* t64 ref
[000069] ------------ t69 = * LEA(b+12) byref
N005 ( 1, 1) [000057] ------------ t57 = LCL_VAR int V02 cse1 <l:$241, c:$280>
/--* t69 byref
+--* t57 int
[000065] -A-XG------- * STOREIND ushort
lowering GT_RETURN
N001 ( 0, 0) [000019] ------------ * RETURN void $440
============Lower has completed modifying nodes.
--------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
--------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..032)-> BB03 ( cond ) i label target LIR
BB02 [0001] 1 BB01 0.50 [032..046) i LIR
BB03 [0002] 2 BB01,BB02 1 [046..047) (return) i label target LIR
--------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [000..032) -> BB03 (cond), preds={} succs={BB02,BB03}
( 29, 33) [000017] ------------ IL_OFFSET void IL offset: 0x0
N001 ( 1, 1) [000063] ------------ t63 = LCL_VAR ref V03 cse2 <l:$140, c:$180>
/--* t63 ref
[000066] -c---------- t66 = * LEA(b+8) byref
/--* t66 byref
N004 ( 4, 4) [000007] ---XG------- t7 = * IND int <l:$343, c:$380>
N005 ( 3, 10) [000030] ------------ t30 = CNS_INT(h) long 0x1c4f1e92978 static Fseq[s_1] $100
/--* t30 long
N006 ( 5, 12) [000001] x---G------- t1 = * IND ref <l:$140, c:$180>
/--* t1 ref
N008 ( 5, 12) [000059] DA--G------- * STORE_LCL_VAR ref V03 cse2
N009 ( 1, 1) [000060] ------------ t60 = LCL_VAR ref V03 cse2 <l:$140, c:$180>
/--* t60 ref
[000067] -c---------- t67 = * LEA(b+12) byref
/--* t67 byref
N013 ( 10, 17) [000002] ---XG------- t2 = * IND ushort <l:$241, c:$280>
/--* t2 ushort
N015 ( 10, 17) [000054] DA-XG------- * STORE_LCL_VAR int V02 cse1
N016 ( 1, 1) [000055] ------------ t55 = LCL_VAR int V02 cse1 <l:$241, c:$280>
N018 ( 1, 1) [000062] ------------ t62 = LCL_VAR ref V03 cse2 <l:$140, c:$180>
/--* t62 ref
[000068] -c---------- t68 = * LEA(b+14) byref
/--* t68 byref
N021 ( 5, 5) [000004] ---XG------- t4 = * IND byte <l:$2c1, c:$300>
/--* t55 int
+--* t4 byte
N022 ( 20, 24) [000005] ---XG------- t5 = * LT int <l:$341, c:$340>
/--* t5 int
N024 ( 20, 24) [000047] DA-XG------- * STORE_LCL_VAR int V01 cse0
N026 ( 1, 1) [000050] ------------ t50 = LCL_VAR int V01 cse0 <l:$341, c:$340>
N028 ( 1, 1) [000014] -c---------- t14 = CNS_INT int 0 $82
/--* t50 int
+--* t14 int
N029 ( 27, 31) [000015] J--XG--N---- * EQ void <l:$347, c:$346>
N030 ( 29, 33) [000016] ---XG------- * JTRUE void
------------ BB02 [032..046), preds={BB01} succs={BB03}
( 7, 7) [000027] ------------ IL_OFFSET void IL offset: 0x32
N001 ( 1, 1) [000064] ------------ t64 = LCL_VAR ref V03 cse2 <l:$140, c:$180>
/--* t64 ref
[000069] -c---------- t69 = * LEA(b+12) byref
N005 ( 1, 1) [000057] ------------ t57 = LCL_VAR int V02 cse1 <l:$241, c:$280>
/--* t69 byref
+--* t57 int
[000065] -A-XG------- * STOREIND ushort
------------ BB03 [046..047) (return), preds={BB01,BB02} succs={}
( 0, 0) [000020] ------------ IL_OFFSET void IL offset: 0x46
N001 ( 0, 0) [000019] ------------ RETURN void $440
-------------------------------------------------------------------------------------------------------------------
*************** In fgLocalVarLiveness()
; Initial local variable assignments
;
; V00 OutArgs lclBlk ( 0)
; V01 cse0 int
; V02 cse1 int
; V03 cse2 ref
In fgLocalVarLivenessInit, sorting locals
refCnt table for 'M0':
V03 cse2 [ ref]: refCnt = 15, refCntWtd = 14
V01 cse0 [ int]: refCnt = 14, refCntWtd = 14
V02 cse1 [ int]: refCnt = 13, refCntWtd = 11.50
V00 OutArgs [lclBlk]: refCnt = 1, refCntWtd = 1
*************** In fgPerBlockLocalVarLiveness()
BB01 USE(1)={V03 } + ByrefExposed + GcHeap
DEF(3)={V03 V01 V02}
BB02 USE(2)={V03 V02}
DEF(0)={ }
BB03 USE(0)={}
DEF(0)={}
** Memory liveness computed, GcHeap states and ByrefExposed states match
*************** In fgInterBlockLocalVarLiveness()
BB liveness after fgLiveVarAnalysis():
BB01 IN (1)={V03 } + ByrefExposed + GcHeap
OUT(2)={V03 V02}
BB02 IN (2)={V03 V02}
OUT(0)={ }
BB03 IN (0)={}
OUT(0)={}
*************** In fgUpdateFlowGraph()
Before updating the flow graph:
--------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
--------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..032)-> BB03 ( cond ) i label target LIR
BB02 [0001] 1 BB01 0.50 [032..046) i LIR
BB03 [0002] 2 BB01,BB02 1 [046..047) (return) i label target LIR
--------------------------------------------------------------------------------------------------------------------------------------
*************** In fgDebugCheckBBlist
Liveness pass finished after lowering, IR:
lvasortagain = 0
--------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
--------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..032)-> BB03 ( cond ) i label target LIR
BB02 [0001] 1 BB01 0.50 [032..046) i LIR
BB03 [0002] 2 BB01,BB02 1 [046..047) (return) i label target LIR
--------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [000..032) -> BB03 (cond), preds={} succs={BB02,BB03}
( 29, 33) [000017] ------------ IL_OFFSET void IL offset: 0x0
N001 ( 1, 1) [000063] ------------ t63 = LCL_VAR ref V03 cse2 (last use) <l:$140, c:$180>
/--* t63 ref
[000066] -c---------- t66 = * LEA(b+8) byref
/--* t66 byref
N004 ( 4, 4) [000007] ---XG------- t7 = * IND int <l:$343, c:$380>
N005 ( 3, 10) [000030] ------------ t30 = CNS_INT(h) long 0x1c4f1e92978 static Fseq[s_1] $100
/--* t30 long
N006 ( 5, 12) [000001] x---G------- t1 = * IND ref <l:$140, c:$180>
/--* t1 ref
N008 ( 5, 12) [000059] DA--G------- * STORE_LCL_VAR ref V03 cse2
N009 ( 1, 1) [000060] ------------ t60 = LCL_VAR ref V03 cse2 <l:$140, c:$180>
/--* t60 ref
[000067] -c---------- t67 = * LEA(b+12) byref
/--* t67 byref
N013 ( 10, 17) [000002] ---XG------- t2 = * IND ushort <l:$241, c:$280>
/--* t2 ushort
N015 ( 10, 17) [000054] DA-XG------- * STORE_LCL_VAR int V02 cse1
N016 ( 1, 1) [000055] ------------ t55 = LCL_VAR int V02 cse1 <l:$241, c:$280>
N018 ( 1, 1) [000062] ------------ t62 = LCL_VAR ref V03 cse2 <l:$140, c:$180>
/--* t62 ref
[000068] -c---------- t68 = * LEA(b+14) byref
/--* t68 byref
N021 ( 5, 5) [000004] ---XG------- t4 = * IND byte <l:$2c1, c:$300>
/--* t55 int
+--* t4 byte
N022 ( 20, 24) [000005] ---XG------- t5 = * LT int <l:$341, c:$340>
/--* t5 int
N024 ( 20, 24) [000047] DA-XG------- * STORE_LCL_VAR int V01 cse0
N026 ( 1, 1) [000050] ------------ t50 = LCL_VAR int V01 cse0 (last use) <l:$341, c:$340>
N028 ( 1, 1) [000014] -c---------- t14 = CNS_INT int 0 $82
/--* t50 int
+--* t14 int
N029 ( 27, 31) [000015] J--XG--N---- * EQ void <l:$347, c:$346>
N030 ( 29, 33) [000016] ---XG------- * JTRUE void
------------ BB02 [032..046), preds={BB01} succs={BB03}
( 7, 7) [000027] ------------ IL_OFFSET void IL offset: 0x32
N001 ( 1, 1) [000064] ------------ t64 = LCL_VAR ref V03 cse2 (last use) <l:$140, c:$180>
/--* t64 ref
[000069] -c---------- t69 = * LEA(b+12) byref
N005 ( 1, 1) [000057] ------------ t57 = LCL_VAR int V02 cse1 (last use) <l:$241, c:$280>
/--* t69 byref
+--* t57 int
[000065] -A-XG------- * STOREIND ushort
------------ BB03 [046..047) (return), preds={BB01,BB02} succs={}
( 0, 0) [000020] ------------ IL_OFFSET void IL offset: 0x46
N001 ( 0, 0) [000019] ------------ RETURN void $440
-------------------------------------------------------------------------------------------------------------------
*************** Exiting Lowering
Trees after Lowering
--------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
--------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..032)-> BB03 ( cond ) i label target LIR
BB02 [0001] 1 BB01 0.50 [032..046) i LIR
BB03 [0002] 2 BB01,BB02 1 [046..047) (return) i label target LIR
--------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [000..032) -> BB03 (cond), preds={} succs={BB02,BB03}
( 29, 33) [000017] ------------ IL_OFFSET void IL offset: 0x0
N001 ( 1, 1) [000063] ------------ t63 = LCL_VAR ref V03 cse2 (last use) <l:$140, c:$180>
/--* t63 ref
[000066] -c---------- t66 = * LEA(b+8) byref
/--* t66 byref
N004 ( 4, 4) [000007] ---XG------- t7 = * IND int <l:$343, c:$380>
N005 ( 3, 10) [000030] ------------ t30 = CNS_INT(h) long 0x1c4f1e92978 static Fseq[s_1] $100
/--* t30 long
N006 ( 5, 12) [000001] x---G------- t1 = * IND ref <l:$140, c:$180>
/--* t1 ref
N008 ( 5, 12) [000059] DA--G------- * STORE_LCL_VAR ref V03 cse2
N009 ( 1, 1) [000060] ------------ t60 = LCL_VAR ref V03 cse2 <l:$140, c:$180>
/--* t60 ref
[000067] -c---------- t67 = * LEA(b+12) byref
/--* t67 byref
N013 ( 10, 17) [000002] ---XG------- t2 = * IND ushort <l:$241, c:$280>
/--* t2 ushort
N015 ( 10, 17) [000054] DA-XG------- * STORE_LCL_VAR int V02 cse1
N016 ( 1, 1) [000055] ------------ t55 = LCL_VAR int V02 cse1 <l:$241, c:$280>
N018 ( 1, 1) [000062] ------------ t62 = LCL_VAR ref V03 cse2 <l:$140, c:$180>
/--* t62 ref
[000068] -c---------- t68 = * LEA(b+14) byref
/--* t68 byref
N021 ( 5, 5) [000004] ---XG------- t4 = * IND byte <l:$2c1, c:$300>
/--* t55 int
+--* t4 byte
N022 ( 20, 24) [000005] ---XG------- t5 = * LT int <l:$341, c:$340>
/--* t5 int
N024 ( 20, 24) [000047] DA-XG------- * STORE_LCL_VAR int V01 cse0
N026 ( 1, 1) [000050] ------------ t50 = LCL_VAR int V01 cse0 (last use) <l:$341, c:$340>
N028 ( 1, 1) [000014] -c---------- t14 = CNS_INT int 0 $82
/--* t50 int
+--* t14 int
N029 ( 27, 31) [000015] J--XG--N---- * EQ void <l:$347, c:$346>
N030 ( 29, 33) [000016] ---XG------- * JTRUE void
------------ BB02 [032..046), preds={BB01} succs={BB03}
( 7, 7) [000027] ------------ IL_OFFSET void IL offset: 0x32
N001 ( 1, 1) [000064] ------------ t64 = LCL_VAR ref V03 cse2 (last use) <l:$140, c:$180>
/--* t64 ref
[000069] -c---------- t69 = * LEA(b+12) byref
N005 ( 1, 1) [000057] ------------ t57 = LCL_VAR int V02 cse1 (last use) <l:$241, c:$280>
/--* t69 byref
+--* t57 int
[000065] -A-XG------- * STOREIND ushort
------------ BB03 [046..047) (return), preds={BB01,BB02} succs={}
( 0, 0) [000020] ------------ IL_OFFSET void IL offset: 0x46
N001 ( 0, 0) [000019] ------------ RETURN void $440
-------------------------------------------------------------------------------------------------------------------
*************** In fgDebugCheckBBlist
*************** In StackLevelSetter
Trees before StackLevelSetter
--------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
--------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..032)-> BB03 ( cond ) i label target LIR
BB02 [0001] 1 BB01 0.50 [032..046) i LIR
BB03 [0002] 2 BB01,BB02 1 [046..047) (return) i label target LIR
--------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [000..032) -> BB03 (cond), preds={} succs={BB02,BB03}
( 29, 33) [000017] ------------ IL_OFFSET void IL offset: 0x0
N001 ( 1, 1) [000063] ------------ t63 = LCL_VAR ref V03 cse2 (last use) <l:$140, c:$180>
/--* t63 ref
[000066] -c---------- t66 = * LEA(b+8) byref
/--* t66 byref
N004 ( 4, 4) [000007] ---XG------- t7 = * IND int <l:$343, c:$380>
N005 ( 3, 10) [000030] ------------ t30 = CNS_INT(h) long 0x1c4f1e92978 static Fseq[s_1] $100
/--* t30 long
N006 ( 5, 12) [000001] x---G------- t1 = * IND ref <l:$140, c:$180>
/--* t1 ref
N008 ( 5, 12) [000059] DA--G------- * STORE_LCL_VAR ref V03 cse2
N009 ( 1, 1) [000060] ------------ t60 = LCL_VAR ref V03 cse2 <l:$140, c:$180>
/--* t60 ref
[000067] -c---------- t67 = * LEA(b+12) byref
/--* t67 byref
N013 ( 10, 17) [000002] ---XG------- t2 = * IND ushort <l:$241, c:$280>
/--* t2 ushort
N015 ( 10, 17) [000054] DA-XG------- * STORE_LCL_VAR int V02 cse1
N016 ( 1, 1) [000055] ------------ t55 = LCL_VAR int V02 cse1 <l:$241, c:$280>
N018 ( 1, 1) [000062] ------------ t62 = LCL_VAR ref V03 cse2 <l:$140, c:$180>
/--* t62 ref
[000068] -c---------- t68 = * LEA(b+14) byref
/--* t68 byref
N021 ( 5, 5) [000004] ---XG------- t4 = * IND byte <l:$2c1, c:$300>
/--* t55 int
+--* t4 byte
N022 ( 20, 24) [000005] ---XG------- t5 = * LT int <l:$341, c:$340>
/--* t5 int
N024 ( 20, 24) [000047] DA-XG------- * STORE_LCL_VAR int V01 cse0
N026 ( 1, 1) [000050] ------------ t50 = LCL_VAR int V01 cse0 (last use) <l:$341, c:$340>
N028 ( 1, 1) [000014] -c---------- t14 = CNS_INT int 0 $82
/--* t50 int
+--* t14 int
N029 ( 27, 31) [000015] J--XG--N---- * EQ void <l:$347, c:$346>
N030 ( 29, 33) [000016] ---XG------- * JTRUE void
------------ BB02 [032..046), preds={BB01} succs={BB03}
( 7, 7) [000027] ------------ IL_OFFSET void IL offset: 0x32
N001 ( 1, 1) [000064] ------------ t64 = LCL_VAR ref V03 cse2 (last use) <l:$140, c:$180>
/--* t64 ref
[000069] -c---------- t69 = * LEA(b+12) byref
N005 ( 1, 1) [000057] ------------ t57 = LCL_VAR int V02 cse1 (last use) <l:$241, c:$280>
/--* t69 byref
+--* t57 int
[000065] -A-XG------- * STOREIND ushort
------------ BB03 [046..047) (return), preds={BB01,BB02} succs={}
( 0, 0) [000020] ------------ IL_OFFSET void IL offset: 0x46
N001 ( 0, 0) [000019] ------------ RETURN void $440
-------------------------------------------------------------------------------------------------------------------
*************** Exiting StackLevelSetter
Trees after StackLevelSetter
--------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
--------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..032)-> BB03 ( cond ) i label target LIR
BB02 [0001] 1 BB01 0.50 [032..046) i LIR
BB03 [0002] 2 BB01,BB02 1 [046..047) (return) i label target LIR
--------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [000..032) -> BB03 (cond), preds={} succs={BB02,BB03}
( 29, 33) [000017] ------------ IL_OFFSET void IL offset: 0x0
N001 ( 1, 1) [000063] ------------ t63 = LCL_VAR ref V03 cse2 (last use) <l:$140, c:$180>
/--* t63 ref
[000066] -c---------- t66 = * LEA(b+8) byref
/--* t66 byref
N004 ( 4, 4) [000007] ---XG------- t7 = * IND int <l:$343, c:$380>
N005 ( 3, 10) [000030] ------------ t30 = CNS_INT(h) long 0x1c4f1e92978 static Fseq[s_1] $100
/--* t30 long
N006 ( 5, 12) [000001] x---G------- t1 = * IND ref <l:$140, c:$180>
/--* t1 ref
N008 ( 5, 12) [000059] DA--G------- * STORE_LCL_VAR ref V03 cse2
N009 ( 1, 1) [000060] ------------ t60 = LCL_VAR ref V03 cse2 <l:$140, c:$180>
/--* t60 ref
[000067] -c---------- t67 = * LEA(b+12) byref
/--* t67 byref
N013 ( 10, 17) [000002] ---XG------- t2 = * IND ushort <l:$241, c:$280>
/--* t2 ushort
N015 ( 10, 17) [000054] DA-XG------- * STORE_LCL_VAR int V02 cse1
N016 ( 1, 1) [000055] ------------ t55 = LCL_VAR int V02 cse1 <l:$241, c:$280>
N018 ( 1, 1) [000062] ------------ t62 = LCL_VAR ref V03 cse2 <l:$140, c:$180>
/--* t62 ref
[000068] -c---------- t68 = * LEA(b+14) byref
/--* t68 byref
N021 ( 5, 5) [000004] ---XG------- t4 = * IND byte <l:$2c1, c:$300>
/--* t55 int
+--* t4 byte
N022 ( 20, 24) [000005] ---XG------- t5 = * LT int <l:$341, c:$340>
/--* t5 int
N024 ( 20, 24) [000047] DA-XG------- * STORE_LCL_VAR int V01 cse0
N026 ( 1, 1) [000050] ------------ t50 = LCL_VAR int V01 cse0 (last use) <l:$341, c:$340>
N028 ( 1, 1) [000014] -c---------- t14 = CNS_INT int 0 $82
/--* t50 int
+--* t14 int
N029 ( 27, 31) [000015] J--XG--N---- * EQ void <l:$347, c:$346>
N030 ( 29, 33) [000016] ---XG------- * JTRUE void
------------ BB02 [032..046), preds={BB01} succs={BB03}
( 7, 7) [000027] ------------ IL_OFFSET void IL offset: 0x32
N001 ( 1, 1) [000064] ------------ t64 = LCL_VAR ref V03 cse2 (last use) <l:$140, c:$180>
/--* t64 ref
[000069] -c---------- t69 = * LEA(b+12) byref
N005 ( 1, 1) [000057] ------------ t57 = LCL_VAR int V02 cse1 (last use) <l:$241, c:$280>
/--* t69 byref
+--* t57 int
[000065] -A-XG------- * STOREIND ushort
------------ BB03 [046..047) (return), preds={BB01,BB02} succs={}
( 0, 0) [000020] ------------ IL_OFFSET void IL offset: 0x46
N001 ( 0, 0) [000019] ------------ RETURN void $440
-------------------------------------------------------------------------------------------------------------------
*************** In fgDebugCheckBBlist
Clearing modified regs.
buildIntervals ========
-----------------
LIVENESS:
-----------------
BB01 use def in out
{V03}
{V01 V02 V03}
{V03}
{V02 V03}
BB02 use def in out
{V02 V03}
{}
{V02 V03}
{}
BB03 use def in out
{}
{}
{}
{}
Interval 0: RefPositions {} physReg:NA Preferences=[allInt]
Interval 1: RefPositions {} physReg:NA Preferences=[allInt]
Interval 2: RefPositions {} physReg:NA Preferences=[allInt]
FP callee save candidate vars: None
floatVarCount = 0; hasLoops = 0, singleExit = 1
TUPLE STYLE DUMP BEFORE LSRA
LSRA Block Sequence: BB01( 1 ) BB02( 0.50) BB03( 1 )
BB01 [000..032) -> BB03 (cond), preds={} succs={BB02,BB03}
=====
N000. IL_OFFSET IL offset: 0x0
N001. V03(t63*)
N000. t66 = LEA(b+8) ; t63*
N004. IND ; t66
N005. t30* = CNS_INT(h) 0x1c4f1e92978 static Fseq[s_1]
N006. t1 = IND ; t30*
N008. V03(t59); t1
N009. V03(t60)
N000. t67 = LEA(b+12); t60
N013. t2 = IND ; t67
N015. V02(t54); t2
N016. V02(t55)
N018. V03(t62)
N000. t68 = LEA(b+14); t62
N021. t4 = IND ; t68
N022. t5 = LT ; t55,t4
N024. V01(t47); t5
N026. V01(t50*)
N028. CNS_INT 0
N029. EQ ; t50*
N030. JTRUE
BB02 [032..046), preds={BB01} succs={BB03}
=====
N000. IL_OFFSET IL offset: 0x32
N001. V03(t64*)
N000. t69 = LEA(b+12); t64*
N005. V02(t57*)
N000. STOREIND ; t69,t57*
BB03 [046..047) (return), preds={BB01,BB02} succs={}
=====
N000. IL_OFFSET IL offset: 0x46
N001. RETURN
buildIntervals second part ========
NEW BLOCK BB01
V03 was live in to first block: creating ZeroInit
<RefPosition #0 @0 RefTypeZeroInit <Ivl:2 V03> IL_OFFSET BB01 regmask=[allInt] minReg=1>
<RefPosition #1 @1 RefTypeBB BB01 regmask=[] minReg=1>
DefList: { }
N003 ( 29, 33) [000017] ------------ * IL_OFFSET void IL offset: 0x0 REG NA
+<TreeNodeInfo 0=0 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 0 produce=0
DefList: { }
N005 ( 1, 1) [000063] ------------ * LCL_VAR ref V03 cse2 NA (last use) REG NA <l:$140, c:$180>
+<TreeNodeInfo 1=0 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 0 produce=1
DefList: { }
N007 (???,???) [000066] -c---------- * LEA(b+8) byref REG NA
Contained
DefList: { }
N009 ( 4, 4) [000007] ---XG------- * IND int REG NA <l:$343, c:$380>
<RefPosition #2 @9 RefTypeUse <Ivl:2 V03> LCL_VAR BB01 regmask=[allInt] minReg=1 last>
Interval 3: RefPositions {} physReg:NA Preferences=[allInt]
<RefPosition #3 @10 RefTypeDef <Ivl:3> IND BB01 regmask=[allInt] minReg=1>
+<TreeNodeInfo 1=1 0i 0f src=[allInt] int=[allInt] dst=[allInt] L I>[U-]
consume= 1 produce=1
DefList: { }
N011 ( 3, 10) [000030] ------------ * CNS_INT(h) long 0x1c4f1e92978 static Fseq[s_1] REG NA $100
Interval 4: RefPositions {} physReg:NA Preferences=[allInt]
<RefPosition #4 @12 RefTypeDef <Ivl:4> CNS_INT BB01 regmask=[allInt] minReg=1>
+<TreeNodeInfo 1=0 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 0 produce=1
DefList: { N011.t30. CNS_INT }
N013 ( 5, 12) [000001] x---G------- * IND ref REG NA <l:$140, c:$180>
<RefPosition #5 @13 RefTypeUse <Ivl:4> BB01 regmask=[allInt] minReg=1 last>
Interval 5: RefPositions {} physReg:NA Preferences=[allInt]
<RefPosition #6 @14 RefTypeDef <Ivl:5> IND BB01 regmask=[allInt] minReg=1>
+<TreeNodeInfo 1=1 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 1 produce=1
DefList: { N013.t1. IND }
N015 ( 5, 12) [000059] DA--G------- * STORE_LCL_VAR ref V03 cse2 NA REG NA
<RefPosition #7 @15 RefTypeUse <Ivl:5> BB01 regmask=[allInt] minReg=1 last>
Assigning related <L2> to <I5>
<RefPosition #8 @16 RefTypeDef <Ivl:2 V03> STORE_LCL_VAR BB01 regmask=[allInt] minReg=1 last>
+<TreeNodeInfo 0=1 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 1 produce=0
DefList: { }
N017 ( 1, 1) [000060] ------------ * LCL_VAR ref V03 cse2 NA REG NA <l:$140, c:$180>
+<TreeNodeInfo 1=0 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 0 produce=1
DefList: { }
N019 (???,???) [000067] -c---------- * LEA(b+12) byref REG NA
Contained
DefList: { }
N021 ( 10, 17) [000002] ---XG------- * IND ushort REG NA <l:$241, c:$280>
<RefPosition #9 @21 RefTypeUse <Ivl:2 V03> LCL_VAR BB01 regmask=[allInt] minReg=1 last>
Interval 6: RefPositions {} physReg:NA Preferences=[allInt]
<RefPosition #10 @22 RefTypeDef <Ivl:6> IND BB01 regmask=[allInt] minReg=1>
+<TreeNodeInfo 1=1 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 1 produce=1
DefList: { N021.t2. IND }
N023 ( 10, 17) [000054] DA-XG------- * STORE_LCL_VAR int V02 cse1 NA REG NA
<RefPosition #11 @23 RefTypeUse <Ivl:6> BB01 regmask=[allInt] minReg=1 last>
Assigning related <L1> to <I6>
<RefPosition #12 @24 RefTypeDef <Ivl:1 V02> STORE_LCL_VAR BB01 regmask=[allInt] minReg=1 last>
+<TreeNodeInfo 0=1 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 1 produce=0
DefList: { }
N025 ( 1, 1) [000055] ------------ * LCL_VAR int V02 cse1 NA REG NA <l:$241, c:$280>
+<TreeNodeInfo 1=0 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 0 produce=1
DefList: { }
N027 ( 1, 1) [000062] ------------ * LCL_VAR ref V03 cse2 NA REG NA <l:$140, c:$180>
+<TreeNodeInfo 1=0 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 0 produce=1
DefList: { }
N029 (???,???) [000068] -c---------- * LEA(b+14) byref REG NA
Contained
DefList: { }
N031 ( 5, 5) [000004] ---XG------- * IND byte REG NA <l:$2c1, c:$300>
<RefPosition #13 @31 RefTypeUse <Ivl:2 V03> LCL_VAR BB01 regmask=[allInt] minReg=1 last>
Interval 7: RefPositions {} physReg:NA Preferences=[allInt]
<RefPosition #14 @32 RefTypeDef <Ivl:7> IND BB01 regmask=[allInt] minReg=1>
+<TreeNodeInfo 1=1 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 1 produce=1
DefList: { N031.t4. IND }
N033 ( 20, 24) [000005] ---XG------- * LT int REG NA <l:$341, c:$340>
<RefPosition #15 @33 RefTypeUse <Ivl:1 V02> LCL_VAR BB01 regmask=[allInt] minReg=1 last>
<RefPosition #16 @33 RefTypeUse <Ivl:7> BB01 regmask=[allInt] minReg=1 last>
Interval 8: RefPositions {} physReg:NA Preferences=[allInt]
<RefPosition #17 @34 RefTypeDef <Ivl:8> LT BB01 regmask=[allInt] minReg=1>
+<TreeNodeInfo 1=2 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 2 produce=1
DefList: { N033.t5. LT }
N035 ( 20, 24) [000047] DA-XG------- * STORE_LCL_VAR int V01 cse0 NA REG NA
<RefPosition #18 @35 RefTypeUse <Ivl:8> BB01 regmask=[allInt] minReg=1 last>
Assigning related <L0> to <I8>
<RefPosition #19 @36 RefTypeDef <Ivl:0 V01> STORE_LCL_VAR BB01 regmask=[allInt] minReg=1 last>
+<TreeNodeInfo 0=1 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 1 produce=0
DefList: { }
N037 ( 1, 1) [000050] ------------ * LCL_VAR int V01 cse0 NA (last use) REG NA <l:$341, c:$340>
+<TreeNodeInfo 1=0 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[-O]
consume= 0 produce=1
DefList: { }
N039 ( 1, 1) [000014] -c---------- * CNS_INT int 0 REG NA $82
Contained
DefList: { }
N041 ( 27, 31) [000015] J--XG--N---- * EQ void REG NA <l:$347, c:$346>
<RefPosition #20 @41 RefTypeUse <Ivl:0 V01> LCL_VAR BB01 regmask=[allInt] minReg=1 last>
+<TreeNodeInfo 0=1 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 1 produce=0
DefList: { }
N043 ( 29, 33) [000016] ---XG------- * JTRUE void REG NA
+<TreeNodeInfo 0=0 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 0 produce=0
CHECKING LAST USES for block 1, liveout={V02 V03}
==============================
use: {V03}
def: {V01 V02 V03}
NEW BLOCK BB02
Setting BB02 as the predecessor for determining incoming variable registers of BB01
<RefPosition #21 @45 RefTypeBB BB02 regmask=[] minReg=1>
DefList: { }
N047 ( 7, 7) [000027] ------------ * IL_OFFSET void IL offset: 0x32 REG NA
+<TreeNodeInfo 0=0 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 0 produce=0
DefList: { }
N049 ( 1, 1) [000064] ------------ * LCL_VAR ref V03 cse2 NA (last use) REG NA <l:$140, c:$180>
+<TreeNodeInfo 1=0 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 0 produce=1
DefList: { }
N051 (???,???) [000069] -c---------- * LEA(b+12) byref REG NA
Contained
DefList: { }
N053 ( 1, 1) [000057] ------------ * LCL_VAR int V02 cse1 NA (last use) REG NA <l:$241, c:$280>
+<TreeNodeInfo 1=0 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 0 produce=1
DefList: { }
N055 (???,???) [000065] -A-XG------- * STOREIND ushort REG NA
<RefPosition #22 @55 RefTypeUse <Ivl:2 V03> LCL_VAR BB02 regmask=[allInt] minReg=1 last>
<RefPosition #23 @55 RefTypeUse <Ivl:1 V02> LCL_VAR BB02 regmask=[allInt] minReg=1 last>
+<TreeNodeInfo 0=2 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 2 produce=0
CHECKING LAST USES for block 2, liveout={}
==============================
use: {V02 V03}
def: {}
NEW BLOCK BB03
Setting BB03 as the predecessor for determining incoming variable registers of BB01
<RefPosition #24 @57 RefTypeBB BB03 regmask=[] minReg=1>
DefList: { }
N059 ( 0, 0) [000020] ------------ * IL_OFFSET void IL offset: 0x46 REG NA
+<TreeNodeInfo 0=0 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 0 produce=0
DefList: { }
N061 ( 0, 0) [000019] ------------ * RETURN void REG NA $440
+<TreeNodeInfo 0=0 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 0 produce=0
CHECKING LAST USES for block 3, liveout={}
==============================
use: {}
def: {}
Linear scan intervals BEFORE VALIDATING INTERVALS:
Interval 0: (V01) RefPositions {#19@36 #20@41} physReg:NA Preferences=[allInt]
Interval 1: (V02) RefPositions {#12@24 #15@33 #23@55} physReg:NA Preferences=[allInt]
Interval 2: (V03) RefPositions {#0@0 #2@9 #8@16 #9@21 #13@31 #22@55} physReg:NA Preferences=[allInt]
Interval 3: RefPositions {#3@10} physReg:NA Preferences=[allInt]
Interval 4: (constant) RefPositions {#4@12 #5@13} physReg:NA Preferences=[allInt]
Interval 5: RefPositions {#6@14 #7@15} physReg:NA Preferences=[allInt] RelatedInterval <L2>[000001C4DFDD1E80]
Interval 6: RefPositions {#10@22 #11@23} physReg:NA Preferences=[allInt] RelatedInterval <L1>[000001C4DFDD1E28]
Interval 7: RefPositions {#14@32 #16@33} physReg:NA Preferences=[allInt]
Interval 8: RefPositions {#17@34 #18@35} physReg:NA Preferences=[allInt] RelatedInterval <L0>[000001C4DFDD1DD0]
------------
REFPOSITIONS BEFORE VALIDATING INTERVALS:
------------
<RefPosition #0 @0 RefTypeZeroInit <Ivl:2 V03> IL_OFFSET BB01 regmask=[allInt] minReg=1>
<RefPosition #1 @1 RefTypeBB BB01 regmask=[] minReg=1>
<RefPosition #2 @9 RefTypeUse <Ivl:2 V03> LCL_VAR BB01 regmask=[allInt] minReg=1 last>
<RefPosition #3 @10 RefTypeDef <Ivl:3> IND BB01 regmask=[allInt] minReg=1 last local>
<RefPosition #4 @12 RefTypeDef <Ivl:4> CNS_INT BB01 regmask=[allInt] minReg=1>
<RefPosition #5 @13 RefTypeUse <Ivl:4> BB01 regmask=[allInt] minReg=1 last>
<RefPosition #6 @14 RefTypeDef <Ivl:5> IND BB01 regmask=[allInt] minReg=1>
<RefPosition #7 @15 RefTypeUse <Ivl:5> BB01 regmask=[allInt] minReg=1 last>
<RefPosition #8 @16 RefTypeDef <Ivl:2 V03> STORE_LCL_VAR BB01 regmask=[allInt] minReg=1>
<RefPosition #9 @21 RefTypeUse <Ivl:2 V03> LCL_VAR BB01 regmask=[allInt] minReg=1>
<RefPosition #10 @22 RefTypeDef <Ivl:6> IND BB01 regmask=[allInt] minReg=1>
<RefPosition #11 @23 RefTypeUse <Ivl:6> BB01 regmask=[allInt] minReg=1 last>
<RefPosition #12 @24 RefTypeDef <Ivl:1 V02> STORE_LCL_VAR BB01 regmask=[allInt] minReg=1>
<RefPosition #13 @31 RefTypeUse <Ivl:2 V03> LCL_VAR BB01 regmask=[allInt] minReg=1>
<RefPosition #14 @32 RefTypeDef <Ivl:7> IND BB01 regmask=[allInt] minReg=1>
<RefPosition #15 @33 RefTypeUse <Ivl:1 V02> LCL_VAR BB01 regmask=[allInt] minReg=1>
<RefPosition #16 @33 RefTypeUse <Ivl:7> BB01 regmask=[allInt] minReg=1 last>
<RefPosition #17 @34 RefTypeDef <Ivl:8> LT BB01 regmask=[allInt] minReg=1>
<RefPosition #18 @35 RefTypeUse <Ivl:8> BB01 regmask=[allInt] minReg=1 last>
<RefPosition #19 @36 RefTypeDef <Ivl:0 V01> STORE_LCL_VAR BB01 regmask=[allInt] minReg=1>
<RefPosition #20 @41 RefTypeUse <Ivl:0 V01> LCL_VAR BB01 regmask=[allInt] minReg=1 last regOptional>
<RefPosition #21 @45 RefTypeBB BB02 regmask=[] minReg=1>
<RefPosition #22 @55 RefTypeUse <Ivl:2 V03> LCL_VAR BB02 regmask=[allInt] minReg=1 last>
<RefPosition #23 @55 RefTypeUse <Ivl:1 V02> LCL_VAR BB02 regmask=[allInt] minReg=1 last>
<RefPosition #24 @57 RefTypeBB BB03 regmask=[] minReg=1>
-----------------
<RefPosition #0 @0 RefTypeZeroInit <Ivl:2 V03> IL_OFFSET BB01 regmask=[allInt] minReg=1>
<RefPosition #2 @9 RefTypeUse <Ivl:2 V03> LCL_VAR BB01 regmask=[allInt] minReg=1 last>
<RefPosition #8 @16 RefTypeDef <Ivl:2 V03> STORE_LCL_VAR BB01 regmask=[allInt] minReg=1>
<RefPosition #9 @21 RefTypeUse <Ivl:2 V03> LCL_VAR BB01 regmask=[allInt] minReg=1>
<RefPosition #13 @31 RefTypeUse <Ivl:2 V03> LCL_VAR BB01 regmask=[allInt] minReg=1>
<RefPosition #22 @55 RefTypeUse <Ivl:2 V03> LCL_VAR BB02 regmask=[allInt] minReg=1 last>
-----------------
<RefPosition #19 @36 RefTypeDef <Ivl:0 V01> STORE_LCL_VAR BB01 regmask=[allInt] minReg=1>
<RefPosition #20 @41 RefTypeUse <Ivl:0 V01> LCL_VAR BB01 regmask=[allInt] minReg=1 last regOptional>
-----------------
<RefPosition #12 @24 RefTypeDef <Ivl:1 V02> STORE_LCL_VAR BB01 regmask=[allInt] minReg=1>
<RefPosition #15 @33 RefTypeUse <Ivl:1 V02> LCL_VAR BB01 regmask=[allInt] minReg=1>
<RefPosition #23 @55 RefTypeUse <Ivl:1 V02> LCL_VAR BB02 regmask=[allInt] minReg=1 last>
TUPLE STYLE DUMP WITH REF POSITIONS
Incoming Parameters: V03
BB01 [000..032) -> BB03 (cond), preds={} succs={BB02,BB03}
=====
N003. IL_OFFSET IL offset: 0x0 REG NA
N005. V03(L2)
N007. LEA(b+8)
N009. IND
Use:<L2>(#2) *
Def:<I3>(#3) LocalDefUse *
N011. CNS_INT(h) 0x1c4f1e92978 static Fseq[s_1] REG NA
Def:<I4>(#4)
N013. IND
Use:<I4>(#5) *
Def:<I5>(#6) Pref:<L2>
N015. V03(L2)
Use:<I5>(#7) *
Def:<L2>(#8)
N017. V03(L2)
N019. LEA(b+12)
N021. IND
Use:<L2>(#9)
Def:<I6>(#10) Pref:<L1>
N023. V02(L1)
Use:<I6>(#11) *
Def:<L1>(#12)
N025. V02(L1)
N027. V03(L2)
N029. LEA(b+14)
N031. IND
Use:<L2>(#13)
Def:<I7>(#14)
N033. LT
Use:<L1>(#15)
Use:<I7>(#16) *
Def:<I8>(#17) Pref:<L0>
N035. V01(L0)
Use:<I8>(#18) *
Def:<L0>(#19)
N037. V01(L0)
N039. CNS_INT 0 REG NA
N041. EQ
Use:<L0>(#20) *
N043. JTRUE
BB02 [032..046), preds={BB01} succs={BB03}
=====
N047. IL_OFFSET IL offset: 0x32 REG NA
N049. V03(L2)
N051. LEA(b+12)
N053. V02(L1)
N055. STOREIND
Use:<L2>(#22) *
Use:<L1>(#23) *
BB03 [046..047) (return), preds={BB01,BB02} succs={}
=====
N059. IL_OFFSET IL offset: 0x46 REG NA
N061. RETURN
Linear scan intervals after buildIntervals:
Interval 0: (V01) RefPositions {#19@36 #20@41} physReg:NA Preferences=[allInt]
Interval 1: (V02) RefPositions {#12@24 #15@33 #23@55} physReg:NA Preferences=[allInt]
Interval 2: (V03) RefPositions {#0@0 #2@9 #8@16 #9@21 #13@31 #22@55} physReg:NA Preferences=[allInt]
Interval 3: RefPositions {#3@10} physReg:NA Preferences=[allInt]
Interval 4: (constant) RefPositions {#4@12 #5@13} physReg:NA Preferences=[allInt]
Interval 5: RefPositions {#6@14 #7@15} physReg:NA Preferences=[allInt] RelatedInterval <L2>[000001C4DFDD1E80]
Interval 6: RefPositions {#10@22 #11@23} physReg:NA Preferences=[allInt] RelatedInterval <L1>[000001C4DFDD1E28]
Interval 7: RefPositions {#14@32 #16@33} physReg:NA Preferences=[allInt]
Interval 8: RefPositions {#17@34 #18@35} physReg:NA Preferences=[allInt] RelatedInterval <L0>[000001C4DFDD1DD0]
*************** In LinearScan::allocateRegisters()
Linear scan intervals before allocateRegisters:
Interval 0: (V01) RefPositions {#19@36 #20@41} physReg:NA Preferences=[allInt]
Interval 1: (V02) RefPositions {#12@24 #15@33 #23@55} physReg:NA Preferences=[allInt]
Interval 2: (V03) RefPositions {#0@0 #2@9 #8@16 #9@21 #13@31 #22@55} physReg:NA Preferences=[allInt]
Interval 3: RefPositions {#3@10} physReg:NA Preferences=[allInt]
Interval 4: (constant) RefPositions {#4@12 #5@13} physReg:NA Preferences=[allInt]
Interval 5: RefPositions {#6@14 #7@15} physReg:NA Preferences=[allInt] RelatedInterval <L2>[000001C4DFDD1E80]
Interval 6: RefPositions {#10@22 #11@23} physReg:NA Preferences=[allInt] RelatedInterval <L1>[000001C4DFDD1E28]
Interval 7: RefPositions {#14@32 #16@33} physReg:NA Preferences=[allInt]
Interval 8: RefPositions {#17@34 #18@35} physReg:NA Preferences=[allInt] RelatedInterval <L0>[000001C4DFDD1DD0]
------------
REFPOSITIONS BEFORE ALLOCATION:
------------
<RefPosition #0 @0 RefTypeZeroInit <Ivl:2 V03> IL_OFFSET BB01 regmask=[allInt] minReg=1>
<RefPosition #1 @1 RefTypeBB BB01 regmask=[] minReg=1>
<RefPosition #2 @9 RefTypeUse <Ivl:2 V03> LCL_VAR BB01 regmask=[allInt] minReg=1 last>
<RefPosition #3 @10 RefTypeDef <Ivl:3> IND BB01 regmask=[allInt] minReg=1 last local>
<RefPosition #4 @12 RefTypeDef <Ivl:4> CNS_INT BB01 regmask=[allInt] minReg=1>
<RefPosition #5 @13 RefTypeUse <Ivl:4> BB01 regmask=[allInt] minReg=1 last>
<RefPosition #6 @14 RefTypeDef <Ivl:5> IND BB01 regmask=[allInt] minReg=1>
<RefPosition #7 @15 RefTypeUse <Ivl:5> BB01 regmask=[allInt] minReg=1 last>
<RefPosition #8 @16 RefTypeDef <Ivl:2 V03> STORE_LCL_VAR BB01 regmask=[allInt] minReg=1>
<RefPosition #9 @21 RefTypeUse <Ivl:2 V03> LCL_VAR BB01 regmask=[allInt] minReg=1>
<RefPosition #10 @22 RefTypeDef <Ivl:6> IND BB01 regmask=[allInt] minReg=1>
<RefPosition #11 @23 RefTypeUse <Ivl:6> BB01 regmask=[allInt] minReg=1 last>
<RefPosition #12 @24 RefTypeDef <Ivl:1 V02> STORE_LCL_VAR BB01 regmask=[allInt] minReg=1>
<RefPosition #13 @31 RefTypeUse <Ivl:2 V03> LCL_VAR BB01 regmask=[allInt] minReg=1>
<RefPosition #14 @32 RefTypeDef <Ivl:7> IND BB01 regmask=[allInt] minReg=1>
<RefPosition #15 @33 RefTypeUse <Ivl:1 V02> LCL_VAR BB01 regmask=[allInt] minReg=1>
<RefPosition #16 @33 RefTypeUse <Ivl:7> BB01 regmask=[allInt] minReg=1 last>
<RefPosition #17 @34 RefTypeDef <Ivl:8> LT BB01 regmask=[allInt] minReg=1>
<RefPosition #18 @35 RefTypeUse <Ivl:8> BB01 regmask=[allInt] minReg=1 last>
<RefPosition #19 @36 RefTypeDef <Ivl:0 V01> STORE_LCL_VAR BB01 regmask=[allInt] minReg=1>
<RefPosition #20 @41 RefTypeUse <Ivl:0 V01> LCL_VAR BB01 regmask=[allInt] minReg=1 last regOptional>
<RefPosition #21 @45 RefTypeBB BB02 regmask=[] minReg=1>
<RefPosition #22 @55 RefTypeUse <Ivl:2 V03> LCL_VAR BB02 regmask=[allInt] minReg=1 last>
<RefPosition #23 @55 RefTypeUse <Ivl:1 V02> LCL_VAR BB02 regmask=[allInt] minReg=1 last>
<RefPosition #24 @57 RefTypeBB BB03 regmask=[] minReg=1>
VAR REFPOSITIONS BEFORE ALLOCATION
--- V00
--- V01
<RefPosition #19 @36 RefTypeDef <Ivl:0 V01> STORE_LCL_VAR BB01 regmask=[allInt] minReg=1>
<RefPosition #20 @41 RefTypeUse <Ivl:0 V01> LCL_VAR BB01 regmask=[allInt] minReg=1 last regOptional>
--- V02
<RefPosition #12 @24 RefTypeDef <Ivl:1 V02> STORE_LCL_VAR BB01 regmask=[allInt] minReg=1>
<RefPosition #15 @33 RefTypeUse <Ivl:1 V02> LCL_VAR BB01 regmask=[allInt] minReg=1>
<RefPosition #23 @55 RefTypeUse <Ivl:1 V02> LCL_VAR BB02 regmask=[allInt] minReg=1 last>
--- V03
<RefPosition #0 @0 RefTypeZeroInit <Ivl:2 V03> IL_OFFSET BB01 regmask=[allInt] minReg=1>
<RefPosition #2 @9 RefTypeUse <Ivl:2 V03> LCL_VAR BB01 regmask=[allInt] minReg=1 last>
<RefPosition #8 @16 RefTypeDef <Ivl:2 V03> STORE_LCL_VAR BB01 regmask=[allInt] minReg=1>
<RefPosition #9 @21 RefTypeUse <Ivl:2 V03> LCL_VAR BB01 regmask=[allInt] minReg=1>
<RefPosition #13 @31 RefTypeUse <Ivl:2 V03> LCL_VAR BB01 regmask=[allInt] minReg=1>
<RefPosition #22 @55 RefTypeUse <Ivl:2 V03> LCL_VAR BB02 regmask=[allInt] minReg=1 last>
Allocating Registers
--------------------
The following table has one or more rows for each RefPosition that is handled during allocation.
The first column provides the basic information about the RefPosition, with its type (e.g. Def,
Use, Fixd) followed by a '*' if it is a last use, and a 'D' if it is delayRegFree, and then the
action taken during allocation (e.g. Alloc a new register, or Keep an existing one).
The subsequent columns show the Interval occupying each register, if any, followed by 'a' if it is
active, and 'i'if it is inactive. Columns are only printed up to the last modifed register, which
may increase during allocation, in which case additional columns will appear. Registers which are
not marked modified have ---- in their column.
------------------------------+----+----+----+----+----+----+
LocRP# Name Type Action Reg |rax |rcx |rbx |rbp |rsi |rdi |
------------------------------+----+----+----+----+----+----+
| | | | | | |
0.#0 V3 Zero Alloc rax |V3 a| | | | | |
1.#1 BB1 PredBB0 |V3 a| | | | | |
9.#2 V3 Use * Keep rax |V3 i| | | | | |
10.#3 I3 Def * Alloc rax |I3 a| | | | | |
Restr rax |V3 i| | | | | |
12.#4 C4 Def Alloc rax |C4 a| | | | | |
13.#5 C4 Use * Keep rax |C4 a| | | | | |
14.#6 I5 Def Restr rax |V3 i| | | | | |
Alloc rax |I5 a| | | | | |
15.#7 I5 Use * Keep rax |I5 a| | | | | |
16.#8 V3 Def Alloc rax |V3 a| | | | | |
21.#9 V3 Use Keep rax |V3 a| | | | | |
------------------------------+----+----+----+----+----+----+----+
LocRP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |
------------------------------+----+----+----+----+----+----+----+
22.#10 I6 Def Alloc rdx |V3 a| |I6 a| | | | |
23.#11 I6 Use * Keep rdx |V3 a| |I6 a| | | | |
24.#12 V2 Def Alloc rdx |V3 a| |V2 a| | | | |
31.#13 V3 Use Keep rax |V3 a| |V2 a| | | | |
32.#14 I7 Def Alloc rcx |V3 a|I7 a|V2 a| | | | |
33.#15 V2 Use Keep rdx |V3 a|I7 a|V2 a| | | | |
33.#16 I7 Use * Keep rcx |V3 a|I7 a|V2 a| | | | |
34.#17 I8 Def Alloc rcx |V3 a|I8 a|V2 a| | | | |
35.#18 I8 Use * Keep rcx |V3 a|I8 a|V2 a| | | | |
36.#19 V1 Def Alloc rcx |V3 a|V1 a|V2 a| | | | |
41.#20 V1 Use * Keep rcx |V3 a|V1 a|V2 a| | | | |
------------------------------+----+----+----+----+----+----+----+
LocRP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |
------------------------------+----+----+----+----+----+----+----+
45.#21 BB2 PredBB1 |V3 a| |V2 a| | | | |
55.#22 V3 Use * Keep rax |V3 a| |V2 a| | | | |
55.#23 V2 Use * Keep rdx |V3 a| |V2 a| | | | |
------------------------------+----+----+----+----+----+----+----+
LocRP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |
------------------------------+----+----+----+----+----+----+----+
57.#24 BB3 PredBB1 | | | | | | | |
------------
REFPOSITIONS AFTER ALLOCATION:
------------
<RefPosition #0 @0 RefTypeZeroInit <Ivl:2 V03> IL_OFFSET BB01 regmask=[rax] minReg=1>
<RefPosition #1 @1 RefTypeBB BB01 regmask=[] minReg=1>
<RefPosition #2 @9 RefTypeUse <Ivl:2 V03> LCL_VAR BB01 regmask=[rax] minReg=1 last>
<RefPosition #3 @10 RefTypeDef <Ivl:3> IND BB01 regmask=[rax] minReg=1 last local>
<RefPosition #4 @12 RefTypeDef <Ivl:4> CNS_INT BB01 regmask=[rax] minReg=1>
<RefPosition #5 @13 RefTypeUse <Ivl:4> BB01 regmask=[rax] minReg=1 last>
<RefPosition #6 @14 RefTypeDef <Ivl:5> IND BB01 regmask=[rax] minReg=1>
<RefPosition #7 @15 RefTypeUse <Ivl:5> BB01 regmask=[rax] minReg=1 last>
<RefPosition #8 @16 RefTypeDef <Ivl:2 V03> STORE_LCL_VAR BB01 regmask=[rax] minReg=1>
<RefPosition #9 @21 RefTypeUse <Ivl:2 V03> LCL_VAR BB01 regmask=[rax] minReg=1>
<RefPosition #10 @22 RefTypeDef <Ivl:6> IND BB01 regmask=[rdx] minReg=1>
<RefPosition #11 @23 RefTypeUse <Ivl:6> BB01 regmask=[rdx] minReg=1 last>
<RefPosition #12 @24 RefTypeDef <Ivl:1 V02> STORE_LCL_VAR BB01 regmask=[rdx] minReg=1>
<RefPosition #13 @31 RefTypeUse <Ivl:2 V03> LCL_VAR BB01 regmask=[rax] minReg=1>
<RefPosition #14 @32 RefTypeDef <Ivl:7> IND BB01 regmask=[rcx] minReg=1>
<RefPosition #15 @33 RefTypeUse <Ivl:1 V02> LCL_VAR BB01 regmask=[rdx] minReg=1>
<RefPosition #16 @33 RefTypeUse <Ivl:7> BB01 regmask=[rcx] minReg=1 last>
<RefPosition #17 @34 RefTypeDef <Ivl:8> LT BB01 regmask=[rcx] minReg=1>
<RefPosition #18 @35 RefTypeUse <Ivl:8> BB01 regmask=[rcx] minReg=1 last>
<RefPosition #19 @36 RefTypeDef <Ivl:0 V01> STORE_LCL_VAR BB01 regmask=[rcx] minReg=1>
<RefPosition #20 @41 RefTypeUse <Ivl:0 V01> LCL_VAR BB01 regmask=[rcx] minReg=1 last regOptional>
<RefPosition #21 @45 RefTypeBB BB02 regmask=[] minReg=1>
<RefPosition #22 @55 RefTypeUse <Ivl:2 V03> LCL_VAR BB02 regmask=[rax] minReg=1 last>
<RefPosition #23 @55 RefTypeUse <Ivl:1 V02> LCL_VAR BB02 regmask=[rdx] minReg=1 last>
<RefPosition #24 @57 RefTypeBB BB03 regmask=[] minReg=1>
VAR REFPOSITIONS AFTER ALLOCATION
--- V00
--- V01
<RefPosition #19 @36 RefTypeDef <Ivl:0 V01> STORE_LCL_VAR BB01 regmask=[rcx] minReg=1>
<RefPosition #20 @41 RefTypeUse <Ivl:0 V01> LCL_VAR BB01 regmask=[rcx] minReg=1 last regOptional>
--- V02
<RefPosition #12 @24 RefTypeDef <Ivl:1 V02> STORE_LCL_VAR BB01 regmask=[rdx] minReg=1>
<RefPosition #15 @33 RefTypeUse <Ivl:1 V02> LCL_VAR BB01 regmask=[rdx] minReg=1>
<RefPosition #23 @55 RefTypeUse <Ivl:1 V02> LCL_VAR BB02 regmask=[rdx] minReg=1 last>
--- V03
<RefPosition #0 @0 RefTypeZeroInit <Ivl:2 V03> IL_OFFSET BB01 regmask=[rax] minReg=1>
<RefPosition #2 @9 RefTypeUse <Ivl:2 V03> LCL_VAR BB01 regmask=[rax] minReg=1 last>
<RefPosition #8 @16 RefTypeDef <Ivl:2 V03> STORE_LCL_VAR BB01 regmask=[rax] minReg=1>
<RefPosition #9 @21 RefTypeUse <Ivl:2 V03> LCL_VAR BB01 regmask=[rax] minReg=1>
<RefPosition #13 @31 RefTypeUse <Ivl:2 V03> LCL_VAR BB01 regmask=[rax] minReg=1>
<RefPosition #22 @55 RefTypeUse <Ivl:2 V03> LCL_VAR BB02 regmask=[rax] minReg=1 last>
Active intervals at end of allocation:
-----------------------
RESOLVING BB BOUNDARIES
-----------------------
Resolution Candidates: {V02 V03}
Has Critical Edges
Prior to Resolution
BB01 use def in out
{V03}
{V01 V02 V03}
{V03}
{V02 V03}
Var=Reg beg of BB01: V03=rax
Var=Reg end of BB01: V03=rax V02=rdx
BB02 use def in out
{V02 V03}
{}
{V02 V03}
{}
Var=Reg beg of BB02: V03=rax V02=rdx
Var=Reg end of BB02: none
BB03 use def in out
{}
{}
{}
{}
Var=Reg beg of BB03: none
Var=Reg end of BB03: none
RESOLVING EDGES
Trees after linear scan register allocator (LSRA)
--------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
--------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..032)-> BB03 ( cond ) i label target LIR
BB02 [0001] 1 BB01 0.50 [032..046) i LIR
BB03 [0002] 2 BB01,BB02 1 [046..047) (return) i label target LIR
--------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [000..032) -> BB03 (cond), preds={} succs={BB02,BB03}
N003 ( 29, 33) [000017] ------------ IL_OFFSET void IL offset: 0x0 REG NA
N005 ( 1, 1) [000063] ------------ t63 = LCL_VAR ref V03 cse2 rax (last use) REG rax <l:$140, c:$180>
/--* t63 ref
N007 (???,???) [000066] -c---------- t66 = * LEA(b+8) byref REG NA
/--* t66 byref
N009 ( 4, 4) [000007] ---XG------- t7 = * IND int REG rax <l:$343, c:$380>
N011 ( 3, 10) [000030] ------------ t30 = CNS_INT(h) long 0x1c4f1e92978 static Fseq[s_1] REG rax $100
/--* t30 long
N013 ( 5, 12) [000001] x---G------- t1 = * IND ref REG rax <l:$140, c:$180>
/--* t1 ref
N015 ( 5, 12) [000059] DA--G------- * STORE_LCL_VAR ref V03 cse2 rax REG rax
N017 ( 1, 1) [000060] ------------ t60 = LCL_VAR ref V03 cse2 rax REG rax <l:$140, c:$180>
/--* t60 ref
N019 (???,???) [000067] -c---------- t67 = * LEA(b+12) byref REG NA
/--* t67 byref
N021 ( 10, 17) [000002] ---XG------- t2 = * IND ushort REG rdx <l:$241, c:$280>
/--* t2 ushort
N023 ( 10, 17) [000054] DA-XG------- * STORE_LCL_VAR int V02 cse1 rdx REG rdx
N025 ( 1, 1) [000055] ------------ t55 = LCL_VAR int V02 cse1 rdx REG rdx <l:$241, c:$280>
N027 ( 1, 1) [000062] ------------ t62 = LCL_VAR ref V03 cse2 rax REG rax <l:$140, c:$180>
/--* t62 ref
N029 (???,???) [000068] -c---------- t68 = * LEA(b+14) byref REG NA
/--* t68 byref
N031 ( 5, 5) [000004] ---XG------- t4 = * IND byte REG rcx <l:$2c1, c:$300>
/--* t55 int
+--* t4 byte
N033 ( 20, 24) [000005] ---XG------- t5 = * LT int REG rcx <l:$341, c:$340>
/--* t5 int
N035 ( 20, 24) [000047] DA-XG------- * STORE_LCL_VAR int V01 cse0 rcx REG rcx
N037 ( 1, 1) [000050] ------------ t50 = LCL_VAR int V01 cse0 rcx (last use) REG rcx <l:$341, c:$340>
N039 ( 1, 1) [000014] -c---------- t14 = CNS_INT int 0 REG NA $82
/--* t50 int
+--* t14 int
N041 ( 27, 31) [000015] J--XG--N---- * EQ void REG NA <l:$347, c:$346>
N043 ( 29, 33) [000016] ---XG------- * JTRUE void REG NA
------------ BB02 [032..046), preds={BB01} succs={BB03}
N047 ( 7, 7) [000027] ------------ IL_OFFSET void IL offset: 0x32 REG NA
N049 ( 1, 1) [000064] ------------ t64 = LCL_VAR ref V03 cse2 rax (last use) REG rax <l:$140, c:$180>
/--* t64 ref
N051 (???,???) [000069] -c---------- t69 = * LEA(b+12) byref REG NA
N053 ( 1, 1) [000057] ------------ t57 = LCL_VAR int V02 cse1 rdx (last use) REG rdx <l:$241, c:$280>
/--* t69 byref
+--* t57 int
N055 (???,???) [000065] -A-XG------- * STOREIND ushort REG NA
------------ BB03 [046..047) (return), preds={BB01,BB02} succs={}
N059 ( 0, 0) [000020] ------------ IL_OFFSET void IL offset: 0x46 REG NA
N061 ( 0, 0) [000019] ------------ RETURN void REG NA $440
-------------------------------------------------------------------------------------------------------------------
Final allocation
------------------------------+----+----+----+----+----+----+----+
LocRP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |
------------------------------+----+----+----+----+----+----+----+
0.#0 V3 Zero Alloc rax |V3 a| | | | | | |
1.#1 BB1 PredBB0 |V3 a| | | | | | |
9.#2 V3 Use * Keep rax |V3 i| | | | | | |
10.#3 I3 Def * Alloc rax |I3 i| | | | | | |
12.#4 C4 Def Alloc rax |C4 a| | | | | | |
13.#5 C4 Use * Keep rax |C4 i| | | | | | |
14.#6 I5 Def Alloc rax |I5 a| | | | | | |
15.#7 I5 Use * Keep rax |I5 i| | | | | | |
16.#8 V3 Def Alloc rax |V3 a| | | | | | |
21.#9 V3 Use Keep rax |V3 a| | | | | | |
22.#10 I6 Def Alloc rdx |V3 a| |I6 a| | | | |
23.#11 I6 Use * Keep rdx |V3 a| |I6 i| | | | |
24.#12 V2 Def Alloc rdx |V3 a| |V2 a| | | | |
31.#13 V3 Use Keep rax |V3 a| |V2 a| | | | |
32.#14 I7 Def Alloc rcx |V3 a|I7 a|V2 a| | | | |
33.#15 V2 Use Keep rdx |V3 a|I7 a|V2 a| | | | |
33.#16 I7 Use * Keep rcx |V3 a|I7 i|V2 a| | | | |
34.#17 I8 Def Alloc rcx |V3 a|I8 a|V2 a| | | | |
35.#18 I8 Use * Keep rcx |V3 a|I8 i|V2 a| | | | |
36.#19 V1 Def Alloc rcx |V3 a|V1 a|V2 a| | | | |
41.#20 V1 Use * Keep rcx |V3 a|V1 i|V2 a| | | | |
------------------------------+----+----+----+----+----+----+----+
LocRP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |
------------------------------+----+----+----+----+----+----+----+
45.#21 BB2 PredBB1 |V3 a| |V2 a| | | | |
55.#22 V3 Use * Keep rax |V3 i| |V2 a| | | | |
55.#23 V2 Use * Keep rdx | | |V2 i| | | | |
------------------------------+----+----+----+----+----+----+----+
LocRP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |
------------------------------+----+----+----+----+----+----+----+
57.#24 BB3 PredBB1 | | | | | | | |
Recording the maximum number of concurrent spills:
----------
LSRA Stats
----------
Total Tracked Vars: 3
Total Reg Cand Vars: 3
Total number of Intervals: 8
Total number of RefPositions: 24
Total Spill Count: 0 Weighted: 0
Total CopyReg Count: 0 Weighted: 0
Total ResolutionMov Count: 0 Weighted: 0
Total number of split edges: 0
Total Number of spill temps created: 0
TUPLE STYLE DUMP WITH REGISTER ASSIGNMENTS
Incoming Parameters: V03(STK=>rax)
BB01 [000..032) -> BB03 (cond), preds={} succs={BB02,BB03}
=====
N003. IL_OFFSET IL offset: 0x0 REG NA
N005. V03(rax*)
N007. STK = LEA(b+8) ; rax*
* N009. rax = IND ; STK
N011. rax* = CNS_INT(h) 0x1c4f1e92978 static Fseq[s_1] REG rax
N013. rax = IND ; rax*
* N015. V03(rax); rax
N017. V03(rax)
N019. STK = LEA(b+12); rax
N021. rdx = IND ; STK
* N023. V02(rdx); rdx
N025. V02(rdx)
N027. V03(rax)
N029. STK = LEA(b+14); rax
N031. rcx = IND ; STK
N033. rcx = LT ; rdx,rcx
* N035. V01(rcx); rcx
N037. V01(rcx*)
N039. CNS_INT 0 REG NA
N041. EQ ; rcx*
N043. JTRUE
Var=Reg end of BB01: V03=rax V02=rdx
BB02 [032..046), preds={BB01} succs={BB03}
=====
Predecessor for variable locations: BB01
Var=Reg beg of BB02: V03=rax V02=rdx
N047. IL_OFFSET IL offset: 0x32 REG NA
N049. V03(rax*)
N051. STK = LEA(b+12); rax*
N053. V02(rdx*)
N055. STOREIND ; STK,rdx*
Var=Reg end of BB02: none
BB03 [046..047) (return), preds={BB01,BB02} succs={}
=====
Predecessor for variable locations: BB01
Var=Reg beg of BB03: none
N059. IL_OFFSET IL offset: 0x46 REG NA
N061. RETURN
Var=Reg end of BB03: none
*************** In genGenerateCode()
--------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
--------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..032)-> BB03 ( cond ) i label target LIR
BB02 [0001] 1 BB01 0.50 [032..046) i LIR
BB03 [0002] 2 BB01,BB02 1 [046..047) (return) i label target LIR
--------------------------------------------------------------------------------------------------------------------------------------
*************** In fgDebugCheckBBlist
Finalizing stack frame
Recording Var Locations at start of BB01
V03(rax)
Modified regs: [rax rcx rdx]
Callee-saved registers pushed: 0 []
*************** In lvaAssignFrameOffsets(FINAL_FRAME_LAYOUT)
; Final local variable assignments
;
;# V00 OutArgs [V00 ] ( 1, 1 ) lclBlk ( 0) [rsp+0x00]
; V01 cse0 [V01,T01] ( 14, 14 ) int -> rcx
; V02 cse1 [V02,T02] ( 13, 11.50) int -> rdx
; V03 cse2 [V03,T00] ( 15, 14 ) ref -> rax must-init
;
; Lcl frame size = 0
=============== Generating BB01 [000..032) -> BB03 (cond), preds={} succs={BB02,BB03} flags=0x00000000.40030020: i label target LIR
BB01 IN (1)={V03 } + ByrefExposed + GcHeap
OUT(2)={V03 V02}
Recording Var Locations at start of BB01
V03(rax)
Change life 0000000000000000 {} -> 0000000000000001 {V03}
V03 in reg rax is becoming live [------]
Live regs: 00000000 {} => 00000001 {rax}
Live regs: (unchanged) 00000001 {rax}
GC regs: (unchanged) 00000001 {rax}
Byref regs: (unchanged) 00000000 {}
L_M23186_BB01:
Label: IG02, GCvars=0000000000000000 {}, gcrefRegs=00000001 {rax}, byrefRegs=00000000 {}
Setting stack level from -572662307 to 0
Added IP mapping: 0x0000 STACK_EMPTY (G_M23186_IG02,ins#0,ofs#0) label
Generating: N003 ( 29, 33) [000017] ------------ IL_OFFSET void IL offset: 0x0 REG NA
Generating: N005 ( 1, 1) [000063] ------------ t63 = LCL_VAR ref V03 cse2 rax (last use) REG rax <l:$140, c:$180>
/--* t63 ref
Generating: N007 (???,???) [000066] -c---------- t66 = * LEA(b+8) byref REG NA
/--* t66 byref
Generating: N009 ( 4, 4) [000007] ---XG------- t7 = * IND int REG rax <l:$343, c:$380>
V03 in reg rax is becoming dead [000063]
Live regs: 00000001 {rax} => 00000000 {}
Live vars: {V03} => {}
GC regs: 00000001 {rax} => 00000000 {}
IN0001: mov eax, dword ptr [rax+8]
Generating: N011 ( 3, 10) [000030] ------------ t30 = CNS_INT(h) long 0x1c4f1e92978 static Fseq[s_1] REG rax $100
IN0002: mov rax, 0x1C4F1E92978
/--* t30 long
Generating: N013 ( 5, 12) [000001] x---G------- t1 = * IND ref REG rax <l:$140, c:$180>
IN0003: mov rax, gword ptr [rax]
GC regs: 00000000 {} => 00000001 {rax}
/--* t1 ref
Generating: N015 ( 5, 12) [000059] DA--G------- * STORE_LCL_VAR ref V03 cse2 rax REG rax
GC regs: 00000001 {rax} => 00000000 {}
V03 in reg rax is becoming live [000059]
Live regs: 00000000 {} => 00000001 {rax}
Live vars: {} => {V03}
GC regs: 00000000 {} => 00000001 {rax}
Generating: N017 ( 1, 1) [000060] ------------ t60 = LCL_VAR ref V03 cse2 rax REG rax <l:$140, c:$180>
/--* t60 ref
Generating: N019 (???,???) [000067] -c---------- t67 = * LEA(b+12) byref REG NA
/--* t67 byref
Generating: N021 ( 10, 17) [000002] ---XG------- t2 = * IND ushort REG rdx <l:$241, c:$280>
IN0004: movzx rdx, word ptr [rax+12]
/--* t2 ushort
Generating: N023 ( 10, 17) [000054] DA-XG------- * STORE_LCL_VAR int V02 cse1 rdx REG rdx
V02 in reg rdx is becoming live [000054]
Live regs: 00000001 {rax} => 00000005 {rax rdx}
Live vars: {V03} => {V02 V03}
Generating: N025 ( 1, 1) [000055] ------------ t55 = LCL_VAR int V02 cse1 rdx REG rdx <l:$241, c:$280>
Generating: N027 ( 1, 1) [000062] ------------ t62 = LCL_VAR ref V03 cse2 rax REG rax <l:$140, c:$180>
/--* t62 ref
Generating: N029 (???,???) [000068] -c---------- t68 = * LEA(b+14) byref REG NA
/--* t68 byref
Generating: N031 ( 5, 5) [000004] ---XG------- t4 = * IND byte REG rcx <l:$2c1, c:$300>
IN0005: movsx rcx, byte ptr [rax+14]
/--* t55 int
+--* t4 byte
Generating: N033 ( 20, 24) [000005] ---XG------- t5 = * LT int REG rcx <l:$341, c:$340>
IN0006: cmp edx, ecx
IN0007: setl cl
IN0008: movzx rcx, cl
/--* t5 int
Generating: N035 ( 20, 24) [000047] DA-XG------- * STORE_LCL_VAR int V01 cse0 rcx REG rcx
V01 in reg rcx is becoming live [000047]
Live regs: 00000005 {rax rdx} => 00000007 {rax rcx rdx}
Live vars: {V02 V03} => {V01 V02 V03}
Generating: N037 ( 1, 1) [000050] ------------ t50 = LCL_VAR int V01 cse0 rcx (last use) REG rcx <l:$341, c:$340>
Generating: N039 ( 1, 1) [000014] -c---------- t14 = CNS_INT int 0 REG NA $82
/--* t50 int
+--* t14 int
Generating: N041 ( 27, 31) [000015] J--XG--N---- * EQ void REG NA <l:$347, c:$346>
V01 in reg rcx is becoming dead [000050]
Live regs: 00000007 {rax rcx rdx} => 00000005 {rax rdx}
Live vars: {V01 V02 V03} => {V02 V03}
IN0009: test ecx, ecx
Generating: N043 ( 29, 33) [000016] ---XG------- * JTRUE void REG NA
IN000a: je L_M23186_BB03
=============== Generating BB02 [032..046), preds={BB01} succs={BB03} flags=0x00000000.40000020: i LIR
BB02 IN (2)={V03 V02}
OUT(0)={ }
Recording Var Locations at start of BB02
V03(rax) V02(rdx)
Liveness not changing: 0000000000000005 {V02 V03}
Live regs: 00000000 {} => 00000005 {rax rdx}
GC regs: 00000000 {} => 00000001 {rax}
Byref regs: (unchanged) 00000000 {}
L_M23186_BB02:
Added IP mapping: 0x0032 STACK_EMPTY (G_M23186_IG02,ins#10,ofs#41) label
Generating: N047 ( 7, 7) [000027] ------------ IL_OFFSET void IL offset: 0x32 REG NA
Generating: N049 ( 1, 1) [000064] ------------ t64 = LCL_VAR ref V03 cse2 rax (last use) REG rax <l:$140, c:$180>
/--* t64 ref
Generating: N051 (???,???) [000069] -c---------- t69 = * LEA(b+12) byref REG NA
Generating: N053 ( 1, 1) [000057] ------------ t57 = LCL_VAR int V02 cse1 rdx (last use) REG rdx <l:$241, c:$280>
/--* t69 byref
+--* t57 int
Generating: N055 (???,???) [000065] -A-XG------- * STOREIND ushort REG NA
V03 in reg rax is becoming dead [000064]
Live regs: 00000005 {rax rdx} => 00000004 {rdx}
Live vars: {V02 V03} => {V02}
GC regs: 00000001 {rax} => 00000000 {}
V02 in reg rdx is becoming dead [000057]
Live regs: 00000004 {rdx} => 00000000 {}
Live vars: {V02} => {}
IN000b: mov word ptr [rax+12], dx
=============== Generating BB03 [046..047) (return), preds={BB01,BB02} succs={} flags=0x00000000.40030020: i label target LIR
BB03 IN (0)={}
OUT(0)={}
Recording Var Locations at start of BB03
<none>
Liveness not changing: 0000000000000000 {}
Live regs: (unchanged) 00000000 {}
GC regs: (unchanged) 00000000 {}
Byref regs: (unchanged) 00000000 {}
L_M23186_BB03:
G_M23186_IG02: ; offs=000000H, funclet=00
Label: IG03, GCvars=0000000000000000 {}, gcrefRegs=00000000 {}, byrefRegs=00000000 {}
Added IP mapping: 0x0046 STACK_EMPTY (G_M23186_IG03,ins#0,ofs#0) label
Generating: N059 ( 0, 0) [000020] ------------ IL_OFFSET void IL offset: 0x46 REG NA
Generating: N061 ( 0, 0) [000019] ------------ RETURN void REG NA $440
Added IP mapping: EPILOG STACK_EMPTY (G_M23186_IG03,ins#0,ofs#0) label
Reserving epilog IG for block BB03
*************** After placeholder IG creation
G_M23186_IG01: ; func=00, offs=000000H, size=0000H, gcrefRegs=00000000 {} <-- Prolog IG
G_M23186_IG02: ; offs=000000H, size=002DH, gcrefRegs=00000001 {rax}, byrefRegs=00000000 {}, byref
G_M23186_IG03: ; epilog placeholder, next placeholder=<END>, BB03 [0002], epilog <-- First placeholder <-- Last placeholder
; PrevGCVars=0000000000000000 {}, PrevGCrefRegs=00000001 {rax}, PrevByrefRegs=00000000 {}
; InitGCVars=0000000000000000 {}, InitGCrefRegs=00000000 {}, InitByrefRegs=00000000 {}
Liveness not changing: 0000000000000000 {}
# compCycleEstimate = 36, compSizeEstimate = 40 Program:M0()
; Final local variable assignments
;
;# V00 OutArgs [V00 ] ( 1, 1 ) lclBlk ( 0) [rsp+0x00]
; V01 cse0 [V01,T01] ( 14, 14 ) int -> rcx
; V02 cse1 [V02,T02] ( 13, 11.50) int -> rdx
; V03 cse2 [V03,T00] ( 15, 14 ) ref -> rax must-init
;
; Lcl frame size = 0
*************** Before prolog / epilog generation
G_M23186_IG01: ; func=00, offs=000000H, size=0000H, gcrefRegs=00000000 {} <-- Prolog IG
G_M23186_IG02: ; offs=000000H, size=002DH, gcrefRegs=00000001 {rax}, byrefRegs=00000000 {}, byref
G_M23186_IG03: ; epilog placeholder, next placeholder=<END>, BB03 [0002], epilog <-- First placeholder <-- Last placeholder
; PrevGCVars=0000000000000000 {}, PrevGCrefRegs=00000001 {rax}, PrevByrefRegs=00000000 {}
; InitGCVars=0000000000000000 {}, InitGCrefRegs=00000000 {}, InitByrefRegs=00000000 {}
Recording Var Locations at start of BB01
V03(rax)
*************** In genFnProlog()
Added IP mapping to front: PROLOG STACK_EMPTY (G_M23186_IG01,ins#0,ofs#0) label
__prolog:
*************** In genEnregisterIncomingStackArgs()
IN000c: xor rax, rax
G_M23186_IG01: ; offs=000000H, funclet=00
*************** In genFnEpilog()
__epilog:
gcVarPtrSetCur=0000000000000000 {}, gcRegGCrefSetCur=00000000 {}, gcRegByrefSetCur=00000000 {}
IN000d: ret
G_M23186_IG03: ; offs=00002DH, funclet=00
0 prologs, 1 epilogs, 0 funclet prologs, 0 funclet epilogs
*************** After prolog / epilog generation
G_M23186_IG01: ; func=00, offs=000000H, size=0002H, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref, nogc <-- Prolog IG
G_M23186_IG02: ; offs=000002H, size=002DH, gcrefRegs=00000001 {rax}, byrefRegs=00000000 {}, byref
G_M23186_IG03: ; offs=00002FH, size=0001H, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref, epilog, nogc
*************** In emitJumpDistBind()
Binding: IN000a: 000000 je L_M23186_BB03
Binding L_M23186_BB03 to G_M23186_IG03
Estimate of fwd jump [E1C92A7C/010]: 0025 -> 002F = 0008
Shrinking jump [E1C92A7C/010]
Adjusted offset of block 03 from 002F to 002B
Total shrinkage = 4, min extra jump size = 4294967295
Hot code size = 0x2C bytes
Cold code size = 0x0 bytes
reserveUnwindInfo(isFunclet=FALSE, isColdCode=FALSE, unwindSize=0x4)
*************** In emitEndCodeGen()
Converting emitMaxStackDepth from bytes (0) to elements (0)
***************************************************************************
Instructions as they come out of the scheduler
G_M23186_IG01: ; func=00, offs=000000H, size=0002H, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref, nogc <-- Prolog IG
IN000c: 000000 33C0 xor rax, rax
G_M23186_IG02: ; func=00, offs=000002H, size=0029H, gcrefRegs=00000001 {rax}, byrefRegs=00000000 {}, byref, isz
New gcrReg live regs=00000001 {rax}
gcrReg +[rax]
gcrReg -[rax]
IN0001: 000002 8B4008 mov eax, dword ptr [rax+8]
IN0002: 000005 48B87829E9F1C4010000 mov rax, 0x1C4F1E92978
gcrReg +[rax]
IN0003: 00000F 488B00 mov rax, gword ptr [rax]
IN0004: 000012 0FB7500C movzx rdx, word ptr [rax+12]
IN0005: 000016 480FBE480E movsx rcx, byte ptr [rax+14]
IN0006: 00001B 3BD1 cmp edx, ecx
IN0007: 00001D 0F9CC1 setl cl
IN0008: 000020 0FB6C9 movzx rcx, cl
IN0009: 000023 85C9 test ecx, ecx
IN000a: 000025 7404 je SHORT G_M23186_IG03
IN000b: 000027 6689500C mov word ptr [rax+12], dx
G_M23186_IG03: ; func=00, offs=00002BH, size=0001H, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref, epilog, nogc
New gcrReg live regs=00000000 {}
gcrReg -[rax]
IN000d: 00002B C3 ret
Allocated method code size = 44 , actual size = 44
*************** After end code gen, before unwindEmit()
G_M23186_IG01: ; func=00, offs=000000H, size=0002H, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref, nogc <-- Prolog IG
IN000c: 000000 xor rax, rax
G_M23186_IG02: ; offs=000002H, size=0029H, gcrefRegs=00000001 {rax}, byrefRegs=00000000 {}, byref, isz
IN0001: 000002 mov eax, dword ptr [rax+8]
IN0002: 000005 mov rax, 0x1C4F1E92978
IN0003: 00000F mov rax, gword ptr [rax]
IN0004: 000012 movzx rdx, word ptr [rax+12]
IN0005: 000016 movsx rcx, byte ptr [rax+14]
IN0006: 00001B cmp edx, ecx
IN0007: 00001D setl cl
IN0008: 000020 movzx rcx, cl
IN0009: 000023 test ecx, ecx
IN000a: 000025 je SHORT G_M23186_IG03
IN000b: 000027 mov word ptr [rax+12], dx
G_M23186_IG03: ; offs=00002BH, size=0001H, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref, epilog, nogc
IN000d: 00002B ret
Unwind Info:
>> Start offset : 0x000000 (not in unwind data)
>> End offset : 0x00002c (not in unwind data)
Version : 1
Flags : 0x00
SizeOfProlog : 0x00
CountOfUnwindCodes: 0
FrameRegister : none (0)
FrameOffset : N/A (no FrameRegister) (Value=0)
UnwindCodes :
allocUnwindInfo(pHotCode=0x00007FFDF9BF26A0, pColdCode=0x0000000000000000, startOffset=0x0, endOffset=0x2c, unwindSize=0x4, pUnwindBlock=0x000001C4DFDC9DBC, funKind=0 (main function))
*************** In genIPmappingGen()
IP mapping count : 5
IL offs PROLOG : 0x00000000 ( STACK_EMPTY )
IL offs 0x0000 : 0x00000002 ( STACK_EMPTY )
IL offs 0x0032 : 0x00000027 ( STACK_EMPTY )
IL offs 0x0046 : 0x0000002B ( STACK_EMPTY )
IL offs EPILOG : 0x0000002B ( STACK_EMPTY )
*************** In genSetScopeInfo()
VarLocInfo count is 0
*************** Variable debug info
0 vars
*************** In gcInfoBlockHdrSave()
Set code length to 44.
Set ReturnKind to Scalar.
Set Outgoing stack arg area size to 0.
Defining 0 call sites:
Method code size: 44
Allocations for Program:M0() (MethodHash=c22fa56d)
count: 519, size: 62088, max = 5080
allocateMemory: 131072, nraUsed: 70080
Alloc'd bytes by kind:
kind | size | pct
---------------------+------------+--------
AssertionProp | 6460 | 10.40%
ASTNode | 9208 | 14.83%
InstDesc | 2596 | 4.18%
ImpStack | 0 | 0.00%
BasicBlock | 1432 | 2.31%
fgArgInfo | 0 | 0.00%
fgArgInfoPtrArr | 0 | 0.00%
FlowList | 96 | 0.15%
TreeStatementList | 384 | 0.62%
SiScope | 0 | 0.00%
FlatFPStateX87 | 0 | 0.00%
DominatorMemory | 128 | 0.21%
LSRA | 3204 | 5.16%
LSRA_Interval | 792 | 1.28%
LSRA_RefPosition | 1600 | 2.58%
Reachability | 16 | 0.03%
SSA | 804 | 1.29%
ValueNumber | 14148 | 22.79%
LvaTable | 2216 | 3.57%
UnwindInfo | 0 | 0.00%
hashBv | 120 | 0.19%
bitset | 152 | 0.24%
FixedBitVect | 0 | 0.00%
Generic | 1138 | 1.83%
IndirAssignMap | 0 | 0.00%
FieldSeqStore | 320 | 0.52%
ZeroOffsetFieldMap | 40 | 0.06%
ArrayInfoMap | 40 | 0.06%
MemoryPhiArg | 0 | 0.00%
CSE | 1568 | 2.53%
GC | 1376 | 2.22%
CorSig | 0 | 0.00%
Inlining | 208 | 0.34%
ArrayStack | 128 | 0.21%
DebugInfo | 200 | 0.32%
DebugOnly | 8146 | 13.12%
Codegen | 5080 | 8.18%
LoopOpt | 0 | 0.00%
LoopHoist | 0 | 0.00%
Unknown | 160 | 0.26%
RangeCheck | 0 | 0.00%
CopyProp | 328 | 0.53%
****** DONE compiling Program:M0()
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