switch_experiment.py

(venv) jamie@neon:~/nm_switch_experiment$ cat switch_experiment.py
from nmigen import *
from nmigen.build import Platform
from nmigen_boards.ecp5_5g_evn import ECP55GEVNPlatform

COUNTER_WIDTH = 4
HALF_WIDTH = int(COUNTER_WIDTH/2)
OUTPUT_WIDTH = 4

class Simple(Elaboratable):
    def __init__(self):
        self.X = Signal(COUNTER_WIDTH)
        self.output = Signal(OUTPUT_WIDTH)
        self.ports = [self.output]

    def elaborate(self, platform):
        m = Module()
        m.d.sync += [
            self.X.eq(self.X + 1),
        ]
        with m.Switch(self.X):
            for term in range(2**COUNTER_WIDTH):
                with m.Case(term):
                    m.d.comb += [
                        self.output.eq(term)
                    ]
        return m

class Messy(Elaboratable):
    def __init__(self):
        self.X = Signal(COUNTER_WIDTH)
        self.output = Signal(OUTPUT_WIDTH)
        self.ports = [self.output]

    def elaborate(self, platform):
        m = Module()
        m.d.sync += [
            self.X.eq(self.X + 1),
        ]

        for a_term in range(int(2**HALF_WIDTH)):
            for b_term in range(int(2**HALF_WIDTH)):
                with m.Switch(self.X[0:HALF_WIDTH]):
                    with m.Case(a_term):
                        with m.Switch(self.X[HALF_WIDTH:]):
                            with m.Case(b_term):
                                m.d.comb += [
                                    self.output.eq((b_term << HALF_WIDTH) | a_term)
                                ]
        return m

if __name__ == '__main__':
    for test_case in (Messy(), Simple()):
        sync = ClockDomain()
        platform = ECP55GEVNPlatform()
        m = Module()
        m.domains += sync
        m.submodules += test_case
        led = platform.request("led",0)
        m.d.comb += [
            led.eq(test_case.output),
            sync.clk.eq(platform.request("clk12"))
        ]

        platform.build(m, build_dir="build_"+test_case.__class__.__name__, do_program=False)




(venv) jamie@neon:~/nm_switch_experiment$ python switch_experiment.py
(venv) jamie@neon:~/nm_switch_experiment$ diff build_Simple/top.svf build_Messy/top.svf
(venv) jamie@neon:~/nm_switch_experiment$ diff -y build_Simple/top.rpt build_Messy/top.rpt | egrep '  +(Number|LUT4|TRELLIS_FF|TRELLIS_IO)'
   Number of wires:                 15                             Number of wires:                 15
   Number of wire bits:             27                             Number of wire bits:             27
   Number of public wires:          15                             Number of public wires:          15
   Number of public wire bits:      27                             Number of public wire bits:      27
   Number of memories:               0                             Number of memories:               0
   Number of memory bits:            0                             Number of memory bits:            0
   Number of processes:              0                             Number of processes:              0
   Number of cells:                  4                             Number of cells:                  4
     LUT4                            1                               LUT4                            1
     TRELLIS_FF                      1                               TRELLIS_FF                      1
     TRELLIS_IO                      2                               TRELLIS_IO                      2
(venv) jamie@neon:~/nm_switch_experiment$